M41T0 STMICROELECTRONICS | Alldatasheet
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Technical content
Figure 1. 8-pin SOIC Packages
Figure 4. Block Diagram
Table 2. Absolute Maximum Ratings
tions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 5. AC Testing Input/Output Waveform Table 4. Capacitance Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
Table 5. DC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). Table 6. Crystal Electrical Characteristics
- Load capacitors are integrated within the M41T0. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
The M41T0 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave ad- dress (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. Seconds Register 2. Minutes Register 3. Century/Hours Register 4. Day Register 5. Date Register 6. Month Register 7. Years Register 8. Control Register 2-Wire Bus Characteristics This bus is intended for communication between different ICs. It consists of two lines: one bi-direc- tional for data signals (SDA) and one for clock sig- nals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: – Data transfer may be initiated only when the bus is not busy. – During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy.Both data and clock lines remain High. Start data transfer.A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer.A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data valid.The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. By definition, a device that gives out a message is called “transmitter”, the receiving device that gets the message is called “receiver”. The device that controls the message is called “master”. The de- vices that are controlled by the master are called “slaves”. Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge relat- ed clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low dur- ing the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must sig- nal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition.
Table 7. AC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).
- Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
followed by the READ Mode Control Bit (R/W=1 ) . the address pointer is incremented to An+2. condition to the slave transmitter. stored in the pointer (see Figure 11., page 13). word address and each data byte (see Figure 9.). Figure 9. Slave Address Location
0100011 MSB
The M41T0 is driven by a quartz controlled oscilla- tor with a nominal frequency of 32.768kHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The M41T0 is tested to meet ± 35 ppm with nominal crystal. The eight- byte Clock Register (see Table 8., page 15) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal for- mat. Seconds, Minutes, and Hours are contained within the first three registers. Bits D6 and D7 of Clock Register 2 (Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to tog- gle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of Register 3 contain the Day (day of week). Registers 4, 5 and 6 contain the Date (day of month), Month and Years. The final register is the Control Register. Bit D7 of Register 0 contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within four seconds (typically one second). The seven clock registers may be read one byte at a time, or in a sequential block. The Control Reg- ister (Address location 7) may be accessed inde- pendently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock reg- isters will be delayed by 250ms to allow the READ to be completed before the update occurs. This will prevent a transition of data during the READ. Note: This 250ms delay affects only the clock reg- ister update and does not alter the actual clock time. Output Driver Pin The OUT pin is an output driver that reflects the contents of D7 of the Control Register. In other words, when D7 of location 7 is a '0' then the OUT pin will be driven low. Note: The OUT pin is open drain which requires an external pull-up resistor. Oscillator Stop Detection If the Oscillator Fail (OF) Bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date da- ta. This bit will be set to '1' any time the oscillator stops. The following conditions can cause the OF Bit to be set: – The first time power is applied (defaults to a '1' on power-up). – The voltage present on V CC is insufficient to support oscillation. – The ST Bit is set to '1.' – External interference or removal of the crystal. This bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF Bit to '0.' This function operates both under normal pow- er and in battery back-up. Initial Power-on Defaults Upon initial application of power to the device, the OUT Bit and OF Bit will be set to a '1,' while the ST Bit will be set to '0.' All other Register bits will ini- tially power-on in a random state.
Table 8. Register Map Note: 1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0', CB will not toggle.
0 ST 10 Seconds Seconds Seconds 00-59
1 OF 10 Minutes Minutes Minutes 00-59
2 CEB (1) CB 10 Hours Hours Century/Hours 0-1/00-23
3 XXXXX D a y D a y 0 1 - 0 7
4 X X 10 Date Date Date 01-31
7 O U T 0XXXXXX C o n t r o l
Figure 13. SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing Note: Drawing is not to scale. Table 9. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Figure 14. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline Note: Drawing is not to scale. Table 10. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
Table 11. Ordering Information Scheme please contact the ST Sales Office nearest to you.
REVISION HISTORY
Table 12. Document Revision History Information Scheme. Datasheet put in new template. 23-Jul-2004 3.0 Content corrected from M41T80 to M41T0.
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