M41ST85WMH6TR

M41ST85Y STMICROELECTRONICS | Alldatasheet

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M41ST85Y, M41ST85W SUMMARY DESCRIPTION The M41ST85Y/W Serial TIMEKEEPER ® /Con- troller SRAM is a low power 512-bit, static CMOS SRAM organized as 64 words by 8 bits. A built-in 32.768 kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 2., page 14) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of RAM provide status/con- trol of Alarm, Watchdog and Square Wave func- tions. Addresses and data are transferred serially via a two line, bi-directional I 2C interface. The built-in address register is incremented automati- cally after each WRITE or READ data byte. The M41ST85Y/W has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power fail- ure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell supply when a power fail- ure occurs. Functions available to the user include a non-vol- atile, time-of-day clock/calendar, Alarm interrupts, Watchdog Timer and programmable Square Wave output. Other features include a Power-On Reset as well as two additional debounced inputs (RSTIN1 and RSTIN2) which can also generate an output Reset (RST). The eight clock address loca- tions contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41ST85Y/W is supplied in a 28-lead SOIC SNAPHAT ® package (which integrates both crys- tal and battery in a single SNAPHAT top) or a 28- pin, 300mil SOIC package (MX) which includes an embedded 32kHz crystal. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct con- nection to a separate SNAPHAT housing contain- ing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the bat- tery/crystal package (e.g., SNAPHAT) part num- ber is “M4TXX-BR12SH” (see Table 19., page 32). Caution: Do not place the SNAPHAT battery/crys- tal top in conductive foam, as this will drain the lith- ium button-cell battery. The 300mil, embedded crystal SOIC requires only a user-supplied battery to provide non-volatile op- eration.

Figure 6. Block Diagram

1. Integrated into SOIC package for MX package option.

44 BYTES

Figure 7. Hardware Hookup Note: 1. Required for embedded crystal (MX) package only.

M41ST85Y, M41ST85W OPERATING MODES The M41ST85Y/W clock operates as a slave de- vice on the serial bus. Access is obtained by im- plementing a start condition followed by the correct slave address (D0h). The 64 bytes con- tained in the device can then be accessed sequen- tially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Century/Hours Register 5. Day Register 6. Date Register 7. Month Register 8. Year Register 9. Control Register 10. Watchdog Register 11 - 16. Alarm Registers 17 - 19. Reserved 20. Square Wave Register 21 - 64. User RAM The M41ST85Y/W clock continually monitors V CC for an out-of-tolerance condition. Should VCC fall below VPFD , the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When V CC falls below VSO , the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and V CC rises above VSO , the battery is disconnected, and the power supply is switched to external VCC . Write protection continues until VCC reaches VPFD (min) plus trec (min). For more information on Battery Storage Life refer to Application Note AN1012. 2-Wire Bus Characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi-direction- al data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: – Data transfer may be initiated only when the bus is not busy. – During data transfer, the data line must remain stable whenever the clock line is High. – Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy.Both data and clock lines remain High. Start data transfer.A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer.A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid.The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The de- vices that are controlled by the master are called “slaves.” Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. A slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low dur- ing the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.

mitter becomes the master receiver. dress pointer is incremented to An+2. increments to a non-clock or RAM address. Figure 11. Slave Address Location Figure 12. READ Mode Sequence

0100011 MSB

M41ST85Y, M41ST85W Data Retention Mode With valid VCC applied, the M41ST85Y/W can be accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the M41ST85Y/W will automatically deselect, write protecting itself (and any external SRAM) when V CC falls between V PFD (max) and VPFD (min). This is accomplished by internally in- hibiting access to the clock registers. At this time, the Reset pin (RST ) is driven active and will re- main active until VCC returns to nominal levels. Ex- ternal RAM access is inhibited in a similar manner by forcing E CON to a high level. This level is within 0.2 volts of the VBAT . ECON will remain at this level as long as VCC remains at an out-of-tolerance con- dition. When VCC falls below the Battery Back-up Switchover Voltage (VSO ), power input is switched from the VCC pin to the SNAPHAT® battery, and the clock registers and external SRAM are main- tained from the attached battery supply. All outputs become high impedance. The V OUT pin is capable of supplying 100 µA of current to the at- tached memory with less than 0.3 volts drop under this condition. On power up, when V CC returns to a nominal value, write protection continues for trec by inhibiting ECON . The RST signal also remains active during this time (see Figure 22., page 27). Note: Most low power SRAMs on the market to- day can be used with the M41ST85Y/W RTC SU- PERVISOR. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all oth- er inputs to the SRAM. This allows inputs to the M41ST85Y/W and SRAMs to be “Don’t Care” once V CC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC =2.0 volts. The chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to V OUT . If data retention lifetime is a critical parameter for the system, it is important to review the data reten- tion current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a typical condition for room tem- perature along with a worst case condition (gener- ally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the I BAT value of the M41ST85Y/W to determine the total current re- quirements for data retention. The available bat- tery capacity for the SNAPHAT ® of your choice can then be divided by this current to determine the amount of data retention available (see Table 19., page 32). For a further more detailed review of lifetime calcu- lations, please see Application Note AN1012.

M41ST85Y, M41ST85W CLOCK OPERATION The eight byte clock register (see Table 2., page 14) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Sec- onds, Seconds, Minutes, and Hours are contained within the first four registers. Note: A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to “00,” and Tenths/Hundredths of Seconds cannot be written to any value other than “00.” Bits D6 and D7 of Clock Register 03h (Century/ Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (de- pending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Control Register (this is described in the Clock Calibration section). Bit D7 of Register 01h con- tains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expect- ed to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce cur- rent drain. When reset to a '0' the oscillator restarts within one second. The eight Clock Registers may be read one byte at a time, or in a sequential block. The Control Reg- ister (Address location 08h) may be accessed in- dependently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock ad- dress is being read, an update of the clock regis- ters will be halted. This will prevent a transition of data during the READ. Power-down Time-Stamp When a power failure occurs, the Halt Update Bit (HT) will automatically be set to a '1.' This will pre- vent the clock from updating the TIMEKEEPER registers, and will allow the user to read the exact time of the power-down event. Resetting the HT Bit to a '0' will allow the clock to update the TIME- KEEPER registers with the current time. For more information, see Application Note AN1572. TIMEKEEPER ® Registers The M41ST85Y/W offers 20 internal registers which contain Clock, Alarm, Watchdog, Flag, Square Wave and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT ™ TIMEKEEPER cells). The external copies are independent of internal func- tions except that they are updated periodically by the simultaneous transfer of the incremented inter- nal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume ei- ther due to a Stop Condition or when the pointer increments to a non-clock or RAM address. TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Square Wave Reg- isters store data in Binary Format.

Table 2. TIMEKEEPER® Register Map

M41ST85Y, M41ST85W Calibrating the Clock The M41ST85Y/W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/–35 ppm (parts per million) oscillator frequency error at oC, which equates to about +/–1.53 minutes per month. When the Calibration circuit is properly em- ployed, accuracy improves to better than ±2 ppm at 25°C. The oscillation rate of crystals changes with tem- perature (see Figure 15., page 16). Therefore, the M41ST85Y/W design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in Figure 16., page 16. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower order bits (D4-D0) in the Control Register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indi- cates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibra- tion step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41ST85Y/W may re- quire. The first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934, “TIMEKEEP- ER ® CALIBRATION.” This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final prod- uct is packaged in a non-user serviceable enclo- sure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manu- facturing environment, and involves the use of the IRQ /FT/OUT pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the Fre- quency Test Bit (FT, D6 of 08h) is '1,' the Alarm Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the Watchdog Steering Bit (WDS, D7 of 09h) is '1' or the Watchdog Register (09h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm oscilla-

tor frequency error, requiring a –10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequen- cy. The IRQ /FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500 to10k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-down.

battery back-up to serve as a system wake-up call. user of an incorrect alarm setting. the Alarm Date Register and to RPT5–RPT1. illustrates the back-up mode alarm timing. Figure 17. Alarm Interrupt Reset Waveform Table 3. Alarm Repeat Modes

11111 O n c e p e r S e c o n d

11110 O n c e p e r M i n u t e

11100 O n c e p e r H o u r

11000 O n c e p e r D a y

10000 O n c e p e r M o n t h

00000 O n c e p e r Y e a r

Figure 18. Back-Up Mode Alarm Waveform time-out into the Watchdog Register, address 09h. rupt or a microprocessor reset. restarting the count-down cycle. and the frequency test function is denied.

Table 4. Square Wave Output Frequency

0000 N o n e –

11008 H z

11014 H z

11102 H z

11111 H z

The M41ST85Y/W continuously monitors VCC . power-up for trec after VCC passes VPFD (max). Figure 19. RSTIN1 & RSTIN2 Timing Waveforms Table 5. Reset AC Characteristics

1. Pulse width less than 50ns will result in no RESET (for noise immunity).
2. Pulse width less than 20ms will result in no RESET (for noise immunity).
3. Programmable (see Table 6., page 22).

M41ST85Y, M41ST85W Power-fail INPUT/OUTPUT The Power-Fail Input (PFI) is compared to an in- ternal reference voltage (1.25V). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a fail- ing power supply. Typically PFI is connected through an external voltage divider (see Figure 7., page 7) to either the unregulated DC input (if it is available) or the regulated output of the VCC reg- ulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several millisec- onds before the regulated VCC input to the M41ST85Y/W or the microprocessor drops below the minimum operating voltage. During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low. This oc- curs after VCC drops below VPFD (min). When pow- er returns, PFO is forced high, irrespective of VPFI for the write protect time (trec), which is the time from VPFD (max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. Century Bit Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to tog- gle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Output Driver Pin When the FT Bit, AFE Bit and watchdog register are not set, the IRQ /FT/OUT pin becomes an out- put driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location 08h are a '0,' then the IRQ /FT/OUT pin will be driven low. Note: The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor. Battery Low Warning The M41ST85Y/W automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. However, data is not com- promised due to the fact that a nominal V CC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while V CC is applied to the de- vice. Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. The M41ST85Y/W only monitors the battery when a nominal V CC is applied to the device. Thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.

Table 6. t Table 7. Default Values Note: 1. WDS, BMB0-BMB4, RB0, RB1.

1. State of other control bits undefined.

1 X 50 2000 µs

Table 8. Absolute Maximum Ratings 245°C for greater than 30 seconds).

1. For SOH28 package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C

for between 90 to 150 seconds).

1. The SOX28 package has Lead-free (Pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240°C

(use same reflow profile as standard (SnPb) lead finish). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

tions when using the quoted parameters. Table 9. DC and AC Measurement Conditions Note: Output High Z is defined as the point where data is no longer driven. Figure 20. AC Testing Input/Output Waveforms Table 10. Capacitance Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.

Table 11. DC Characteristics

1. Measured with VOUT and ECON open.
2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
3. External SRAM must match RTC SUPERVISOR chip VCC specification.
4. For PFO and SQW pins (CMOS).
5. Conditioned output (ECON ) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will re-
6. For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than VCC , this supply must be equal to, or less than 3.0V when

VCC = 0V (during battery back-up mode).

1. For rechargeable back-up, VBAT (max) may be considered VCC .

Figure 21. Bus Timing Requirements Sequence Table 12. AC Characteristics

1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.

Figure 22. Power Down/Up Mode AC Waveforms Table 13. Power Down/Up AC Characteristics

1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until

200µs after VCC passes VPFD (min).

1. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
2. Programmable (see Table 6., page 22)

Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline Note: Drawing is not to scale. Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data

Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data

Figure 25. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data

Figure 26. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline Note: Drawing is not to scale. Table 17. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mech. Data

Table 18. Ordering Information Scheme number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form (see 19).

1. The SOX28 package includes an embedded 32,768Hz crystal.

Table 19. SNAPHAT Battery Table

M41ST85Y, M41ST85W

REVISION HISTORY

Table 20. Document Revision History 06-Sep-01 3.3 DC Characteristics VBAT changed; VOHB changed; PFI Hysteresis (PFI Rising) spec.

M41ST85Y, M41ST85W Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America