M41ST84W

M41ST84Y STMICROELECTRONICS | Alldatasheet

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configured in binary coded decimal (BCD) format. cally after each WRITE or READ data byte. completion of the surface mount process. keyed to prevent reverse insertion. ber is “M4TXX-BR12SH” (see Table 20, page 29). Figure 3. Logic Diagram Note: 1. For SO16 package only. Table 1. Signal Names Note: 1. For SO16 package only.

Figure 4. 16-pin SOIC Connections Figure 5. 28-pin SOIC Connections Figure 6. Block Diagram

44 BYTES

Figure 7. Hardware Hookup Table 2. Absolute Maximum Ratings CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

tions when using the quoted parameters. Table 3. DC and AC Measurement Conditions Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 8. AC Testing Input/Output Waveforms Table 4. Capacitance Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.

Table 5. DC Characteristics

1. RSTIN internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
2. For PFO and SQW pins (CMOS).
3. For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than VCC , this supply must be equal to, or less than 3.0V when

VCC = 0V (during battery back-up mode).

1. For rechargeable back-up, VBAT (max) may be considered VCC .

Table 6. Crystal Electrical Characteristics (Externally Supplied) trace lengths and isolation from RF generating signals should be taken into account.

1. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:

tp://www.kdsj.co.jp for further information on this crystal type.

M41ST84Y, M41ST84W OPERATING MODES The M41ST84Y/W clock operates as a slave de- vice on the serial bus. Access is obtained by im- plementing a start condition followed by the correct slave address (D0h). The 64 bytes con- tained in the device can then be accessed sequen- tially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Century/Hours Register 5. Day Register 6. Date Register 7. Month Register 8. Year Register 9. Control Register 10. Watchdog Register 11 - 16. Alarm Registers 17 - 19. Reserved 20. Square Wave Register 21 - 64. User RAM The M41ST84Y/W clock continually monitors V CC for an out-of tolerance condition. Should VCC fall below VPFD , the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When V CC falls below VSO , the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and V CC rises above VSO , the battery is disconnected, and the power supply is switched to external VCC . Write protection continues until VCC reaches VPFD (min) plus tREC (min). For more information on Battery Storage Life refer to Application Note AN1012. 2-Wire Bus Characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi-direction- al data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: – Data transfer may be initiated only when the bus is not busy. – During data transfer, the data line must remain stable whenever the clock line is High. – Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy.Both data and clock lines remain High. Start data transfer.A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer.A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid.The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. By definition a device that gives out a message is called “transmitter”, the receiving device that gets the message is called “receiver”. The device that controls the message is called “master”. The de- vices that are controlled by the master are called “slaves”. Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. A slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low dur- ing the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.

Table 7. AC Characteristics

1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.

increments to a non-clock or RAM address. one stored in the pointer (see Figure 14, page 13). Figure 12. Slave Address Location Figure 13. READ Mode Sequence

0100011 MSB

lations, please see Application Note AN1012. Figure 16. Power Down/Up Mode AC Waveforms Table 8. Power Down/Up AC Characteristics

1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
3. Programmable (see Table 13, page 23)
4. At 25°C (when using SOH28 + M4T28-BR12SH SNAPHAT top); VCC = 0V.

M41ST84Y, M41ST84W CLOCK OPERATION The eight byte clock register (see Table 9, page 16) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Note: A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to “00,” and Tenths/Hundredths of Seconds cannot be written to any value other than “00.” Bits D6 and D7 of Clock Register 03h (Century/ Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (de- pending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Control Register (this is described in the Clock Calibration section). Bit D7 of Register 01h con- tains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expect- ed to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce cur- rent drain. When reset to a '0' the oscillator restarts within one second. The eight clock registers may be read one byte at a time, or in a sequential block. The Control Reg- ister (Address location 08h) may be accessed in- dependently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock ad- dress is being read, an update of the clock regis- ters will be halted. This will prevent a transition of data during the READ. Note: When a power failure occurs, the Halt Up- date Bit (HT) will automatically be set to a '1.' This will prevent the clock from updating the TIME- KEEPER ® registers, and will allow the user to read the exact time of the power-down event. Resetting the HT Bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time. TIMEKEEPER ® Registers The M41ST84Y/W offers 12 additional internal registers which contain the Alarm, Watchdog, Flag, Square Wave and Control data. These reg- isters are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT ™ TIMEKEEPER cells). The external copies are independent of in- ternal functions except that they are updated peri- odically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume ei- ther due to a Stop Condition or when the pointer increments to a non-clock or RAM address. TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Square Wave Reg- isters store data in Binary Format.

Table 9. TIMEKEEPER® Register Map

M41ST84Y, M41ST84W Calibrating the Clock The M41ST84Y/W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/–35 PPM (parts per million) oscillator frequency error at oC, which equates to about +/–1.53 minutes per month. When the Calibration circuit is properly em- ployed, accuracy improves to better than +1/–2 PPM at 25°C. The oscillation rate of crystals changes with tem- perature (see Figure 20, page 24). Therefore, the M41ST84Y/W design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in Figure 21, page 24. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value load- ed into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, sub- tracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indi- cates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 PPM of adjustment per calibra- tion step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41ST84Y/W may re- quire. The first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that ac- cesses the Calibration byte. The second approach is better suited to a manu- facturing environment, and involves the use of the IRQ /FT/OUT pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the Fre- quency Test Bit (FT, D6 of 08h) is '1,' the Alarm Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the Watchdog Steering Bit (WDS, D7 of 09h) is '1' or the Watchdog Register (09h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of

512.010124 Hz would indicate a +20 PPM oscilla-

tor frequency error, requiring a –10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequen- cy. The IRQ /FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500 to 10k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-down.

battery back-up to serve as a system wake-up call. the user of an incorrect alarm setting. illustrates the back-up mode alarm timing. Figure 17. Alarm Interrupt Reset Waveform Table 10. Alarm Repeat Modes

11111 O n c e p e r S e c o n d

11110 O n c e p e r M i n u t e

11100 O nce per Hour

11000 O nce per Day

10000 O n c e p e r M o n t h

00000 O n c e p e r Y e a r

Figure 18. Back-Up Mode Alarm Waveform time-out into the Watchdog Register, address 09h. Watchdog Register = 3*1, or 3 seconds). rupt or a microprocessor reset. restarting the count-down cycle. vails and the Frequency Test function is denied.

Table 11. Square Wave Output Frequency

0000 N o n e –

11008 H z

11014 H z

11102 H z

11111 H z

M41ST84Y, M41ST84W Power-fail INPUT/OUTPUT The Power-Fail Input (PFI) is compared to an in- ternal reference voltage (1.25V). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an under-voltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 7, page 6) to either the unregulated DC input (if it is available) or the regulated output of the V CC regu- lator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several millisec- onds before the regulated VCC input to the M41ST84Y/W or the microprocessor drops below the minimum operating voltage. During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low. This oc- curs after VCC drops below VPFD (min). When pow- er returns, PFO is forced high, irrespective of VPFI for the write protect time (tREC ), which is the time from VPFD (max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. Century Bit Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a “1” will cause CB to tog- gle, either from a “0” to “1” or from “1” to “0” at the turn of the century (depending upon its initial state). If CEB is set to a “0”, CB will not toggle. Output Driver Pin When the FT Bit, AFE Bit and watchdog register are not set, the IRQ /FT/OUT pin becomes an out- put driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location 08h are a '0,' then the IRQ /FT/OUT pin will be driven low. Note: The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor. Battery Low Warning The M41ST84Y/W automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. However, data is not com- promised due to the fact that a nominal V CC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while V CC is applied to the de- vice. Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. The M41ST84Y/W only monitors the battery when a nominal V CC is applied to the device. Thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. t REC Bit Bit D7 of Clock Register 04h contains the tREC Bit (TR). tREC refers to the automatic continuation of the deselect time after VCC reaches VPFD . This al- lows for a voltage setting time before WRITEs may again be performed to the device after a power- down condition. The t REC Bit will allow the user to set the length of this deselect time as defined by Table 13, page 23. Initial Power-on Defaults Upon initial application of power to the device, the following register bits are set to a '0' state: Watch- dog Register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state: ST, OUT, and HT (see Table 14, page 23).

Table 13. tREC Definitions Table 14. Default Values Note: 1. WDS, BMB0-BMB4, RB0, RB1.

1. State of other control bits undefined.

1 X 50 2000 µs

Figure 22. SO16 – 16-lead Plastic Small Outline, Package Outline Note: Drawing is not to scale. Table 15. SO16 – 16-lead Plastic Small Outline, Package Mechanical Data

Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline Note: Drawing is not to scale. Table 16. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data

Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data

Figure 25. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data

Table 19. Ordering Information Scheme number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.

1. Contact Local Sales Office

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery. please contact the ST Sales Office nearest to you. Table 20. SNAPHAT Battery Table

M41ST84Y, M41ST84W

REVISION HISTORY

Table 21. Document Revision History

M41ST84Y, M41ST84W M41ST84, M41ST84Y, M41ST84W, 41ST84, ST84, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SU- PERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVI- SOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, 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Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Com- parator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Com- parator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SO- IC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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