M4182RM6E

M41T82_08 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 58

Technical content

Datasheet sections

• 1 Description
• 2 Operation
• 2.1.1 Bus not busy
• 2.1.2 Start data transfer
• 2.1.3 Stop data transfer
• 2.1.4 Data valid
• 2.1.5 Acknowledge
• 2.2 Read mode
• 2.3 Write mode
• 2.4 Data retention and battery switchover (V SO = VRST)
• 2.5 Power-on reset (t rec)
• 3 Clock operation
• 3.1 Power-down time-stamp
• 3.2 Clock/control register map
• 3.3 Real-time clock accuracy
• 3.4 Clock calibration
• 3.4.1 Digital calibration (periodic counter correction)
• 3.4.2 Analog calibration (programmable load capacitance)
• 3.5 Setting the alarm clock registers
• 3.6 Optional second programmable alarm
• 3.7 Watchdog timer
• 3.8.1 Timer interrupt/timer pulse (TI /TP , M41T83 only)
• 3.8.2 Timer flag (TF)
• 3.8.3 Timer interrupt enable (TIE, M41T83 only)
• 3.8.4 Timer enable (TE)
• 3.8.5 TD1/0
• 3.9 Square wave output (M41T83 only)
• 3.10 Battery low warning
• 3.11 Century bits

Features

■ Ultra-low battery supply current of 365 nA ■ Factory calibrated accuracy ±5 PPM guaranteed after 2 reflows (SOX18) – Much better accuracies achievable using built-in programmable analog and digital calibration circuits ■ 2.0 V to 5.5 V clock operating voltage ■ Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century ■ Automatic switchover and reset output circuitry (fixed reference) –M 4 1 T 8 3 S V CC = 3.00 V to 5.50 V (2.85 V ≤ VRST ≤ 3.00 V) –M 4 1 T 8 3 R VCC = 2.70 V to 5.50 V (2.55 V ≤ VRST ≤ 2.70 V) –M 4 1 T 8 3 Z VCC = 2.38 V to 5.50 V (2.25 V ≤ VRST ≤ 2.38 V) ■ Serial interface supports I2C Bus (400 kHz protocol) ■ Programmable alarm with interrupt function (valid even during battery back-up mode) ■ Optional 2nd programmable alarm available ■ Square wave output defaults to 32 KHz on power-up (M41T83 only) ■ RESET (RST) output ■ Watchdog timer ■ Programmable 8-bit counter/timer ■ 7 bytes of battery-backed user SRAM ■ Battery low flag ■ Power-down time stamp (HT bit) ■ Low operating current of 80 µA ■ Oscillator stop detection ■ Battery or Super-cap™ back-up ■ Operating temperature of –40°C to 85°C ■ Package options include: – a 16-lead QFN (M41T83), – an 18-lead embedded crystal SOIC (M41T83), or – an 8-lead SOIC (M41T82) ■ RoHS compliance: lead-free components are compliant with the RoHS directive SOX18 (MY , 18-pin, 300 mil SOIC QFN16, 4 mm x 4 mm (QA) SO8 (M) with embedded crystal) (VFQFPN16)

1 Description

The M41T8x are low power serial I2C real-time clocks with a built-in 32.768 kHz oscillator (external crystal-controlled for the QFN16 and SO8 packages, embedded crystal for the SOX18 package). Eight bytes of the Register Map (see Table 2 on page 23) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the Register Map provide status/control of the two Alarms, Watchdog, 8-bit Counter, and Square Wave functions. An additional seven bytes are made available as user SRAM. Addresses and data are transferred serially via a two line, bi-directional I 2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T8x has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button battery when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, two Alarm interrupts, Watchdog Timer, programmable 8-bit Counter, and Square Wave outputs. The eight clock address locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. The M41T83 is supplied in either a QFN16 (QA) or an SOX18 (MY), 300mil SOIC which includes an embedded 32 KHz crystal. The SOX18 package requires only a user-supplied battery to provide non-volatile operation. The M41T82 is available only in an SO8 package.

1. For SO8 and QFN16 packages only.
2. Defaults to 32 KHz on power-up.
3. For SOX18 and QFN16 packages only.
4. DU pin must be tied to V CC.

Table 1. Signal names

Figure 6. M41T82 block diagram

Figure 7. M41T82 hardware hookup

Figure 8. M41T83 block diagram

8 BITS OF OTP

Figure 9. M41T83 hardware hookup

2 Operation

The M41T8x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 32 bytes contained in the device can then be accessed sequentially in the following order:

• 1st byte: tenths/hundredths of a second register
• 2nd byte: seconds register
• 3rd byte: minutes register
• 4th byte: century/hours register
• 5th byte: day register
• 6th byte: date register
• 7th byte: month register
• 8th byte: year register
• 9th byte: digital calibration register
• 10th byte: watchdog register
• 11th - 15th bytes: alarm 1 registers
• 16th byte: flags register
• 17th byte: timer value register
• 18th byte: timer control register
• 19th byte: analog calibration register
• 20th byte: square wave register
• 21st - 25th bytes: alarm 2 registers
• 26th - 32nd bytes: user RAM The M41T8x clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VRST, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. The power input will also be switched from the VCC pin to the battery when VCC falls below the battery back-up switchover voltage (VSO = VRST). At this time the clock registers will be maintained by the attached battery supply. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC.

2.1 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi- directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is High.
• Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined:

2.1.1 Bus not busy

Both data and clock lines remain High.

2.1.2 Start data transfer

A change in the state of the data line, from high to Low, while the clock is High, defines the START condition.

2.1.3 Stop data transfer

A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.

2.1.4 Data valid

The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Figure 10. Serial bus data transfer sequence Figure 11. Acknowledgement sequence

2.2 Read mode

Note: This is true both in READ Mode and WRITE Mode. last one stored in the pointer (see Figure 14 on page 18). Figure 12. Slave address location

0100011 MSB

2.3 Write mode

Figure 15. Write mode sequence

2.4 Data retention and battery switchover (V SO = VRST)

Once VCC falls below the switchover voltage (VSO = VRST), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life. If VBAT is less than, or greater than VRST, the device power is switched from VCC to VBAT when VCC drops below VRST (see Figure 25 on page 48). At this time the clock registers and user RAM will be maintained by the attached battery supply. When it is powered back up, the device switches back from battery to VCC at VSO + hysteresis. When VCC rises above VRST, it will recognize the inputs. For more information on battery storage life refer to Application Note AN1012.

2.5 Power-on reset (t rec)

The M41T8x continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST output pulls low (open drain) and remains low after power-up for trec (210 ms typical) after VCC rises above VRST (max). Note: The t rec period does not affect the RTC operation. Write protect only occurs when VCC is below VRST. When VCC rises above VRST, the RTC will be selectable immediately. Only the RST output is affected by the trec period. The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time.

M41T82 M41T83 Clock operation

3 Clock operation

The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see Table 2 on page 23 and Table 4 on page 25) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical). Note: Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST bit to '0.' This provides an additional “kick-start” to the oscillator circuit. Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0 (CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in the clock calibration section). For the M41T83, bit D7 of register 09h (Watchdog register) contains the Oscillator Fail Interrupt Enable bit (OFIE). When the user sets this bit to '1,' any condition which sets the Oscillator Fail bit (OF) (see Section 3.13: Oscillator fail detection on page 42) will also generate an interrupt output. Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the ST bit and CB0-CB1 bits will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight clock registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.

3.1 Power-down time-stamp

When a power failure occurs, the Halt Update bit (HT) will automatically be set to a “1”. This will prevent the clock from updating the clock registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a “0” will allow the clock to update the clock with the current time. For more information, see Application note AN1572.

Clock operation M41T82 M41T83

3.2 Clock/control register map

The M41T8x offers 32 internal registers which contain clock, calibration (digital and analog), Alarm 1 and 2, Watchdog, Flags, Timer, and Square Wave (M41T83 only). The clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT™ TIMEKEEPER ® cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address (00h to 07h). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock address. Clock and alarm registers store data in BCD format. Calibration, Timer, Watchdog, and Square Wave bits are written in a binary format.

Table 2. M41T82 clock/control register map (32 bytes) (1)

1. See Table 3: Key to Table 2: M41T82 clock/control register map (32 bytes)
2. AF2 will always read ‘0’, if the AL2E bit is set to ‘0’.

Table 3. Key to Table 2: M41T82 clock/control register map (32 bytes)

0 Must be set to zero

Table 4. M41T83 clock/control register map (32 bytes) (1)

1. See Table 5: Key to Table 4: M41T83 clock/control register map (32 bytes).
2. AF2 will always read ‘0’, if the AL2E bit is set to ‘0’.

Table 5. Key to Table 4: M41T83 clock/control register map (32 bytes)

3.3 Real-time clock accuracy

causing additional error (see Figure 17 on page 31).

1. An Analog Calibration register (12h) can be used to adjust internal (on-chip) load

Section 3.4.2: Analog calibration (programmable load capacitance) on page 30).

1. A Digital Calibration register (08h) can also be used to adjust the clock counter by

Digital calibration (periodic counter correction) on page 28). Figure 16. Internal load capacitance adjustment

Clock operation M41T82 M41T83

3.4 Clock calibration

The M41T8x oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at 25°C. The M41T8x design provides the following two methods for clock error correction.

3.4.1 Digital calibration (p eriodic counter correction)

This method employs the use of periodic counter correction by adjusting the ratio of the 100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100 Hz divider stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide the input frequency to the Fraction of Seconds Clock register. By adjusting the number of 512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed down, as shown in Figure 19 on page 34. When a non-zero value is loaded into the five Calibration bits (DC4 – DC0) found in the Digital Calibration Register (08h) and the sign bit is ‘1’, (indicating positive calibration), the 100Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. Since the 100 pulses are now being output in a shorter window, this has the effect of speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when the sign bit is ‘0’, indicating negative calibration, the block outputs 100 pulses for every 513 input pulses. Since the 100 pulses are then being output in a longer window, this has the effect of slowing down the clock by 1/512 seconds for each second the circuit is active. The amount of calibration is controlled by using the value in the calibration register (N) to generate the adjustment in one second increments. This is done for the first N seconds once every eight minutes for positive calibration, and for N seconds once every sixteen minutes for negative calibration (see Table 6 on page 29). For example, if the Calibration register is set to '100010,' then the adjustment will occur for two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the adjustment will occur for 3 seconds in every alternating minute. The Digital Calibration bits (DC4 – DC0) occupy the five lower order bits in the Digital Calibration Register (08h). These bits can be set to represent any value between 0 and 31 in binary form. The sixth bit (DCS) is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative) cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or –2.034 ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35 seconds per month, which corresponds to a total range of +5.5 or –2.75 minutes per month. Note: 1 The modified pulses are not observable on the Frequency Test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation.

2 Positive digital calibration is performed on an eight minute cycle, therefore the value in the

calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. Negative digital calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes.

Table 6. Digital calibration values

Clock operation M41T82 M41T83

3.4.2 Analog calibration (p rogrammable load capacitance)

A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. By design, the oscillator is intended to be 0 ppm ± crystal accuracy at room temperature (25°C, see Figure 17 on page 31). For a 12.5 pF crystal, the default loading on each side of the crystal will be 25 pF . For incrementing or decrementing the calibration value, capacitance will be added or removed in increments of 0.25 pF to each side of the crystal. Internally, CLOAD of the oscillator is changed via two digitally controlled capacitors, CXI and CXO, connected from the XI and XO pins to ground (see Figure 16 on page 27). The effective on-chip series load capacitance, CLOAD, ranges from 3.5 pF to 17.4 pF , with a nominal value of 12.5 pF (AC0-AC6 = ‘0’). The effective series load capacitance (CLOAD) is the combination of CXI and CXO: Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. An Analog Calibration Sign (ACS) bit determines if capacitance is added (ACS bit = ‘0’, negative calibration) or removed (ACS bit = ‘1’, positive calibration). The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency by removing capacitance) due to the typical characteristic of quartz crystals to slow down due to changes in temperature, but negative calibration is also available. Since the Analog Calibration Register adjustment is essentially “pulling” the frequency of the oscillator, the resulting frequency changes will not be linear with incremental capacitance changes. The equations which govern this mechanism indicate that smaller capacitor values of Analog Calibration adjustment will provide larger increments. Thus, the larger values of Analog Calibration adjustment will produce smaller incremental frequency changes. These values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest capacitance settings. The range provided by the Analog Calibration Register adjustment with a typical surface mount crystal is approximately ±30 ppm around the AC6-AC0 = 0 default setting because of this property (see T a b l e7 o n p a g e3 1). C LOAD 11 C XI⁄ 1C XO⁄+()⁄=

Figure 17. Crystal accuracy across temperature Table 7. Analog calibration values

1. Maximum negative calibration value
2. Maximum positive calibration value

Clock operation M41T82 M41T83 The on-chip capacitance can be calculated as follows: For example:

• CLOAD (12h = x0000000) = 12.5 pF ,
• CLOAD (12h =11001000) = 3.5 pF , and
• CLOAD (12h = 00100111) = 17.4 pF . The oscillator sees a minimum of 3.5 pF with no programmable load capacitance selected. Note: These are typical values, and the total lo ad capacitance seen by the crystal will include approximately 1-2 pF of package and board capacitance in addition to the Analog Calibration register value. Any invalid value of Analog Calibration will result in the default capacitance of 25 pF . The combination of analog and digital trimming can give up to –93 to +156 ppm of the total adjustment. Figure 18 on page 33 represents a typical curve of clock ppm adjustment versus the Analog Calibration value. This curve may vary with different crystals, so it is good practice to evaluate the crystal to be used with an M41T8x device before establishing the adjustment values for the application in question. CLOAD 2--- AC6 AC0 value– decimal,() 0.25pF×[] 25pF+=

Figure 18. Clock accuracy vs. on-chip load capacitance

• The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses either or both of the Calibration bytes.
• The second approach is better suited to a manufacturing environment, and involves the use of the IRQ1/FT/OUT pin. The IRQ1/FT/ OUT pin will toggle at 512Hz when FT and OUT bits = '1' (M41T83 only) and ST = '0.' Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a –10 (xx001010) to be loaded into the Digital Calibration byte, or +6 pF (00011000) into the Analog Calibration byte for correction. Note: Setting or changing the Digital Calibration byte does not affect the Frequency Test, Square Wave, or Watchdog Timer frequency, but changing the Analog Calibration byte DOES affect all functions derived from the low current oscillator (see Figure 19).

Figure 19. Clock divider chain and calibration circuits

Figure 20. Crystal isolation example

1. Substrate pad should be tied to V SS.

3.5 Setting the alarm clock registers

Address locations 0Ah-0Eh (Alarm 1) and 14h-18h (Alarm 2) contain the alarm settings. operation. T a b l e8 o n p a g e3 7 shows the possible bit configurations. moved to a different address.

3.6 Optional second programmable alarm

Figure 21. Alarm interrupt reset waveform Figure 22. Back-up mode alarm waveform

3.7 Watchdog timer

generates a watchdog interrupt. Watchdog Register. The time-out period then starts over. Flag (bit D7; Register 0Fh). SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied. Table 8. Alarm repeat modes

11111 O n c e p e r s e c o n d

11110 O n c e p e r m i n u t e

11100 O n c e p e r h o u r

11000 O n c e p e r d a y

10000 O n c e p e r m o n t h

00000 O n c e p e r y e a r

frequency of at least twice the selected timer clock.

3.8.1 Timer interr upt/timer pulse (TI/TP, M41T83 only)

• TI/TP = 0 IRQ1/FT/OUT is active when TF is logic '1' (subject to the status of the Timer Interrupt Enable bit (TIE).
• TI/TP = 1 IRQ1/FT/OUT pulses are active when TF is logic '1' according to Table 10 (subject to the status of the TIE bit). Note: If an Alarm cond ition, Watchdog time-out, Oscillator Failure, or OUT = 0 causes IRQ1/FT/OUT to be asserted low, then IRQ1/FT/OUT will remain asserted even if TI/TP is set to '1'. When in pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on IRQ1/FT/OUT. The output pulses will only stop if TE, TIE, or TI/TP are reset to '0'.

Table 9. Timer control register map (1)

1. Bit positions labeled with ‘0’ should always be written with logic '0.'

3.8.2 Timer flag (TF)

/TP bit). The TF bit is cleared by reading the Flags Register.

3.8.3 Timer interrupt enab le (TIE, M41T83 only)

clear the interrupt, the TF bit or the TIE bit must be reset.

3.8.4 Timer enable (TE)

• TE = 0 When the Timer Register (10h) is set to ‘0’, the timer is disabled.
• TE = 1 The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the counter will begin from the same value as when it was disabled.

3.8.5 TD1/0

TD1 and TD0 bits should be set to ‘11’ (1/60 Hz) for power saving. Table 10. Interrupt operation (bit TI /TP = 1)

1. TF and IRQ1 /FT/OUT become active simultaneously.
2. n = loaded countdown timer value. The timer is stopped when n = 0.

Table 11. Timer source clock frequency selection (244.1 µs to 4.25 hrs)

3.9 Square wave output (M41T83 only)

Wave Enable bit (SQWE) located in Register 0Ah. wave output will be disabled. Table 12. Timer countdown value register bits (addr 11h) (1)

1. Writing to the timer register will not reset the TF bit or clear the interrupt.

This register holds the loaded countdown value ‘n’. Countdown period = n / source clock frequency. Table 13. Square wave output frequency

0000 N o n e –

11008 H z

11014 H z

11102 H z

11111 H z

3.10 Battery low warning

the next scheduled 24-hour interval. should be considered suspect and verified as correct. A fresh battery should be installed. battery back-up mode, the battery should be replaced. power-up via a checksum or other technique.

3.11 Century bits

leap years correctly. See Table 14 for additional explanation.

3.12 Output driver pin

08h. In other words, when D7 (OUT bit) is a '0,' then the IRQ1/FT/OUT pin will be driven low. Note: The IRQ1 /FT/OUT pin is an open drain which requires an external pull-up resistor. Table 14. Century bits examples

1. Leap year occurs every four years (f or years evenly divisible by four), except for years evenly divisible by
2. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year

00 Y e s 2 0 0 0

3.13 Oscillator fail detection

validity of the clock and date data. This bit will be set to '1' any time the oscillator stops.

• The first time power is applied (defaults to a '1' on power-up). Note: If the OF bit cannot be written to '1' 4 seconds after the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.'
• The voltage present on VCC or battery is insufficient to support oscillation.
• The ST bit is set to '1.'
• External interference of the crystal For the M41T83, if the Oscillator Fail Interrupt Enable bit (OFIE) is set to a '1,' the IRQ1/FT/OUT pin will also be activated. The IRQ1/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (NOT by reading the Flag Register). The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event occurs during a power down condition, this bit will be set correctly.

3.14 Oscillator fail interr upt enable (M41T83 only)

by reading the Flags Register).

3.15 Initial power-on defaults

state indicated in Table 15 and Table 16. Table 15. Initial power-on default values (part 1)

1. All other control bits po wer-up in an undetermined state.

3.16 OTP bit operation (M41T83 in SOX18 package only)

each following year due to crystal aging. desired value of analog calibration. Table 16. Initial power-up default values (part 2)

1. All other control bits po wer-up in an undetermined state.

25 AL2E

4 Maximum ratings

Program and other relevant quality documents. Table 17. Absolute maximum ratings

1. Data based on characterization results, not tested in production.
2. Reflow at peak temperature of 260°C (total th ermal budget not to exceed 245°C for greater than 30

5 DC and AC parameters

the measurement conditions when using the quoted parameters. Figure 23. Measurement AC I/O waveform

1. Effective capacitance m easured with power supply at 3.6V; sampled only, not 100% tested.

Table 18. Operating and AC measurement conditions (1)

1. Output Hi-Z is defined as the point where data is no longer driven.

Table 19. Capacitance

Table 20. DC characteristics

1. Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.38 V to 5.5 V (except where noted).

5.5 V 125 150 µA

3.0 V 55 µA

5.5 V 8 10 µA

1. For non-rechargeable Lithium battery.

Figure 24. I CC2 vs. temperature Table 21. Crystal electrical characteristics

1. Externally supplied if using t he QFN16 or SO8 package. STMicroelectronics recommends the Citizen CFS-

see Section 8: References on page 56.

1. Load capacitors are integrated within the M41T8x. Ci rcuit board layout considerations for the 32.768 kHz

crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. Table 22. Oscillator characteristics

1. With default analog calibration value ( = 0).

Figure 25. Power down/up mode AC waveforms Table 23. Power down/up trip points DC characteristics

1. All voltages referenced to V SS.
2. Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.38 to 5.5 V (except where noted).

Figure 26. Bus timing requirement sequence Table 24. AC characteristics

1. Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.38 to 5.5 V (except where noted).
2. Transmitter must internally provi de a hold time to bridge the undefined region (300 ns max) of the falling

Package mechanical information M41T82 M41T83

6 Package mechanical information

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 27. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline Table 25. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm mech. data

Figure 30. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline Table 26. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal,

Figure 31. SO8 – 8-lead plastic small package outline Table 27. SO8 – 8-lead plastic small outline (150 mils body width), package mech.

7 Part numbering

ST sales office nearest you. Table 28. Ordering information

1. The SOX18 package includes an embedded 32,768 Hz crystal.

8 References

Below is a listing of the crystal component suppliers mentioned in this document.

• Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com.
• Micro Crystal can be contacted at sales@microcrystal.ch or http://www.microcrystal.com.

9 Revision history

Table 29. Document revision history amended footnotes in Table 1, Table 14 and Figure 5. KHz through document; made small text changes throughout document. Crystal information (Table 21). footnote 1 in Table 21; added Section 8: References. 17-Apr-2008 7 Updated cover page.