M40Z111_07 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
Datasheet sections
- 1 Description
- 2 Operation
- 2.1 Data retention lifetime calculation
- 2.2 V CC noise and negative going transients
- 3 Maximum rating
- 4 DC and AC parameters
- 5 Package mechanical data
- 6 Part numbering
- 7 Revision history
Features
■ Convert low power SRAMs into NVRAMs ■ Precision power monitoring and power switching circuitry ■ Automatic write-protection when VCC is out-of- tolerance ■ Choice of supply voltages and power-fail deselect voltages: –M 4 0 Z 1 1 1 : V CC = 4.5 to 5.5V THS = VSS; 4.5 ≤ VPFD ≤ 4.75V THS = VOUT; 4.2 ≤ VPFD ≤ 4.5V –M 4 0 Z 1 1 1 W : VCC = 3.0 to 3.6V THS = VSS; 2.8 ≤ VPFD ≤ 3.0V VCC = 2.7 to 3.3V THS = VOUT; 2.5 ≤ VPFD ≤ 2.7V ■ Less than 15ns chip enable access propagation delay (for 5.0v device) ■ Packaging includes a 28-lead SOIC and SNAPHAT ® top (to be ordered separately) ■ SOIC package provides direct connection for a SNAPHAT top which contains the battery ■ RoHS compliant – Lead-free second level interconnect SOH28 (MH) SNAPHAT (SH) battery
1 Description
low-power SRAM into a non-volatile memory. inactive to write-protect the stored data in the SRAM. the SRAM remains write protected until a valid power condition returns. completion of the surface mount process. “M4Z28-BR00SH1” or “M4Z32-BR00SH1” (See Table 11 on page 19). Figure 1. Logic diagram
Table 1. Signal names Figure 2. SOIC28 connections
Figure 3. Hardware hookup
Operation M40Z111, M40Z111W
2 Operation
The M40Z111/W, as shown in Figure 3 on page 7, can control up to two standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E CON) output pin follows the chip enable (E) input pin with timing shown in Table 2 on page 10. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). When VCC degrades during a power failure, ECON is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). The power fail detection value associated with VPFD is selected by the THS pin and is shown in Table 6 on page 14. Note: Note: The THS pin must be connected to either VSS or VOUT. If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time t WP, ECON is unconditionally driven high, write protecting the SRAM. A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user can be assured the memory will be write protected provided the VCC fall time exceeds tF. As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 6 on page 14). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output ECON is held inactive for tER (200ms maximum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 5 on page 9).
2.1 Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM SUPERVISOR. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and SRAMs to be “Don't Care” once V CC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to V OUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the I CCDR value of the M40Z111/W to determine the total current requirements for data retention.
Table 2. Power down/up AC characteristics
2.2 V CC noise and negative going transients
Figure 6) is recommended in order to provide the needed filtering. CC to VSS (cathode connected to VCC, anode to VSS). recommended for surface mount.
- V PFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
- V PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
- t ER (min) = 20ms for industrial temperature range - grade 6 device.
Figure 6. Supply voltage protection
3 Maximum rating
Program and other relevant quality documents. Table 3. Absolute maximum ratings Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
- For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (total thermal budget
not to exceed 245°C for greater than 30 seconds).
4 DC and AC parameters
in their projects match the measurement conditions when using the quoted parameters. Table 4. DC and AC measurement conditions Note: Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 7. AC testing load circuit Table 5. Capacitance
- Effective capacitance meas ured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only,
Table 6. DC characteristics
5 Package mechanical data
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 8. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, Note: Drawing is not to scale.
Table 7. SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data
Figure 9. 4-pin SNAPHAT housing for 48mAh battery, package outline Note: Drawing is not to scale. Table 8. 4-pin SNAPHAT housing for 48mAh battery, package mechanical data
Figure 10. 4-pin SNAPHAT housing for 120mAh battery, package outline Note: Drawing is not to scale. Table 9. 4-pin SNAPHAT housing for 120mAh battery, package mechanical data
6 Part numbering
Table 10. Ordering information scheme will drain the lithium button-cell battery. of this device, please contact the ST sales office nearest to you. Table 11. Battery table
- The SOIC package (SOH28) requires the battery package (SNAPHAT ®) which is ordered separately under
the part number “M4ZXX-BR00SHX” in plastic tubes or “M4ZXX-BR00SHXTR” in tape & reel form.
7 Revision history
Table 12. Document revision history updated Figure 5, Table 3, 10, 11.