M40Z300_10 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 25
Technical content
Datasheet sections
- 1 Description
- 2 Operation
- 2.1 Two to four decode
- 2.2 Data retention lifetime calculation
- 2.3 Power-on reset output
- 2.4 Battery low pin
- 3 Maximum ratings
- 4 DC and AC parameters
- 5 Package mechanical data
- 6 Part numbering
- 7 Revision history
Features
■ Converts low power SRAM into NVRAMs ■ Precision power monitoring and power switching circuitry ■ Automatic WRITE-protection when VCC is out- of-tolerance ■ Two-input decoder allows control for up to
8 SRAMs (with 2 devices active in parallel)
■ Choice of supply voltages and power-fail deselect voltages: –M 4 0 Z 3 0 0 : VCC = 4.5 V to 5.5 V THS = VSS: 4.5 V ≤ VPFD ≤ 4.75 V THS = VOUT: 4.2 V ≤ VPFD ≤ 4.5 V –M 4 0 Z 3 0 0 W : VCC = 3.0 V to 3.6 V THS = VSS: 2.8 V ≤ VPFD ≤ 3.0 V VCC = 2.7 V to 3.3 V THS = VOUT: 2.5 V ≤ VPFD ≤ 2.7 V ■ Reset output (RST) for power on reset ■ Battery low pin (BL) ■ Less than 12 ns chip enable access propagation delay (for 5.0 V device) ■ Packaging includes a 28-lead SOIC and SNAPHAT ® top (to be ordered separately), or A 16-lead SOIC ■ SOIC package provides direct connection for a SNAPHAT top which contains the battery ■ RoHS compliant – Lead-free second level interconnect SO16 (MQ) SNAPHAT (SH) crystal/battery SOH28 (MH)
Table 8. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package mechanical data . . . 19 Table 11. SO16 – 16-lead plastic small outline, 150 mils body width, package mechanical data . . . 22 Table 13. SNAPHAT
M40Z300, M40Z300W Description Doc ID 5679 Rev 5 5/25
1 Description
The M40Z300/W NVRAM supervisor is a self-contained device which converts a standard low-power SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the conditioned chip enable outputs (E1CON to E4CON) are forced inactive to write-protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the SNAPHAT® to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns. The 28-pin, 330 mil SOIC provides sockets with gold plated contacts for direct connection to a separate SNAPHAT housing containing the battery. The SNAPHAT housing has gold plated pins which mate with the sockets, ensuring reliable connection. The housing is keyed to prevent improper insertion. This unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process which greatly reduces the board manufacturing process complexity of either directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a “SNAP .” The 16-pin SOIC provides battery pins for an external user-supplied battery. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 28-pin SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4ZXX-BR00SH”. Caution: Do not place the SNAPHAT battery top in conductive foam, as this will drain the lithium button-cell battery.
Figure 1. Logic diagram
- For 16-pin SOIC package only.
Table 1. Signal names
- For M40Z300W, B– must be connected to the negativ e battery terminal only (not to pin 8, VSS).
Figure 5. Hardware hookup
- If the second chip enable pin (E2) is unused, it should be tied to VOUT.
M40Z300, M40Z300W Operation Doc ID 5679 Rev 5 9/25
2 Operation
The M40Z300/W, as shown in Figure 5 on page 8, can control up to four (eight, if placed in parallel) standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E1 CON to E4CON) output pins follow the chip enable (E) input pin with timing shown in Figure 6 on page 10 and Table 7 on page 17. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). When VCC degrades during a power failure, E1CON to E4CON are forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). For the M40Z300 the power fail detection value associated with VPFD is selected by the Threshold Select (THS) pin and is shown in Table 6 on page 15. For the M40Z300W, the THS pin selects both the supply voltage and VPFD (also shown in Table 6 on page 15). Note: In either case, THS pin must be connected to either V SS or VOUT. If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time t WPT, E1CON to E4CON are unconditionally driven high, write protecting the SRAM. A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below V PFD (min), the user can be assured the memory will be write protected within the Write Protect Time (tWPT) provided the VCC fall time exceeds tF (see Figure 6 on page 10). As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 6 on page 15). When VCC rises above VSO, VOUT is switched back to the supply voltage. Outputs E1CON to E4CON are held inactive for tCER (120ms maximum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 10 on page 16).
2.1 Two to four decode
independent SRAMs. The truth table for these inputs is shown in Table 2. Table 2. Truth table Figure 6. Address-decode time propagation delay between E1CON - E4CON.
2.2 Data retention lifetime calculation
), this pin should be tied to VOUT.
M40Z300, M40Z300W Operation Doc ID 5679 Rev 5 11/25 The data retention current value of the SRAMs can then be added to the IBAT value of the M40Z300/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT ® of your choice can then be divided by this current to determine the amount of data retention available (see Table 13 on page 23). Caution: Take care to avoid inadvertent discharge through VOUT and E1CON - E4CON after battery has been attached. For a further more detailed review of lifetime calculations, please see application note AN1012.
2.3 Power-on reset output
All microprocessors have a reset input which forces them to a known state when starting. The M40Z300/W has a reset output (RST ) pin which is guaranteed to be low within tWPT of VPFD (see Table 7). This signal is an open drain configuration. An appropriate pull-up resistor should be chosen to control the rise time. This signal will be valid for all voltage conditions, even when VCC equals VSS. Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low for tREC to allow the power supply to stabilize.
2.4 Battery low pin
The M40Z300/W automatically performs battery voltage monitoring upon power-up, and at factory-programmed time intervals of at least 24 hours. The battery low (BL ) pin will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL pin will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5 V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V CC is supplied. In order to insure data integrity during subsequent periods of battery backup mode, the battery should be replaced. The SNAPHAT® top should be replaced with valid VCC applied to the device. The M40Z300/W only monitors the battery when a nominal VCC is applied to the device. Thus appli-cations which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time.
2.5 V CC noise and negative going transients
Figure 7) is recommended in order to provide the needed filtering. CC to VSS (cathode connected to VCC, anode to VSS). recommended for surface mount. Figure 7. Supply voltage protection
3 Maximum ratings
extended periods may affect device reliability. Table 3. Absolute maximum ratings Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
- For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
4 DC and AC parameters
in their projects match the measurement conditions when using the quoted parameters. Table 4. DC and AC measurement conditions Note: Output High Z is defined as the point where data is no longer driven. Figure 8. AC testing load circuit Table 5. Capacitance
- Sampled only, not 100% tested.
Table 6. DC characteristics
- For RST & BL pins (open drain).
- Chip enable outputs (E1 CON - E4CON) can only sustain CMOS leakage currents in the battery backup mode.
Higher leakage currents will reduce battery life.
- Measured with V OUT and E1CON - E4CON open.
Table 7. Power down/up mode AC characteristics
- Valid for ambient operating temperature: T A = 0 to 70 °C or –40 to 8 5°C; VCC = 2.7 to 3.6 V or 4.5 to
- V PFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
- V PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
- t REC (min) = 20ms for industrial temperature Grade 6 device.
Package mechanical data M40Z300, M40Z300W 18/25 Doc ID 5679 Rev 5
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Figure 11. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, Note: Drawing is not to scale. Table 8. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package
Figure 12. SH – 4-pin SNAPHAT housing for 48 mAh battery, package outline Note: Drawing is not to scale. Table 9. SH – 4-pin SNAPHAT housing for 48 mAh battery, package mechanical data
Figure 13. SH – 4-pin SNAPHAT housing for 120mAh battery, package outline Note: Drawing is not to scale. Table 10. SH – 4-pin SNAPHAT housing for 120 mAh battery, package mechanical data
Figure 14. SO16 – 16-lead plastic small outline, 150 mils body width, package Note: Drawing is not to scale. Table 11. SO16 – 16-lead plastic small outline, 150 mils body width, package
6 Part numbering
Table 12. Ordering information example drain the lithium button-cell battery.
- Not recommended for new design. Contac t ST sales office for availability.
- The SOIC package (SOH28) requir es the battery package (SNAPHAT®) which is ordered separately under
the part number “M4Zxx-BR00SH” in plastic tubes or “M4Zxx-BR00SHTR” in tape & reel form. Table 13. SNAPHAT ® battery table
7 Revision history
Table 14. Document revision history