M40Z111 STMICROELECTRONICS | Alldatasheet
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Technical content
Figure 1. 28-pin SOIC Package
M40Z111, M40Z111W TABLE OF CONTENTS V
Figure 4. Hardware Hookup Table 2. Absolute Maximum Ratings CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
tions when using the quoted parameters. Table 3. DC and AC Measurement Conditions Note: Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 5. AC Testing Load Circuit Table 4. Capacitance Note: 1. Effective capacitance measured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only, not 100% tested.
Table 5. DC Characteristics
M40Z111, M40Z111W OPERATION The M40Z111/W, as shown in Figure 4, page 4, can control up to two standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E CON ) output pin follows the chip enable (E) input pin with timing shown in Table 6, page 9. An internal switch connects VCC to VOUT .T h i s switch has a voltage drop of less than 0.3V OUT1 ). When V CC degrades during a power failure, ECON is forced inactive independent of E. In this situa- tion, the SRAM is unconditionally write protected as V CC falls below an out-of-tolerance threshold (VPFD ). The power fail detection value associated with VPFD is selected by the THS pin and is shown in Table 5, page 6. Note: The THS pin must be connected to either VSS or VOUT . If chip enable access is in progress during a power fail detection, that memory cycle continues to com- pletion before the memory is write protected. If the memory cycle is not terminated within time t WP , ECON is unconditionally driven high, write protect- ing the SRAM. A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below V PFD (min), the user can be as- sured the memory will be write protected provided the V CC fall time exceeds tF. As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT . This occurs at the switchover voltage (VSO ). Below the VSO , the battery provides a volt- age VOHB to the SRAM and can supply current IOUT2 (see Table 5, page 6). When VCC rises above VSO ,V OUT is switched back to the supply voltage. Output ECON is held inactive for tER (200ms maximum) after the power supply has reached VPFD , independent of the Einput, to allow for processor stabilization (see Figure 7, page 8). Data Retention Lifetime Calculation Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM SUPERVI- SOR. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and SRAMs to be “Don't Care” once V CC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC =2 . 0 V . The chip enable access time must be sufficient to meet the system needs with the chip enable prop- agation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to V OUT . If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condi- tion for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the I CCDR value of the M40Z111/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT® of your choice can then be divided by this current to determine the amount of data retention avail- able (see Table 8, page 10). For more information on Battery Storage Life refer to the Application Note AN1012.
Table 6. Power Down/Up AC Characteristics
- VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC
- VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
- tER (min) = 20ms for Industrial Temperature Range - Grade 6 device.
VSS (cathode connected to VCC , anode to VSS ). Figure 8. Supply Voltage Protection
Table 7. Ordering Information Scheme “M4ZXX-BR00SHX” in plastic tube or “M4ZXX-BR00SHXTR” in Tape & Reel form. please contact the ST Sales Office nearest to you. Table 8. Battery Table
Figure 9. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline Note: Drawing is not to scale. Table 9. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
Figure 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline Note: Drawing is not to scale. Table 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
Figure 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline Note: Drawing is not to scale. Table 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
M40Z111, M40Z111W
REVISION HISTORY
Table 12. Document Revision History Reformatted, TOC added, changed DC Characteristics (Table 5); changed battery, ind.
M40Z111, M40Z111W Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.