M40SZ100Y STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 19
Technical content
M40SZ100Y, M40SZ100W TABLE OF CONTENTS
CC input for an out-of-tolerance condition. tected until a valid power condition returns. ® housing containing the battery. less” 16-pin SOIC package (MQ). ber is “M4ZXX-BR00SH” (see Table 13, page 17). Figure 3. Logic Diagram Note: 1. For 16-pin SOIC package only. Table 1. Signal Names
Figure 7. Hardware Hookup Table 2. Absolute Maximum Ratings CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 5. DC Characteristics
- Measured with VOUT and ECON open.
- RSTIN internally pulled-up to VCC through 100kΩ resistor.
- External SRAM must match SUPERVISOR chip VCC specification (3V or 5V).
- For rechargeable back-up, VBAT (max) may be considered VCC – 0.5V.
- Chip Enable output (ECON ) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will re-
- For RST & BL pins (Open Drain).
M40SZ100Y, M40SZ100W OPERATION The M40SZ100Y/W, as shown in Figure 7, page 5, can control one (two, if placed in parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are config- ured like this, however many fast SRAMs are not. During normal operating conditions, the condi- tioned chip enable (E CON ) output pin follows the chip enable (E) input pin with timing shown in Ta- ble 6, page 10. An internal switch connects VCC to VOUT . This switch has a voltage drop of less than 0.3V (IOUT1 ). When V CC degrades during a power failure, ECON is forced inactive independent of E. In this situa- tion, the SRAM is unconditionally write protected as V CC falls below an out-of-tolerance threshold (VPFD ). For the M40SZ100Y/W the power fail de- tection value associated with VPFD is shown in Ta- ble 5, page 7. If chip enable access is in progress during a power fail detection, that memory cycle continues to com- pletion before the memory is write protected. If the memory cycle is not terminated within time tWPT , ECON is unconditionally driven high, write protect- ing the SRAM. A power failure during a WRITE cy- cle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below V PFD (min), the user can be assured the memory will be write protected within the Write Protect Time (tWPT ) pro- vided the VCC fall time does not exceed tF (see Ta- ble 6, page 10). As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT . This occurs at the switchover voltage (VSO ). Below the VSO , the battery provides a volt- age VOHB to the SRAM and can supply current IOUT2 (see Table 5, page 7). When V CC rises above VSO , VOUT is switched back to the supply voltage. Output ECON is held in- active for tCER (120ms maximum) after the power supply has reached VPFD , independent of the E in- put, to allow for processor stabilization (see Figure 11, page 10). Data Retention Lifetime Calculation Most low power SRAMs on the market today can be used with the M40SZ100Y/W NVRAM Control- ler. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other in- puts to the SRAM. This allows inputs to the M40SZ100Y/W and SRAMs to be “Don't care” once V CC falls below VPFD (min) (see Figure 10, page 9). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable ac- cess time must be sufficient to meet the system needs with the chip enable propagation delays in- cluded. If data retention lifetime is a critical parameter for the system, it is important to review the data reten- tion current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers gen- erally specify a typical condition for room temper- ature along with a worst case condition (generally at elevated temperatures). The system level re- quirements will determine the choice of which val- ue to use. The data retention current value of the SRAMs can then be added to the I CCDR value of the M40SZ100Y/W to determine the total current requirements for data retention. The available bat- tery capacity for the SNAPHAT ® of your choice (see Table 13, page 17) can then be divided by this current to determine the amount of data reten- tion available. CAUTION : Take care to avoid inadvertent dis- charge through VOUT and ECON after battery has been attached. For a further more detailed review of lifetime calcu- lations, please see Application Note AN1012.
Figure 10. Power Down Timing
Figure 11. Power Up Timing Table 6. Power Down/Up AC Characteristics
- VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC
- VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
page 7). This signal is an open drain configuration. equals VSS (with valid battery voltage). tREC to allow the power supply to stabilize. VCC through a 100kΩ resistor. Figure 12. RSTIN Timing Waveform Table 7. Reset AC Characteristics
- Pulse width less than 50ns will result in no RESET (for noise immunity).
- CL = 5pF (see Figure 8, page 6).
chosen to control the rise time. VSS (cathode connected to VCC , anode to VSS ). Figure 13. Supply Voltage Protection
Figure 14. SO16 – 16-lead Plastic Small Package Outline Note: Drawing is not to scale. Table 8. SO16 – 16-lead Plastic Small Plastic Package Mechanical Data
Figure 15. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline Note: Drawing is not to scale. Table 9. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
Figure 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline Note: Drawing is not to scale. Table 10. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
Figure 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline Note: Drawing is not to scale. Table 11. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
Table 12. Ordering Information Scheme “M4ZXX-BR00SHX” in plastic tube or “M4ZXX-BR00SHXTR” in Tape & Reel form.
- Contact Local Sales Office
please contact the ST Sales Office nearest to you. Table 13. SNAPHAT® Battery Table
M40SZ100Y, M40SZ100W
REVISION HISTORY
Table 14. Document Revision History
M40SZ100Y, M40SZ100W M40SZ100, M40SZ100Y, M40SZ100W, 40SZ100, 40SZ100Y, 40SZ100W, ZEROPOWER, ZEROPOWER, ZEROPOW- ER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, SUPERVISOR, SUPERVISOR, SU- PERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVI- SOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Oscillator, Os- cillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Os- cillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Micro- processor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Micro- processor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Pro- tect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States