M3S9B92-EBZ20T

LM3S9B92_11 TI | Alldatasheet

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Stellaris® LM3S9B92 Microcontroller DATA SHEET Copyright © 2007-2011 Texas Instruments Incorporated DS-LM3S9B92-9538 TEXAS INSTRUMENTS-ADVANCE INFORMATION

Copyright © 2007-2011 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. ADV ANCE INFORMA TION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated

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Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm March 19, 20112 Texas Instruments-Advance Information

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Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address Register 26: Ethernet PHY Management Register 27 – Special Control/Status (MR27), address Register 29: Ethernet PHY Management Register 31 – PHY Special Control/Status (MR31), address March 19, 201130 Texas Instruments-Advance Information Table of Contents

Register 35: USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D .... 1020 Register 36: USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E .... 1021 31March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

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Register 300: USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset Register 301: USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset Register 302: USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset Register 303: USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset Register 304: USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset Register 305: USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset Register 306: USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset March 19, 201136 Texas Instruments-Advance Information Table of Contents

Register 307: USB Request Packet Count in Block Transfer Endpoint 8 (USBRQPKTCOUNT8), offset Register 308: USB Request Packet Count in Block Transfer Endpoint 9 (USBRQPKTCOUNT9), offset Register 309: USB Request Packet Count in Block Transfer Endpoint 10 (USBRQPKTCOUNT10), offset Register 310: USB Request Packet Count in Block Transfer Endpoint 11 (USBRQPKTCOUNT11), offset Register 311: USB Request Packet Count in Block Transfer Endpoint 12 (USBRQPKTCOUNT12), offset Register 312: USB Request Packet Count in Block Transfer Endpoint 13 (USBRQPKTCOUNT13), offset Register 313: USB Request Packet Count in Block Transfer Endpoint 14 (USBRQPKTCOUNT14), offset Register 314: USB Request Packet Count in Block Transfer Endpoint 15 (USBRQPKTCOUNT15), offset 37March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

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The revision history table notes changes made between the indicated revisions of the LM3S9B92 data sheet. Table1.RevisionHistory DescriptionRevisionDate ■ Clarified "Reset Control" section in the "System Control" chapter. ■ Corrected USB PLL speed in "Main Clock Tree" diagram. ■ Corrected reset value forDMAChannelWait-on-RequestStatus(DMAWAITSTAT) register. ■ Corrected "GPIO Pins With Non-Zero Reset Values" table. ■ Added diagram "Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual CSn" to EPI chapter. ■ Clarified that that the timer reload only happens in periodic mode. ■ Clarified that only bit 0 in theWatchdogControl(WDTCTL) register is protected from writes once set. ■ Added "Sample Averaging Example" diagram to ADC chapter. ■ Corrected "SSI Timing for SPI Frame Format" figure. ■ In "Electrical Characteristics" chapter: – Deleted T PORMIN parameter from "Power Characteristics" table, and deleted corresponding diagram. – Corrected t RDYSU parameter in "EPI General-Purpose Interface Characteristics" table and "General-Purpose Mode iRDY Timing" diagram. – Added t ADCSAMP sample time parameter to "ADC Characteristics" table. ■ Additional minor data sheet clarifications and corrections. 9538March 2011 41March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ Clarified Main Oscillator verification circuit sequence. ■ Added note that there must be a delay of 3 system clocks after the module clock is enabled before any of that module's registers are accessed. Also added note to add delay between powering-on the Ethernet PHY and accessing it. ■ Added "Example Schematic for Muxed Host-Bus 16 Mode" figure to External Peripheral Interface (EPI) chapter. ■ Corrected reset ofDevice Mode (DEVMOD)bitfield inUSBGeneral-PurposeControlandStatus (USBGPCS)register. ■ Clarified initialization and configuration procedure in "Analog Comparators" chapter. ■ In Electrical Characteristics chapter: – Added specification for maximum input voltage on a non-power pin when the microcontroller is unpowered (VNON parameter in Maximum Ratings table). – Replaced Preliminary Current Consumption Specifications with Nominal Power Consumption, Maximum Current Specifications, and Typical Current Consumption vs. Frequency sections. – Clarified Reset, and Power and Brown-out Characteristics and added a new specification for powering down before powering back up. – Added characteristics required when using an external regulator to provide power for VDDC. ■ Additional minor data sheet clarifications and corrections. 9161January 2011 March 19, 201142 Texas Instruments-Advance Information

Revision History

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ Information on Advanced Encryption Standard (AES) cryptography tables and Cyclic Redundancy Check (CRC) error detection functionality was inadvertently omitted from some datasheets. This has been added. ■ In APINTregister, changed bit name fromSYSRESETREQ to SYSRESREQ. ■ Added DEBUG (Debug Priority) bit field toSYSPRI3register. ■ Clarified Flash memory caution. ■ Restructured the General-Purpose Timer chapter to combine duplicated text. ■ Combined High and Low bit fields inGPTMTAILR, GPTMTAMATCHR, GPTMTAR, GPTMTAV, GPTMTBILR, GPTMTAMATCHR, GPTMTBRand GPTMTBVregisters for compatibility with future releases. ■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported. ■ Added SSI master clock restriction that SSIClk cannot be faster than 25 MHz. ■ Changed I 2C master and slave register base addresses and offsets to be relative to I2C module base, so register base and offsets were changed for all I2C slave registers. ■ In Electrical Characteristics chapter: – Added single-ended clock source input voltage values to "Recommended DC Operating Conditions" table. – Deleted Oscillation mode value from "MOSC Oscillator Input Characteristics" table. – Added T VDD2_3 supply voltage parameter to "Reset Characteristics" table. – Added "Power-On Reset and Voltage Parameters" timing diagram. – Added t ALEADD parameter to "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" table. – Added "Host-Bus 8/16 Mode Muxed Read Timing" and "Host-Bus 8/16 Mode Muxed Write Timing" timing diagrams. 8832December 2010 43March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was added, including all the Cortex-M3 registers. ■ Changed register names to be consistent with StellarisWare® names: the Cortex-M3Interrupt ControlandStatus(ICSR) register to theInterruptControlandState(INTCTRL) register, and the Cortex-M3InterruptSetEnable(SETNA) register to theInterrupt0-31SetEnable(EN0) register. ■ In the System Control chapter: – Corrected Reset Sources table (see Table 5-3 on page 200). – Added section "Special Considerations for Reset." ■ In the Internal Memory chapter: – Added clarification of instruction execution during Flash operations. – Deleted ROMVersion(RMVER) register as it is not used. ■ Modified Figure 8-1 on page 402 and Figure 8-2 on page 403 to clarify operation of the GPIO inputs when used as an alternate function. ■ Corrected GPIOAMSEL bit field inGPIOAnalogModeSelect(GPIOAMSEL) register to be eight-bits wide, bits[7:0]. ■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode. ■ In CAN chapter, clarified CAN bit timing examples. ■ In Operating Characteristics chapter, corrected Thermal resistance (junction to ambient) value to 32. ■ In Electrical Characteristics chapter: – Added "Input voltage for a GPIO configured as an analog input" value to Table 26-1 on page 1294. – Added ILKG parameter (GPIO input leakage current) to Table 26-5 on page 1296. – Corrected reset timing in Table 26-22 on page 1306. – Specified Max value forVREFA in Table 26-30 on page 1314. – Corrected values for tCLKRF (SSIClk rise/fall time) in Table 26-32 on page 1314. – Added I 2C Characteristics table (see Table 26-33 on page 1316). ■ Added dimensions for Tray and Tape and Reel shipping mediums. 7794September 2010 ■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.7413June 2010 March 19, 201144 Texas Instruments-Advance Information

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ Changed memory map ending address for EPI0 mapped peripheral and RAM from 0xCFFF.FFFF to 0xDFFF.FFFF. ■ Removed 4.194304-MHz crystal as a source for the system clock and PLL. ■ Summarized ROM contents descriptions in the "Internal Memory" chapter and removed various ROM appendices. ■ Clarified DMA channel terminology: changed name ofDMAChannelAlternateSelect(DMACHALT) register toDMAChannelAssignment(DMACHASGN) register, changedCHALT bit field toCHASGN, and changed terminology from primary and alternate channels to primary and secondary channels. ■ Clarified EPIMainBaudRate(EPIBAUD) equation. ■ In Signal Tables chapter, added table "Connections for Unused Signals." ■ In "Electrical Characteristics" chapter: – In "Reset Characteristics" table, corrected Supply voltage (VDD) rise time. – Clarified figure "SDRAM Initialization and Load Mode Register Timing". – Added BSEL0n/BSEL1n to EPI timing diagrams. 7299June 2010 ■ Added data sheets for five new Stellaris® Tempest-class parts: LM3S1R26, LM3S1621, LM3S1B21, LM3S9781, and LM3S9B81. ■ Additional minor data sheet clarifications and corrections. 7164May 2010 ■ Added pin table "Possible Pin Assignments for Alternate Functions", which lists the signals based on number of possible pin assignments. This table can be used to plan how to configure the pins for a particular functionality. ■ Additional minor data sheet clarifications and corrections. 7101May 2010 ■ Corrected reset for EPIHB8CFG, EPI_HB16CFGand EPIGPCFGregisters. ■ Extended TBRL bit field inGPTMTBRregister. ■ Additional minor data sheet clarifications and corrections. 6983March 2010 ■ Renamed theUSER_DBGregister to theBOOTCFGregister in the Internal Memory chapter. Added information on how to use a GPIO pin to force the ROM Boot Loader to execute on reset. ■ Added three figures to the ADC chapter on sample phase control. ■ Clarified configuration of USB0VBUS and USB0ID in OTG mode. 6912March 2010 45March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ Added 108-ball BGA package. ■ In "System Control" chapter: – Clarified functional description for external reset and brown-out reset. – Clarified Debug Access Port operation after Sleep modes. – Corrected the reset value of theRun-ModeClockConfiguration2(RCC2) register. ■ In "Internal Memory" chapter, clarified wording on Flash memory access errors and added a section on interrupts to the Flash memory description. ■ In "External Peripheral Interface" chapter: – Added clarification about byte selects and dual chip selects. – Added timing diagrams for continuous-read mode (formerly SRAM mode). – Corrected reset values ofEPIWriteFIFOCount(EPIWFIFOCNT) and EPIRawInterrupt Status(EPIRIS) registers. ■ Added clarification about timer operating modes and added register descriptions for theGPTM TimernPrescaleMatch(GPTMTnPMR) registers. ■ Clarified register descriptions forGPTMTimerAValue(GPTMTAV) and GPTMTimerBValue (GPTMTBV)registers. ■ Corrected the reset value of theADCSampleSequenceResultFIFOn(ADCSSFIFOn) registers. ■ Added ADCSamplePhaseControl(ADCSPC) register at offset 0x24. ■ Added caution note to theI2CMasterTimerPeriod(I2CMTPR) register description and changed field width to 7 bits. ■ In the "Controller Area Network" chapter, added clarification about reading from the CAN FIFO buffer and clarified packet timestamps functional description. ■ In the "Ethernet Controller" chapter: – Corrected the reset value and theLED1 bit positions of theEthernetMACLEDEncoding (MACLED)register. – Added clarification about the use of theNPR field in theEthernetMACNumberofPackets (MACNP)register. – Corrected reset values forEthernetPHYManagementRegister0–Control(MR0) and EthernetPHYManagementRegister5–Auto-NegotiationLinkPartnerBasePageAbility (MR5)registers. ■ Added Session Disconnect (DISCON) bit to theUSBGeneralInterruptStatus(USBIS) and USBInterruptEnable(USBIE) registers. ■ Made these changes to the Operating Characteristics chapter: – Added storage temperature ratings to "Temperature Characteristics" table – Added "ESD Absolute Maximum Ratings" table ■ Made these changes to the Electrical Characteristics chapter: – In "Flash Memory Characteristics" table, corrected Mass erase time – Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) – In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time – Modified the preliminary current consumption specification for Run mode 1 and Deep-Sleep mode. – Added table entry for VDD3ON power consumption to Table 26-8 on page 1296. ■ Added additional DriverLib functions to appendix. 6790February 2010 March 19, 201146 Texas Instruments-Advance Information

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ Released new 1000, 3000, 5000 and 9000 series Stellaris® devices. ■ The IDCODE value was corrected to be 0x4BA0.0477. ■ Clarified that the NMISET bit in theICSRregister in the NVIC is also a source for NMI. ■ Clarified the use of the LDO. ■ To clarify clock operation, reorganized clocking section, changed theUSEFRACT bit to theDIV400 bit and theFRACT bit to theSYSDIV2LSB bit in theRCC2register, added tables, and rewrote descriptions. ■ Corrected bit description of theDSDIVORIDE field in theDSLPCLKCFGregister. ■ Removed theDSFLASHCFGregister at System Control offset 0x14C as it does not function correctly. ■ Removed the MAXADC1SPD and MAXADC0SPD fields from theDCGC0as they have no function in deep-sleep mode. ■ Corrected address offsets for theFlashWriteBuffer(FWBn) registers. ■ Added FlashControl(FCTL) register at Internal memory offset 0x0F8 to help control frequent power cycling when hibernation is not used. ■ Changed the name of the EPI channels for clarification: EPI0_TX became EPI0_WFIFO and EPI0_RX became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions. ■ Removed the DMACHISregister at DMA module offset 0x504 as it does not function correctly. ■ Corrected alternate channel assignments for the µDMA controller. ■ Major improvements to the EPI chapter. ■ EPISDRAMCFG2register was deleted as its function is not needed. ■ Clarified CAN bit timing and corrected examples. ■ Added pseudo-code for MDI/MDIX operation. ■ Corrected reset value of theMR1register to 0x7809. ■ Clarified PWM source for ADC triggering ■ Corrected ADDR field in theUSBTXFIFOADDregister to be 9 bits instead of 13 bits. ■ Changed SSI set up and hold times to be expressed in system clocks, not ns. ■ Updated Electrical Characteristics chapter with latest data. Changes were made to ADC and EPI content. ■ Additional minor data sheet clarifications and corrections. 6458October 2009 47March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ Added "Non-Blocking Read Cycle", "Normal Read Cycle", and "Write Cycle" sections to EPI chapter. ■ Corrected values for MAXADC0SPD and MAXADC1SPD bits inDC1, RCGC0, SCGC0, andDCGC0 registers. ■ Corrected figure "TI Synchronous Serial Frame Format (Single Transfer)". ■ Added description for Ethernet PHY power-saving modes. ■ Made a number of corrections to the Electrical Characteristics chapter: – Deleted V BAT and VREFA parameters from and added footnotes to Recommended DC Operating Conditions table. – Deleted Nominal and Maximum Current Specifications section. – Modified EPI SDRAM Characteristics table:

• Changed t EPIR to tSDRAMR and deleted values for 2-mA and 4-mA drive.
• Changed t EPIF to tSDRAMF and deleted values for 2-mA and 4-mA drive. – Changed values for tCOV, tCOI, and tCOT parameters in EPI SDRAM Interface Characteristics table. – Deleted SDRAM Read Command Timing, SDRAM Write Command Timing, SDRAM Write Burst Timing, SDRAM Precharge Command Timing and SDRAM CAS Latency Timing figures and replaced with SDRAM Read Timing and SDRAM Write Timing figures. – Modified Host-Bus 8/16 Mode Write Timing figure. – Modified General-Purpose Mode Read and Write Timing figure. – Modified values for tDV and tDI parameters, and deleted tOD parameter from EPI General-Purpose Interface Characteristics figure. – Major changes to ADC Characteristics tables, including adding additonal tables and diagram. ■ Added missing ROM_I2SIntStatus function to ROM DriverLib Functions appendix. ■ Corrected ordering part numbers. ■ Additional minor data sheet clarifications and corrections. 5930July 2009 March 19, 201148 Texas Instruments-Advance Information

Table1.RevisionHistory (continued) DescriptionRevisionDate ■ In System Control chapter, clarified power-on reset and external reset pin descriptions in "Reset Sources" section. ■ Added missing comparator output pin bits toDC3register; reset value changed as well. ■ Clarified explanation of nonvolatile register programming in Internal Memory chapter. ■ Added explanation of reset value toFMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, andUSER_REG0 registers. ■ In Request Type Support table in DMA chapter, corrected general-purpose timer row. ■ In General-Purpose Timers chapter, clarified DMA operation. ■ Added table "Preliminary Current Consumption" to Characteristics chapter. ■ Corrected Nom and Max values in EPI Characteristics table. ■ Added "CSn to output invalid" parameter to EPI table "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" and figure "Host-Bus 8/16 Mode Read Timing". ■ Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table. ■ Updated ROM DriverLib appendix with RevC0 functions. ■ Updated part ordering numbers. ■ Additional minor data sheet clarifications and corrections. 5779June 2009 Started tracking revision history.5285May 2009 49March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

This data sheet provides reference information for the LM3S9B92 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. AboutThisManual This document is organized into sections that correspond to each major feature. RelatedDocuments The following related documents are available on the Stellaris® web site at www.ti.com/stellaris: ■ Stellaris® Errata ■ ARM® Cortex™-M3 Errata ■ Cortex™-M3 Instruction Set Technical User's Manual ■ Stellaris® Boot Loader User's Guide ■ Stellaris® Graphics Library User's Guide ■ Stellaris® Peripheral Driver Library User's Guide ■ Stellaris® ROM User’s Guide ■ Stellaris® USB Library User's Guide The following related documents are also referenced: ■ ARM® Debug Interface V5 Architecture Specification ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. March 19, 201150 Texas Instruments-Advance Information About This Document

This document uses the conventions shown in Table 2 on page 51. Table2.DocumentationConventions MeaningNotation GeneralRegisterNotation APB registers are indicated in uppercase bold. For example,PBORCTLis the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example,SRCRnrepresents any (or all) of the three Software Reset Control registers: SRCR0,SRCR1 , andSRCR2. REGISTER A single bit in a register.bit Two or more consecutive and related bits.bit field A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 97. offset 0xnnn Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Register N Register bits markedreserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. yy:xx This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RegisterBit/Field Types Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC Software can read this field. Always write the chip reset value.RO Software can read or write this field.R/W Software can read or write this field. Writing to it with any value clears the register.R/WC Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1C Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. R/W1S Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. W1C Only a write by software is valid; a read of the register returns no meaningful data.WO This value in the register bit diagram shows the bit/field value after any reset, unless noted.RegisterBit/Field ResetValue Bit cleared to 0 on chip reset.0 Bit set to 1 on chip reset.1 Nondeterministic.- Pin/SignalNotation Pin alternate function; a pin defaults to the signal without the brackets.[ ] Refers to the physical connection on the package.pin Refers to the electrical signal encoding of a pin.signal 51March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table2.DocumentationConventions (continued) MeaningNotation Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (seeSIGNAL and SIGNAL below). assert a signal Change the value of the signal from the logically True state to the logically False state.deassert a signal Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assertSIGNAL is to drive it Low; to deassertSIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassertSIGNAL is to drive it Low. SIGNAL Numbers An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. X Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. March 19, 201152 Texas Instruments-Advance Information About This Document

1 ArchitecturalOverview

Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM® Cortex™-M3-based microcontrollers to the broadest reach of the microcontroller market. For current users of 8- and 16-bit MCUs, Stellaris® with Cortex-M3 offers a direct path to the strongest ecosystem of development tools, software and knowledge in the industry. Designers who migrate to Stellaris benefit from great tools, small code footprint and outstanding performance. Even more important, designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to 1 GHz. For users of current 32-bit MCUs, the Stellaris family offers the industry’s first implementation of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2 technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system cost while delivering 25 percent better performance. The Texas Instruments Stellaris family of microcontrollers—the first ARM Cortex-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S9B92 microcontroller has the following features: ■ ARM Cortex-M3 Processor Core – 80-MHz operation; 100 DMIPS performance – ARM Cortex SysTick Timer – Nested Vectored Interrupt Controller (NVIC) ■ On-Chip Memory – 256 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above 50 MHz – 96 KB single-cycle SRAM – Internal ROM loaded with StellarisWare® software:

• Stellaris Peripheral Driver Library
• Stellaris Boot Loader
• Advanced Encryption Standard (AES) cryptography tables
• Cyclic Redundancy Check (CRC) error detection functionality ■ External Peripheral Interface (EPI) – 8/16/32-bit dedicated parallel bus for external peripherals – Supports SDRAM, SRAM/Flash memory, FPGAs, CPLDs ■ Advanced Serial Integration – 10/100 Ethernet MAC and PHY – Two CAN 2.0 A/B controllers – USB 2.0 OTG/Host/Device 53March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

– Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls) – Two I2C modules – Two Synchronous Serial Interface modules (SSI) – Integrated Interchip Sound (I2S) module ■ System Integration – Direct Memory Access Controller (DMA) – System control and clocks including on-chip precision 16-MHz oscillator – Four 32-bit timers (up to eight 16-bit), with real-time clock capability – Eight Capture Compare PWM pins (CCP) – Two Watchdog Timers

• One timer runs off the main oscillator
• One timer runs off the precision internal oscillator – Up to 65 GPIOs, depending on configuration
• Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
• Independently configurable to 2, 4 or 8 mA drive capability
• Up to 4 GPIOs can have 18 mA drive capability ■ Advanced Motion Control – Eight advanced PWM outputs for motion and energy applications – Four fault inputs to promote low-latency shutdown – Two Quadrature Encoder Inputs (QEI) ■ Analog – Two 10-bit Analog-to-Digital Converters (ADC) with 16 analog input channels and a sample rate of one million samples/second – Three analog comparators – 16 digital comparators – On-chip voltage regulator ■ JTAG and ARM Serial Wire Debug (SWD) ■ 100-pin LQFP and 108-ball BGA package ■ Industrial (-40°C to 85°C) Temperature Range The LM3S9B92 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. March 19, 201154 Texas Instruments-Advance Information Architectural Overview

In addition, the LM3S9B92 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S9B92 microcontroller is code-compatible to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page 1376 for ordering information for Stellaris family devices.

1.1 FunctionalOverview

The following sections provide an overview of the features of the LM3S9B92 microcontroller. The page number in parentheses indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 1376.

1.1.1 ARMCortex-M3

The following sections provide an overview of the ARM Cortex-M3 processor core and instruction set, the integrated System Timer (SysTick) and the Nested Vectored Interrupt Controller.

1.1.1.1 ProcessorCore (seepage78)

All members of the Stellaris product family, including the LM3S9B92 microcontroller, are designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. ■ 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast multiplier ■ Deterministic, high-performance interrupt handling for time-critical applications 55March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7 processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage ■ Ultra-low power consumption with integrated sleep modes ■ 80-MHz operation ■ 1.25 DMIPS/MHz

1.1.1.2 MemoryMap (seepage97)

A memory map lists the location of instructions and data in memory. The memory map for the LM3S9B92 controller can be found in “Memory Model” on page 97. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map.

1.1.1.3 SystemTimer(SysTick) (seepage121)

ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine ■ A high-speed alarm timer using the system clock ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter ■ A simple counter used to measure time to completion and time used ■ An internal clock-source control based on missing/meeting durations.

1.1.1.4 NestedVectoredInterruptController(NVIC) (seepage122)

The LM3S9B92 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 53 interrupts. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining ■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications March 19, 201156 Texas Instruments-Advance Information Architectural Overview

■ Dynamically reprioritizable interrupts ■ Exceptional interrupt handling via hardware implementation of required register manipulations

1.1.1.5 SystemControlBlock(SCB) (seepage124)

The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions.

1.1.1.6 MemoryProtectionUnit(MPU) (seepage124)

The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system.

1.1.2 On-ChipMemory

The following sections describe the on-chip memory modules.

1.1.2.1 SRAM (seepage303)

The LM3S9B92 microcontroller provides 96 KB of single-cycle on-chip SRAM. The internal SRAM of the Stellaris devices is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller (µDMA).

1.1.2.2 FlashMemory (seepage305)

The LM3S9B92 microcontroller provides 256 KB of single-cycle on-chip Flash memory (above 50 MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches incur a one-cycle stall). The Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger.

1.1.2.3 ROM (seepage303)

The LM3S9B92 ROM is preprogrammed with the following software and programs: ■ Stellaris Peripheral Driver Library ■ Stellaris Boot Loader ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error-detection functionality 57March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

The Stellaris Peripheral Driver Library is a royalty-free software library for controlling on-chip peripherals with a boot-loader capability. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M3 core. No special pragmas or custom assembly code prologue/epilogue functions are required. For applications that require in-field programmability, the royalty-free Stellaris Boot Loader can act as an application loader and support in-field firmware updates. The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government. AES is a strong encryption method with reasonable performance and size. In addition, it is fast in both hardware and software, is fairly easy to implement, and requires little memory. The Texas Instruments encryption package is available with full source code, and is based on lesser general public license (LGPL) source. An LGPL means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source). Modifications to the package source, however, must be open source. CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents as when previously checked. This technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more readily.

1.1.3 ExternalPeripheralInterface (seepage453)

The External Peripheral Interface (EPI) provides access to external devices using a parallel path. Unlike communications peripherals such as SSI, UART, and I2C, the EPI is designed to act like a bus to external peripherals and memory. The EPI has the following features: ■ 8/16/32-bit dedicated parallel bus for external peripherals and memory ■ Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from SDRAM, SRAM and Flash memory ■ Blocking and non-blocking reads ■ Separates processor from timing details through use of an internal write FIFO ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for read and write – Read channel request asserted by programmable levels on the internal non-blocking read FIFO (NBRFIFO) – Write channel request asserted by empty on the internal write FIFO (WFIFO) The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory (SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a communication mechanism and is speed-controlled using clocking. ■ Synchronous Dynamic Random Access Memory (SDRAM) mode March 19, 201158 Texas Instruments-Advance Information Architectural Overview

– Supports x16 (single data rate) SDRAM at up to 50 MHz – Supports low-cost SDRAMs up to 64 MB (512 megabits) – Includes automatic refresh and access to all banks/rows – Includes a Sleep/Standby mode to keep contents active with minimal power draw – Multiplexed address/data interface for reduced pin count ■ Host-Bus mode – Traditional x8 and x16 MCU bus interface capabilities – Similar device compatibility options as PIC, ATmega, 8051, and others – Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with no byte selects) – Support of both muxed and de-muxed address and data – Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant, with support for external FIFO (XFIFO) EMPTY and FULL signals – Speed controlled, with read and write data wait-state counters – Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn – Manual chip-enable (or use extra address pins) ■ General-Purpose mode – Wide parallel interfaces for fast communications with CPLDs and FPGAs – Data widths up to 32 bits – Data rates up to 150 MB/second – Optional "address" sizes from 4 bits to 20 bits – Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input ■ General parallel GPIO – 1 to 32 bits, FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls

1.1.4 SerialCommunicationsPeripherals

The LM3S9B92 controller supports both asynchronous and synchronous serial communications with: ■ 10/100 Ethernet MAC and PHY 59March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ Two CAN 2.0 A/B controllers ■ USB 2.0 OTG/Host/Device ■ Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls) ■ Two I2C modules ■ Two Synchronous Serial Interface modules (SSI) ■ Integrated Interchip Sound (I2S) module The following sections provide more detail on each of these communications functions.

1.1.4.1 EthernetController (seepage903)

Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. This specification defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface and has the following features: ■ Conforms to theIEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line – 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler – Full-featured auto-negotiation ■ Multiple operational modes – Full- and half-duplex 100 Mbps – Full- and half-duplex 10 Mbps – Power-saving and power-down modes ■ Highly configurable – Programmable MAC address – LED activity selection – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ■ Physical media manipulation – MDI/MDI-X cross-over support through software assist March 19, 201160 Texas Instruments-Advance Information Architectural Overview

– Register-programmable transmit amplitude – Automatic polarity correction and 10BASE-T signal reception ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive channel request asserted on packet receipt – Transmit channel request asserted on empty transmit FIFO

1.1.4.2 ControllerAreaNetwork (seepage853)

Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally created for automotive purposes, it is now used in many embedded control applications (for example, industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The LM3S9B92 microcontroller includes two CAN units with the following features: ■ CAN protocol version 2.0 part A/B ■ Bit rates up to 1 Mbps ■ 32 message objects with individual identifier masks ■ Maskable interrupt ■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications ■ Programmable Loopback mode for self-test operation ■ Programmable FIFO mode enables storage of multiple message objects ■ Gluelessly attaches to an external CAN transceiver through theCANnTX and CANnRX signals

1.1.4.3 USB (seepage962)

Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The LM3S9B92 microcontroller supports three configurations in USB 2.0 full and low speed: USB Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other USB-enabled systems). The USB module has the following features: ■ Complies with USB-IF certification standards ■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY 61March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous ■ 32 endpoints – 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint – 15 configurable IN endpoints and 15 configurable OUT endpoints ■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size ■ VBUS droop and valid ID detection and interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data

1.1.4.4 UART (seepage676)

A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S9B92 microcontroller includes three fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem status, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. The three UARTs have the following features: ■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by 16) and 10 Mbps for high speed (divide by 8) ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing March 19, 201162 Texas Instruments-Advance Information Architectural Overview

Programmable use of IrDA Serial Infrared (SIR) or UART input/output– – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Support for communication with ISO 7816 smart cards ■ Full modem handshake support (on UART1) ■ LIN protocol support ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level

1.1.4.5 I 2C (seepage780)

The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. Each device on the I2C bus can be designated as either a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts. The LM3S9B92 microcontroller includes two I2C modules with the following features: ■ Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation ■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive 63March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

1.1.4.6 SSI (seepage737)

Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts data between parallel and serial. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The LM3S9B92 microcontroller includes two SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation ■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO contains 4 entries

1.1.4.7 Inter-IntegratedCircuitSound(I 2S)Interface (seepage817)

The I2S interface is a configurable serial audio core that contains a transmit module and a receive module. The module is configurable for the I2S as well as Left-Justified and Right-Justified serial March 19, 201164 Texas Instruments-Advance Information Architectural Overview

audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact 8-Bit Stereo. The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo, each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements further. Both the transmitter and receiver are capable of being a master or a slave. The Stellaris I2S interface has the following features: ■ Configurable audio format supporting I2S, Left-justification, and Right-justification ■ Configurable sample size from 8 to 32 bits ■ Mono and Stereo support ■ 8-, 16-, and 32-bit FIFO interface for packing memory ■ Independent transmit and receive 8-entry FIFOs ■ Configurable FIFO-level interrupt and µDMA requests ■ Independent transmit and receive MCLK direction control ■ Transmit and receive internal MCLK sources ■ Independent transmit and receive control for serial clock and word select ■ MCLK and SCLK can be independently set to master or slave ■ Configurable transmit zero or last sample when FIFO empty ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Burst requests – Channel requests asserted when FIFO contains required amount of data

1.1.5 SystemIntegration

The LM3S9B92 microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ Four 32-bit timers (up to eight 16-bit), with real-time clock capability ■ Eight Capture Compare PWM pins (CCP) ■ Two Watchdog Timers 65March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

– One timer runs off the main oscillator – One timer runs off the precision internal oscillator ■ Up to 65 GPIOs, depending on configuration – Highly flexible pin muxing allows use as GPIO or one of several peripheral functions – Independently configurable to 2, 4 or 8 mA drive capability – Up to 4 GPIOs can have 18 mA drive capability The following sections provide more detail on each of these functions.

1.1.5.1 DirectMemoryAccess (seepage339)

The LM3S9B92 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ■ ARM PrimeCell® 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Primary and secondary channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping March 19, 201166 Texas Instruments-Advance Information Architectural Overview

– Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests

1.1.5.2 SystemControlandClocks (seepage199)

System control determines the overall operation of the device. It provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. ■ Device identification information: version, part number, SRAM size, Flash memory size, and so on ■ Power control – On-chip fixed Low Drop-Out (LDO) voltage regulator – Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating – Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Multiple clock sources for microcontroller system clock – Precision Oscillator (PIOSC): On-chip resource providing a 16 MHz ±1% frequency at room temperature

• 16 MHz ±3% across temperature
• Software power down control for low power modes – Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external single-ended clock source is connected to theOSC0 input pin, or an external crystal is connected across theOSC0 input andOSC1 output pins.
• External oscillator used with or without on-chip PLL: select supported frequencies from 1 MHz to 16.384 MHz.
• External crystal: from DC to maximum device speed – Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during power-saving modes ■ Flexible reset sources – Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) detector alerts to system power drops – Software reset 67March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

– Watchdog timer reset – MOSC failure

1.1.5.3 ProgrammableTimers (seepage526)

Programmable timers can be used to count or time external events that drive the Timer input pins. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional options: ■ Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes – 16-bit PWM mode with software-programmable output inversion of the PWM signal ■ Count up or down ■ Eight Capture Compare PWM pins (CCP) ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ ADC event trigger ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt

1.1.5.4 CCPPins (seepage533)

Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The LM3S9B92 microcontroller includes eight Capture Compare PWM pins (CCP) that can be programmed to operate in the following modes: March 19, 201168 Texas Instruments-Advance Information Architectural Overview

■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer captures and stores the current timer value when a programmed event occurs. ■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer compares the current value with a stored value and generates an interrupt when a match occurs. ■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated based on a match between the counter value and a value stored in a match register and is output on the CCP pin.

1.1.5.5 WatchdogTimers (seepage572)

A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer can generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. The LM3S9B92 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug

1.1.5.6 ProgrammableGPIOs (seepage397)

General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-65 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1216 for the signals available to each GPIO pin). ■ Up to 65 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Fast toggle capable of a change every two clock cycles 69March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables

1.1.6 AdvancedMotionControl

The LM3S9B92 microcontroller provides motion control functions integrated into the device, including: ■ Eight advanced PWM outputs for motion and energy applications ■ Four fault inputs to promote low-latency shutdown ■ Two Quadrature Encoder Inputs (QEI) The following provides more detail on these motion control functions.

1.1.6.1 PWM (seepage1114)

Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. The LM3S9B92 PWM module consists of four PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. Each PWM generator has the following features: March 19, 201170 Texas Instruments-Advance Information Architectural Overview

■ Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled ■ One 16-bit counter – Runs in Down or Up/Down mode – Output frequency controlled by a 16-bit load value – Load value updates can be synchronized – Produces output signals at zero and load value ■ Two PWM comparators – Comparator value updates can be synchronized – Produces output signals on match ■ PWM signal generator – Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals – Produces two independent PWM signals ■ Dead-band generator – Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge – Can be bypassed, leaving input PWM signals unmodified ■ Can initiate an ADC sample sequence The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The PWM control block has the following options: ■ PWM output enable of each PWM signal ■ Optional output inversion of each PWM signal (polarity control) ■ Optional fault handling for each PWM signal ■ Synchronization of timers in the PWM generator blocks ■ Synchronization of timer/comparator updates across the PWM generator blocks ■ Synchronization of PWM output enables across the PWM generator blocks ■ Interrupt status summary of the PWM generator blocks ■ Extended fault capabilities with multiple fault signals, programmable polarities, and filtering ■ PWM generators can be operated independently or synchronized with other generators 71March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

1.1.6.2 QEI (seepage1191)

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index signal, can be used to reset the position counter. The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 20 MHz for a 80-MHz system). The LM3S9B92 microcontroller includes two QEI modules providing control of two motors at the same time with the following features: ■ Position integrator that tracks the encoder position ■ Programmable noise filter on the inputs ■ Velocity capture using built-in timer ■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) ■ Interrupt generation on: – Index pulse – Velocity-timer expiration – Direction change – Quadrature error detection

1.1.7 Analog

The LM3S9B92 microcontroller provides analog functions integrated into the device, including: ■ Two 10-bit Analog-to-Digital Converters (ADC) with 16 analog input channels and a sample rate of one million samples/second ■ Three analog comparators ■ 16 digital comparators ■ On-chip voltage regulator The following provides more detail on these analog functions.

1.1.7.1 ADC (seepage597)

An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris ADC module features 10-bit conversion resolution and supports 16 input channels plus an internal temperature sensor. Four buffered sample sequencers allow rapid sampling of up to 16 analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator function that allows the conversion value to be diverted to a comparison unit that provides eight digital comparators. March 19, 201172 Texas Instruments-Advance Information Architectural Overview

The LM3S9B92 microcontroller provides two ADC modules with the following features: ■ 16 shared analog input channels ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Maximum sample rate of one million samples/second ■ Optional phase shift in sample time programmable from 22.5º to 337.5º ■ Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – PWM – GPIO ■ Hardware averaging of up to 64 samples for improved accuracy ■ Digital comparison unit providing eight digital comparators ■ Converter uses an internal 3-V reference or an external reference ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA

1.1.7.2 AnalogComparators (seepage1101)

An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The LM3S9B92 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. The LM3S9B92 microcontroller provides three independent integrated analog comparators with the following functions: 73March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of the following voltages: – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage

1.1.8 JTAGandARMSerialWireDebug (seepage187)

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module providing all the normal JTAG debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. The SWJ-DP interface has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

1.1.9 PackagingandTemperature

■ Industrial-range 100-pin RoHS-compliant LQFP package ■ Industrial-range 108-ball RoHS-compliant BGA package

1.2 TargetApplications

The Stellaris family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: March 19, 201174 Texas Instruments-Advance Information Architectural Overview

■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation

1.3 High-LevelBlockDiagram

Figure 1-1 on page 76 depicts the features on the Stellaris LM3S9B92 microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus. 75March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure1-1.StellarisLM3S9B92MicrocontrollerHigh-LevelBlockDiagram LM3S9B92 ARM® Cortex™-M3 (80 MHz) NVIC MPU Flash (256 KB) Boot Loader DriverLib AES & CRC ROM DCode bus ICode bus JTAG/SWD System Control and Clocks (w/ Precis. Osc.) Bus Matrix System Bus SRAM (96 KB) SYSTEM PERIPHERALS Watchdog Timers (2) DMA General- Purpose Timers (4) GPIOs (65) External Peripheral Interface SERIAL PERIPHERALS UARTs (3) USB OTG (FS PHY) I2C (2) SSI (2) Ethernet MAC/PHY CAN Controllers (2) I2S ANALOG PERIPHERALS ADC Channels (16) Analog Comparators (3) MOTION CONTROL PERIPHERALS QEI (2) PWM (8) Advanced Peripheral Bus (APB) Advanced High-Performance Bus (AHB) March 19, 201176 Texas Instruments-Advance Information Architectural Overview

1.4 HardwareDetails

Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 1214 ■ “Signal Tables” on page 1216 ■ “Operating Characteristics” on page 1293 ■ “Electrical Characteristics” on page 1294 ■ “Package Information” on page 1378 77March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

2 TheCortex-M3Processor

The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ 32-bit ARM® Cortex™-M3 architecture optimized for small-footprint embedded applications ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast multiplier ■ Deterministic, high-performance interrupt handling for time-critical applications ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7 processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage ■ Ultra-low power consumption with integrated sleep modes ■ 80-MHz operation ■ 1.25 DMIPS/MHz The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. March 19, 201178 Texas Instruments-Advance Information The Cortex-M3 Processor

This chapter provides information on the Stellaris implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see theCortex™-M3 Instruction Set Technical User's Manual.

2.1 BlockDiagram

The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 79March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure2-1.CPUBlockDiagram Private Peripheral Bus ( internal) Data W atchpoint and T race Interrupts Debug Sleep Instrumentation T race Macrocell T race Port Interface Unit CM3 Core Instructions Data Flash Patch and Breakpoint Memory Protection Unit Debug Access Port Nested V ectored Interrupt Controller Serial Wire JT AG Debug Port Bus Matrix Adv . Peripheral Bus I-code bus D-code bus System bus ROM T able Serial Wire Output T race Port ( SWO) ARM Cortex -M3

2.2 Overview

2.2.1 System-LevelInterface

The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis.

2.2.2 IntegratedConfigurableDebug

The Cortex-M3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See theARM® Debug Interface V5 Architecture Specification for details on SWJ-DP . For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. March 19, 201180 Texas Instruments-Advance Information The Cortex-M3 Processor

The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5 Architecture Specification.

2.2.3 TracePortInterfaceUnit(TPIU)

The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 81. Figure2-2.TPIUBlockDiagram A TB Interface Asynchronous FIFO APB Interface T race Out ( serializer) Debug A TB Slave Port APB Slave Port Serial Wire T race Port ( SWO)

2.2.4 Cortex-M3SystemComponentDetails

The Cortex-M3 includes the following system components: ■ SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see “System Timer (SysTick)” on page 121). ■ Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 122). ■ System Control Block (SCB) 81March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions( see “System Control Block (SCB)” on page 124). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see “Memory Protection Unit (MPU)” on page 124).

2.3 ProgrammingModel

This section describes the Cortex-M3 programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included.

2.3.1 ProcessorModeandPrivilegeLevelsforSoftwareExecution

The Cortex-M3 has two modes of operation: ■ Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. ■ Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M3 has two privilege levels: ■ Unprivileged In this mode, software has the following restrictions: – Limited access to theMSR and MRS instructions and no use of theCPS instruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals ■ Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, theCONTROLregister (see page 96) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. Only privileged software can write to theCONTROLregister to change the privilege level for software execution in Thread mode. Unprivileged software can use theSVC instruction to make a supervisor call to transfer control to privileged software.

2.3.2 Stacks

The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements March 19, 201182 Texas Instruments-Advance Information The Cortex-M3 Processor

two stacks: the main stack and the process stack, with independent copies of the stack pointer (see the SPregister on page 86). In Thread mode, theCONTROLregister (see page 96) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 83. Table2-1.SummaryofProcessorMode,PrivilegeLevel,andStackUse StackUsedPrivilegeLevelUseProcessorMode Main stack or process stackaPrivileged or unprivilegedaApplicationsThread Main stackAlways privilegedException handlersHandler a. SeeCONTROL(page 96).

2.3.3 RegisterMap

Figure 2-3 on page 83 shows the Cortex-M3 register set. Table 2-2 on page 84 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. Figure2-3.Cortex-M3RegisterSet SP (R13) LR (R14) PC (R15) R 0 R 1 R 3 R 4 R 2 R10 R1 1 R12 L ow registers H igh registers M SP P S P PSR PRIMASK F AUL TMASK BASEPRI CONTROL General-purpose registers Stack Pointer Link Register Program Counter Program status register Exception mask registers CONTROL register Special registers Banked version of SP 83March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table2-2.ProcessorRegisterMap See pageDescriptionResetTypeNameOffset 85Cortex General-Purpose Register 0-R/WR0 - 85Cortex General-Purpose Register 1-R/WR1 - 85Cortex General-Purpose Register 2-R/WR2 - 85Cortex General-Purpose Register 3-R/WR3 - 85Cortex General-Purpose Register 4-R/WR4 - 85Cortex General-Purpose Register 5-R/WR5 - 85Cortex General-Purpose Register 6-R/WR6 - 85Cortex General-Purpose Register 7-R/WR7 - 85Cortex General-Purpose Register 8-R/WR8 - 85Cortex General-Purpose Register 9-R/WR9 - 85Cortex General-Purpose Register 10-R/WR10- 85Cortex General-Purpose Register 11-R/WR11- 85Cortex General-Purpose Register 12-R/WR12- 86Stack Pointer-R/WSP - 87Link Register0xFFFF.FFFFR/WLR - 88Program Counter-R/WPC - 89Program Status Register0x0100.0000R/WPSR- 93Priority Mask Register0x0000.0000R/WPRIMASK- 94Fault Mask Register0x0000.0000R/WFAULTMASK- 95Base Priority Mask Register0x0000.0000R/WBASEPRI- 96Control Register0x0000.0000R/WCONTROL-

2.3.4 RegisterDescriptions

This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 83. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. March 19, 201184 Texas Instruments-Advance Information The Cortex-M3 Processor

Register1:CortexGeneral-PurposeRegister0(R0) Register2:CortexGeneral-PurposeRegister1(R1) Register3:CortexGeneral-PurposeRegister2(R2) Register4:CortexGeneral-PurposeRegister3(R3) Register5:CortexGeneral-PurposeRegister4(R4) Register6:CortexGeneral-PurposeRegister5(R5) Register7:CortexGeneral-PurposeRegister6(R6) Register8:CortexGeneral-PurposeRegister7(R7) Register9:CortexGeneral-PurposeRegister8(R8) Register10:CortexGeneral-PurposeRegister9(R9) Register11:CortexGeneral-PurposeRegister10(R10) Register12:CortexGeneral-PurposeRegister11(R11) Register13:CortexGeneral-PurposeRegister12(R12) The Rnregisters are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type R/W, reset - 16171819202122232425262728293031 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Register data.-R/WDATA31:0 85March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register14:StackPointer(SP) The StackPointer(SP) is register R13. In Thread mode, the function of this register changes depending on theASP bit in theControlRegister(CONTROL) register. When theASP bit is clear, this register is theMainStackPointer(MSP) . When theASP bit is set, this register is theProcess StackPointer(PSP) . On reset, theASP bit is clear, and the processor loads theMSPwith the value from address 0x0000.0000. TheMSPcan only be accessed in privileged mode; thePSPcan be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type R/W, reset - 16171819202122232425262728293031 SP R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 SP R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field This field is the address of the stack pointer.-R/WSP31:0 March 19, 201186 Texas Instruments-Advance Information The Cortex-M3 Processor

Register15:LinkRegister(LR) The LinkRegister(LR ) is register R14, and it stores the return information for subroutines, function calls, and exceptions.LRcan be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded intoLRon exception entry. See Table 2-10 on page 114 for the values and description. Link Register (LR) Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 LINK R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 LINK R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field This field is the return address.0xFFFF.FFFFR/WLINK31:0 87March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register16:ProgramCounter(PC) The ProgramCounter(PC) is register R15, and it contains the current program address. On reset, the processor loads thePCwith the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into theTHUMB bit of theEPSRat reset and must be 1. ThePCregister can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type R/W, reset - 16171819202122232425262728293031 PC R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 PC R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field This field is the current program address.-R/WPC31:0 March 19, 201188 Texas Instruments-Advance Information The Cortex-M3 Processor

Register17:ProgramStatusRegister(PSR) Note: This register is also referred to asxPSR. The ProgramStatusRegister(PSR) has three functions, and the register bits are assigned to the different functions: ■ ApplicationProgramStatusRegister(APSR) , bits 31:27, ■ ExecutionProgramStatusRegister(EPSR) , bits 26:24, 15:10 ■ InterruptProgramStatusRegister(IPSR) , bits 6:0 The PSR, IPSR, andEPSRregisters can only be accessed in privileged mode; theAPSRregister can be accessed in either privileged or unprivileged mode. APSRcontains the current state of the condition flags from previous instruction executions. EPSRcontains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read theEPSRdirectly through application software using theMSR instruction always return zero. Attempts to write theEPSRusing theMSR instruction in application software are always ignored. Fault handlers can examine theEPSRvalue in the stackedPSRto determine the operation that faulted (see “Exception Entry and Return” on page 112). IPSRcontains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to theMSR or MRS instructions. For example, all of the registers can be read usingPSRwith theMRS instruction, orAPSRonly can be written to using APSRwith theMSR instruction. page 89 shows the possible register combinations for thePSR. See the MRS and MSR instruction descriptions in theCortex™-M3 Instruction Set Technical User's Manual for more information about how to access the program status registers. Table2-3.PSRRegisterCombinations CombinationTypeRegister APSR, EPSR, andIPSRR/Wa, bPSR EPSRand IPSRROIEPSR APSRand IPSRR/WaIAPSR APSRand EPSRR/WbEAPSR a. The processor ignores writes to theIPSRbits. b. Reads of theEPSRbits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type R/W, reset 0x0100.0000 16171819202122232425262728293031 reservedTHUMBICI / ITQVCZN ROROROROROROROROROROROR/WR/WR/WR/WR/WType 0000000010000000Reset 0123456789101112131415 ISRNUMreservedICI / IT ROROROROROROROROROROROROROROROROType 0000000000000000Reset 89March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field APSRNegative or Less Flag DescriptionValue The previous operation result was negative or less than.1 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessingPSRor APSR. 0R/WN31 APSRZero Flag DescriptionValue The previous operation result was zero.1 The previous operation result was non-zero.0 The value of this bit is only meaningful when accessingPSRor APSR. 0R/WZ30 APSRCarry or Borrow Flag DescriptionValue The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. The value of this bit is only meaningful when accessingPSRor APSR. 0R/WC29 APSROverflow Flag DescriptionValue The previous operation resulted in an overflow.1 The previous operation did not result in an overflow.0 The value of this bit is only meaningful when accessingPSRor APSR. 0R/WV28 APSRDSP Overflow and Saturation Flag DescriptionValue DSP Overflow or saturation has occurred.1 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessingPSRor APSR. This bit is cleared by software using anMRS instruction. 0R/WQ27 March 19, 201190 Texas Instruments-Advance Information The Cortex-M3 Processor

DescriptionResetTypeNameBit/Field EPSRICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of theIT instruction. When EPSRholds theICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following a 16-bitIT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See theCortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessingPSRor EPSR. 0x0ROICI / IT26:25 EPSRThumb State This bit indicates the Thumb state and should always be set. The following can clear theTHUMB bit: ■ The BLX, BX and POP{PC} instructions ■ Restoration from the stackedxPSRvalue on an exception return ■ Bit 0 of the vector value on an exception entry Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on page 116 for more information. The value of this bit is only meaningful when accessingPSRor EPSR. 1ROTHUMB24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved23:16 EPSRICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of theIT instruction. When an interrupt occurs during the execution of anLDM, STM, PUSH or POP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. WhenEPSRholds the ICI execution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bitIT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See theCortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessingPSRor EPSR. 0x0ROICI / IT15:10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved9:7 91March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field IPSRISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). DescriptionValue Thread mode0x00 Reserved0x01 NMI0x02 Hard fault0x03 Memory management fault0x04 Bus fault0x05 Usage fault0x06 Reserved0x07-0x0A SVCall0x0B Reserved for Debug0x0C Reserved0x0D PendSV0x0E SysTick0x0F Interrupt Vector 00x10 Interrupt Vector 10x11 Interrupt Vector 540x46 Reserved0x47-0x7F See “Exception Types” on page 107 for more information. The value of this field is only meaningful when accessingPSRor IPSR. 0x00ROISRNUM6:0 March 19, 201192 Texas Instruments-Advance Information The Cortex-M3 Processor

Register18:PriorityMaskRegister(PRIMASK) The PRIMASKregister prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. TheMSR and MRS instructions are used to access thePRIMASKregister, and the CPS instruction may be used to change the value of thePRIMASKregister. See theCortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 107. Priority Mask Register (PRIMASK) Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PRIMASKreserved R/WROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Priority Mask DescriptionValue Prevents the activation of all exceptions with configurable priority. No effect.0 0R/WPRIMASK0 93March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register19:FaultMaskRegister(FAULTMASK) The FAULTMASKregister prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. TheMSR and MRS instructions are used to access the FAULTMASKregister, and theCPS instruction may be used to change the value of theFAULTMASK register. See theCortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 107. Fault Mask Register (FAULTMASK) Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 FAULTMASKreserved R/WROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Fault Mask DescriptionValue Prevents the activation of all exceptions except for NMI.1 No effect.0 The processor clears theFAULTMASK bit on exit from any exception handler except the NMI handler. 0R/WFAULTMASK0 March 19, 201194 Texas Instruments-Advance Information The Cortex-M3 Processor

Register20:BasePriorityMaskRegister(BASEPRI) The BASEPRIregister defines the minimum priority for exception processing. WhenBASEPRIis set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as theBASEPRIvalue. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see “Exception Types” on page 107. Base Priority Mask Register (BASEPRI) Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBASEPRIreserved ROROROROROR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. ThePRIMASKregister can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. DescriptionValue All exceptions are unmasked.0x0 All exceptions with priority level 1-7 are masked.0x1 All exceptions with priority level 2-7 are masked.0x2 All exceptions with priority level 3-7 are masked.0x3 All exceptions with priority level 4-7 are masked.0x4 All exceptions with priority level 5-7 are masked.0x5 All exceptions with priority level 6-7 are masked.0x6 All exceptions with priority level 7 are masked.0x7 0x0R/WBASEPRI7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved4:0 95March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register21:ControlRegister(CONTROL) The CONTROLregister controls the stack used and the privilege level for software execution when the processor is in Thread mode. This register is only accessible in privileged mode. Handler mode always usesMSP, so the processor ignores explicit writes to theASP bit of the CONTROLregister when in Handler mode. The exception entry and return mechanisms automatically update theCONTROLregister based on the EXC_RETURN value (see Table 2-10 on page 114). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode usesMSP. To switch the stack pointer used in Thread mode toPSP, either use theMSR instruction to set theASP bit, as detailed in theCortex™-M3 Instruction Set Technical User's Manual, or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 114. Note: When changing the stack pointer, software must use anISB instruction immediately after the MSR instruction, ensuring that instructions after theISB execute use the new stack pointer. See theCortex™-M3 Instruction Set Technical User's Manual. Control Register (CONTROL) Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TMPLASPreserved R/WR/WROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:2 Active Stack Pointer DescriptionValue PSPis the current stack pointer.1 MSPis the current stack pointer0 In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. 0R/WASP1 Thread Mode Privilege Level DescriptionValue Unprivileged software can be executed in Thread mode.1 Only privileged software can be executed in Thread mode.0 0R/WTMPL0 March 19, 201196 Texas Instruments-Advance Information The Cortex-M3 Processor

2.3.5 ExceptionsandInterrupts

The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 112 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” on page 122 for more information.

2.3.6 DataTypes

The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See “Memory Regions, Types and Attributes” on page 99 for more information.

2.4 MemoryModel

This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the LM3S9B92 controller is provided in Table 2-4 on page 97. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see “Bit-Banding” on page 102). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see “Cortex-M3 Peripherals” on page 121). Note: Within the memory map, all reserved space returns a bus fault when read or written. Table2-4.MemoryMap Fordetails, seepage... DescriptionEndStart Memory 305On-chip Flash0x0003.FFFF0x0000.0000 -Reserved0x00FF.FFFF0x0004.0000 303Reserved for ROM0x1FFF.FFFF0x0100.0000 303Bit-banded on-chip SRAM0x2001.7FFF0x2000.0000 -Reserved0x21FF.FFFF0x2001.8000 303Bit-band alias of 0x2000.0000 through 0x200F.FFFF0x222F.FFFF0x2200.0000 -Reserved0x3FFF.FFFF0x2230.0000 FiRMPeripherals 575Watchdog timer 00x4000.0FFF0x4000.0000 575Watchdog timer 10x4000.1FFF0x4000.1000 -Reserved0x4000.3FFF0x4000.2000 410GPIO Port A0x4000.4FFF0x4000.4000 410GPIO Port B0x4000.5FFF0x4000.5000 410GPIO Port C0x4000.6FFF0x4000.6000 97March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table2-4.MemoryMap (continued) Fordetails, seepage... DescriptionEndStart 410GPIO Port D0x4000.7FFF0x4000.7000 752SSI00x4000.8FFF0x4000.8000 752SSI10x4000.9FFF0x4000.9000 -Reserved0x4000.BFFF0x4000.A000 689UART00x4000.CFFF0x4000.C000 689UART10x4000.DFFF0x4000.D000 689UART20x4000.EFFF0x4000.E000 -Reserved0x4001.FFFF0x4000.F000 Peripherals 796I2C 00x4002.0FFF0x4002.0000 796I2C 10x4002.1FFF0x4002.1000 -Reserved0x4002.3FFF0x4002.2000 410GPIO Port E0x4002.4FFF0x4002.4000 410GPIO Port F0x4002.5FFF0x4002.5000 410GPIO Port G0x4002.6FFF0x4002.6000 410GPIO Port H0x4002.7FFF0x4002.7000 1128PWM0x4002.8FFF0x4002.8000 -Reserved0x4002.BFFF0x4002.9000 1197QEI00x4002.CFFF0x4002.C000 1197QEI10x4002.DFFF0x4002.D000 -Reserved0x4002.FFFF0x4002.E000 541Timer 00x4003.0FFF0x4003.0000 541Timer 10x4003.1FFF0x4003.1000 541Timer 20x4003.2FFF0x4003.2000 541Timer 30x4003.3FFF0x4003.3000 -Reserved0x4003.7FFF0x4003.4000 618ADC00x4003.8FFF0x4003.8000 618ADC10x4003.9FFF0x4003.9000 -Reserved0x4003.BFFF0x4003.A000 1101Analog Comparators0x4003.CFFF0x4003.C000 410GPIO Port J0x4003.DFFF0x4003.D000 -Reserved0x4003.FFFF0x4003.E000 873CAN0 Controller0x4004.0FFF0x4004.0000 873CAN1 Controller0x4004.1FFF0x4004.1000 -Reserved0x4004.7FFF0x4004.2000 916Ethernet Controller0x4004.8FFF0x4004.8000 -Reserved0x4004.FFFF0x4004.9000 989USB0x4005.0FFF0x4005.0000 -Reserved0x4005.3FFF0x4005.1000 829I2S00x4005.4FFF0x4005.4000 -Reserved0x4005.7FFF0x4005.5000 March 19, 201198 Texas Instruments-Advance Information The Cortex-M3 Processor

Table2-4.MemoryMap (continued) Fordetails, seepage... DescriptionEndStart 410GPIO Port A (AHB aperture)0x4005.8FFF0x4005.8000 410GPIO Port B (AHB aperture)0x4005.9FFF0x4005.9000 410GPIO Port C (AHB aperture)0x4005.AFFF0x4005.A000 410GPIO Port D (AHB aperture)0x4005.BFFF0x4005.B000 410GPIO Port E (AHB aperture)0x4005.CFFF0x4005.C000 410GPIO Port F (AHB aperture)0x4005.DFFF0x4005.D000 410GPIO Port G (AHB aperture)0x4005.EFFF0x4005.E000 410GPIO Port H (AHB aperture)0x4005.FFFF0x4005.F000 410GPIO Port J (AHB aperture)0x4006.0FFF0x4006.0000 -Reserved0x400C.FFFF0x4006.1000 484EPI 00x400D.0FFF0x400D.0000 -Reserved0x400F.CFFF0x400D.1000 311Flash memory control0x400F.DFFF0x400F.D000 216System control0x400F.EFFF0x400F.E000 360µDMA0x400F.FFFF0x400F.F000 -Reserved0x41FF.FFFF0x4010.0000 -Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000 -Reserved0x5FFF.FFFF0x4400.0000 -EPI0 mapped peripheral and RAM0xDFFF.FFFF0x6000.0000 PrivatePeripheralBus 80Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000 80Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000 80Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000 -Reserved0xE000.DFFF0xE000.3000 106Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU)0xE000.EFFF0xE000.E000 -Reserved0xE003.FFFF0xE000.F000 81Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000 -Reserved0xFFFF.FFFF0xE004.1000

2.4.1 MemoryRegions,TypesandAttributes

The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: ■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. 99March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region.

2.4.2 MemorySystemOrderingofMemoryAccesses

For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see “Software Ordering of Memory Accesses” on page 101). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2.

2.4.3 BehaviorofMemoryAccesses

Table 2-5 on page 100 shows the behavior of accesses to each region in the memory map. See “Memory Regions, Types and Attributes” on page 99 for more information on memory types and the XN attribute. Stellaris devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 97 for more information). Table2-5.MemoryAccessBehavior DescriptionExecute Never (XN) MemoryTypeMemoryRegionAddressRange This executable region is for program code. Data can also be stored here. -NormalCode0x0000.0000 - 0x1FFF.FFFF This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 102). -NormalSRAM0x2000.0000 - 0x3FFF.FFFF This region includes bit band and bit band alias areas (see Table 2-7 on page 102). XNDevicePeripheral0x4000.0000 - 0x5FFF.FFFF This executable region is for data.-NormalExternal RAM0x6000.0000 - 0x9FFF.FFFF This region is for external device memory.XNDeviceExternal device0xA000.0000 - 0xDFFF.FFFF This region includes the NVIC, system timer, and system control block. XNStrongly Ordered Private peripheral bus 0xE000.0000- 0xE00F.FFFF ---Reserved0xE010.0000- 0xFFFF.FFFF The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M3 has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” on page 124. The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. March 19, 2011100 Texas Instruments-Advance Information The Cortex-M3 Processor

2.4.4 SoftwareOrderingofMemoryAccesses

The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ■ The processor has multiple bus interfaces. ■ Memory or devices in the memory map have different wait states. ■ Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” on page 100 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M3 has the following memory barrier instructions: ■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. ■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Memory barrier instructions can be used in the following situations: ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use aDSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. – Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. ■ Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use aDMB instruction between the operations. TheDMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. ■ Self-modifying code If a program contains self-modifying code, use anISB instruction immediately after the code modification in the program. TheISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching 101March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

If the system contains a memory map switching mechanism, use aDSB instruction after switching the memory map in the program. TheDSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, useDSB instructions after the change. The change then takes effect on completion of theDSB instruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use ofDMB instructions. For more information on the memory barrier instructions, see theCortex™-M3 Instruction Set Technical User's Manual.

2.4.5 Bit-Banding

A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 102. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 102. For the specific address range of the bit-band regions, see Table 2-4 on page 97. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. Table2-6.SRAMMemoryBit-BandingRegions InstructionandDataAccessesMemoryRegionAddressRange Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. SRAM bit-band region0x2000.0000 - 0x200F.FFFF Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. SRAM bit-band alias0x2200.0000 - 0x23FF.FFFF Table2-7.PeripheralMemoryBit-BandingRegions InstructionandDataAccessesMemoryRegionAddressRange Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band region0x4000.0000 - 0x400F.FFFF Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Peripheral bit-band alias0x4200.0000 - 0x43FF.FFFF The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset March 19, 2011102 Texas Instruments-Advance Information The Cortex-M3 Processor

where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 104 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: ■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) ■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 103March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure2-4.Bit-BandMapping 0x23FF .FFE4 0x2200.0004 32-MB Alias Region 7 0 0x2000.00000x2000.00010x2000.00020x2000.0003 6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1 07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1 0x200F .FFFC0x200F .FFFD0x200F .FFFE0x200F .FFFF 1-MB SRAM Bit-Band Region

2.4.5.1 DirectlyAccessinganAliasRegion

Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.

2.4.5.2 DirectlyAccessingaBit-BandRegion

“Behavior of Memory Accesses” on page 100 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions.

2.4.6 DataStorage

The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 105 illustrates how data is stored. March 19, 2011104 Texas Instruments-Advance Information The Cortex-M3 Processor

Figure2-5.DataStorage Memory Register Address A A+1 lsbyte msbyte A+2 A+3 B0B1B3 B2 31 24 23 16 15 8 7 0

2.4.7 SynchronizationPrimitives

The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: ■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. ■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write is performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: ■ The word instructionsLDREX and STREX ■ The halfword instructionsLDREXH and STREXH ■ The byte instructionsLDREXB and STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and test the returned status bit. If the status bit is clear, the read-modify-write completed successfully; if the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 105March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

1. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: ■ It executes aCLREX instruction. ■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds. ■ An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see theCortex™-M3 Instruction Set Technical User's Manual.

2.5 ExceptionModel

The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 108 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 53 interrupts (listed in Table 2-9 on page 109). Priorities on the system handlers are set with the NVICSystemHandlerPriorityn(SYSPRIn) registers. Interrupts are enabled through the NVICInterruptSetEnablen(ENn) register and prioritized with the NVICInterruptPriorityn(PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in “Nested Vectored Interrupt Controller (NVIC)” on page 122. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 122 for more information on exceptions and interrupts.

2.5.1 ExceptionStates

Each exception is in one of the following states: March 19, 2011106 Texas Instruments-Advance Information The Cortex-M3 Processor

■ Inactive.The exception is not active and not pending. ■ Pending.The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. ■ Active.An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. ■ ActiveandPending. The exception is being serviced by the processor, and there is a pending exception from the same source.

2.5.2 ExceptionTypes

The exception types are: ■ Reset.Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. ■ NMI.A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using theInterruptControlandState(INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. ■ HardFault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. ■ MemoryManagementFault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. ■ BusFault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. ■ UsageFault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return 107March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall.A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. ■ DebugMonitor.This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. ■ PendSV.PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using theInterruptControlandState(INTCTRL) register. ■ SysTick.A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using theInterruptControlandState(INTCTRL) register. In an OS environment, the processor can use this exception as system tick. ■ Interrupt(IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 109 lists the interrupts on the LM3S9B92 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 108 shows as having configurable priority (see theSYSHNDCTRLregister on page 165 and theDIS0register on page 138). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 114. Table2-8.ExceptionTypes ActivationVectorAddressor Offsetb PriorityaVector Number ExceptionType Stack top is loaded from the first entry of the vector table on reset. 0x0000.0000-0- Asynchronous0x0000.0004-3 (highest)1Reset Asynchronous0x0000.0008-22Non-Maskable Interrupt (NMI) -0x0000.000C-13Hard Fault Synchronous0x0000.0010programmablec4Memory Management Synchronous when precise and asynchronous when imprecise 0x0000.0014programmablec5Bus Fault Synchronous0x0000.0018programmablec6Usage Fault Reserved--7-10- Synchronous0x0000.002Cprogrammablec11SVCall Synchronous0x0000.0030programmablec12Debug Monitor Reserved--13- Asynchronous0x0000.0038programmablec14PendSV March 19, 2011108 Texas Instruments-Advance Information The Cortex-M3 Processor

Table2-8.ExceptionTypes (continued) ActivationVectorAddressor Offsetb PriorityaVector Number ExceptionType Asynchronous0x0000.003Cprogrammablec15SysTick Asynchronous0x0000.0040 and aboveprogrammabled16 and aboveInterrupts a. 0 is the default priority for all the programmable priorities. b. See “Vector Table” on page 110. c. SeeSYSPRI1on page 162. d. SeePRInregisters on page 146. Table2-9.Interrupts DescriptionVectorAddressor Offset InterruptNumber(Bit inInterruptRegisters) VectorNumber Processor exceptions0x0000.0000 - 0x0000.003C -0-15 GPIO Port A0x0000.0040016 GPIO Port B0x0000.0044117 GPIO Port C0x0000.0048218 GPIO Port D0x0000.004C319 GPIO Port E0x0000.0050420 UART00x0000.0054521 UART10x0000.0058622 SSI00x0000.005C723 I2C00x0000.0060824 PWM Fault0x0000.0064925 PWM Generator 00x0000.00681026 PWM Generator 10x0000.006C1127 PWM Generator 20x0000.00701228 QEI00x0000.00741329 ADC0 Sequence 00x0000.00781430 ADC0 Sequence 10x0000.007C1531 ADC0 Sequence 20x0000.00801632 ADC0 Sequence 30x0000.00841733 Watchdog Timers 0 and 10x0000.00881834 Timer 0A0x0000.008C1935 Timer 0B0x0000.00902036 Timer 1A0x0000.00942137 Timer 1B0x0000.00982238 Timer 2A0x0000.009C2339 Timer 2B0x0000.00A02440 Analog Comparator 00x0000.00A42541 Analog Comparator 10x0000.00A82642 Analog Comparator 20x0000.00AC2743 System Control0x0000.00B02844 Flash Memory Control0x0000.00B42945 109March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table2-9.Interrupts (continued) DescriptionVectorAddressor Offset InterruptNumber(Bit inInterruptRegisters) VectorNumber GPIO Port F0x0000.00B83046 GPIO Port G0x0000.00BC3147 GPIO Port H0x0000.00C03248 UART20x0000.00C43349 SSI10x0000.00C83450 Timer 3A0x0000.00CC3551 Timer 3B0x0000.00D03652 I2C10x0000.00D43753 QEI10x0000.00D83854 CAN00x0000.00DC3955 CAN10x0000.00E04056 Reserved-4157 Ethernet Controller0x0000.00E84258 Reserved-4359 USB0x0000.00F04460 PWM Generator 30x0000.00F44561 µDMA Software0x0000.00F84662 µDMA Error0x0000.00FC4763 ADC1 Sequence 00x0000.01004864 ADC1 Sequence 10x0000.01044965 ADC1 Sequence 20x0000.01085066 ADC1 Sequence 30x0000.010C5167 I2S00x0000.01105268 EPI0x0000.01145369 GPIO Port J0x0000.01185470

2.5.3 ExceptionHandlers

The processor handles exceptions using: ■ InterruptServiceRoutines(ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ FaultHandlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. ■ SystemHandlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers.

2.5.4 VectorTable

The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 108. Figure 2-6 on page 111 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code March 19, 2011110 Texas Instruments-Advance Information The Cortex-M3 Processor

Figure2-6.Vectortable Initial SP value Reset Hard fault NMI Memory management fault Usage fault Bus fault 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 Reserved SVCall PendSV Reserved for Debug Systick IRQ0 Reserved 0x002C 0x0038 0x003C 0x0040 Of fsetException number 1 1 V ector IRQ1 IRQ2 0x0044 IRQ54 0x0048 0x004C 0x01 18 IRQ number -14 -13 -12 -1 1 -10 On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the VectorTableOffset(VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0200 to 0x3FFF.FE00 (see “Vector Table” on page 110). Note that when configuring theVTABLEregister, the offset must be aligned on a 512-byte boundary.

2.5.5 ExceptionPriorities

As Table 2-8 on page 108 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 162 and page 146. Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. 111March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.

2.5.6 InterruptPriorityGrouping

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: ■ An upper field that defines the group priority ■ A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 156.

2.5.7 ExceptionEntryandReturn

Descriptions of exception handling use the following terms: ■ Preemption.When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” on page 112 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 113 more information. ■ Return.Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 113 for more information. ■ Tail-Chaining.This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ■ Late-Arriving.This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On March 19, 2011112 Texas Instruments-Advance Information The Cortex-M3 Processor

return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.

2.5.7.1 ExceptionEntry

Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASKon page 93,FAULTMASKon page 94, andBASEPRIon page 95). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to asstack frame. Figure2-7.ExceptionStackFrame Pre-IRQ top of stack x PSR PC LR R 12 R 3 R 2 R 1 {aligner} IRQ top of stack ... Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to thePCat exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to theLR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception.

2.5.7.2 ExceptionReturn

Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into thePC: ■ An LDM or POP instruction that loads thePC 113March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ A BX instruction using any register ■ An LDR instruction with thePCas the destination EXC_RETURN is the value loaded into theLRon exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 2-10 on page 114 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:4 are all set. When this value is loaded into thePC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table2-10.ExceptionReturnBehavior DescriptionEXC_RETURN[31:0] Reserved0xFFFF.FFF0 Return to Handler mode. Exception return uses state fromMSP. Execution usesMSPafter return. 0xFFFF.FFF1 Reserved0xFFFF.FFF2 - 0xFFFF.FFF8 Return to Thread mode. Exception return uses state fromMSP. Execution usesMSPafter return. 0xFFFF.FFF9 Reserved0xFFFF.FFFA - 0xFFFF.FFFC Return to Thread mode. Exception return uses state fromPSP. Execution usesPSPafter return. 0xFFFF.FFFD Reserved0xFFFF.FFFE - 0xFFFF.FFFF

2.6 FaultHandling

Faults are a subset of the exceptions (see “Exception Model” on page 106). The following conditions generate a fault: ■ A bus error on an instruction fetch or vector table load or a data access. ■ An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.

2.6.1 FaultTypes

Table 2-11 on page 114 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 169 for more information about the fault status registers. Table2-11.Faults BitNameFaultStatusRegisterHandlerFault VECTHardFaultStatus(HFAULTSTAT)Hard faultBus error on a vector read FORCEDHardFaultStatus(HFAULTSTAT)Hard faultFault escalated to a hard fault March 19, 2011114 Texas Instruments-Advance Information The Cortex-M3 Processor

Table2-11.Faults (continued) BitNameFaultStatusRegisterHandlerFault IERR aMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on instruction access DERRMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on data access MSTKEMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on exception stacking MUSTKEMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on exception unstacking BSTKEBusFaultStatus(BFAULTSTAT)Bus faultBus error during exception stacking BUSTKEBusFaultStatus(BFAULTSTAT)Bus faultBus error during exception unstacking IBUSBusFaultStatus(BFAULTSTAT)Bus faultBus error during instruction prefetch PRECISEBusFaultStatus(BFAULTSTAT)Bus faultPrecise data bus error IMPREBusFaultStatus(BFAULTSTAT)Bus faultImprecise data bus error NOCPUsageFaultStatus(UFAULTSTAT)Usage faultAttempt to access a coprocessor UNDEFUsageFaultStatus(UFAULTSTAT)Usage faultUndefined instruction INVSTATUsageFaultStatus(UFAULTSTAT)Usage faultAttempt to enter an invalid instruction set stateb INVPCUsageFaultStatus(UFAULTSTAT)Usage faultInvalid EXC_RETURN value UNALIGNUsageFaultStatus(UFAULTSTAT)Usage faultIllegal unaligned load or store DIV0UsageFaultStatus(UFAULTSTAT)Usage faultDivide by 0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation.

2.6.2 FaultEscalationandHardFaults

All fault exceptions except for hard fault have configurable exception priority (seeSYSPRI1on page 162). Software can disable execution of the handlers for these faults (seeSYSHNDCTRLon page 165). Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 106. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described asescalated to hard fault . Escalation to hard fault occurs when: ■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. ■ A fault occurs and the handler for that fault is not enabled. 115March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault.

2.6.3 FaultStatusRegistersandFaultAddressRegisters

The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 116. Table2-12.FaultStatusandFaultAddressRegisters RegisterDescriptionAddressRegisterNameStatusRegisterNameHandler page 175-HardFaultStatus(HFAULTSTAT)Hard fault page 169 page 176 MemoryManagementFault Address(MMADDR) MemoryManagementFaultStatus (MFAULTSTAT) Memory management fault page 169 page 177 BusFaultAddress (FAULTADDR) BusFaultStatus(BFAULTSTAT)Bus fault page 169-UsageFaultStatus(UFAULTSTAT)Usage fault

2.6.4 Lockup

The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset or an NMI occurs. Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state.

2.7 PowerManagement

The Cortex-M3 processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of theSystemControl(SYSCTRL) register selects which sleep mode is used (see page 158). For more information about the behavior of the sleep modes, see “System Control” on page 213. This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.

2.7.1 EnteringSleepModes

This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. March 19, 2011116 Texas Instruments-Advance Information The Cortex-M3 Processor

2.7.1.1 WaitforInterrupt

The wait for interrupt instruction,WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 117). When the processor executes aWFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M3 Instruction Set Technical User's Manual for more information.

2.7.1.2 WaitforEvent

The wait for event instruction,WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes aWFE instruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of aWFE instruction. Typically, this situation occurs if anSEV instruction has been executed. Software cannot access this register directly. See theCortex™-M3 Instruction Set Technical User's Manual for more information.

2.7.1.3 Sleep-on-Exit

If theSLEEPEXIT bit of theSYSCTRLregister is set, when the processor completes the execution of an exception handler, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs.

2.7.2 WakeUpfromSleepMode

The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.

2.7.2.1 WakeUpfromWFIorSleep-on-Exit

Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting thePRIMASK bit and clearing theFAULTMASK bit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clearsPRIMASK. For more information about PRIMASKand FAULTMASK, see page 93 and page 94.

2.7.2.2 WakeUpfromWFE

The processor wakes up if it detects an exception with sufficient priority to cause exception entry. In addition, if theSEVONPEND bit in theSYSCTRLregister is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information aboutSYSCTRL, see page 158.

2.8 InstructionSetSummary

The processor implements a version of the Thumb instruction set. Table 2-13 on page 118 lists the supported instructions. Note: In Table 2-13 on page 118: ■ Angle brackets, <>, enclose alternative forms of the operand 117March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ Braces, {}, enclose optional operands ■ The Operands column is not exhaustive ■ Op2 is a flexible second operand that can be either a register or a constant ■ Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual. Table2-13.Cortex-M3InstructionSummary FlagsBriefDescriptionOperandsMnemonic N,Z,C,VAdd with carry{Rd,} Rn, Op2ADC, ADCS N,Z,C,VAdd{Rd,} Rn, Op2ADD, ADDS N,Z,C,VAdd{Rd,} Rn , #imm12ADD, ADDW -Load PC-relative addressRd, labelADR N,Z,CLogical AND{Rd,} Rn, Op2AND, ANDS N,Z,CArithmetic shift rightRd, Rm, <Rs|#n>ASR, ASRS -BranchlabelB -Bit field clearRd, #lsb, #widthBFC -Bit field insertRd, Rn, #lsb, #widthBFI N,Z,CBit clear{Rd,} Rn, Op2BIC, BICS -Breakpoint#immBKPT -Branch with linklabelBL -Branch indirect with linkRmBLX -Branch indirectRmBX -Compare and branch if non-zeroRn, labelCBNZ -Compare and branch if zeroRn, labelCBZ -Clear exclusive-CLREX -Count leading zerosRd, RmCLZ N,Z,C,VCompare negativeRn, Op2CMN N,Z,C,VCompareRn, Op2CMP -Change processor state, disable interrupts iCPSID -Change processor state, enable interrupts iCPSIE -Data memory barrier-DMB -Data synchronization barrier-DSB N,Z,CExclusive OR{Rd,} Rn, Op2EOR, EORS -Instruction synchronization barrier-ISB -If-Then condition block-IT -Load multiple registers, increment afterRn{!}, reglistLDM -Load multiple registers, decrement before Rn{!}, reglistLDMDB, LDMEA -Load multiple registers, increment afterRn{!}, reglistLDMFD, LDMIA -Load register with wordRt, [Rn, #offset]LDR -Load register with byteRt, [Rn, #offset]LDRB, LDRBT -Load register with two bytesRt, Rt2, [Rn, #offset]LDRD March 19, 2011118 Texas Instruments-Advance Information The Cortex-M3 Processor

Table2-13.Cortex-M3InstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic -Load register exclusiveRt, [Rn, #offset]LDREX -Load register exclusive with byteRt, [Rn]LDREXB -Load register exclusive with halfwordRt, [Rn]LDREXH -Load register with halfwordRt, [Rn, #offset]LDRH, LDRHT -Load register with signed byteRt, [Rn, #offset]LDRSB, LDRSBT -Load register with signed halfwordRt, [Rn, #offset]LDRSH, LDRSHT -Load register with wordRt, [Rn, #offset]LDRT N,Z,CLogical shift leftRd, Rm, <Rs|#n>LSL, LSLS N,Z,CLogical shift rightRd, Rm, <Rs|#n>LSR, LSRS -Multiply with accumulate, 32-bit resultRd, Rn, Rm, RaMLA -Multiply and subtract, 32-bit resultRd, Rn, Rm, RaMLS N,Z,CMoveRd, Op2MOV, MOVS N,Z,CMove 16-bit constantRd, #imm16MOV, MOVW -Move topRd, #imm16MOVT -Move from special register to general register Rd, spec_regMRS N,Z,C,VMove from general register to special register MSR N,ZMultiply, 32-bit result{Rd,} Rn, RmMUL, MULS N,Z,CMove NOTRd, Op2MVN, MVNS -No operation-NOP N,Z,CLogical OR NOT{Rd,} Rn, Op2ORN, ORNS N,Z,CLogical OR{Rd,} Rn, Op2ORR, ORRS -Pop registers from stackreglistPOP -Push registers onto stackreglistPUSH -Reverse bitsRd, RnRBIT -Reverse byte order in a wordRd, RnREV -Reverse byte order in each halfwordRd, RnREV16 -Reverse byte order in bottom halfword and sign extend Rd, RnREVSH N,Z,CRotate rightRd, Rm, <Rs|#n>ROR, RORS N,Z,CRotate right with extendRd, RmRRX, RRXS N,Z,C,VReverse subtract{Rd,} Rn, Op2RSB, RSBS N,Z,C,VSubtract with carry{Rd,} Rn, Op2SBC, SBCS -Signed bit field extractRd, Rn, #lsb, #widthSBFX -Signed divide{Rd,} Rn, RmSDIV -Send event-SEV -Signed multiply with accumulate (32x32+64), 64-bit result RdLo, RdHi, Rn, RmSMLAL -Signed multiply (32x32), 64-bit resultRdLo, RdHi, Rn, RmSMULL QSigned saturateRd, #n, Rm {,shift #s}SSAT -Store multiple registers, increment afterRn{!}, reglistSTM 119March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table2-13.Cortex-M3InstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic -Store multiple registers, decrement before Rn{!}, reglistSTMDB, STMEA -Store multiple registers, increment afterRn{!}, reglistSTMFD, STMIA -Store register wordRt, [Rn {, #offset}]STR -Store register byteRt, [Rn {, #offset}]STRB, STRBT -Store register two wordsRt, Rt2, [Rn {, #offset}]STRD -Store register exclusiveRt, Rt, [Rn {, #offset}]STREX -Store register exclusive byteRd, Rt, [Rn]STREXB -Store register exclusive halfwordRd, Rt, [Rn]STREXH -Store register halfwordRt, [Rn {, #offset}]STRH, STRHT -Store register signed byteRt, [Rn {, #offset}]STRSB, STRSBT -Store register signed halfwordRt, [Rn {, #offset}]STRSH, STRSHT -Store register wordRt, [Rn {, #offset}]STRT N,Z,C,VSubtract{Rd,} Rn, Op2SUB, SUBS N,Z,C,VSubtract 12-bit constant{Rd,} Rn, #imm12SUB, SUBW -Supervisor call#immSVC -Sign extend a byte{Rd,} Rm {,ROR #n}SXTB -Sign extend a halfword{Rd,} Rm {,ROR #n}SXTH -Table branch byte[Rn, Rm]TBB -Table branch halfword[Rn, Rm, LSL #1]TBH N,Z,CTest equivalenceRn, Op2TEQ N,Z,CTestRn, Op2TST -Unsigned bit field extractRd, Rn, #lsb, #widthUBFX -Unsigned divide{Rd,} Rn, RmUDIV -Unsigned multiply with accumulate (32x32+32+32), 64-bit result RdLo, RdHi, Rn, RmUMLAL -Unsigned multiply (32x 2), 64-bit resultRdLo, RdHi, Rn, RmUMULL QUnsigned SaturateRd, #n, Rm {,shift #s}USAT -Zero extend a Byte{Rd,} Rm, {,ROR #n}UXTB -Zero extend a Halfword{Rd,} Rm, {,ROR #n}UXTH QUnsigned saturateRd, #n, Rm {,shift #s}USAT -Zero extend a byte{Rd,} Rm {,ROR #n}UXTB -Zero extend a halfword{Rd,} Rm {,ROR #n}UXTH -Wait for event-WFE -Wait for interrupt-WFI March 19, 2011120 Texas Instruments-Advance Information The Cortex-M3 Processor

3 Cortex-M3Peripherals

This chapter provides information on the Stellaris® implementation of the Cortex-M3 processor peripherals, including: ■ SysTick (see page 121) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. ■ Nested Vectored Interrupt Controller (NVIC) (see page 122) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers ■ System Control Block (SCB) (see page 124) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. ■ Memory Protection Unit (MPU) (see page 124) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. Table 3-1 on page 121 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table3-1.CorePeripheralRegisterRegions Description(seepage...)CorePeripheralAddress 121System Timer0xE000.E010-0xE000.E01F 122Nested Vectored Interrupt Controller0xE000.E100-0xE000.E4EF 0xE000.EF00-0xE000.EF03 124System Control Block0xE000.E008-0xE000.E00F 0xE000.ED00-0xE000.ED3F 124Memory Protection Unit0xE000.ED90-0xE000.EDB8

3.1 FunctionalDescription

This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals: SysTick, NVIC, SCB and MPU.

3.1.1 SystemTimer(SysTick)

Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. 121March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. TheCOUNT bit in the STCTRLcontrol and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: ■ SysTickControlandStatus(STCTRL) : A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ SysTickReloadValue(STRELOAD) : The reload value for the counter, used to provide the counter's wrap value. ■ SysTickCurrentValue(STCURRENT) : The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in theSTRELOADregister on the next clock edge, then decrements on subsequent clocks. Clearing theSTRELOADregister disables the counter on the next wrap. When the counter reaches zero, theCOUNT status bit is set. TheCOUNT bit clears on reads. Writing to theSTCURRENTregister clears the register and theCOUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. Note: When the processor is halted for debugging, the counter does not decrement.

3.1.2 NestedVectoredInterruptController(NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 53 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). March 19, 2011122 Texas Instruments-Advance Information Cortex-M3 Peripherals

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling.

3.1.2.1 Level-SensitiveandPulseInterrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 123 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing.

3.1.2.2 HardwareandSoftwareControlofInterrupts

The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: ■ The NVIC detects that the interrupt signal is High and the interrupt is not active. ■ The NVIC detects a rising edge on the interrupt signal. ■ Software writes to the corresponding interrupt set-pending register bit, or to theSoftwareTrigger Interrupt(SWTRIG) register to make a Software-Generated Interrupt pending. See theINT bit in thePEND0register on page 140 orSWTRIGon page 148. A pending interrupt remains pending until one of the following: ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 123March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending.

3.1.3 SystemControlBlock(SCB)

The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions.

3.1.4 MemoryProtectionUnit(MPU)

This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 99 for more information). Table 3-2 on page 124 shows the possible MPU region attributes. See the section called “MPU Configuration for a Stellaris Microcontroller” on page 128 for guidelines for programming a microcontroller implementation. Table3-2.MemoryAttributesSummary DescriptionMemoryType All accesses to Strongly Ordered memory occur in program order.Strongly Ordered Memory-mapped peripheralsDevice Normal memoryNormal To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: ■ Except for theMPURegionAttributeandSize(MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTRregister can be accessed with byte or aligned halfword or word accesses. March 19, 2011124 Texas Instruments-Advance Information Cortex-M3 Peripherals

The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup.

3.1.4.1 UpdatinganMPURegion

To update the attributes for an MPU region, theMPURegionNumber(MPUNUMBER) , MPU RegionBaseAddress(MPUBASE) and MPUATTRregisters must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use theMPUBASExand MPUATTRxaliases to program up to four regions simultaneously using an STM instruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R4, [R0, #0x4] ; Region Base Address STRH R2, [R0, #0x8] ; Region Size and Enable STRH R3, [R0, #0xA] ; Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable STRH R2, [R0, #0x8] ; Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. ■ After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. 125March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then aDSB instruction and anISB instruction should be used. ADSB is required after changing MPU settings, such as at the end of context switch. AnISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for pre-packed information, meaning that theMPURegion BaseAddress(MPUBASE) register (see page 182) contains the required region number and has the VALID bit set. This method can be used when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPUBASE ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in theSRD field of theMPURegionAttributeandSize(MPUATTR) register (see page 184) to disable a subregion. The least-significant bit of theSRD field controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region March 19, 2011126 Texas Instruments-Advance Information Cortex-M3 Peripherals

overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, theSRD field must be configured to0x00, otherwise the MPU behavior is unpredictable. Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure theSRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 127 shows. Figure3-1.SRDUseExample Region 1 Disabled subregion Disabled subregion Region 2, with subregions Base address of both regions Of fset from base address 64KB 128KB 192KB 256KB 320KB 384KB 448KB 512KB3.1.4.2 MPUAccessPermissionAttributes The access permission bits,TEX, S, C, B, AP, andXN of theMPUATTRregister, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 127 shows the encodings for theTEX, C, B, andS access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Stellaris Microcontroller” on page 128 for information on programming the MPU for Stellaris implementations. Table3-3.TEX,S,C,andBBitFieldEncoding OtherAttributesShareabilityMemoryTypeB CSTEX -ShareableStrongly Ordered0 0xa000b -ShareableDevice1 0xa000 Outer and inner write-through. No write allocate. Not shareableNormal0 10000 ShareableNormal0 11000 Not shareableNormal1 10000 ShareableNormal1 11000 Outer and inner noncacheable. Not shareableNormal0 00001 ShareableNormal0 01001 --Reserved encoding1 0xa001 --Reserved encoding0 1xa001 Outer and inner write-back. Write and read allocate. Not shareableNormal1 10001 ShareableNormal1 11001 127March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table3-3.TEX,S,C,andBBitFieldEncoding (continued) OtherAttributesShareabilityMemoryTypeB CSTEX Nonshared Device.Not shareableDevice0 0xa010 --Reserved encoding1 0xa010 --Reserved encodingxa1xa010 Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. Not shareableNormalA A01BB ShareableNormalA A11BB a. The MPU ignores the value of this bit. Table 3-4 on page 128 shows the cache policy for memory attribute encodings with aTEX value in the range of 0x4-0x7. Table3-4.CachePolicyforMemoryAttributeEncoding CorrespondingCachePolicyEncoding,AAorBB Non-cacheable00 Write back, write and read allocate01 Write through, no write allocate10 Write back, no write allocate11 Table 3-5 on page 128 shows theAP encodings in theMPUATTRregister that define the access permissions for privileged and unprivileged software. Table3-5.APBitFieldEncoding DescriptionUnprivileged Permissions Privileged Permissions AP BitField All accesses generate a permission fault.No accessNo access000 Access from privileged software only.No accessR/W001 Writes by unprivileged software generate a permission fault. ROR/W010 Full access.R/WR/W011 Reserved.UnpredictableUnpredictable100 Reads by privileged software only.No accessRO101 Read-only, by privileged or unprivileged software.RORO110 Read-only, by privileged or unprivileged software.RORO111 MPU Configuration for a Stellaris Microcontroller Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 128. Table3-6.MemoryRegionAttributesforStellarisMicrocontrollers MemoryTypeandAttributesB C STEXMemoryRegion Normal memory, non-shareable, write-through0 1 0000bFlash memory Normal memory, shareable, write-through0 1 1000bInternal SRAM March 19, 2011128 Texas Instruments-Advance Information Cortex-M3 Peripherals

Table3-6.MemoryRegionAttributesforStellarisMicrocontrollers (continued) MemoryTypeandAttributesB C STEXMemoryRegion Normal memory, shareable, write-back, write-allocate 1 1 1000bExternal SRAM Device memory, shareable1 0 1000bPeripherals In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations.

3.1.4.3 MPUMismatch

When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 97 for more information). TheMFAULTSTATregister indicates the cause of the fault. See page 169 for more information.

3.2 RegisterMap

Table 3-7 on page 129 lists the Cortex-M3 Peripheral SysTick, NVIC, SCB, and MPU registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table3-7.PeripheralsRegisterMap See pageDescriptionResetTypeNameOffset SystemTimer(SysTick)Registers 132SysTick Control and Status Register0x0000.0004R/WSTCTRL0x010 134SysTick Reload Value Register0x0000.0000R/WSTRELOAD0x014 135SysTick Current Value Register0x0000.0000R/WCSTCURRENT0x018 NestedVectoredInterruptController(NVIC)Registers 136Interrupt 0-31 Set Enable0x0000.0000R/WEN00x100 137Interrupt 32-54 Set Enable0x0000.0000R/WEN10x104 138Interrupt 0-31 Clear Enable0x0000.0000R/WDIS00x180 139Interrupt 32-54 Clear Enable0x0000.0000R/WDIS10x184 140Interrupt 0-31 Set Pending0x0000.0000R/WPEND00x200 141Interrupt 32-54 Set Pending0x0000.0000R/WPEND10x204 142Interrupt 0-31 Clear Pending0x0000.0000R/WUNPEND00x280 143Interrupt 32-54 Clear Pending0x0000.0000R/WUNPEND10x284 144Interrupt 0-31 Active Bit0x0000.0000ROACTIVE00x300 145Interrupt 32-54 Active Bit0x0000.0000ROACTIVE10x304 146Interrupt 0-3 Priority0x0000.0000R/WPRI00x400 129March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table3-7.PeripheralsRegisterMap (continued) See pageDescriptionResetTypeNameOffset 146Interrupt 4-7 Priority0x0000.0000R/WPRI10x404 146Interrupt 8-11 Priority0x0000.0000R/WPRI20x408 146Interrupt 12-15 Priority0x0000.0000R/WPRI30x40C 146Interrupt 16-19 Priority0x0000.0000R/WPRI40x410 146Interrupt 20-23 Priority0x0000.0000R/WPRI50x414 146Interrupt 24-27 Priority0x0000.0000R/WPRI60x418 146Interrupt 28-31 Priority0x0000.0000R/WPRI70x41C 146Interrupt 32-35 Priority0x0000.0000R/WPRI80x420 146Interrupt 36-39 Priority0x0000.0000R/WPRI90x424 146Interrupt 40-43 Priority0x0000.0000R/WPRI100x428 146Interrupt 44-47 Priority0x0000.0000R/WPRI110x42C 146Interrupt 48-51 Priority0x0000.0000R/WPRI120x430 146Interrupt 52-54 Priority0x0000.0000R/WPRI130x434 148Software Trigger Interrupt0x0000.0000WOSWTRIG0xF00 SystemControlBlock(SCB)Registers 149Auxiliary Control0x0000.0000R/WACTLR0x008 151CPU ID Base0x412F.C230ROCPUID0xD00 152Interrupt Control and State0x0000.0000R/WINTCTRL0xD04 155Vector Table Offset0x0000.0000R/WVTABLE0xD08 156Application Interrupt and Reset Control0xFA05.0000R/WAPINT0xD0C 158System Control0x0000.0000R/WSYSCTRL0xD10 160Configuration and Control0x0000.0200R/WCFGCTRL0xD14 162System Handler Priority 10x0000.0000R/WSYSPRI10xD18 163System Handler Priority 20x0000.0000R/WSYSPRI20xD1C 164System Handler Priority 30x0000.0000R/WSYSPRI30xD20 165System Handler Control and State0x0000.0000R/WSYSHNDCTRL0xD24 169Configurable Fault Status0x0000.0000R/W1CFAULTSTAT0xD28 175Hard Fault Status0x0000.0000R/W1CHFAULTSTAT0xD2C 176Memory Management Fault Address-R/WMMADDR0xD34 177Bus Fault Address-R/WFAULTADDR0xD38 MemoryProtectionUnit(MPU)Registers 178MPU Type0x0000.0800ROMPUTYPE0xD90 March 19, 2011130 Texas Instruments-Advance Information Cortex-M3 Peripherals

Table3-7.PeripheralsRegisterMap (continued) See pageDescriptionResetTypeNameOffset 179MPU Control0x0000.0000R/WMPUCTRL0xD94 181MPU Region Number0x0000.0000R/WMPUNUMBER0xD98 182MPU Region Base Address0x0000.0000R/WMPUBASE0xD9C 184MPU Region Attribute and Size0x0000.0000R/WMPUATTR0xDA0 182MPU Region Base Address Alias 10x0000.0000R/WMPUBASE10xDA4 184MPU Region Attribute and Size Alias 10x0000.0000R/WMPUATTR10xDA8 182MPU Region Base Address Alias 20x0000.0000R/WMPUBASE20xDAC 184MPU Region Attribute and Size Alias 20x0000.0000R/WMPUATTR20xDB0 182MPU Region Base Address Alias 30x0000.0000R/WMPUBASE30xDB4 184MPU Region Attribute and Size Alias 30x0000.0000R/WMPUATTR30xDB8

3.3 SystemTimer(SysTick)RegisterDescriptions

This section lists and describes the System Timer registers, in numerical order by address offset. 131March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register1:SysTickControlandStatusRegister(STCTRL),offset0x010 Note: This register can only be accessed from privileged mode. The SysTickSTCTRLregister enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type R/W, reset 0x0000.0004 16171819202122232425262728293031 COUNTreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ENABLEINTENCLK_SRCreserved R/WR/WR/WROROROROROROROROROROROROROType 0010000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:17 Count Flag DescriptionValue The SysTick timer has not counted to 0 since the last time this bit was read. The SysTick timer has counted to 0 since the last time this bit was read. This bit is cleared by a read of the register or if theSTCURRENTregister is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in theAHB-APControlRegister is clear. Otherwise, the COUNT bit is not changed by the debugger read. See theARM® Debug Interface V5 Architecture Specification for more information on MasterType. 0ROCOUNT16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved15:3 Clock Source DescriptionValue External reference clock. (Not implemented for Stellaris microcontrollers.) System clock1 Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. 1R/WCLK_SRC2 March 19, 2011132 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Interrupt Enable DescriptionValue Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. An interrupt is generated to the NVIC when SysTick counts to 0. 0R/WINTEN1 Enable DescriptionValue The counter is disabled.0 Enables SysTick to operate in a multi-shot way. That is, the counter loads theRELOAD value and begins counting down. On reaching 0, theCOUNT bit is set and an interrupt is generated if enabled byINTEN. The counter then loads the RELOAD value again and begins counting. 0R/WENABLE0 133March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register2:SysTickReloadValueRegister(STRELOAD),offset0x014 Note: This register can only be accessed from privileged mode. The STRELOADregister specifies the start value to load into theSysTickCurrentValue (STCURRENT)register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into theRELOAD field. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 RELOADreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RELOAD R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Reload Value Value to load into theSysTickCurrentValue(STCURRENT) register when the counter reaches 0. 0x00.0000R/WRELOAD23:0 March 19, 2011134 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register3:SysTickCurrentValueRegister(STCURRENT),offset0x018 Note: This register can only be accessed from privileged mode. The STCURRENTregister contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type R/WC, reset 0x0000.0000 16171819202122232425262728293031 CURRENTreserved R/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CURRENT R/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears theCOUNT bit of theSTCTRLregister. 0x00.0000R/WCCURRENT23:0

3.4 NVICRegisterDescriptions

This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling theConfigurationandControl(CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming theVTABLEregister to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 155. 135March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register4:Interrupt0-31SetEnable(EN0),offset0x100 Note: This register can only be accessed from privileged mode. The EN0register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 109 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Enable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the correspondingINT[n] bit in the DISnregister. 0x0000.0000R/WINT31:0 March 19, 2011136 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register5:Interrupt32-54SetEnable(EN1),offset0x104 Note: This register can only be accessed from privileged mode. The EN1register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 109 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 32-54 Set Enable (EN1) Base 0xE000.E000 Offset 0x104 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INTreserved R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:23 Interrupt Enable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the correspondingINT[n] bit in the DIS1register. 0x00.0000R/WINT22:0 137March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register6:Interrupt0-31ClearEnable(DIS0),offset0x180 Note: This register can only be accessed from privileged mode. The DIS0register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 109 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Disable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, clears the correspondingINT[n] bit in theEN0 register, disabling interrupt [n]. 0x0000.0000R/WINT31:0 March 19, 2011138 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register7:Interrupt32-54ClearEnable(DIS1),offset0x184 Note: This register can only be accessed from privileged mode. The DIS1register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 109 for interrupt assignments. Interrupt 32-54 Clear Enable (DIS1) Base 0xE000.E000 Offset 0x184 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INTreserved R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:23 Interrupt Disable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, clears the correspondingINT[n] bit in theEN1 register, disabling interrupt [n]. 0x00.0000R/WINT22:0 139March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register8:Interrupt0-31SetPending(PEND0),offset0x200 Note: This register can only be accessed from privileged mode. The PEND0register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 109 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Set Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the correspondingINT[n] bit in the UNPEND0register. 0x0000.0000R/WINT31:0 March 19, 2011140 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register9:Interrupt32-54SetPending(PEND1),offset0x204 Note: This register can only be accessed from privileged mode. The PEND1register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 109 for interrupt assignments. Interrupt 32-54 Set Pending (PEND1) Base 0xE000.E000 Offset 0x204 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INTreserved R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:23 Interrupt Set Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the correspondingINT[n] bit in the UNPEND1register. 0x00.0000R/WINT22:0 141March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register10:Interrupt0-31ClearPending(UNPEND0),offset0x280 Note: This register can only be accessed from privileged mode. The UNPEND0register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 109 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Clear Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, clears the correspondingINT[n] bit in thePEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 0x0000.0000R/WINT31:0 March 19, 2011142 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register11:Interrupt32-54ClearPending(UNPEND1),offset0x284 Note: This register can only be accessed from privileged mode. The UNPEND1register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 109 for interrupt assignments. Interrupt 32-54 Clear Pending (UNPEND1) Base 0xE000.E000 Offset 0x284 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 INTreserved R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INT R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:23 Interrupt Clear Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, clears the correspondingINT[n] bit in thePEND1 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 0x00.0000R/WINT22:0 143March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register12:Interrupt0-31ActiveBit(ACTIVE0),offset0x300 Note: This register can only be accessed from privileged mode. The ACTIVE0register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 109 for interrupt assignments. Caution – Do not manually set or clear the bits in this register . Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 16171819202122232425262728293031 INT ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INT ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Active DescriptionValue The corresponding interrupt is not active.0 The corresponding interrupt is active, or active and pending.1 0x0000.0000ROINT31:0 March 19, 2011144 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register13:Interrupt32-54ActiveBit(ACTIVE1),offset0x304 Note: This register can only be accessed from privileged mode. The ACTIVE1register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 109 for interrupt assignments. Caution – Do not manually set or clear the bits in this register . Interrupt 32-54 Active Bit (ACTIVE1) Base 0xE000.E000 Offset 0x304 Type RO, reset 0x0000.0000 16171819202122232425262728293031 INTreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INT ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:23 Interrupt Active DescriptionValue The corresponding interrupt is not active.0 The corresponding interrupt is active, or active and pending.1 0x00.0000ROINT22:0 145March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register14:Interrupt0-3Priority(PRI0),offset0x400 Register15:Interrupt4-7Priority(PRI1),offset0x404 Register16:Interrupt8-11Priority(PRI2),offset0x408 Register17:Interrupt12-15Priority(PRI3),offset0x40C Register18:Interrupt16-19Priority(PRI4),offset0x410 Register19:Interrupt20-23Priority(PRI5),offset0x414 Register20:Interrupt24-27Priority(PRI6),offset0x418 Register21:Interrupt28-31Priority(PRI7),offset0x41C Register22:Interrupt32-35Priority(PRI8),offset0x420 Register23:Interrupt36-39Priority(PRI9),offset0x424 Register24:Interrupt40-43Priority(PRI10),offset0x428 Register25:Interrupt44-47Priority(PRI11),offset0x42C Register26:Interrupt48-51Priority(PRI12),offset0x430 Register27:Interrupt52-54Priority(PRI13),offset0x434 Note: This register can only be accessed from privileged mode. The PRInregisters provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: InterruptPRInRegisterBitField Interrupt [4n+3]Bits 31:29 Interrupt [4n+2]Bits 23:21 Interrupt [4n+1]Bits 15:13 Interrupt [4n]Bits 7:5 See Table 2-9 on page 109 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. ThePRIGROUP field in theApplicationInterruptandResetControl(APINT) register (see page 156) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. March 19, 2011146 Texas Instruments-Advance Information Cortex-M3 Peripherals

Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedINTCreservedINTD ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 reservedINTAreservedINTB ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0R/WINTD31:29 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved28:24 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0R/WINTC23:21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved20:16 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0R/WINTB15:13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved12:8 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0R/WINTA7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved4:0 147March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register28:SoftwareTriggerInterrupt(SWTRIG),offset0xF00 Note: Only privileged software can enable unprivileged access to theSWTRIGregister. Writing an interrupt number to theSWTRIGregister generates a Software Generated Interrupt (SGI). See Table 2-9 on page 109 for interrupt assignments. When theMAINPEND bit in theConfigurationandControl(CFGCTRL) register (see page 160) is set, unprivileged software can access theSWTRIGregister. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTIDreserved WOWOWOWOWOWOROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:6 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 0x00WOINTID5:0

3.5 SystemControlBlock(SCB)RegisterDescriptions

This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for theFAULTSTATand SYSPRI1-SYSPRI3registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. March 19, 2011148 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register29:AuxiliaryControl(ACTLR),offset0x008 Note: This register can only be accessed from privileged mode. The ACTLRregister provides disable bits forIT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M3 processor and does not normally require modification. Auxiliary Control (ACTLR) Base 0xE000.E000 Offset 0x008 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DISMCYCDISWBUFDISFOLDreserved R/WR/WR/WROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 Disable IT Folding DescriptionValue No effect.0 Disables IT folding.1 In some situations, the processor can start executing the first instruction in anIT block while it is still executing theIT instruction. This behavior is calledIT folding, and improves performance, However,IT folding can cause jitter in looping. If a task must avoid jitter, set theDISFOLD bit before executing the task, to disableIT folding. 0R/WDISFOLD2 Disable Write Buffer DescriptionValue No effect.0 Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M3 processor. 0R/WDISWBUF1 149March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Disable Interrupts of Multiple Cycle Instructions DescriptionValue No effect.0 Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because anyLDM or STM must complete before the processor can stack the current state and enter the interrupt handler. 0R/WDISMCYC0 March 19, 2011150 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register30:CPUIDBase(CPUID),offset0xD00 Note: This register can only be accessed from privileged mode. The CPUIDregister contains the ARM® Cortex™-M3 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x412F.C230 16171819202122232425262728293031 CONVARIMP ROROROROROROROROR0R0R0R0R0R0R0R0Type 1111010010000010Reset 0123456789101112131415 REVPARTNO ROROROROROROROROROROROROROROROROType 0000110001000011Reset DescriptionResetTypeNameBit/Field Implementer Code DescriptionValue ARM0x41 0x41R0IMP31:24 Variant Number DescriptionValue The rn value in the rnpn product revision identifier, for example, the 2 in r2p0. 0x2 0x2ROVAR23:20 Constant DescriptionValue Always reads as 0xF.0xF 0xFROCON19:16 Part Number DescriptionValue Cortex-M3 processor.0xC23 0xC23ROPARTNO15:4 Revision Number DescriptionValue The pn value in the rnpn product revision identifier, for example, the 0 in r2p0. 0x0 0x0ROREV3:0 151March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register31:InterruptControlandState(INTCTRL),offset0xD04 Note: This register can only be accessed from privileged mode. The INCTRLregister provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing toINCTRL, the effect is unpredictable when writing a 1 to both thePENDSV and UNPENDSV bits, or writing a 1 to both thePENDSTSET and PENDSTCLR bits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 VECPENDreservedISRPENDISRPREreservedPENDSTCLRPENDSTSETUNPENDSVPENDSVreservedNMISET ROROROROROROROROROWOR/WWOR/WROROR/WType 0000000000000000Reset 0123456789101112131415 VECACTreservedRETBASEVECPEND ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field NMI Set Pending DescriptionValue On a read, indicates an NMI exception is not pending. On a write, no effect. On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if theNMI signal is reasserted while the processor is executing that handler. 0R/WNMISET31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved30:29 PendSV Set Pending DescriptionValue On a read, indicates a PendSV exception is not pending. On a write, no effect. On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to theUNPENDSV bit. 0R/WPENDSV28 March 19, 2011152 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field PendSV Clear Pending DescriptionValue On a write, no effect.0 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 0WOUNPENDSV27 SysTick Set Pending DescriptionValue On a read, indicates a SysTick exception is not pending. On a write, no effect. On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing a 1 to thePENDSTCLR bit. 0R/WPENDSTSET26 SysTick Clear Pending DescriptionValue On a write, no effect.0 On a write, removes the pending state from the SysTick exception. This bit is write only; on a register read, its value is unknown. 0WOPENDSTCLR25 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved24 Debug Interrupt Handling DescriptionValue The release from halt does not take an interrupt.0 The release from halt takes an interrupt.1 This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 0ROISRPRE23 Interrupt Pending DescriptionValue No interrupt is pending.0 An interrupt is pending.1 This bit provides status for all interrupts excluding NMI and Faults. 0ROISRPEND22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved21:19 153March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of theBASEPRIand FAULTMASKregisters, but not any effect of the PRIMASKregister. DescriptionValue No exceptions are pending0x00 Reserved0x01 NMI0x02 Hard fault0x03 Memory management fault0x04 Bus fault0x05 Usage fault0x06 Reserved0x07-0x0A SVCall0x0B Reserved for Debug0x0C Reserved0x0D PendSV0x0E SysTick0x0F Interrupt Vector 00x10 Interrupt Vector 10x11 Interrupt Vector 540x46 Reserved0x47-0x7F 0x00ROVECPEND18:12 Return to Base DescriptionValue There are preempted active exceptions to execute.0 There are no active exceptions, or the currently executing exception is the only active exception. This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the InterruptProgramStatus(IPSR) register is non-zero). 0RORETBASE11 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved10:7 Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for theVECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in theIPSRregister. Subtract 16 from this value to obtain the IRQ number required to index into theInterruptSetEnable(ENn) , InterruptClearEnable(DISn ), InterruptSetPending(PENDn), InterruptClearPending(UNPENDn), and InterruptPriority(PRIn) registers (see page 89). 0x00ROVECACT6:0 March 19, 2011154 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register32:VectorTableOffset(VTABLE),offset0xD08 Note: This register can only be accessed from privileged mode. The VTABLEregister indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 OFFSETBASEreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROType 0000000000000000Reset 0123456789101112131415 reservedOFFSET ROROROROROROROROROR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:30 Vector Table Base DescriptionValue The vector table is in the code memory region.0 The vector table is in the SRAM memory region.1 0R/WBASE29 Vector Table Offset When configuring theOFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 54 interrupts, the minimum alignment is 128 words. 0x000.00R/WOFFSET28:9 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved8:0 155March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register33:ApplicationInterruptandResetControl(APINT),offset0xD0C Note: This register can only be accessed from privileged mode. The APINTregister provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits theINTx fields in the InterruptPriority(PRIx) registers into separate group priority and subpriority fields. Table 3-8 on page 156 shows how thePRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in theINTA field. For the INTB field, the corresponding bits are 15:13; forINTC, 23:21; and forINTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table3-8.InterruptPriorityLevels SubprioritiesGroup Priorities SubpriorityFieldGroupPriorityFieldBinaryPointaPRIGROUP BitField 18None[7:5]bxxx.0x0 - 0x4 24[5][7:6]bxx.y0x5 42[6:5][7]bx.yy0x6 81[7:5]Noneb.yyy0x7 a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type R/W, reset 0xFA05.0000 16171819202122232425262728293031 VECTKEY R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1010000001011111Reset 0123456789101112131415 VECTRESETVECTCLRACTSYSRESREQreservedPRIGROUPreservedENDIANESS WOWOWOROROROROROR/WR/WR/WROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. 0xFA05R/WVECTKEY31:16 Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared to 0. 0ROENDIANESS15 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved14:11 March 19, 2011156 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-8 on page 156 for more information). 0x0R/WPRIGROUP10:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:3 System Reset Request DescriptionValue No effect.0 Resets the core and all on-chip peripherals except the Debug interface. This bit is automatically cleared during the reset of the core and reads as 0. 0WOSYSRESREQ2 Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0WOVECTCLRACT1 System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0WOVECTRESET0 157March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register34:SystemControl(SYSCTRL),offset0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRLregister controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedSLEEPEXITSLEEPDEEPreservedSEVONPENDreserved ROR/WR/WROR/WROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:5 Wake Up on Pending DescriptionValue Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or interrupt enters the pending state, the event signal wakes up the processor fromWFE. If the processor is not waiting for an event, the event is registered and affects the nextWFE. The processor also wakes up on execution of aSEV instruction or an external event. 0R/WSEVONPEND4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 Deep Sleep Enable DescriptionValue Use Sleep mode as the low power mode.0 Use Deep-sleep mode as the low power mode.1 0R/WSLEEPDEEP2 March 19, 2011158 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Sleep on ISR Exit DescriptionValue When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0R/WSLEEPEXIT1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 159March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register35:ConfigurationandControl(CFGCTRL),offset0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRLregister controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by theFAULTMASKregister to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to theSWTRIGregister by unprivileged software (see page 148). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type R/W, reset 0x0000.0200 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 BASETHRMAINPENDreservedUNALIGNEDDIV0reservedBFHFNMIGNSTKALIGNreserved R/WR/WROR/WR/WROROROR/WR/WROROROROROROType 0000000001000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:10 Stack Alignment on Exception Entry DescriptionValue The stack is 4-byte aligned.0 The stack is 8-byte aligned.1 On exception entry, the processor uses bit 9 of the stackedPSRto indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 1R/WSTKALIGN9 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, andFAULTMASKescalated handlers. DescriptionValue Data bus faults caused by load and store instructions cause a lock-up. Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 0R/WBFHFNMIGN8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:5 March 19, 2011160 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. DescriptionValue Do not trap on divide by 0. A divide by zero returns a quotient of 0. Trap on divide by 0.1 0R/WDIV04 Trap on Unaligned Access DescriptionValue Do not trap on unaligned halfword and word accesses.0 Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, andSTRD instructions always fault regardless of whetherUNALIGNED is set. 0R/WUNALIGNED3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 Allow Main Interrupt Trigger DescriptionValue Disables unprivileged software access to theSWTRIGregister.0 Enables unprivileged software access to theSWTRIGregister (see page 148). 0R/WMAINPEND1 Thread State Control DescriptionValue The processor can enter Thread mode only when no exception is active. The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 113 for more information). 0R/WBASETHR0 161March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register36:SystemHandlerPriority1(SYSPRI1),offset0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedUSAGEreserved ROROROROROR/WR/WR/WROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedMEMreservedBUS ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0R/WUSAGE23:21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved20:16 Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0R/WBUS15:13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved12:8 Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0R/WMEM7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved4:0 March 19, 2011162 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register37:SystemHandlerPriority2(SYSPRI2),offset0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedSVC ROROROROROROROROROROROROROR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0R/WSVC31:29 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000ROreserved28:0 163March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register38:SystemHandlerPriority3(SYSPRI3),offset0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedPENDSVreservedTICK ROROROROROR/WR/WR/WROROROROROR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 reservedDEBUGreserved ROROROROROR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0R/WTICK31:29 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved28:24 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0R/WPENDSV23:21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved20:8 Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0R/WDEBUG7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0.0000ROreserved4:0 March 19, 2011164 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register39:SystemHandlerControlandState(SYSHNDCTRL),offset0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRLregister enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution – Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 MEMBUSUSAGEreserved R/WR/WR/WROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 MEMABUSAreservedUSGAreservedSVCAMONreservedPNDSVTICKUSAGEPMEMPBUSPSVC R/WR/WROR/WROROROR/WR/WROR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:19 Usage Fault Enable DescriptionValue Disables the usage fault exception.0 Enables the usage fault exception.1 0R/WUSAGE18 Bus Fault Enable DescriptionValue Disables the bus fault exception.0 Enables the bus fault exception.1 0R/WBUS17 165March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Memory Management Fault Enable DescriptionValue Disables the memory management fault exception.0 Enables the memory management fault exception.1 0R/WMEM16 SVC Call Pending DescriptionValue An SVC call exception is not pending.0 An SVC call exception is pending.1 This bit can be modified to change the pending status of the SVC call exception. 0R/WSVC15 Bus Fault Pending DescriptionValue A bus fault exception is not pending.0 A bus fault exception is pending.1 This bit can be modified to change the pending status of the bus fault exception. 0R/WBUSP14 Memory Management Fault Pending DescriptionValue A memory management fault exception is not pending.0 A memory management fault exception is pending.1 This bit can be modified to change the pending status of the memory management fault exception. 0R/WMEMP13 Usage Fault Pending DescriptionValue A usage fault exception is not pending.0 A usage fault exception is pending.1 This bit can be modified to change the pending status of the usage fault exception. 0R/WUSAGEP12 SysTick Exception Active DescriptionValue A SysTick exception is not active.0 A SysTick exception is active.1 This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. 0R/WTICK11 March 19, 2011166 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field PendSV Exception Active DescriptionValue A PendSV exception is not active.0 A PendSV exception is active.1 This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 0R/WPNDSV10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved9 Debug Monitor Active DescriptionValue The Debug monitor is not active.0 The Debug monitor is active.1 0R/WMON8 SVC Call Active DescriptionValue SVC call is not active.0 SVC call is active.1 This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 0R/WSVCA7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved6:4 Usage Fault Active DescriptionValue Usage fault is not active.0 Usage fault is active.1 This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 0R/WUSGA3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 Bus Fault Active DescriptionValue Bus fault is not active.0 Bus fault is active.1 This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. 0R/WBUSA1 167March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Memory Management Fault Active DescriptionValue Memory management fault is not active.0 Memory management fault is active.1 This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. 0R/WMEMA0 March 19, 2011168 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register40:ConfigurableFaultStatus(FAULTSTAT),offset0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTATregister indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ UsageFaultStatus(UFAULTSTAT) , bits 31:16 ■ BusFaultStatus(BFAULTSTAT) , bits 15:8 ■ MemoryManagementFaultStatus(MFAULTSTAT) , bits 7:0 FAULTSTATis byte accessible.FAULTSTATor its subregisters can be accessed as follows: ■ The complete FAULTSTATregister, with a word access to offset 0xD28 ■ The MFAULTSTAT, with a byte access to offset 0xD28 ■ The MFAULTSTATand BFAULTSTAT, with a halfword access to offset 0xD28 ■ The BFAULTSTAT, with a byte access to offset 0xD29 ■ The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save theMemoryManagementFaultAddress(MMADDR) or BusFaultAddress (FAULTADDR)value. 2. Read theMMARV bit inMFAULTSTAT, or theBFARV bit inBFAULTSTATto determine if the MMADDRor FAULTADDRcontents are valid. Software must follow this sequence because another higher priority exception might change the MMADDRor FAULTADDRvalue. For example, if a higher priority handler preempts the current fault handler, the other fault might change theMMADDRor FAULTADDRvalue. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type R/W1C, reset 0x0000.0000 16171819202122232425262728293031 UNDEFINVSTATINVPCNOCPreservedUNALIGNDIV0reserved R/W1CR/W1CR/W1CR/W1CROROROROR/W1CR/W1CROROROROROROType 0000000000000000Reset 0123456789101112131415 IERRDERRreservedMUSTKEMSTKEreservedMMARVIBUSPRECISEIMPREBUSTKEBSTKEreservedBFARV R/W1CR/W1CROR/W1CR/W1CROROR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CROROR/W1CType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:26 169March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Divide-by-Zero Usage Fault DescriptionValue No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. The processor has executed anSDIV or UDIV instruction with a divisor of 0. When this bit is set, thePCvalue stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting theDIV0 bit in the ConfigurationandControl(CFGCTRL) register (see page 160). This bit is cleared by writing a 1 to it. 0R/W1CDIV025 Unaligned Access Usage Fault DescriptionValue No unaligned access fault has occurred, or unaligned access trapping is not enabled. The processor has made an unaligned memory access.1 Unaligned LDM, STM, LDRD, andSTRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting theUNALIGNED bit in theCFGCTRLregister (see page 160). This bit is cleared by writing a 1 to it. 0R/W1CUNALIGN24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved23:20 No Coprocessor Usage Fault DescriptionValue A usage fault has not been caused by attempting to access a coprocessor. The processor has attempted to access a coprocessor.1 This bit is cleared by writing a 1 to it. 0R/W1CNOCP19 Invalid PC Load Usage Fault DescriptionValue A usage fault has not been caused by attempting to load an invalid PCvalue. The processor has attempted an illegal load of EXC_RETURN to thePCas a result of an invalid context or an invalid EXC_RETURN value. When this bit is set, thePCvalue stacked for the exception return points to the instruction that tried to perform the illegal load of thePC. This bit is cleared by writing a 1 to it. 0R/W1CINVPC18 March 19, 2011170 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Invalid State Usage Fault DescriptionValue A usage fault has not been caused by an invalid state.0 The processor has attempted to execute an instruction that makes illegal use of theEPSRregister. When this bit is set, thePCvalue stacked for the exception return points to the instruction that attempted the illegal use of theExecution ProgramStatusRegister(EPSR) register. This bit is not set if an undefined instruction uses theEPSRregister. This bit is cleared by writing a 1 to it. 0R/W1CINVSTAT17 Undefined Instruction Usage Fault DescriptionValue A usage fault has not been caused by an undefined instruction.0 The processor has attempted to execute an undefined instruction. When this bit is set, thePCvalue stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 0R/W1CUNDEF16 Bus Fault Address Register Valid DescriptionValue The value in theBusFaultAddress(FAULTADDR) register is not a valid fault address. The FAULTADDRregister is holding a valid fault address.1 This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whoseFAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 0R/W1CBFARV15 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved14:13 Stack Bus Fault DescriptionValue No bus fault has occurred on stacking for exception entry.0 Stacking for an exception entry has caused one or more bus faults. When this bit is set, theSPis still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDRregister. This bit is cleared by writing a 1 to it. 0R/W1CBSTKE12 171March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Unstack Bus Fault DescriptionValue No bus fault has occurred on unstacking for a return from exception. Unstacking for a return from exception has caused one or more bus faults. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. TheSPis not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDRregister. This bit is cleared by writing a 1 to it. 0R/W1CBUSTKE11 Imprecise Data Bus Error DescriptionValue An imprecise data bus error has not occurred.0 A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When this bit is set, a fault address is not written to theFAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both theIMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 0R/W1CIMPRE10 Precise Data Bus Error DescriptionValue A precise data bus error has not occurred.0 A data bus error has occurred, and thePCvalue stacked for the exception return points to the instruction that caused the fault. When this bit is set, the fault address is written to theFAULTADDR register. This bit is cleared by writing a 1 to it. 0R/W1CPRECISE9 Instruction Bus Error DescriptionValue An instruction bus error has not occurred.0 An instruction bus error has occurred.1 The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to theFAULTADDR register. This bit is cleared by writing a 1 to it. 0R/W1CIBUS8 March 19, 2011172 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Memory Management Fault Address Register Valid DescriptionValue The value in theMemoryManagementFaultAddress (MMADDR)register is not a valid fault address. The MMADDRregister is holding a valid fault address.1 If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whoseMMADDRregister value has been overwritten. This bit is cleared by writing a 1 to it. 0R/W1CMMARV7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved6:5 Stack Access Violation DescriptionValue No memory management fault has occurred on stacking for exception entry. Stacking for an exception entry has caused one or more access violations. When this bit is set, theSPis still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDRregister. This bit is cleared by writing a 1 to it. 0R/W1CMSTKE4 Unstack Access Violation DescriptionValue No memory management fault has occurred on unstacking for a return from exception. Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. TheSPis not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDRregister. This bit is cleared by writing a 1 to it. 0R/W1CMUSTKE3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 173March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Data Access Violation DescriptionValue A data access violation has not occurred.0 The processor attempted a load or store at a location that does not permit the operation. When this bit is set, thePCvalue stacked for the exception return points to the faulting instruction and the address of the attempted access is written to theMMADDRregister. This bit is cleared by writing a 1 to it. 0R/W1CDERR1 Instruction Access Violation DescriptionValue An instruction access violation has not occurred.0 The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, thePCvalue stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to theMMADDRregister. This bit is cleared by writing a 1 to it. 0R/W1CIERR0 March 19, 2011174 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register41:HardFaultStatus(HFAULTSTAT),offset0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTATregister gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type R/W1C, reset 0x0000.0000 16171819202122232425262728293031 reservedFORCEDDBG ROROROROROROROROROROROROROROR/W1CR/W1CType 0000000000000000Reset 0123456789101112131415 reservedVECTreserved ROR/W1CROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. 0R/W1CDBG31 Forced Hard Fault DescriptionValue No forced hard fault has occurred.0 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 0R/W1CFORCED30 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved29:2 Vector Table Read Fault DescriptionValue No bus fault has occurred on a vector table read.0 A bus fault occurred on a vector table read.1 This error is always handled by the hard fault handler. When this bit is set, thePCvalue stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 0R/W1CVECT1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 175March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register42:MemoryManagementFaultAddress(MMADDR),offset0xD34 Note: This register can only be accessed from privileged mode. The MMADDRregister contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in theMMADDRregister is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in theMemory ManagementFaultStatus(MFAULTSTAT) register indicate the cause of the fault and whether the value in theMMADDRregister is valid (see page 169). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type R/W, reset - 16171819202122232425262728293031 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Fault Address When theMMARV bit ofMFAULTSTATis set, this field holds the address of the location that generated the memory management fault. -R/WADDR31:0 March 19, 2011176 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register43:BusFaultAddress(FAULTADDR),offset0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDRregister contains the address of the location that generated a bus fault. When an unaligned access faults, the address in theFAULTADDRregister is the one requested by the instruction, even if it is not the address of the fault. Bits in theBusFaultStatus(BFAULTSTAT) register indicate the cause of the fault and whether the value in theFAULTADDRregister is valid (see page 169). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type R/W, reset - 16171819202122232425262728293031 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Fault Address When theFAULTADDRV bit ofBFAULTSTATis set, this field holds the address of the location that generated the bus fault. -R/WADDR31:0

3.6 MemoryProtectionUnit(MPU)RegisterDescriptions

This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. 177March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register44:MPUType(MPUTYPE),offset0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPEregister indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 16171819202122232425262728293031 IREGIONreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SEPARATEreservedDREGION ROROROROROROROROROROROROROROROROType 0000000000010000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by theDREGION field. 0x00ROIREGION23:16 Number of D Regions DescriptionValue Indicates there are eight supported MPU data regions.0x08 0x08RODREGION15:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved7:1 Separate or Unified MPU DescriptionValue Indicates the MPU is unified.0 0ROSEPARATE0 March 19, 2011178 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register45:MPUControl(MPUCTRL),offset0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRLregister enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), andFaultMask Register(FAULTMASK) escalated handlers. When theENABLE and PRIVDEFEN bits are both set: ■ For privileged accesses, the default memory map is as described in “Memory Model” on page 97. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. ■ Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of theENABLE bit. When theENABLE bit is set, at least one region of the memory map must be enabled for the system to function unless thePRIVDEFEN bit is set. If thePRIVDEFEN bit is set and no regions are enabled, then only privileged software can operate. When theENABLE bit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 100 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whetherPRIVDEFEN is set. Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception or whenFAULTMASKis enabled. Setting theHFNMIENA bit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ENABLEHFNMIENAPRIVDEFENreserved R/WR/WR/WROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 179March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field MPU Default Region This bit enables privileged software access to the default memory map. DescriptionValue If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. 0R/WPRIVDEFEN2 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASKhandlers. DescriptionValue The MPU is disabled during hard fault, NMI, andFAULTMASK handlers, regardless of the value of theENABLE bit. The MPU is enabled during hard fault, NMI, andFAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. 0R/WHFNMIENA1 MPU Enable DescriptionValue The MPU is disabled.0 The MPU is enabled.1 When the MPU is disabled and theHFNMIENA bit is set, the resulting behavior is unpredictable. 0R/WENABLE0 March 19, 2011180 Texas Instruments-Advance Information Cortex-M3 Peripherals

Register46:MPURegionNumber(MPUNUMBER),offset0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBERregister selects which memory region is referenced by theMPURegionBase Address(MPUBASE) and MPURegionAttributeandSize(MPUATTR) registers. Normally, the required region number should be written to this register before accessing theMPUBASEor the MPUATTRregister. However, the region number can be changed by writing to theMPUBASE register with theVALID bit set (see page 182). This write updates the value of theREGION field. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 NUMBERreserved R/WR/WR/WROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 MPU Region to Access This field indicates the MPU region referenced by theMPUBASEand MPUATTRregisters. The MPU supports eight memory regions. 0x0R/WNUMBER2:0 181March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register47:MPURegionBaseAddress(MPUBASE),offset0xD9C Register48:MPURegionBaseAddressAlias1(MPUBASE1),offset0xDA4 Register49:MPURegionBaseAddressAlias2(MPUBASE2),offset0xDAC Register50:MPURegionBaseAddressAlias3(MPUBASE3),offset0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASEregister defines the base address of the MPU region selected by theMPURegion Number(MPUNUMBER) register and can update the value of theMPUNUMBERregister. To change the current region number and update theMPUNUMBERregister, write theMPUBASE register with theVALID bit set. The ADDR field is bits 31:N of theMPUBASEregister. Bits (N-1):5 are reserved. The region size, as specified by theSIZE field in theMPURegionAttributeandSize(MPUATTR) register, defines the value ofN where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in theMPUATTRregister, there is no validADDR field. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 REGIONreservedVALIDADDR R/WR/WR/WROWOR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Base Address Mask Bits 31:N in this field contain the region base address. The value ofN depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000R/WADDR31:5 March 19, 2011182 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Region Number Valid DescriptionValue The MPUNUMBERregister is not changed and the processor updates the base address for the region specified in the MPUNUMBERregister and ignores the value of theREGION field. The MPUNUMBERregister is updated with the value of the REGION field and the base address is updated for the region specified in theREGION field. This bit is always read as 0. 0WOVALID4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 Region Number On a write, contains the value to be written to theMPUNUMBERregister. On a read, returns the current region number in theMPUNUMBER register. 0x0R/WREGION2:0 183March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register51:MPURegionAttributeandSize(MPUATTR),offset0xDA0 Register52:MPURegionAttributeandSizeAlias1(MPUATTR1),offset0xDA8 Register53:MPURegionAttributeandSizeAlias2(MPUATTR2),offset0xDB0 Register54:MPURegionAttributeandSizeAlias3(MPUATTR3),offset0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTRregister defines the region size and memory attributes of the MPU region specified by theMPURegionNumber(MPUNUMBER) register and enables that region and any subregions. The MPUATTRregister is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits,XN, AP, TEX, S, C, andB, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZE field defines the size of the MPU memory region specified by theMPUNUMBERregister as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to aSIZE value of 4. Table 3-9 on page 184 gives exampleSIZE values with the corresponding region size and value of N in the MPURegionBaseAddress(MPUBASE) register. Table3-9.ExampleSIZEFieldValues NoteValueofN aRegionSizeSIZE Encoding Minimum permitted size532 B00100b (0x4) -101 KB01001b (0x9) -201 MB10011b (0x13) -301 GB11101b (0x1D) Maximum possible sizeNo validADDR field inMPUBASE; the region occupies the complete memory map.

4 GB11111b (0x1F)

a. Refers to the N parameter in theMPUBASEregister (see page 182). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 BCSTEXreservedAPreservedXNreserved R/WR/WR/WR/WR/WR/WROROR/WR/WR/WROR/WROROROType 0000000000000000Reset 0123456789101112131415 ENABLESIZEreservedSRD R/WR/WR/WR/WR/WR/WROROR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset March 19, 2011184 Texas Instruments-Advance Information Cortex-M3 Peripherals

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:29 Instruction Access Disable DescriptionValue Instruction fetches are enabled.0 Instruction fetches are disabled.1 0R/WXN28 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 Access Privilege For information on using this bit field, see Table 3-5 on page 128. 0R/WAP26:24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved23:22 Type Extension Mask For information on using this bit field, see Table 3-3 on page 127. 0x0R/WTEX21:19 Shareable For information on using this bit, see Table 3-3 on page 127. 0R/WS18 Cacheable For information on using this bit, see Table 3-3 on page 127. 0R/WC17 Bufferable For information on using this bit, see Table 3-3 on page 127. 0R/WB16 Subregion Disable Bits DescriptionValue The corresponding subregion is enabled.0 The corresponding subregion is disabled.1 Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure theSRD field as 0x00. See the section called “Subregions” on page 126 for more information. 0x00R/WSRD15:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:6 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBERregister. Refer to Table 3-9 on page 184 for more information. 0x0R/WSIZE5:1 185March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Region Enable DescriptionValue The region is disabled.0 The region is enabled.1 0R/WENABLE0 March 19, 2011186 Texas Instruments-Advance Information Cortex-M3 Peripherals

4 JTAGInterface

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of four pins:TCK, TMS, TDI, andTDO. Data is transmitted serially into the controller onTDI and out of the controller onTDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to theIEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Stellaris® JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core by multiplexing theTDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the StellarisTDO output. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. The Stellaris JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See theARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 187March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

4.1 BlockDiagram

Figure4-1.JTAGModuleBlockDiagram Instruction Register (IR) T AP Controller BYP ASS Data Register Boundary Scan Data Register IDCODE Data Register ABOR T Data Register DP ACC Data Register AP ACC Data Register TCK TMS TDI TDO Cortex-M3 Debug Port

4.2 SignalDescription

Table 4-1 on page 188 and Table 4-2 on page 189 list the external signals of the JTAG/SWD controller and describe the function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals are under commit protection and require a special process to be configured as GPIOs, see “Commit Control” on page 405. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. TheAFSEL bit in theGPIOAlternateFunctionSelect(GPIOAFSEL) register (page 421) is set to choose the JTAG/SWD function. The number in parentheses is the encoding that must be programmed into the PMCn field in theGPIOPortControl(GPIOPCTL) register (page 439) to assign the JTAG/SWD controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 397. Table4-1.SignalsforJTAG_SWD_SWO(100LQFP) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName JTAG/SWD CLK.TTLIPC0 (3)80SWCLK JTAG TMS and SWDIO.TTLI/OPC1 (3)79SWDIO JTAG TDO and SWO.TTLOPC3 (3)77SWO JTAG/SWD CLK.TTLIPC0 (3)80TCK JTAG TDI.TTLIPC2 (3)78TDI JTAG TDO and SWO.TTLOPC3 (3)77TDO March 19, 2011188 Texas Instruments-Advance Information JTAG Interface

Table4-1.SignalsforJTAG_SWD_SWO(100LQFP) (continued) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName JTAG TMS and SWDIO.TTLIPC1 (3)79TMS a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table4-2.SignalsforJTAG_SWD_SWO(108BGA) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName JTAG/SWD CLK.TTLIPC0 (3)A9SWCLK JTAG TMS and SWDIO.TTLI/OPC1 (3)B9SWDIO JTAG TDO and SWO.TTLOPC3 (3)A10SWO JTAG/SWD CLK.TTLIPC0 (3)A9TCK JTAG TDI.TTLIPC2 (3)B8TDI JTAG TDO and SWO.TTLOPC3 (3)A10TDO JTAG TMS and SWDIO.TTLIPC1 (3)B9TMS a. The TTL designation indicates the pin has TTL-compatible voltage levels.

4.3 FunctionalDescription

A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 188. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by theTCK and TMS inputs. The current state of the TAP controller depends on the sequence of values captured onTMS at the rising edge ofTCK. The TAP controller determines when the serial shift chains capture new data, shift data fromTDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path betweenTDI and TDO is always connected (see Table 4-4 on page 195 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 1304 for JTAG timing diagrams. Note: Of all the possible reset sources, only Power-On reset (POR) and the assertion of theRST input have any effect on the JTAG module. The pin configurations are reset by both the RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset Sources” on page 200 for more information on reset.

4.3.1 JTAGInterfacePins

The JTAG interface consists of four standard pins:TCK, TMS, TDI, andTDO. These pins and their associated state after a power-on reset or reset caused by theRST input are given in Table 4-3. Detailed information on each pin follows. Refer to “General-Purpose Input/Outputs (GPIOs)” on page 397 for information on how to reprogram the configuration of these pins. 189March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table4-3.JTAGPortPinsStateafterPower-OnResetorRST assertion DriveValueDriveStrengthInternalPull-DownInternalPull-UpDataDirectionPinName N/AN/ADisabledEnabledInputTCK N/AN/ADisabledEnabledInputTMS N/AN/ADisabledEnabledInputTDI High-Z2-mA driverDisabledEnabledOutputTDO

4.3.1.1 TestClockInput(TCK)

The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation,TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. WhileTCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on theTCK pin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as theTCK pin is constantly being driven by an external source (see page 427 and page 429).

4.3.1.2 TestModeSelect(TMS)

The TMS pin selects the next state of the JTAG TAP controller.TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value ofTMS, the next state may be entered. Because theTMS pin is sampled on the rising edge ofTCK, theIEEE Standard 1149.1 expects the value onTMS to change on the falling edge ofTCK. Holding TMS high for five consecutiveTCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG module and associated registers are reset to their default values. This procedure should be performed to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 191. By default, the internal pull-up resistor on theTMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost (see page 427).

4.3.1.3 TestDataInput(TDI)

The TDI pin provides a stream of serial information to the IR chain and the DR chains.TDI is sampled on the rising edge ofTCK and, depending on the current TAP state and the current instruction, may present this data to the proper shift register chain. Because theTDI pin is sampled on the rising edge ofTCK, theIEEE Standard 1149.1 expects the value onTDI to change on the falling edge ofTCK. By default, the internal pull-up resistor on theTDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost (see page 427).

4.3.1.4 TestDataOutput(TDO)

The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value ofTDO depends on the current TAP state, the current instruction, and the data in the March 19, 2011190 Texas Instruments-Advance Information JTAG Interface

chain being accessed. In order to save power when the JTAG port is not being used, theTDO pin is placed in an inactive drive state when not actively shifting out data. BecauseTDO can be connected to theTDI of another controller in a daisy-chain configuration, theIEEE Standard 1149.1 expects the value onTDO to change on the falling edge ofTCK. By default, the internal pull-up resistor on theTDO pin is enabled after reset, assuring that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states (see page 427 and page 429).

4.3.2 JTAGTAPController

The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset the JTAG module after the microcontroller has been powered on, theTMS input must be held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting the correct sequence on theTMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer toIEEE Standard 1149.1. Figure4-2.TestAccessPortStateMachine T est Logic Reset Run T est Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Shift IR Exit 1 DR Exit 1 IR Exit 2 DR Exit 2 IR Pause DR Pause IR Update DR Update IR 1 11 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0

4.3.3 ShiftRegisters

The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows 191March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

this information to be shifted out onTDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain onTDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 195.

4.3.4 OperationalConsiderations

Certain operational parameters must be considered when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below.

4.3.4.1 GPIOFunctionality

When the microcontroller is reset with either a POR orRST , the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0] set in thePortCGPIODigitalEnable(GPIODEN) register), enabling the pull-up resistors (PUE[3:0] set in thePortCGPIOPull-UpSelect(GPIOPUR) register), disabling the pull-down resistors (PDE[3:0] cleared in thePortCGPIOPull-DownSelect(GPIOPDR) register) and enabling the alternate hardware function (AFSEL[3:0]set in thePortCGPIOAlternateFunctionSelect (GPIOAFSEL)register) on the JTAG/SWD pins. See page 421, page 427, page 429, and page 432. It is possible for software to configure these pins as GPIOs after reset by clearingAFSEL[3:0] in the PortCGPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller . If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger . The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for theNMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of theGPIOAlternateFunctionSelect(GPIOAFSEL) register (see page 421),GPIOPullUpSelect(GPIOPUR) register (see page 427),GPIOPull-Down Select(GPIOPDR) register (see page 429), andGPIODigitalEnable(GPIODEN) register (see page 432) are not committed to storage unless theGPIOLock(GPIOLOCK) register (see page 434) has been unlocked and the appropriate bits of theGPIOCommit(GPIOCR) register (see page 435) have been set.

4.3.4.2 CommunicationwithJTAG/SWD

Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. March 19, 2011192 Texas Instruments-Advance Information JTAG Interface

4.3.4.3 Recoveringa"Locked"Microcontroller

Note: Performing the sequence below restores the nonvolatile registers discussed in “Nonvolatile Register Programming” on page 309 to their factory default values. The mass erase of the Flash memory caused by the sequence below occurs prior to the nonvolatile registers being restored. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug port unlock sequence that can be used to recover the microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence is: 1. Assert and hold theRST signal. 2. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD Switching” on page 194. 3. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG Switching” on page 194. 4. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 5. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 6. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 7. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 8. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 9. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 10. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 11. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 12. Release theRST signal. 13. Wait 400 ms. 14. Power-cycle the microcontroller.

4.3.4.4 ARMSerialWireDebug(SWD)

In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. 193March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Stepping through this sequence of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see theARM® Debug Interface V5 Architecture Specification . Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to theIEEE Standard 1149.1. This instance is the only one where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on theTCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50TCK/SWCLK cycles withTMS/SWDIO High to ensure that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, onTMS. 3. Send at least 50TCK/SWCLK cycles withTMS/SWDIO High to ensure that if SWJ-DP was already in SWD mode, the SWD goes into the line reset state before sending the switch sequence. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch command to the microcontroller. The 16-bitTMS command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first. This command can also be represented as 0xE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on theTCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50TCK/SWCLK cycles withTMS/SWDIO High to ensure that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, onTMS. 3. Send at least 50TCK/SWCLK cycles withTMS/SWDIO High to ensure that if SWJ-DP was already in JTAG mode, the JTAG goes into the Test Logic Reset state before sending the switch sequence.

4.4 InitializationandConfiguration

After a Power-On-Reset or an external reset (RST ), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. To return the pins to their JTAG functions, enable the four JTAG pins (PC[3:0]) for their alternate function using theGPIOAFSELregister. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings. March 19, 2011194 Texas Instruments-Advance Information JTAG Interface

4.5 RegisterDescriptions

The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within the JTAG controller are all accessed serially through the TAP Controller. These registers include the Instruction Register and the six Data Registers.

4.5.1 InstructionRegister(IR)

The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-4. A detailed explanation of each instruction, along with its associated Data Register, follows. Table4-4.JTAGInstructionRegisterCommands DescriptionInstructionIR[3:0] Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. EXTEST0x0 Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. INTEST0x1 Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. SAMPLE / PRELOAD0x2 Shifts data into the ARM Debug Port Abort Register.ABORT0x8 Shifts data into and out of the ARM DP Access Register.DPACC0xA Shifts data into and out of the ARM AC Access Register.APACC0xB Loads manufacturing information defined by theIEEE Standard 1149.1 into the IDCODE chain and shifts it out. IDCODE0xE Connects TDI to TDO through a single Shift Register chain.BYPASS0xF Defaults to the BYPASS instruction to ensure thatTDI is always connected to TDO. ReservedAll Others

4.5.1.1 EXTESTInstruction

The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. With tests that drive known values out of the controller, this instruction can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register.

4.5.1.2 INTESTInstruction

The INTEST instruction is not associated with its own Data Register chain. Instead, the INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. With tests that drive known values into the controller, this instruction can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 195March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

While the INTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register.

4.5.1.3 SAMPLE/PRELOADInstruction

The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out onTDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register fromTDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. See “Boundary Scan Data Register” on page 197 for more information.

4.5.1.4 ABORTInstruction

The ABORT instruction connects the associated ABORT Data Register chain betweenTDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. See the “ABORT Data Register” on page 198 for more information.

4.5.1.5 DPACCInstruction

The DPACC instruction connects the associated DPACC Data Register chain betweenTDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. See “DPACC Data Register” on page 198 for more information.

4.5.1.6 APACCInstruction

The APACC instruction connects the associated APACC Data Register chain betweenTDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. See “APACC Data Register” on page 198 for more information.

4.5.1.7 IDCODEInstruction

The IDCODE instruction connects the associated IDCODE Data Register chain betweenTDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure input and output data streams. IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 197 for more information. March 19, 2011196 Texas Instruments-Advance Information JTAG Interface

4.5.1.8 BYPASSInstruction

The BYPASS instruction connects the associated BYPASS Data Register chain betweenTDI and TDO. This instruction is used to create a minimum length serial path between theTDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 197 for more information.

4.5.2 DataRegisters

The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.

4.5.2.1 IDCODEDataRegister

The format for the 32-bit IDCODE Data Register defined by theIEEE Standard 1149.1 is shown in Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This definition allows auto-configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure4-3.IDCODERegisterFormat V ersion Part Number Manufacturer ID 1 31 28 27 12 1 1 1 0 TDOTDI

4.5.2.2 BYPASSDataRegister

The format for the 1-bit BYPASS Data Register defined by theIEEE Standard 1149.1 is shown in Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This definition allows auto-configuration test tools to determine which instruction is the default instruction. Figure4-4.BYPASSRegisterFormat

0 TDOTDI

4.5.2.3 BoundaryScanDataRegister

The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each 197March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as shown in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge ofTCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. The EXTEST instruction forces data out of the controller, and the INTEST instruction forces data into the controller. Figure4-5.BoundaryScanRegisterFormat I N TDI st GPIO TDO... O U T O E I N m th GPIO O U T O E I N (m+1) th GPIO O U T O E ... I N GPIO n th O U T O E

4.5.2.4 APACCDataRegister

The format for the 35-bit APACC Data Register defined by ARM is described in theARM® Debug Interface V5 Architecture Specification .

4.5.2.5 DPACCDataRegister

The format for the 35-bit DPACC Data Register defined by ARM is described in theARM® Debug Interface V5 Architecture Specification .

4.5.2.6 ABORTDataRegister

The format for the 35-bit ABORT Data Register defined by ARM is described in theARM® Debug Interface V5 Architecture Specification . March 19, 2011198 Texas Instruments-Advance Information JTAG Interface

5 SystemControl

System control configures the overall operation of the device and provides information about the device. Configurable features include reset control, NMI operation, power control, clock control, and low-power modes.

5.1 SignalDescription

Table 5-1 on page 199 and Table 5-2 on page 199 list the external signals of the System Control module and describe the function of each. TheNMI signal is the alternate function for the GPIOPB7 signal and functions as a GPIO after reset.PB7 is under commit protection and requires a special process to be configured as any alternate function or to subsequently return to the GPIO function, see “Commit Control” on page 405. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for theNMI signal. TheAFSEL bit in theGPIOAlternateFunction Select(GPIOAFSEL) register (page 421) should be set to choose the NMI function. The number in parentheses is the encoding that must be programmed into thePMCn field in theGPIOPortControl (GPIOPCTL)register (page 439) to assign theNMI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 397. The remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function. Table5-1.SignalsforSystemControl&Clocks(100LQFP) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Non-maskable interrupt.TTLIPB7 (4)89NMI Main oscillator crystal input or an external clock reference input. AnalogIfixed48OSC0 Main oscillator crystal output. Leave unconnected when using a single-ended clock source. AnalogOfixed49OSC1 System reset input.TTLIfixed64RST a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table5-2.SignalsforSystemControl&Clocks(108BGA) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Non-maskable interrupt.TTLIPB7 (4)A8NMI Main oscillator crystal input or an external clock reference input. AnalogIfixedL11OSC0 Main oscillator crystal output. Leave unconnected when using a single-ended clock source. AnalogOfixedM11OSC1 System reset input.TTLIfixedH11RST a. The TTL designation indicates the pin has TTL-compatible voltage levels.

5.2 FunctionalDescription

The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 200 199March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ Local control, such as reset (see “Reset Control” on page 200), power (see “Power Control” on page 205) and clock control (see “Clock Control” on page 206) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 213

5.2.1 DeviceIdentification

Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, Flash memory size, and other features. See theDID0(page 217),DID1 (page 245),DC0-DC9(page 247) andNVMSTAT(page 268) registers.

5.2.2 ResetControl

This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence.

5.2.2.1 ResetSources

The LM3S9B92 microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 201). 2. External reset input pin (RST ) assertion (see page 201). 3. Internal brown-out (BOR) detector (see page 203). 4. Software-initiated reset (with the software reset registers) (see page 204). 5. A watchdog timer reset condition violation (see page 204). 6. MOSC failure (see page 205). Table 5-3 provides a summary of results of the various reset operations. Table5-3.ResetSources On-ChipPeripheralsReset?JTAGReset?CoreReset?ResetSource YesYesYesPower-On Reset YesYesYesRST YesYesYesBrown-Out Reset YesYesYesSoftware System Request Reset using theSYSRESREQ bit in theAPINTregister. NoYesYesSoftware System Request Reset using theVECTRESET bit in theAPINTregister. YesaYesNoSoftware Peripheral Reset YesYesYesWatchdog Reset YesYesYesMOSC Failure Reset a. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, theResetCause(RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, in which case, all the bits in theRESCregister are cleared except for the POR indicator. A bit in theRESCregister can be cleared by writing a 0. March 19, 2011200 Texas Instruments-Advance Information System Control

At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal as configured in theBoot Configuration(BOOTCFG) register. At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFGregister is read. If theEN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is valid data at address 0x0000.0004, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. For example, if theBOOTCFGregister is written and committed with the value of 0x0000.3C01, then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. IfPB7 is Low, the core unconditionally begins executing the ROM boot loader. IfPB7 is High, then the application in Flash memory is executed if the reset vector at location 0x0000.0004 is not 0xFFFF.FFFF. Otherwise, the ROM boot loader is executed.

5.2.2.2 Power-OnReset(POR)

Note: The JTAG controller can only be reset by the power-on reset and the brown-out reset. The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete (see “Power and Brown-out Characteristics” on page 1302). For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, theRST input may be used as discussed in “External RSTPin” on page 201. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset timing is shown in Figure 26-4 on page 1303.

5.2.2.3 ExternalRST

Note: It is recommended that the trace for theRST signal must be kept as short as possible. Be sure to place any components connected to theRST signal as close to the microcontroller as possible. 201March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

If the application only uses the internal POR circuit, theRST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 202. Figure5-1.BasicRST Configuration PU RST Stellaris® R VDD RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see “JTAG Interface” on page 187). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see “Reset” on page 1306). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, theRST input may be connected to an RC network as shown in Figure 5-2 on page 202. Figure5-2.ExternalCircuitrytoExtendPower-OnReset PU C 1 RST Stellaris® R VDD RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF If the application requires the use of an external reset switch, Figure 5-3 on page 203 shows the proper circuitry to use. March 19, 2011202 Texas Instruments-Advance Information System Control

Figure5-3.ResetCircuitControlledbySwitch PU C 1 R S RST Stellaris® R VDD Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 26-10 on page 1306.

5.2.2.4 Brown-OutReset(BOR)

Note: The JTAG controller can only be reset by the power-on reset and the brown-out reset. The microcontroller provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate an interrupt or a system reset. The default condition is to generate an interrupt, so BOR must be enabled. Brown-out resets are controlled with thePower-OnandBrown-OutReset Control(PBORCTL) register. TheBORIOR bit in thePBORCTLregister must be set for a brown-out condition to trigger a reset; ifBORIOR is clear, an interrupt is generated. When a Brown-out condition occurs during a Flash PROGRAM or ERASE operation, a full system reset is always triggered without regard to the setting in thePBORCTLregister. The brown-out reset sequence is as follows: 1. When VDD drops below VBTH, an internal BOR condition is set. 2. If the BOR condition exists, an internal reset is asserted. 3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. 4. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being set before software has a chance to investigate the original cause. The result of a brown-out reset is equivalent to that of an assertion of the externalRST input, and the reset is held active until the proper VDD level is restored. TheRESCregister can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 26-5 on page 1303. 203March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

5.2.2.5 SoftwareReset

Software can reset a specific peripheral or generate a reset to the entire microcontroller. Peripherals can be individually reset by software via three registers that control reset signals to each on-chip peripheral (see theSRCRnregisters, page 295). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 213). The entire microcontroller, including the core, can be reset by software by setting theSYSRESREQ bit in theApplicationInterruptandResetControl(APINT) register. The software-initiated system reset sequence is as follows: 1. A software microcontroller reset is initiated by setting theSYSRESREQ bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The core only can be reset by software by setting theVECTRESET bit in theAPINTregister. The software-initiated core reset sequence is as follows: 1. A core reset is initiated by setting theVECTRESET bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 26-11 on page 1306.

5.2.2.6 WatchdogTimerReset

The Watchdog Timer module's function is to prevent system hangs. The LM3S9B92 microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module operates in the same manner except that because the PIOSC watchdog timer module is in a different clock domain, register accesses must have a time delay between them. The watchdog timer can be configured to generate an interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out. After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of the WatchdogTimerLoad(WDTLOAD) register and resumes counting down from that value. If the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. March 19, 2011204 Texas Instruments-Advance Information System Control

1. The internal reset is released and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. For more information on the Watchdog Timer module, see “Watchdog Timers” on page 572. The watchdog reset timing is shown in Figure 26-12 on page 1307.

5.2.3 Non-MaskableInterrupt

The microcontroller has three sources of non-maskable interrupt (NMI): ■ The assertion of theNMI signal ■ A main oscillator verification error ■ The NMISET bit in theInterruptControlandState(INTCTRL) register in the Cortex™-M3 (see page 152). Software must check the cause of the interrupt in order to distinguish among the sources.

5.2.3.1 NMIPin

The NMI signal is the alternate function for GPIO port pinPB7. The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs (GPIOs)” on page 397. Note that enabling the NMI alternate function requires the use of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see page 435. The active sense of theNMI signal is High; asserting the enabledNMI signal above VIH initiates the NMI interrupt sequence.

5.2.3.2 MainOscillatorVerificationFailure

The LM3S9B92 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, a power-on reset is generated and control is transferred to the NMI handler. The NMI handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. The detection circuit is enabled by setting theCVAL bit in theMainOscillatorControl(MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator fail status (MOSCFAIL) bit in theResetCause(RESC) register. The main oscillator verification circuit action is described in more detail in “Main Oscillator Verification Circuit” on page 212.

5.2.4 PowerControl

The Stellaris® microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture. An external regulator may be used instead of the on-chip LDO, but must meet the requirements in Table 26-20 on page 1302. Regardless of the LDO implementation, the internal LDO requires decoupling capacitors as specified in “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 1295. Note: VDDA must be supplied with 3.3 V, or the microcontroller does not function properly.VDDA is the supply for all of the analog circuitry on the device, including the clock circuitry. 205March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure5-4.PowerArchitecture Analog Circuits I/O Buf fers Low-Noise LDO Internal Logic and PLL GND GNDA GNDA VDDA VDDA VDDC VDDC LDO +3.3V GND GND GNDVDD VDD

5.2.5 ClockControl

System control determines the control of clocks in this part.

5.2.5.1 FundamentalClockSources

There are multiple clock sources for use in the microcontroller: ■ PrecisionInternalOscillator(PIOSC). The precision internal oscillator is an on-chip clock source that is the clock source the microcontroller uses during and following POR. It does not require the use of any external components and provides a clock that is 16 MHz ±1% at room temperature and ±3% across temperature. The PIOSC allows for a reduced system cost in applications that require an accurate clock source. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ MainOscillator(MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to theOSC0 input pin, or an external crystal is connected across theOSC0 input andOSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz to 16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz to 16.384 MHz. The single-ended clock source range is from DC March 19, 2011206 Texas Instruments-Advance Information System Control

through the specified speed of the microcontroller. The supported crystals are listed in theXTAL bit field in theRCCregister (see page 228). Note that the MOSC provides the clock source for the USB PLL and must be connected to a crystal or an oscillator. ■ Internal30-kHzOscillator. The internal 30-kHz oscillator provides an operational frequency of 30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the MOSC to be powered down. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz (inclusive). Table 5-4 on page 207 shows how the various clock sources can be used in a system. Table5-4.ClockSourceOptions UsedasSysClk?DrivePLL?ClockSource BYPASS = 1,OSCSRC = 0x1YesBYPASS = 0,OSCSRC = 0x1 YesPrecision Internal Oscillator BYPASS = 1,OSCSRC = 0x2Yes-NoPrecision Internal Oscillator divide by 4 (4 MHz ± 1%) BYPASS = 1,OSCSRC = 0x0YesBYPASS = 0,OSCSRC = 0x0 YesMain Oscillator BYPASS = 1,OSCSRC = 0x3Yes-NoInternal 30-kHz Oscillator

5.2.5.2 ClockConfiguration

The Run-ModeClockConfiguration(RCC) and Run-ModeClockConfiguration2(RCC2) registers provide control for the system clock. TheRCC2register is provided to extend fields that offer additional encodings over theRCCregister. When used, theRCC2register field values are used by the logic over the corresponding field in theRCCregister. In particular,RCC2provides for a larger assortment of clock configuration options. These registers control the following clock functionality: ■ Source of clocks in sleep and deep-sleep modes ■ System clock derived from PLL or other clock source ■ Enabling/disabling of oscillators and PLL ■ Clock divisors ■ Crystal input selection Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation. The PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more range (set withPWMDIV in RCC). Note: When the ADC module is in operation, the system clock must be at least 16 MHz. When the USB module is in operation, MOSC must be provided with a clock source, and the system clock must be at least 20 MHz. 207March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure5-5.MainClockTree Main OSC Precision Internal OSC ( 16 MHz) Internal OSC ( 30 kHz) ÷ 4 ÷ 25 PWRDN ADC Clock System Clock MOSCDIS a IOSCDIS a SYSDIV e USESYSDIV a,d PWMDW a USEPWMDIV a PWM Clock Hibernation OSC ( 32.768 kHz) OSCSRC b,d BYP ASS b,d XT AL a PWRDN b ÷ 2 USB PLL ( 480 MHz) ÷ 4 USB Clock XT AL a USBPWRDN c RXINT RXFRAC I S Receive MCLK I S T ransmit MCLK PLL ( 400 MHz) TXINT TXFRAC a. Control provided by RCC register bit/field. b . Control provided by RCC register bit/field or RCC 2 register bit/field, if overridden with RCC 2 register bit USERCC 2 . c . Control provided by RCC 2 register bit/field. d . Also may be controlled by DSLPCLKCFG when in deep sleep mode. e . Control provided by RCC register SYSDIV field, RCC 2 register SYSDIV 2 field if overridden with USERCC 2 bit, or [ SYSDIV 2 , SYSDIV 2 LSB ] if both USERCC 2 and DIV 400 bits are set. DIV400 c Note: The figure above shows all features available on all Stellaris® Tempest-class microcontrollers. Not all peripherals may be available on this device. Using the SYSDIV and SYSDIV2 Fields In theRCCregister, theSYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how theBYPASS bit in this register March 19, 2011208 Texas Instruments-Advance Information System Control

is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-5 shows how theSYSDIV encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). The divisor is equivalent to theSYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-4 on page 207. Table5-5.PossibleSystemClockFrequenciesUsingtheSYSDIVField StellarisWareParameteraFrequency(BYPASS=1)Frequency(BYPASS=0)DivisorSYSDIV SYSCTL_SYSDIV_1bClock source frequency/2reserved/10x0 SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x1 SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x2 SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x3 SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x4 SYSCTL_SYSDIV_6Clock source frequency/633.33 MHz/60x5 SYSCTL_SYSDIV_7Clock source frequency/728.57 MHz/70x6 SYSCTL_SYSDIV_8Clock source frequency/825 MHz/80x7 SYSCTL_SYSDIV_9Clock source frequency/922.22 MHz/90x8 SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x9 SYSCTL_SYSDIV_11Clock source frequency/1118.18 MHz/110xA SYSCTL_SYSDIV_12Clock source frequency/1216.67 MHz/120xB SYSCTL_SYSDIV_13Clock source frequency/1315.38 MHz/130xC SYSCTL_SYSDIV_14Clock source frequency/1414.29 MHz/140xD SYSCTL_SYSDIV_15Clock source frequency/1513.33 MHz/150xE SYSCTL_SYSDIV_16Clock source frequency/1612.5 MHz (default)/160xF a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. The SYSDIV2 field in theRCC2register is 2 bits wider than theSYSDIV field in theRCCregister so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to theSYSDIV2 encoding plus 1. Table 5-6 shows how theSYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-4 on page 207. Table5-6.ExamplesofPossibleSystemClockFrequenciesUsingtheSYSDIV2Field StellarisWareParameteraFrequency(BYPASS2=1)Frequency (BYPASS2=0) DivisorSYSDIV2 SYSCTL_SYSDIV_1bClock source frequency/2reserved/10x00 SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x01 SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x02 SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x03 SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x09 SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x09 209March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table5-6.ExamplesofPossibleSystemClockFrequenciesUsingtheSYSDIV2Field (continued) StellarisWareParameteraFrequency(BYPASS2=1)Frequency (BYPASS2=0) DivisorSYSDIV2 SYSCTL_SYSDIV_64Clock source frequency/643.125 MHz/640x3F a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. To allow for additional frequency choices when using the PLL, theDIV400 bit is provided along with theSYSDIV2LSB bit. When theDIV400 bit is set, bit 22 becomes the LSB forSYSDIV2. In this situation, the divisor is equivalent to the (SYSDIV2encoding withSYSDIV2LSB appended) plus one. Table 5-7 shows the frequency choices whenDIV400 is set. When theDIV400 bit is clear, SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table 5-6 on page 209. Table5-7.ExamplesofPossibleSystemClockFrequencieswithDIV400=1 StellarisWareParameterbFrequency(BYPASS2=0)aDivisorSYSDIV2LSBSYSDIV2 -reserved/2reserved0x00 -reserved/30 0x01 -reserved/41 SYSCTL_SYSDIV_2_580 MHz/50 0x02 SYSCTL_SYSDIV_366.67 MHz/61 -reserved/70 0x03 SYSCTL_SYSDIV_450 MHz/81 SYSCTL_SYSDIV_4_544.44 MHz/90 0x04 SYSCTL_SYSDIV_540 MHz/101 SYSCTL_SYSDIV_63_53.15 MHz/1270 0x3F SYSCTL_SYSDIV_643.125 MHz/1281 a. Note thatDIV400 and SYSDIV2LSB are only valid whenBYPASS2=0. b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.

5.2.5.3 PrecisionInternalOscillatorOperation(PIOSC)

The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC must remain enabled as it is used for internal functions. The PIOSC can only be disabled during Deep-Sleep mode. It can be powered down by setting theIOSCDIS bit in theRCCregister. The PIOSC generates a 16-MHz clock with a ±1% accuracy at room temperatures. Across the extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at room temperature, however, the frequency can be trimmed for other voltage or temperature conditions using software in one of two ways: ■ Default calibration: clear theUTEN bit and set theUPDATE bit in thePrecisionInternalOscillator Calibration(PIOSCCAL) register. ■ User-defined calibration: The user can program theUT value to adjust the PIOSC frequency. As the UT value increases, the generated period increases. To commit a newUT value, first set the March 19, 2011210 Texas Instruments-Advance Information System Control

UTEN bit, then program theUT field, and then set theUPDATE bit. The adjustment finishes within a few clock periods and is glitch free.

5.2.5.4 CrystalConfigurationfortheMainOscillator(MOSC)

The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise, the range of supported crystals is 1 to 16.384 MHz. The XTAL bit in theRCCregister (see page 228) describes the available crystal choices and default programming values. Software configures theRCCregister XTAL field with the crystal number. If the PLL is used in the design, theXTAL field value is internally translated to the PLL settings.

5.2.5.5 MainPLLFrequencyConfiguration

The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor, unless theDIV400 bit in theRCC2register is set. To configure the PIOSC to be the clock source for the main PLL, program theOSCRC2 field in the Run-ModeClockConfiguration2(RCC2) register to be 0x1. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in theXTALtoPLLTranslation (PLLCFG)register (see page 233). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 26-14 on page 1301 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in theRun-ModeClockConfiguration(RCC) register (see page 228) describes the available crystal choices and default programming of thePLLCFGregister. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated.

5.2.5.6 USBPLLFrequencyConfiguration

The USB PLL is disabled by default during power-on reset and is enabled later by software. The USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock reference for the USB PLL. The USB PLL is enabled by clearing theUSBPWRDN bit of theRCC2 register. TheXTAL bit field (Crystal Value) of theRCCregister describes the available crystal choices. The main oscillator must be connected to one of the following crystal values in order to correctly generate the USB clock: 4, 5, 6, 8, 10, 12, or 16 MHz. Only these crystals provide the necessary USB PLL VCO frequency to conform with the USB timing specifications.

5.2.5.7 PLLModes

Both PLLs have two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using theRCC/RCC2register fields (see page 228 and page 236). 211March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

5.2.5.8 PLLOperation

If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 26-13 on page 1300). During the relock time, the affected PLL is not usable as a clock reference. Either PLL is changed by one of the following: ■ Change to theXTAL value in theRCCregister—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter clocked by the system clock is used to measure the TREADY requirement. If the system clock is the main oscillator and it is running off an 8.192 MHz or slower external oscillator clock, the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz). If the system clock is running off the PIOSC or an external oscillator clock that is faster than 8.192 MHz, the down counter is set to 0x2400. Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before theRCC/RCC2register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the microcontroller from the oscillator selected by theRCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling thePLLLRIS bit in theRawInterruptStatus(RIS) register, and enabling the PLL Lock interrupt. The USB PLL is not protected during the lock time (TREADY), and software should ensure that the USB PLL has locked before using the interface. Software can use many methods to ensure the TREADY period has passed, including periodically polling theUSBPLLLRIS bit in theRawInterrupt Status(RIS) register, and enabling the USB PLL Lock interrupt.

5.2.5.9 MainOscillatorVerificationCircuit

The clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. The detection circuit is enabled using theCVAL bit in theMainOscillatorControl(MOSCCTL) register. If this circuit is enabled and detects an error, the following sequence is performed by the hardware: 1. The MOSCFAIL bit in theResetCause(RESC) register is set. 2. If the internal oscillator (PIOSC) is disabled, it is enabled. 3. The system clock is switched from the main oscillator to the PIOSC. 4. An internal power-on reset is initiated that lasts for 32 PIOSC periods. 5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence. if theMOSCIM bit in theMOSCCTLregister is set, then the following sequence is performed by the hardware: 1. The system clock is switched from the main oscillator to the PIOSC. March 19, 2011212 Texas Instruments-Advance Information System Control

1. The MOFRIS bit in theRISregister is set to indicate a MOSC failure.

5.2.6 SystemControl

For power-savings purposes, theRCGCn, SCGCn, andDCGCnregisters control the clock gating logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively. There must be a delay of 3 system clocks after a peripheral module clock is enabled in theRCGCregister before any module registers are accessed. There are three levels of operation for the microcontroller defined as: ■ Run mode ■ Sleep mode ■ Deep-Sleep mode The following sections describe the different modes in detail. Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their Run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface.

5.2.6.1 RunMode

In Run mode, the microcontroller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by theRCGCnregisters. The system clock can be any of the available clock sources including the PLL.

5.2.6.2 SleepMode

In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M3 core executing aWFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 116 for more details. Peripherals are clocked that are enabled in theSCGCnregisters when auto-clock gating is enabled (see theRCCregister) or theRCGCnregisters when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode.

5.2.6.3 Deep-SleepMode

In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns 213March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first setting theSLEEPDEEP bit in theSystem Control(SYSCTRL) register (see page 158) and then executing a WFI instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 116 for more details. The Cortex-M3 processor core and the memory subsystem are not clocked in Deep-Sleep mode. Peripherals are clocked that are enabled in theDCGCnregisters when auto-clock gating is enabled (see theRCCregister) or theRCGCnregisters when auto-clock gating is disabled. The system clock source is specified in theDSLPCLKCFGregister. When theDSLPCLKCFGregister is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides the SYSDIV field of the activeRCC/RCC2register, to be determined by theDSDIVORIDE setting in theDSLPCLKCFGregister, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during Deep-Sleep. See page 240.

5.3 InitializationandConfiguration

The PLL is configured using direct register writes to theRCC/RCC2register. If theRCC2register is being used, theUSERCC2 bit must be set and the appropriateRCC2bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting theBYPASS bit and clearing theUSESYS bit in theRCCregister, thereby configuring the microcontroller to run off a “raw” clock source and allowing for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear thePWRDN bit in RCC/RCC2. Setting theXTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing thePWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) inRCC/RCC2and set theUSESYS bit inRCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling thePLLLRIS bit in theRawInterruptStatus(RIS ) register. 5. Enable use of the PLL by clearing theBYPASS bit inRCC/RCC2.

5.4 RegisterMap

Table 5-8 on page 215 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Additional Flash and ROM registers defined in the System Control register space are described in the “Internal Memory” on page 302. March 19, 2011214 Texas Instruments-Advance Information System Control

Table5-8.SystemControlRegisterMap See pageDescriptionResetTypeNameOffset 217Device Identification 0-RODID00x000 245Device Identification 1-RODID10x004 247Device Capabilities 00x017F.007FRODC00x008 248Device Capabilities 1-RODC10x010 250Device Capabilities 20x570F.5337RODC20x014 252Device Capabilities 30xBFFF.FFFFRODC30x018 255Device Capabilities 40x5000.F1FFRODC40x01C 257Device Capabilities 50x0F30.00FFRODC50x020 259Device Capabilities 60x0000.0013RODC60x024 260Device Capabilities 70xFFFF.FFFFRODC70x028 264Device Capabilities 8 ADC Channels0xFFFF.FFFFRODC80x02C 219Brown-Out Reset Control0x0000.7FFDR/WPBORCTL0x030 295Software Reset Control 00x00000000R/WSRCR00x040 297Software Reset Control 10x00000000R/WSRCR10x044 300Software Reset Control 20x00000000R/WSRCR20x048 220Raw Interrupt Status0x0000.0000RORIS0x050 222Interrupt Mask Control0x0000.0000R/WIMC0x054 224Masked Interrupt Status and Clear0x0000.0000R/W1CMISC0x058 226Reset Cause-R/WRESC0x05C 228Run-Mode Clock Configuration0x078E.3AD1R/WRCC0x060 233XTAL to PLL Translation-ROPLLCFG0x064 234GPIO High-Performance Bus Control0x0000.0000R/WGPIOHBCTL0x06C 236Run-Mode Clock Configuration 20x07C0.6810R/WRCC20x070 239Main Oscillator Control0x0000.0000R/WMOSCCTL0x07C 269Run Mode Clock Gating Control Register 00x00000040R/WRCGC00x100 277Run Mode Clock Gating Control Register 10x00000000R/WRCGC10x104 286Run Mode Clock Gating Control Register 20x00000000R/WRCGC20x108 272Sleep Mode Clock Gating Control Register 00x00000040R/WSCGC00x110 280Sleep Mode Clock Gating Control Register 10x00000000R/WSCGC10x114 289Sleep Mode Clock Gating Control Register 20x00000000R/WSCGC20x118 275Deep Sleep Mode Clock Gating Control Register 00x00000040R/WDCGC00x120 283Deep-Sleep Mode Clock Gating Control Register 10x00000000R/WDCGC10x124 215March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table5-8.SystemControlRegisterMap (continued) See pageDescriptionResetTypeNameOffset 292Deep Sleep Mode Clock Gating Control Register 20x00000000R/WDCGC20x128 240Deep Sleep Clock Configuration0x0780.0000R/WDSLPCLKCFG0x144 242Precision Internal Oscillator Calibration0x0000.0000R/WPIOSCCAL0x150 243I2S MCLK Configuration0x0000.0000R/WI2SMCLKCFG0x170 266Device Capabilities 9 ADC Digital Comparators0x00FF.00FFRODC90x190 268Non-Volatile Memory Information0x0000.0001RONVMSTAT0x1A0

5.5 RegisterDescriptions

All addresses given are relative to the System Control base address of 0x400F.E000. March 19, 2011216 Texas Instruments-Advance Information System Control

Register1:DeviceIdentification0(DID0),offset0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of theCLASS field in theDID0register and thePARTNO field in theDID1 register. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset - 16171819202122232425262728293031 CLASSreservedVERreserved ROROROROROROROROROROROROROROROROType 0010000000001000Reset 0123456789101112131415 MINORMAJOR ROROROROROROROROROROROROROROROROType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 DID0 Version This field defines theDID0register format version. The version number is numeric. The value of theVER field is encoded as follows (all other encodings are reserved): DescriptionValue Second version of theDID0register format.0x1 0x1ROVER30:28 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved27:24 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all microcontrollers in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior microcontrollers. The value of theCLASS field is encoded as follows (all other encodings are reserved): DescriptionValue Stellaris® Tempest-class microcontrollers0x04 0x04ROCLASS23:16 217March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Major Revision This field specifies the major revision number of the microcontroller. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: DescriptionValue Revision A (initial device)0x0 Revision B (first base layer revision)0x1 Revision C (second base layer revision)0x2 and so on. -ROMAJOR15:8 Minor Revision This field specifies the minor revision number of the microcontroller. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when theMAJOR field is changed. This field is numeric and is encoded as follows: DescriptionValue Initial device, or a major revision update.0x0 First metal layer change.0x1 Second metal layer change.0x2 and so on. -ROMINOR7:0 March 19, 2011218 Texas Instruments-Advance Information System Control

Register2:Brown-OutResetControl(PBORCTL),offset0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBORIORreserved ROR/WROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:2 BOR Interrupt or Reset DescriptionValue A Brown Out Event causes an interrupt to be generated to the interrupt controller. A Brown Out Event causes a reset of the microcontroller.1 0R/WBORIOR1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 219March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register3:RawInterruptStatus(RIS),offset0x050 This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in theInterruptMaskControl(IMC) register is set. Writing a 1 to the corresponding bit in theMaskedInterruptStatusandClear(MISC) register clears an interrupt status bit. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBORRISreservedPLLLRISUSBPLLLRISMOSCPUPRISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:9 MOSC Power Up Raw Interrupt Status DescriptionValue Sufficient time has passed for the MOSC to reach the expected frequency. The value for this power-up time is indicated by TMOSC_SETTLE. Sufficient time has not passed for the MOSC to reach the expected frequency. This bit is cleared by writing a 1 to theMOSCPUPMIS bit in theMISC register. 0ROMOSCPUPRIS8 USB PLL Lock Raw Interrupt Status DescriptionValue The USB PLL timer has reached TREADY indicating that sufficient time has passed for the USB PLL to lock. The USB PLL timer has not reached TREADY.0 This bit is cleared by writing a 1 to theUSBPLLLMIS bit in theMISC register. 0ROUSBPLLLRIS7 PLL Lock Raw Interrupt Status DescriptionValue The PLL timer has reached TREADY indicating that sufficient time has passed for the PLL to lock. The PLL timer has not reached TREADY.0 This bit is cleared by writing a 1 to thePLLLMIS bit in theMISCregister. 0ROPLLLRIS6 March 19, 2011220 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved5:2 Brown-Out Reset Raw Interrupt Status DescriptionValue A brown-out condition is currently active.1 A brown-out condition is not currently active.0 Note theBORIOR bit in thePBORCTLregister must be cleared to cause an interrupt due to a Brown Out Event. This bit is cleared by writing a 1 to theBORMIS bit in theMISCregister. 0ROBORRIS1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 221March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register4:InterruptMaskControl(IMC),offset0x054 This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in theRawInterruptStatus(RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBORIMreservedPLLLIMUSBPLLLIMMOSCPUPIMreserved ROR/WROROROROR/WR/WR/WROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:9 MOSC Power Up Interrupt Mask DescriptionValue An interrupt is sent to the interrupt controller when the MOSCPUPRIS bit in theRISregister is set. The MOSCPUPRIS interrupt is suppressed and not sent to the interrupt controller. 0R/WMOSCPUPIM8 USB PLL Lock Interrupt Mask DescriptionValue An interrupt is sent to the interrupt controller when the USBPLLLRIS bit in theRISregister is set. The USBPLLLRIS interrupt is suppressed and not sent to the interrupt controller. 0R/WUSBPLLLIM7 PLL Lock Interrupt Mask DescriptionValue An interrupt is sent to the interrupt controller when thePLLLRIS bit in theRISregister is set. The PLLLRIS interrupt is suppressed and not sent to the interrupt controller. 0R/WPLLLIM6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved5:2 March 19, 2011222 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Brown-Out Reset Interrupt Mask DescriptionValue An interrupt is sent to the interrupt controller when theBORRIS bit in theRISregister is set. The BORRIS interrupt is suppressed and not sent to the interrupt controller. 0R/WBORIM1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 223March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register5:MaskedInterruptStatusandClear(MISC),offset0x058 On a read, this register gives the current masked status value of the corresponding interrupt in the RawInterruptStatus(RIS) register. All of the bits are R/W1C, thus writing a 1 to a bit clears the corresponding raw interrupt bit in theRISregister (see page 220). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBORMISreservedPLLLMISUSBPLLLMISMOSCPUPMISreserved ROR/W1CROROROROR/W1CR/W1CR/W1CROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:9 MOSC Power Up Masked Interrupt Status DescriptionValue When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the MOSC PLL to lock. Writing a 1 to this bit clears it and also theMOSCPUPRIS bit in the RISregister. When read, a 0 indicates that sufficient time has not passed for the MOSC PLL to lock. A write of 0 has no effect on the state of this bit. 0R/W1CMOSCPUPMIS8 USB PLL Lock Masked Interrupt Status DescriptionValue When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the USB PLL to lock. Writing a 1 to this bit clears it and also theUSBPLLLRIS bit in the RISregister. When read, a 0 indicates that sufficient time has not passed for the USB PLL to lock. A write of 0 has no effect on the state of this bit. 0R/W1CUSBPLLLMIS7 March 19, 2011224 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field PLL Lock Masked Interrupt Status DescriptionValue When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the PLL to lock. Writing a 1 to this bit clears it and also thePLLLRIS bit in the RISregister. When read, a 0 indicates that sufficient time has not passed for the PLL to lock. A write of 0 has no effect on the state of this bit. 0R/W1CPLLLMIS6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved5:2 BOR Masked Interrupt Status DescriptionValue When read, a 1 indicates that an unmasked interrupt was signaled because of a brown-out condition. Writing a 1 to this bit clears it and also theBORRIS bit in the RISregister. When read, a 0 indicates that a brown-out condition has not occurred. A write of 0 has no effect on the state of this bit. 0R/W1CBORMIS1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 225March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register6:ResetCause(RESC),offset0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other thanPOR in theRESCregister are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset - 16171819202122232425262728293031 MOSCFAILreserved R/WROROROROROROROROROROROROROROROType -000000000000000Reset 0123456789101112131415 EXTPORBORWDT0SWWDT1reserved R/WR/WR/WR/WR/WR/WROROROROROROROROROROType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:17 MOSC Failure Reset DescriptionValue When read, this bit indicates that the MOSC circuit was enabled for clock validation and failed, generating a reset event. When read, this bit indicates that a MOSC failure has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. -R/WMOSCFAIL16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved15:6 Watchdog Timer 1 Reset DescriptionValue When read, this bit indicates that Watchdog Timer 1 timed out and generated a reset. When read, this bit indicates that Watchdog Timer 1 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. -R/WWDT15 March 19, 2011226 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Software Reset DescriptionValue When read, this bit indicates that a software reset has caused a reset event. When read, this bit indicates that a software reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. -R/WSW4 Watchdog Timer 0 Reset DescriptionValue When read, this bit indicates that Watchdog Timer 0 timed out and generated a reset. When read, this bit indicates that Watchdog Timer 0 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. -R/WWDT03 Brown-Out Reset DescriptionValue When read, this bit indicates that a brown-out reset has caused a reset event. When read, this bit indicates that a brown-out reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. -R/WBOR2 Power-On Reset DescriptionValue When read, this bit indicates that a power-on reset has caused a reset event. When read, this bit indicates that a power-on reset has not generated a reset. Writing a 0 to this bit clears it. -R/WPOR1 External Reset DescriptionValue When read, this bit indicates that an external reset (RST assertion) has caused a reset event. When read, this bit indicates that an external reset (RST assertion) has not caused a reset event since the previous power-on reset. Writing a 0 to this bit clears it. -R/WEXT0 227March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register7:Run-ModeClockConfiguration(RCC),offset0x060 The bits in this register configure the system clock and oscillators. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x078E.3AD1 16171819202122232425262728293031 reservedPWMDIVUSEPWMDIVreservedUSESYSDIVSYSDIVACGreserved ROR/WR/WR/WR/WROR/WR/WR/WR/WR/WR/WROROROROType 0111000111100000Reset 0123456789101112131415 MOSCDISIOSCDISreservedOSCSRCXTALBYPASSreservedPWRDNreserved R/WR/WROROR/WR/WR/WR/WR/WR/WR/WR/WROR/WROROType 1000101101011100Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:28 Auto Clock Gating This bit specifies whether the system uses theSleep-ModeClock GatingControl(SCGCn) registers andDeep-Sleep-ModeClock GatingControl(DCGCn) registers if the microcontroller enters a Sleep or Deep-Sleep mode (respectively). DescriptionValue The SCGCnor DCGCnregisters are used to control the clocks distributed to the peripherals when the microcontroller is in a sleep mode. TheSCGCnand DCGCnregisters allow unused peripherals to consume less power when the microcontroller is in a sleep mode. The Run-ModeClockGatingControl(RCGCn) registers are used when the microcontroller enters a sleep mode. The RCGCnregisters are always used to control the clocks in Run mode. 0R/WACG27 System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how theBYPASS bit in this register is configured). See Table 5-5 on page 209 for bit encodings. If theSYSDIV value is less thanMINSYSDIV (see page 248), and the PLL is being used, then theMINSYSDIV value is used as the divisor. If the PLL is not being used, theSYSDIV value can be less than MINSYSDIV. 0xFR/WSYSDIV26:23 March 19, 2011228 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Enable System Clock Divider DescriptionValue The system clock divider is the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If theUSERCC2 bit in theRCC2register is set, then theSYSDIV2 field in theRCC2register is used as the system clock divider rather than theSYSDIV field in this register. The system clock is used undivided.0 0R/WUSESYSDIV22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved21 Enable PWM Clock Divisor DescriptionValue The PWM clock divider is the source for the PWM clock.1 The system clock is the source for the PWM clock.0 Note that when the PWM divisor is used, it is applied to the clock for both PWM modules. 0R/WUSEPWMDIV20 PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. The rising edge of this clock is synchronous with the system clock. DivisorValue /2 0x0 /4 0x1 /8 0x2 /16 0x3 /32 0x4 /64 0x5 /64 0x6 /64 (default)0x7 0x7R/WPWMDIV19:17 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved16:14 PLL Power Down DescriptionValue The PLL is powered down. Care must be taken to ensure that another clock source is functioning and that theBYPASS bit is set before setting this bit. The PLL is operating normally.0 1R/WPWRDN13 229March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1ROreserved12 PLL Bypass DescriptionValue The system clock is derived from the OSC source and divided by the divisor specified bySYSDIV. The system clock is the PLL output clock divided by the divisor specified bySYSDIV. See Table 5-5 on page 209 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. 1R/WBYPASS11 March 19, 2011230 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Depending on the crystal used, the PLL frequency may not be exactly 400 MHz, see Table 26-14 on page 1301 for more information. Frequencies that may be used with the USB interface are indicated in the table. To function within the clocking requirements of the USB specification, a crystal of 4, 5, 6, 8, 10, 12, or 16 MHz must be used. Crystal Frequency (MHz) Using the PLL Crystal Frequency (MHz) Not Using the PLL Value reserved1.000 MHz0x00 reserved1.8432 MHz0x01 reserved2.000 MHz0x02 reserved2.4576 MHz0x03

3.579545 MHz0x04

3.6864 MHz0x05

4 MHz (USB)0x06

4.096 MHz0x07

4.9152 MHz0x08

5 MHz (USB)0x09

5.12 MHz0x0A

6 MHz (reset value)(USB)0x0B

6.144 MHz0x0C

7.3728 MHz0x0D

8 MHz (USB)0x0E

8.192 MHz0x0F

10.0 MHz (USB)0x10

12.0 MHz (USB)0x11

12.288 MHz0x12

13.56 MHz0x13

14.31818 MHz0x14

16.0 MHz (USB)0x15

16.384 MHz0x16

0x0BR/WXTAL10:6 231March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Oscillator Source Selects the input source for the OSC. The values are: Input SourceValue MOSC Main oscillator 0x0 PIOSC Precision internal oscillator (default) 0x1 PIOSC/4 Precision internal oscillator / 4 0x2 30 kHz 30-kHz internal oscillator 0x3 For additional oscillator sources, see theRCC2register. 0x1R/WOSCSRC5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:2 Precision Internal Oscillator Disable DescriptionValue The precision internal oscillator (PIOSC) is disabled.1 The precision internal oscillator is enabled.0 0R/WIOSCDIS1 Main Oscillator Disable DescriptionValue The main oscillator is disabled (default).1 The main oscillator is enabled.0 1R/WMOSCDIS0 March 19, 2011232 Texas Instruments-Advance Information System Control

Register8:XTALtoPLLTranslation(PLLCFG),offset0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that theXTAL field changes in theRun-ModeClockConfiguration(RCC) register (see page 228). The PLL frequency is calculated using thePLLCFGfield values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RFreserved ROROROROROROROROROROROROROROROROType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:14 PLL F Value This field specifies the value supplied to the PLL’s F input. -ROF13:5 PLL R Value This field specifies the value supplied to the PLL’s R input. -ROR4:0 233March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register9:GPIOHigh-PerformanceBusControl(GPIOHBCTL),offset0x06C This register controls which internal bus is used to access each GPIO port. When a bit is clear, the corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and through the APB memory aperture. When a bit is set, the corresponding port is accessed across the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each GPIO port can be individually configured to use AHB or APB, but may be accessed only through one aperture. The AHB bus provides better back-to-back access performance than the APB bus. The address aperture in the memory map changes for the ports that are enabled for AHB access (see Table 8-7 on page 408). GPIO High-Performance Bus Control (GPIOHBCTL) Base 0x400F.E000 Offset 0x06C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PORTAPORTBPORTCPORTDPORTEPORTFPORTGPORTHPORTJreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:9 Port J Advanced High-Performance Bus This bit defines the memory aperture for Port J. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTJ8 Port H Advanced High-Performance Bus This bit defines the memory aperture for Port H. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTH7 Port G Advanced High-Performance Bus This bit defines the memory aperture for Port G. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTG6 March 19, 2011234 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Port F Advanced High-Performance Bus This bit defines the memory aperture for Port F. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTF5 Port E Advanced High-Performance Bus This bit defines the memory aperture for Port E. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTE4 Port D Advanced High-Performance Bus This bit defines the memory aperture for Port D. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTD3 Port C Advanced High-Performance Bus This bit defines the memory aperture for Port C. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTC2 Port B Advanced High-Performance Bus This bit defines the memory aperture for Port B. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTB1 Port A Advanced High-Performance Bus This bit defines the memory aperture for Port A. DescriptionValue Advanced High-Performance Bus (AHB)1 Advanced Peripheral Bus (APB). This bus is the legacy bus.0 0R/WPORTA0 235March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register10:Run-ModeClockConfiguration2(RCC2),offset0x070 This register overrides theRCCequivalent register fields, as shown in Table 5-9, when theUSERCC2 bit is set, allowing the extended capabilities of theRCC2register to be used while also providing a means to be backward-compatible to previous parts. EachRCC2field that supersedes anRCC field is located at the same LSB bit position; however, someRCC2fields are larger than the corresponding RCCfield. Table5-9.RCC2FieldsthatOverrideRCCFields OverridesRCCFieldRCC2Field... SYSDIV, bits[26:23]SYSDIV2, bits[28:23] PWRDN, bit[13]PWRDN2, bit[13] BYPASS, bit[11]BYPASS2, bit[11] OSCSRC, bits[5:4]OSCSRC2, bits[6:4] Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x07C0.6810 16171819202122232425262728293031 reservedSYSDIV2LSBSYSDIV2reservedDIV400USERCC2 ROROROROROROR/WR/WR/WR/WR/WR/WR/WROR/WR/WType 0000001111100000Reset 0123456789101112131415 reservedOSCSRC2reservedBYPASS2reservedPWRDN2USBPWRDNreserved ROROROROR/WR/WR/WROROROROR/WROR/WR/WROType 0000100000010110Reset DescriptionResetTypeNameBit/Field Use RCC2 DescriptionValue The RCC2register fields override theRCCregister fields.1 The RCCregister fields are used, and the fields inRCC2are ignored. 0R/WUSERCC231 Divide PLL as 400 MHz vs. 200 MHz This bit, along with theSYSDIV2LSB bit, allows additional frequency choices. DescriptionValue Append theSYSDIV2LSB bit to theSYSDIV2 field to create a 7 bit divisor using the 400 MHz PLL output, see Table 5-7 on page 210. Use SYSDIV2 as is and apply to 200 MHz predivided PLL output. See Table 5-6 on page 209 for programming guidelines. 0R/WDIV40030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved29 March 19, 2011236 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field System Clock Divisor 2 Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how theBYPASS2 bit is configured).SYSDIV2 is used for the divisor when both the USESYSDIV bit in theRCCregister and theUSERCC2 bit in this register are set. See Table 5-6 on page 209 for programming guidelines. 0x0FR/WSYSDIV228:23 Additional LSB forSYSDIV2 When DIV400 is set, this bit becomes the LSB ofSYSDIV2. IfDIV400 is clear, this bit is not used. See Table 5-6 on page 209 for programming guidelines. This bit can only be set or cleared whenDIV400 is set. 1R/WSYSDIV2LSB22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved21:15 Power-Down USB PLL DescriptionValue The USB PLL is powered down.1 The USB PLL operates normally.0 1R/WUSBPWRDN14 Power-Down PLL 2 DescriptionValue The PLL is powered down.1 The PLL operates normally.0 1R/WPWRDN213 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12 PLL Bypass 2 DescriptionValue The system clock is derived from the OSC source and divided by the divisor specified bySYSDIV2. The system clock is the PLL output clock divided by the divisor specified bySYSDIV2. See Table 5-6 on page 209 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. 1R/WBYPASS211 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved10:7 237March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Oscillator Source 2 Selects the input source for the OSC. The values are: DescriptionValue MOSC Main oscillator 0x0 PIOSC Precision internal oscillator 0x1 PIOSC/4 Precision internal oscillator / 4 0x2 30 kHz 30-kHz internal oscillator 0x3 Reserved0x4-0x7 0x1R/WOSCSRC26:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:0 March 19, 2011238 Texas Instruments-Advance Information System Control

Register11:MainOscillatorControl(MOSCCTL),offset0x07C This register provides the ability to enable the MOSC clock verification circuit. When enabled, this circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the NMI handler. Main Oscillator Control (MOSCCTL) Base 0x400F.E000 Offset 0x07C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CVALreserved R/WROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Clock Validation for MOSC DescriptionValue The MOSC monitor circuit is enabled.1 The MOSC monitor circuit is disabled.0 0R/WCVAL0 239March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register12:DeepSleepClockConfiguration(DSLPCLKCFG),offset0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 16171819202122232425262728293031 reservedDSDIVORIDEreserved ROROROROROROROR/WR/WR/WR/WR/WR/WROROROType 0000000111100000Reset 0123456789101112131415 reservedDSOSCSRCreserved ROROROROR/WR/WR/WROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:29 Divider Field Override If Deep-Sleep mode is enabled when the PLL is running, the PLL is disabled. This 6-bit field contains a system divider field that overrides the SYSDIV field in theRCCregister or theSYSDIV2 field in theRCC2 register during Deep Sleep. This divider is applied to the source selected by theDSOSCSRCfield. DescriptionValue /1 0x0 /2 0x1 /3 0x2 /4 0x3 /64 0x3F 0x0FR/WDSDIVORIDE28:23 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved22:7 March 19, 2011240 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Clock Source Specifies the clock source during Deep-Sleep mode. DescriptionValue MOSC Use the main oscillator as the source. 0x0 Note: If the PIOSC is being used as the clock reference for the PLL, the PIOSC is the clock source instead of MOSC in Deep-Sleep mode. PIOSC Use the precision internal 16-MHz oscillator as the source. 0x1 Reserved0x2 30 kHz Use the 30-kHz internal oscillator as the source. 0x3 Reserved0x4-0x7 0x0R/WDSOSCSRC6:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:0 241March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register13:PrecisionInternalOscillatorCalibration(PIOSCCAL),offset0x150 This register provides the ability to update or recalibrate the precision internal oscillator. Precision Internal Oscillator Calibration (PIOSCCAL) Base 0x400F.E000 Offset 0x150 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedUTEN ROROROROROROROROROROROROROROROR/WType 0000000000000000Reset 0123456789101112131415 UTreservedUPDATEreserved R/WR/WR/WR/WR/WR/WR/WROR/WROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Use User Trim Value DescriptionValue The trim value in bits[6:0] of this register are used for any update trim operation. The factory calibration value is used for an update trim operation.0 0R/WUTEN31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved30:9 Update Trim DescriptionValue Updates the PIOSC trim value with theUT bit. Used withUTEN.1 No action.0 This bit is auto-cleared after the update. 0R/WUPDATE8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 User Trim Value User trim value that can be loaded into the PIOSC. Refer to “Main PLL Frequency Configuration” on page 211 for more information on calibrating the PIOSC. 0x0R/WUT6:0 March 19, 2011242 Texas Instruments-Advance Information System Control

Register14:I 2SMCLKConfiguration(I2SMCLKCFG),offset0x170 This register configures the receive and transmit fractional clock dividers for the for the I2S master transmit and receive clocks (I2S0TXMCLK and I2S0RXMCLK). Varying the integer and fractional inputs for the clocks allows greater accuracy in hitting the target I2S clock frequencies. Refer to “Clock Control” on page 822 for combinations of theTXI and TXF bits and theRXI and RXF bits that provide MCLK frequencies within acceptable error limits. I2S MCLK Configuration (I2SMCLKCFG) Base 0x400F.E000 Offset 0x170 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 RXFRXIreservedRXEN R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROR/WType 0000000000000000Reset 0123456789101112131415 TXFTXIreservedTXEN R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field RX Clock Enable DescriptionValue The I2S receive clock generator is enabled.1 The I2S receive clock generator is disabled. If theRXSLV bit in theI2SModuleConfiguration(I2SCFG) register is set, then theI2S0RXMCLK must be externally generated. 0R/WRXEN31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved30 RX Clock Integer Input This field contains the integer input for the receive clock generator. 0x0R/WRXI29:20 RX Clock Fractional Input This field contains the fractional input for the receive clock generator. 0x0R/WRXF19:16 TX Clock Enable DescriptionValue The I2S transmit clock generator is enabled.1 The I2S transmit clock generator is disabled. If theTXSLV bit in theI2SModuleConfiguration(I2SCFG) register is set, then theI2S0TXMCLK must be externally generated. 0R/WTXEN15 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved14 243March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field TX Clock Integer Input This field contains the integer input for the transmit clock generator. 0x00R/WTXI13:4 TX Clock Fractional Input This field contains the fractional input for the transmit clock generator. 0x0R/WTXF3:0 March 19, 2011244 Texas Instruments-Advance Information System Control

Register15:DeviceIdentification1(DID1),offset0x004 This register identifies the device family, part number, temperature range, and package type. Each microcontroller is uniquely identified by the combined values of theCLASS field in theDID0register and thePARTNO field in theDID1register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset - 16171819202122232425262728293031 PARTNOFAMVER ROROROROROROROROROROROROROROROROType 0101011000001000Reset 0123456789101112131415 QUALROHSPKGTEMPreservedPINCOUNT ROROROROROROROROROROROROROROROROType DescriptionResetTypeNameBit/Field DID1 Version This field defines theDID1register format version. The version number is numeric. The value of theVER field is encoded as follows (all other encodings are reserved): DescriptionValue Second version of theDID1register format.0x1 0x1ROVER31:28 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): DescriptionValue Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. 0x0 0x0ROFAM27:24 Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): DescriptionValue LM3S9B920x6A 0x6AROPARTNO23:16 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): DescriptionValue 100-pin package0x2 0x2ROPINCOUNT15:13 245March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:8 Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): DescriptionValue Commercial temperature range (0°C to 70°C)0x0 Industrial temperature range (-40°C to 85°C)0x1 Extended temperature range (-40°C to 105°C)0x2 -ROTEMP7:5 Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): DescriptionValue SOIC package0x0 LQFP package0x1 BGA package0x2 -ROPKG4:3 RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1ROROHS2 Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): DescriptionValue Engineering Sample (unqualified)0x0 Pilot Production (unqualified)0x1 Fully Qualified0x2 -ROQUAL1:0 March 19, 2011246 Texas Instruments-Advance Information System Control

Register16:DeviceCapabilities0(DC0),offset0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x017F.007F 16171819202122232425262728293031 SRAMSZ ROROROROROROROROROROROROROROROROType 1111111010000000Reset 0123456789101112131415 FLASHSZ ROROROROROROROROROROROROROROROROType 1111111000000000Reset DescriptionResetTypeNameBit/Field SRAM Size Indicates the size of the on-chip SRAM memory. DescriptionValue

96 KB of SRAM0x017F

0x017FROSRAMSZ31:16 Flash Size Indicates the size of the on-chip flash memory. DescriptionValue

256 KB of Flash0x007F

0x007FROFLASHSZ15:0 247March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register17:DeviceCapabilities1(DC1),offset0x010 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset - 16171819202122232425262728293031 ADC0ADC1reservedPWMreservedCAN0CAN1reservedWDT1reserved ROROROROROROROROROROROROROROROROType 1100100011001000Reset 0123456789101112131415 JTAGSWDSWOWDT0PLLTEMPSNSreservedMPUMAXADC0SPDMAXADC1SPDMINSYSDIV ROROROROROROROROROROROROROROROROType 111111011111----Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 Watchdog Timer1 Present When set, indicates that watchdog timer 1 is present. 1ROWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:26 CAN Module 1 Present When set, indicates that CAN unit 1 is present. 1ROCAN125 CAN Module 0 Present When set, indicates that CAN unit 0 is present. 1ROCAN024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:21 PWM Module Present When set, indicates that the PWM module is present. 1ROPWM20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:18 ADC Module 1 Present When set, indicates that ADC module 1 is present. 1ROADC117 ADC Module 0 Present When set, indicates that ADC module 0 is present 1ROADC016 March 19, 2011248 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. DescriptionValue Specifies an 80-MHz CPU clock with a PLL divider of 2.5.0x1 Specifies a 66.67-MHz CPU clock with a PLL divider of 3.0x2 Specifies a 50-MHz CPU clock with a PLL divider of 4.0x3 Specifies a 25-MHz clock with a PLL divider of 8.0x7 Specifies a 20-MHz clock with a PLL divider of 10.0x9 -ROMINSYSDIV15:12 Max ADC1 Speed This field indicates the maximum rate at which the ADC samples data. DescriptionValue 1M samples/second0x3 0x3ROMAXADC1SPD11:10 Max ADC0 Speed This field indicates the maximum rate at which the ADC samples data. DescriptionValue 1M samples/second0x3 0x3ROMAXADC0SPD9:8 MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter for details on the MPU. 1ROMPU7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved6 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 1ROTEMPSNS5 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 1ROPLL4 Watchdog Timer 0 Present When set, indicates that watchdog timer 0 is present. 1ROWDT03 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 1ROSWO2 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 1ROSWD1 JTAG Present When set, indicates that the JTAG debugger interface is present. 1ROJTAG0 249March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register18:DeviceCapabilities2(DC2),offset0x014 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x570F.5337 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reservedI2S0reservedEPI0reserved ROROROROROROROROROROROROROROROROType 1111000011101010Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedQEI0QEI1reservedI2C0reservedI2C1reserved ROROROROROROROROROROROROROROROROType 1110110011001010Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 EPI Module 0 Present When set, indicates that EPI module 0 is present. 1ROEPI030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 I2S Module 0 Present When set, indicates that I2S module 0 is present. 1ROI2S028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. 1ROCOMP226 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 1ROCOMP125 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 1ROCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer Module 3 Present When set, indicates that General-Purpose Timer module 3 is present. 1ROTIMER319 Timer Module 2 Present When set, indicates that General-Purpose Timer module 2 is present. 1ROTIMER218 March 19, 2011250 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Timer Module 1 Present When set, indicates that General-Purpose Timer module 1 is present. 1ROTIMER117 Timer Module 0 Present When set, indicates that General-Purpose Timer module 0 is present. 1ROTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C Module 1 Present When set, indicates that I2C module 1 is present. 1ROI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 I2C Module 0 Present When set, indicates that I2C module 0 is present. 1ROI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:10 QEI Module 1 Present When set, indicates that QEI module 1 is present. 1ROQEI19 QEI Module 0 Present When set, indicates that QEI module 0 is present. 1ROQEI08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7:6 SSI Module 1 Present When set, indicates that SSI module 1 is present. 1ROSSI15 SSI Module 0 Present When set, indicates that SSI module 0 is present. 1ROSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART Module 2 Present When set, indicates that UART module 2 is present. 1ROUART22 UART Module 1 Present When set, indicates that UART module 1 is present. 1ROUART11 UART Module 0 Present When set, indicates that UART module 0 is present. 1ROUART00 251March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register19:DeviceCapabilities3(DC3),offset0x018 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0xBFFF.FFFF 16171819202122232425262728293031 ADC0AIN0ADC0AIN1ADC0AIN2ADC0AIN3ADC0AIN4ADC0AIN5ADC0AIN6ADC0AIN7CCP0CCP1CCP2CCP3CCP4CCP5reserved32KHZ ROROROROROROROROROROROROROROROROType 1111111111111101Reset 0123456789101112131415 PWM0PWM1PWM2PWM3PWM4PWM5C0MINUSC0PLUSC0OC1MINUSC1PLUSC1OC2MINUSC2PLUSC2OPWMFAULT ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. 1RO32KHZ31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved30 CCP5 Pin Present When set, indicates that Capture/Compare/PWM pin 5 is present. 1ROCCP529 CCP4 Pin Present When set, indicates that Capture/Compare/PWM pin 4 is present. 1ROCCP428 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 1ROCCP327 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 1ROCCP226 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 1ROCCP125 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 1ROCCP024 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. 1ROADC0AIN723 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. 1ROADC0AIN622 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. 1ROADC0AIN521 ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. 1ROADC0AIN420 March 19, 2011252 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. 1ROADC0AIN319 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. 1ROADC0AIN218 ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. 1ROADC0AIN117 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. 1ROADC0AIN016 PWM Fault Pin Present When set, indicates that a PWM Fault pin is present. See DC5 for specific Fault pins on this device. 1ROPWMFAULT15 C2o Pin Present When set, indicates that the analog comparator 2 output pin is present. 1ROC2O14 C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. 1ROC2PLUS13 C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. 1ROC2MINUS12 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. 1ROC1O11 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 1ROC1PLUS10 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 1ROC1MINUS9 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 1ROC0O8 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 1ROC0PLUS7 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 1ROC0MINUS6 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 1ROPWM55 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. 1ROPWM44 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 1ROPWM33 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 1ROPWM22 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 1ROPWM11 253March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 1ROPWM00 March 19, 2011254 Texas Instruments-Advance Information System Control

Register20:DeviceCapabilities4(DC4),offset0x01C This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x5000.F1FF 16171819202122232425262728293031 reservedEMAC0reservedEPHY0reserved ROROROROROROROROROROROROROROROROType 0000000000001010Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedROMUDMACCP6CCP7 ROROROROROROROROROROROROROROROROType 1111111110001111Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 Ethernet PHY Layer 0 Present When set, indicates that Ethernet PHY layer 0 is present. 1ROEPHY030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 Ethernet MAC Layer 0 Present When set, indicates that Ethernet MAC layer 0 is present. 1ROEMAC028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:16 CCP7 Pin Present When set, indicates that Capture/Compare/PWM pin 7 is present. 1ROCCP715 CCP6 Pin Present When set, indicates that Capture/Compare/PWM pin 6 is present. 1ROCCP614 Micro-DMA Module Present When set, indicates that the micro-DMA module present. 1ROUDMA13 Internal Code ROM Present When set, indicates that internal code ROM is present. 1ROROM12 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:9 GPIO Port J Present When set, indicates that GPIO Port J is present. 1ROGPIOJ8 255March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field GPIO Port H Present When set, indicates that GPIO Port H is present. 1ROGPIOH7 GPIO Port G Present When set, indicates that GPIO Port G is present. 1ROGPIOG6 GPIO Port F Present When set, indicates that GPIO Port F is present. 1ROGPIOF5 GPIO Port E Present When set, indicates that GPIO Port E is present. 1ROGPIOE4 GPIO Port D Present When set, indicates that GPIO Port D is present. 1ROGPIOD3 GPIO Port C Present When set, indicates that GPIO Port C is present. 1ROGPIOC2 GPIO Port B Present When set, indicates that GPIO Port B is present. 1ROGPIOB1 GPIO Port A Present When set, indicates that GPIO Port A is present. 1ROGPIOA0 March 19, 2011256 Texas Instruments-Advance Information System Control

Register21:DeviceCapabilities5(DC5),offset0x020 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 5 (DC5) Base 0x400F.E000 Offset 0x020 Type RO, reset 0x0F30.00FF 16171819202122232425262728293031 reservedPWMESYNCPWMEFLTreservedPWMFAULT0PWMFAULT1PWMFAULT2PWMFAULT3reserved ROROROROROROROROROROROROROROROROType 0000110011110000Reset 0123456789101112131415 PWM0PWM1PWM2PWM3PWM4PWM5PWM6PWM7reserved ROROROROROROROROROROROROROROROROType 1111111100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:28 PWM Fault 3 Pin Present When set, indicates that the PWM Fault 3 pin is present. 1ROPWMFAULT327 PWM Fault 2 Pin Present When set, indicates that the PWM Fault 2 pin is present. 1ROPWMFAULT226 PWM Fault 1 Pin Present When set, indicates that the PWM Fault 1 pin is present. 1ROPWMFAULT125 PWM Fault 0 Pin Present When set, indicates that the PWM Fault 0 pin is present. 1ROPWMFAULT024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:22 PWM Extended Fault Active When set, indicates that the PWM Extended Fault feature is active. 1ROPWMEFLT21 PWM Extended SYNC Active When set, indicates that the PWM Extended SYNC feature is active. 1ROPWMESYNC20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:8 PWM7 Pin Present When set, indicates that the PWM pin 7 is present. 1ROPWM77 PWM6 Pin Present When set, indicates that the PWM pin 6 is present. 1ROPWM66 257March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 1ROPWM55 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. 1ROPWM44 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 1ROPWM33 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 1ROPWM22 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 1ROPWM11 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 1ROPWM00 March 19, 2011258 Texas Instruments-Advance Information System Control

Register22:DeviceCapabilities6(DC6),offset0x024 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 6 (DC6) Base 0x400F.E000 Offset 0x024 Type RO, reset 0x0000.0013 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 USB0reservedUSB0PHYreserved ROROROROROROROROROROROROROROROROType 1100100000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:5 USB Module 0 PHY Present When set, indicates that the USB module 0 PHY is present. 1ROUSB0PHY4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3:2 USB Module 0 Present Thie field indicates that USB module 0 is present and specifies its capability. DescriptionValue USB0 is OTG.0x3 0x3ROUSB01:0 259March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register23:DeviceCapabilities7(DC7),offset0x028 This register is predefined by the part and can be used to verify uDMA channel features. A 1 indicates the channel is available on this device; a 0 that the channel is only available on other devices in the family. Most channels have primary and secondary assignments. If the primary function is not available on this microcontroller, the secondary function becomes the primary function. If the secondary function is not available, the primary function is the only option. Device Capabilities 7 (DC7) Base 0x400F.E000 Offset 0x028 Type RO, reset 0xFFFF.FFFF 16171819202122232425262728293031 DMACH16DMACH17DMACH18DMACH19DMACH20DMACH21DMACH22DMACH23DMACH24DMACH25DMACH26DMACH27DMACH28DMACH29DMACH30reserved ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 DMACH0DMACH1DMACH2DMACH3DMACH4DMACH5DMACH6DMACH7DMACH8DMACH9DMACH10DMACH11DMACH12DMACH13DMACH14DMACH15 ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field Reserved Reserved for uDMA channel 31. 1ROreserved31 SW When set, indicates uDMA channel 30 is available for software transfers. 1RODMACH3030 I2S0_TX / CAN1_TX When set, indicates uDMA channel 29 is available and connected to the transmit path of I2S module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of CAN module 1 transmit. 1RODMACH2929 I2S0_RX / CAN1_RX When set, indicates uDMA channel 28 is available and connected to the receive path of I2S module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of CAN module 1 receive. 1RODMACH2828 CAN1_TX / ADC1_SS3 When set, indicates uDMA channel 27 is available and connected to the transmit path of CAN module 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 1RODMACH2727 CAN1_RX / ADC1_SS2 When set, indicates uDMA channel 26 is available and connected to the receive path of CAN module 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 1RODMACH2626 March 19, 2011260 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field SSI1_TX / ADC1_SS1 When set, indicates uDMA channel 25 is available and connected to the transmit path of SSI module 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 1RODMACH2525 SSI1_RX / ADC1_SS0 When set, indicates uDMA channel 24 is available and connected to the receive path of SSI module 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 1RODMACH2424 UART1_TX / CAN2_TX When set, indicates uDMA channel 23 is available and connected to the transmit path of UART module 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of CAN module 2 transmit. 1RODMACH2323 UART1_RX / CAN2_RX When set, indicates uDMA channel 22 is available and connected to the receive path of UART module 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of CAN module 2 receive. 1RODMACH2222 Timer1B / EPI0_WFIFO When set, indicates uDMA channel 21 is available and connected to Timer 1B.If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of EPI module write FIFO (WRIFO). 1RODMACH2121 Timer1A / EPI0_NBRFIFO When set, indicates uDMA channel 20 is available and connected to Timer 1A. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of EPI module 0 non-blocking read FIFO (NBRFIFO). 1RODMACH2020 Timer0B / Timer1B When set, indicates uDMA channel 19 is available and connected to Timer 0B. If the corresponding bit in theDMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 1B. 1RODMACH1919 Timer0A / Timer1A When set, indicates uDMA channel 18 is available and connected to Timer 0A. If the corresponding bit in theDMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 1A. 1RODMACH1818 ADC0_SS3 When set, indicates uDMA channel 17 is available and connected to ADC module 0 Sample Sequencer 3. 1RODMACH1717 ADC0_SS2 When set, indicates uDMA channel 16 is available and connected to ADC module 0 Sample Sequencer 2. 1RODMACH1616 261March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field ADC0_SS1 / Timer2B When set, indicates uDMA channel 15 is available and connected to ADC module 0 Sample Sequencer 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 1RODMACH1515 ADC0_SS0 / Timer2A When set, indicates uDMA channel 14 is available and connected to ADC module 0 Sample Sequencer 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 1RODMACH1414 CAN0_TX / UART2_TX When set, indicates uDMA channel 13 is available and connected to the transmit path of CAN module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of UART module 2 transmit. 1RODMACH1313 CAN0_RX / UART2_RX When set, indicates uDMA channel 12 is available and connected to the receive path of CAN module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of UART module 2 receive. 1RODMACH1212 SSI0_TX / SSI1_TX When set, indicates uDMA channel 11 is available and connected to the transmit path of SSI module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of SSI module 1 transmit. 1RODMACH1111 SSI0_RX / SSI1_RX When set, indicates uDMA channel 10 is available and connected to the receive path of SSI module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of SSI module 1 receive. 1RODMACH1010 UART0_TX / UART1_TX When set, indicates uDMA channel 9 is available and connected to the transmit path of UART module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the seondary channel assignment of UART module 1 transmit. 1RODMACH99 UART0_RX / UART1_RX When set, indicates uDMA channel 8 is available and connected to the receive path of UART module 0. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of UART module 1 receive. 1RODMACH88 ETH_TX / Timer2B When set, indicates uDMA channel 7 is available and connected to the transmit path of the Ethernet module. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 1RODMACH77 ETH_RX / Timer2A When set, indicates uDMA channel 6 is available and connected to the receive path of the Ethernet module. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 1RODMACH66 March 19, 2011262 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field USB_EP3_TX / Timer2B When set, indicates uDMA channel 5 is available and connected to the transmit path of USB endpoint 3. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 1RODMACH55 USB_EP3_RX / Timer2A When set, indicates uDMA channel 4 is available and connected to the receive path of USB endpoint 3. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 1RODMACH44 USB_EP2_TX / Timer3B When set, indicates uDMA channel 3 is available and connected to the transmit path of USB endpoint 2. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 3B. 1RODMACH33 USB_EP2_RX / Timer3A When set, indicates uDMA channel 2 is available and connected to the receive path of USB endpoint 2. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of Timer 3A. 1RODMACH22 USB_EP1_TX / UART2_TX When set, indicates uDMA channel 1 is available and connected to the transmit path of USB endpoint 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of UART module 2 transmit. 1RODMACH11 USB_EP1_RX / UART2_RX When set, indicates uDMA channel 0 is available and connected to the receive path of USB endpoint 1. If the corresponding bit in the DMACHASGNregister is set, the channel is connected instead to the secondary channel assignment of UART module 2 receive. 1RODMACH00 263March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register24:DeviceCapabilities8ADCChannels(DC8),offset0x02C This register is predefined by the part and can be used to verify features. Device Capabilities 8 ADC Channels (DC8) Base 0x400F.E000 Offset 0x02C Type RO, reset 0xFFFF.FFFF 16171819202122232425262728293031 ADC1AIN0ADC1AIN1ADC1AIN2ADC1AIN3ADC1AIN4ADC1AIN5ADC1AIN6ADC1AIN7ADC1AIN8ADC1AIN9ADC1AIN10ADC1AIN11ADC1AIN12ADC1AIN13ADC1AIN14ADC1AIN15 ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 ADC0AIN0ADC0AIN1ADC0AIN2ADC0AIN3ADC0AIN4ADC0AIN5ADC0AIN6ADC0AIN7ADC0AIN8ADC0AIN9ADC0AIN10ADC0AIN11ADC0AIN12ADC0AIN13ADC0AIN14ADC0AIN15 ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field ADC Module 1 AIN15 Pin Present When set, indicates that ADC module 1 input pin 15 is present. 1ROADC1AIN1531 ADC Module 1 AIN14 Pin Present When set, indicates that ADC module 1 input pin 14 is present. 1ROADC1AIN1430 ADC Module 1 AIN13 Pin Present When set, indicates that ADC module 1 input pin 13 is present. 1ROADC1AIN1329 ADC Module 1 AIN12 Pin Present When set, indicates that ADC module 1 input pin 12 is present. 1ROADC1AIN1228 ADC Module 1 AIN11 Pin Present When set, indicates that ADC module 1 input pin 11 is present. 1ROADC1AIN1127 ADC Module 1 AIN10 Pin Present When set, indicates that ADC module 1 input pin 10 is present. 1ROADC1AIN1026 ADC Module 1 AIN9 Pin Present When set, indicates that ADC module 1 input pin 9 is present. 1ROADC1AIN925 ADC Module 1 AIN8 Pin Present When set, indicates that ADC module 1 input pin 8 is present. 1ROADC1AIN824 ADC Module 1 AIN7 Pin Present When set, indicates that ADC module 1 input pin 7 is present. 1ROADC1AIN723 ADC Module 1 AIN6 Pin Present When set, indicates that ADC module 1 input pin 6 is present. 1ROADC1AIN622 ADC Module 1 AIN5 Pin Present When set, indicates that ADC module 1 input pin 5 is present. 1ROADC1AIN521 ADC Module 1 AIN4 Pin Present When set, indicates that ADC module 1 input pin 4 is present. 1ROADC1AIN420 ADC Module 1 AIN3 Pin Present When set, indicates that ADC module 1 input pin 3 is present. 1ROADC1AIN319 March 19, 2011264 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field ADC Module 1 AIN2 Pin Present When set, indicates that ADC module 1 input pin 2 is present. 1ROADC1AIN218 ADC Module 1 AIN1 Pin Present When set, indicates that ADC module 1 input pin 1 is present. 1ROADC1AIN117 ADC Module 1 AIN0 Pin Present When set, indicates that ADC module 1 input pin 0 is present. 1ROADC1AIN016 ADC Module 0 AIN15 Pin Present When set, indicates that ADC module 0 input pin 15 is present. 1ROADC0AIN1515 ADC Module 0 AIN14 Pin Present When set, indicates that ADC module 0 input pin 14 is present. 1ROADC0AIN1414 ADC Module 0 AIN13 Pin Present When set, indicates that ADC module 0 input pin 13 is present. 1ROADC0AIN1313 ADC Module 0 AIN12 Pin Present When set, indicates that ADC module 0 input pin 12 is present. 1ROADC0AIN1212 ADC Module 0 AIN11 Pin Present When set, indicates that ADC module 0 input pin 11 is present. 1ROADC0AIN1111 ADC Module 0 AIN10 Pin Present When set, indicates that ADC module 0 input pin 10 is present. 1ROADC0AIN1010 ADC Module 0 AIN9 Pin Present When set, indicates that ADC module 0 input pin 9 is present. 1ROADC0AIN99 ADC Module 0 AIN8 Pin Present When set, indicates that ADC module 0 input pin 8 is present. 1ROADC0AIN88 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. 1ROADC0AIN77 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. 1ROADC0AIN66 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. 1ROADC0AIN55 ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. 1ROADC0AIN44 ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. 1ROADC0AIN33 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. 1ROADC0AIN22 ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. 1ROADC0AIN11 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. 1ROADC0AIN00 265March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register25:DeviceCapabilities9ADCDigitalComparators(DC9),offset 0x190 This register is predefined by the part and can be used to verify features. Device Capabilities 9 ADC Digital Comparators (DC9) Base 0x400F.E000 Offset 0x190 Type RO, reset 0x00FF.00FF 16171819202122232425262728293031 ADC1DC0ADC1DC1ADC1DC2ADC1DC3ADC1DC4ADC1DC5ADC1DC6ADC1DC7reserved ROROROROROROROROROROROROROROROROType 1111111100000000Reset 0123456789101112131415 ADC0DC0ADC0DC1ADC0DC2ADC0DC3ADC0DC4ADC0DC5ADC0DC6ADC0DC7reserved ROROROROROROROROROROROROROROROROType 1111111100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:24 ADC1 DC7 Present When set, indicates that ADC module 1 Digital Comparator 7 is present. 1ROADC1DC723 ADC1 DC6 Present When set, indicates that ADC module 1 Digital Comparator 6 is present. 1ROADC1DC622 ADC1 DC5 Present When set, indicates that ADC module 1 Digital Comparator 5 is present. 1ROADC1DC521 ADC1 DC4 Present When set, indicates that ADC module 1 Digital Comparator 4 is present. 1ROADC1DC420 ADC1 DC3 Present When set, indicates that ADC module 1 Digital Comparator 3 is present. 1ROADC1DC319 ADC1 DC2 Present When set, indicates that ADC module 1 Digital Comparator 2 is present. 1ROADC1DC218 ADC1 DC1 Present When set, indicates that ADC module 1 Digital Comparator 1 is present. 1ROADC1DC117 ADC1 DC0 Present When set, indicates that ADC module 1 Digital Comparator 0 is present. 1ROADC1DC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:8 ADC0 DC7 Present When set, indicates that ADC module 0 Digital Comparator 7 is present. 1ROADC0DC77 ADC0 DC6 Present When set, indicates that ADC module 0 Digital Comparator 6 is present. 1ROADC0DC66 March 19, 2011266 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field ADC0 DC5 Present When set, indicates that ADC module 0 Digital Comparator 5 is present. 1ROADC0DC55 ADC0 DC4 Present When set, indicates that ADC module 0 Digital Comparator 4 is present. 1ROADC0DC44 ADC0 DC3 Present When set, indicates that ADC module 0 Digital Comparator 3 is present. 1ROADC0DC33 ADC0 DC2 Present When set, indicates that ADC module 0 Digital Comparator 2 is present. 1ROADC0DC22 ADC0 DC1 Present When set, indicates that ADC module 0 Digital Comparator 1 is present. 1ROADC0DC11 ADC0 DC0 Present When set, indicates that ADC module 0 Digital Comparator 0 is present. 1ROADC0DC00 267March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register26:Non-VolatileMemoryInformation(NVMSTAT),offset0x1A0 This register is predefined by the part and can be used to verify features. Non-Volatile Memory Information (NVMSTAT) Base 0x400F.E000 Offset 0x1A0 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 FWBreserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1

32 Word Flash Write Buffer Active

When set, indicates that the 32 word Flash memory write buffer feature is active. 1ROFWB0 March 19, 2011268 Texas Instruments-Advance Information System Control

Register27:RunModeClockGatingControlRegister0(RCGC0),offset0x100 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC0is the clock configuration register for running operation,SCGC0for Sleep operation, andDCGC0for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 16171819202122232425262728293031 ADC0ADC1reservedPWMreservedCAN0CAN1reservedWDT1reserved R/WR/WROROR/WROROROR/WR/WROROR/WROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reservedreservedreservedMAXADC0SPDMAXADC1SPDreserved ROROROR/WROROROROR/WR/WR/WR/WROROROROType 0000001000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:26 CAN1 Clock Gating Control This bit controls the clock gating for CAN module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCAN125 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCAN024 269March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:21 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WPWM20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:18 ADC1 Clock Gating Control This bit controls the clock gating for SAR ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WADC117 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:12 ADC1 Sample Speed This field sets the rate at which ADC module 1 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting theMAXADC1SPD bit as follows (all other encodings are reserved): DescriptionValue 1M samples/second0x3 500K samples/second0x2 250K samples/second0x1 125K samples/second0x0 0R/WMAXADC1SPD11:10 ADC0 Sample Speed This field sets the rate at which ADC0 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting theMAXADC0SPDbit as follows (all other encodings are reserved): DescriptionValue 1M samples/second0x3 500K samples/second0x2 250K samples/second0x1 125K samples/second0x0 0R/WMAXADC0SPD9:8 March 19, 2011270 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1ROreserved6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5:4 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 271March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register28:SleepModeClockGatingControlRegister0(SCGC0),offset 0x110 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC0is the clock configuration register for running operation,SCGC0for Sleep operation, andDCGC0for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 16171819202122232425262728293031 ADC0ADC1reservedPWMreservedCAN0CAN1reservedWDT1reserved R/WR/WROROR/WROROROR/WR/WROROR/WROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reservedreservedreservedMAXADC0SPDMAXADC1SPDreserved ROROROR/WROROROROR/WR/WR/WR/WROROROROType 0000001000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Clock Gating Control This bit controls the clock gating for Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:26 CAN1 Clock Gating Control This bit controls the clock gating for CAN module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCAN125 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCAN024 March 19, 2011272 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:21 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WPWM20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:18 ADC1 Clock Gating Control This bit controls the clock gating for ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WADC117 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:12 ADC1 Sample Speed This field sets the rate at which ADC module 1 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting theMAXADC1SPD bit as follows (all other encodings are reserved): DescriptionValue 1M samples/second0x3 500K samples/second0x2 250K samples/second0x1 125K samples/second0x0 0R/WMAXADC1SPD11:10 ADC0 Sample Speed This field sets the rate at which ADC module 0 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting theMAXADC0SPD bit as follows (all other encodings are reserved): DescriptionValue 1M samples/second0x3 500K samples/second0x2 250K samples/second0x1 125K samples/second0x0 0R/WMAXADC0SPD9:8 273March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1ROreserved6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5:4 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 March 19, 2011274 Texas Instruments-Advance Information System Control

Register29:DeepSleepModeClockGatingControlRegister0(DCGC0), offset0x120 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC0is the clock configuration register for running operation,SCGC0for Sleep operation, andDCGC0for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 16171819202122232425262728293031 ADC0ADC1reservedPWMreservedCAN0CAN1reservedWDT1reserved R/WR/WROROR/WROROROR/WR/WROROR/WROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reservedreservedreserved ROROROR/WROROROROROROROROROROROROType 0000001000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:26 CAN1 Clock Gating Control This bit controls the clock gating for CAN module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCAN125 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCAN024 275March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:21 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WPWM20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:18 ADC1 Clock Gating Control This bit controls the clock gating for ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WADC117 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1ROreserved6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5:4 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 March 19, 2011276 Texas Instruments-Advance Information System Control

Register30:RunModeClockGatingControlRegister1(RCGC1),offset0x104 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC1is the clock configuration register for running operation,SCGC1for Sleep operation, andDCGC1for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reservedI2S0reservedEPI0reserved R/WR/WR/WR/WROROROROR/WR/WR/WROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedQEI0QEI1reservedI2C0reservedI2C1reserved R/WR/WR/WROR/WR/WROROR/WR/WROROR/WROR/WROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 EPI0 Clock Gating This bit controls the clock gating for EPI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEPI030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 I2S0 Clock Gating This bit controls the clock gating for I2S module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2S028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 277March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP226 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP125 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER319 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER218 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER117 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 March 19, 2011278 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:10 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WQEI19 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WQEI08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7:6 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WSSI15 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART22 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART11 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART00 279March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register31:SleepModeClockGatingControlRegister1(SCGC1),offset 0x114 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC1is the clock configuration register for running operation,SCGC1for Sleep operation, andDCGC1for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reservedI2S0reservedEPI0reserved R/WR/WR/WR/WROROROROR/WR/WR/WROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedQEI0QEI1reservedI2C0reservedI2C1reserved R/WR/WR/WROR/WR/WROROR/WR/WROROR/WROR/WROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 EPI0 Clock Gating This bit controls the clock gating for EPI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEPI030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 I2S0 Clock Gating This bit controls the clock gating for I2S module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2S028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 March 19, 2011280 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP226 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP125 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER319 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER218 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER117 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 281March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:10 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WQEI19 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WQEI08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7:6 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WSSI15 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART22 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART11 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART00 March 19, 2011282 Texas Instruments-Advance Information System Control

Register32:Deep-SleepModeClockGatingControlRegister1(DCGC1), offset0x124 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC1is the clock configuration register for running operation,SCGC1for Sleep operation, andDCGC1for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reservedI2S0reservedEPI0reserved R/WR/WR/WR/WROROROROR/WR/WR/WROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedQEI0QEI1reservedI2C0reservedI2C1reserved R/WR/WR/WROR/WR/WROROR/WR/WROROR/WROR/WROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 EPI0 Clock Gating This bit controls the clock gating for EPI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEPI030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 I2S0 Clock Gating This bit controls the clock gating for I2S module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2S028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 283March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP226 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP125 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER319 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER218 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER117 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 March 19, 2011284 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:10 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WQEI19 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WQEI08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7:6 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WSSI15 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART22 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART11 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUART00 285March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register33:RunModeClockGatingControlRegister2(RCGC2),offset0x108 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC2is the clock configuration register for running operation,SCGC2for Sleep operation, andDCGC2for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 16171819202122232425262728293031 USB0reservedEMAC0reservedEPHY0reserved R/WROROROROROROROROROROROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROR/WROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEPHY030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEMAC028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:17 March 19, 2011286 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUSB016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOJ8 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOH7 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOG6 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOF5 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOE4 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOD3 287March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOC2 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOB1 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOA0 March 19, 2011288 Texas Instruments-Advance Information System Control

Register34:SleepModeClockGatingControlRegister2(SCGC2),offset 0x118 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC2is the clock configuration register for running operation,SCGC2for Sleep operation, andDCGC2for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 16171819202122232425262728293031 USB0reservedEMAC0reservedEPHY0reserved R/WROROROROROROROROROROROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROR/WROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEPHY030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEMAC028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:17 289March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUSB016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOJ8 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOH7 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOG6 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOF5 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOE4 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOD3 March 19, 2011290 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOC2 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOB1 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOA0 291March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register35:DeepSleepModeClockGatingControlRegister2(DCGC2), offset0x128 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC2is the clock configuration register for running operation,SCGC2for Sleep operation, andDCGC2for Deep-Sleep operation. Setting the ACG bit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 16171819202122232425262728293031 USB0reservedEMAC0reservedEPHY0reserved R/WROROROROROROROROROROROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROR/WROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEPHY030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WEMAC028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:17 March 19, 2011292 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUSB016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOJ8 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOH7 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOG6 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOF5 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOE4 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOD3 293March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOC2 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOB1 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0R/WGPIOA0 March 19, 2011294 Texas Instruments-Advance Information System Control

Register36:SoftwareResetControl0(SRCR0),offset0x040 This register allows individual modules to be reset. Writes to this register are masked by the bits in the DeviceCapabilities1(DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 16171819202122232425262728293031 ADC0ADC1reservedPWMreservedCAN0CAN1reservedWDT1reserved R/WR/WROROR/WROROROR/WR/WROROR/WROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reserved ROROROR/WROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Reset Control When this bit is set, Watchdog Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:26 CAN1 Reset Control When this bit is set, CAN module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WCAN125 CAN0 Reset Control When this bit is set, CAN module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WCAN024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:21 PWM Reset Control When this bit is set, PWM module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WPWM20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:18 295March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field ADC1 Reset Control When this bit is set, ADC module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WADC117 ADC0 Reset Control When this bit is set, ADC module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:4 WDT0 Reset Control When this bit is set, Watchdog Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 March 19, 2011296 Texas Instruments-Advance Information System Control

Register37:SoftwareResetControl1(SRCR1),offset0x044 This register allows individual modules to be reset. Writes to this register are masked by the bits in the DeviceCapabilities2(DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reservedI2S0reservedEPI0reserved R/WR/WR/WR/WROROROROR/WR/WR/WROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedQEI0QEI1reservedI2C0reservedI2C1reserved R/WR/WR/WROR/WR/WROROR/WR/WROROR/WROR/WROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 EPI0 Reset Control When this bit is set, EPI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WEPI030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 I2S0 Reset Control When this bit is set, I2S module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WI2S028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 Analog Comp 2 Reset Control When this bit is set, Analog Comparator module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WCOMP226 Analog Comp 1 Reset Control When this bit is set, Analog Comparator module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WCOMP125 Analog Comp 0 Reset Control When this bit is set, Analog Comparator module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WCOMP024 297March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Reset Control Timer 3 Reset Control. When this bit is set, General-Purpose Timer module 3 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WTIMER319 Timer 2 Reset Control When this bit is set, General-Purpose Timer module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WTIMER218 Timer 1 Reset Control When this bit is set, General-Purpose Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WTIMER117 Timer 0 Reset Control When this bit is set, General-Purpose Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Reset Control When this bit is set, I2C module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 I2C0 Reset Control When this bit is set, I2C module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:10 QEI1 Reset Control When this bit is set, QEI module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WQEI19 QEI0 Reset Control When this bit is set, QEI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WQEI08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7:6 March 19, 2011298 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field SSI1 Reset Control When this bit is set, SSI module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WSSI15 SSI0 Reset Control When this bit is set, SSI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Reset Control When this bit is set, UART module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WUART22 UART1 Reset Control When this bit is set, UART module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WUART11 UART0 Reset Control When this bit is set, UART module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WUART00 299March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register38:SoftwareResetControl2(SRCR2),offset0x048 This register allows individual modules to be reset. Writes to this register are masked by the bits in the DeviceCapabilities4(DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 16171819202122232425262728293031 USB0reservedEMAC0reservedEPHY0reserved R/WROROROROROROROROROROROR/WROR/WROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROR/WROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 PHY0 Reset Control When this bit is set, Ethernet PHY layer 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WEPHY030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 MAC0 Reset Control When this bit is set, Ethernet MAC layer 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WEMAC028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:17 USB0 Reset Control When this bit is set, USB module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WUSB016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Reset Control When this bit is set, uDMA module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 March 19, 2011300 Texas Instruments-Advance Information System Control

DescriptionResetTypeNameBit/Field Port J Reset Control When this bit is set, Port J module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOJ8 Port H Reset Control When this bit is set, Port H module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOH7 Port G Reset Control When this bit is set, Port G module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOG6 Port F Reset Control When this bit is set, Port F module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOF5 Port E Reset Control When this bit is set, Port E module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOE4 Port D Reset Control When this bit is set, Port D module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOD3 Port C Reset Control When this bit is set, Port C module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOC2 Port B Reset Control When this bit is set, Port B module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOB1 Port A Reset Control When this bit is set, Port A module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0R/WGPIOA0 301March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

6 InternalMemory

The LM3S9B92 microcontroller comes with 96 KB of bit-banded SRAM, internal ROM,and 256 KB of Flash memory. The Flash memory controller provides a user-friendly interface, making Flash memory programming a simple task. Flash memory protection can be applied to the Flash memory on a 2-KB block basis.

6.1 BlockDiagram

Figure 6-1 on page 302 illustrates the internal memory blocks and control logic. The dashed boxes in the figure indicate registers residing in the System Control module. Figure6-1.InternalMemoryBlockDiagram ROM Control RMCTL ROM Array Flash Control Flash W rite Buffer FMA FMD FCIM FCMISC Flash Array Cortex-M3 Bridge SRAM Array System Bus Icode Bus Dcode Bus Flash Protection FMPRE FMPPE Flash T iming USECRL Flash Protection FMPREn FMPPEn User Registers BOOTCFG USER_REG0 USER_REG1 USER_REG2 USER_REG3 FMC FCRIS FMC2 FWBV AL FWBn 32 words

6.2 FunctionalDescription

This section describes the functionality of the SRAM, ROM, and Flash memories. Note: The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. March 19, 2011302 Texas Instruments-Advance Information Internal Memory

6.2.1 SRAM

The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band base is located at address 0x2200.0000. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see “Bit-Banding” on page 102. Note: The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks are partitioned such that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). A write access that is followed immediately by a read access to the same bank incurs a stall of a single clock cycle. However, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay.

6.2.2 ROM

The internal ROM of the Stellaris device is located at address 0x0100.0000 of the device memory map. Detailed information on the ROM contents can be found in theStellaris® ROM User’s Guide . The ROM contains the following components: ■ Stellaris Boot Loader and vector table ■ Stellaris Peripheral Driver Library (DriverLib) release for product-specific peripherals and interfaces ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error detection functionality The boot loader is used as an initial program loader (when the Flash memory is empty) as well as an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory requirements and freeing the Flash memory to be used for other purposes (such as additional features in the application). Advance Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to validate a span of data has the same contents as when previously checked.

6.2.2.1 BootLoaderOverview

The Stellaris Boot Loader is used to download code to the Flash memory of a device without the use of a debug interface. When the core is reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured in theBootConfiguration(BOOTCFG) register. 303March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFGregister is read. If theEN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. The boot loader uses a simple packet interface to provide synchronous communication with the device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as it does not enable the PLL. The following serial interfaces can be used: ■ UART0 ■ SSI0 ■ I 2C0 ■ Ethernet For simplicity, both the data format and communication protocol are identical for all serial interfaces. Note: The Flash-memory-resident version of the Boot Loader also supports CAN and USB. See theStellaris® Boot Loader User's Guide for information on the boot loader software.

6.2.2.2 StellarisPeripheralDriverLibrary

The Stellaris Peripheral Driver Library contains a file calleddriverlib/rom.h that assists with calling the peripheral driver library functions in the ROM. The detailed description of each function is available in theStellaris® ROM User’s Guide . See the "Using the ROM" chapter of theStellaris® Peripheral Driver Library User's Guide for more details on calling the ROM functions and using driverlib/rom.h. A table at the beginning of the ROM points to the entry points for the APIs that are provided in the ROM. Accessing the API through these tables provides scalability; while the API locations may change in future versions of the ROM, the API tables will not. The tables are split into two levels; the main table contains one pointer per peripheral which points to a secondary table that contains one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010, right after the Cortex-M3 vector table in the ROM. DriverLib functions are described in detail in theStellaris® Peripheral Driver Library User's Guide . Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The Stellaris Graphics Library provides a set of graphics primitives and a widget set for creating graphical user interfaces on Stellaris microcontroller-based boards that have a graphical display (for more information, see theStellaris® Graphics Library User's Guide ). The Stellaris USB Library is a set March 19, 2011304 Texas Instruments-Advance Information Internal Memory

of data types and functions for creating USB Device, Host or On-The-Go (OTG) applications on Stellaris microcontroller-based boards (for more information, see theStellaris® USB Library User's Guide).

6.2.2.3 AdvancedEncryptionStandard(AES)CryptographyTables

AES is a strong encryption method with reasonable performance and size. AES is fast in both hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for applications that can use pre-arranged keys, such as setup during manufacturing or configuration. Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the forward S-box substitution table, the second is the reverse S-box substitution table, the third is the forward polynomial table, and the final is the reverse polynomial table. See theStellaris® ROM User’s Guide for more information on AES.

6.2.2.4 CyclicRedundancyCheck(CRC)ErrorDetection

The CRC technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more readily. See theStellaris® ROM User’s Guide for more information on CRC.

6.2.3 FlashMemory

At system clock speeds of 50 MHz and below, the Flash memory is read in a single cycle. The Flash memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability to concurrently program 32 continuous words in Flash memory. Erasing a block causes the entire contents of the block to be reset to all 1s. The 1-KB blocks are paired into sets of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. Caution – The Stellaris Flash memory array has ECC which uses a test port into the Flash memory to continually scan the array for ECC errors and to correct any that are detected. This operation is transparent to the microcontroller . The BIST must scan the entire memory array occasionally to ensure integrity, taking about five minutes to do so. In systems where the microcontroller is frequently powered for less than five minutes, power should be removed from the microcontroller in a controlled manner to ensure proper operation. This controlled manner can either be through entering Hibernation mode or software can request permission to power down the part using the USDREQ bit in the Flash Control (FCTL) register and wait to receive an acknowledge from the USDACK bit prior to removing power. If the microcontroller is powered down using this controlled method, the BIST engine keeps track of where it was in the memory array and it always scans the complete array after any aggregate of five minutes powered-on, regardless of the number of intervening power cycles. If the microcontroller is powered down before five minutes of being powered up, BIST starts again from wherever it left off before the last controlled power-down or from 0 if there never was a controlled power down. An occasional short power down is not a concern, but the microcontroller should not always be powered down frequently in an uncontrolled manner. The microcontroller can be power-cycled as frequently as necessary if it is powered-down in a controlled manner. 305March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

6.2.3.1 PrefetchBuffer

The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency is greater than 50 MHz. In this mode, the Flash memory operates at half of the system clock. The prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait states while code is executing linearly. The fetch buffer includes a branch speculation mechanism that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short loop branches often stay in the buffer. As a result, some branches can be executed with no wait states. Other branches incur a single wait state.

6.2.3.2 FlashMemoryProtection

The user is provided two forms of Flash memory protection per 2-KB Flash memory block in four pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per policy per block) in theFMPPEnand FMPREnregisters. ■ FlashMemoryProtectionProgramEnable(FMPPEn) : If a bit is set, the corresponding block may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be changed. ■ FlashMemoryProtectionReadEnable(FMPREn) : If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 6-1 on page 306. Table6-1.FlashMemoryProtectionPolicyCombinations ProtectionFMPREnFMPPEn Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. No protection. The block may be written, erased, executed or read.11 A Flash memory access that attempts to read a read-protected block (FMPREnbit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEnbit is set) is prohibited and can optionally generate an interrupt (by setting theAMASK bit in theFlashControllerInterruptMask(FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using theFlashMemoryControl(FMC) register. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 309.

6.2.3.3 Interrupts

The Flash memory controller can generate interrupts when the following conditions are observed: March 19, 2011306 Texas Instruments-Advance Information Internal Memory

■ Programming Interrupt - signals when a program or erase action is complete. ■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its correspondingFMPPEnbit. The interrupt events that can trigger a controller-level interrupt are defined in theFlashController MaskedInterruptStatus(FCMIS) register (see page 318) by setting the correspondingMASK bits. If interrupts are not used, the raw interrupt status is always visible via theFlashControllerRaw InterruptStatus(FCRIS) register (see page 317). Interrupts are always cleared (for both theFCMISand FCRISregisters) by writing a 1 to the corresponding bit in theFlashControllerMaskedInterruptStatusandClear(FCMISC) register (see page 319).

6.2.3.4 FlashMemoryProgramming

The Stellaris devices provide a user-friendly interface for Flash memory programming. All erase/program operations are handled via three registers:FlashMemoryAddress(FMA) , Flash MemoryData(FMD) , andFlashMemoryControl(FMC) . Note that if the debug capabilities of the microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be performed in order to reactivate the debug module. See “Recovering a "Locked" Microcontroller” on page 193. During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress. Caution – The Flash memory is divided into sectors of electrically separated address ranges of 4 KB each, aligned on 4 KB boundaries. Erase/program operations on a 1-KB page have an electrical effect on the other three 1-KB pages within the sector . A specific 1-KB page must be erased after 6 total erase/program cycles occur to the other pages within its 4-KB sector . The following sequence of operations on a 4-KB sector of Flash memory (Page 0..3) provides an example: ■ Page 3 is erase and programmed with values. ■ Page 0, Page 1, and Page 2 are erased and then programmed with values. At this point Page 3 has been affected by 3 erase/program cycles. ■ Page 0, Page 1, and Page 2 are again erased and then programmed with values. At this point Page 3 has been affected by 6 erase/program cycles. ■ If the contents of Page 3 must continue to be valid, Page 3 must be erased and reprogrammed before any other page in this sector has another erase or program operation. To program a 32-bit word 1. Write source data to theFMDregister. 2. Write the target address to theFMAregister. 3. Write the Flash memory write key and theWRITE bit (a value of 0xA442.0001) to theFMC register. 4. Poll theFMCregister until theWRITE bit is cleared. 307March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Important: To ensure proper operation, two writes to the same word must be separated by an ERASE. The following two sequences are allowed: ■ ERASE -> PROGRAM value -> PROGRAM 0x0000.0000 ■ ERASE -> PROGRAM value -> ERASE The following sequence is NOT allowed: ■ ERASE -> PROGRAM value -> PROGRAM value To perform an erase of a 1-KB page 1. Write the page address to theFMAregister. 2. Write the Flash memory write key and theERASE bit (a value of 0xA442.0002) to theFMC register. 3. Poll theFMCregister until theERASE bit is cleared or, alternatively, enable the programming interrupt using thePMASK bit in theFCIMregister. To perform a mass erase of the Flash memory 1. Write the Flash memory write key and theMERASE bit (a value of 0xA442.0004) to theFMC register. 2. Poll theFMCregister until theMERASE bit is cleared or, alternatively, enable the programming interrupt using thePMASK bit in theFCIMregister. 6.2.3.5 32-WordFlashMemoryWriteBuffer A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory by concurrently programing 32 words with a single buffered Flash memory write operation. The buffered Flash memory write operation takes the same amount of time as the single word write operation controlled by bit 0 in theFMCregister. The data for the buffered write is written to the FlashWriteBuffer(FWBn) registers. The registers are 32-word aligned with Flash memory, and therefore the registerFWB0corresponds with the address inFMAwhere bits [6:0] ofFMAare all 0.FWB1corresponds with the address in FMA+ 0x4 and so on. Only theFWBnregisters that have been updated since the previous buffered Flash memory write operation are written. TheFlashWriteBufferValid(FWBVAL) register shows which registers have been written since the last buffered Flash memory write operation. This register contains a bit for each of the 32FWBnregisters, where bit[n] ofFWBVALcorresponds toFWBn. The FWBnregister has been updated if the corresponding bit in theFWBVALregister is set. To program 32 words with a single buffered Flash memory write operation 1. Write the source data to theFWBnregisters. 2. Write the target address to theFMAregister. This must be a 32-word aligned address (that is, bits [6:0] inFMAmust be 0s). 3. Write the Flash memory write key and theWRBUF bit (a value of 0xA442.0001) to theFMC2 register. March 19, 2011308 Texas Instruments-Advance Information Internal Memory

1. Poll theFMC2register until theWRBUF bit is cleared or wait for thePMIS interrupt to be signaled.

6.2.3.6 NonvolatileRegisterProgramming

This section discusses how to update registers that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a write operation. The register contents are unaffected by any reset condition except power-on reset, which returns the register contents to 0xFFFF.FFFF. By committing the register values using the COMT bit in theFMCregister, the register contents become nonvolatile and are therefore retained following power cycling. Once the register contents are committed, the only way to restore the factory default values is to perform the sequence described in “Recovering a "Locked" Microcontroller” on page 193. With the exception of theBootConfiguration(BOOTCFG) register, the settings in these registers can be tested before committing them to Flash memory. For theBOOTCFGregister, the data to be written is loaded into theFMDregister before it is committed. TheFMDregister is read only and does not allow theBOOTCFGoperation to be tried before committing it to nonvolatile memory. Important: The Flash memory resident registers can only have bits changed from 1 to 0 by user programming and can only be committed once. After being committed, these registers can only be restored to their factory default values only by performing the sequence described in “Recovering a "Locked" Microcontroller” on page 193. The mass erase of the main Flash memory array caused by the sequence is performed prior to restoring these registers. In addition, theUSER_REG0, USER_REG1, USER_REG2, USER_REG3, andBOOTCFGregisters each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. Table 6-2 on page 309 provides theFMAaddress required for commitment of each of the registers and the source of the data to be written when theFMCregister is written with a value of 0xA442.0008. After writing theCOMT bit, the user may poll theFMCregister to wait for the commit operation to complete. Table6-2.User-ProgrammableFlashMemoryResidentRegisters DataSourceFMAValueRegistertobeCommitted FMPRE00x0000.0000FMPRE0 FMPRE10x0000.0002FMPRE1 FMPRE20x0000.0004FMPRE2 FMPRE30x0000.0006FMPRE3 FMPPE00x0000.0001FMPPE0 FMPPE10x0000.0003FMPPE1 FMPPE20x0000.0005FMPPE2 FMPPE30x0000.0007FMPPE3 USER_REG00x8000.0000USER_REG0 USER_REG10x8000.0001USER_REG1 USER_REG20x8000.0002USER_REG2 USER_REG30x8000.0003USER_REG3 FMD0x7510.0000BOOTCFG 309March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

6.3 RegisterMap

Table 6-3 on page 310 lists the ROM Controller register and the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. TheFMA, FMD, FMC, FCRIS, FCIM, FCMISC, FMC2, FWBVAL, andFWBnregister offsets are relative to the Flash memory control base address of 0x400F.D000. The ROM and Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. Table6-3.FlashRegisterMap See pageDescriptionResetTypeNameOffset FlashMemoryRegisters(FlashControlOffset) 312Flash Memory Address0x0000.0000R/WFMA0x000 313Flash Memory Data0x0000.0000R/WFMD0x004 314Flash Memory Control0x0000.0000R/WFMC0x008 317Flash Controller Raw Interrupt Status0x0000.0000ROFCRIS0x00C 318Flash Controller Interrupt Mask0x0000.0000R/WFCIM0x010 319Flash Controller Masked Interrupt Status and Clear0x0000.0000R/W1CFCMISC0x014 320Flash Memory Control 20x0000.0000R/WFMC20x020 321Flash Write Buffer Valid0x0000.0000R/WFWBVAL0x030 322Flash Control0x0000.0000R/WFCTL0x0F8 323Flash Write Buffer n0x0000.0000R/WFWBn0x100 - 0x17C MemoryRegisters(SystemControlOffset) 324ROM Control-R/W1CRMCTL0x0F0 325Flash Memory Protection Read Enable 00xFFFF.FFFFR/WFMPRE00x130 325Flash Memory Protection Read Enable 00xFFFF.FFFFR/WFMPRE00x200 326Flash Memory Protection Program Enable 00xFFFF.FFFFR/WFMPPE00x134 326Flash Memory Protection Program Enable 00xFFFF.FFFFR/WFMPPE00x400 327Boot Configuration0xFFFF.FFFER/WBOOTCFG0x1D0 329User Register 00xFFFF.FFFFR/WUSER_REG00x1E0 330User Register 10xFFFF.FFFFR/WUSER_REG10x1E4 331User Register 20xFFFF.FFFFR/WUSER_REG20x1E8 332User Register 30xFFFF.FFFFR/WUSER_REG30x1EC 333Flash Memory Protection Read Enable 10xFFFF.FFFFR/WFMPRE10x204 334Flash Memory Protection Read Enable 20xFFFF.FFFFR/WFMPRE20x208 335Flash Memory Protection Read Enable 30xFFFF.FFFFR/WFMPRE30x20C 336Flash Memory Protection Program Enable 10xFFFF.FFFFR/WFMPPE10x404 March 19, 2011310 Texas Instruments-Advance Information Internal Memory

Table6-3.FlashRegisterMap (continued) See pageDescriptionResetTypeNameOffset 337Flash Memory Protection Program Enable 20xFFFF.FFFFR/WFMPPE20x408 338Flash Memory Protection Program Enable 30xFFFF.FFFFR/WFMPPE30x40C

6.4 FlashMemoryRegisterDescriptions(FlashControlOffset)

This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. 311March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register1:FlashMemoryAddress(FMA),offset0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned CPU byte address and specifies which block is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 OFFSETreserved R/WR/WROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 OFFSET R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:18 Address Offset Address offset in Flash memory where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 309 for details on values for this field). 0x0R/WOFFSET17:0 March 19, 2011312 Texas Instruments-Advance Information Internal Memory

Register2:FlashMemoryData(FMD),offset0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Data Value Data value for write operation. 0x0000.0000R/WDATA31:0 313March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register3:FlashMemoryControl(FMC),offset0x008 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by theFlashMemoryAddress(FMA) register (see page 312). If the access is a write access, the data contained in theFlashMemoryData(FMD) register (see page 313) is written to the specified address. This register must be the final register written and initiates the memory operation. The four control bits in the lower byte of this register are used to initiate memory operations. Care must be taken not to set multiple control bits as the results of such an operation are unpredictable. Caution – If any of bits [15:4] are written to 1, the device may become inoperable. These bits should always be written to 0. In all registers, the value of a reserved bit should be preserved across a read-modify-write operation. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 WRKEY WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0000000000000000Reset 0123456789101112131415 WRITEERASEMERASECOMTreserved R/WR/WR/WR/WROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. The value 0xA442 must be written into this field for a Flash memory write to occur. Writes to theFMC register without thisWRKEY value are ignored. A read of this field returns the value 0. 0x0000WOWRKEY31:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved15:4 March 19, 2011314 Texas Instruments-Advance Information Internal Memory

DescriptionResetTypeNameBit/Field Commit Register Value This bit is used to commit writes to Flash-memory-resident registers and to monitor the progress of that process. DescriptionValue Set this bit to commit (write) the register value to a Flash-memory-resident register. When read, a 1 indicates that the previous commit access is not complete. A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous commit access is complete. See “Nonvolatile Register Programming” on page 309 for more information on programming Flash-memory-resident registers. 0R/WCOMT3 Mass Erase Flash Memory This bit is used to mass erase the Flash main memory and to monitor the progress of that process. DescriptionValue Set this bit to erase the Flash main memory. When read, a 1 indicates that the previous mass erase access is not complete. A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous mass erase access is complete. For information on erase time, see “Flash Memory Characteristics” on page 1295. 0R/WMERASE2 Erase a Page of Flash Memory This bit is used to erase a page of Flash memory and to monitor the progress of that process. DescriptionValue Set this bit to erase the Flash memory page specified by the contents of theFMAregister. When read, a 1 indicates that the previous page erase access is not complete. A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous page erase access is complete. For information on erase time, see “Flash Memory Characteristics” on page 1295. 0R/WERASE1 315March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Write a Word into Flash Memory This bit is used to write a word into Flash memory and to monitor the progress of that process. DescriptionValue Set this bit to write the data stored in theFMDregister into the Flash memory location specified by the contents of theFMA register. When read, a 1 indicates that the write update access is not complete. A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous write update access is complete. For information on programming time, see “Flash Memory Characteristics” on page 1295. 0R/WWRITE0 March 19, 2011316 Texas Instruments-Advance Information Internal Memory

Register4:FlashControllerRawInterruptStatus(FCRIS),offset0x00C This register indicates that the Flash memory controller has an interrupt condition. An interrupt is sent to the interrupt controller only if the correspondingFCIMregister bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ARISPRISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:2 Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through theFMCor FMC2register bits (see page 314 and page 320). DescriptionValue The programming or erase cycle has completed.1 The programming or erase cycle has not completed.0 This status is sent to the interrupt controller when thePMASK bit in the FCIMregister is set. This bit is cleared by writing a 1 to thePMISC bit in theFCMISCregister. 0ROPRIS1 Access Raw Interrupt Status DescriptionValue A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in theFMPPEnregisters. No access has tried to improperly program or erase the Flash memory. This status is sent to the interrupt controller when theAMASK bit in the FCIMregister is set. This bit is cleared by writing a 1 to theAMISC bit in theFCMISCregister. 0ROARIS0 317March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register5:FlashControllerInterruptMask(FCIM),offset0x010 This register controls whether the Flash memory controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 AMASKPMASKreserved R/WR/WROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:2 Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. DescriptionValue An interrupt is sent to the interrupt controller when thePRIS bit is set. The PRIS interrupt is suppressed and not sent to the interrupt controller. 0R/WPMASK1 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. DescriptionValue An interrupt is sent to the interrupt controller when theARIS bit is set. The ARIS interrupt is suppressed and not sent to the interrupt controller. 0R/WAMASK0 March 19, 2011318 Texas Instruments-Advance Information Internal Memory

Register6:FlashControllerMaskedInterruptStatusandClear(FCMISC), offset0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 AMISCPMISCreserved R/W1CR/W1CROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:2 Programming Masked Interrupt Status and Clear DescriptionValue When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clearsPMISC and also thePRIS bit in the FCRISregister (see page 317). When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. 0R/W1CPMISC1 Access Masked Interrupt Status and Clear DescriptionValue When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in theFMPPEnregisters. Writing a 1 to this bit clearsAMISC and also theARIS bit in the FCRISregister (see page 317). When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. 0R/W1CAMISC0 319March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register7:FlashMemoryControl2(FMC2),offset0x020 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by theFlashMemoryAddress(FMA) register (see page 312). If the access is a write access, the data contained in theFlashWriteBuffer(FWB) registers is written. This register must be the final register written as it initiates the memory operation. Flash Memory Control 2 (FMC2) Base 0x400F.D000 Offset 0x020 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 WRKEY WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0000000000000000Reset 0123456789101112131415 WRBUFreserved R/WROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. The value 0xA442 must be written into this field for a write to occur. Writes to theFMC2register without this WRKEY value are ignored. A read of this field returns the value 0. 0x0000WOWRKEY31:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved15:1 Buffered Flash Memory Write This bit is used to start a buffered write to Flash memory. DescriptionValue Set this bit to write the data stored in theFWBnregisters to the location specified by the contents of theFMAregister. When read, a 1 indicates that the previous buffered Flash memory write access is not complete. A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous buffered Flash memory write access is complete. For information on programming time, see “Flash Memory Characteristics” on page 1295. 0R/WWRBUF0 March 19, 2011320 Texas Instruments-Advance Information Internal Memory

Register8:FlashWriteBufferValid(FWBVAL),offset0x030 This register provides a bitwise status of whichFWBnregisters have been written by the processor since the last write of the Flash memory write buffer. The entries with a 1 are written on the next write of the Flash memory write buffer. This register is cleared after the write operation by hardware. A protection violation on the write operation also clears this status. Software can program the same 32 words to various Flash memory locations by setting theFWB[n] bits after they are cleared by the write operation. The next write operation then uses the same data as the previous one. In addition, if aFWBnregister change should not be written to Flash memory, software can clear the correspondingFWB[n] bit to preserve the existing data when the next write operation occurs. Flash Write Buffer Valid (FWBVAL) Base 0x400F.D000 Offset 0x030 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 FWB[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 FWB[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Flash Memory Write Buffer DescriptionValue The correspondingFWBnregister has been updated since the last buffer write operation and is ready to be written to Flash memory. The correspondingFWBnregister has no new data to be written.0 Bit 0 corresponds toFWB0, offset 0x100, and bit 31 corresponds to FWB31, offset 0x13C. 0x0R/WFWB[n]31:0 321March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register9:FlashControl(FCTL),offset0x0F8 This register is used to ensure that the microcontroller is powered down in a controlled fashion in systems where power is cycled more frequently than once every five minutes. TheUSDREQ bit should be set to indicate that power is going to be turned off. Software should poll theUSDACK bit to determine when it is acceptable to power down. Flash Control (FCTL) Base 0x400F.D000 Offset 0x0F8 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 USDREQUSDACKreserved R/WROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:2 User Shut Down Acknowledge DescriptionValue The microcontroller can be powered down.1 The microcontroller cannot yet be powered down.0 This bit should be set within 50 ms of setting theUSDREQ bit. 0ROUSDACK1 User Shut Down Request DescriptionValue Requests permission to power down the microcontroller.1 No effect.0 0R/WUSDREQ0 March 19, 2011322 Texas Instruments-Advance Information Internal Memory

Register10:FlashWriteBuffern(FWBn),offset0x100-0x17C These 32 registers hold the contents of the data to be written into the Flash memory on a buffered Flash memory write operation. The offset selects one of the 32-bit registers. OnlyFWBnregisters that have been updated since the preceding buffered Flash memory write operation are written into the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or 2 words. TheFWBnregisters are written into the Flash memory with theFWB0register corresponding to the address contained inFMA. FWB1is written to the addressFMA+0x4 etc. Note that only data bits that are 0 result in the Flash memory being modified. A data bit that is 1 leaves the content of the Flash memory bit at its previous value. Flash Write Buffer n (FWBn) Base 0x400F.D000 Offset 0x100 - 0x17C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Data Data to be written into the Flash memory. 0x0000.0000R/WDATA31:0

6.5 MemoryRegisterDescriptions(SystemControlOffset)

The remainder of this section lists and describes the registers that reside in the System Control address space, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 323March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register11:ROMControl(RMCTL),offset0x0F0 This register provides control of the ROM controller state. This register offset is relative to the System Control base address of 0x400F.E000. At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFGregister is read. If theEN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. ROM Control (RMCTL) Base 0x400F.E000 Offset 0x0F0 Type R/W1C, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 BAreserved R/W1CROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Boot Alias DescriptionValue The microcontroller's ROM appears at address 0x0.1 The Flash memory is at address 0x0.0 This bit is cleared by writing a 1 to this bit position. 1R/W1CBA0 March 19, 2011324 Texas Instruments-Advance Information Internal Memory

Register12:FlashMemoryProtectionReadEnable0(FMPRE0),offset0x130 and0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.E000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 0xFFFFFFFF 0xFFFFFFFFR/WREAD_ENABLE31:0 325March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register13:FlashMemoryProtectionProgramEnable0(FMPPE0),offset 0x134and0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.E000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 0xFFFFFFFF 0xFFFFFFFFR/WPROG_ENABLE31:0 March 19, 2011326 Texas Instruments-Advance Information Internal Memory

Register14:BootConfiguration(BOOTCFG),offset0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides configuration of a GPIO pin to enable the ROM Boot Loader as well as a write-once mechanism to disable external debugger access to the device. Upon reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal from Ports A-H as configured by the bits in this register. If the EN bit is set or the specified pin does not have the required polarity, the system control module checks address 0x000.0004 to see if the Flash memory has a valid reset vector. If the data at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not yet been programmed, and the core executes the ROM Boot Loader. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Clearing the DBG1 bit disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. Boot Configuration (BOOTCFG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 16171819202122232425262728293031 reservedNW ROROROROROROROROROROROROROROROR/WType 1111111111111111Reset 0123456789101112131415 DBG0DBG1reservedENPOLPINPORT R/WR/WROROROROROROR/WR/WR/WR/WR/WR/WR/WR/WType 0111111111111111Reset DescriptionResetTypeNameBit/Field Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 1R/WNW31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x7FFFROreserved30:16 327March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Boot GPIO Port This field selects the port of the GPIO port pin that enables the ROM boot loader at reset. DescriptionValue Port A0x0 Port B0x1 Port C0x2 Port D0x3 Port E0x4 Port F0x5 Port G0x6 Port H0x7 0x7R/WPORT15:13 Boot GPIO Pin This field selects the pin number of the GPIO port pin that enables the ROM boot loader at reset. DescriptionValue Pin 00x0 Pin 10x1 Pin 20x2 Pin 30x3 Pin 40x4 Pin 50x5 Pin 60x6 Pin 70x7 0x7R/WPIN12:10 Boot GPIO Polarity When set, this bit selects a high level for the GPIO port pin to enable the ROM boot loader at reset. When clear, this bit selects a low level for the GPIO port pin. 0x1R/WPOL9 Boot GPIO Enable Clearing this bit enables the use of a GPIO pin to enable the ROM Boot Loader at reset. When this bit is set, the contents of address 0x0000.0004 are checked to see if the Flash memory has been programmed. If the contents are not 0xFFFF.FFFF, the core executes out of Flash memory. If the Flash has not been programmed, the core executes out of ROM. 0x1R/WEN8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x3FROreserved7:2 Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 1R/WDBG11 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0x0R/WDBG00 March 19, 2011328 Texas Instruments-Advance Information Internal Memory

Register15:UserRegister0(USER_REG0),offset0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. The only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG section. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 DATANW R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 1R/WNW31 User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 0x7FFFFFFFR/WDATA30:0 329March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register16:UserRegister1(USER_REG1),offset0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 DATANW R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 1R/WNW31 User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 0x7FFFFFFFR/WDATA30:0 March 19, 2011330 Texas Instruments-Advance Information Internal Memory

Register17:UserRegister2(USER_REG2),offset0x1E8 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 2 (USER_REG2) Base 0x400F.E000 Offset 0x1E8 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 DATANW R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 1R/WNW31 User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 0x7FFFFFFFR/WDATA30:0 331March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register18:UserRegister3(USER_REG3),offset0x1EC Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 3 (USER_REG3) Base 0x400F.E000 Offset 0x1EC Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 DATANW R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 DATA R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 1R/WNW31 User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 0x7FFFFFFFR/WDATA30:0 March 19, 2011332 Texas Instruments-Advance Information Internal Memory

Register19:FlashMemoryProtectionReadEnable1(FMPRE1),offset0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 0xFFFFFFFF 0xFFFFFFFFR/WREAD_ENABLE31:0 333March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register20:FlashMemoryProtectionReadEnable2(FMPRE2),offset0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. 0xFFFFFFFF 0xFFFFFFFFR/WREAD_ENABLE31:0 March 19, 2011334 Texas Instruments-Advance Information Internal Memory

Register21:FlashMemoryProtectionReadEnable3(FMPRE3),offset0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 READ_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. 0xFFFFFFFF 0xFFFFFFFFR/WREAD_ENABLE31:0 335March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register22:FlashMemoryProtectionProgramEnable1(FMPPE1),offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 0xFFFFFFFF 0xFFFFFFFFR/WPROG_ENABLE31:0 March 19, 2011336 Texas Instruments-Advance Information Internal Memory

Register23:FlashMemoryProtectionProgramEnable2(FMPPE2),offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. 0xFFFFFFFF 0xFFFFFFFFR/WPROG_ENABLE31:0 337March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register24:FlashMemoryProtectionProgramEnable3(FMPPE3),offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREnstores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. OtherFMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 PROG_ENABLE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. DescriptionValue Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. 0xFFFFFFFF 0xFFFFFFFFR/WPROG_ENABLE31:0 March 19, 2011338 Texas Instruments-Advance Information Internal Memory

7 MicroDirectMemoryAccess(μDMA)

The LM3S9B92 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex™-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ■ ARM ® PrimeCell® 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Primary and secondary channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests 339March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

7.1 BlockDiagram

Figure7-1.μDMABlockDiagram System Memory CH Control T able T ransfer Buf fers Used by µ DMA uDMA Controller DMASRCENDP DMADSTENDP DMACHCTRL DMASRCENDP DMADSTENDP DMACHCTRL DMA error Peripheral DMA Channel 0 Peripheral DMA Channel N -1 DMAST A T DMACFG DMACTLBASE DMAAL TBASE DMA W AITST A T DMASWREQ DMAUSEBURSTSET DMAUSEBURSTCLR DMAREQMASKSET DMAREQMASKCLR DMAENASET DMAENACLR DMAAL TSET DMAAL TCLR DMAPRIOSET DMAPRIOCLR DMAERRCLR request done request done General Peripheral N Registers Nested V ectored Interrupt Controller ( NVIC) ARM Cortex -M3 IRQ request done DMACHASGN

7.2 FunctionalDescription

The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is always subordinate to the processor core, so it never holds up a bus transaction by the processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture has been optimized to greatly enhance the ability of the processor core and the μDMA controller to efficiently share the on-chip bus, thus improving performance. The optimizations include RAM striping and peripheral bus segmentation, which in many cases allow both the processor core and the μDMA controller to access the bus and perform simultaneous data transfers. The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. Each peripheral function that is supported has a dedicated channel on the μDMA controller that can be configured independently. The μDMA controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. While simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. Each channel also has a configurable arbitration size. The arbitration size is the number of items that are transferred in a burst before the μDMA controller rearbitrates for channel priority. Using the March 19, 2011340 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a μDMA service request.

7.2.1 ChannelAssignments

μDMA channels 0-31 are assigned to peripherals according to the following table. TheDMAChannel Assignment(DMACHASGN)register (see page 387) can be used to specify the primary or secondary assignment. If the primary function is not available on this microcontroller, the secondary function becomes the primary function. If the secondary function is not available, the primary function is the only option. Note: Channels noted in the table as "Available for software" may be assigned to peripherals in the future. However, they are currently available for software use. Channel 30 is dedicated for software use. The USB endpoints mapped to μDMA channels 0-3 can be changed with theUSBDMASEL register (see page 1099). Because of the way the μDMA controller interacts with peripherals, the μDMA channel for the peripheral must be enabled in order for the μDMA controller to be able to read and write the peripheral registers, even if a different μDMA channel is used to perform the μDMA transfer. To minimize confusion and chance of software errors, it is best practice to use a peripheral's μDMA channel for performing all μDMA transfers for that peripheral, even if it is processor-triggered and using AUTO mode, which could be considered a software transfer. Note that if the software channel is used, interrupts occur on the dedicated μDMA interrupt vector. If the peripheral channel is used, then the interrupt occurs on the interrupt vector for the peripheral. Table7-1.μDMAChannelAssignments SecondaryAssignmentPrimaryAssignmentμDMAChannel UART2 ReceiveUSB Endpoint 1 Receive0 UART2 TransmitUSB Endpoint 1 Transmit1 General-Purpose Timer 3AUSB Endpoint 2 Receive2 General-Purpose Timer 3BUSB Endpoint 2 Transmit3 General-Purpose Timer 2AUSB Endpoint 3 Receive4 General-Purpose Timer 2BUSB Endpoint 3 Transmit5 General-Purpose Timer 2AEthernet Receive6 General-Purpose Timer 2BEthernet Transmit7 UART1 ReceiveUART0 Receive8 UART1 TransmitUART0 Transmit9 SSI1 ReceiveSSI0 Receive10 SSI1 TransmitSSI0 Transmit11 UART2 ReceiveAvailable for software12 UART2 TransmitAvailable for software13 General-Purpose Timer 2AADC0 Sample Sequencer 014 General-Purpose Timer 2BADC0 Sample Sequencer 115 Available for softwareADC0 Sample Sequencer 216 Available for softwareADC0 Sample Sequencer 317 General-Purpose Timer 1AGeneral-Purpose Timer 0A18 General-Purpose Timer 1BGeneral-Purpose Timer 0B19 341March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table7-1.μDMAChannelAssignments (continued) SecondaryAssignmentPrimaryAssignmentμDMAChannel EPI0 NBRFIFOGeneral-Purpose Timer 1A20 EPI0 WFIFOGeneral-Purpose Timer 1B21 Available for softwareUART1 Receive22 Available for softwareUART1 Transmit23 ADC1 Sample Sequencer 0SSI1 Receive24 ADC1 Sample Sequencer 1SSI1 Transmit25 ADC1 Sample Sequencer 2Available for software26 ADC1 Sample Sequencer 3Available for software27 Available for softwareI2S0 Receive28 Available for softwareI2S0 Transmit29 Dedicated for software use30 Reserved31

7.2.2 Priority

The μDMA controller assigns priority to each channel based on the channel number and the priority level bit for the channel. Channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. Each channel has a priority level bit to provide two levels of priority: default priority and high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. The priority bit for a channel can be set using theDMAChannelPrioritySet(DMAPRIOSET) register and cleared with theDMAChannelPriorityClear(DMAPRIOCLR) register.

7.2.3 ArbitrationSize

When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels making a request and services the μDMA channel with the highest priority. Once a transfer begins, it continues for a selectable number of transfers before rearbitrating among the requesting channels again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. After the μDMA controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels is increased because the μDMA controller completes the lower priority burst before checking for higher priority requests. Therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. The arbitration size can also be thought of as a burst size. It is the maximum number of items that are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor must perform a bus transaction on the same bus, even in the middle of a burst transfer.

7.2.4 RequestTypes

The μDMA controller responds to two types of requests from a peripheral: single or burst. Each peripheral may support either or both types of requests. A single request means that the peripheral March 19, 2011342 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items. The μDMA controller responds differently depending on whether the peripheral is making a single request or a burst request. If both are asserted, and the μDMA channel has been set up for a burst transfer, then the burst request takes precedence. See Table 7-2 on page 343, which shows how each peripheral supports the two request types. Table7-2.RequestTypeSupport BurstRequestSignalSingleRequestSignalPeripheral Sequencer IE bitNoneADC WFIFO Level (configurable)NoneEPI WFIFO NBRFIFO Level (configurable)NoneEPI NBRFIFO NoneTX FIFO emptyEthernet TX NoneRX packet receivedEthernet RX NoneRaw interrupt pulseGeneral-Purpose Timer FIFO service requestNoneI2S TX FIFO service requestNoneI2S RX TX FIFO Level (fixed at 4)TX FIFO Not FullSSI TX RX FIFO Level (fixed at 4)RX FIFO Not EmptySSI RX TX FIFO Level (configurable)TX FIFO Not FullUART TX RX FIFO Level (configurable)RX FIFO Not EmptyUART RX FIFO TXRDYNoneUSB TX FIFO RXRDYNoneUSB RX

7.2.4.1 SingleRequest

When a single request is detected, and not a burst request, the μDMA controller transfers one item and then stops to wait for another request.

7.2.4.2 BurstRequest

When a burst request is detected, the μDMA controller transfers the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size should be the same as the number of data items that the peripheral can accommodate when making a burst request. For example, the UART generates a burst request based on the FIFO trigger level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the same number of non-burst transfers. It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time. The single request can be disabled by using theDMAChannel UseburstSet(DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the μDMA controller only responds to burst requests for that channel.

7.2.5 ChannelConfiguration

The μDMA controller uses an area of system memory to store a set of channel control structures in a table. The control table may have one or two entries for each μDMA channel. Each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. The 343March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. Table 7-3 on page 344 shows the layout in memory of the channel control table. Each channel may have one or two control structures in the control table: a primary control structure and an optional alternate control structure. The table is organized so that all of the primary entries are in the first half of the table, and all the alternate structures are in the second half of the table. The primary entry is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. In this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not necessary, and that memory can be used for something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. Any unused memory in the control table may be used by the application. This includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. Table7-3.ControlStructureMemoryMap ChannelOffset 0, Primary0x0 1, Primary0x10 31, Primary0x1F0 0, Alternate0x200 1, Alternate0x210 31, Alternate0x3F0 Table 7-4 shows an individual control structure entry in the control table. Each entry is aligned on a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. The end pointers point to the ending address of the transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral register), then the pointer should point to the transfer address. Table7-4.ChannelControlStructure DescriptionOffset Source End Pointer0x000 Destination End Pointer0x004 Control Word0x008 Unused0x00C The control word contains the following fields: ■ Source and destination data sizes ■ Source and destination address increment size ■ Number of transfers before bus arbitration ■ Total number of items to transfer March 19, 2011344 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

■ Useburst flag ■ Transfer mode The control word and each field are described in detail in “μDMA Channel Control Structure” on page 361. The μDMA controller updates the transfer size and transfer mode fields as the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be reconfigured before each new transfer. The source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the DMAChannelEnableSet(DMAENASET) register. A channel can be disabled by setting the channel bit in theDMAChannelEnableClear(DMAENACLR) register. At the end of a complete μDMA transfer, the controller automatically disables the channel.

7.2.6 TransferModes

The μDMA controller supports several transfer modes. Two of the modes support simple one-time transfers. Several complex modes support a continuous flow of data.

7.2.6.1 StopMode

While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word. When the mode field has this value, the μDMA controller does not perform any transfers and disables the channel if it is enabled. At the end of a transfer, the μDMA controller updates the control word to set the mode to Stop.

7.2.6.2 BasicMode

In Basic mode, the μDMA controller performs transfers as long as there are more items to transfer, and a transfer request is present. This mode is used with peripherals that assert a μDMA request signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any situation where the request is momentary even though the entire transfer should be completed. For example, a software-initiated transfer creates a momentary request, and in Basic mode, only the number of transfers specified by theARBSIZEfield in theDMAChannelControlWord(DMACHCTL) register is transferred on a software request, even if there is more data to transfer. When all of the items have been transferred using Basic mode, the μDMA controller sets the mode for that channel to Stop.

7.2.6.3 AutoMode

Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer runs to completion, even if the μDMA request is removed. This mode is suitable for software-triggered transfers. Generally, Auto mode is not used with a peripheral. When all the items have been transferred using Auto mode, the μDMA controller sets the mode for that channel to Stop.

7.2.6.4 Ping-Pong

Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong mode, both the primary and alternate data structures must be implemented. Both structures are set up by the processor for data transfer between memory and a peripheral. The transfer is started using the primary control structure. When the transfer using the primary control structure is complete, the μDMA controller reads the alternate control structure for that channel to continue the transfer. 345March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Each time this happens, an interrupt is generated, and the processor can reload the control structure for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. Refer to Figure 7-2 on page 346 for an example showing operation in Ping-Pong mode. Figure7-2.ExampleofPing-PongμDMATransaction Alternate Structure Primary Structure Primary Structure Alternate Structure transfer continues using alternate BUFFER B BUFFER A

• Process data in BUFFER A
• Reload primary structure transfers using BUFFER A BUFFER A transfers using BUFFER A transfers using BUFFER B transfer continues using alternatetransfer continues using primary BUFFER B transfers using BUFFER B Peripheral/ µ DMA Interrupt
• Process data in BUFFER B
• Reload alternate structure
• Process data in BUFFER B
• Reload alternate structure µ DMA Controller Cortex-M3 Processor T ime Peripheral/ µ DMA Interrupt Peripheral/ µ DMA Interrupt SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused March 19, 2011346 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

7.2.6.5 MemoryScatter-Gather

Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. For example, a gather μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. In Memory Scatter-Gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode. Each entry in the table is copied in turn to the alternate structure where it is then executed. The μDMA controller alternates between using the primary control structure to copy the next transfer instruction from the list and then executing the new transfer instruction. The end of the list is marked by programming the control word for the last entry to use Auto transfer mode. Once the last transfer is performed using Auto mode, the μDMA controller stops. A completion interrupt is generated only after the last transfer. It is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set of other channels to perform a transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by causing a peripheral action that results in a μDMA request. By programming the μDMA controller using this method, a set of arbitrary transfers can be performed based on a single μDMA request. Refer to Figure 7-3 on page 348 and Figure 7-4 on page 349, which show an example of operation in Memory Scatter-Gather mode. This example shows agather operation, where data in three separate buffers in memory is copied together into one buffer. Figure 7-3 on page 348 shows how the application sets up a μDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. Figure 7-4 on page 349 shows the sequence as the μDMA controller performs the three sets of copy operations. First, using the primary control structure, the μDMA controller loads the alternate control structure with task A. It then performs the copy operation specified by task A, copying the data from the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. 347March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure7-3.MemoryScatter-Gather,SetupandConfiguration NOTES: 1 . Application has a need to copy data items from three separate locations in memory into one combined buf fer . 2 . Application sets up µ DMA “task list” in memory , which contains the pointers and control configuration for three µ DMA copy “tasks.” 3 . Application sets up the channel primary control structure to copy each task configuration , one at a time, to the alternate control structure, where it is executed by the µ DMA controller . C

4 WORDS (SRC A)

16 WORDS (SRC B)

ITEMS=16 Unused SRC DST ITEMS=1

1 WORD (SRC C)

4 (DEST A) 16 (DEST B) 1 (DEST C) DSTA B “T ASK” A “T ASK” B “T ASK” C SRC DST ITEMS=12 SRC DST ITEMS=n Task List in Memory 21 3 Source and Destination Buffer in Memory Channel Control Table in Memory Channel Primary Control Structure Channel Alternate Control Structure Unused ITEMS=4 SRC Unused March 19, 2011348 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Figure7-4.MemoryScatter-Gather,μDMACopySequence SRC DST COPIED SRC DST COPIED PRI AL T SRC DST COPIED SRC DST COPIED SRC DST COPIED SRC DST COPIED Task List in Memory µ DMA Control Table in Memory Buffers in Memory T ASK B T ASK C PRI AL T SRC B SRC C DEST B DEST C Using the channel’ s primary control structure, the µ DMA controller copies task A configuration to the channel ’s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer A to the destination buf fer . Task List in Memory µ DMA Control Table in Memory Buffers in Memory Using the channel’ s primary control structure, the µ DMA controller copies task B configuration to the channel ’s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer B to the destination buf fer . µ DMA Control Table in Memory Buffers in Memory Using the channel’ s primary control structure, the µ DMA controller copies task C configuration to the channel ’s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer C to the destination buf fer . PRI AL T Task List in Memory T ASK A T ASK B T ASK A T ASK C SRC A SRC C DEST A DEST C SRC A SRC B DEST A DEST B T ASK A T ASK B SRC A T ASK C SRC C DEST C SRC B DEST B DEST A 349March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

7.2.6.6 PeripheralScatter-Gather

Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers are controlled by a peripheral making a μDMA request. Upon detecting a request from the peripheral, the μDMA controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer. At the end of this transfer, the next transfer is started only if the peripheral again asserts a μDMA request. The μDMA controller continues to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. A completion interrupt is generated only after the last transfer. By using this method, the μDMA controller can transfer data to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. Refer to Figure 7-5 on page 351 and Figure 7-6 on page 352, which show an example of operation in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three separate buffers in memory is copied to a single peripheral data register. Figure 7-5 on page 351 shows how the application sets up a µDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. Figure 7-6 on page 352 shows the sequence as the µDMA controller performs the three sets of copy operations. First, using the primary control structure, the µDMA controller loads the alternate control structure with task A. It then performs the copy operation specified by task A, copying the data from the source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. March 19, 2011350 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Figure7-5.PeripheralScatter-Gather,SetupandConfiguration C A B SRC DST ITEMS=12 SRC DST ITEMS=n Task List in Memory 21 3 Source Buffer in Memory Channel Control Table in Memory Channel Primary Control Structure Channel Alternate Control Structure DEST Peripheral Data Register SRC DST ITEMS=16 Unused SRC DST ITEMS=1 DST “T ASK” A “T ASK” B “T ASK” C Unused ITEMS=4 SRC Unused NOTES: 1 . Application has a need to copy data items from three separate locations in memory into a peripheral data register . 2 . Application sets up µ DMA “task list” in memory , which contains the pointers and control configuration for three µ DMA copy “tasks.” 3 . Application sets up the channel primary control structure to copy each task configuration , one at a time, to the alternate control structure, where it is executed by the µ DMA controller . 351March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure7-6.PeripheralScatter-Gather,μDMACopySequence SRC C T ASK A SRC DST COPIED SRC DST COPIED PRI AL T SRC DST COPIED SRC DST COPIED SRC DST COPIED SRC DST COPIED Task List in Memory µ DMA Control Table in Memory Buffers in Memory T ASK B T ASK C PRI AL T Using the channel’ s primary control structure, the µ DMA controller copies task A configuration to the channel ’s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer A to the peripheral data register . Task List in Memory µ DMA Control Table in Memory Buffers in Memory Using the channel’ s primary control structure, the µ DMA controller copies task B configuration to the channel ’s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer B to the peripheral data register . µ DMA Control Table in Memory Buffers in Memory Using the channel’ s primary control structure, the µ DMA controller copies task C configuration to the channel ’s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer C to the peripheral data register . PRI AL T Task List in Memory T ASK A T ASK B T ASK A T ASK C Peripheral Data Register SRC B SRC C Peripheral Data Register SRC A SRC C Peripheral Data Register SRC A SRC B T ASK B T ASK C SRC B SRC A March 19, 2011352 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

7.2.7 TransferSizeandIncrement

The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and destination address increment values can be set independently, and it is not necessary for the address increment to match the data size as long as the increment is the same or larger than the data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address increment of full words (4 bytes). The data to be transferred must be aligned in memory according to the data size (8, 16, or 32 bits). Table 7-5 shows the configuration to read from a peripheral that supplies 8-bit data. Table7-5.μDMAReadExample:8-BitPeripheral ConfigurationField 8 bitsSource data size 8 bitsDestination data size No incrementSource address increment ByteDestination address increment Peripheral read FIFO registerSource end pointer End of the data buffer in memoryDestination end pointer

7.2.8 PeripheralInterface

Each peripheral that supports μDMA has a single request and/or burst request signal that is asserted when the peripheral is ready to transfer data (see Table 7-2 on page 343). The request signal can be disabled or enabled using theDMAChannelRequestMaskSet(DMAREQMASKSET) and DMAChannelRequestMaskClear(DMAREQMASKCLR) registers. The μDMA request signal is disabled, or masked, when the channel request mask bit is set. When the request is not masked, the μDMA channel is configured correctly and enabled, and the peripheral asserts the request signal, the μDMA controller begins the transfer. Note: When using μDMA to transfer data to and from a peripheral, the peripheral must disable all interrupts to the NVIC. When a μDMA transfer is complete, the μDMA controller generates an interrupt, see “Interrupts and Errors” on page 354 for more information. For more information on how a specific peripheral interacts with the μDMA controller, refer to the DMA Operation section in the chapter that discusses that peripheral.

7.2.9 SoftwareRequest

One μDMA channel is dedicated to software-initiated transfers. This channel also has a dedicated interrupt to signal completion of a μDMA transfer. A transfer is initiated by software by first configuring and enabling the transfer, and then issuing a software request using theDMAChannelSoftware Request(DMASWREQ) register. For software-based transfers, the Auto transfer mode should be used. It is possible to initiate a transfer on any channel using theDMASWREQregister. If a request is initiated by software using a peripheral μDMA channel, then the completion interrupt occurs on the interrupt vector for the peripheral instead of the software interrupt vector. Any channel may be used for software requests as long as the corresponding peripheral is not using μDMA for data transfer. 353March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

7.2.10 InterruptsandErrors

When a μDMA transfer is complete, the μDMA controller generates a completion interrupt on the interrupt vector of the peripheral. Therefore, if μDMA is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the μDMA transfer completion interrupt. If the transfer uses the software μDMA channel, then the completion interrupt occurs on the dedicated software μDMA interrupt vector (see Table 7-6 on page 354). When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's interrupt registers). Thus, when a large amount of data is transferred using μDMA, instead of receiving multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the interrupt controller. If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data transfer, it disables the μDMA channel that caused the error and generates an interrupt on the μDMA error interrupt vector. The processor can read theDMABusErrorClear(DMAERRCLR) register to determine if an error is pending. TheERRCLR bit is set if an error occurred. The error can be cleared by writing a 1 to theERRCLR bit. Table 7-6 shows the dedicated interrupt assignments for the μDMA controller. Table7-6.μDMAInterruptAssignments AssignmentInterrupt μDMA Software Channel Transfer46 μDMA Error47

7.3 InitializationandConfiguration

7.3.1 ModuleInitialization

Before the μDMA controller can be used, it must be enabled in the System Control block and in the peripheral. The location of the channel control structure must also be programmed. The following steps should be performed one time during system initialization: 1. The μDMA peripheral must be enabled in the System Control block. To do this, set theUDMA bit of the System ControlRCGC2register (see page 286). 2. Enable the μDMA controller by setting theMASTEREN bit of theDMAConfiguration(DMACFG) register. 3. Program the location of the channel control table by writing the base address of the table to the DMAChannelControlBasePointer(DMACTLBASE) register. The base address must be aligned on a 1024-byte boundary.

7.3.2 ConfiguringaMemory-to-MemoryTransfer

μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used for software-initiated, memory-to-memory transfer if the associated peripheral is not being used. March 19, 2011354 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

7.3.2.1 ConfiguretheChannelAttributes

First, configure the channel attributes: 1. Program bit 30 of theDMAChannelPrioritySet(DMAPRIOSET) or DMAChannelPriority Clear(DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 30 of theDMAChannelPrimaryAlternateClear(DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 30 of theDMAChannelUseburstClear(DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 30 of theDMAChannelRequestMaskClear(DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel.

7.3.2.2 ConfiguretheChannelControlStructure

Now the channel control structure must be configured. This example transfers 256 words from one memory buffer to another. Channel 30 is used for a software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control table. The channel control structure for channel 30 is located at the offsets shown in Table 7-7. Table7-7.ChannelControlStructureOffsetsforChannel30 DescriptionOffset Channel 30 Source End PointerControl Table Base + 0x1E0 Channel 30 Destination End PointerControl Table Base + 0x1E4 Channel 30 Control WordControl Table Base + 0x1E8 Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). 1. Program the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC. 2. Program the destination end pointer at offset 0x1E4 to the address of the destination buffer + 0x3FC. The control word at offset 0x1E8 must be programmed according to Table 7-8. Table7-8.ChannelControlWordConfigurationforMemoryTransferExample DescriptionValueBitsFieldinDMACHCTL 32-bit destination address increment231:30DSTINC 32-bit destination data size229:28DSTSIZE 32-bit source address increment227:26SRCINC 32-bit source data size225:24SRCSIZE Reserved023:18reserved Arbitrates after 8 transfers317:14ARBSIZE Transfer 256 items25513:4XFERSIZE N/A for this transfer type03NXTUSEBURST Use Auto-request transfer mode22:0XFERMODE 355March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

7.3.2.3 StarttheTransfer

Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 30 of theDMAChannelEnableSet(DMAENASET) register. 2. Issue a transfer request by setting bit 30 of theDMAChannelSoftwareRequest(DMASWREQ) register. The μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt when the transfer is complete. If needed, the status can be checked by reading bit 30 of the DMAENASETregister. This bit is automatically cleared when the transfer is complete. The status can also be checked by reading theXFERMODE field of the channel control word at offset 0x1E8. This field is automatically cleared at the end of the transfer.

7.3.3 ConfiguringaPeripheralforSimpleTransmit

This example configures the μDMA controller to transmit a buffer of data to a peripheral. The peripheral has a transmit FIFO with a trigger level of 4. The example peripheral uses μDMA channel

7.3.3.1 ConfiguretheChannelAttributes

First, configure the channel attributes: 1. Configure bit 7 of theDMAChannelPrioritySet(DMAPRIOSET) or DMAChannelPriority Clear(DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 7 of theDMAChannelPrimaryAlternateClear(DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 7 of theDMAChannelUseburstClear(DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 7 of theDMAChannelRequestMaskClear(DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel.

7.3.3.2 ConfiguretheChannelControlStructure

This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register using μDMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control table. The channel control structure for channel 7 is located at the offsets shown in Table 7-9. Table7-9.ChannelControlStructureOffsetsforChannel7 DescriptionOffset Channel 7 Source End PointerControl Table Base + 0x070 Channel 7 Destination End PointerControl Table Base + 0x074 Channel 7 Control WordControl Table Base + 0x078 Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Because the peripheral pointer does not change, it simply points to the peripheral's data register. 1. Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F. March 19, 2011356 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

1. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO register. The control word at offset 0x078 must be programmed according to Table 7-10. Table7-10.ChannelControlWordConfigurationforPeripheralTransmitExample DescriptionValueBitsFieldinDMACHCTL Destination address does not increment331:30DSTINC 8-bit destination data size029:28DSTSIZE 8-bit source address increment027:26SRCINC 8-bit source data size025:24SRCSIZE Reserved023:18reserved Arbitrates after 4 transfers217:14ARBSIZE Transfer 64 items6313:4XFERSIZE N/A for this transfer type03NXTUSEBURST Use Basic transfer mode12:0XFERMODE Note: In this example, it is not important if the peripheral makes a single request or a burst request. Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to 4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what the FIFO can accommodate. If the peripheral makes a single request (if there is any space in the FIFO), then one byte is transferred at a time. If it is important to the application that transfers only be made in bursts, then the Channel UseburstSET[7] bit should be set in the DMAChannelUseburstSet(DMAUSEBURSTSET) register.

7.3.3.3 StarttheTransfer

Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 7 of theDMAChannelEnableSet(DMAENASET) register. The μDMA controller is now configured for transfer on channel 7. The controller makes transfers to the peripheral whenever the peripheral asserts a μDMA request. The transfers continue until the entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller disables the channel and sets theXFERMODE field of the channel control word to 0 (Stopped). The status of the transfer can be checked by reading bit 7 of theDMAChannelEnableSet(DMAENASET) register. This bit is automatically cleared when the transfer is complete. The status can also be checked by reading theXFERMODE field of the channel control word at offset 0x078. This field is automatically cleared at the end of the transfer. If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when the entire transfer is complete.

7.3.4 ConfiguringaPeripheralforPing-PongReceive

This example configures the μDMA controller to continuously receive 8-bit data from a peripheral into a pair of 64-byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example peripheral uses μDMA channel 8.

7.3.4.1 ConfiguretheChannelAttributes

First, configure the channel attributes: 357March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

1. Configure bit 8 of theDMAChannelPrioritySet(DMAPRIOSET) or DMAChannelPriority Clear(DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 8 of theDMAChannelPrimaryAlternateClear(DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 8 of theDMAChannelUseburstClear(DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 8 of theDMAChannelRequestMaskClear(DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel.

7.3.4.2 ConfiguretheChannelControlStructure

This example transfers bytes from the peripheral's receive FIFO register into two memory buffers of 64 bytes each. As data is received, when one buffer is full, the μDMA controller switches to use the other. To use Ping-Pong buffering, both primary and alternate channel control structures must be used. The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate channel control structure is at offset 0x280. The channel control structures for channel 8 are located at the offsets shown in Table 7-11. Table7-11.PrimaryandAlternateChannelControlStructureOffsetsforChannel8 DescriptionOffset Channel 8 Primary Source End PointerControl Table Base + 0x080 Channel 8 Primary Destination End PointerControl Table Base + 0x084 Channel 8 Primary Control WordControl Table Base + 0x088 Channel 8 Alternate Source End PointerControl Table Base + 0x280 Channel 8 Alternate Destination End PointerControl Table Base + 0x284 Channel 8 Alternate Control WordControl Table Base + 0x288 Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Because the peripheral pointer does not change, it simply points to the peripheral's data register. Both the primary and alternate sets of pointers must be configured. 1. Program the primary source end pointer at offset 0x080 to the address of the peripheral's receive buffer. 2. Program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer A + 0x3F. 3. Program the alternate source end pointer at offset 0x280 to the address of the peripheral's receive buffer. 4. Program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer B + 0x3F. The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially programmed the same way. 1. Program the primary channel control word at offset 0x088 according to Table 7-12. March 19, 2011358 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

1. Program the alternate channel control word at offset 0x288 according to Table 7-12. Table7-12.ChannelControlWordConfigurationforPeripheralPing-PongReceiveExample DescriptionValueBitsFieldinDMACHCTL 8-bit destination address increment031:30DSTINC 8-bit destination data size029:28DSTSIZE Source address does not increment327:26SRCINC 8-bit source data size025:24SRCSIZE Reserved023:18reserved Arbitrates after 8 transfers317:14ARBSIZE Transfer 64 items6313:4XFERSIZE N/A for this transfer type03NXTUSEBURST Use Ping-Pong transfer mode32:0XFERMODE Note: In this example, it is not important if the peripheral makes a single request or a burst request. Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to 8. If the peripheral does make a burst request, then 8 bytes are transferred, which is what the FIFO can accommodate. If the peripheral makes a single request (if there is any data in the FIFO), then one byte is transferred at a time. If it is important to the application that transfers only be made in bursts, then the Channel UseburstSET[8] bit should be set in the DMAChannelUseburstSet(DMAUSEBURSTSET) register.

7.3.4.3 ConfigurethePeripheralInterrupt

An interrupt handler should be configured when using μDMA Ping-Pong mode, it is best to use an interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling. The interrupt handler is triggered after each buffer is complete. 1. Configure and enable an interrupt handler for the peripheral.

7.3.4.4 EnabletheμDMAChannel

Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 8 of theDMAChannelEnableSet(DMAENASET) register.

7.3.4.5 ProcessInterrupts

The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral asserts the μDMA request signal, the μDMA controller makes transfers into buffer A using the primary channel control structure. When the primary transfer to buffer A is complete, it switches to the alternate channel control structure and makes transfers into buffer B. At the same time, the primary channel control word mode field is configured to indicate Stopped, and an interrupt is When an interrupt is triggered, the interrupt handler must determine which buffer is complete and process the data or set a flag that the data must be processed by non-interrupt buffer processing code. Then the next buffer transfer must be set up. In the interrupt handler: 1. Read the primary channel control word at offset 0x088 and check theXFERMODE field. If the field is 0, this means buffer A is complete. If buffer A is complete, then: 359March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

a. Process the newly received data in buffer A or signal the buffer processing code that buffer A has data available. b. Reprogram the primary channel control word at offset 0x88 according to Table 7-12 on page 359. 2. Read the alternate channel control word at offset 0x288 and check theXFERMODE field. If the field is 0, this means buffer B is complete. If buffer B is complete, then: a. Process the newly received data in buffer B or signal the buffer processing code that buffer B has data available. b. Reprogram the alternate channel control word at offset 0x288 according to Table 7-12 on page 359.

7.3.5 ConfiguringChannelAssignments

Channel assignments for each μDMA channel can be changed using theDMACHASGNregister. Each bit represents a μDMA channel. If the bit is set, then the secondary function is used for the channel. Refer to Table 7-1 on page 341 for channel assignments. For example, to use SSI1 Receive on channel 8 instead of UART0, set bit 8 of theDMACHASGN register.

7.4 RegisterMap

Table 7-13 on page 360 lists the μDMA channel control structures and registers. The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, that is, the base address is n/a (not applicable). In the table below, the offset for the channel control structures is the offset from the entry in the channel control table. See “Channel Configuration” on page 343 and Table 7-3 on page 344 for a description of how the entries in the channel control table are located in memory. The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers can be programmed (see page 286). There must be a delay of 3 system clocks after the μDMA module clock is enabled before any μDMA module registers are accessed. Table7-13.μDMARegisterMap See pageDescriptionResetTypeNameOffset μDMAChannelControlStructure(OffsetfromChannelControlTableBase) 362DMA Channel Source Address End Pointer-R/WDMASRCENDP0x000 363DMA Channel Destination Address End Pointer-R/WDMADSTENDP0x004 364DMA Channel Control Word-R/WDMACHCTL0x008 μDMARegisters(OffsetfromμDMABaseAddress) 369DMA Status0x001F.0000RODMASTAT0x000 371DMA Configuration-WODMACFG0x004 372DMA Channel Control Base Pointer0x0000.0000R/WDMACTLBASE0x008 March 19, 2011360 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Table7-13.μDMARegisterMap (continued) See pageDescriptionResetTypeNameOffset 373DMA Alternate Channel Control Base Pointer0x0000.0200RODMAALTBASE0x00C 374DMA Channel Wait-on-Request Status0xFFFF.FFC0RODMAWAITSTAT0x010 375DMA Channel Software Request-WODMASWREQ0x014 376DMA Channel Useburst Set0x0000.0000R/WDMAUSEBURSTSET0x018 377DMA Channel Useburst Clear-WODMAUSEBURSTCLR0x01C 378DMA Channel Request Mask Set0x0000.0000R/WDMAREQMASKSET0x020 379DMA Channel Request Mask Clear-WODMAREQMASKCLR0x024 380DMA Channel Enable Set0x0000.0000R/WDMAENASET0x028 381DMA Channel Enable Clear-WODMAENACLR0x02C 382DMA Channel Primary Alternate Set0x0000.0000R/WDMAALTSET0x030 383DMA Channel Primary Alternate Clear-WODMAALTCLR0x034 384DMA Channel Priority Set0x0000.0000R/WDMAPRIOSET0x038 385DMA Channel Priority Clear-WODMAPRIOCLR0x03C 386DMA Bus Error Clear0x0000.0000R/WDMAERRCLR0x04C 387DMA Channel Assignment0x0000.0000R/WDMACHASGN0x500 392DMA Peripheral Identification 40x0000.0004RODMAPeriphID40xFD0 388DMA Peripheral Identification 00x0000.0030RODMAPeriphID00xFE0 389DMA Peripheral Identification 10x0000.00B2RODMAPeriphID10xFE4 390DMA Peripheral Identification 20x0000.000BRODMAPeriphID20xFE8 391DMA Peripheral Identification 30x0000.0000RODMAPeriphID30xFEC 393DMA PrimeCell Identification 00x0000.000DRODMAPCellID00xFF0 394DMA PrimeCell Identification 10x0000.00F0RODMAPCellID10xFF4 395DMA PrimeCell Identification 20x0000.0005RODMAPCellID20xFF8 396DMA PrimeCell Identification 30x0000.00B1RODMAPCellID30xFFC 7.5 μDMAChannelControlStructure The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel has two control structures, which are located in a table in system memory. Refer to “Channel Configuration” on page 343 for an explanation of the Channel Control Table and the Channel Control Structure. The channel control structure is one entry in the channel control table. Each channel has a primary and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. 361March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register1:DMAChannelSourceAddressEndPointer(DMASRCENDP),offset 0x000 DMAChannelSourceAddressEndPointer(DMASRCENDP) is part of the Channel Control Structure and is used to specify the source address for a μDMA transfer. The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Source Address End Pointer (DMASRCENDP) Base n/a Offset 0x000 Type R/W, reset - 16171819202122232425262728293031 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Source Address End Pointer This field points to the last address of the μDMA transfer source (inclusive). If the source address is not incrementing (theSRCINC field in theDMACHCTLregister is 0x3), then this field points at the source location itself (such as a peripheral data register). -R/WADDR31:0 March 19, 2011362 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register2:DMAChannelDestinationAddressEndPointer(DMADSTENDP), offset0x004 DMAChannelDestinationAddressEndPointer(DMADSTENDP) is part of the Channel Control Structure and is used to specify the destination address for a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Destination Address End Pointer (DMADSTENDP) Base n/a Offset 0x004 Type R/W, reset - 16171819202122232425262728293031 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Destination Address End Pointer This field points to the last address of the μDMA transfer destination (inclusive). If the destination address is not incrementing (theDSTINC field in theDMACHCTLregister is 0x3), then this field points at the destination location itself (such as a peripheral data register). -R/WADDR31:0 363March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register3:DMAChannelControlWord(DMACHCTL),offset0x008 DMAChannelControlWord(DMACHCTL) is part of the Channel Control Structure and is used to specify parameters of a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Control Word (DMACHCTL) Base n/a Offset 0x008 Type R/W, reset - 16171819202122232425262728293031 ARBSIZEreservedSRCSIZESRCINCDSTSIZEDSTINC R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 XFERMODENXTUSEBURSTXFERSIZEARBSIZE R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Destination Address Increment This field configures the destination address increment. The address increment value must be equal or greater than the value of the destination size (DSTSIZE). DescriptionValue Byte Increment by 8-bit locations 0x0 Half-word Increment by 16-bit locations 0x1 Word Increment by 32-bit locations 0x2 No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel 0x3 -R/WDSTINC31:30 Destination Data Size This field configures the destination item data size. Note: DSTSIZE must be the same asSRCSIZE. DescriptionValue Byte 8-bit data size 0x0 Half-word 16-bit data size 0x1 Word 32-bit data size 0x2 Reserved0x3 -R/WDSTSIZE29:28 March 19, 2011364 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

DescriptionResetTypeNameBit/Field Source Address Increment This field configures the source address increment. The address increment value must be equal or greater than the value of the source size (SRCSIZE). DescriptionValue Byte Increment by 8-bit locations 0x0 Half-word Increment by 16-bit locations 0x1 Word Increment by 32-bit locations 0x2 No increment Address remains set to the value of the Source Address End Pointer (DMASRCENDP) for the channel 0x3 -R/WSRCINC27:26 Source Data Size This field configures the source item data size. Note: DSTSIZE must be the same asSRCSIZE. DescriptionValue Byte 8-bit data size. 0x0 Half-word 16-bit data size. 0x1 Word 32-bit data size. 0x2 Reserved0x3 -R/WSRCSIZE25:24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. -R/Wreserved23:18 365March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Arbitration Size This field configures the number of transfers that can occur before the μDMA controller re-arbitrates. The possible arbitration rate configurations represent powers of 2 and are shown below. DescriptionValue

1 Transfer

Arbitrates after each μDMA transfer 0x0

2 Transfers0x1

4 Transfers0x2

8 Transfers0x3

16 Transfers0x4

32 Transfers0x5

64 Transfers0x6

128 Transfers0x7

256 Transfers0x8

512 Transfers0x9

1024 Transfers

In this configuration, no arbitration occurs during the μDMA transfer because the maximum transfer size is 1024. 0xA-0xF -R/WARBSIZE17:14 Transfer Size (minus 1) This field configures the total number of items to transfer. The value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. The transfer size is the number of items, not the number of bytes. If the data size is 32 bits, then this value is the number of 32-bit words to transfer. The μDMA controller updates this field immediately prior to entering the arbitration process, so it contains the number of outstanding items that is necessary to complete the μDMA cycle. -R/WXFERSIZE13:4 Next Useburst This field controls whether the UseburstSET[n] bit is automatically set for the last transfer of a peripheral scatter-gather operation. Normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the μDMA controller uses single transfers to complete the transaction. If this bit is set, then the controller uses a burst transfer to complete the last transfer. -R/WNXTUSEBURST3 March 19, 2011366 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

DescriptionResetTypeNameBit/Field μDMA Transfer Mode This field configures the operating mode of the μDMA cycle. Refer to “Transfer Modes” on page 345 for a detailed explanation of transfer modes. Because this register is in system RAM, it has no reset value. Therefore, this field should be initialized to 0 before the channel is enabled. DescriptionValue Stop0x0 Basic0x1 Auto-Request0x2 Ping-Pong0x3 Memory Scatter-Gather0x4 Alternate Memory Scatter-Gather0x5 Peripheral Scatter-Gather0x6 Alternate Peripheral Scatter-Gather0x7 -R/WXFERMODE2:0 XFERMODEBitFieldValues. Stop Channel is stopped or configuration data is invalid. No more transfers can occur. Basic For each trigger (whether from a peripheral or a software request), the μDMA controller performs the number of transfers specified by theARBSIZE field. Auto-Request The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of XFERSIZE items without any further requests. Ping-Pong This mode uses both the primary and alternate control structures for this channel. When the number of transfers specified by theXFERSIZE field have completed for the current control structure (primary or alternate), the µDMA controller switches to the other one. These switches continue until one of the control structures is not set to ping-pong mode. At that point, the µDMA controller stops. An interrupt is generated on completion of the transfers configured by each control structure. See “Ping-Pong” on page 345. Memory Scatter-Gather When using this mode, the primary control structure for the channel is configured to allow a list of operations (tasks) to be performed. The source address pointer specifies the start of a table of tasks to be copied to the alternate control structure for this channel. TheXFERMODE field for the alternate control structure should be configured to 0x5 (Alternate memory scatter-gather) to perform the task. When the task completes, the µDMA switches back to the primary channel control structure, which then copies the next task to the alternate control structure. This process continues until the table of tasks is empty. The last task must have anXFERMODE value other than 0x5. Note that for continuous operation, the last task can update the primary channel control structure back to the start of the list or to another list. See “Memory Scatter-Gather” on page 347. 367March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Alternate Memory Scatter-Gather This value must be used in the alternate channel control data structure when the μDMA controller operates in Memory Scatter-Gather mode. Peripheral Scatter-Gather This value must be used in the primary channel control data structure when the μDMA controller operates in Peripheral Scatter-Gather mode. In this mode, the μDMA controller operates exactly the same as in Memory Scatter-Gather mode, except that instead of performing the number of transfers specified by theXFERSIZE field in the alternate control structure at one time, the μDMA controller only performs the number of transfers specified by theARBSIZE field per trigger; see Basic mode for details. See “Peripheral Scatter-Gather” on page 350. Alternate Peripheral Scatter-Gather This value must be used in the alternate channel control data structure when the μDMA controller operates in Peripheral Scatter-Gather mode. 7.6 μDMARegisterDescriptions The register addresses given are relative to the μDMA base address of 0x400F.F000. March 19, 2011368 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register4:DMAStatus(DMASTAT),offset0x000 The DMAStatus(DMASTAT) register returns the status of the μDMA controller. You cannot read this register when the μDMA controller is in the reset state. DMA Status (DMASTAT) Base 0x400F.F000 Offset 0x000 Type RO, reset 0x001F.0000 16171819202122232425262728293031 DMACHANSreserved ROROROROROROROROROROROROROROROROType 1111100000000000Reset 0123456789101112131415 MASTENreservedSTATEreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:21 Available μDMA Channels Minus 1 This field contains a value equal to the number of μDMA channels the μDMA controller is configured to use, minus one. The value of 0x1F corresponds to 32 μDMA channels. 0x1FRODMACHANS20:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved15:8 Control State Machine Status This field shows the current status of the control state machine. Status can be one of the following. DescriptionValue Idle0x0 Reading channel controller data.0x1 Reading source end pointer.0x2 Reading destination end pointer.0x3 Reading source data.0x4 Writing destination data.0x5 Waiting for µDMA request to clear.0x6 Writing channel controller data.0x7 Stalled0x8 Done0x9 Undefined0xA-0xF 0x0ROSTATE7:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:1 369March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Master Enable Status DescriptionValue The μDMA controller is disabled.0 The μDMA controller is enabled.1 0ROMASTEN0 March 19, 2011370 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register5:DMAConfiguration(DMACFG),offset0x004 The DMACFGregister controls the configuration of the μDMA controller. DMA Configuration (DMACFG) Base 0x400F.F000 Offset 0x004 Type WO, reset - 16171819202122232425262728293031 reserved WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0123456789101112131415 MASTENreserved WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. -WOreserved31:1 Controller Master Enable DescriptionValue Disables the μDMA controller.0 Enables μDMA controller.1 -WOMASTEN0 371March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register6:DMAChannelControlBasePointer(DMACTLBASE),offset0x008 The DMACTLBASEregister must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the μDMA controller depends on the number of μDMA channels used and whether the alternate channel control data structure is used. See “Channel Configuration” on page 343 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. This register cannot be read when the μDMA controller is in the reset state. DMA Channel Control Base Pointer (DMACTLBASE) Base 0x400F.F000 Offset 0x008 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 reservedADDR ROROROROROROROROROROR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Channel Control Base Address This field contains the pointer to the base address of the channel control table. The base address must be 1024-byte aligned. 0x0000.00R/WADDR31:10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved9:0 March 19, 2011372 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register7:DMAAlternateChannelControlBasePointer(DMAALTBASE), offset0x00C The DMAALTBASEregister returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. This register cannot be read when the μDMA controller is in the reset state. DMA Alternate Channel Control Base Pointer (DMAALTBASE) Base 0x400F.F000 Offset 0x00C Type RO, reset 0x0000.0200 16171819202122232425262728293031 ADDR ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ADDR ROROROROROROROROROROROROROROROROType 0000000001000000Reset DescriptionResetTypeNameBit/Field Alternate Channel Address Pointer This field provides the base address of the alternate channel control structures. 0x0000.0200ROADDR31:0 373March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register8:DMAChannelWait-on-RequestStatus(DMAWAITSTAT),offset 0x010 This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can hold off the μDMA from performing a single request until the peripheral is ready for a burst request to enhance the μDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the μDMA controller is in the reset state. DMA Channel Wait-on-Request Status (DMAWAITSTAT) Base 0x400F.F000 Offset 0x010 Type RO, reset 0xFFFF.FFC0 16171819202122232425262728293031 WAITREQ[n] ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 WAITREQ[n] ROROROROROROROROROROROROROROROROType 0000001111111111Reset DescriptionResetTypeNameBit/Field Channel [n] Wait Status These bits provide the channel wait-on-request status. Bit 0 corresponds to channel 0. DescriptionValue The corresponding channel is waiting on a request.1 The corresponding channel is not waiting on a request.0 0xFFFF.FFC0ROWAITREQ[n]31:0 March 19, 2011374 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register9:DMAChannelSoftwareRequest(DMASWREQ),offset0x014 Each bit of theDMASWREQregister represents the corresponding μDMA channel. Setting a bit generates a request for the specified μDMA channel. DMA Channel Software Request (DMASWREQ) Base 0x400F.F000 Offset 0x014 Type WO, reset - 16171819202122232425262728293031 SWREQ[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0123456789101112131415 SWREQ[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType DescriptionResetTypeNameBit/Field Channel [n] Software Request These bits generate software requests. Bit 0 corresponds to channel 0. DescriptionValue Generate a software request for the corresponding channel.1 No request generated.0 These bits are automatically cleared when the software request has been completed. -WOSWREQ[n]31:0 375March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register10:DMAChannelUseburstSet(DMAUSEBURSTSET),offset0x018 Each bit of theDMAUSEBURSTSETregister represents the corresponding μDMA channel. Setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the arbitration (burst) size, the correspondingSET[n] bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the μDMA controller automatically clears the correspondingSET[n] bit, allowing the remaining items to transfer using single requests. In order to resume transfers using burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding peripheral does not support the burst request model. Refer to “Request Types” on page 342 for more details about request types. DMA Channel Useburst Set (DMAUSEBURSTSET) Base 0x400F.F000 Offset 0x018 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Channel [n] Useburst Set DescriptionValue μDMA channel [n] responds to single or burst requests.0 μDMA channel [n] responds only to burst requests.1 Bit 0 corresponds to channel 0. This bit is automatically cleared as described above. A bit can also be manually cleared by setting the corresponding CLR[n] bit in theDMAUSEBURSTCLRregister. 0x0000.0000R/WSET[n]31:0 March 19, 2011376 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register11:DMAChannelUseburstClear(DMAUSEBURSTCLR),offset0x01C Each bit of theDMAUSEBURSTCLRregister represents the corresponding μDMA channel. Setting a bit clears the correspondingSET[n] bit in theDMAUSEBURSTSETregister. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Base 0x400F.F000 Offset 0x01C Type WO, reset - 16171819202122232425262728293031 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0123456789101112131415 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType DescriptionResetTypeNameBit/Field Channel [n] Useburst Clear DescriptionValue No effect.0 Setting a bit clears the correspondingSET[n] bit in the DMAUSEBURSTSETregister meaning that µDMA channel [n] responds to single and burst requests. -WOCLR[n]31:0 377March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register12:DMAChannelRequestMaskSet(DMAREQMASKSET),offset 0x020 Each bit of theDMAREQMASKSETregister represents the corresponding μDMA channel. Setting a bit disables μDMA requests for the channel. Reading the register returns the request mask status. When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA transfers. The channel can then be used for software-initiated transfers. DMA Channel Request Mask Set (DMAREQMASKSET) Base 0x400F.F000 Offset 0x020 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Channel [n] Request Mask Set DescriptionValue The peripheral associated with channel [n] is enabled to request μDMA transfers. The peripheral associated with channel [n] is not able to request μDMA transfers. Channel [n] may be used for software-initiated transfers. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in theDMAREQMASKCLRregister. 0x0000.0000R/WSET[n]31:0 March 19, 2011378 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register13:DMAChannelRequestMaskClear(DMAREQMASKCLR),offset 0x024 Each bit of theDMAREQMASKCLRregister represents the corresponding μDMA channel. Setting a bit clears the correspondingSET[n] bit in theDMAREQMASKSETregister. DMA Channel Request Mask Clear (DMAREQMASKCLR) Base 0x400F.F000 Offset 0x024 Type WO, reset - 16171819202122232425262728293031 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0123456789101112131415 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType DescriptionResetTypeNameBit/Field Channel [n] Request Mask Clear DescriptionValue No effect.0 Setting a bit clears the correspondingSET[n] bit in the DMAREQMASKSETregister meaning that the peripheral associated with channel [n] is enabled to request μDMA transfers. -WOCLR[n]31:0 379March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register14:DMAChannelEnableSet(DMAENASET),offset0x028 Each bit of theDMAENASETregister represents the corresponding µDMA channel. Setting a bit enables the corresponding µDMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for software-initiated transfers. DMA Channel Enable Set (DMAENASET) Base 0x400F.F000 Offset 0x028 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Channel [n] Enable Set DescriptionValue µDMA Channel [n] is disabled.0 µDMA Channel [n] is enabled.1 Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in theDMAENACLRregister. 0x0000.0000R/WSET[n]31:0 March 19, 2011380 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register15:DMAChannelEnableClear(DMAENACLR),offset0x02C Each bit of theDMAENACLRregister represents the corresponding µDMA channel. Setting a bit clears the correspondingSET[n] bit in theDMAENASETregister. DMA Channel Enable Clear (DMAENACLR) Base 0x400F.F000 Offset 0x02C Type WO, reset - 16171819202122232425262728293031 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0123456789101112131415 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType DescriptionResetTypeNameBit/Field Clear Channel [n] Enable Clear DescriptionValue No effect.0 Setting a bit clears the correspondingSET[n] bit in the DMAENASETregister meaning that channel [n] is disabled for μDMA transfers. Note: The controller disables a channel when it completes the μDMA cycle. -WOCLR[n]31:0 381March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register16:DMAChannelPrimaryAlternateSet(DMAALTSET),offset0x030 Each bit of theDMAALTSETregister represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding µDMA channel. DMA Channel Primary Alternate Set (DMAALTSET) Base 0x400F.F000 Offset 0x030 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Channel [n] Alternate Set DescriptionValue µDMA channel [n] is using the primary control structure.0 µDMA channel [n] is using the alternate control structure.1 Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in theDMAALTCLRregister. Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure. 0x0000.0000R/WSET[n]31:0 March 19, 2011382 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register17:DMAChannelPrimaryAlternateClear(DMAALTCLR),offset 0x034 Each bit of theDMAALTCLRregister represents the corresponding μDMA channel. Setting a bit clears the correspondingSET[n] bit in theDMAALTSETregister. DMA Channel Primary Alternate Clear (DMAALTCLR) Base 0x400F.F000 Offset 0x034 Type WO, reset - 16171819202122232425262728293031 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0123456789101112131415 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType DescriptionResetTypeNameBit/Field Channel [n] Alternate Clear DescriptionValue No effect.0 Setting a bit clears the correspondingSET[n] bit in the DMAALTSETregister meaning that channel [n] is using the primary control structure. Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure. -WOCLR[n]31:0 383March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register18:DMAChannelPrioritySet(DMAPRIOSET),offset0x038 Each bit of theDMAPRIOSETregister represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask. DMA Channel Priority Set (DMAPRIOSET) Base 0x400F.F000 Offset 0x038 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 SET[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Channel [n] Priority Set DescriptionValue µDMA channel [n] is using the default priority level.0 µDMA channel [n] is using a high priority level.1 Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in theDMAPRIOCLRregister. 0x0000.0000R/WSET[n]31:0 March 19, 2011384 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register19:DMAChannelPriorityClear(DMAPRIOCLR),offset0x03C Each bit of theDMAPRIOCLRregister represents the corresponding µDMA channel. Setting a bit clears the correspondingSET[n] bit in theDMAPRIOSETregister. DMA Channel Priority Clear (DMAPRIOCLR) Base 0x400F.F000 Offset 0x03C Type WO, reset - 16171819202122232425262728293031 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0123456789101112131415 CLR[n] WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType DescriptionResetTypeNameBit/Field Channel [n] Priority Clear DescriptionValue No effect.0 Setting a bit clears the correspondingSET[n] bit in the DMAPRIOSETregister meaning that channel [n] is using the default priority level. -WOCLR[n]31:0 385March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register20:DMABusErrorClear(DMAERRCLR),offset0x04C The DMAERRCLRregister is used to read and clear the µDMA bus error status. The error status is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the μDMA controller. The other channels are unaffected. DMA Bus Error Clear (DMAERRCLR) Base 0x400F.F000 Offset 0x04C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ERRCLRreserved R/W1CROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 μDMA Bus Error Status DescriptionValue No bus error is pending.0 A bus error is pending.1 This bit is cleared by writing a 1 to it. 0R/W1CERRCLR0 March 19, 2011386 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register21:DMAChannelAssignment(DMACHASGN),offset0x500 Each bit of theDMACHASGNregister represents the corresponding µDMA channel. Setting a bit selects the secondary channel assignment as specified in Table 7-1 on page 341. DMA Channel Assignment (DMACHASGN) Base 0x400F.F000 Offset 0x500 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 CHASGN[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 CHASGN[n] R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Channel [n] Assignment Select DescriptionValue Use the primary channel assignment.0 Use the secondary channel assignment.1 -R/WCHASGN[n]31:0 387March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register22:DMAPeripheralIdentification0(DMAPeriphID0),offset0xFE0 The DMAPeriphIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 0 (DMAPeriphID0) Base 0x400F.F000 Offset 0xFE0 Type RO, reset 0x0000.0030 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID0reserved ROROROROROROROROROROROROROROROROType 0000110000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 μDMA Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 0x30ROPID07:0 March 19, 2011388 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register23:DMAPeripheralIdentification1(DMAPeriphID1),offset0xFE4 The DMAPeriphIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 1 (DMAPeriphID1) Base 0x400F.F000 Offset 0xFE4 Type RO, reset 0x0000.00B2 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID1reserved ROROROROROROROROROROROROROROROROType 0100110100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 μDMA Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 0xB2ROPID17:0 389March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register24:DMAPeripheralIdentification2(DMAPeriphID2),offset0xFE8 The DMAPeriphIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 2 (DMAPeriphID2) Base 0x400F.F000 Offset 0xFE8 Type RO, reset 0x0000.000B 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID2reserved ROROROROROROROROROROROROROROROROType 1101000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 μDMA Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 0x0BROPID27:0 March 19, 2011390 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register25:DMAPeripheralIdentification3(DMAPeriphID3),offset0xFEC The DMAPeriphIDnregisters are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 3 (DMAPeriphID3) Base 0x400F.F000 Offset 0xFEC Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID3reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 μDMA Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 0x00ROPID37:0 391March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register26:DMAPeripheralIdentification4(DMAPeriphID4),offset0xFD0 The DMAPeriphIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 4 (DMAPeriphID4) Base 0x400F.F000 Offset 0xFD0 Type RO, reset 0x0000.0004 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID4reserved ROROROROROROROROROROROROROROROROType 0010000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 μDMA Peripheral ID Register Can be used by software to identify the presence of this peripheral. 0x04ROPID47:0 March 19, 2011392 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register27:DMAPrimeCellIdentification0(DMAPCellID0),offset0xFF0 The DMAPCellIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 0 (DMAPCellID0) Base 0x400F.F000 Offset 0xFF0 Type RO, reset 0x0000.000D 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID0reserved ROROROROROROROROROROROROROROROROType 1011000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 μDMA PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 0x0DROCID07:0 393March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register28:DMAPrimeCellIdentification1(DMAPCellID1),offset0xFF4 The DMAPCellIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 1 (DMAPCellID1) Base 0x400F.F000 Offset 0xFF4 Type RO, reset 0x0000.00F0 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID1reserved ROROROROROROROROROROROROROROROROType 0000111100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 μDMA PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 0xF0ROCID17:0 March 19, 2011394 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

Register29:DMAPrimeCellIdentification2(DMAPCellID2),offset0xFF8 The DMAPCellIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 2 (DMAPCellID2) Base 0x400F.F000 Offset 0xFF8 Type RO, reset 0x0000.0005 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID2reserved ROROROROROROROROROROROROROROROROType 1010000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:8 μDMA PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 0x05ROCID27:0 395March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register30:DMAPrimeCellIdentification3(DMAPCellID3),offset0xFFC The DMAPCellIDnregisters are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 3 (DMAPCellID3) Base 0x400F.F000 Offset 0xFFC Type RO, reset 0x0000.00B1 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID3reserved ROROROROROROROROROROROROROROROROType 1000110100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:8 μDMA PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 0xB1ROCID37:0 March 19, 2011396 Texas Instruments-Advance Information Micro Direct Memory Access (μDMA)

8 General-PurposeInput/Outputs(GPIOs)

The GPIO module is composed of nine physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H, Port J). The GPIO module supports up to 65 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Up to 65 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Fast toggle capable of a change every two clock cycles ■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables

8.1 SignalDescription

GPIO signals have alternate hardware functions. Table 8-2 on page 398 and Table 8-3 on page 400 list the GPIO pins and their analog and digital alternate functions. TheAINx and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the correspondingDEN bit in theGPIODigitalEnable(GPIODEN) register and setting the correspondingAMSEL bit in theGPIOAnalogModeSelect(GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-, 397March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

C0+, C1-, C1+, C2-, C2+, USB0VBUS, USB0ID). These signals are configured by clearing theDEN bit in theGPIODigitalEnable(GPIODEN) register. The digital alternate hardware functions are enabled by setting the appropriate bit in theGPIOAlternateFunctionSelect(GPIOAFSEL) and GPIODENregisters and configuring thePMCx bit field in theGPIOPortControl(GPIOPCTL) register to the numeric encoding shown in the table below. Note that each pin must be programmed individually; no type of grouping is implied by the columns in the table. Table entries that are shaded gray are the default values for the corresponding GPIO pin. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, andGPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table8-1.GPIOPinsWithNon-ZeroResetValues GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefaultStateGPIOPins 0x10010UART0PA[1:0] 0x10010SSI0PA[5:2] 0x10010I2C0PB[3:2] 0x31011JTAG/SWDPC[3:0] Table8-2.GPIOPinsandAlternateFunctions(100LQFP) DigitalFunction(GPIOPCTLPMCxBitFieldEncoding) a Analog FunctionPin IO 1110987654321 - -U1RxI2C1SCL- - - - - -U0Rx- 26PA0 - -U1TxI2C1SDA- - - - - -U0Tx- 27PA1 - -I2S0RXSD- - - -PWM4- -SSI0Clk- 28PA2 - -I2S0RXMCLK- - - -PWM5- -SSI0Fss- 29PA3 - -I2S0TXSCK- - -CAN0RxPWM6- -SSI0Rx- 30PA4 - -I2S0TXWS- - -CAN0TxPWM7- -SSI0Tx- 31PA5 - -U1CTSUSB0EPEN-CAN0RxPWM4PWM0-CCP1I2C1SCL- 34PA6 - -U1DCDUSB0PFLTCCP3CAN0TxPWM5PWM1-CCP4I2C1SDA- 35PA7 - - - - - -U1Rx- -PWM2CCP0USB0ID66PB0 - - - - - -U1TxCCP1-PWM3CCP2USB0VBUS67PB1 - - -USB0EPEN- -CCP0CCP3-IDX0I2C0SCL- 72PB2 - - -USB0PFLT- - -Fault3-Fault0I2C0SDA- 65PB3 - - -EPI0S23U1RxIDX0CAN0RxU2Rx- - -AIN10 C0- 92PB4 - - -EPI0S22U1TxCCP2CAN0TxCCP0CCP6CCP5C0oAIN11 C1- 91PB5 - -I2S0TXSCK- -CCP5IDX0Fault1C0oCCP7CCP1VREFA C0+ 90PB6 - - - - - - - -TCK SWCLK - - - 80PC0 - - - - - - - -TMS SWDIO - - - 79PC1 March 19, 2011398 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Table8-2.GPIOPinsandAlternateFunctions(100LQFP) (continued) DigitalFunction(GPIOPCTLPMCxBitFieldEncoding) a Analog FunctionPin IO 1110987654321 - - - - - - - -TDO SWO - - - 77PC3 - -CCP1EPI0S2-CCP4CCP2PWM6-PhA0CCP5- 25PC4 - - -EPI0S3-USB0EPENCCP3Fault2C0oC1oCCP1C1+24PC5 - - -EPI0S4USB0PFLTCCP0U1RxPWM7C2oPhB0CCP3C2+23PC6 - - -EPI0S5C1oUSB0PFLTU1TxCCP0-PhB0CCP4C2-22PC7 - -U1CTSI2S0RXSCK-CCP6U1RxU2RxIDX0CAN0RxPWM0AIN1510PD0 PhB1CCP2U1DCDI2S0RXWS-CCP7U1TxU2TxPhA0CAN0TxPWM1AIN1411PD1 - - -EPI0S20- - -CCP5PWM2CCP6U1RxAIN1312PD2 - - -EPI0S21- - -CCP0PWM3CCP7U1TxAIN1213PD3 -EPI0S19U1RII2S0RXSD- - - - -CCP3CCP0AIN797PD4 -EPI0S28U2RxI2S0RXMCLK- - - - -CCP4CCP2AIN698PD5 -EPI0S29U2TxI2S0TXSCK- - - - - -Fault0AIN599PD6 -EPI0S30U1DTRI2S0TXWS- - - -CCP1C0oIDX0AIN4100PD7 - -USB0PFLTEPI0S8- - - -CCP3SSI1ClkPWM4- 74PE0 - - -EPI0S9- -CCP6CCP2Fault0SSI1FssPWM5- 75PE1 - - -EPI0S24- -CCP2PhA0PhB1SSI1RxCCP4AIN995PE2 - - -EPI0S25- -CCP7PhB0PhA1SSI1TxCCP1AIN896PE3 - -I2S0TXWS- -CCP2U2TxFault0- -CCP3AIN36PE4 - -I2S0TXSD- - - - - - -CCP5AIN25PE5 - -U1CTS- - - - - -C1oPWM4AIN12PE6 - -U1DCD- - - - - -C2oPWM5AIN01PE7 - -U1DSRI2S0TXSD- - - -PWM0PhB0CAN1Rx- 47PF0 -CCP3U1RTSI2S0TXMCLK- - - -PWM1IDX1CAN1Tx- 61PF1 - -SSI1Clk- - - -PWM2-PWM4LED1- 60PF2 - -SSI1Fss- - - -PWM3-PWM5LED0- 59PF3 - -SSI1RxEPI0S12- - -Fault0-C0oCCP0- 42PF4 - -SSI1TxEPI0S15- - - - -C1oCCP2- 41PF5 - - -EPI0S13USB0EPEN- -PWM4I2C1SCLPWM0U2Rx- 19PG0 - - -EPI0S14- - -PWM5I2C1SDAPWM1U2Tx- 18PG1 - -EPI0S31CCP5- - -PWM7- -PhB1- 36PG7 - -PWM4EPI0S6- - - - -PWM2CCP6- 86PH0 - -PWM5EPI0S7- - - - -PWM3CCP7- 85PH1 - - -EPI0S1- - -Fault3-C1oIDX1- 84PH2 - - -EPI0S0- - -USB0EPEN-Fault0PhB0- 83PH3 SSI1Clk- -EPI0S10- - -USB0PFLT- - - - 76PH4 SSI1FssFault2-EPI0S11- - - - - - - - 63PH5 SSI1RxPWM4-EPI0S26- - - - - - - - 62PH6 SSI1TxPWM5-EPI0S27- - - - - - - - 15PH7 399March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table8-2.GPIOPinsandAlternateFunctions(100LQFP) (continued) DigitalFunction(GPIOPCTLPMCxBitFieldEncoding) a Analog FunctionPin IO 1110987654321 I2C1SCLPWM0-EPI0S16- - - - - - - - 14PJ0 I2C1SDAPWM1USB0PFLTEPI0S17- - - - - - - - 87PJ1 -Fault0CCP0EPI0S18- - - - - - - - 39PJ2 -CCP6U1CTSEPI0S19- - - - - - - - 50PJ3 -CCP4U1DCDEPI0S28- - - - - - - - 52PJ4 -CCP2U1DSREPI0S29- - - - - - - - 53PJ5 -CCP1U1RTSEPI0S30- - - - - - - - 54PJ6 -CCP0U1DTR- - - - - - - - - 55PJ7 a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. Table8-3.GPIOPinsandAlternateFunctions(108BGA) DigitalFunction(GPIOPCTLPMCxBitFieldEncoding) a Analog FunctionPin IO 1110987654321 - -U1RxI2C1SCL- - - - - -U0Rx- L3PA0 - -U1TxI2C1SDA- - - - - -U0Tx- M3PA1 - -I2S0RXSD- - - -PWM4- -SSI0Clk- M4PA2 - -I2S0RXMCLK- - - -PWM5- -SSI0Fss- L4PA3 - -I2S0TXSCK- - -CAN0RxPWM6- -SSI0Rx- L5PA4 - -I2S0TXWS- - -CAN0TxPWM7- -SSI0Tx- M5PA5 - -U1CTSUSB0EPEN-CAN0RxPWM4PWM0-CCP1I2C1SCL- L6PA6 - -U1DCDUSB0PFLTCCP3CAN0TxPWM5PWM1-CCP4I2C1SDA- M6PA7 - - - - - -U1Rx- -PWM2CCP0USB0IDE12PB0 - - - - - -U1TxCCP1-PWM3CCP2USB0VBUSD12PB1 - - -USB0EPEN- -CCP0CCP3-IDX0I2C0SCL- A11PB2 - - -USB0PFLT- - -Fault3-Fault0I2C0SDA- E11PB3 - - -EPI0S23U1RxIDX0CAN0RxU2Rx- - -AIN10 C0- A6PB4 - - -EPI0S22U1TxCCP2CAN0TxCCP0CCP6CCP5C0oAIN11 C1- B7PB5 - -I2S0TXSCK- -CCP5IDX0Fault1C0oCCP7CCP1VREFA C0+ A7PB6 - - - - - - - -TCK SWCLK - - - A9PC0 - - - - - - - -TMS SWDIO - - - B9PC1 - - - - - - - -TDO SWO - - - A10PC3 - -CCP1EPI0S2-CCP4CCP2PWM6-PhA0CCP5- L1PC4 - - -EPI0S3-USB0EPENCCP3Fault2C0oC1oCCP1C1+M1PC5 - - -EPI0S4USB0PFLTCCP0U1RxPWM7C2oPhB0CCP3C2+M2PC6 March 19, 2011400 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Table8-3.GPIOPinsandAlternateFunctions(108BGA) (continued) DigitalFunction(GPIOPCTLPMCxBitFieldEncoding) a Analog FunctionPin IO 1110987654321 - - -EPI0S5C1oUSB0PFLTU1TxCCP0-PhB0CCP4C2-L2PC7 - -U1CTSI2S0RXSCK-CCP6U1RxU2RxIDX0CAN0RxPWM0AIN15G1PD0 PhB1CCP2U1DCDI2S0RXWS-CCP7U1TxU2TxPhA0CAN0TxPWM1AIN14G2PD1 - - -EPI0S20- - -CCP5PWM2CCP6U1RxAIN13H2PD2 - - -EPI0S21- - -CCP0PWM3CCP7U1TxAIN12H1PD3 -EPI0S19U1RII2S0RXSD- - - - -CCP3CCP0AIN7B5PD4 -EPI0S28U2RxI2S0RXMCLK- - - - -CCP4CCP2AIN6C6PD5 -EPI0S29U2TxI2S0TXSCK- - - - - -Fault0AIN5A3PD6 -EPI0S30U1DTRI2S0TXWS- - - -CCP1C0oIDX0AIN4A2PD7 - -USB0PFLTEPI0S8- - - -CCP3SSI1ClkPWM4- B11PE0 - - -EPI0S9- -CCP6CCP2Fault0SSI1FssPWM5- A12PE1 - - -EPI0S24- -CCP2PhA0PhB1SSI1RxCCP4AIN9A4PE2 - - -EPI0S25- -CCP7PhB0PhA1SSI1TxCCP1AIN8B4PE3 - -I2S0TXWS- -CCP2U2TxFault0- -CCP3AIN3B2PE4 - -I2S0TXSD- - - - - - -CCP5AIN2B3PE5 - -U1CTS- - - - - -C1oPWM4AIN1A1PE6 - -U1DCD- - - - - -C2oPWM5AIN0B1PE7 - -U1DSRI2S0TXSD- - - -PWM0PhB0CAN1Rx- M9PF0 -CCP3U1RTSI2S0TXMCLK- - - -PWM1IDX1CAN1Tx- H12PF1 - -SSI1Clk- - - -PWM2-PWM4LED1- J11PF2 - -SSI1Fss- - - -PWM3-PWM5LED0- J12PF3 - -SSI1RxEPI0S12- - -Fault0-C0oCCP0- K4PF4 - -SSI1TxEPI0S15- - - - -C1oCCP2- K3PF5 - - -EPI0S13USB0EPEN- -PWM4I2C1SCLPWM0U2Rx- K1PG0 - - -EPI0S14- - -PWM5I2C1SDAPWM1U2Tx- K2PG1 - -EPI0S31CCP5- - -PWM7- -PhB1- C10PG7 - -PWM4EPI0S6- - - - -PWM2CCP6- C9PH0 - -PWM5EPI0S7- - - - -PWM3CCP7- C8PH1 - - -EPI0S1- - -Fault3-C1oIDX1- D11PH2 - - -EPI0S0- - -USB0EPEN-Fault0PhB0- D10PH3 SSI1Clk- -EPI0S10- - -USB0PFLT- - - - B10PH4 SSI1FssFault2-EPI0S11- - - - - - - - F10PH5 SSI1RxPWM4-EPI0S26- - - - - - - - G3PH6 SSI1TxPWM5-EPI0S27- - - - - - - - H3PH7 I2C1SCLPWM0-EPI0S16- - - - - - - - F3PJ0 I2C1SDAPWM1USB0PFLTEPI0S17- - - - - - - - B6PJ1 -Fault0CCP0EPI0S18- - - - - - - - K6PJ2 -CCP6U1CTSEPI0S19- - - - - - - -M10PJ3 -CCP4U1DCDEPI0S28- - - - - - - - K11PJ4 -CCP2U1DSREPI0S29- - - - - - - - K12PJ5 401March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table8-3.GPIOPinsandAlternateFunctions(108BGA) (continued) DigitalFunction(GPIOPCTLPMCxBitFieldEncoding) a Analog FunctionPin IO 1110987654321 -CCP1U1RTSEPI0S30- - - - - - - - L10PJ6 -CCP0U1DTR- - - - - - - - - L12PJ7 a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.

8.2 FunctionalDescription

Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-1 on page 402 and Figure 8-2 on page 403). The LM3S9B92 microcontroller contains nineports and thus nine of these physical GPIO blocks. Note that not all pins may be implemented on every block. Some GPIO pins can function as I/O signals for the on-chip peripheral modules. For information on which GPIO pins are used for alternate hardware functions, refer to Table 24-5 on page 1247. Figure8-1.DigitalI/OPads Pad Control Commit Control Mode Control GPIOAFSEL Data Control Interrupt Control MUXMUX DEMUX Digital I/O Pad Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Pad Input Pad Output Enable GPIOLOCK GPIOCR GPIODA T A GPIODIR GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Alternate Input Alternate Output Alternate Output Enable Interrupt GPIO Input GPIO Output GPIO Output Enable Pad Output Package I/O Pin MUX Periph 0 Periph 1 Periph n Port Control GPIOPCTL March 19, 2011402 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Figure8-2.Analog/DigitalI/OPads Pad Control Data Control GPIO Input GPIO Output GPIO Output Enable Interrupt Control Interrupt MUXMUX GPIODR8R GPIODR2R GPIODR4R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN GPIOAMSEL GPIOIEV GPIOIS GPIOIBE GPIOIM GPIORIS GPIOMIS GPIOICR GPIODA T A GPIODIR Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Analog Circuitry (for GPIO pins that connect to the ADC input MUX ) ADC Isolation Circuit Pad Output Enable Package I/O Pin Pad Input Pad Output Analog/Digital I/O Pad Commit Control Mode Control GPIOAFSEL GPIOLOCK GPIOCR Alternate Input Alternate Output Alternate Output Enable MUX Periph 0 Periph 1 Periph n Port Control GPIOPCTL DEMUX

8.2.1 DataControl

The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller . If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger .

8.2.1.1 DataDirectionOperation

The GPIODirection(GPIODIR) register (see page 412) is used to configure each individual pin as an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data register bit captures and stores the value on the GPIO port. When the data direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is driven out on the GPIO port. 403March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

8.2.1.2 DataRegisterOperation

To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIOData(GPIODATA) register (see page 411) by using bits [9:2] of the address bus as a mask. In this manner, software drivers can modify individual GPIO pins in a single instruction without affecting the state of the other pins. This method is more efficient than the conventional method of performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this feature, theGPIODATAregister covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set, the value of theGPIODATA register is altered. If the address bit is cleared, the data bit is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in Figure 8-3, whereu indicates that data is unchanged by the write. Figure8-3.GPIODATAWriteExample 0 10 0 1 10 0 0 u 1u u 0 1u u 9 8 7 6 5 4 3 2 1 0 1 11 0 0 11 1 7 6 5 4 3 2 1 0 GPIODA T A 0xEB 0x098 ADDR[9:2] During a read, if the address bit associated with the data bit is set, the value is read. If the address bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-4. Figure8-4.GPIODATAReadExample 0 10 1 0 00 1 0 0 0 10 1 0 00 0 9 8 7 6 5 4 3 2 1 0 0 11 1 1 11 0 7 6 5 4 3 2 1 0 Returned V alue GPIODA T A 0x0C4 ADDR[9:2]

8.2.2 InterruptControl

The interrupt capabilities of each GPIO port are controlled by a set of seven registers. These registers are used to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, the external source must hold the level constant for the interrupt to be recognized by the controller. Three registers define the edge or sense that causes interrupts: ■ GPIOInterruptSense(GPIOIS) register (see page 413) March 19, 2011404 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

■ GPIOInterruptBothEdges(GPIOIBE) register (see page 414) ■ GPIOInterruptEvent(GPIOIEV) register (see page 415) Interrupts are enabled/disabled via theGPIOInterruptMask(GPIOIM) register (see page 416). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIORawInterruptStatus(GPIORIS) and GPIOMaskedInterruptStatus(GPIOMIS) registers (see page 417 and page 418). As the name implies, theGPIOMISregister only shows interrupt conditions that are allowed to be passed to the interrupt controller. TheGPIORISregister indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the interrupt controller. Interrupts are cleared by writing a 1 to the appropriate bit of theGPIOInterruptClear(GPIOICR) register (see page 420). When programming the interrupt control registers (GPIOIS, GPIOIBE, orGPIOIEV), the interrupts should be masked (GPIOIMcleared). Writing any value to an interrupt control register can generate a spurious interrupt if the corresponding bits are enabled.

8.2.2.1 ADCTriggerSource

In addition to providing GPIO functionality,PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit ofGPIOIM is set), an interrupt for Port B is generated, and an external trigger signal is sent to the ADC. If theADCEvent MultiplexerSelect(ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. See page 629. If no other Port B pins are being used to generate interrupts, theInterrupt0-31SetEnable(EN0) register can disable the Port B interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts onPB4 and wait for the ADC interrupt, or the ADC interrupt must be disabled in theEN0register and the Port B interrupt handler must poll the ADC registers until the conversion is completed. See page 136 for more information.

8.2.3 ModeControl

The GPIO pins can be controlled by either software or hardware. Software control is the default for most signals and corresponds to the GPIO mode, where theGPIODATAregister is used to read or write the corresponding pins. When hardware control is enabled via theGPIOAlternateFunction Select(GPIOAFSEL) register (see page 421), the pin state is controlled by its alternate function (that is, the peripheral). Further pin muxing options are provided through theGPIOPortControl(GPIOPCTL) register which selects one of several peripheral functions for each GPIO. For information on the configuration options, refer to Table 24-5 on page 1247. Note: If any pin is to be used as an ADC input, the appropriate bit in theGPIOAMSELregister must be set to disable the analog isolation circuit.

8.2.4 CommitControl

The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for theNMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of theGPIOAlternateFunctionSelect(GPIOAFSEL) register (see page 421),GPIOPullUpSelect(GPIOPUR) register (see page 427),GPIOPull-Down Select(GPIOPDR) register (see page 429), andGPIODigitalEnable(GPIODEN) register (see 405March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

page 432) are not committed to storage unless theGPIOLock(GPIOLOCK) register (see page 434) has been unlocked and the appropriate bits of theGPIOCommit(GPIOCR) register (see page 435) have been set.

8.2.5 PadControl

The pad control registers allow software to configure the GPIO pads based on the application requirements. The pad control registers include theGPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, andGPIODENregisters. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable for each GPIO. For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package.

8.2.6 Identification

The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include theGPIOPeriphID0-GPIOPeriphID7registers as well as theGPIOPCellID0-GPIOPCellID3registers.

8.3 InitializationandConfiguration

The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. These apertures are mutually exclusive. The aperture enabled for a given GPIO port is controlled by the appropriate bit in theGPIOHBCTL register (see page 234). To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in theRCGC2register (see page 286). When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured to be undriven (tristate):GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, andGPIOPUR=0, except for the pins shown in Table 8-1 on page 398. Table 8-4 on page 406 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-5 on page 407 shows how a rising edge interrupt is configured for pin 2 of a GPIO port. Table8-4.GPIOPadConfigurationExamples GPIORegisterBitValue a Configuration SLRDR8RDR4RDR2RPDRPURDENODRDIRAFSEL XXXX??1000Digital Input (GPIO) ??????1010Digital Output (GPIO) ????XX1110Open Drain Output (GPIO) ????XX11X1Open Drain Input/Output (I2C) XXXX??10X1Digital Input (Timer CCP) March 19, 2011406 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Table8-4.GPIOPadConfigurationExamples (continued) GPIORegisterBitValue a Configuration SLRDR8RDR4RDR2RPDRPURDENODRDIRAFSEL XXXX??10X1Digital Input (QEI) ??????10X1Digital Output (PWM) ??????10X1Digital Output (Timer PWM) ??????10X1Digital Input/Output (SSI) ??????10X1Digital Input/Output (UART) XXXX000000Analog Input (Comparator) (Comparator) a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table8-5.GPIOInterruptConfigurationExample Pin2BitValue a DesiredInterrupt EventTriggerRegister 01234567 XX0XXXXX0=edge 1=level GPIOIS XX0XXXXX0=single edge 1=both edges GPIOIBE XX1XXXXX0=Low level, or falling edge 1=High level, or rising edge GPIOIEV 001000000=masked 1=not masked GPIOIM a. X=Ignored (don’t care bit)

8.4 RegisterMap

Table 8-7 on page 408 lists the GPIO registers. Each GPIO port can be accessed through one of two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to unconnected bits has no effect, and reading unconnected bits returns no meaningful data. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ GPIO Port A (APB): 0x4000.4000 ■ GPIO Port A (AHB): 0x4005.8000 ■ GPIO Port B (APB): 0x4000.5000 407March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

■ GPIO Port B (AHB): 0x4005.9000 ■ GPIO Port C (APB): 0x4000.6000 ■ GPIO Port C (AHB): 0x4005.A000 ■ GPIO Port D (APB): 0x4000.7000 ■ GPIO Port D (AHB): 0x4005.B000 ■ GPIO Port E (APB): 0x4002.4000 ■ GPIO Port E (AHB): 0x4005.C000 ■ GPIO Port F (APB): 0x4002.5000 ■ GPIO Port F (AHB): 0x4005.D000 ■ GPIO Port G (APB): 0x4002.6000 ■ GPIO Port G (AHB): 0x4005.E000 ■ GPIO Port H (APB): 0x4002.7000 ■ GPIO Port H (AHB): 0x4005.F000 ■ GPIO Port J (APB): 0x4003.D000 ■ GPIO Port J (AHB): 0x4006.0000 Note that each GPIO module clock must be enabled before the registers can be programmed (see page 286). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, andGPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table8-6.GPIOPinsWithNon-ZeroResetValues GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefaultStateGPIOPins 0x10010UART0PA[1:0] 0x10010SSI0PA[5:2] 0x10010I2C0PB[3:2] 0x31011JTAG/SWDPC[3:0] The default register type for theGPIOCRregister is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7and PC[3:0]). These five pins are the only GPIOs that are protected by theGPIOCRregister. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for theGPIOCRregister is 0x0000.00FF for all GPIO pins, with the exception of theNMI pin and the four JTAG/SWD pins (PB7and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as GPIO pins, thePC[3:0] pins default to non-committable. Similarly, to ensure that theNMI pin is not accidentally programmed as a GPIO pin, thePB7 pin defaults to non-committable. Because of this, the default reset value ofGPIOCRfor GPIO Port B is 0x0000.007F while the default reset value ofGPIOCRfor Port C is 0x0000.00F0. Table8-7.GPIORegisterMap See pageDescriptionResetTypeNameOffset 411GPIO Data0x0000.0000R/WGPIODATA0x000 412GPIO Direction0x0000.0000R/WGPIODIR0x400 March 19, 2011408 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Table8-7.GPIORegisterMap (continued) See pageDescriptionResetTypeNameOffset 413GPIO Interrupt Sense0x0000.0000R/WGPIOIS0x404 414GPIO Interrupt Both Edges0x0000.0000R/WGPIOIBE0x408 415GPIO Interrupt Event0x0000.0000R/WGPIOIEV0x40C 416GPIO Interrupt Mask0x0000.0000R/WGPIOIM0x410 417GPIO Raw Interrupt Status0x0000.0000ROGPIORIS0x414 418GPIO Masked Interrupt Status0x0000.0000ROGPIOMIS0x418 420GPIO Interrupt Clear0x0000.0000W1CGPIOICR0x41C 421GPIO Alternate Function Select-R/WGPIOAFSEL0x420 423GPIO 2-mA Drive Select0x0000.00FFR/WGPIODR2R0x500 424GPIO 4-mA Drive Select0x0000.0000R/WGPIODR4R0x504 425GPIO 8-mA Drive Select0x0000.0000R/WGPIODR8R0x508 426GPIO Open Drain Select0x0000.0000R/WGPIOODR0x50C 427GPIO Pull-Up Select-R/WGPIOPUR0x510 429GPIO Pull-Down Select0x0000.0000R/WGPIOPDR0x514 431GPIO Slew Rate Control Select0x0000.0000R/WGPIOSLR0x518 432GPIO Digital Enable-R/WGPIODEN0x51C 434GPIO Lock0x0000.0001R/WGPIOLOCK0x520 435GPIO Commit--GPIOCR0x524 437GPIO Analog Mode Select0x0000.0000R/WGPIOAMSEL0x528 439GPIO Port Control-R/WGPIOPCTL0x52C 441GPIO Peripheral Identification 40x0000.0000ROGPIOPeriphID40xFD0 442GPIO Peripheral Identification 50x0000.0000ROGPIOPeriphID50xFD4 443GPIO Peripheral Identification 60x0000.0000ROGPIOPeriphID60xFD8 444GPIO Peripheral Identification 70x0000.0000ROGPIOPeriphID70xFDC 445GPIO Peripheral Identification 00x0000.0061ROGPIOPeriphID00xFE0 446GPIO Peripheral Identification 10x0000.0000ROGPIOPeriphID10xFE4 447GPIO Peripheral Identification 20x0000.0018ROGPIOPeriphID20xFE8 448GPIO Peripheral Identification 30x0000.0001ROGPIOPeriphID30xFEC 449GPIO PrimeCell Identification 00x0000.000DROGPIOPCellID00xFF0 450GPIO PrimeCell Identification 10x0000.00F0ROGPIOPCellID10xFF4 451GPIO PrimeCell Identification 20x0000.0005ROGPIOPCellID20xFF8 452GPIO PrimeCell Identification 30x0000.00B1ROGPIOPCellID30xFFC 409March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

8.5 RegisterDescriptions

The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. March 19, 2011410 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register1:GPIOData(GPIODATA),offset0x000 The GPIODATAregister is the data register. In software control mode, values written in the GPIODATAregister are transferred onto the GPIO port pins if the respective pins have been configured as outputs through theGPIODirection(GPIODIR) register (see page 412). In order to write toGPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are set in the address mask cause the corresponding bits inGPIODATAto be read, and bits that are clear in the address mask cause the corresponding bits inGPIODATAto be read as 0, regardless of their value. A read fromGPIODATAreturns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x000 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DATAreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and written to the registers are masked by the eight address lines [9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. See “Data Register Operation” on page 404 for examples of reads and writes. 0x00R/WDATA7:0 411March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register2:GPIODirection(GPIODIR),offset0x400 The GPIODIRregister is the data direction register. Setting a bit in theGPIODIRregister configures the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x400 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DIRreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Data Direction DescriptionValue Corresponding pin is an input.0 Corresponding pins is an output.1 0x00R/WDIR7:0 March 19, 2011412 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register3:GPIOInterruptSense(GPIOIS),offset0x404 The GPIOISregister is the interrupt sense register. Setting a bit in theGPIOISregister configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x404 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ISreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Interrupt Sense DescriptionValue The edge on the corresponding pin is detected (edge-sensitive).0 The level on the corresponding pin is detected (level-sensitive).1 0x00R/WIS7:0 413March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register4:GPIOInterruptBothEdges(GPIOIBE),offset0x408 The GPIOIBEregister allows both edges to cause interrupts. When the corresponding bit in the GPIOInterruptSense(GPIOIS) register (see page 413) is set to detect edges, setting a bit in the GPIOIBEregister configures the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in theGPIOInterruptEvent(GPIOIEV) register (see page 415). Clearing a bit configures the pin to be controlled by theGPIOIEVregister. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x408 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 IBEreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Interrupt Both Edges DescriptionValue Interrupt generation is controlled by theGPIOInterruptEvent (GPIOIEV)register (see page 415). Both edges on the corresponding pin trigger an interrupt.1 0x00R/WIBE7:0 March 19, 2011414 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register5:GPIOInterruptEvent(GPIOIEV),offset0x40C The GPIOIEVregister is the interrupt event register. Setting a bit in theGPIOIEVregister configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in theGPIOInterruptSense(GPIOIS) register (see page 413). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in theGPIOIS register. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x40C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 IEVreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Interrupt Event DescriptionValue A falling edge or a Low level on the corresponding pin triggers an interrupt. A rising edge or a High level on the corresponding pin triggers an interrupt. 0x00R/WIEV7:0 415March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register6:GPIOInterruptMask(GPIOIM),offset0x410 The GPIOIMregister is the interrupt mask register. Setting a bit in theGPIOIMregister allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x410 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 IMEreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Interrupt Mask Enable DescriptionValue The interrupt from the corresponding pin is masked.0 The interrupt from the corresponding pin is sent to the interrupt controller. 0x00R/WIME7:0 March 19, 2011416 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register7:GPIORawInterruptStatus(GPIORIS),offset0x414 The GPIORISregister is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin. If the corresponding bit in theGPIOInterrupt Mask(GPIOIM) register (see page 416) is set, the interrupt is sent to the interrupt controller. Bits read as zero indicate that corresponding input pins have not initiated an interrupt. A bit in this register can be cleared by writing a 1 to the corresponding bit in theGPIOInterruptClear(GPIOICR) register. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x414 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Interrupt Raw Status DescriptionValue An interrupt condition has occurred on the corresponding pin.1 An interrupt condition has not occurred on the corresponding pin. A bit is cleared by writing a 1 to the corresponding bit in theGPIOICR register. 0x00RORIS7:0 417March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register8:GPIOMaskedInterruptStatus(GPIOMIS),offset0x418 The GPIOMISregister is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality,PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit ofGPIOIM is set), an interrupt for Port B is generated, and an external trigger signal is sent to the ADC. If theADCEvent MultiplexerSelect(ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. See page 629. If no other Port B pins are being used to generate interrupts, theInterrupt0-31SetEnable(EN0) register can disable the Port B interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts onPB4 and wait for the ADC interrupt, or the ADC interrupt must be disabled in theEN0register and the Port B interrupt handler must poll the ADC registers until the conversion is completed. See page 136 for more information. GPIOMISis the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x418 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 MISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 March 19, 2011418 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

DescriptionResetTypeNameBit/Field GPIO Masked Interrupt Status DescriptionValue An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. An interrupt condition on the corresponding pin is masked or has not occurred. A bit is cleared by writing a 1 to the corresponding bit in theGPIOICR register. 0x00ROMIS7:0 419March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register9:GPIOInterruptClear(GPIOICR),offset0x41C The GPIOICRregister is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt bit in theGPIORISand GPIOMISregisters. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x41C Type W1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ICreserved W1CW1CW1CW1CW1CW1CW1CW1CROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Interrupt Clear DescriptionValue The corresponding interrupt is cleared.1 The corresponding interrupt is unaffected.0 0x00W1CIC7:0 March 19, 2011420 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register10:GPIOAlternateFunctionSelect(GPIOAFSEL),offset0x420 The GPIOAFSELregister is the mode control select register. If a bit is clear, the pin is used as a GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral functions are multiplexed on each GPIO. TheGPIOPortControl(GPIOPCTL) register is used to select one of the possible functions. Table 24-5 on page 1247 details which functions are muxed on each GPIO pin. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in the table below. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, andGPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table8-8.GPIOPinsWithNon-ZeroResetValues GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefaultStateGPIOPins 0x10010UART0PA[1:0] 0x10010SSI0PA[5:2] 0x10010I2C0PB[3:2] 0x31011JTAG/SWDPC[3:0] Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller . If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger . The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for theNMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of theGPIOAlternateFunctionSelect(GPIOAFSEL) register (see page 421),GPIOPullUpSelect(GPIOPUR) register (see page 427),GPIOPull-Down Select(GPIOPDR) register (see page 429), andGPIODigitalEnable(GPIODEN) register (see page 432) are not committed to storage unless theGPIOLock(GPIOLOCK) register (see page 434) has been unlocked and the appropriate bits of theGPIOCommit(GPIOCR) register (see page 435) have been set. When using the I2C module, in addition to setting theGPIOAFSELregister bits for the I2C clock and data pins, the data pins should be set to open drain using theGPIOOpenDrainSelect (GPIOODR)register (see examples in “Initialization and Configuration” on page 406). 421March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x420 Type R/W, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 AFSELreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Alternate Function Select DescriptionValue The associated pin functions as a GPIO and is controlled by the GPIO registers. The associated pin functions as a peripheral signal and is controlled by the alternate hardware function. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 8-1 on page 398. -R/WAFSEL7:0 March 19, 2011422 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register11:GPIO2-mADriveSelect(GPIODR2R),offset0x500 The GPIODR2Rregister is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting theDRV2 bit for a GPIO signal, the correspondingDRV4 bit in theGPIODR4Rregister andDRV8 bit in theGPIODR8Rregister are automatically cleared by hardware. By default, all GPIO pins have 2-mA drive. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x500 Type R/W, reset 0x0000.00FF 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DRV2reserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 1111111100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Output Pad 2-mA Drive Enable DescriptionValue The corresponding GPIO pin has 2-mA drive.1 The drive for the corresponding GPIO pin is controlled by the GPIODR4Ror GPIODR8Rregister. Setting a bit in either theGPIODR4register or theGPIODR8register clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 0xFFR/WDRV27:0 423March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register12:GPIO4-mADriveSelect(GPIODR4R),offset0x504 The GPIODR4Rregister is the 4-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting theDRV4 bit for a GPIO signal, the correspondingDRV2 bit in theGPIODR2Rregister andDRV8 bit in theGPIODR8Rregister are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x504 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DRV4reserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Output Pad 4-mA Drive Enable DescriptionValue The corresponding GPIO pin has 4-mA drive.1 The drive for the corresponding GPIO pin is controlled by the GPIODR2Ror GPIODR8Rregister. Setting a bit in either theGPIODR2register or theGPIODR8register clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 0x00R/WDRV47:0 March 19, 2011424 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register13:GPIO8-mADriveSelect(GPIODR8R),offset0x508 The GPIODR8Rregister is the 8-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting theDRV8 bit for a GPIO signal, the correspondingDRV2 bit in theGPIODR2Rregister andDRV4 bit in theGPIODR4Rregister are automatically cleared by hardware. The 8-mA setting is also used for high-current operation. Note: There is no configuration difference between 8-mA and high-current operation. The additional current capacity results from a shift in the VOH/VOL levels. See “Recommended DC Operating Conditions” on page 1294 for further information. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x508 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DRV8reserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Output Pad 8-mA Drive Enable DescriptionValue The corresponding GPIO pin has 8-mA drive.1 The drive for the corresponding GPIO pin is controlled by the GPIODR2Ror GPIODR4Rregister. Setting a bit in either theGPIODR2register or theGPIODR4register clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 0x00R/WDRV87:0 425March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register14:GPIOOpenDrainSelect(GPIOODR),offset0x50C The GPIOODRregister is the open drain control register. Setting a bit in this register enables the open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the corresponding bit should also be set in theGPIODigitalEnable(GPIODEN) register (see page 432). Corresponding bits in the drive strength and slew rate control registers (GPIODR2R, GPIODR4R, GPIODR8R, andGPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain input if the corresponding bit in theGPIODIRregister is cleared. If open drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module, in addition to configuring the pin to open drain, theGPIOAlternate FunctionSelect(GPIOAFSEL) register bits for the I2C clock and data pins should be set (see examples in “Initialization and Configuration” on page 406). GPIO Open Drain Select (GPIOODR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x50C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ODEreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Output Pad Open Drain Enable DescriptionValue The corresponding pin is configured as open drain.1 The corresponding pin is not configured as open drain.0 0x00R/WODE7:0 March 19, 2011426 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register15:GPIOPull-UpSelect(GPIOPUR),offset0x510 The GPIOPURregister is the pull-up control register. When a bit is set, a weak pull-up resistor on the corresponding GPIO signal is enabled. Setting a bit inGPIOPURautomatically clears the corresponding bit in theGPIOPull-DownSelect(GPIOPDR) register (see page 429). Write access to this register is protected with theGPIOCRregister. Bits inGPIOCRthat are cleared prevent writes to the equivalent bit in this register. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, andGPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table8-9.GPIOPinsWithNon-ZeroResetValues GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefaultStateGPIOPins 0x10010UART0PA[1:0] 0x10010SSI0PA[5:2] 0x10010I2C0PB[3:2] 0x31011JTAG/SWDPC[3:0] Note: The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for theNMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of theGPIOAlternate FunctionSelect(GPIOAFSEL) register (see page 421),GPIOPullUpSelect(GPIOPUR) register (see page 427),GPIOPull-DownSelect(GPIOPDR) register (see page 429), and GPIODigitalEnable(GPIODEN) register (see page 432) are not committed to storage unless theGPIOLock(GPIOLOCK) register (see page 434) has been unlocked and the appropriate bits of theGPIOCommit(GPIOCR) register (see page 435) have been set. GPIO Pull-Up Select (GPIOPUR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x510 Type R/W, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PUEreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 427March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Pad Weak Pull-Up Enable DescriptionValue The corresponding pin has a weak pull-up resistor.1 The corresponding pin is not affected.0 Setting a bit in theGPIOPDRregister clears the corresponding bit in the GPIOPURregister. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 8-1 on page 398. -R/WPUE7:0 March 19, 2011428 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register16:GPIOPull-DownSelect(GPIOPDR),offset0x514 The GPIOPDRregister is the pull-down control register. When a bit is set, a weak pull-down resistor on the corresponding GPIO signal is enabled. Setting a bit inGPIOPDRautomatically clears the corresponding bit in theGPIOPull-UpSelect(GPIOPUR) register (see page 427). Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, andGPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table8-10.GPIOPinsWithNon-ZeroResetValues GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefaultStateGPIOPins 0x10010UART0PA[1:0] 0x10010SSI0PA[5:2] 0x10010I2C0PB[3:2] 0x31011JTAG/SWDPC[3:0] Note: The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for theNMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of theGPIOAlternate FunctionSelect(GPIOAFSEL) register (see page 421),GPIOPullUpSelect(GPIOPUR) register (see page 427),GPIOPull-DownSelect(GPIOPDR) register (see page 429), and GPIODigitalEnable(GPIODEN) register (see page 432) are not committed to storage unless theGPIOLock(GPIOLOCK) register (see page 434) has been unlocked and the appropriate bits of theGPIOCommit(GPIOCR) register (see page 435) have been set. GPIO Pull-Down Select (GPIOPDR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x514 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PDEreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset 429March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Pad Weak Pull-Down Enable DescriptionValue The corresponding pin has a weak pull-down resistor.1 The corresponding pin is not affected.0 Setting a bit in theGPIOPURregister clears the corresponding bit in the GPIOPDRregister. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 0x00R/WPDE7:0 March 19, 2011430 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register17:GPIOSlewRateControlSelect(GPIOSLR),offset0x518 The GPIOSLRregister is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via theGPIO8-mADriveSelect(GPIODR8R) register (see page 425). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x518 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SRLreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Slew Rate Limit Enable (8-mA drive only) DescriptionValue Slew rate control is enabled for the corresponding pin.1 Slew rate control is disabled for the corresponding pin.0 0x00R/WSRL7:0 431March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register18:GPIODigitalEnable(GPIODEN),offset0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODENregister is the digital enable register. By default, all GPIO signals except those listed below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin as a digital input or output (either GPIO or alternate function), the correspondingGPIODEN bit must be set. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, andGPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table8-11.GPIOPinsWithNon-ZeroResetValues GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefaultStateGPIOPins 0x10010UART0PA[1:0] 0x10010SSI0PA[5:2] 0x10010I2C0PB[3:2] 0x31011JTAG/SWDPC[3:0] Note: The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for theNMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of theGPIOAlternate FunctionSelect(GPIOAFSEL) register (see page 421),GPIOPullUpSelect(GPIOPUR) register (see page 427),GPIOPull-DownSelect(GPIOPDR) register (see page 429), and GPIODigitalEnable(GPIODEN) register (see page 432) are not committed to storage unless theGPIOLock(GPIOLOCK) register (see page 434) has been unlocked and the appropriate bits of theGPIOCommit(GPIOCR) register (see page 435) have been set. March 19, 2011432 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

GPIO Digital Enable (GPIODEN) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x51C Type R/W, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DENreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Digital Enable DescriptionValue The digital functions for the corresponding pin are disabled.0 The digital functions for the corresponding pin are enabled. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 8-1 on page 398. -R/WDEN7:0 433March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register19:GPIOLock(GPIOLOCK),offset0x520 The GPIOLOCKregister enables write access to theGPIOCRregister (see page 435). Writing 0x4C4F.434B to theGPIOLOCKregister unlocks theGPIOCRregister. Writing any other value to the GPIOLOCKregister re-enables the locked state. Reading theGPIOLOCKregister returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading theGPIOLOCKregister returns 0x0000.0001. When write accesses are enabled, or unlocked, reading theGPIOLOCKregister returns 0x0000.0000. GPIO Lock (GPIOLOCK) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x520 Type R/W, reset 0x0000.0001 16171819202122232425262728293031 LOCK R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 LOCK R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1000000000000000Reset DescriptionResetTypeNameBit/Field GPIO Lock A write of the value 0x4C4F.434B unlocks theGPIOCommit(GPIOCR) register for write access.A write of any other value or a write to the GPIOCRregister reapplies the lock, preventing any register updates. A read of this register returns the following values: DescriptionValue The GPIOCRregister is locked and may not be modified.0x1 The GPIOCRregister is unlocked and may be modified.0x0 0x0000.0001R/WLOCK31:0 March 19, 2011434 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register20:GPIOCommit(GPIOCR),offset0x524 The GPIOCRregister is the commit register. The value of theGPIOCRregister determines which bits of theGPIOAFSEL, GPIOPUR, GPIOPDR, andGPIODENregisters are committed when a write to these registers is performed. If a bit in theGPIOCRregister is cleared, the data being written to the corresponding bit in theGPIOAFSEL, GPIOPUR, GPIOPDR, orGPIODENregisters cannot be committed and retains its previous value. If a bit in theGPIOCRregister is set, the data being written to the corresponding bit of theGPIOAFSEL, GPIOPUR, GPIOPDR, orGPIODENregisters is committed to the register and reflects the new value. The contents of theGPIOCRregister can only be modified if the status in theGPIOLOCKregister is unlocked. Writes to theGPIOCRregister are ignored if the status in theGPIOLOCKregister is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the GPIOCRregister to 0 forPB7 and PC[3:0], the NMI and JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to theGPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the NMI and JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in theGPIOCRregisters cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to theGPIOAFSEL, GPIOPUR, GPIOPDR, orGPIODENregister bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x524 Type -, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CRreserved 435March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Commit DescriptionValue The correspondingGPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODENbits can be written. The correspondingGPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODENbits cannot be written. Note: The default register type for theGPIOCRregister is RO for all GPIO pins with the exception of theNMI pin and the four JTAG/SWD pins (PB7and PC[3:0]). These five pins are the only GPIOs that are protected by theGPIOCRregister. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for theGPIOCRregister is 0x0000.00FF for all GPIO pins, with the exception of theNMI pin and the four JTAG/SWD pins (PB7and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as GPIO pins, thePC[3:0] pins default to non-committable. Similarly, to ensure that theNMI pin is not accidentally programmed as a GPIO pin, thePB7 pin defaults to non-committable. Because of this, the default reset value of GPIOCRfor GPIO Port B is 0x0000.007F while the default reset value ofGPIOCRfor Port C is 0x0000.00F0. --CR7:0 March 19, 2011436 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register21:GPIOAnalogModeSelect(GPIOAMSEL),offset0x528 Important: This register is only valid for ports D and E; the corresponding base addresses for the remaining ports are not valid. If any pin is to be used as an ADC input, the appropriate bit inGPIOAMSELmust be set to disable the analog isolation circuit. The GPIOAMSELregister controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 5-V source and affect analog operation, analog circuitry requires isolation from the pins when they are not used in their analog function. Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. For information on which GPIO pins can be used for ADC functions, refer to Table 24-5 on page 1247. GPIO Analog Mode Select (GPIOAMSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x528 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 GPIOAMSELreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 437March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field GPIO Analog Mode Select DescriptionValue The analog function of the pin is enabled, the isolation is disabled, and the pin is capable of analog functions. The analog function of the pin is disabled, the isolation is enabled, and the pin is capable of digital functions as specified by the other GPIO configuration registers. Note: This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. The reset state of this register is 0 for all signals. 0x00R/WGPIOAMSEL7:0 March 19, 2011438 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register22:GPIOPortControl(GPIOPCTL),offset0x52C The GPIOPCTLregister is used in conjunction with theGPIOAFSELregister and selects the specific peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSELregister are cleared on reset, therefore most GPIO pins are configured as GPIOs by default. When a bit is set in theGPIOAFSELregister, the corresponding GPIO signal is controlled by an associated peripheral. TheGPIOPCTLregister selects one out of a set of peripheral functions for each GPIO, providing additional flexibility in signal definition. For information on the defined encodings for the bit fields in this register, refer to Table 24-5 on page 1247. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in the table below. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, andGPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table8-12.GPIOPinsWithNon-ZeroResetValues GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefaultStateGPIOPins 0x10010UART0PA[1:0] 0x10010SSI0PA[5:2] 0x10010I2C0PB[3:2] 0x31011JTAG/SWDPC[3:0] GPIO Port Control (GPIOPCTL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x52C Type R/W, reset - 16171819202122232425262728293031 PMC4PMC5PMC6PMC7 R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0123456789101112131415 PMC0PMC1PMC2PMC3 R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType DescriptionResetTypeNameBit/Field Port Mux Control 7 This field controls the configuration for GPIO pin 7. -R/WPMC731:28 439March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Port Mux Control 6 This field controls the configuration for GPIO pin 6. -R/WPMC627:24 Port Mux Control 5 This field controls the configuration for GPIO pin 5. -R/WPMC523:20 Port Mux Control 4 This field controls the configuration for GPIO pin 4. -R/WPMC419:16 Port Mux Control 3 This field controls the configuration for GPIO pin 3. -R/WPMC315:12 Port Mux Control 2 This field controls the configuration for GPIO pin 2. -R/WPMC211:8 Port Mux Control 1 This field controls the configuration for GPIO pin 1. -R/WPMC17:4 Port Mux Control 0 This field controls the configuration for GPIO pin 0. -R/WPMC03:0 March 19, 2011440 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register23:GPIOPeripheralIdentification4(GPIOPeriphID4),offset0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, andGPIOPeriphID7registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID4reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [7:0]0x00ROPID47:0 441March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register24:GPIOPeripheralIdentification5(GPIOPeriphID5),offset0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, andGPIOPeriphID7registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID5reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [15:8]0x00ROPID57:0 March 19, 2011442 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register25:GPIOPeripheralIdentification6(GPIOPeriphID6),offset0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, andGPIOPeriphID7registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID6reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [23:16]0x00ROPID67:0 443March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register26:GPIOPeripheralIdentification7(GPIOPeriphID7),offset0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, andGPIOPeriphID7registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFDC Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID7reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [31:24]0x00ROPID77:0 March 19, 2011444 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register27:GPIOPeripheralIdentification0(GPIOPeriphID0),offset0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, andGPIOPeriphID3registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE0 Type RO, reset 0x0000.0061 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID0reserved ROROROROROROROROROROROROROROROROType 1000011000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 0x61ROPID07:0 445March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register28:GPIOPeripheralIdentification1(GPIOPeriphID1),offset0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, andGPIOPeriphID3registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE4 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 0x00ROPID17:0 March 19, 2011446 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register29:GPIOPeripheralIdentification2(GPIOPeriphID2),offset0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, andGPIOPeriphID3registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID2reserved ROROROROROROROROROROROROROROROROType 0001100000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 0x18ROPID27:0 447March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register30:GPIOPeripheralIdentification3(GPIOPeriphID3),offset0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, andGPIOPeriphID3registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFEC Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PID3reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 0x01ROPID37:0 March 19, 2011448 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register31:GPIOPrimeCellIdentification0(GPIOPCellID0),offset0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, andGPIOPCellID3registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID0reserved ROROROROROROROROROROROROROROROROType 1011000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 0x0DROCID07:0 449March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register32:GPIOPrimeCellIdentification1(GPIOPCellID1),offset0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, andGPIOPCellID3registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID1reserved ROROROROROROROROROROROROROROROROType 0000111100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 0xF0ROCID17:0 March 19, 2011450 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

Register33:GPIOPrimeCellIdentification2(GPIOPCellID2),offset0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, andGPIOPCellID3registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID2reserved ROROROROROROROROROROROROROROROROType 1010000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 0x05ROCID27:0 451March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register34:GPIOPrimeCellIdentification3(GPIOPCellID3),offset0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, andGPIOPCellID3registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CID3reserved ROROROROROROROROROROROROROROROROType 1000110100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPIO PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 0xB1ROCID37:0 March 19, 2011452 Texas Instruments-Advance Information General-Purpose Input/Outputs (GPIOs)

9 ExternalPeripheralInterface(EPI)

The External Peripheral Interface is a high-speed parallel bus for external peripherals or memory. It has several modes of operation to interface gluelessly to many types of external devices. The External Peripheral Interface is similar to a standard microprocessor address/data bus, except that it must typically be connected to just one type of external device. Enhanced capabilities include µDMA support, clocking control and support for external FIFO buffers. The EPI has the following features: ■ 8/16/32-bit dedicated parallel bus for external peripherals and memory ■ Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from SDRAM, SRAM and Flash memory ■ Blocking and non-blocking reads ■ Separates processor from timing details through use of an internal write FIFO ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for read and write – Read channel request asserted by programmable levels on the internal non-blocking read FIFO (NBRFIFO) – Write channel request asserted by empty on the internal write FIFO (WFIFO) The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory (SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a communication mechanism and is speed-controlled using clocking. ■ Synchronous Dynamic Random Access Memory (SDRAM) mode – Supports x16 (single data rate) SDRAM at up to 50 MHz – Supports low-cost SDRAMs up to 64 MB (512 megabits) – Includes automatic refresh and access to all banks/rows – Includes a Sleep/Standby mode to keep contents active with minimal power draw – Multiplexed address/data interface for reduced pin count ■ Host-Bus mode – Traditional x8 and x16 MCU bus interface capabilities – Similar device compatibility options as PIC, ATmega, 8051, and others – Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with no byte selects) 453March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

– Support of both muxed and de-muxed address and data – Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant, with support for external FIFO (XFIFO) EMPTY and FULL signals – Speed controlled, with read and write data wait-state counters – Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn – Manual chip-enable (or use extra address pins) ■ General-Purpose mode – Wide parallel interfaces for fast communications with CPLDs and FPGAs – Data widths up to 32 bits – Data rates up to 150 MB/second – Optional "address" sizes from 4 bits to 20 bits – Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input ■ General parallel GPIO – 1 to 32 bits, FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls

9.1 EPIBlockDiagram

Figure 9-1 on page 455 provides a block diagram of a Stellaris® EPI module. March 19, 2011454 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Figure9-1.EPIBlockDiagram Baud Rate Control ( Clock) AHB Bus Interface With DMA Wide Parallel Interface Host Bus SDRAM General Parallel GPIO AHB EPI 31:0 NBRFIFO 8 x 32 bits WFIFO 4 x 32 bits

9.2 SignalDescription

Table 9-1 on page 455 and Table 9-2 on page 456 list the external signals of the EPI controller and describe the function of each. The EPI controller signals are alternate functions for GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the EPI signals. TheAFSEL bit in theGPIOAlternateFunction Select(GPIOAFSEL) register (page 421) should be set to choose the EPI controller function. The number in parentheses is the encoding that must be programmed into thePMCn field in theGPIO PortControl(GPIOPCTL) register (page 439) to assign the EPI signals to the specified GPIO port pins. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 397. Table9-1.SignalsforExternalPeripheralInterface(100LQFP) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName EPI module 0 signal 0.TTLI/OPH3 (8)83EPI0S0 EPI module 0 signal 1.TTLI/OPH2 (8)84EPI0S1 EPI module 0 signal 2.TTLI/OPC4 (8)25EPI0S2 EPI module 0 signal 3.TTLI/OPC5 (8)24EPI0S3 EPI module 0 signal 4.TTLI/OPC6 (8)23EPI0S4 EPI module 0 signal 5.TTLI/OPC7 (8)22EPI0S5 EPI module 0 signal 6.TTLI/OPH0 (8)86EPI0S6 EPI module 0 signal 7.TTLI/OPH1 (8)85EPI0S7 EPI module 0 signal 8.TTLI/OPE0 (8)74EPI0S8 EPI module 0 signal 9.TTLI/OPE1 (8)75EPI0S9 455March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table9-1.SignalsforExternalPeripheralInterface(100LQFP) (continued) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName EPI module 0 signal 10.TTLI/OPH4 (8)76EPI0S10 EPI module 0 signal 11.TTLI/OPH5 (8)63EPI0S11 EPI module 0 signal 12.TTLI/OPF4 (8)42EPI0S12 EPI module 0 signal 13.TTLI/OPG0 (8)19EPI0S13 EPI module 0 signal 14.TTLI/OPG1 (8)18EPI0S14 EPI module 0 signal 15.TTLI/OPF5 (8)41EPI0S15 EPI module 0 signal 16.TTLI/OPJ0 (8)14EPI0S16 EPI module 0 signal 17.TTLI/OPJ1 (8)87EPI0S17 EPI module 0 signal 18.TTLI/OPJ2 (8)39EPI0S18 EPI module 0 signal 19.TTLI/OPJ3 (8) PD4 (10) EPI0S19 EPI module 0 signal 20.TTLI/OPD2 (8)12EPI0S20 EPI module 0 signal 21.TTLI/OPD3 (8)13EPI0S21 EPI module 0 signal 22.TTLI/OPB5 (8)91EPI0S22 EPI module 0 signal 23.TTLI/OPB4 (8)92EPI0S23 EPI module 0 signal 24.TTLI/OPE2 (8)95EPI0S24 EPI module 0 signal 25.TTLI/OPE3 (8)96EPI0S25 EPI module 0 signal 26.TTLI/OPH6 (8)62EPI0S26 EPI module 0 signal 27.TTLI/OPH7 (8)15EPI0S27 EPI module 0 signal 28.TTLI/OPJ4 (8) PD5 (10) EPI0S28 EPI module 0 signal 29.TTLI/OPJ5 (8) PD6 (10) EPI0S29 EPI module 0 signal 30.TTLI/OPJ6 (8) PD7 (10) 100 EPI0S30 EPI module 0 signal 31.TTLI/OPG7 (9)36EPI0S31 a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table9-2.SignalsforExternalPeripheralInterface(108BGA) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName EPI module 0 signal 0.TTLI/OPH3 (8)D10EPI0S0 EPI module 0 signal 1.TTLI/OPH2 (8)D11EPI0S1 EPI module 0 signal 2.TTLI/OPC4 (8)L1EPI0S2 EPI module 0 signal 3.TTLI/OPC5 (8)M1EPI0S3 EPI module 0 signal 4.TTLI/OPC6 (8)M2EPI0S4 EPI module 0 signal 5.TTLI/OPC7 (8)L2EPI0S5 EPI module 0 signal 6.TTLI/OPH0 (8)C9EPI0S6 EPI module 0 signal 7.TTLI/OPH1 (8)C8EPI0S7 EPI module 0 signal 8.TTLI/OPE0 (8)B11EPI0S8 EPI module 0 signal 9.TTLI/OPE1 (8)A12EPI0S9 EPI module 0 signal 10.TTLI/OPH4 (8)B10EPI0S10 March 19, 2011456 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Table9-2.SignalsforExternalPeripheralInterface(108BGA) (continued) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName EPI module 0 signal 11.TTLI/OPH5 (8)F10EPI0S11 EPI module 0 signal 12.TTLI/OPF4 (8)K4EPI0S12 EPI module 0 signal 13.TTLI/OPG0 (8)K1EPI0S13 EPI module 0 signal 14.TTLI/OPG1 (8)K2EPI0S14 EPI module 0 signal 15.TTLI/OPF5 (8)K3EPI0S15 EPI module 0 signal 16.TTLI/OPJ0 (8)F3EPI0S16 EPI module 0 signal 17.TTLI/OPJ1 (8)B6EPI0S17 EPI module 0 signal 18.TTLI/OPJ2 (8)K6EPI0S18 EPI module 0 signal 19.TTLI/OPJ3 (8) PD4 (10) M10 EPI0S19 EPI module 0 signal 20.TTLI/OPD2 (8)H2EPI0S20 EPI module 0 signal 21.TTLI/OPD3 (8)H1EPI0S21 EPI module 0 signal 22.TTLI/OPB5 (8)B7EPI0S22 EPI module 0 signal 23.TTLI/OPB4 (8)A6EPI0S23 EPI module 0 signal 24.TTLI/OPE2 (8)A4EPI0S24 EPI module 0 signal 25.TTLI/OPE3 (8)B4EPI0S25 EPI module 0 signal 26.TTLI/OPH6 (8)G3EPI0S26 EPI module 0 signal 27.TTLI/OPH7 (8)H3EPI0S27 EPI module 0 signal 28.TTLI/OPJ4 (8) PD5 (10) K11 EPI0S28 EPI module 0 signal 29.TTLI/OPJ5 (8) PD6 (10) K12 EPI0S29 EPI module 0 signal 30.TTLI/OPJ6 (8) PD7 (10) L10 EPI0S30 EPI module 0 signal 31.TTLI/OPG7 (9)C10EPI0S31 a. The TTL designation indicates the pin has TTL-compatible voltage levels.

9.3 FunctionalDescription

The EPI controller provides a glueless, programmable interface to a variety of common external peripherals such as SDRAM, Host Bus x8 and x16 devices, RAM, NOR Flash memory, CPLDs and FPGAs. In addition, the EPI controller provides custom GPIO that can use a FIFO with speed control by using either the internal write FIFO (WFIFO) or the non-blocking read FIFO (NBRFIFO). The WFIFO can hold 4 words of data that are written to the external interface at the rate controlled by the EPIMainBaudRate(EPIBAUD) register. The NBRFIFO can hold 8 words of data and samples at the rate controlled by theEPIBAUDregister. The EPI controller provides predictable operation and thus has an advantage over regular GPIO which has more variable timing due to on-chip bus arbitration and delays across bus bridges. Blocking reads stall the CPU until the transaction completes. Non-blocking reads are performed in the background and allow the processor to continue operation. In addition, write data can also be stored in the WFIFO to allow multiple writes with no stalls. Main read and write operations can be performed in subsets of the range 0x6000.0000 to 0xDFFF.FFFF. A read from an address mapped location uses the offset and size to control the address and size of the external operation. When performing a multi-value load, the read is done as a burst (when available) to maximize performance. A write to an address mapped location uses 457March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

the offset and size to control the address and size of the external operation. When performing a multi-value store, the write is done as a burst (when available) to maximize performance. NAND Flash memory (x8) can be read natively. Automatic programming support is not provided; programming must be done by the user following the manufacturer's protocol. Automatic page ECC is also not supported, but can be performed in software.

9.3.1 Non-BlockingReads

The EPI Controller supports a special kind of read called a non-blocking read, also referred to as a posted read. Where a normal read stalls the processor or μDMA until the data is returned, a non-blocking read is performed in the background. A non-blocking read is configured by writing the start address into aEPIRADDRnregister, the size per transaction into aEPIRSIZEnregister, and then the count of operations into aEPIRPSTDn register. After each read is completed, the result is written into the NBRFIFO and theEPIRADDRn register is incremented by the size (1, 2, or 4). If the NBRFIFO is filled, then the reads pause until space is made available. The NBRFIFO can be configured to interrupt the processor or trigger the μDMA based on fullness using theEPIFIFOLVL register. By using the trigger/interrupt method, the μDMA (or processor) can keep space available in the NBRFIFO and allow the reads to continue unimpeded. When performing non-blocking reads, the SDRAM controller issues two additional read transactions after the burst request is terminated. The data for these additional transfers is discarded. This situation is transparent to the user other than the additional EPI bus activity and can safely be ignored. Two non-blocking read register sets are available to allow sequencing and ping-pong use. When one completes, the other then activates. So, for example, if 20 words are to be read from 0x100 and 10 words from 0x200, theEPIRPSTD0register can be set up with the read from 0x100 (with a count of 20), and theEPIRPSTD1register can be set up with the read from 0x200 (with a count of 10). WhenEPIRPSTD0finishes (count goes to 0), theEPIRPSTD1register then starts its operation. The NBRFIFO has then passed 30 values. When used with the μDMA, it may transfer 30 values (simple sequence), or the primary/alternate model may be used to handle the first 20 in one way and the second 10 in another. It is also possible to reload theEPIRPSTD0register when it is finished (and theEPIRPSTD1register is active); thereby, keeping the interface constantly busy. To cancel a non-blocking read, theEPIRPSTDnregister is cleared. Care must be taken, however if the register set was active to drain away any values read into the NBRFIFO and ensure that any read in progress is allowed to complete. To ensure that the cancel is complete, the following algorithm is used (using theEPIRPSTD0register for example): EPIRPSTD0= 0; while ((EPISTAT& 0x11) == 0x10) ; // we are active and busy // if here, then other one is active or interface no longer busy cnt = (EPIRADDR0– original_address) /EPIRSIZE0; // count of values read cnt -= values_read_so_far; // cnt is now number left in FIFO while (cnt--) March 19, 2011458 Texas Instruments-Advance Information External Peripheral Interface (EPI)

value =EPIREADFIFO; // drain The above algorithm can be optimized in code; however, the important point is to wait for the cancel to complete because the external interface could have been in the process of reading a value when the cancel came in, and it must be allowed to complete.

9.3.2 DMAOperation

The µDMA can be used to achieve maximum transfer rates on the EPI through the NBRFIFO and the WFIFO. The µDMA has one channel for write and one for read. The write channel copies values to the WFIFO when the WFIFO is at the level specified by theEPIFIFOLevelSelects(EPIFIFOLVL) register. The non-blocking read channel copies values from the NBRFIFO when the NBRFIFO is at the level specified by theEPIFIFOLVLregister. For non-blocking reads, the start address, the size per transaction, and the count of elements must be programmed in the µDMA. Note that both non-blocking read register sets can be used, and they fill the NBRFIFO such that one runs to completion, then the next one starts (they do not interleave). Using the NBRFIFO provides the best possible transfer rate. For blocking reads, the µDMA software channel (or another unused channel) is used for memory-to-memory transfers (or memory to peripheral, where some other peripheral is used). In this situation, the µDMA stalls until the read is complete and is not able to service another channel until the read is done. As a result, the arbitration size should normally be programmed to one access at a time. The µDMA controller can also transfer from and to the NBRFIFO and the WFIFO using the µDMA software channel in memory mode, however, the µDMA is stalled once the NBRFIFO is empty or the WFIFO is full. Note that when the µDMA controller is stalled, the core continues operation. See “Micro Direct Memory Access (μDMA)” on page 339 for more information on configuring the µDMA. The size of the FIFOs must be taken into consideration when configuring the µDMA to transfer data to and from the EPI. The arbitration size should be 4 or less when writing to EPI address space and 8 or less when reading from EPI address space.

9.4 InitializationandConfiguration

To enable and initialize the EPI controller, the following steps are necessary: 1. Enable the EPI module using theRCGC1register. See page 277. 2. Enable the clock to the appropriate GPIO module via theRCGC2register. See page 286. To find out which GPIO port to enable, refer to Table 9-1 on page 455 or Table 9-2 on page 456. 3. Set the GPIOAFSEL bits for the appropriate pins. See page 421. To determine which GPIOs to configure, see Table 24-4 on page 1238. 4. Configure the GPIO current level and/or slew rate as specified for the mode selected. See page 423 and page 431. 5. Configure thePMCn fields in theGPIOPCTLregister to assign the EPI signals to the appropriate pins. See page 439 and Table 24-5 on page 1247. 6. Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the MODE field in theEPIConfiguration(EPICFG) register. Set the mode-specific details (if needed) using the appropriate mode configurationEPIxxxConfiguration(EPIxxxCFG) and EPIxxx Configuration2(EPIxxxCFG2) registers. Set theEPIMainBaudRate(EPIBAUD) register if the baud rate must be slower than the system clock rate. 459March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

1. Configure the address mapping using theEPIAddressMap(EPIADDRMAP) register. The selected start address and range is dependent on the type of external device and maximum address (as appropriate). For example, for a 512-megabit SDRAM, program theERADR field to 0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program theERSZ field to 0x3 for 256 MB. If using General-Purpose mode and no address at all, program theEPADR field to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program theEPSZ field to 0x0 for 256 bytes. 8. To read or write directly, use the mapped address area (configured with theEPIADDRMAP register). Up to 4 or 5 writes can be performed at once without blocking. Each read is blocked until the value is retrieved. 9. To perform a non-blocking read, see “Non-Blocking Reads” on page 458. The following sub-sections describe the initialization and configuration for each of the modes of operation. Care must be taken to initialize everything properly to ensure correct operation. Control of the GPIO states is also important, as changes may cause the external device to interpret pin states as actions or commands (see “Register Descriptions” on page 410). Normally, a pull-up or pull-down is needed on the board to at least control the chip-select or chip-enable as the Stellaris GPIOs come out of reset in tri-state.

9.4.1 SDRAMMode

When activating the SDRAM mode, it is important to consider a few points: 1. Generally, it takes over 100 μs from when the mode is activated to when the first operation is allowed. The SDRAM controller begins the SDRAM initialization sequence as soon as the mode is selected and enabled via theEPICFGregister. It is important that the GPIOs are properly configured before the SDRAM mode is enabled, as the EPI controller is relying on the GPIO block's ability to drive the pins immediately. As part of the initialization sequence, the LOAD MODE REGISTER command is automatically sent to the SDRAM with a value of 0x27, which sets a CAS latency of 2 and a full page burst length. 2. The INITSEQ bit in theEPIStatus(EPISTAT) register can be checked to determine when the initialization sequence is complete. 3. When using a frequency range and/or refresh value other than the default value, it is important to configure theFREQ and RFSH fields in theEPISDRAMConfiguration(EPISDRAMCFG) register shortly after activating the mode. After the 100-μs startup time, the EPI block must be configured properly to keep the SDRAM contents stable. 4. The SLEEP bit in theEPISDRAMCFGregister may be configured to put the SDRAM into a low-power self-refreshing state. It is important to note that the SDRAM mode must not be disabled once enabled, or else the SDRAM is no longer clocked and the contents are lost. The SIZE field of theEPISDRAMCFGregister must be configured correctly based on the amount of SDRAM in the system. The FREQ field must be configured according to the value that represents the range being used. Based on the range selected, the number of external clocks used between certain operations (for example, PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used, then the only downside is that the peripheral is slower (uses more cycles for these delays). If a lower frequency is given, incorrect operation occurs. See “External Peripheral Interface (EPI)” on page 1308 for timing details for the SDRAM mode. March 19, 2011460 Texas Instruments-Advance Information External Peripheral Interface (EPI)

9.4.1.1 ExternalSignalConnections

Table 9-3 on page 461 defines how EPI module signals should be connected to SDRAMs. The table applies when using a x16 SDRAM up to 512 megabits. Note that the EPI signals must use 8-mA drive when interfacing to SDRAM, see page 425. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table9-3.EPISDRAMSignalConnections SDRAMSignalaEPISignal D0A0EPI0S0 D1A1EPI0S1 D2A2EPI0S2 D3A3EPI0S3 D4A4EPI0S4 D5A5EPI0S5 D6A6EPI0S6 D7A7EPI0S7 D8A8EPI0S8 D9A9EPI0S9 D10A10EPI0S10 D11A11EPI0S11 D12A12bEPI0S12 D13BA0EPI0S13 D14BA1EPI0S14 D15EPI0S15 DQMLEPI0S16 DQMHEPI0S17 CASnEPI0S18 RASnEPI0S19 not usedEPI0S20-EPI0S27 WEnEPI0S28 CSnEPI0S29 CKEEPI0S30 CLKEPI0S31 a. If 2 signals are listed, connect the EPI signal to both pins. b. Only for 256/512 megabit SDRAMs

9.4.1.2 RefreshConfiguration

The refresh count is based on the external clock speed and the number of rows per bank as well as the refresh period. TheRFSH field represents how many external clock cycles remain before an AUTO-REFRESH is required. The normal formula is: RFSH = (tRefresh_us / number_rows) / ext_clock_period A refresh period is normally 64 ms, or 64000 μs. The number of rows is normally 4096 or 8192. The ext_clock_period is a value expressed in μsec and is derived by dividing 1000 by the clock speed expressed in MHz. So, 50 MHz is 1000/50=20 ns, or 0.02 μs. A typical SDRAM is 4096 rows per bank if the system clock is running at 50 MHz with anEPIBAUDregister value of 0: 461March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

RFSH = (64000/4096) / 0.02 = 15.625 μs / 0.02 μs = 781.25 The default value in theRFSH field is 750 decimal or 0x2EE to allow for a margin of safety and providing 15 μs per refresh. It is important to note that this number should always be smaller or equal to what is required by the above equation. For example, if running the external clock at 25 MHz (40 ns per clock period), 390 is the highest number that may be used. Note that the external clock may be 25 MHz when the system clock is 25 MHz or when the system clock is 50 MHz and configuring theCOUNT0 field in theEPIBAUDregister to 1 (divide by 2). If a number larger than allowed is used, the SDRAM is not refreshed often enough, and data is lost.

9.4.1.3 BusInterfaceSpeed

The EPI Controller SDRAM interface can operate up to 50 MHz. TheCOUNT0 field in theEPIBAUD register configures the speed of the EPI clock. For system clock (SysClk) speeds up to 50 MHz, the COUNT0 field can be 0x0000, and the SDRAM interface can run at the same speed as SysClk. However, if SysClk is running at higher speeds, the bus interface can run only as fast as half speed, and theCOUNT0 field must be configured to at least 0x0001.

9.4.1.4 Non-BlockingReadCycle

Figure 9-2 on page 462 shows a non-blocking read cycle of n halfwords; n can be any number greater than or equal to 1. The cycle begins with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed CAS latency of 2, the Read command with the column address on theEPI0S[15:0] signals follows after 2 clock cycles. Following one more NOP cycle, data is read in on theEPI0S[15:0] signals on every rising clock edge. The Burst Terminate command is issued during the cycle when the next-to-last halfword is read in. The DQMH and DQML signals are deasserted after the last halfword of data is received; the CSn signal deasserts on the following clock cycle, signaling the end of the read cycle. At least one clock period of inactivity separates any two SDRAM cycles. Figure9-2.SDRAMNon-BlockingReadCycle Row Column Data 0 Data 1 ... Data n CLK ( EPI0S31) CKE ( EPI0S30) CSn ( EPI0S29) WEn ( EPI0S28) RASn ( EPI0S19) CASn ( EPI0S18) DQMH, DQML ( EPI0S [17:16]) AD [15:0] ( EPI0S [15:0]) Activate NOP NOP Read NOP Burst T erm AD [15:0] driven in AD [15:0] driven out AD [15:0] driven out

9.4.1.5 NormalReadCycle

Figure 9-3 on page 463 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins with the Activate command and the row address on theEPI0S[15:0]signals. With the programmed CAS latency of 2, the Read command with the column address on theEPI0S[15:0] signals follows March 19, 2011462 Texas Instruments-Advance Information External Peripheral Interface (EPI)

after 2 clock cycles. Following one more NOP cycle, data is read in on theEPI0S[15:0] signals on every rising clock edge. The DQMH, DQML, and CSn signals are deasserted after the last halfword of data is received, signaling the end of the cycle. At least one clock period of inactivity separates any two SDRAM cycles. Figure9-3.SDRAMNormalReadCycle Row Column Data 0 Data 1 CLK ( EPI0S31) CKE ( EPI0S30) CSn ( EPI0S29) WEn ( EPI0S28) RASn ( EPI0S19) CASn ( EPI0S18) DQMH, DQML ( EPI0S [17:16]) AD [15:0] ( EPI0S [15:0]) Activate NOP NOP Read NOP AD [15:0] driven in AD [15:0] driven out AD [15:0] driven out

9.4.1.6 WriteCycle

Figure 9-4 on page 464 shows a write cycle of n halfwords; n can be any number greater than or equal to 1. The cycle begins with the Activate command and the row address on theEPI0S[15:0] signals. With the programmed CAS latency of 2, the Write command with the column address on the EPI0S[15:0]signals follows after 2 clock cycles. When writing to SDRAMs, the Write command is presented with the first halfword of data. Because the address lines and the data lines are multiplexed, the column address is modified to be (programmed address -1). During the Write command, the DQMH and DQML signals are high, so no data is written to the SDRAM. On the next clock, the DQMH and DQML signals are asserted, and the data associated with the programmed address is written. The Burst Terminate command occurs during the clock cycle following the write of the last halfword of data. The WEn, DQMH, DQML, and CSn signals are deasserted after the last halfword of data is received, signaling the end of the access. At least one clock period of inactivity separates any two SDRAM cycles. 463March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure9-4.SDRAMWriteCycle Row Column-1 Data 0 Data 1 ... Data n CLK ( EPI0S31) CKE ( EPI0S30) CSn ( EPI0S29) WEn ( EPI0S28) RASn ( EPI0S19) CASn ( EPI0S18) DQMH, DQML ( EPI0S [17:16]) AD [15:0] ( EPI0S [15:0]) Activate NOP NOP W rite Burst T erm AD [15:0] driven out AD [15:0] driven out

9.4.2 HostBusMode

Host Bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051devices and SRAM devices. This interface is asynchronous and uses strobe pins to control activity.

9.4.2.1 ControlPins

The main three strobes are ALE (Address latch enable), WRn (write), and RDn (sometimes called OEn, used for read). Note that the timings are designed for older logic and so are hold-time vs. setup-time specific. To ensure proper operation on this bus, the EPI block uses two system clocks per transition to allow significant skewing of control vs. data signals. So, for example, ALE rises one EPI clock before ADDR/DATA is asserted. Likewise, ALE falls (latch point) one EPI clock before DATA changes or tri-states. The same approach is used for the WRn and RDn/OEn strobes. The polarity of the read and write strobes can be active High or active Low by clearing or setting the RDHIGH and WRHIGH bits in theEPIHost-BusnConfiguration2(EPIHBnCFG2) register. The ALE can be changed to an active-low chip select signal, CSn, through theEPIHBnCFG2register. The ALE is best used for Host-Bus muxed mode in which EPI address and data pins are shared. All Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an external latch to capture the address then hold it until the data phase. CSn is best used for Host-Bus unmuxed mode in which EPI address and data pins are separate. The CSn indicates when the address and data phases of a read or write access is occurring. Both the ALE and the CSn modes can be enhanced to access two external devices using settings in theEPIHBnCFG2register. Wait states can be added to the data phase of the access using theWRWS and RDWS bits in the EPIHBnCFG2register. For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and output to what the XFIFO can handle. Host-Bus 8 and Host-Bus 16 modes are very configurable. The user has the ability to connect 1 or 2 external devices to the EPI signals as well as control whether byte select signals are provided in HB16 mode. These capabilities depend on the configuration of theMODE field in theEPIHBnCFG register, theCSCFG field in theEPIHBnCFG2register, and theBSEL bit in theEPIHB16CFGregister. March 19, 2011464 Texas Instruments-Advance Information External Peripheral Interface (EPI)

If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in theEPIHBnCFG2register), both chip selects can share the peripheral or the memory space, or one chip select can use the peripheral space and the other can use the memory space. In theEPIADDRMAPregister, if the EPADR field is not 0x0 and theERADR field is 0x0, then the address specified byEPADR is used for both chip selects, with CS0n being asserted when the MSB of the address range is 0 and CS1n being asserted when the MSB of the address range is 1. If theERADR field is not 0x0 and theEPADR field is 0x0, then the address specified byERADR is used for both chip selects, with the MSB performing the same delineation. If both theEPADR and theERADR are not 0x0, then CS0n is asserted for the address range defined byEPADR and CS1n is asserted for the address range defined by ERADR. If theCSBAUD bit in theEPIHBnCFG2register is set, the 2 chip selects can use different clock frequencies. If theCSBAUD bit is clear, both chip selects use the clock frequency, wait states, and strobe polarity defined for CS0n. When BSEL=1 in theEPIHB16CFGregister, byte select signals are provided, so byte-sized data can be read and written at any address, however these signals reduce the available address width by 2 pins. The byte select signals are active Low.BSEL0n corresponds to the LSB of the halfword, and BSEL1n corresponds to the MSB of the halfword. When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes at even addresses write invalid values into the odd byte. As a result, accesses should be made as half-words (16-bits) or words (32-bits). In C/C++, programmers should use only short int and long int for accesses. Also, because data accesses in HB16 mode with no byte selects are on 2-byte boundaries, the available address space is doubled. For example, 28 bits of address accesses 512 MB in this mode. Table 9-4 on page 465 shows the capabilities of the HB8 and HB16 modes as well as the available address bits with the possible combinations of these bits. Although theEPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not required and should be configured as a GPIO to reduce EMI in the system. Table9-4.CapabilitiesofHostBus8andHostBus16Modes AvailableAddressByteAccessBSELMax#of External Devices CSCFGMODEHostBusType 28 bitsAlwaysN/A10x0, 0x10x0HB8 27 bitsAlwaysN/A20x20x0HB8 26 bitsAlwaysN/A20x30x0HB8 20 bitsAlwaysN/A10x0, 0x10x1HB8 19 bitsAlwaysN/A20x20x1HB8 18 bitsAlwaysN/A20x30x1HB8 noneAlwaysN/A10x10x3HB8 noneAlwaysN/A20x30x3HB8 28 bitsaNo010x0, 0x10x0HB16 26 bitsYes110x0, 0x10x0HB16 27 bitsaNo020x20x0HB16 25 bitsYes120x20x0HB16 26 bitsaNo020x30x0HB16 24 bitsYes120x30x0HB16 12 bitsaNo010x0, 0x10x1HB16 10 bitsYes110x0, 0x10x1HB16 11 bitsaNo020x20x1HB16 465March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table9-4.CapabilitiesofHostBus8andHostBus16Modes (continued) AvailableAddressByteAccessBSELMax#of External Devices CSCFGMODEHostBusType 9 bitsYes120x20x1HB16 10 bitsaNo020x30x1HB16 8 bitsYes120x30x1HB16 noneNo010x10x3HB16 noneYes110x10x3HB16 noneNo020x30x3HB16 noneYes120x30x3HB16 a. If byte selects are not used, data accesses are on 2-byte boundaries. As a result, the available address space is doubled. Table 9-5 on page 466 shows how theEPI[31:0] signals function while in Host-Bus 8 mode. Notice that the signal configuration changes based on the address/data mode selected by theMODE field in theEPIHB8CFG2register and on the chip select configuration selected by theCSCFG field in the same register. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table9-5.EPIHost-Bus8SignalConnections HB8Signal(MODE =XFIFO) HB8Signal(MODE =ADNOMUX(Cont. Read)) HB8Signal(MODE =ADMUX) CSCFGEPISignal D0D0AD0XaEPI0S0 D1D1AD1XEPI0S1 D2D2AD2XEPI0S2 D3D3AD3XEPI0S3 D4D4AD4XEPI0S4 D5D5AD5XEPI0S5 D6D6AD6XEPI0S6 D7D7AD7XEPI0S7 -A0A8XEPI0S8 -A1A9XEPI0S9 -A2A10XEPI0S10 -A3A11XEPI0S11 -A4A12XEPI0S12 -A5A13XEPI0S13 -A6A14XEPI0S14 -A7A15XEPI0S15 -A8A16XEPI0S16 -A9A17XEPI0S17 -A10A18XEPI0S18 -A11A19XEPI0S19 -A12A20XEPI0S20 -A13A21XEPI0S21 -A14A22XEPI0S22 -A15A23XEPI0S23 March 19, 2011466 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Table9-5.EPIHost-Bus8SignalConnections (continued) HB8Signal(MODE =XFIFO) HB8Signal(MODE =ADNOMUX(Cont. Read)) HB8Signal(MODE =ADMUX) CSCFGEPISignal -A16A24XEPI0S24 A17A25b 0x0 EPI0S25 0x1 CS1n0x2 -0x3 FEMPTY A18A26 0x0 EPI0S26 0x1 0x2 CS0nCS0n0x3 FFULL A19A27 0x0 EPI0S27 0x1 CS1nCS1n 0x2 0x3 RDnRDn/OEnRDn/OEnXEPI0S28 WRnWRnWRnXEPI0S29 -ALEALE0x0 EPI0S30 CSnCSnCSn0x1 CS0nCS0nCS0n0x2 -ALEALE0x3 ClockcClockcClockcXEPI0S31 a. "X" indicates the state of this field is a don't care. b. When an entry straddles several row, the signal configuration is the same for all rows. c. The clock signal is not required for this mode and has unspecified timing relationships to other signals. Table 9-6 on page 467 shows how theEPI[31:0] signals function while in Host-Bus 16 mode. Notice that the signal configuration changes based on the address/data mode selected by theMODE field in theEPIHB16CFG2register, on the chip select configuration selected by theCSCFG field in the same register, and on whether byte selects are used as configured by theBSEL bit in the EPIHB16CFGregister. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table9-6.EPIHost-Bus16SignalConnections HB16Signal (MODE =XFIFO) HB16Signal(MODE =ADNOMUX(Cont. Read)) HB16Signal(MODE =ADMUX) BSELCSCFGEPISignal D0D0AD0bXXaEPI0S0 D1D1AD1XXEPI0S1 D2D2AD2XXEPI0S2 D3D3AD3XXEPI0S3 D4D4AD4XXEPI0S4 D5D5AD5XXEPI0S5 D6D6AD6XXEPI0S6 467March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table9-6.EPIHost-Bus16SignalConnections (continued) HB16Signal (MODE =XFIFO) HB16Signal(MODE =ADNOMUX(Cont. Read)) HB16Signal(MODE =ADMUX) BSELCSCFGEPISignal D7D7AD7XXEPI0S7 D8D8AD8XXEPI0S8 D9D9AD9XXEPI0S9 D10D10AD10XXEPI0S10 D11D11AD11XXEPI0S11 D12D12AD12XXEPI0S12 D13D13AD13XXEPI0S13 D14D14AD14XXEPI0S14 D15D15AD15XXEPI0S15 -A0bA16XXEPI0S16 -A1A17XXEPI0S17 -A2A18XXEPI0S18 -A3A19XXEPI0S19 -A4A20XXEPI0S20 -A5A21XXEPI0S21 -A6A22XXEPI0S22 -A7A23 XcEPI0S23 A8A24 0x0 EPI0S24 0x1 0x2 0x3 BSEL0nBSEL0n1 -A9A25X 0x0 EPI0S25 0x1 CS1n A9A250 0x2 BSEL0nBSEL0n1 A9A250 0x3 BSEL1nBSEL1n1 FEMPTY A10A260 0x0 EPI0S26 BSEL0nBSEL0n1 A10A260 0x1 BSEL0nBSEL0n1 A10A260 0x2 BSEL1nBSEL1n1 CS0nCS0nX0x3 March 19, 2011468 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Table9-6.EPIHost-Bus16SignalConnections (continued) HB16Signal (MODE =XFIFO) HB16Signal(MODE =ADNOMUX(Cont. Read)) HB16Signal(MODE =ADMUX) BSELCSCFGEPISignal FFULL A11A270 0x0 EPI0S27 BSEL1nBSEL1n1 A11A270 0x1 BSEL1nBSEL1n1 CS1nCS1n X0x2 X0x3 RDnRDn/OEnRDn/OEnXXEPI0S28 WRnWRnWRnXXEPI0S29 -ALEALEX0x0 EPI0S30 CSnCSnCSnX0x1 CS0nCS0nCS0nX0x2 -ALEALEX0x3 ClockdClockdClockdXXEPI0S31 a. "X" indicates the state of this field is a don't care. b. In this mode, half-word accesses are used. A0 is the LSB of the address and is equivalent to the internal Cortex-M3 A1 address. This pin should be connected to A0 of 16-bit memories. c. When an entry straddles several row, the signal configuration is the same for all rows. d. The clock signal is not required for this mode and has unspecified timing relationships to other signals. Figure 9-5 on page 470 shows how to connect the EPI signals to a 16-bit SRAM and a 16-bit Flash memory with muxed address and memory using byte selects and dual chip selects with ALE. This schematic is just an example of how to connect the signals; timing and loading have not been analyzed. In addition, not all bypass capacitors are shown. 469March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure9-5.ExampleSchematicforMuxedHost-Bus16Mode STELLARIS MICROCONTROLLERS www.ti.com/stellaris AUSTIN TX, 78746

108 WILD BASIN ROAD, SUITE 350

?PART NUMBER? 1/6/2011 ?DESC2? ?DESC1? ?PROJECT NAME? ?REV? epi16_example.sch OF ??? SHEET PART NO. DATE REVISION DESIGNER FILENAME

DESCRIPTION

R Configuration assumes EPIHB16 Mode = ADMUX, BSEL = 1, CSCFG = 3 Example Schematic for signal connection purposes only. Timing, Loading and other analysis have not been validated CON-EPI-MALE C0603 0.1uF C0603 0.1uF C0603 0.1uF C0603 0.1uF CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 A12 A11 A10 NC I/O8 I/O9 I/O10 I/O11 VCC VSS I/O12 I/O13 I/O14 I/O15 BLE BHE OE CY62147 A15 A14 A13 A12 A11 A10 NC NC WE NC NC NC NC A18 A17 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VDD DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15 VSS NC A16 SST39VF800A 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 2LE 2D8 2D7 GND 2D6 2D5 VCC 2D4 2D3 GND 2D2 2D1 1D8 1D7 GND 1D6 1D5 VCC 1D4 1D3 GND 1D2 1D1 1LE 74X16373 C0603 0.1uF C0603 0.1uF C0603 0.1uF EPI_16_BUS +3.3V +5V GND GND EPI13 EPI14 EPI27 EPI16 EPI21 EPI20 EPI30 EPI29 EPI28 EPI19 EPI25 EPI22 EPI23 EPI24 EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 EPI8 EPI9 EPI10 EPI11 EPI12 EPI15 EPI18 EPI17 EPI31 EPI26 GND GND EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 EPI30 +3.3V GND GND +3.3V GND A[0:15] A10 A11 A12 A13 A14 A15 A[0:15] EPI_16_BUS EPI_16_BUS A10 A11 A12 A13 A14 A15 EPI16 EPI17 EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 EPI28 EPI29 EPI26 EPI25 EPI24 A[0:15] EPI_16_BUS EPI_16_BUS A10 A11 A12 A13 A14 A15 EPI16 EPI17 EPI18 EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 EPI29 EPI28 EPI27 EPI_16_BUS +3.3V GND +3.3V GND GND +3.3V +3.3V GND

9.4.2.2 SpeedofTransactions

The COUNT0 field in theEPIBAUDregister must be configured to set the main transaction rate based on what the slave device can support (including wiring considerations). The main control transitions are normally ½ the baud rate (COUNT0= 1) because the EPI block forces data vs. control to change on alternating clocks. When using dual chip-selects, each chip select can access the bus using differing baud rates by setting theCSBAUD bit in theEPIHBnCFG2register. In this case, the COUNT0 field controls the CS0n transactions, and theCOUNT1 field controls the CS1n transactions. Additionally, the Host-Bus mode provides read and write wait states for the data portion to support different classes of device. These wait states stretch the data period (hold the rising edge of data March 19, 2011470 Texas Instruments-Advance Information External Peripheral Interface (EPI)

strobe) and may be used in all four sub-modes. The wait states are set using theWRWS and RDWS bits in theEPIHost-BusnConfiguration(EPIHBnCFG) register.

9.4.2.3 Sub-ModesofHostBus8/16

The EPI controller supports four variants of the Host-Bus model using 8 or 16 bits of data in all four cases. The four sub-modes are selected using theMODE bits in theEPIHBnCFGregister, and are: 1. Address and data are muxed. This scheme is used by many 8051 devices, some Microchip PIC parts, and some ATmega parts. When used for standard SRAMs, a latch must be used between the microcontroller and the SRAM. This sub-mode is provided for compatibility with existing devices that support data transfers without a latch (for example, LCD controllers or CPLDs). In general, the de-muxed sub-mode should normally be used. The ALE configuration should be used in this mode, as all Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an external latch to capture the address then hold until the data phase. The ALE configuration is controlled by configuring theCSCFG field to be 0x0 in theEPIHBnCFG2 register. The ALE can be enhanced to access two external devices with the addition of two separate CSn signals. By configuring theCSCFG field in the to be 0x3 in theEPIHBnCFG2 register, EPI0S30 functions as ALE,EPI0S27 functions as CS1n, andEPI0S26 functions as CS0n. The CSn is best used for Host-Bus unmuxed mode which EPI address and data pins are separate. The CSn indicates when the address and data phases of a read or write access are occurring. 2. Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB). This scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts. This mode is generally used with real SRAMs, many EEPROMs, and many NOR Flash memory devices. Note that there is no hardware command write support for Flash memory devices; this mode should only be used for Flash memory devices programmed at manufacturing time. If a Flash memory device must be written and does not support a direct programming model, the command mechanism must be performed in software. The CSn configuration should be used in this mode. The CSn signal indicates when the address and data phases of a read or write access is occurring. The CSn configuration is controlled by configuring theCSCFG field to be 0x1 in theEPIHBnCFG2register. 3. Continuous read mode where address and data are separate. This sub-mode is used for real SRAMs which can be read more quickly by only changing the address (and not using RDn/OEn strobing). In this sub-mode, reads are performed by keeping the read mode selected (output enable is asserted) and then changing the address pins. The data pins are changed by the SRAM after the address pins change. For example, to read data from address 0x100 and then 0x101, the EPI controller asserts the output-enable signal and then configures the address pins to 0x100; the EPI controller then captures what is on the data pins and increments A0 to 1 (so the address is now 0x101); the EPI controller then captures what is on the data pins. Note that this mode consumes higher power because the SRAM must continuously drive the data pins. This mode is not practical in HB16 mode for normal SRAMs because there are generally not enough address bits available. 4. FIFO mode uses 8 or 16 bits of data, removes ALE and address pins and optionally adds external XFIFO FULL/EMPTY flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configurations (FIFO through block RAM). This sub-mode provides the data side of the normal Host-Bus interface, but is paced by the FIFO control signals. It is important to consider that the XFIFO FULL/EMPTY control signals may stall the interface and could have an impact on blocking read latency from the processor or μDMA. 471March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

The WORD bit in theEPIHBnCFG2register can be set to use memory more efficiently. By default, the EPI controller uses data bits [7:0] for Host-Bus 8 accesses or bits [15:0] for Host-Bus 16 accesses. When theWORD bit is set, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] (HB8) or [31:16] (HB16). In addition, for the three modes above (1, 2, 4) that the Host-Bus 16 mode supports, byte select signals can be optionally implemented by setting theBSEL bit in theEPIHB16CFGregister. See “External Peripheral Interface (EPI)” on page 1308 for timing details for the Host-Bus mode.

9.4.2.4 BusOperation

Bus operation is the same in Host-Bus 8 and Host-Bus 16 modes and is asynchronous. Timing diagrams show both ALE and CSn operation, but only one signal or the other is used in all modes except for ALE with dual chip selects mode (CSCFGfield is 0x3 in theEPIHBnCFG2register). Address and data on write cycles are held after the CSn signal is deasserted. The optional HB16 byte select signals have the same timing as the address signals. If wait states are required in the bus access, they can be inserted during the data phase of the access using theWRWS and RDWS bits in theEPIHBnCFG2register. Each wait state adds 2 EPI clock cycles to the duration of the WRn or RDn strobe. During idle cycles, the address and muxed address data signals maintain the state of the last cycle. Figure 9-6 on page 472 shows a basic Host-Bus read cycle. Figure 9-7 on page 473 shows a basic Host-Bus write cycle. Both of these figures show address and data signals in the non-multiplexed mode (MODEfield ix 0x1 in theEPIHBnCFGregister). Figure9-6.Host-BusReadCycle,MODE=0x1,WRHIGH=0,RDHIGH=0 Data ALE ( EPI 0 S 30 ) CSn ( EPI 0 S 30 ) WRn ( EPI 0 S 29 ) RDn/OEn ( EPI 0 S 28 ) Address Data BSEL0n/ BSEL 1n a a BSEL 0 n and BSEL 1 n are available in Host - Bus 16 mode only . March 19, 2011472 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Figure9-7.Host-BusWriteCycle,MODE=0x1,WRHIGH=0,RDHIGH=0 Data ALE ( EPI 0 S 30 ) CSn ( EPI 0 S 30 ) WRn ( EPI 0 S 29 ) RDn/OEn ( EPI 0 S 28 ) Address Data BSEL0n/ BSEL 1n a a BSEL 0 n and BSEL 1 n are available in Host - Bus 16 mode only . Figure 9-8 on page 473 shows a write cycle with the address and data signals multiplexed (MODE field is 0x0 in theEPIHBnCFGregister). A read cycle would look similar, with the RDn strobe being asserted along with CSn and data being latched on the rising edge of RDn. Figure9-8.Host-BusWriteCyclewithMultiplexedAddressandData,MODE=0x0,WRHIGH=0,RDHIGH Data ALE ( EPI 0 S 30 ) CSn ( EPI 0 S 30 ) WRn ( EPI 0 S 29 ) RDn/OEn ( EPI 0 S 28 ) Address ( high order , non muxed) Muxed Address /Data Address BSEL0n/ BSEL 1n a a BSEL 0 n and BSEL 1 n are available in Host - Bus 16 mode only . When using ALE with dual CSn configuration (CSCFGfield in theEPIHBnCFG2register is 0x3), the appropriate CSn signal is asserted at the same time as ALE as shown in Figure 9-9 on page 474. 473March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure9-11.WriteFollowedbyReadtoExternalFIFO FFULL ( EPI 0 S 27 ) FEMPTY ( EPI 0 S 26 ) CSn ( EPI 0 S 30 ) WRn ( EPI 0 S 29 ) RDn ( EPI 0 S 28 ) Data Data Data Figure9-12.Two-EntryFIFO FFULL ( EPI 0 S 27 ) FEMPTY ( EPI 0 S 26 ) CSn ( EPI 0 S 30 ) WRn ( EPI 0 S 29 ) RDn ( EPI 0 S 28 ) Data Data Data Data

9.4.3 General-PurposeMode

The General-PurposeModeConfiguration(EPIGPCFG) register is used to configure the control, data, and address pins, if used. Any unused EPI controller signals can be used as GPIOs or another alternate function. The general-purpose configuration can be used for custom interfaces with FPGAs, CPLDs, and digital data acquisition and actuator control. Important: The RD2CYC bit in theEPIGPCFGregister must be set at all times in General-Purpose mode to ensure proper operation. General-Purpose mode is designed for three general types of use: ■ Extremely high-speed clocked interfaces to FPGAs and CPLDs. Three sizes of data and optional address are supported. Framing and clock-enable functions permit more optimized interfaces. ■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely controlled by theEPIBAUDregister baud rate (when used with the WFIFO and/or the NBRFIFO) or by the rate of accesses from software or μDMA. Examples of this type of use include: – Reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the COUNT0 field in theEPIBAUDregister to some divider, and then using non-blocking reads. 475March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

– Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators, LEDs, etc. – Implementing SDIO 4-bit mode where commands are driven or captured on 6 pins with fixed timing, fed by the µDMA. ■ General custom interfaces of any speed. The configuration allows for choice of an output clock (free-running or gated), a framing signal (with frame size), a ready input (to stretch transactions), a read and write strobe, an address (of varying sizes), and data (of varying sizes). Additionally, provisions are made for separating data and address phases. The interface has the following optional features: ■ Use of the EPI clock output is controlled by theCLKPIN bit in theEPIGPCFGregister. Unclocked uses include general-purpose I/O and asynchronous interfaces (optionally using RD and WR strobes). Clocked interfaces allow for higher speeds and are much easier to connect to FPGAs and CPLDs (which usually include input clocks). ■ EPI clock, if used, may be free running or gated depending on theCLKGATE bit in theEPIGPCFG register. A free-running EPI clock requires another method for determining when data is live, such as the frame pin or RD/WR strobes. A gated clock approach uses a setup-time model in which the EPI clock controls when transactions are starting and stopping. The gated clock is held high until a new transaction is started and goes high at the end of the cycle where RD/WR/FRAME and address (and data if write) are emitted. ■ Use of the ready input (iRDY) from the external device is controlled by theRDYEN bit in the EPIGPCFGregister. The iRDY signal usesEPI0S27 and may only be used with a free-running clock. iRDY gates transactions, no matter what state they are in. When iRDY is deasserted, the transaction is held off from completing. ■ Use of the frame output (FRAME) is controlled by theFRMPIN bit in theEPIGPCFGregister. The frame pin may be used whether the clock is output or not, and whether the clock is free running or not. It may also be used along with the iRDY signal. The frame may be a pulse (one clock) or may be 50/50 split across the frame size (controlled by theFRM50 bit in theEPIGPCFG register). The frame count (the size of the frame as specified by theFRMCNT field in the EPIGPCFGregister) may be between 1 and 15 clocks for pulsed and between 2 and 30 clocks for 50/50. The frame pin counts transactions and not clocks; a transaction is any clock where the RD or WR strobe is high (if used). So, if theFRMCNT bit is set, then the frame pin pulses every other transaction; if 2-cycle reads and writes are used, it pulses every other address phase. FRM50 must be used with this in mind as it may hold state for many clocks waiting for the next transaction. ■ Use of the RD and WR outputs is controlled by theRW bit in theEPIGPCFGregister. For interfaces where the direction is known (in advance, related to frame size, or other means), these strobes are not needed. For most other interfaces, RD and WR are used so the external peripheral knows what transaction is taking place, and if any transaction is taking place. ■ Separation of address/request and data phases may be used on writes using theWR2CYC bit in the EPIGPCFGregister. This configuration allows the external peripheral extra time to act. Address and data phases must be separated on reads, and theRD2CYC bit in theEPIGPCFG register must be set. When configured to use an address as specified by theASIZE field in the EPIGPCFGregister, the address is emitted on the with the RD strobe (first cycle) and data is March 19, 2011476 Texas Instruments-Advance Information External Peripheral Interface (EPI)

expected to be returned on the next cycle (when RD is not asserted). If no address is used, then RD is asserted on the first cycle and data is captured on the second cycle (when RD is not asserted), allowing more setup time for data. For writes, the output may be in one or two cycles. In the two-cycle case, the address (if any) is emitted on the first cycle with the WR strobe and the data is emitted on the second cycle (with WR not asserted). Although split address and write data phases are not normally needed for logic reasons, it may be useful to make read and write timings match. If 2-cycle reads or writes are used, theRW bit is automatically set. ■ Address may be emitted (controlled by theASIZE field in theEPIGPCFGregister). The address may be up to 4 bits (16 possible values), up to 12 bits (4096 possible values), or up to 20 bits (1 M possible values). Size of address limits size of data, for example, 4 bits of address support up to 24 bits data. 4-bit address usesEPI0S[27:24]; 12-bit address usesEPI0S[27:16]; 20-bit address usesEPI0S[27:8]. The address signals may be used by the external peripheral as an address, code (command), or for other unrelated uses (such as a chip enable). If the chosen address/data combination does not use all of the EPI signals, the unused pins can be used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit data, the pins assigned toEPIS0[23:8] can be assigned to other functions. ■ Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by theDSIZE field in theEPIGPCFG register). 32-bit data cannot be used with address or EPI clock or any other signal. 24-bit data can only be used with 4-bit address or no address. 32-bit data requires that either theWR2CYC bit or theRD2CYC bit in theEPIGPCFGregister is set. ■ Memory can be used more efficiently by using the Word Access Mode. By default, the EPI controller uses data bits [7:0] when theDSIZE field in theEPIGPCFGregister is 0x0; data bits [15:0] when theDSIZE field is 0x1; data bits [23:0] when theDSIZE field is 0x2; and data bits [31:0] when theDSIZE field is 0x3. When theWORD bit in theEPIGPCFG2register is set, the EPI controller automatically routes bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] forDSIZE=0x0 and bits [31:16] forDSIZE=0x1. ■ When using the EPI controller as a GPIO interface, writes are FIFOed (up to 4 can be held at any time), and up to 32 pins are changed using theEPIBAUDclock rate specified byCOUNT0. As a result, output pin control can be very precisely controlled as a function of time. By contrast, when writing to normal GPIOs, writes can only occur 8-bits at a time and take up to two clock cycles to complete. In addition, the write itself may be further delayed by the bus due to μDMA or draining of a previous write. With both GPIO and the EPI controller, reads may be performed directly, in which case the current pin states are read back. With the EPI controller, the non-blocking interface may also be used to perform reads based on a fixed time rule via the EPIBAUDclock rate. Table 9-7 on page 477 shows how theEPI0S[31:0] signals function while in General-Purpose mode. Notice that the address connections vary depending on the data-width restrictions of the external peripheral. Table9-7.EPIGeneralPurposeSignalConnections General-Purpose Signal(D32) General-Purpose Signal(D24,A4) General-Purpose Signal(D16,A12) General-Purpose Signal(D8,A20) EPISignal D0D0D0D0EPI0S0 D1D1D1D1EPI0S1 D2D2D2D2EPI0S2 477March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table9-7.EPIGeneralPurposeSignalConnections (continued) General-Purpose Signal(D32) General-Purpose Signal(D24,A4) General-Purpose Signal(D16,A12) General-Purpose Signal(D8,A20) EPISignal D3D3D3D3EPI0S3 D4D4D4D4EPI0S4 D5D5D5D5EPI0S5 D6D6D6D6EPI0S6 D7D7D7D7EPI0S7 D8D8D8A0EPI0S8 D9D9D9A1EPI0S9 D10D10D10A2EPI0S10 D11D11D11A3EPI0S11 D12D12D12A4EPI0S12 D13D13D13A5EPI0S13 D14D14D14A6EPI0S14 D15D15D15A7EPI0S15 D16D16A0aA8EPI0S16 D17D17A1A9EPI0S17 D18D18A2A10EPI0S18 D19D19A3A11EPI0S19 D20D20A4A12EPI0S20 D21D21A5A13EPI0S21 D22D22A6A14EPI0S22 D23D23A7A15EPI0S23 D24A0bA8A16EPI0S24 D25A1A9A17EPI0S25 D26A2A10A18EPI0S26 D27A3/iRDYcA11/iRDYcA19/iRDYcEPI0S27 D28WRWRWREPI0S28 D29RDRDRDEPI0S29 D30FrameFrameFrameEPI0S30 D31ClockClockClockEPI0S31 a. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address. b. In this mode, word accesses are used. AO is the LSB of the address and is equivalent to the system A2 address. c. This signal is iRDY if theRDYEN bit in theEPIGPCFGregister is set.

9.4.3.1 BusOperation

A basic access is 1 EPI clock for write cycles and 2 EPI clocks for read cycles. An additional EPI clock can be inserted into a write cycle by setting theWR2CYC bit in theEPIGPCFGregister. Note that theRD2CYC bit must always be set in theEPIGPCFGregister. If the iRDY signal is deasserted, further transactions are held off until the iRDY signal is asserted again. March 19, 2011478 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Figure9-13.Single-CycleWriteAccess,FRM50=0,FRMCNT=0,WRCYC=0 Data Clock ( EPI 0 S 31 ) Frame ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) Address Data Figure9-14.Two-CycleRead,WriteAccesses,FRM50=0,FRMCNT=0,RDCYC=1,WRCYC=1 Read Data Data CLOCK ( EPI 0 S 31 ) FRAME ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) Address Data W rite 479March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Figure9-15.ReadAccesses,FRM50=0,FRMCNT=0,RDCYC=1 Addr2 CLOCK ( EPI 0 S 31 ) FRAME ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) Address Data Addr1 Addr3 Data2Data1 Data3 FRAME Signal Operation The operation of the FRAME signal is controlled by theFRMCNT and FRM50 bits. WhenFRM50 is clear, the FRAME signal is high whenever the WR or RD strobe is high. WhenFRMCNT is clear, the FRAME signal is simply the logical OR of the WR and RD strobes so the FRAME signal is high during every read or write access, see Figure 9-16 on page 480. Figure9-16.FRAMESignalOperation,FRM50=0andFRMCNT=0 Clock ( EPI 0 S 31 ) Frame ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) If theFRMCNT field is 0x1, then the FRAME signal pulses high during every other read or write access, see Figure 9-17 on page 480. Figure9-17.FRAMESignalOperation,FRM50=0andFRMCNT=1 Clock ( EPI 0 S 31 ) Frame ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) If theFRMCNT field is 0x2 andFRM50 is clear, then the FRAME signal pulses high during every third access, and so on for every value ofFRMCNT, see Figure 9-18 on page 481. March 19, 2011480 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Figure9-18.FRAMESignalOperation,FRM50=0andFRMCNT=2 Clock ( EPI 0 S 31 ) Frame ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) When FRM50 is set, the FRAME signal transitions on the rising edge of either the WR or RD strobes. When FRMCNT=0, the FRAME signal transitions on the rising edge of WR or RD for every access, see Figure 9-19 on page 481. Figure9-19.FRAMESignalOperation,FRM50=1andFRMCNT=0 Clock ( EPI 0 S 31 ) Frame ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) When FRMCNT=1, the FRAME signal transitions on the rising edge of the WR or RD strobes for every other access, see Figure 9-20 on page 481. Figure9-20.FRAMESignalOperation,FRM50=1andFRMCNT=1 Clock ( EPI 0 S 31 ) Frame ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) When FRMCNT=2, the FRAME signal transitions the rising edge of the WR or RD strobes for every third access, and so on for every value ofFRMCNT, see Figure 9-21 on page 481. Figure9-21.FRAMESignalOperation,FRM50=1andFRMCNT=2 CLOCK ( EPI 0 S 31 ) FRAME ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) WR ( EPI 0 S 28 ) 481March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

The ready input (iRDY) from the external device is enabled by theRDYEN bit in theEPIGPCFG register. iRDY is input onEPI0S27 and may only be used with a free-running clock (CLKGATEis clear). iRDY is sampled on the falling edge of the EPI clock and gates transactions, no matter what state they are in. Figure 9-22 on page 482 shows the iRDY signal being recognized as deasserted on the falling edge of T1. The FRAME, RD, Address, Data signals behave as they would during a normal transaction in T1. T2 is the frozen state, and signals are held in this state until iRDY is recognized as asserted again. At the falling edge of T2, when iRDY is asserted again, the cycle continues and completes in T3. Figure9-22.iRDYSignalOperation,FRM50=0,FRMCNT=0,andRD2CYC=1 Clock ( EPI 0 S 31 ) Frame ( EPI 0 S 30 ) RD ( EPI 0 S 29 ) iRDY ( EPI 0 S 27 ) Address Data T0 T1 T2 T3 EPI Clock Operation If theCLKGATE bit in theEPIGPCFGregister is clear, the EPI clock always toggles when General-purpose mode is enabled. IfCLKGATE is set, the clock is output only when a transaction is occurring, otherwise the clock is held high. If theWR2CYC bit is clear, the EPI clock begins toggling 1 cycle before the WR strobe goes high. If theWR2CYC bit is set, the EPI clock begins toggling when the WR strobe goes high. The clock stops toggling after the first rising edge after the WR strobe is deasserted. The RD strobe operates in the same manner as the WR strobe when theWR2CYC bit is set, as theRD2CYC bit must always be set. See Figure 9-23 on page 482 and Figure 9-24 on page 483. Figure9-23.EPIClockOperation,CLKGATE=1,WR2CYC=0 WR ( EPI 0 S 28 ) Address Data Clock ( EPI 0 S 31 ) March 19, 2011482 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Figure9-24.EPIClockOperation,CLKGATE=1,WR2CYC=1 Clock ( EPI 0 S 31 ) WR ( EPI 0 S 28 ) Address Data

9.5 RegisterMap

Table 9-8 on page 483 lists the EPI registers. The offset listed is a hexadecimal increment to the register’s address, relative to the base address of 0x400D.0000. Note that the EPI controller clock must be enabled before the registers can be programmed (see page 277). There must be a delay of 3 system clocks after the EPI module clock is enabled before any EPI module registers are accessed. Note: A back-to-back write followed by a read of the same register reads the value that written by the first write access, not the value from the second write access. (This situation only occurs when the processor core attempts this action, the μDMA does not do this.). To read back what was just written, another instruction must be generated between the write and read. Read-write does not have this issue, so use of read-write for clear of error interrupt cause is not affected. Table9-8.ExternalPeripheralInterface(EPI)RegisterMap See pageDescriptionResetTypeNameOffset 485EPI Configuration0x0000.0000R/WEPICFG0x000 486EPI Main Baud Rate0x0000.0000R/WEPIBAUD0x004 488EPI SDRAM Configuration0x42EE.0000R/WEPISDRAMCFG0x010 490EPI Host-Bus 8 Configuration0x0000.0000R/WEPIHB8CFG0x010 494EPI Host-Bus 16 Configuration0x0000.0000R/WEPIHB16CFG0x010 498EPI General-Purpose Configuration0x0000.0000R/WEPIGPCFG0x010 502EPI Host-Bus 8 Configuration 20x0000.0000R/WEPIHB8CFG20x014 504EPI Host-Bus 16 Configuration 20x0000.0000R/WEPIHB16CFG20x014 506EPI General-Purpose Configuration 20x0000.0000R/WEPIGPCFG20x014 507EPI Address Map0x0000.0000R/WEPIADDRMAP0x01C 509EPI Read Size 00x0000.0003R/WEPIRSIZE00x020 510EPI Read Address 00x0000.0000R/WEPIRADDR00x024 511EPI Non-Blocking Read Data 00x0000.0000R/WEPIRPSTD00x028 509EPI Read Size 10x0000.0003R/WEPIRSIZE10x030 510EPI Read Address 10x0000.0000R/WEPIRADDR10x034 483March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table9-8.ExternalPeripheralInterface(EPI)RegisterMap (continued) See pageDescriptionResetTypeNameOffset 511EPI Non-Blocking Read Data 10x0000.0000R/WEPIRPSTD10x038 513EPI Status0x0000.0000ROEPISTAT0x060 515EPI Read FIFO Count-ROEPIRFIFOCNT0x06C 516EPI Read FIFO-ROEPIREADFIFO0x070 516EPI Read FIFO Alias 1-ROEPIREADFIFO10x074 516EPI Read FIFO Alias 2-ROEPIREADFIFO20x078 516EPI Read FIFO Alias 3-ROEPIREADFIFO30x07C 516EPI Read FIFO Alias 4-ROEPIREADFIFO40x080 516EPI Read FIFO Alias 5-ROEPIREADFIFO50x084 516EPI Read FIFO Alias 6-ROEPIREADFIFO60x088 516EPI Read FIFO Alias 7-ROEPIREADFIFO70x08C 517EPI FIFO Level Selects0x0000.0033R/WEPIFIFOLVL0x200 519EPI Write FIFO Count0x0000.0004ROEPIWFIFOCNT0x204 520EPI Interrupt Mask0x0000.0000R/WEPIIM0x210 521EPI Raw Interrupt Status0x0000.0004ROEPIRIS0x214 523EPI Masked Interrupt Status0x0000.0000ROEPIMIS0x218 524EPI Error Interrupt Status and Clear0x0000.0000R/W1CEPIEISC0x21C

9.6 RegisterDescriptions

This section lists and describes the EPI registers, in numerical order by address offset. March 19, 2011484 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register1:EPIConfiguration(EPICFG),offset0x000 Important: The MODE field determines which configuration register is accessed for offsets 0x010 and 0x014. Any write to theEPICFGregister resets the register contents at offsets 0x010 and 0x014. The configuration register is used to enable the block, select a mode, and select the basic pin use (based on the mode). Note that attempting to program an undefinedMODE field clears theBLKEN bit and disables the EPI controller. EPI Configuration (EPICFG) Base 0x400D.0000 Offset 0x000 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 MODEBLKENreserved R/WR/WR/WR/WR/WROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:5 Block Enable DescriptionValue The EPI controller is enabled.1 The EPI controller is disabled.0 0R/WBLKEN4 Mode Select DescriptionValue General Purpose General-Purpose mode. Control, address, and data pins are configured using theEPIGPCFGand EPIGPCFG2registers. 0x0 SDRAM Supports SDR SDRAM. Control, address, and data pins are configured using theEPISDRAMCFGregister. 0x1 8-Bit Host-Bus (HB8) Host-bus 8-bit interface (also known as the MCU interface). Control, address, and data pins are configured using the EPIHB8CFGand EPIHB8CFG2registers. 0x2 16-Bit Host-Bus (HB16) Host-bus 16-bit interface (standard SRAM). Control, address, and data pins are configured using theEPIHB16CFGand EPIHB16CFG2registers. 0x3 Reserved0x3-0xF 0x0R/WMODE3:0 485March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register2:EPIMainBaudRate(EPIBAUD),offset0x004 The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the system clock down to control the speed on the external interface. If the mode selected emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does not use an EPI clock, this register controls the speed of changes on the external interface. Care must be taken to program this register properly so that the speed of the external bus corresponds to the speed of the external peripheral and puts acceptable current load on the pins.COUNT0 is the bit field used in all modes except in HB8 and HB16 modes with dual chip selects when different baud rates are selected, see page 502. If different baud rates are used,COUNT0 is associated with the address range specified by CS0 andCOUNT1 is associated with the address range specified by CS1. The COUNTn field is not a straight divider or count. The EPI Clock onEPI0S31 is related to the COUNTn field and the system clock as follows: If COUNTn = 0, kFreqSystemCloceqEPIClockFr = otherwise: 212 ×⎟ ⎛ +⎥⎦ = COUNTn kFreqSystemCloceqEPIClockFr where the symbol aroundCOUNTn/2 is the floor operator, meaning the largest integer less than or equal toCOUNTn/2. So, for example, aCOUNTn of 0x0001 results in a clock rate of ½(system clock); aCOUNTn of 0x0002 or 0x0003 results in a clock rate of ¼(system clock). EPI Main Baud Rate (EPIBAUD) Base 0x400D.0000 Offset 0x004 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 COUNT1 ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 COUNT0 R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Baud Rate Counter 1 This bit field is only valid when theCSCFG field is 0x2 or 0x3 and the CSBAUD bit is set in theEPIHBnCFG2register. This bit field contains a counter used to divide the system clock by the count. The maximum frequency for the external EPI clock is 50 MHz. A count of 0 means the system clock is used as is. 0x0000ROCOUNT131:16 March 19, 2011486 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Baud Rate Counter 0 This bit field contains a counter used to divide the system clock by the count. The maximum frequency for the external EPI clock is 50 MHz. A count of 0 means the system clock is used as is. 0x0000R/WCOUNT015:0 487March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register3:EPISDRAMConfiguration(EPISDRAMCFG),offset0x010 Important: The MODE field in theEPICFGregister determines which configuration register is accessed for offsets 0x010 and 0x014. To accessEPISDRAMCFG, theMODE field must be 0x1. The SDRAM Configuration register is used to specify several parameters for the SDRAM controller. Note that this register is reset when theMODE field in theEPICFGregister is changed. If another mode is selected and the SDRAM mode is selected again, the values must be reinitialized. The SDRAM interface designed to interface to x16 SDR SDRAMs of 64 MHz or higher, with the address and data pins overlapped (wire ORed on the board). See Table 9-3 on page 461 for pin assignments. EPI SDRAM Configuration (EPISDRAMCFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x42EE.0000 16171819202122232425262728293031 RFSHreservedFREQ R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROR/WR/WType 0111011101000010Reset 0123456789101112131415 SIZEreservedSLEEPreserved R/WR/WROROROROROROROR/WROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Frequency Range This field configures the frequency range of the system clock. This field must be configured correctly to ensure proper operation. This field does not affect the refresh counting, which is configured separately using the RFSH field (and is based on system clock rate and number of rows per bank). The ranges are: DescriptionValue 0 - 15 MHz0x0 15 - 30 MHz0x1 30 - 50 MHz0x2 50 - 100 MHz0x3 0x1R/WFREQ31:30 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved29:27 Refresh Counter This field contains the refresh counter in system clocks. The reset value of 0x2EE provides a refresh period of 64 ms when using a 50 MHz clock. 0x2EER/WRFSH26:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved15:10 March 19, 2011488 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Sleep Mode DescriptionValue The SDRAM is put into low power state, but is self-refreshed.1 No effect.0 0R/WSLEEP9 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved8:2 Size of SDRAM The value of this field affects address pins and behavior. DescriptionValue 64 megabits (8MB)0x0 128 megabits (16MB)0x1 256 megabits (32MB)0x2 512 megabits (64MB)0x3 0x0R/WSIZE1:0 489March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register4:EPIHost-Bus8Configuration(EPIHB8CFG),offset0x010 Important: The MODE field in theEPICFGregister determines which configuration register is accessed for offsets 0x010 and 0x014. To accessEPIHB8CFG, theMODE field must be 0x2. The Host Bus 8 Configuration register is activated when the HB8 mode is selected. The HB8 mode supports muxed address/data (overlay of lower 8 address and all 8 data pins), separated address/data, and address-less FIFO mode. Note that this register is reset when theMODE field in the EPICFGregister is changed. If another mode is selected and the HB8 mode is selected again, the values must be reinitialized. This mode is intended to support SRAMs, Flash memory (read), FIFOs, CPLDs/FPGAs, and devices with an MCU/HostBus slave or 8-bit FIFO interface support. Refer to Table 9-5 on page 466 for information on signal configuration controlled by this register and the EPIHB8CFG2register. If less address pins are required, the correspondingAFSEL bit (page 421) should not be enabled so the EPI controller does not drive those pins, and they are available as standard GPIOs. There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways: 1. Manually control via GPIOs. 2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses are not used. For example, if pinsEPI0S27 and EPI0S26 are used for Device 1 and 0 respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and 0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the corresponding GPIOs must be properly configured to ensure that the pins are disabled when the interface is not in use. 3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus providing CEn functionality. EPI Host-Bus 8 Configuration (EPIHB8CFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedRDHIGHWRHIGHXFEENXFFENreserved ROROROROR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset 0123456789101112131415 MODEreservedRDWSWRWSMAXWAIT R/WR/WROROR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 March 19, 2011490 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field External FIFO FULL Enable DescriptionValue An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL full signal is high, XFIFO writes are stalled. No effect.0 0R/WXFFEN23 External FIFO EMPTY Enable DescriptionValue An external FIFO empty signal can be used to control read cycles. If this bit is set and the FEMPTY signal is high, XFIFO reads are stalled. No effect.0 0R/WXFEEN22 WRITE Strobe Polarity DescriptionValue The WRITE strobe is WR (active High).1 The WRITE strobe is WRn (active Low).0 If both CS0n and CS1n are enabled (theCSCFGfield in theEPIHB8CFG2 register is 0x2 or 0x3), the programmed write strobe polarity is used for both CS0n and CS1n accesses. 0R/WWRHIGH21 READ Strobe Polarity DescriptionValue The READ strobe is RD (active High).1 The READ strobe is RDn (active Low).0 If both CS0n and CS1n are enabled (theCSCFGfield in theEPIHB8CFG2 register is 0x2 or 0x3), the programmed read strobe polarity is used for both CS0n and CS1n accesses. 0R/WRDHIGH20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved19:16 Maximum Wait This field defines the maximum number of external clocks to wait while an external FIFO ready signal is holding off a transaction (FFULL and FEMPTY). When this field is clear, the transaction is held off forever. Note: When theMODE field is configured to be 0x2 and theBLKEN bit is set in theEPICFGregister, enabling HB8 mode, this field defaults to 0xFF. 0x00R/WMAXWAIT15:8 491March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Write Wait States This field adds wait states to the data phase (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. DescriptionValue No wait states.0x0 1 wait state.0x1 2 wait states.0x2 3 wait states.0x3 This field is used in conjunction with theEPIBAUDregister. If both CS0n and CS1n are enabled (theCSCFGfield in theEPIHB8CFG2 register is 0x2 or 0x3), the same number of wait states is added to both CS0n and CS1n accesses. 0x0R/WWRWS7:6 Read Wait States This field adds wait states to the data phase (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. DescriptionValue No wait states.0x0 1 wait state.0x1 2 wait states.0x2 3 wait states.0x3 This field is used in conjunction with theEPIBAUDregister. If both CS0n and CS1n are enabled (theCSCFGfield in theEPIHB8CFG2 register is 0x2 or 0x3), the same number of wait states is added to both CS0n and CS1n accesses. 0x0R/WRDWS5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:2 March 19, 2011492 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Host Bus Sub-Mode This field determines which of four Host Bus 8 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 9-5 on page 466 for information on how this bit field affects the operation of the EPI signals. DescriptionValue ADMUX – AD[7:0] Data and Address are muxed. 0x0 ADNONMUX – D[7:0] Data and address are separate. 0x1 Continuous Read - D[7:0] This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OEn strobing. 0x2 XFIFO – D[7:0] This mode adds XFIFO controls with sense of XFIFO full and XFIFO empty. This mode uses no address or ALE. 0x3 0x0R/WMODE1:0 493March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register5:EPIHost-Bus16Configuration(EPIHB16CFG),offset0x010 Important: The MODE field in theEPICFGregister determines which configuration register is accessed for offsets 0x010 and 0x014. To accessEPIHB16CFG, theMODE field must be 0x3. The Host Bus 16 sub-configuration register is activated when the HB16 mode is selected. The HB16 mode supports muxed address/data (overlay of lower 16 address and all 16 data pins), separated address/data, and address-less FIFO mode. Note that this register is reset when theMODE field in the EPICFGregister is changed. If another mode is selected and the HB16 mode is selected again, the values must be reinitialized. This mode is intended to support SRAMs, Flash memory (read), FIFOs, and CPLDs/FPGAs, and devices with an MCU/HostBus slave or 16-bit FIFO interface support. Refer to Table 9-6 on page 467 for information on signal configuration controlled by this register and the EPIHB16CFG2register. If less address pins are required, the correspondingAFSEL bit (page 421) should not be enabled so the EPI controller does not drive those pins, and they are available as standard GPIOs. There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways: 1. Manually control via GPIOs. 2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses are not used. For example, if pinsEPI0S27 and EPI0S26 are used for Device 1 and 0 respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and 0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the corresponding GPIOs must be properly configured to ensure that the pins are disabled when the interface is not in use. 3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus providing CEn functionality. EPI Host-Bus 16 Configuration (EPIHB16CFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedRDHIGHWRHIGHXFEENXFFENreserved ROROROROR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset 0123456789101112131415 MODEBSELreservedRDWSWRWSMAXWAIT R/WR/WR/WROR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 March 19, 2011494 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field External FIFO FULL Enable DescriptionValue An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL signal is high, XFIFO writes are stalled. No effect.0 0R/WXFFEN23 External FIFO EMPTY Enable DescriptionValue An external FIFO empty signal can be used to control read cycles. If this bit is set and the FEMPTY signal is high, XFIFO reads are stalled. No effect.0 0R/WXFEEN22 WRITE Strobe Polarity DescriptionValue The WRITE strobe is WR (active High).1 The WRITE strobe is WRn (active Low).0 If both CS0n and CS1n are enabled (theCSCFG field in the EPIHB16CFG2register is 0x2 or 0x3), the programmed write strobe polarity is used for both CS0n and CS1n accesses. 0R/WWRHIGH21 READ Strobe Polarity DescriptionValue The READ strobe is RD (active High).1 The READ strobe is RDn (active Low).0 If both CS0n and CS1n are enabled (theCSCFG field in the EPIHB16CFG2register is 0x2 or 0x3), the programmed read strobe polarity is used for both CS0n and CS1n accesses. 0R/WRDHIGH20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved19:16 Maximum Wait This field defines the maximum number of external clocks to wait while an external FIFO ready signal is holding off a transaction (FFULL and FEMPTY). When this field is clear, the transaction is held off forever. Note: When theMODE field is configured to be 0x3 and theBLKEN bit is set in theEPICFGregister, enabling HB16 mode, this field defaults to 0xFF. 0x00R/WMAXWAIT15:8 495March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Write Wait States This field adds wait states to the data phase (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. DescriptionValue No wait states.0x0 1 wait state.0x1 2 wait states.0x2 3 wait states.0x3 This field is used in conjunction with theEPIBAUDregister. If both CS0n and CS1n are enabled (theCSCFG field in the EPIHB16CFG2register is 0x2 or 0x3), the same number of wait states is added to both CS0n and CS1n accesses. 0x0R/WWRWS7:6 Read Wait States This field adds wait states to the data phase (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. DescriptionValue No wait states.0x0 1 wait state.0x1 2 wait states.0x2 3 wait states.0x3 This field is used in conjunction with theEPIBAUDregister. If both CS0n and CS1n are enabled (theCSCFG field in the EPIHB16CFG2register is 0x2 or 0x3), the same number of wait states is added to both CS0n and CS1n accesses. 0x0R/WRDWS5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 Byte Select Configuration This bit enables byte select operation. DescriptionValue No Byte Selects Data is read and written as 16 bits. Enable Byte Selects Two EPI signals function as byte select signals to allow 8-bit transfers. See Table 9-6 on page 467 for details on which EPI signals are used. 0R/WBSEL2 March 19, 2011496 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Host Bus Sub-Mode This field determines which of three Host Bus 16 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 9-6 on page 467 for information on how this bit field affects the operation of the EPI signals. DescriptionValue ADMUX – AD[15:0] Data and Address are muxed. 0x0 ADNONMUX – D[15:0] Data and address are separate. This mode is not practical in HB16 mode for normal peripherals because there are generally not enough address bits available. 0x1 Continuous Read - D[15:0] This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OEn strobing. This mode is not practical in HB16 mode for normal SRAMs because there are generally not enough address bits available. 0x2 XFIFO – D[15:0] This mode adds XFIFO controls with sense of XFIFO full and XFIFO empty. This mode uses no address or ALE. 0x3 0x0R/WMODE1:0 497March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register6:EPIGeneral-PurposeConfiguration(EPIGPCFG),offset0x010 Important: The MODE field in theEPICFGregister determines which configuration register is accessed for offsets 0x010 and 0x014. To accessEPIGPCFG, theMODE field must be 0x0. The RD2CYC bit must be set at all times in General-Purpose mode to ensure proper operation. The General-Purpose configuration register is used to configure the control, data, and address pins. This mode can be used for custom interfaces with FPGAs, CPLDs, and for digital data acquisition and actuator control. Note that this register is reset when theMODE field in theEPICFGregister is changed. If another mode is selected and the General-purpose mode is selected again, the register the values must be reinitialized. This mode is designed for 3 general types of use: ■ Extremely high-speed clocked interfaces to FPGAs and CPLDs, with 3 sizes of data and optional address. Framing and clock-enable permit more optimized interfaces. ■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely controlled by the baud rate in theEPIBAUDregister (when used with the NBRFIFO and/or the WFIFO) or by rate of accesses from software or μDMA. ■ General custom interfaces of any speed. The configuration allows for choice of an output clock (free running or gated), a framing signal (with frame size), a ready input (to stretch transactions), read and write strobes, address of varying sizes, and data of varying sizes. Additionally, provisions are made for splitting address and data phases on the external interface. EPI General-Purpose Configuration (EPIGPCFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedRD2CYCWR2CYCreservedRWFRMCNTFRM50FRMPINRDYENreservedCLKGATECLKPIN ROROR/WR/WROR/WR/WR/WR/WR/WR/WR/WR/WROR/WR/WType 0000000000000000Reset 0123456789101112131415 DSIZEreservedASIZEreservedMAXWAIT R/WR/WROROR/WR/WROROR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Clock Pin DescriptionValue EPI0S31 functions as the EPI clock output.1 No clock output.0 The EPI clock is generated from theCOUNT0 field in theEPIBAUD register (as is the system clock which is divided down from it). 0R/WCLKPIN31 March 19, 2011498 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Clock Gated DescriptionValue The EPI clock is output only when there is data to write or read (current transaction); otherwise the EPI clock is held low. The EPI clock is free running.0 Note thatEPI0S27is an iRDY signal ifRDYEN is set.CLKGATEis ignored if CLKPIN is 0 or if theCOUNT0 field in theEPIBAUDregister is cleared. 0R/WCLKGATE30 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 Ready Enable DescriptionValue The external peripheral drives an iRDY signal into pinEPI0S27.1 The external peripheral does not drive an iRDY signal and is assumed to be ready always. The ready enable signal may only be used with a free-running EPI clock (CLKGATE=0). The external iRDY signal is sampled on the falling edge of the EPI clock. Setup and hold times must be met to ensure registration on the next falling EPI clock edge. This bit is ignored ifCLKPIN is 0 orCLKGATE is 1. 0R/WRDYEN28 Framing Pin DescriptionValue A framing signal is output onEPI0S30.1 No framing signal is output.0 Framing has no impact on data itself, but forms a context for the external peripheral. When used with a free-running EPI clock, the FRAME signal forms the valid signal. When used with a gated EPI clock, it is usually used to form a frame size. 0R/WFRMPIN27 50/50 Frame DescriptionValue The FRAME signal is output as 50/50 duty cycle using count (see FRMCNT). The FRAME signal is output as a single pulse, and then held low for the count. This bit is ignored ifFRMPIN is 0. 0R/WFRM5026 499March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Frame Count This field specifies the size of the frame in EPI clocks. The frame counter is used to determine the frame size. The count isFRMCNT+1. So, a FRMCNT of 0 forms a pure transaction valid signal (held high during transactions, low otherwise). A FRMCNT of 0 withFRM50 set inverts the FRAME signal on each transaction. AFRMCNT of 1 means the FRAME signal is inverted every other transaction; a value of 15 means every sixteenth transaction. If FRM50 is set, the frame is held high forFRMCNT+1 transactions, then held low for that many transactions, and so on. If FRM50 is clear, the frame is pulsed high for one EPI clock and then low forFRMCNT EPI clocks. This field is ignored ifFRMPIN is 0. 0x0R/WFRMCNT25:22 Read and Write DescriptionValue RD and WR strobes are asserted onEPI0S29 and EPI0S28. RD is asserted high on the rising edge of the EPI clock when a read is being performed. WR is asserted high on the rising edge of the EPI clock when a write is being performed RD and WR strobes are not output.0 This bit is forced to 1 whenRD2CYC and/or WR2CYC is 1. 0R/WRW21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved20 2-Cycle Writes DescriptionValue Writes are two EPI clock cycles long, with address on one EPI clock cycle (with the WR strobe asserted) and data written on the following EPI clock cycle (with WR strobe de-asserted). The next address (if any) is in the cycle following. Data is output on the same EPI clock cycle as the address.0 When this bit is set, then theRW bit is forced to be set. 0R/WWR2CYC19 2-Cycle Reads DescriptionValue Reads are two EPI clock cycles, with address on one EPI clock cycle (with the RD strobe asserted) and data captured on the following EPI clock cycle (with the RD strobe de-asserted). The next address (if any) is in the cycle following. Data is captured on the EPI clock cycle with READ strobe asserted. When this bit is set, then theRW bit is forced to be set. Caution – This bit must be set at all times in General-Purpose mode to ensure proper operation. 0R/WRD2CYC18 March 19, 2011500 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved17:16 Maximum Wait This field defines the maximum number of EPI clocks to wait while the iRDY signal (seeRDYEN) is holding off a transaction. If this field is 0, the transaction is held forever. If the maximum wait of 255 clocks (MAXWAIT=0xFF) is exceeded, an error interrupt occurs and the transaction is aborted/ignored. Note: When theMODE field is configured to be 0x0 and theBLKEN bit is set in theEPICFGregister , enabling General-Purpose mode, this field defaults to 0xFF. 0x00R/WMAXWAIT15:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:6 Address Bus Size This field defines the size of the address bus. The address can be up to 4-bits wide with a 24-bit data bus, up to 12-bits wide with a 16-bit data bus, and up to 20-bits wide with an 8-bit data bus. If the full address bus is not used, use the least significant address bits. Any unused address bits can be used as GPIOs by clearing theAFSEL bit for the corresponding GPIOs. Also, ifRDYEN is 1, then the address sizes are 1 smaller (3, 11, 19). The values are: DescriptionValue No address0x0 Up to 4 bits wide.0x1 Up to 12 bits wide. This size cannot be used with 24-bit data.0x2 Up to 20 bits wide. This size cannot be used with data sizes other than 8. 0x3 0x0R/WASIZE5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:2 Size of Data Bus This field defines the size of the data bus (starting atEPI0S0). Subsets of these numbers can be created by clearing theAFSEL bit for the corresponding GPIOs. Note that size 32 may not be used with clock, frame, address, or other control. The values are: DescriptionValue

8 Bits Wide (EPI0S0to EPI0S7)0x0

16 Bits Wide (EPI0S0to EPI0S15)0x1

24 Bits Wide (EPI0S0to EPI0S23)0x2

32 Bits Wide (EPI0S0to EPI0S31)

This size may not be used with an EPI clock. This value is normally used for acquisition input and actuator control as well as other general-purpose uses that require 32 bits per direction. 0x3 0x0R/WDSIZE1:0 501March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register7:EPIHost-Bus8Configuration2(EPIHB8CFG2),offset0x014 Important: The MODE field in theEPICFGregister determines which configuration register is accessed for offsets 0x010 and 0x014. To accessEPIHB8CFG2, theMODE field must be 0x2. This register is used to configure operation while in Host-Bus 8 mode. Note that this register is reset when theMODE field in theEPICFGregister is changed. If another mode is selected and the Host-Bus 8 mode is selected again, the values must be reinitialized. EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) Base 0x400D.0000 Offset 0x014 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedCSCFGCSBAUDreservedWORD ROROROROROROROROR/WR/WR/WROROROROR/WType 0000000000000000Reset 0123456789101112131415 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Word Access Mode By default, the EPI controller uses data bits [7:0] for Host-Bus 8 accesses. When using Word Access mode, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8]. WhenWORD is set, short and long variables can be used in C programs. DescriptionValue Word Access mode is disabled.0 Word Access mode is enabled.1 0R/WWORD31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved30:27 Chip Select Baud Rate DescriptionValue Same Baud Rate Both CS0n and CS1n use the baud rate for the external bus that is defined by theCOUNT0 field in theEPIBAUDregister. Different Baud Rates CS0n uses the baud rate for the external bus that is defined by the COUNT0 field in theEPIBAUDregister. CS1n uses the baud rate defined by theCOUNT1 field in theEPIBAUDregister. 0R/WCSBAUD26 March 19, 2011502 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Chip Select Configuration DescriptionValue ALE Configuration EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the address and data are muxed (HB8MODE field in theEPIHB8CFGregister is 0x0). The ALE signal is used by an external latch to hold the address through the bus cycle. 0x0 CSn Configuration EPI0S30is used as a Chip Select (CSn). When using this mode, the address and data are generally not muxed (HB8MODEfield in theEPIHB8CFGregister is 0x1). However, if address and data muxing is needed, the WR signal (EPI0S29) and the RD signal (EPI0S28) can be used to latch the address when CSn is low. 0x1 Dual CSn Configuration EPI0S30 is used as CS0n andEPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral. 0x2 ALE with Dual CSn Configuration EPI0S30 is used as address latch (ALE),EPI0S27 is used as CS1n, andEPI0S26 is used as CS0n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. 0x3 0x0R/WCSCFG25:24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved23:0 503March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register8:EPIHost-Bus16Configuration2(EPIHB16CFG2),offset0x014 Important: The MODE field in theEPICFGregister determines which configuration register is accessed for offsets 0x010 and 0x014. To accessEPIHB16CFG2, theMODE field must be 0x3. This register is used to configure operation while in Host-Bus 16 mode. Note that this register is reset when theMODE field in theEPICFGregister is changed. If another mode is selected and the Host-Bus 16 mode is selected again, the values must be reinitialized. EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Base 0x400D.0000 Offset 0x014 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedCSCFGCSBAUDreservedWORD ROROROROROROROROR/WR/WR/WROROROROR/WType 0000000000000000Reset 0123456789101112131415 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Word Access Mode By default, the EPI controller uses data bits [15:0] for Host-Bus 16 accesses. When using Word Access mode, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:16]. WhenWORD is set, long variables can be used in C programs. DescriptionValue Word Access mode is disabled.0 Word Access mode is enabled.1 0R/WWORD31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved30:27 Chip Select Baud Rate DescriptionValue Same Baud Rate Both CS0n and CS1n use the baud rate for the external bus that is defined by theCOUNT0 field in theEPIBAUDregister. Different Baud Rates CS0n uses the baud rate for the external bus that is defined by the COUNT0 field in theEPIBAUDregister. CS1n uses the baud rate defined by theCOUNT1 field in theEPIBAUDregister. 0R/WCSBAUD26 March 19, 2011504 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Chip Select Configuration This field controls the chip select options, including an ALE format, a single chip select, two chip selects, and an ALE combined with two chip selects. DescriptionValue ALE Configuration EPI0S30 is used as an address latch (ALE). When using this mode, the address and data should be muxed (HB16MODEfield in theEPIHB16CFGregister should be configured to 0x0). If needed, the address can be latched by external logic. 0x0 CSn Configuration EPI0S30is used as a Chip Select (CSn). When using this mode, the address and data should not be muxed (HB816MODEfield in theEPIHB16CFGregister should be configured to 0x1). In this mode, the WR signal (EPI0S29) and the RD signal (EPI0S28) are used to latch the address when CSn is low. 0x1 Dual CSn Configuration EPI0S30 is used as CS0n andEPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral. 0x2 ALE with Dual CSn Configuration EPI0S30 is used as address latch (ALE),EPI0S27 is used as CS1n, andEPI0S26 is used as CS0n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. 0x3 0x0R/WCSCFG25:24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved23:0 505March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register9:EPIGeneral-PurposeConfiguration2(EPIGPCFG2),offset0x014 Important: The MODE field in theEPICFGregister determines which configuration register is accessed for offsets 0x010 and 0x014. To accessEPIGPCFG2, theMODE field must be 0x0. This register is used to configure operation while in General-Purpose mode. Note that this register is reset when theMODE field in theEPICFGregister is changed. If another mode is selected and the General-Purpose mode is selected again, the values must be reinitialized. EPI General-Purpose Configuration 2 (EPIGPCFG2) Base 0x400D.0000 Offset 0x014 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reservedWORD ROROROROROROROROROROROROROROROR/WType 0000000000000000Reset 0123456789101112131415 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Word Access Mode By default, the EPI controller uses data bits [7:0] when theDSIZE field in theEPIGPCFGregister is 0x0; data bits [15:0] when theDSIZE field is 0x1; data bits [23:0] when theDSIZE field is 0x2; and data bits [31:0] when theDSIZE field is 0x3. When using Word Access mode, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] forDSIZE=0x0 and bits [31:16] forDSIZE=0x1. For DSIZE=0x2 or 0x3, this bit must be clear. DescriptionValue Word Access mode is disabled.0 Word Access mode is enabled.1 0x0R/WWORD31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000ROreserved30:0 March 19, 2011506 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register10:EPIAddressMap(EPIADDRMAP),offset0x01C This register enables address mapping. The EPI controller can directly address memory and peripherals. In addition, the EPI controller supports address mapping to allow indirect accesses in the External RAM and External Peripheral areas. If the external device is a peripheral, including a FIFO or a directly addressable device, theEPSZ and EPADR bit fields should be configured for the address space. If the external device is SDRAM, SRAM, or NOR Flash memory, theERADR and ERSZ bit fields should be configured for the address space. If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in theEPIHBnCFG2register), both chip selects can share the peripheral or the memory space, or one chip select can use the peripheral space and the other can use the memory space. If theEPADR field is not 0x0 and the ERADR field is 0x0, then the address specified byEPADR is used for both chip selects, with CS0n being asserted when the MSB of the address range is 0 and CS1n being asserted when the MSB of the address range is 1. If theERADR field is not 0x0 and theEPADR field is 0x0, then the address specified byERADR is used for both chip selects, with the MSB performing the same delineation. If both theEPADR and theERADR are not 0x0, then CS0n is asserted for the address range defined by EPADR and CS1n is asserted for the address range defined byERADR. EPI Address Map (EPIADDRMAP) Base 0x400D.0000 Offset 0x01C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ERADRERSZEPADREPSZreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 External Peripheral Size This field selects the size of the external peripheral. If the size of the external peripheral is larger, a bus fault occurs. If the size of the external peripheral is smaller, it wraps (upper address bits unused). Note: When not using byte selects in Host-Bus 16, data is accessed on 2-byte boundaries. As a result, the available address space is double the amount shown below. DescriptionValue 256 bytes; lower address range: 0x00 to 0xFF0x0

64 KB; lower address range: 0x0000 to 0xFFFF0x1

16 MB; lower address range: 0x00.0000 to 0xFF.FFFF0x2 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF0x3 0x0R/WEPSZ7:6 507March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field External Peripheral Address This field selects address mapping for the external peripheral area. DescriptionValue Not mapped0x0 At 0xA000.00000x1 At 0xC000.00000x2 reserved0x3 0x0R/WEPADR5:4 External RAM Size This field selects the size of mapped RAM. If the size of the external memory is larger, a bus fault occurs. If the size of the external memory is smaller, it wraps (upper address bits unused): DescriptionValue 256 bytes; lower address range: 0x00 to 0xFF0x0 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF0x2 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF0x3 0x0R/WERSZ3:2 External RAM Address Selects address mapping for external RAM area: DescriptionValue Not mapped0x0 At 0x6000.00000x1 At 0x8000.00000x2 reserved0x3 0x0R/WERADR1:0 March 19, 2011508 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register11:EPIReadSize0(EPIRSIZE0),offset0x020 Register12:EPIReadSize1(EPIRSIZE1),offset0x030 This register selects the size of transactions when performing non-blocking reads with the EPIRPSTDnregisters. This size affects how the external address is incremented. The SIZE field must match the external data width as configured in theEPIHBnCFGor EPIGPCFG register if theWORD bit is clear in theEPIHBnCFG2or EPIGPCFG2register. If theWORD bit is set, the SIZE field must be greater than or equal to the external data width. SDRAM mode uses a 16-bit data interface. IfSIZE is 0x1, data is returned on the least significant bits (D[7:0]), and the remaining bits D[31:8] are all zeros, therefore the data on bits D[15:8] is lost. If SIZE is 0x2, data is returned on the least significant bits (D[15:0]), and the remaining bits D[31:16] are all zeros. Note that changing this register while a read is active has an unpredictable effect. EPI Read Size 0 (EPIRSIZE0) Base 0x400D.0000 Offset 0x020 Type R/W, reset 0x0000.0003 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SIZEreserved R/WR/WROROROROROROROROROROROROROROType 1100000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:2 Current Size DescriptionValue reserved0x0 Byte (8 bits)0x1 Half-word (16 bits)0x2 Word (32 bits)0x3 0x3R/WSIZE1:0 509March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register13:EPIReadAddress0(EPIRADDR0),offset0x024 Register14:EPIReadAddress1(EPIRADDR1),offset0x034 This register holds the current address value. When performing non-blocking reads via the EPIRPSTDnregisters, this register’s value forms the address (when used by the mode). That is, when anEPIRPSTDnregister is written with a non-0 value, this register is used as the first address. After each read, it is incremented by the size specified by the correspondingEPIRSIZEnregister. Thus at the end of a read, this register contains the next address for the next read. For example, if the last read was 0x20, and the size is word, then the register contains 0x24. When a non-blocking read is cancelled, this register contains the next address that would have been read had it not been cancelled. For example, if reading by bytes and 0x103 had been read but not 0x104, this register contains 0x104. In this manner, the system can determine the number of values in the NBRFIFO to drain. Note that changing this register while a read is active has an unpredictable effect due to race condition. EPI Read Address 0 (EPIRADDR0) Base 0x400D.0000 Offset 0x024 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 ADDRreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROType 0000000000000000Reset 0123456789101112131415 ADDR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:29 Current Address Next address to read. 0x000.0000R/WADDR28:0 March 19, 2011510 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register15:EPINon-BlockingReadData0(EPIRPSTD0),offset0x028 Register16:EPINon-BlockingReadData1(EPIRPSTD1),offset0x038 This register sets up a non-blocking read via the external interface. A non-blocking read is started by writing to this register with the count (other than 0). Clearing this register terminates an active non-blocking read as well as cancelling any that are pending. This register should always be cleared before writing a value other than 0; failure to do so can cause improper operation. Note that both NBR channels can be enabled at the same time, but NBR channel 0 has the highest priority and channel 1 does not start until channel 0 is finished. The first address is based on the correspondingEPIRADDRnregister. The address register is incremented by the size specified by theEPIRSIZEnregister after each read. If the size is less than a word, only the least significant bits of data are filled into the NBRFIFO; the most significant bits are cleared. Note that all three registers may be written using one STM instruction, such as with a structure copy in C/C++. The data may be read from theEPIREADFIFOregister after the read cycle is completed. The interrupt mechanism is normally used to trigger the FIFO reads via ISR or μDMA. If the countdown has not reached 0 and the NBRFIFO is full, the external interface waits until a NBRFIFO entry becomes available to continue. Note: if a blocking read or write is performed through the address mapped area (at 0x6000.0000 through 0xDFFF.FFFF), any current non-blocking read is paused (at the next safe boundary), and the blocking request is inserted. After completion of any blocking reads or writes, the non-blocking reads continue from where they were paused. The other way to read data is via the address mapped locations (see theEPIADDRMAPregister), but this method is blocking (core or μDMA waits until result is returned). To cancel a non-blocking read, clear this register. To make sure that all values read are drained from the NBRFIFO, theEPISTATregister must be consulted to be certain that bitsNBRBUSY and ACTIVE are cleared. One of these registers should not be cleared until either the otherEPIRPSTDn register becomes active or the external interface is not busy. At that point, the corresponding EPIRADDRnregister indicates how many values were read. EPI Non-Blocking Read Data 0 (EPIRPSTD0) Base 0x400D.0000 Offset 0x028 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 POSTCNTreserved R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:13 511March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Post Count A write of a non-zero value starts a read operation for that count. Note that it is the software's responsibility to handle address wraparound. Reading this register provides the current count. A write of 0 cancels a non-blocking read (whether active now or pending). Prior to writing a non-zero value, this register must first be cleared. 0x000R/WPOSTCNT12:0 March 19, 2011512 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register17:EPIStatus(EPISTAT),offset0x060 This register indicates which non-blocking read register is currently active; it also indicates whether the external interface is busy performing a write or non-blocking read (it cannot be performing a blocking read, as the bus would be blocked and as a result, this register could not be accessed). This register is useful to determining which non-blocking read register is active when both are loaded with values and when implementing sequencing or sharing. This register is also useful when canceling non-blocking reads, as it shows how many values were read by the canceled side. EPI Status (EPISTAT) Base 0x400D.0000 Offset 0x060 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ACTIVEreservedNBRBUSYWBUSYINITSEQXFEMPTYXFFULLCELOWreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:10 Clock Enable Low This bit provides information on the clock status when in general-purpose mode and theRDYEN bit is set. DescriptionValue The external device is gating the clock (iRDY is low). Attempts to read or write in this situation are stalled until the clock is enabled or the counter times out as specified by the MAXWAIT field. The external device is not gating the clock.0 0ROCELOW9 External FIFO Full This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode with theXFFEN bit set in theEPIHBnCFG register. TheEPI0S26 signal reflects the status of this bit. DescriptionValue The XFIFO is signaling as full (the FIFO full signal is high). Attempts to write in this case are stalled until the XFIFO full signal goes low or the counter times out as specified by the MAXWAIT field. The external device is not gating the clock.0 0ROXFFULL8 513March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field External FIFO Empty This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode with theXFEEN bit set in theEPIHBnCFG register. TheEPI0S27 signal reflects the status of this bit. DescriptionValue The XFIFO is signaling as empty (the FIFO empty signal is high). Attempts to read in this case are stalled until the XFIFO empty signal goes low or the counter times out as specified by the MAXWAIT field. The external device is not gating the clock.0 0ROXFEMPTY7 Initialization Sequence DescriptionValue The SDRAM interface is running through the wakeup period (greater than 100 μs). If an attempt is made to read or write the SDRAM during this period, the access is held off until the wakeup period is complete. The SDRAM interface is not in the wakeup period.0 0ROINITSEQ6 Write Busy DescriptionValue The external interface is performing a write.1 The external interface is not performing a write.0 0ROWBUSY5 Non-Blocking Read Busy DescriptionValue The external interface is performing a non-blocking read, or if the non-blocking read is paused due to a write. The external interface is not performing a non-blocking read.0 0RONBRBUSY4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:1 Register Active DescriptionValue The EPIRPSTD1register is active.1 If NBRBUSY is set, theEPIRPSTD0register is active. If theNBRBUSY bit is clear, then neitherEPIRPSTDxregister is active. 0ROACTIVE0 March 19, 2011514 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register18:EPIReadFIFOCount(EPIRFIFOCNT),offset0x06C This register returns the number of values in the NBRFIFO (the data in the NBRFIFO can be read via theEPIREADFIFOregister). A race is possible, but that only means that more values may come in after this register has been read. EPI Read FIFO Count (EPIRFIFOCNT) Base 0x400D.0000 Offset 0x06C Type RO, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 COUNTreserved ROROROROROROROROROROROROROROROROType ---0000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 FIFO Count Number of filled entries in the NBRFIFO. -ROCOUNT2:0 515March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register19:EPIReadFIFO(EPIREADFIFO),offset0x070 Register20:EPIReadFIFOAlias1(EPIREADFIFO1),offset0x074 Register21:EPIReadFIFOAlias2(EPIREADFIFO2),offset0x078 Register22:EPIReadFIFOAlias3(EPIREADFIFO3),offset0x07C Register23:EPIReadFIFOAlias4(EPIREADFIFO4),offset0x080 Register24:EPIReadFIFOAlias5(EPIREADFIFO5),offset0x084 Register25:EPIReadFIFOAlias6(EPIREADFIFO6),offset0x088 Register26:EPIReadFIFOAlias7(EPIREADFIFO7),offset0x08C Important: This register is read-sensitive. See the register description for details. This register returns the contents of the NBRFIFO or 0 if the NBRFIFO is empty. Each read returns the data that is at the top of the NBRFIFO, and then empties that value from the NBRFIFO. The alias registers can be used with the LDMIA instruction for more efficient operation (for up to 8 registers). SeeCortex™-M3 Instruction Set Technical User's Manual for more information on the LDMIA instruction. EPI Read FIFO (EPIREADFIFO) Base 0x400D.0000 Offset 0x070 Type RO, reset - 16171819202122232425262728293031 DATA ROROROROROROROROROROROROROROROROType 0123456789101112131415 DATA ROROROROROROROROROROROROROROROROType DescriptionResetTypeNameBit/Field Reads Data This field contains the data that is at the top of the NBRFIFO. After being read, the NBRFIFO entry is removed. -RODATA31:0 March 19, 2011516 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register27:EPIFIFOLevelSelects(EPIFIFOLVL),offset0x200 This register allows selection of the FIFO levels which trigger an interrupt to the interrupt controller or, more efficiently, a DMA request to the μDMA. The NBRFIFO select triggers on fullness such that it triggers on match or above (more full). The WFIFO triggers on emptiness such that it triggers on match or below (less entries). It should be noted that the FIFO triggers are not identical to other such FIFOs in Stellaris peripherals. In particular, empty and full triggers are provided to avoid wait states when using blocking operations. The settings in this register are only meaningful if the μDMA is active or the interrupt is enabled. Additionally, this register allows protection against writes stalling and notification of performing blocking reads which stall for extra time due to preceding writes. The two functions behave in a non-orthogonal way because read and write are not orthogonal. The write error bit configures the system such that an attempted write to an already full WFIFO abandons the write and signals an error interrupt to prevent accidental latencies due to stalling writes. The read error bit configures the system such that after a read has been stalled due to any preceding writes in the WFIFO, the error interrupt is generated. Note that the excess stall is not prevented, but an interrupt is generated after the fact to notify that it has happened. EPI FIFO Level Selects (EPIFIFOLVL) Base 0x400D.0000 Offset 0x200 Type R/W, reset 0x0000.0033 16171819202122232425262728293031 RSERRWFERRreserved R/WR/WROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RDFIFOreservedWRFIFOreserved R/WR/WR/WROR/WR/WR/WROROROROROROROROROType 1100110000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:18 Write Full Error DescriptionValue This bit enables the Write Full error interrupt (WTFULLin the EPIICregister) to be generated when a write is attempted and the WFIFO is full. The write stalls until a WFIFO entry becomes available. The Write Full error interrupt is disabled. Writes are stalled when the WFIFO is full until a space becomes available but an error is not generated. Note that the Cortex-M3 write buffer may hide that stall if no other memory transactions are attempted during that time. 0R/WWFERR17 517March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Read Stall Error DescriptionValue This bit enables the Read Stalled error interrupt (RSTALLin the EPIICregister) to be generated when a read is attempted and the WFIFO is not empty. The read is still stalled during the time the WFIFO drains, but this error notifies the application that this excess delay has occurred. The Read Stalled error interrupt is disabled. Reads behave as normal and are stalled until any preceding writes have completed and the read has returned a result. Note that the configuration of this bit has no effect on non-blocking reads. 0R/WRSERR16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved15:7 Write FIFO This field configures the trigger point for the WFIFO. DescriptionValue Trigger when there are 1 to 4 spaces available in the WFIFO.0x0 reserved0x1 Trigger when there are 1 to 3 spaces available in the WFIFO.0x2 Trigger when there are 1 to 2 spaces available in the WFIFO.0x3 Trigger when there is 1 space available in the WFIFO.0x4 reserved0x5-0x7 0x3R/WWRFIFO6:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 Read FIFO This field configures the trigger point for the NBRFIFO. DescriptionValue reserved0x0 Trigger when there are 1 or more entries in the NBRFIFO.0x1 Trigger when there are 2 or more entries in the NBRFIFO.0x2 Trigger when there are 4 or more entries in the NBRFIFO.0x3 Trigger when there are 6 or more entries in the NBRFIFO.0x4 Trigger when there are 7 or more entries in the NBRFIFO.0x5 Trigger when there are 8 entries in the NBRFIFO.0x6 reserved0x7 0x3R/WRDFIFO2:0 March 19, 2011518 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register28:EPIWriteFIFOCount(EPIWFIFOCNT),offset0x204 This register contains the number of slots currently available in the WFIFO. This register may be used for polled writes to avoid stalling and for blocking reads to avoid excess stalling (due to undrained writes). An example use for writes may be: for (idx = 0; idx < cnt; idx++) { while (EPIWFIFOCNT == 0) ; *ext_ram = *mydata++; The above code ensures that writes to the address mapped location do not occur unless the WFIFO has room. Although polling makes the code wait (spinning in the loop), it does not prevent interrupts being serviced due to bus stalling. EPI Write FIFO Count (EPIWFIFOCNT) Base 0x400D.0000 Offset 0x204 Type RO, reset 0x0000.0004 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 WTAVreserved ROROROROROROROROROROROROROROROROType 0010000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 Available Write Transactions The number of write transactions available in the WFIFO. When clear, a write is stalled waiting for a slot to become free (from a preceding write completing). 0x4ROWTAV2:0 519March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register29:EPIInterruptMask(EPIIM),offset0x210 This register is the interrupt mask set or clear register. For each interrupt source (read, write, and error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller; a mask value of 0 prevents the interrupt source from triggering an interrupt. Note that interrupt masking has no effect on μDMA, which operates off the raw source of the read and write interrupts. EPI Interrupt Mask (EPIIM) Base 0x400D.0000 Offset 0x210 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ERRIMRDIMWRIMreserved R/WR/WR/WROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 Write Interrupt Mask DescriptionValue WRRIS in theEPIRISregister is not masked and can trigger an interrupt to the interrupt controller. WRRIS in theEPIRISregister is masked and does not cause an interrupt. 0R/WWRIM2 Read Interrupt Mask DescriptionValue RDRIS in theEPIRISregister is not masked and can trigger an interrupt to the interrupt controller. RDRIS in theEPIRISregister is masked and does not cause an interrupt. 0R/WRDIM1 Error Interrupt Mask DescriptionValue ERRIS in theEPIRISregister is not masked and can trigger an interrupt to the interrupt controller. ERRIS in theEPIRISregister is masked and does not cause an interrupt. 0R/WERRIM0 March 19, 2011520 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register30:EPIRawInterruptStatus(EPIRIS),offset0x214 This register is the raw interrupt status register. On a read, it gives the current state of each interrupt source. A write has no effect. Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by EPIFIFOLVL. Raw status for error is held until the error is cleared by writing to theEPIICregister. EPI Raw Interrupt Status (EPIRIS) Base 0x400D.0000 Offset 0x214 Type RO, reset 0x0000.0004 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ERRRISRDRISWRRISreserved ROROROROROROROROROROROROROROROROType 0010000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 Write Raw Interrupt Status DescriptionValue The number of available entries in the WFIFO is within the range specified by the trigger level (theWRFIFO field in the EPIFIFOLVLregister). The number of available entries in the WFIFO is above the range specified by the trigger level. This bit is cleared when the level in the WFIFO is above the trigger point programmed by theWRFIFO field. 1ROWRRIS2 Read Raw Interrupt Status DescriptionValue The number of valid entries in the NBRFIFO is within the range specified by the trigger level (theRDFIFO field in the EPIFIFOLVLregister). The number of valid entries in the NBRFIFO is below the range specified by the trigger level. This bit is cleared when the level in the NBRFIFO is below the trigger point programmed by theRDFIFO field. 0RORDRIS1 521March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field Error Raw Interrupt Status The error interrupt occurs in the following situations: ■ WFIFO Full. For a full WFIFO to generate an error interrupt, the WFERR bit in theEPIFIFOLVLregister must be set. ■ Read Stalled. For a stalled read to generate an error interrupt, the RSERR bit in theEPIFIFOLVLregister must be set. ■ Timeout. If the MAXWAIT field in theEPIGPCFGregister is configured to a value other than 0, a timeout error occurs when iRDY or XFIFO not-ready signals hold a transaction for more than the count in theMAXWAIT field. DescriptionValue A WFIFO Full, a Read Stalled, or a Timeout error has occurred.1 An error has not occurred.0 To determine which error occurred, read the status of theEPIError InterruptStatusandClear(EPIEISC) register. This bit is cleared by writing a 1 to the bit in theEPIEISCregister that caused the interrupt. 0ROERRRIS0 March 19, 2011522 Texas Instruments-Advance Information External Peripheral Interface (EPI)

Register31:EPIMaskedInterruptStatus(EPIMIS),offset0x218 This register is the masked interrupt status register. On read, it gives the current state of each interrupt source (read, write, and error) after being masked via theEPIIMregister. A write has no effect. The values returned are the ANDing of theEPIIMand EPIRISregisters. If a bit is set in this register, the interrupt is sent to the interrupt controller. EPI Masked Interrupt Status (EPIMIS) Base 0x400D.0000 Offset 0x218 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ERRMISRDMISWRMISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 Write Masked Interrupt Status DescriptionValue The number of available entries in the WFIFO is within the range specified by the trigger level (theWRFIFO field in the EPIFIFOLVLregister) and theWRIM bit in theEPIIMregister is set, triggering an interrupt to the interrupt controller. The number of available entries in the WFIFO is above the range specified by the trigger level or the interrupt is masked. 0ROWRMIS2 Read Masked Interrupt Status DescriptionValue The number of valid entries in the NBRFIFO is within the range specified by the trigger level (theRDFIFO field in the EPIFIFOLVLregister) and theRDIM bit in theEPIIMregister is set, triggering an interrupt to the interrupt controller. The number of valid entries in the NBRFIFO is below the range specified by the trigger level or the interrupt is masked. 0RORDMIS1 Error Masked Interrupt Status DescriptionValue A WFIFO Full, a Read Stalled, or a Timeout error has occurred and theERIM bit in theEPIIMregister is set, triggering an interrupt to the interrupt controller. An error has not occurred or the interrupt is masked.0 0ROERRMIS0 523March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register32:EPIErrorInterruptStatusandClear(EPIEISC),offset0x21C This register is used to clear a pending error interrupt. If any of these bits are set, theERRRIS bit in theEPIRISregister is set, and an EPI controller error is sent to the interrupt controller if theERIM bit in theEPIIMregister is set. Clearing any defined bit has no effect; setting a bit clears the error source and the raw error returns to 0. Note that writing to this register and reading back immediately (pipelined by the processor) returns the old register contents. One cycle is needed between write and read. EPI Error Interrupt Status and Clear (EPIEISC) Base 0x400D.0000 Offset 0x21C Type R/W1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TOUTRSTALLWTFULLreserved R/W1CR/W1CR/W1CROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 Write FIFO Full Error DescriptionValue The WFERR bit is enabled and a write is stalled due to the WFIFO being full. The WFERR bit is not enabled or no writes are stalled.0 Writing a 1 to this bit clears it and theWFERR bit in theEPIFIFOLVL register. 0R/W1CWTFULL2 Read Stalled Error DescriptionValue The RSERR bit is enabled and a pending read is stalled due to writes in the WFIFO. The RSERR bit is not enabled pr no pending reads are stalled.0 Writing a 1 to this bit clears it and theRSERR bit in theEPIFIFOLVL register. 0R/W1CRSTALL1 March 19, 2011524 Texas Instruments-Advance Information External Peripheral Interface (EPI)

DescriptionResetTypeNameBit/Field Timeout Error This bit is the timeout error source. The timeout error occurs when the iRDY or XFIFO not-ready signals hold a transaction for more than the count in theMAXWAIT field (when not 0). DescriptionValue A timeout error has occurred.1 No timeout error has occurred.0 Writing a 1 to bit this clears it. 0R/W1CTOUT0 525March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

10 General-PurposeTimers

Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger μDMA transfers. In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see 121) and the PWM timer in the PWM module (see “PWM Timer” on page 1119). The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional options: ■ Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes – 16-bit PWM mode with software-programmable output inversion of the PWM signal ■ Count up or down ■ Eight Capture Compare PWM pins (CCP) ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ ADC event trigger ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt March 19, 2011526 Texas Instruments-Advance Information General-Purpose Timers

10.1 BlockDiagram

In the block diagram, the specific Capture Compare PWM (CCP) pins available depend on the Stellaris device. See Table 10-1 on page 527 for the available CCP pins and their timer assignments. Figure10-1.GPTMModuleBlockDiagram Clock / Edge Detect R TC Divider Clock / Edge Detect

32 KHz or

0x0000 (Down Counter Modes) 0 xFFFF (Up Counter Modes) 0x0000 (Down Counter Modes) 0 xFFFF (Up Counter Modes) En En Interrupt / Config GPTMCFG GPTMRIS GPTMICR GPTMMIS GPTMIMR GPTMCTL GPTMT A V GPTMTBV T imer A Free -Running V alue T imer B Free -Running V alue T imer A Control GPTMT APMR GPTMT AILR GPTMT AMA TCHR GPTMT APR GPTMT AMR T imer B Control GPTMTBPMR GPTMTBILR GPTMTBMA TCHR GPTMTBPR GPTMTBMR Table10-1.AvailableCCPPins OddCCPPinEvenCCPPin16-BitUp/DownCounterTimer -CCP0TimerATimer 0 CCP1-TimerB -CCP2TimerATimer 1 CCP3-TimerB -CCP4TimerATimer 2 CCP5-TimerB -CCP6TimerATimer 3 CCP7-TimerB

10.2 SignalDescription

Table 10-2 on page 528 and Table 10-3 on page 529 list the external signals of the GP Timer module and describe the function of each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these GP Timer signals. TheAFSEL bit in the GPIOAlternateFunctionSelect(GPIOAFSEL) register (page 421) should be set to choose the GP Timer function. The number in parentheses is the encoding that must be programmed into 527March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

the PMCn field in theGPIOPortControl(GPIOPCTL) register (page 439) to assign the GP Timer signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 397. Table10-2.SignalsforGeneral-PurposeTimers(100LQFP) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Capture/Compare/PWM 0.TTLI/OPD3 (4) PC7 (4) PC6 (6) PJ2 (9) PF4 (1) PJ7 (10) PB0 (1) PB2 (5) PB5 (4) PD4 (1) CCP0 Capture/Compare/PWM 1.TTLI/OPC5 (1) PC4 (9) PA6 (2) PJ6 (10) PB1 (4) PB6 (1) PE3 (1) PD7 (3) 100 CCP1 Capture/Compare/PWM 2.TTLI/OPE4 (6) PD1 (10) PC4 (5) PF5 (1) PJ5 (10) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) CCP2 Capture/Compare/PWM 3.TTLI/OPE4 (1) PC6 (1) PC5 (5) PA7 (7) PF1 (10) PB2 (4) PE0 (3) PD4 (2) CCP3 Capture/Compare/PWM 4.TTLI/OPC7 (1) PC4 (6) PA7 (2) PJ4 (10) PE2 (1) PD5 (2) CCP4 Capture/Compare/PWM 5.TTLI/OPE5 (1) PD2 (4) PC4 (1) PG7 (8) PB6 (6) PB5 (2) CCP5 March 19, 2011528 Texas Instruments-Advance Information General-Purpose Timers

Table10-2.SignalsforGeneral-PurposeTimers(100LQFP) (continued) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Capture/Compare/PWM 6.TTLI/OPD0 (6) PD2 (2) PJ3 (10) PE1 (5) PH0 (1) PB5 (3) CCP6 Capture/Compare/PWM 7.TTLI/OPD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) CCP7 a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table10-3.SignalsforGeneral-PurposeTimers(108BGA) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Capture/Compare/PWM 0.TTLI/OPD3 (4) PC7 (4) PC6 (6) PJ2 (9) PF4 (1) PJ7 (10) PB0 (1) PB2 (5) PB5 (4) PD4 (1) L12 E12 A11 CCP0 Capture/Compare/PWM 1.TTLI/OPC5 (1) PC4 (9) PA6 (2) PJ6 (10) PB1 (4) PB6 (1) PE3 (1) PD7 (3) L10 D12 CCP1 Capture/Compare/PWM 2.TTLI/OPE4 (6) PD1 (10) PC4 (5) PF5 (1) PJ5 (10) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) K12 D12 A12 CCP2 Capture/Compare/PWM 3.TTLI/OPE4 (1) PC6 (1) PC5 (5) PA7 (7) PF1 (10) PB2 (4) PE0 (3) PD4 (2) H12 A11 B11 CCP3 529March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Table10-3.SignalsforGeneral-PurposeTimers(108BGA) (continued) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Capture/Compare/PWM 4.TTLI/OPC7 (1) PC4 (6) PA7 (2) PJ4 (10) PE2 (1) PD5 (2) K11 CCP4 Capture/Compare/PWM 5.TTLI/OPE5 (1) PD2 (4) PC4 (1) PG7 (8) PB6 (6) PB5 (2) C10 CCP5 Capture/Compare/PWM 6.TTLI/OPD0 (6) PD2 (2) PJ3 (10) PE1 (5) PH0 (1) PB5 (3) M10 A12 CCP6 Capture/Compare/PWM 7.TTLI/OPD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) CCP7 a. The TTL designation indicates the pin has TTL-compatible voltage levels.

10.3 FunctionalDescription

The main components of each GPTM block are two free-running up/down counters (referred to as Timer A and Timer B), two match registers, two prescaler match registers, two shadow registers, and two load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Timer A and Timer B can be used individually, in which case they have a 16-bit counting range. In addition, Timer A and Timer B can be concatenated to provide a 32-bit counting range. Note that the prescaler can only be used when the timers are used individually. The available modes for each GPTM block are shown in Table 10-4 on page 530. Note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. Table10-4.General-PurposeTimerCapabilities PrescalerSizeaCounterSizeCountDirectionTimerUseMode 8-bit16-bitUp or DownIndividual One-shot -32-bitUp or DownConcatenated 8-bit16-bitUp or DownIndividual Periodic -32-bitUp or DownConcatenated -32-bitUpConcatenatedRTC 8-bit16-bitDownIndividualEdge Count -16-bitDownIndividualEdge Time March 19, 2011530 Texas Instruments-Advance Information General-Purpose Timers

Table10-4.General-PurposeTimerCapabilities (continued) PrescalerSizeaCounterSizeCountDirectionTimerUseMode -16-bitDownIndividualPWM a. The prescaler is only available when the timers are used individually Software configures the GPTM using theGPTMConfiguration(GPTMCFG) register (see page 542), the GPTMTimerAMode(GPTMTAMR) register (see page 543), and theGPTMTimerBMode (GPTMTBMR)register (see page 545). When in one of the concatentated modes, Timer A and Timer B can only operate in one mode. However, when configured in an individual mode, Timer A and Timer B can be independently configured in any combination of the individual modes.

10.3.1 GPTMResetConditions

After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all 1s, along with their corresponding load registers: theGPTMTimerAIntervalLoad(GPTMTAILR) register (see page 560) and theGPTMTimerBIntervalLoad(GPTMTBILR) register (see page 561) and shadow registers: theGPTMTimerAValue(GPTMTAV) register (see page 570) and theGPTM TimerBValue(GPTMTBV) register (see page 571). The prescale counters are initialized to 0x00: the GPTMTimerAPrescale(GPTMTAPR) register (see page 564) and theGPTMTimerBPrescale (GPTMTBPR)register (see page 565).

10.3.2 TimerModes

This section describes the operation of the various timer modes. When using Timer A and Timer B in concatenated mode, only the Timer A control and status bits must be used; there is no need to use Timer B control and status bits. The GPTM is placed into individual mode by writing a value of 0x4 to theGPTMConfiguration(GPTMCFG) register (see page 542). In the following sections, the variable "n" is used in bit field and register names to imply either a Timer A fun m,kction or a Timer B function. The prescaler is only available in the 16-bit one-shot, periodic, and input edge count timer mode. Note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count mode is the value in theGPTMTimernMatch(GPTMTnMATCH) and the optionalGPTMTimernPrescaleMatch(GPTMTnPMR) registers.

10.3.2.1 One-Shot/PeriodicTimerMode

The selection of one-shot or periodic mode is determined by the value written to theTnMR field of the GPTMTimernMode(GPTMTnMR) register (see page 543). The timer is configured to count up or down using theTnCDIR bit in theGPTMTnMRregister. When software sets theTnEN bit in theGPTMControl(GPTMCTL) register (see page 547), the timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if theTnWOT bit is set in theGPTMTnMRregister, once theTnEN bit is set, the timer waits for a trigger to begin counting (see the section called “Wait-for-Trigger Mode” on page 532). When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start value from theGPTMTnILRand theGPTMTnPRregisters on the next cycle. When the timer is counting up and it reaches the timeout event (the value in theGPTMTnILRand theGPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears theTnEN bit in theGPTMCTLregister. If configured as a periodic timer, the timer starts counting again on the next cycle. In periodic, snap-shot mode (TnSNAPSbit in theGPTMTnMR register is set), the actual free-running value of the timer at the time-out event is loaded into the 531March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

GPTMTnRregister. In this manner, software can determine the time elapsed from the interrupt assertion to the ISR entry. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the time-out event. The GPTM sets theTnTORIS bit in theGPTMRawInterruptStatus(GPTMRIS) register (see page 552), and holds it until it is cleared by writing theGPTMInterruptClear(GPTMICR) register (see page 558). If the timeout interrupt is enabled in theGPTMInterruptMask(GPTMIMR) register (see page 550), the GPTM also sets theTnTOMIS bit in theGPTMMaskedInterruptStatus (GPTMMIS)register (see page 555). By setting theTnMIE bit in theGPTMTAMRregister, an interrupt can also be generated when the Timer value equals the value loaded into theGPTMTimernMatch (GPTMTnMATCH)and GPTMTimernPrescaleMatch(GPTMTnPMR) registers. This interrupt has the same status, masking, and clearing functions as the timeout interrupt. The ADC trigger is enabled by setting theTnOTE bit inGPTMCTL. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 343. If software updates theGPTMTnILRregister while the counter is counting down, the counter loads the new value on the next clock cycle and continues counting down from the new value. If software updates theGPTMTnILRregister while the counter is counting up, the timeout event is changed on the next cycle to the new value. If software updates theGPTMTimernValue(GPTMTnV) register while the counter is counting up or down, the counter loads the new value on the next clock cycle and continues counting from the new value. If software updates theGPTMTnMATCHRregister while the counter is counting, the counter loads the new value on the next clock cycle and continues counting from the new value. If theTnSTALL bit in theGPTMCTLregister is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. The following table shows a variety of configurations for a 16-bit free-running timer while using the prescaler. All values assume an 80-MHz clock with Tc=12.5 ns (clock period). Table10-5.16-BitTimerWithPrescalerConfigurations UnitsMaxTime#Clock(Tc)aPrescale mS0.8192100000000 mS1.6384200000001 mS2.4576300000010 mS208.076825411111101 mS208.89625511111110 mS209.715225611111111 a. Tc is the clock period. Wait-for-Trigger Mode The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured, a single timer can initiate mulitple timing events using the Timer triggers. Wait-for-Trigger mode is enabled by setting theTnWOT bit in theGPTMTnMRregister. When theTnWOT bit is set, Timer N+1 does not begin counting until the timer in the previous position in the daisy chain (Timer N) reaches its time-out event. The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2 follows GPTM1, and so on. If Timer A is in 32-bit mode (controlled by theGPTMCFG bit in the GPTMCFGregister), it triggers Timer A in the next module. If Timer A is in 16-bit mode, it triggers Timer B in the same module, and Timer B triggers Timer A in the next module. Care must be taken that theTAWOT bit is never set in GPTM0. Figure 10-2 on page 533 shows how theGPTMCFG bit affects the daisy chain. This function is valid for both one-shot and periodic modes. March 19, 2011532 Texas Instruments-Advance Information General-Purpose Timers

Figure10-2.TimerDaisyChain GP T imer N T imer B T imer A 1 0 GPTMCFG GP T imer N+1 T imer B T imer A 1 0 GPTMCFG T imer B ADC T rigger T imer A ADC T rigger T imer B ADC T rigger T imer A ADC T rigger

10.3.2.2 Real-TimeClockTimerMode

In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers are configured as an up-counter. When RTC mode is selected for the first time after reset, the counter is loaded with a value of 0x1. All subsequent load values must be written to theGPTM TimerAIntervalLoad(GPTMTAILR) register (see page 560). The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1-Hz rate and is passed along to the input of the counter. When software writes theTAEN bit in theGPTMCTLregister, the counter starts counting up from its preloaded value of 0x1. When the current count value matches the preloaded value in the GPTMTAMATCHRregister, the GPTM asserts theRTCRIS bit inGPTMRISand continues counting until either a hardware reset, or it is disabled by software (clearing theTAEN bit). When the timer value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the RTC interrupt is enabled inGPTMIMR, the GPTM also sets theRTCMIS bit inGPTMMISand generates a controller interrupt. The status flags are cleared by writing theRTCCINT bit inGPTMICR. In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 343. If theTASTALL and/or TBSTALL bits in theGPTMCTLregister are set, the timer does not freeze if the RTCEN bit is set inGPTMCTL.

10.3.2.3 InputEdge-CountMode

Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. In Edge-Count mode, the timer is configured as a 24-bit down-counter including the optional prescaler with the upper count value stored in theGPTMTimernPrescale(GPTMTnPR) register and the lower bits in theGPTMTnRregister. In this mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, theTnCMR bit of the GPTMTnMRregister must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of theGPTMCTLregister. During initialization, theGPTMTnMATCHRand GPTMTnPMRregisters are configured so that the difference between the value in theGPTMTnILR and GPTMTnPRregisters and theGPTMTnMATCHRand GPTMTnPMRregisters equals the number of edge events that must be counted. 533March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

When software writes theTnEN bit in theGPTMControl(GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matchesGPTMTnMATCHRand GPTMTnPMR. When the counts match, the GPTM asserts the CnMRIS bit in theGPTMRISregister (and theCnMMIS bit, if the interrupt is not masked). In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting theTnOTE bit inGPTMCTL.The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 343. After the match value is reached, the counter is then reloaded using the value inGPTMTnILRand GPTMTnPRregisters, and stopped because the GPTM automatically clears theTnEN bit in the GPTMCTLregister. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 10-3 on page 534 shows how Input Edge-Count mode works. In this case, the timer start value is set toGPTMTnILR=0x000A and the match value is set toGPTMTnMATCHR=0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted because the timer automatically clears theTnEN bit after the current count matches the value in theGPTMTnMATCHRregister. Figure10-3.InputEdge-CountModeExample Input Signal T imer stops, flags asserted T imer reload on next cycle Ignored IgnoredCount 0x000A 0x0006 0x0007 0x0008 0x0009

10.3.2.4 InputEdge-TimeMode

Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. The prescaler is not available in 16-Bit Input Edge-Time mode. In Edge-Time mode, the timer is configured as a 16-bit down-counter. In this mode, the timer is initialized to the value loaded in theGPTMTnILRregister. The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time mode by March 19, 2011534 Texas Instruments-Advance Information General-Purpose Timers

setting theTnCMR bit in theGPTMTnMRregister, and the type of event that the timer captures is determined by theTnEVENT fields of theGPTMCTLregister. When software writes theTnEN bit in theGPTMCTLregister, the timer is enabled for event capture. When the selected input event is detected, the current timer counter value is captured in the GPTMTnRregister and is available to be read by the microcontroller. The GPTM then asserts the CnERIS bit (and theCnEMIS bit, if the interrupt is not masked). TheGPTMTnVcontains the free-running value of the timer and can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting theTnOTE bit inGPTMCTL.The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 343. After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with the value from the GPTMTnILRregister. Figure 10-4 on page 535 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into theGPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into theGPTMTnRregister). Figure10-4.16-BitInputEdge-TimeModeExample GPTMTnR=Y Input Signal T ime Count GPTMTnR=X GPTMTnR=Z Z X Y 0xFFFF

10.3.2.5 PWMMode

Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 16-bit down-counter with a start value (and thus period) defined by theGPTMTnILRregister. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with theGPTMTnMRregister by setting theTnAMS bit to 0x1, the TnCMR bit to 0x0, and theTnMR field to 0x1 or 0x2. 535March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

When software writes theTnEN bit in theGPTMCTLregister, the counter begins counting down until it reaches the 0x0 state. On the next counter cycle in periodic mode, the counter reloads its start value from theGPTMTnILRregister and continues counting until disabled by software clearing the TnEN bit in theGPTMCTLregister. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of theGPTMTnILRregister (its start state), and is deasserted when the counter value equals the value in theGPTMTnMATCHR register. Software has the capability of inverting the output PWM signal by setting theTnPWML bit in theGPTMCTLregister. Figure 10-5 on page 536 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock andTnPWML=0 (duty cycle would be 33% for theTnPWML =1 configuration). For this example, the start value isGPTMTnILR=0xC350 and the match value is GPTMTnMATCHR=0x411A. Figure10-5.16-BitPWMModeExample Output Signal T ime Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x41 1A TnPWML = 0 TnPWML = 1 TnEN set

10.3.3 DMAOperation

The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs. The arbitration size of the μDMA transfer should be set to the amount of data that should be transferred whenever a timer event occurs. For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of 8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items have been transferred. No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct Memory Access (μDMA)” on page 339 for more details about programming the μDMA controller. March 19, 2011536 Texas Instruments-Advance Information General-Purpose Timers

10.3.4 AccessingConcatenatedRegisterValues

The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to theGPTMCFG bit field in the GPTMConfiguration(GPTMCFG) register. In both configurations, certain registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTMTimerAIntervalLoad(GPTMTAILR) register [15:0], see page 560 ■ GPTMTimerBIntervalLoad(GPTMTBILR) register [15:0], see page 561 ■ GPTMTimerA(GPTMTAR) register [15:0], see page 568 ■ GPTMTimerB(GPTMTBR) register [15:0], see page 569 ■ GPTMTimerAValue(GPTMTAV) register [15:0], see page 570 ■ GPTMTimerBValue(GPTMTBV) register [15:0], see page 571 ■ GPTMTimerAMatch(GPTMTAMATCHR) register [15:0], see page 562 ■ GPTMTimerBMatch(GPTMTBMATCHR) register [15:0], see page 563 In the 32-bit modes, the GPTM translates a 32-bit write access toGPTMTAILRinto a write access to bothGPTMTAILRand GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a 32-bit read access toGPTMTARreturns the value: GPTMTBR[15:0]:GPTMTAR[15:0] A 32-bit read access toGPTMTAVreturns the value: GPTMTBV[15:0]:GPTMTAV[15:0]

10.4 InitializationandConfiguration

To use a GPTM, the appropriateTIMERn bit must be set in theRCGC1register (see page 277). If using any CCP pins, the clock to the appropriate GPIO module must be enabled via theRCGC1 register (see page 277). To find out which GPIO port to enable, refer to Table 24-4 on page 1238. Configure thePMCn fields in theGPIOPCTLregister to assign the CCP signals to the appropriate pins (see page 439 and Table 24-5 on page 1247). This section shows module initialization and configuration examples for each of the supported timer modes.

10.4.1 One-Shot/PeriodicTimerMode

The GPTM is configured for One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (theTnEN bit in theGPTMCTLregister is cleared) before making any changes. 2. Write theGPTMConfigurationRegister(GPTMCFG) with a value of 0x0000.0000. 3. Configure theTnMR field in theGPTMTimernModeRegister(GPTMTnMR) : 537March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Optionally configure theTnSNAPS, TnWOT, TnMTE, andTnCDIR bits in theGPTMTnMRregister to select whether to capture the value of the free-running timer at time-out, use an external trigger to start counting, configure an additional trigger or interrupt, and count up or down. 5. Load the start value into theGPTMTimernIntervalLoadRegister(GPTMTnILR) . 6. If interrupts are required, set the appropriate bits in theGPTMInterruptMaskRegister (GPTMIMR). 7. Set theTnEN bit in theGPTMCTLregister to enable the timer and start counting. 8. Poll theGPTMRISregister or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the appropriate bit of theGPTMInterruptClear Register(GPTMICR). If theTnMIE bit in theGPTMTnMRregister is set, theRTCRIS bit in theGPTMRISregister is set, and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads the timer and continues counting after the time-out event.

10.4.2 Real-TimeClock(RTC)Mode

To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (theTAEN bit is cleared) before making any changes. 2. Write theGPTMConfigurationRegister(GPTMCFG) with a value of 0x0000.0001. 3. Write the match value to theGPTMTimernMatchRegister(GPTMTnMATCHR) . 4. Set/clear theRTCEN bit in theGPTMControlRegister(GPTMCTL) as needed. 5. If interrupts are required, set theRTCIM bit in theGPTMInterruptMaskRegister(GPTMIMR) . 6. Set theTAEN bit in theGPTMCTLregister to enable the timer and start counting. When the timer count equals the value in theGPTMTnMATCHRregister, the GPTM asserts the RTCRIS bit in theGPTMRISregister and continues counting until Timer A is disabled or a hardware reset. The interrupt is cleared by writing theRTCCINT bit in theGPTMICRregister.

10.4.3 InputEdge-CountMode

A timer is configured to Input Edge-Count mode by the following sequence: 1. Ensure the timer is disabled (theTnEN bit is cleared) before making any changes. 2. Write theGPTMConfiguration(GPTMCFG) register with a value of 0x0000.0004. 3. In theGPTMTimerMode(GPTMTnMR) register, write theTnCMR field to 0x0 and theTnMR field to 0x3. March 19, 2011538 Texas Instruments-Advance Information General-Purpose Timers

1. Configure the type of event(s) that the timer captures by writing theTnEVENT field of theGPTM Control(GPTMCTL) register. 5. If a prescaler is to be used, write the prescale value to theGPTMTimernPrescaleRegister (GPTMTnPR). 6. Load the timer start value into theGPTMTimernIntervalLoad(GPTMTnILR) register. 7. Load the event count into theGPTMTimernMatch(GPTMTnMATCHR) register. 8. If interrupts are required, set theCnMIM bit in theGPTMInterruptMask(GPTMIMR) register. 9. Set theTnEN bit in theGPTMCTLregister to enable the timer and begin waiting for edge events. 10. Poll theCnMRIS bit in theGPTMRISregister or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to theCnMCINT bit of theGPTM InterruptClear(GPTMICR) register. When counting down in Input Edge-Count Mode, the timer stops after the programmed number of edge events has been detected. To re-enable the timer, ensure that theTnEN bit is cleared and repeat step 4 on page 539 through step 9 on page 539.

10.4.4 InputEdgeTimingMode

A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (theTnEN bit is cleared) before making any changes. 2. Write theGPTMConfiguration(GPTMCFG) register with a value of 0x0000.0004. 3. In theGPTMTimerMode(GPTMTnMR) register, write theTnCMR field to 0x1 and theTnMR field to 0x3. 4. Configure the type of event that the timer captures by writing theTnEVENT field of theGPTM Control(GPTMCTL) register. 5. Load the timer start value into theGPTMTimernIntervalLoad(GPTMTnILR) register. 6. If interrupts are required, set theCnEIM bit in theGPTMInterruptMask(GPTMIMR) register. 7. Set theTnEN bit in theGPTMControl(GPTMCTL) register to enable the timer and start counting. 8. Poll theCnERIS bit in theGPTMRISregister or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to theCnECINT bit of theGPTM InterruptClear(GPTMICR) register. The time at which the event happened can be obtained by reading theGPTMTimern(GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing theGPTMTnILRregister. The change takes effect at the next cycle after the write.

10.4.5 PWMMode

A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (theTnEN bit is cleared) before making any changes. 539March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

1. Write theGPTMConfiguration(GPTMCFG) register with a value of 0x0000.0004. 3. In theGPTMTimerMode(GPTMTnMR) register, set theTnAMS bit to 0x1, theTnCMR bit to 0x0, and theTnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in theTnPWML field of theGPTMControl(GPTMCTL) register. 5. Load the timer start value into theGPTMTimernIntervalLoad(GPTMTnILR) register. 6. Load theGPTMTimernMatch(GPTMTnMATCHR) register with the match value. 7. Set theTnEN bit in theGPTMControl(GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing theGPTMTnILRregister, and the change takes effect at the next cycle after the write.

10.5 RegisterMap

Table 10-6 on page 540 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ Timer 0: 0x4003.0000 ■ Timer 1: 0x4003.1000 ■ Timer 2: 0x4003.2000 ■ Timer 3: 0x4003.3000 Note that the GP Timer module clock must be enabled before the registers can be programmed (see page 277). There must be a delay of 3 system clocks after the Timer module clock is enabled before any Timer module registers are accessed. Table10-6.TimersRegisterMap See pageDescriptionResetTypeNameOffset 542GPTM Configuration0x0000.0000R/WGPTMCFG0x000 543GPTM Timer A Mode0x0000.0000R/WGPTMTAMR0x004 545GPTM Timer B Mode0x0000.0000R/WGPTMTBMR0x008 547GPTM Control0x0000.0000R/WGPTMCTL0x00C 550GPTM Interrupt Mask0x0000.0000R/WGPTMIMR0x018 552GPTM Raw Interrupt Status0x0000.0000ROGPTMRIS0x01C 555GPTM Masked Interrupt Status0x0000.0000ROGPTMMIS0x020 558GPTM Interrupt Clear0x0000.0000W1CGPTMICR0x024 560GPTM Timer A Interval Load0xFFFF.FFFFR/WGPTMTAILR0x028 561GPTM Timer B Interval Load0x0000.FFFFR/WGPTMTBILR0x02C 562GPTM Timer A Match0xFFFF.FFFFR/WGPTMTAMATCHR0x030 March 19, 2011540 Texas Instruments-Advance Information General-Purpose Timers

Table10-6.TimersRegisterMap (continued) See pageDescriptionResetTypeNameOffset 563GPTM Timer B Match0x0000.FFFFR/WGPTMTBMATCHR0x034 564GPTM Timer A Prescale0x0000.0000R/WGPTMTAPR0x038 565GPTM Timer B Prescale0x0000.0000R/WGPTMTBPR0x03C 566GPTM TimerA Prescale Match0x0000.0000R/WGPTMTAPMR0x040 567GPTM TimerB Prescale Match0x0000.0000R/WGPTMTBPMR0x044 568GPTM Timer A0xFFFF.FFFFROGPTMTAR0x048 569GPTM Timer B0x0000.FFFFROGPTMTBR0x04C 570GPTM Timer A Value0xFFFF.FFFFRWGPTMTAV0x050 571GPTM Timer B Value0x0000.FFFFRWGPTMTBV0x054

10.6 RegisterDescriptions

The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. 541March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register1:GPTMConfiguration(GPTMCFG),offset0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. Important: Bits in this register should only be changed when theTAEN and TBEN bits in the GPTMCTLregister are cleared. GPTM Configuration (GPTMCFG) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 GPTMCFGreserved R/WR/WR/WROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 GPTM Configuration The GPTMCFG values are defined as follows: DescriptionValue 32-bit timer configuration.0x0 32-bit real-time clock (RTC) counter configuration.0x1 Reserved0x2-0x3 16-bit timer configuration. The function is controlled by bits 1:0 ofGPTMTAMRand GPTMTBMR. 0x4 Reserved0x5-0x7 0x0R/WGPTMCFG2:0 March 19, 2011542 Texas Instruments-Advance Information General-Purpose Timers

Register2:GPTMTimerAMode(GPTMTAMR),offset0x004 This register configures the GPTM based on the configuration selected in theGPTMCFGregister. When in PWM mode, set theTAAMS bit , clear theTACMR bit, and configure theTAMR field to 0x1 or 0x2. This register controls the modes for Timer A when it is used individually. When Timer A and Timer B are concatenated, this register controls the modes for both Timer A and Timer B, and the contents of GPTMTBMRare ignored. Important: Bits in this register should only be changed when theTAEN bit in theGPTMCTLregister is cleared. GPTM Timer A Mode (GPTMTAMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TAMRTACMRTAAMSTACDIRTAMIETAWOTTASNAPSreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPTM Timer A Snap-Shot Mode DescriptionValue Snap-shot mode is disabled.0 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into theGPTMTimerA(GPTMTAR) register. 0R/WTASNAPS7 GPTM Timer A Wait-on-Trigger DescriptionValue Timer A begins counting as soon as it is enabled.0 If Timer A is enabled (TAENis set in theGPTMCTLregister), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain, see Figure 10-2 on page 533. This function is valid for both one-shot and periodic modes. This bit must be clear for GP Timer Module 0, Timer A. 0R/WTAWOT6 543March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field GPTM Timer A Match Interrupt Enable DescriptionValue The match interrupt is disabled.0 An interrupt is generated when the match value in the GPTMTAMATCHRregister is reached in the one-shot and periodic modes. 0R/WTAMIE5 GPTM Timer A Count Direction DescriptionValue The timer counts down.0 When in one-shot or periodic mode, the timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up. 0R/WTACDIR4 GPTM Timer A Alternate Mode Select The TAAMS values are defined as follows: DescriptionValue Capture mode is enabled.0 PWM mode is enabled.1 Note: To enable PWM mode, you must also clear theTACMR bit and configure theTAMR field to 0x1 or 0x2. 0R/WTAAMS3 GPTM Timer A Capture Mode The TACMR values are defined as follows: DescriptionValue Edge-Count mode0 Edge-Time mode1 0R/WTACMR2 GPTM Timer A Mode The TAMR values are defined as follows: DescriptionValue Reserved0x0 One-Shot Timer mode0x1 Periodic Timer mode0x2 Capture mode0x3 The Timer mode is based on the timer configuration defined by bits 2:0 in theGPTMCFGregister. 0x0R/WTAMR1:0 March 19, 2011544 Texas Instruments-Advance Information General-Purpose Timers

Register3:GPTMTimerBMode(GPTMTBMR),offset0x008 This register configures the GPTM based on the configuration selected in theGPTMCFGregister. When in PWM mode, set theTBAMS bit, clear theTBCMR bit, and configure theTBMR field to 0x1 or 0x2. This register controls the modes for Timer B when it is used individually. When Timer A and Timer B are concatenated, this register is ignored andGPTMTBMRcontrols the modes for both Timer A and Timer B. Important: Bits in this register should only be changed when theTBEN bit in theGPTMCTLregister is cleared. GPTM Timer B Mode (GPTMTBMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TBMRTBCMRTBAMSTBCDIRTBMIETBWOTTBSNAPSreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 GPTM Timer B Snap-Shot Mode DescriptionValue Snap-shot mode is disabled.0 If Timer B is configured in the periodic mode, the actual free-running value of Timer B is loaded at the time-out event into theGPTMTimerB(GPTMTBR) register. 0R/WTBSNAPS7 GPTM Timer B Wait-on-Trigger DescriptionValue Timer B begins counting as soon as it is enabled.0 If Timer B is enabled (TBENis set in theGPTMCTLregister), Timer B does not begin counting until it receives an it receives a trigger from the timer in the previous position in the daisy chain, see Figure 10-2 on page 533. This function is valid for both one-shot and periodic modes. 0R/WTBWOT6 545March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field GPTM Timer B Match Interrupt Enable DescriptionValue The match interrupt is disabled.0 An interrupt is generated when the match value in the GPTMTBMATCHRregister is reached in the one-shot and periodic modes. 0R/WTBMIE5 GPTM Timer B Count Direction DescriptionValue The timer counts down.0 When in one-shot or periodic mode, the timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up. 0R/WTBCDIR4 GPTM Timer B Alternate Mode Select The TBAMS values are defined as follows: DescriptionValue Capture mode is enabled.0 PWM mode is enabled.1 Note: To enable PWM mode, you must also clear theTBCMR bit and configure theTBMR field to 0x1 or 0x2. 0R/WTBAMS3 GPTM Timer B Capture Mode The TBCMR values are defined as follows: DescriptionValue Edge-Count mode0 Edge-Time mode1 0R/WTBCMR2 GPTM Timer B Mode The TBMR values are defined as follows: DescriptionValue Reserved0x0 One-Shot Timer mode0x1 Periodic Timer mode0x2 Capture mode0x3 The timer mode is based on the timer configuration defined by bits 2:0 in theGPTMCFGregister. 0x0R/WTBMR1:0 March 19, 2011546 Texas Instruments-Advance Information General-Purpose Timers

Register4:GPTMControl(GPTMCTL),offset0x00C This register is used alongside theGPTMCFGand GMTMTnMRregisters to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. Important: Bits in this register should only be changed when theTnEN bit for the respective timer is cleared. GPTM Control (GPTMCTL) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x00C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TAENTASTALLTAEVENTRTCENTAOTETAPWMLreservedTBENTBSTALLTBEVENTreservedTBOTETBPWMLreserved R/WR/WR/WR/WR/WR/WR/WROR/WR/WR/WR/WROR/WR/WROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:15 GPTM Timer B PWM Output Level The TBPWML values are defined as follows: DescriptionValue Output is unaffected.0 Output is inverted.1 0R/WTBPWML14 GPTM Timer B Output Trigger Enable The TBOTE values are defined as follows: DescriptionValue The output Timer B ADC trigger is disabled.0 The output Timer B ADC trigger is enabled.1 In addition, the ADC must be enabled and the timer selected as a trigger source with theEMn bit in theADCEMUXregister (see page 629). 0R/WTBOTE13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12 547March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field GPTM Timer B Event Mode The TBEVENT values are defined as follows: DescriptionValue Positive edge0x0 Negative edge0x1 Reserved0x2 Both edges0x3 0x0R/WTBEVENT11:10 GPTM Timer B Stall Enable The TBSTALL values are defined as follows: DescriptionValue Timer B continues counting while the processor is halted by the debugger. Timer B freezes counting while the processor is halted by the debugger. If the processor is executing normally, theTBSTALL bit is ignored. 0R/WTBSTALL9 GPTM Timer B Enable The TBEN values are defined as follows: DescriptionValue Timer B is disabled.0 Timer B is enabled and begins counting or the capture logic is enabled based on theGPTMCFGregister. 0R/WTBEN8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 GPTM Timer A PWM Output Level The TAPWML values are defined as follows: DescriptionValue Output is unaffected.0 Output is inverted.1 0R/WTAPWML6 GPTM Timer A Output Trigger Enable The TAOTE values are defined as follows: DescriptionValue The output Timer A ADC trigger is disabled.0 The output Timer A ADC trigger is enabled.1 In addition, the ADC must be enabled and the timer selected as a trigger source with theEMn bit in theADCEMUXregister (see page 629). 0R/WTAOTE5 March 19, 2011548 Texas Instruments-Advance Information General-Purpose Timers

DescriptionResetTypeNameBit/Field GPTM RTC Enable The RTCEN values are defined as follows: DescriptionValue RTC counting is disabled.0 RTC counting is enabled.1 0R/WRTCEN4 GPTM Timer A Event Mode The TAEVENT values are defined as follows: DescriptionValue Positive edge0x0 Negative edge0x1 Reserved0x2 Both edges0x3 0x0R/WTAEVENT3:2 GPTM Timer A Stall Enable The TASTALL values are defined as follows: DescriptionValue Timer A continues counting while the processor is halted by the debugger. Timer A freezes counting while the processor is halted by the debugger. If the processor is executing normally, theTASTALL bit is ignored. 0R/WTASTALL1 GPTM Timer A Enable The TAEN values are defined as follows: DescriptionValue Timer A is disabled.0 Timer A is enabled and begins counting or the capture logic is enabled based on theGPTMCFGregister. 0R/WTAEN0 549March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register5:GPTMInterruptMask(GPTMIMR),offset0x018 This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it. GPTM Interrupt Mask (GPTMIMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TATOIMCAMIMCAEIMRTCIMTAMIMreservedTBTOIMCBMIMCBEIMTBMIMreserved R/WR/WR/WR/WR/WROROROR/WR/WR/WR/WROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:12 GPTM Timer B Mode Match Interrupt Mask The TBMIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WTBMIM11 GPTM Capture B Event Interrupt Mask The CBEIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WCBEIM10 GPTM Capture B Match Interrupt Mask The CBMIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WCBMIM9 March 19, 2011550 Texas Instruments-Advance Information General-Purpose Timers

DescriptionResetTypeNameBit/Field GPTM Timer B Time-Out Interrupt Mask The TBTOIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WTBTOIM8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:5 GPTM Timer A Mode Match Interrupt Mask The TAMIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WTAMIM4 GPTM RTC Interrupt Mask The RTCIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WRTCIM3 GPTM Capture A Event Interrupt Mask The CAEIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WCAEIM2 GPTM Capture A Match Interrupt Mask The CAMIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WCAMIM1 GPTM Timer A Time-Out Interrupt Mask The TATOIM values are defined as follows: DescriptionValue Interrupt is disabled.0 Interrupt is enabled.1 0R/WTATOIM0 551March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register6:GPTMRawInterruptStatus(GPTMRIS),offset0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in theGPTMIMRregister. Each bit can be cleared by writing a 1 to its corresponding bit inGPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x01C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TATORISCAMRISCAERISRTCRISTAMRISreservedTBTORISCBMRISCBERISTBMRISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:12 GPTM Timer B Mode Match Raw Interrupt DescriptionValue The TBMIE bit is set in theGPTMTBMRregister, and the match value in theGPTMTBMATCHRregister has been reached when in the one-shot and periodic modes. The match value has not been reached.0 This bit is cleared by writing a 1 to theTBMCINT bit in theGPTMICR register. 0ROTBMRIS11 GPTM Capture B Event Raw Interrupt DescriptionValue The Capture B event has occurred.1 The Capture B event has not occurred.0 This bit is cleared by writing a 1 to theCBECINT bit in theGPTMICR register. 0ROCBERIS10 GPTM Capture B Match Raw Interrupt DescriptionValue The Capture B match has occurred.1 The Capture B match has not occurred.0 This bit is cleared by writing a 1 to theCBMCINT bit in theGPTMICR register. 0ROCBMRIS9 March 19, 2011552 Texas Instruments-Advance Information General-Purpose Timers

DescriptionResetTypeNameBit/Field GPTM Timer B Time-Out Raw Interrupt DescriptionValue Timer B has timed out.1 Timer B has not timed out.0 This bit is cleared by writing a 1 to theTBTOCINT bit in theGPTMICR register. 0ROTBTORIS8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:5 GPTM Timer A Mode Match Raw Interrupt DescriptionValue The TAMIE bit is set in theGPTMTAMRregister, and the match value in theGPTMTAMATCHRregister has been reached when in the one-shot and periodic modes. The match value has not been reached.0 This bit is cleared by writing a 1 to theTAMCINT bit in theGPTMICR register. 0ROTAMRIS4 GPTM RTC Raw Interrupt DescriptionValue The RTC event has occurred.1 The RTC event has not occurred.0 This bit is cleared by writing a 1 to theRTCCINT bit in theGPTMICR register. 0RORTCRIS3 GPTM Capture A Event Raw Interrupt DescriptionValue The Capture A event has occurred.1 The Capture A event has not occurred.0 This bit is cleared by writing a 1 to theCAECINT bit in theGPTMICR register. 0ROCAERIS2 GPTM Capture A Match Raw Interrupt DescriptionValue The Capture A match has occurred.1 The Capture A match has not occurred.0 This bit is cleared by writing a 1 to theCAMCINT bit in theGPTMICR register. 0ROCAMRIS1 553March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field GPTM Timer A Time-Out Raw Interrupt DescriptionValue Timer A has timed out.1 Timer A has not timed out.0 This bit is cleared by writing a 1 to theTATOCINT bit in theGPTMICR register. 0ROTATORIS0 March 19, 2011554 Texas Instruments-Advance Information General-Purpose Timers

Register7:GPTMMaskedInterruptStatus(GPTMMIS),offset0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit inGPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x020 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TATOMISCAMMISCAEMISRTCMISTAMMISreservedTBTOMISCBMMISCBEMISTBMMISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:12 GPTM Timer B Mode Match Masked Interrupt DescriptionValue An unmasked Timer B Mode Match interrupt has occurred. A Timer B Mode Match interrupt has not occurred or is masked.0 This bit is cleared by writing a 1 to theTBMCINT bit in theGPTMICR register. 0ROTBMMIS11 GPTM Capture B Event Masked Interrupt DescriptionValue An unmasked Capture B event interrupt has occurred. A Capture B event interrupt has not occurred or is masked.0 This bit is cleared by writing a 1 to theCBECINT bit in theGPTMICR register. 0ROCBEMIS10 555March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

DescriptionResetTypeNameBit/Field GPTM Capture B Match Masked Interrupt DescriptionValue An unmasked Capture B Match interrupt has occurred. A Capture B Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to theCBMCINT bit in theGPTMICR register. 0ROCBMMIS9 GPTM Timer B Time-Out Masked Interrupt DescriptionValue An unmasked Timer B Time-Out interrupt has occurred. A Timer B Time-Out interrupt has not occurred or is masked.0 This bit is cleared by writing a 1 to theTBTOCINT bit in theGPTMICR register. 0ROTBTOMIS8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:5 GPTM Timer A Mode Match Masked Interrupt DescriptionValue An unmasked Timer A Mode Match interrupt has occurred. A Timer A Mode Match interrupt has not occurred or is masked.0 This bit is cleared by writing a 1 to theTAMCINT bit in theGPTMICR register. 0ROTAMMIS4 GPTM RTC Masked Interrupt DescriptionValue An unmasked RTC event interrupt has occurred. An RTC event interrupt has not occurred or is masked.0 This bit is cleared by writing a 1 to theRTCCINT bit in theGPTMICR register. 0RORTCMIS3 GPTM Capture A Event Masked Interrupt DescriptionValue An unmasked Capture A event interrupt has occurred. A Capture A event interrupt has not occurred or is masked.0 This bit is cleared by writing a 1 to theCAECINT bit in theGPTMICR register. 0ROCAEMIS2 March 19, 2011556 Texas Instruments-Advance Information General-Purpose Timers

DescriptionResetTypeNameBit/Field GPTM Capture A Match Masked Interrupt DescriptionValue An unmasked Capture A Match interrupt has occurred. A Capture A Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to theCAMCINT bit in theGPTMICR register. 0ROCAMMIS1 GPTM Timer A Time-Out Masked Interrupt DescriptionValue An unmasked Timer A Time-Out interrupt has occurred. A Timer A Time-Out interrupt has not occurred or is masked.0 This bit is cleared by writing a 1 to theTATOCINT bit in theGPTMICR register. 0ROTATOMIS0 557March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register8:GPTMInterruptClear(GPTMICR),offset0x024 This register is used to clear the status bits in theGPTMRISand GPTMMISregisters. Writing a 1 to a bit clears the corresponding bit in theGPTMRISand GPTMMISregisters. GPTM Interrupt Clear (GPTMICR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TATOCINTCAMCINTCAECINTRTCCINTTAMCINTreservedTBTOCINTCBMCINTCBECINTTBMCINTreserved W1CW1CW1CW1CW1CROROROW1CW1CW1CW1CROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:12 GPTM Timer B Mode Match Interrupt Clear Writing a 1 to this bit clears theTBMRIS bit in theGPTMRISregister and theTBMMIS bit in theGPTMMISregister. 0W1CTBMCINT11 GPTM Capture B Event Interrupt Clear Writing a 1 to this bit clears theCBERIS bit in theGPTMRISregister and theCBEMIS bit in theGPTMMISregister. 0W1CCBECINT10 GPTM Capture B Match Interrupt Clear Writing a 1 to this bit clears theCBMRIS bit in theGPTMRISregister and theCBMMIS bit in theGPTMMISregister. 0W1CCBMCINT9 GPTM Timer B Time-Out Interrupt Clear Writing a 1 to this bit clears theTBTORIS bit in theGPTMRISregister and theTBTOMIS bit in theGPTMMISregister. 0W1CTBTOCINT8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:5 GPTM Timer A Mode Match Interrupt Clear Writing a 1 to this bit clears theTAMRIS bit in theGPTMRISregister and theTAMMIS bit in theGPTMMISregister. 0W1CTAMCINT4 GPTM RTC Interrupt Clear Writing a 1 to this bit clears theRTCRIS bit in theGPTMRISregister and theRTCMIS bit in theGPTMMISregister. 0W1CRTCCINT3 GPTM Capture A Event Interrupt Clear Writing a 1 to this bit clears theCAERIS bit in theGPTMRISregister and theCAEMIS bit in theGPTMMISregister. 0W1CCAECINT2 March 19, 2011558 Texas Instruments-Advance Information General-Purpose Timers

DescriptionResetTypeNameBit/Field GPTM Capture A Match Interrupt Clear Writing a 1 to this bit clears theCAMRIS bit in theGPTMRISregister and theCAMMIS bit in theGPTMMISregister. 0W1CCAMCINT1 GPTM Timer A Time-Out Raw Interrupt Writing a 1 to this bit clears theTATORIS bit in theGPTMRISregister and theTATOMIS bit in theGPTMMISregister. 0W1CTATOCINT0 559March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register9:GPTMTimerAIntervalLoad(GPTMTAILR),offset0x028 When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes,GPTMTAILRappears as a 32-bit register (the upper 16-bits correspond to the contents of theGPTMTimerBIntervalLoad(GPTMTBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state ofGPTMTBILR. GPTM Timer A Interval Load (GPTMTAILR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x028 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 TAILR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 TAILR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value ofGPTMTAILR. 0xFFFF.FFFFR/WTAILR31:0 March 19, 2011560 Texas Instruments-Advance Information General-Purpose Timers

Register10:GPTMTimerBIntervalLoad(GPTMTBILR),offset0x02C When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of theGPTMTAILRregister. Reads from this register return the current value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits 31:16 are reserved in both cases. GPTM Timer B Interval Load (GPTMTBILR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.FFFF 16171819202122232425262728293031 TBILR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 TBILR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value ofGPTMTBILR. When a GPTM is in 32-bit mode, writes are ignored, and reads return the current value ofGPTMTBILR. 0x0000.FFFFR/WTBILR31:0 561March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register11:GPTMTimerAMatch(GPTMTAMATCHR),offset0x030 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along withGPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value inGPTMTAILRminus this value. In PWM mode, this value along withGPTMTAILR, determines the duty cycle of the output PWM signal. When a GPTM is configured to one of the 32-bit modes,GPTMTAMATCHRappears as a 32-bit register (the upper 16-bits correspond to the contents of theGPTMTimerBMatch (GPTMTBMATCHR)register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state ofGPTMTBMATCHR. GPTM Timer A Match (GPTMTAMATCHR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 TAMR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 TAMR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer A Match Register This value is compared to theGPTMTARregister to determine match events. 0xFFFF.FFFFR/WTAMR31:0 March 19, 2011562 Texas Instruments-Advance Information General-Purpose Timers

Register12:GPTMTimerBMatch(GPTMTBMATCHR),offset0x034 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along withGPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value inGPTMTBILRminus this value. In PWM mode, this value along withGPTMTBILR, determines the duty cycle of the output PWM signal. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of theGPTMTAMATCHRregister. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. GPTM Timer B Match (GPTMTBMATCHR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.FFFF 16171819202122232425262728293031 TBMR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 0000000000000000Reset 0123456789101112131415 TBMR R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer B Match Register This value is compared to theGPTMTBRregister to determine match events. 0x0000.FFFFR/WTBMR31:0 563March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register13:GPTMTimerAPrescale(GPTMTAPR),offset0x038 This register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. In Edge-Count mode, this register is the MSB of the 24-bit count value. GPTM Timer A Prescale (GPTMTAPR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TAPSRreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved31:8 GPTM Timer A Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 10-5 on page 532 for more details and an example. 0x00R/WTAPSR7:0 March 19, 2011564 Texas Instruments-Advance Information General-Purpose Timers

Register14:GPTMTimerBPrescale(GPTMTBPR),offset0x03C This register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. In Edge-Count mode, this register is the MSB of the 24-bit count value. GPTM Timer B Prescale (GPTMTBPR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TBPSRreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved31:8 GPTM Timer B Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 10-5 on page 532 for more details and an example. 0x00R/WTBPSR7:0 565March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register15:GPTMTimerAPrescaleMatch(GPTMTAPMR),offset0x040 This register effectively extends the range ofGPTMTAMATCHRto 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TAPSMRreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved31:8 GPTM TimerA Prescale Match This value is used alongsideGPTMTAMATCHRto detect timer match events while using a prescaler. 0x00R/WTAPSMR7:0 March 19, 2011566 Texas Instruments-Advance Information General-Purpose Timers

Register16:GPTMTimerBPrescaleMatch(GPTMTBPMR),offset0x044 This register effectively extends the range ofGPTMTBMATCHRto 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TBPSMRreserved R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved31:8 GPTM TimerB Prescale Match This value is used alongsideGPTMTBMATCHRto detect timer match events while using a prescaler. 0x00R/WTBPSMR7:0 567March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register17:GPTMTimerA(GPTMTAR),offset0x048 This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes,GPTMTARappears as a 32-bit register (the upper 16-bits correspond to the contents of theGPTMTimerB(GPTMTBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in theGPTMTAVregister. GPTM Timer A (GPTMTAR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0xFFFF.FFFF 16171819202122232425262728293031 TAR ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 TAR ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer A Register A read returns the current value of theGPTMTimerACountRegister , in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 0xFFFF.FFFFROTAR31:0 March 19, 2011568 Texas Instruments-Advance Information General-Purpose Timers

Register18:GPTMTimerB(GPTMTBR),offset0x04C This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of theGPTMTARregister. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. GPTM Timer B (GPTMTBR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.FFFF 16171819202122232425262728293031 TBR ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TBR ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer B Register A read returns the current value of theGPTMTimerBCountRegister , in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 0x0000.FFFFROTBR31:0 569March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register19:GPTMTimerAValue(GPTMTAV),offset0x050 When read, this register shows the current, free-running value of Timer A in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into theGPTMTARregister on the next clock cycle. In Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes,GPTMTAVappears as a 32-bit register (the upper 16-bits correspond to the contents of theGPTMTimerBValue(GPTMTBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. Note: The GPTMTAVregister cannot be written in Edge-Count mode. GPTM Timer A Value (GPTMTAV) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x050 Type RW, reset 0xFFFF.FFFF 16171819202122232425262728293031 TAV RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset 0123456789101112131415 TAV RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer A Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTARregister on the next clock cycle. 0xFFFF.FFFFRWTAV31:0 March 19, 2011570 Texas Instruments-Advance Information General-Purpose Timers

Register20:GPTMTimerBValue(GPTMTBV),offset0x054 When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into theGPTMTBRregister on the next clock cycle. In Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of theGPTMTAVregister. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the current, free-running value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. GPTM Timer B Value (GPTMTBV) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x054 Type RW, reset 0x0000.FFFF 16171819202122232425262728293031 TBV RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 TBV RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset DescriptionResetTypeNameBit/Field GPTM Timer B Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTARregister on the next clock cycle. 0x0000.FFFFRWTBV31:0 571March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

11 WatchdogTimers

A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The LM3S9B92 microcontroller has two Watchdog Timer Modules, one module is clocked by the system clock (Watchdog Timer 0) and the other is clocked by the PIOSC (Watchdog Timer 1). The two modules are identical except that WDT1 is in a different clock domain, and therefore requires synchronizers. As a result, WDT1 has a bit defined in theWatchdogTimerControl(WDTCTL) register to indicate when a write to a WDT1 register is complete. Software can use this bit to ensure that the previous access has completed before starting the next access. The Stellaris® LM3S9B92 controller has two Watchdog Timer modules with the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. March 19, 2011572 Texas Instruments-Advance Information Watchdog Timers

11.1 BlockDiagram

Figure11-1.WDTModuleBlockDiagram Control / Clock / Interrupt Generation WDTCTL WDTICR WDTRIS WDTMIS WDTLOCK WDTTEST WDTLOAD WDTV ALUE Comparator 32-Bit Down Counter 0x0000.0000 Interrupt System Clock/ PIOSC Identification Registers WDTPCellID 0 WDTPeriphID 0 WDTPeriphID 4 WDTPCellID 1 WDTPeriphID 1 WDTPeriphID 5 WDTPCellID 2 WDTPeriphID 2 WDTPeriphID 6 WDTPCellID 3 WDTPeriphID 3 WDTPeriphID 7

11.2 FunctionalDescription

The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of theWatchdogTimer Load(WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, theWatchdogTimerLock(WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled by setting theRESEN bit in theWDTCTLregister, the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in theWDTLOADregister, and counting resumes from that value. If WDTLOADis written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. 573March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Writing toWDTLOADdoes not clear an active interrupt. An interrupt must be specifically cleared by writing to theWatchdogInterruptClear(WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state.

11.2.1 RegisterAccessTiming

Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions. TheWRC bit in the WatchdogControl(WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should pollWDTCTLfor WRC=1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock.

11.3 InitializationandConfiguration

To use the WDT, its peripheral clock must be enabled by setting theWDT bit in theRCGC0register, see page 269. The Watchdog Timer is configured using the following sequence: 1. Load theWDTLOADregister with the desired timer load value. 2. If WDT1, wait for theWRC bit in theWDTCTLregister to be set. 3. If the Watchdog is configured to trigger system resets, set theRESEN bit in theWDTCTLregister. 4. If WDT1, wait for theWRC bit in theWDTCTLregister to be set. 5. Set theINTEN bit in theWDTCTLregister to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to theWDTLOCKregister. To unlock the Watchdog Timer, write a value of 0x1ACC.E551.

11.4 RegisterMap

Table 11-1 on page 575 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address: ■ WDT0: 0x4000.0000 ■ WDT1: 0x4000.1000 Note that the Watchdog Timer module clock must be enabled before the registers can be programmed (see page 269). March 19, 2011574 Texas Instruments-Advance Information Watchdog Timers

Table11-1.WatchdogTimersRegisterMap See pageDescriptionResetTypeNameOffset 576Watchdog Load0xFFFF.FFFFR/WWDTLOAD0x000 577Watchdog Value0xFFFF.FFFFROWDTVALUE0x004 578Watchdog Control 0x0000.0000 (WDT0) 0x8000.0000 (WDT1) R/WWDTCTL0x008 580Watchdog Interrupt Clear-WOWDTICR0x00C 581Watchdog Raw Interrupt Status0x0000.0000ROWDTRIS0x010 582Watchdog Masked Interrupt Status0x0000.0000ROWDTMIS0x014 583Watchdog Test0x0000.0000R/WWDTTEST0x418 584Watchdog Lock0x0000.0000R/WWDTLOCK0xC00 585Watchdog Peripheral Identification 40x0000.0000ROWDTPeriphID40xFD0 586Watchdog Peripheral Identification 50x0000.0000ROWDTPeriphID50xFD4 587Watchdog Peripheral Identification 60x0000.0000ROWDTPeriphID60xFD8 588Watchdog Peripheral Identification 70x0000.0000ROWDTPeriphID70xFDC 589Watchdog Peripheral Identification 00x0000.0005ROWDTPeriphID00xFE0 590Watchdog Peripheral Identification 10x0000.0018ROWDTPeriphID10xFE4 591Watchdog Peripheral Identification 20x0000.0018ROWDTPeriphID20xFE8 592Watchdog Peripheral Identification 30x0000.0001ROWDTPeriphID30xFEC 593Watchdog PrimeCell Identification 00x0000.000DROWDTPCellID00xFF0 594Watchdog PrimeCell Identification 10x0000.00F0ROWDTPCellID10xFF4 595Watchdog PrimeCell Identification 20x0000.0006ROWDTPCellID20xFF8 596Watchdog PrimeCell Identification 30x0000.00B1ROWDTPCellID30xFFC

11.5 RegisterDescriptions

The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 575March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

Register1:WatchdogLoad(WDTLOAD),offset0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOADregister is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 16171819202122232425262728293031 WDTLOAD R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset 0123456789101112131415 WDTLOAD R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType 1111111111111111Reset DescriptionResetTypeNameBit/Field Watchdog Load Value0xFFFF.FFFFR/WWDTLOAD31:0 March 19, 2011576 Texas Instruments-Advance Information Watchdog Timers

Register2:WatchdogValue(WDTVALUE),offset0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 16171819202122232425262728293031 WDTVALUE ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 WDTVALUE ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field Watchdog Value Current value of the 32-bit down counter. 0xFFFF.FFFFROWDTVALUE31:0 577March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S9B92 Microcontroller

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