M39P0R8070E2 NUMONYX | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Datasheet sections
- 1 Summary description
- 2 Signal descriptions
- 2.1 Address inputs (A0-Amax)
- 2.2 LPSDRAM Bank Select Address Inputs (BA0-BA1)
- 2.3 Data Inputs/Outputs (DQ0-DQ15)
- 2.4 Flash memory Chip Enable Input (E
- 2.5 Flash memory Output Enable (G F)
- 2.6 Flash memory Write Enable (W F)
- 2.7 Flash memory Write Protect input (WP F)
- 2.8 Flash memory Reset (RP F)
- 2.9 Flash memory Deep Power-Down (DPD F)
- 2.10 Flash memory Latch Enable (L F)
- 2.11 Flash memory Clock (K F)
- 2.12 Flash memory Wait (WAIT F)
- 2.13 LPSDRAM Chip Select (E S)
- 2.14 LPSDRAM Column Address Strobe (CAS S)
- 2.15 LPSDRAM Row Address Strobe (RAS S)
- 2.16 LPSDRAM Write Enable (W S)
- 2.17 LPSDRAM Clock input (K S)
- 2.18 LPSDRAM Clock Enable (KE S)
- 2.19 LPSDRAM Lower/Upper Data Input/Output Mask (LDQM S/UDQMS)
- 2.20 Flash memory V DDF supply voltage
- 2.21 LPSDRAM V DDS supply voltage
- 2.22 V DDQ supply voltage
- 2.23 Flash memory V PPF Program supply voltage
- 2.24 V SS ground
- 3 Functional description
- 4 Maximum rating
256 or 512Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 128 Mbit Low Power SDRAM, 1.8V supply, Multi-Chip Package Feature summary ■ Multi-Chip Package – 1 die of 256 (16Mb x 16) or 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash memory – 1 die of 128 Mbit (4 Banks of 2Mb x16) Low Power Synchronous Dynamic RAM ■ Supply voltage –V DDF = VDDS = VDDQ = 1.7 to 1.95V –V PPF = 9V for fast program ■ Electronic signature – Manufacturer Code: 20h – 256 Mbit Device Code: 8818 – 512 Mbit Device Code: 8819 ■ Package – ECOPACK® (RoHS compliant) Flash memory ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 108MHz, 66MHz – Asynchronous Page Read mode – Random Access: 96ns ■ Programming time – 4.2µs typical Word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple Bank memory array: 32 Mbit Banks (256Mb devices); 64 Mbit Banks (512Mb devices) – Four Extended Flash Array (EFA) Blocks of
64 Kbits
■ Dual operations – program/erase in one Bank while read in others – No delay between read and write operations ■ 100,000 program/erase cycles per block ■ Security – 64-bit unique device number – 2112-bit user programmable OTP Cells ■ Block locking – All Blocks locked at power-up – Any combination of Blocks can be locked with zero latency –W P F for Block Lock-Down – Absolute Write Protection with V PPF = VSS ■ Common Flash Interface (CFI) LPSDRAM ■ 128 Mbit Synchronous Dynamic RAM – Organized as 4 Banks of 2 MWords, each 16 bits wide ■ Synchronous Burst Read and Write – Fixed burst lengths: 1, 2, 4, 8 Words or Full Page – Burst Types: Sequential and Interleaved – Maximum Clock frequency: 104MHz ■ Automatic and controlled Precharge ■ Low power features: – Partial Array Self Refresh (PASR) – Automatic Temperature Compensated Self Refresh (TCSR) – Driver Strength (DS) – Deep Power-Down Mode ■ Auto Refresh and Self Refresh TFBGA105 (ZAD) 9 x 11mm FBGA www.numonyx.com
M39P0R8070E2, M39P0R9070E2 Contents
Summary description M39P0R8070E2, M39P0R9070E2
1 Summary description
The M39P0R8070E2 and M39P0R9070E2 combine two memory devices in a Multi-Chip Package:
- 256-Mbit (M58PR256J) or 512-Mbit (M58PR512J) Multiple Bank Flash memory
- 128-Mbit Low Power Synchronous DRAM (the M65KA128AE) The purpose of this document is to describe how the two memory components operate with respect to each other. It should be read in conjunction with the M58PRxxxJ and M65KA128AE datasheets, where all specifications required to operate the Flash memory and LPSDRAM components are fully detailed. These datasheets are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA105 package. It is supplied with all the bits erased (set to ‘1’).
Figure 1. Logic diagram
- Amax is A23 in the M39P0R8070E2 and A24 in the M39P0R9070E2.
Table 1. Signal names
- A12-A23 (in the M39P0R8070E2) or A12-A24 (in th e M39P0R9070E2) are Address Inputs for the Flash
Figure 2. TFBGA connections (top view through package)
- Ball A7 is NC in the M39P0R8070E2 and it is A24 in the M39P0R9070E2.
Signal descriptions M39P0R8070E2, M39P0R9070E2
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device.
2.1 Address inputs (A0-Amax)
Amax is equal to A23 in the M39P0R8070E2 and, to A24 in the M39P0R9070E2. A0-A11 are common to the Flash memory and LPSDRAM components. A12-AMax are Address Inputs for the Flash memory component only. In the Flash memory, the Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. In the LPSDRAM, the A0-A11 Address Inputs are used to select the row or column to be made active. If a row is selected, all A0-A11 Address Inputs are used. If a column is selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High (set to ‘1’) during Read or Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to ‘0’) during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle.
2.2 LPSDRAM Bank Select Address Inputs (BA0-BA1)
The BA0 and BA1 Bank Select Address Inputs are used by the LPSDRAM to select the bank to be made active. The LPSDRAM must be enabled, the Row Address Strobe, RASS, must be Low, VIL, the Column Address Strobe, CASS, and W must be High, VIH, when selecting the addresses. The address inputs are latched on the rising edge of the clock signal, K
2.3 Data Inputs/Outputs (DQ0-DQ15)
In the Flash memory, the Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. In the LPSDRAM, the Data Inputs/Outputs are common to all memory components. They output the data stored at the selected address during a Read operation, or are used to input the data during a write operation.
2.4 Flash memory Chip Enable Input (E F)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V IL and Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have E F and ES all at VIL at the same time, only one memory component should be enabled at a time.
M39P0R8070E2, M39P0R9070E2 Signal descriptions
2.5 Flash memory Output Enable (G F)
The Output Enable input controls data outputs during the Bus Read operation of the memory.
2.6 Flash memory Write Enable (W F)
The Write Enable input controls the Bus Write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.7 Flash memory Write Protect input (WP F)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See M58PR512J datasheet for details).
2.8 Flash memory Reset (RP F)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2 (Refer to the M58PRxxxJ datasheet, for the value of IDD2). After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to M58PRxxxJ datasheet).
2.9 Flash memory De ep Power-Down (DPDF)
The Deep Power-Down input is used to put the Flash memory in Deep Power-Down mode. When the Flash memory is in Standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the Deep Power-Down input will cause the memory to enter the Deep Power-Down mode. When the device is in the Deep Power-Down mode, the memory cannot be modified and the data is protected. The polarity of the DPDF pin is determined by ECR14. The Deep Power-Down input is active Low by default.
Signal descriptions M39P0R8070E2, M39P0R9070E2
2.10 Flash memory Latch Enable (L F)
The Latch Enable input latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.11 Flash memory Clock (K F)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is ignored during asynchronous read and in write operations.
2.12 Flash memory Wait (WAIT F)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in advance.
2.13 LPSDRAM Chip Select (E S)
The Chip Select input ES activates the LPSDRAM state machine, address buffers and decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.14 LPSDRAM Column Address Strobe (CAS S)
The Column Address Strobe, CASS, is used in conjunction with Address Inputs A8-A0 and BA1-BA0, to select the starting column location prior to a Read or Write.
2.15 LPSDRAM Row Address Strobe (RAS S)
The Row Address Strobe, RASS, is used in conjunction with Address Inputs A11-A0 and BA1-BA0, to select the starting address location prior to a Read or Write.
2.16 LPSDRAM Write Enable (W S)
The Write Enable input, WS, controls writing to the LPSDRAM.
2.17 LPSDRAM Clock input (K S)
The Clock signal, KS, is used to clock the Read and Write cycles. During normal operation, the Clock Enable pin, KES, is High, VIH. The clock signal KS can be suspended to switch the device to the Self Refresh, Power-Down or Deep Power-Down mode by driving KES Low, VIL.
M39P0R8070E2, M39P0R9070E2 Signal descriptions
2.18 LPSDRAM Clock Enable ( KES)
The Clock Enable, KES, pin is used to control the synchronizing of the signals with Clock signal KS. If KES is High, VIH, the next Clock rising edge is valid. When KES is Low, VIL, the signals are no longer clocked and data Read and Write cycles are extended. KES is also involved in switching the device to the Self-Refresh, Power-Down and Deep Power-Down modes.
2.19 LPSDRAM Lower/Upper Data Input/Output Mask
(LDQMS/UDQMS) Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals used to mask the Read or Write data. The DQM latency is two clock cycles for read operations and there is no latency for write operations.
2.20 Flash memory V DDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supply for all operations (Read, Program and Erase).
2.21 LPSDRAM V DDS supply voltage
VDDS provides the power supply to the internal core of the LPSDRAM component. It is the main power supply for all operations (Read and Write).
2.22 V DDQ supply voltage
VDDQ is common to the Flash memory and LPSDRAM memory components. It provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDDF for the Flash memory, or VDDS for the LPSDRAM. VDDQ can be tied to VDDF or VDDS, or can use a separate supply.
Signal descriptions M39P0R8070E2, M39P0R9070E2
2.23 Flash memory V PPF Program supply voltage
VPPF is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see M58PRxxxJ datasheet for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.
2.24 V SS ground
VSS ground is common to the LPSDRAM and Flash memory components. It is the reference for the core supply. It must be connected to the system ground. Note: Each device in a system should have V DDF,VDDS, VDDQ and VPPH decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
3 Functional description
Figure 3. Functional block diagram
- Amax is A23 in the M39P0R8070E2 and A24 in the M39P0R9070E2.
128 Mbit
Table 2. Bus operations Any SDRAM operation mode is allowed.
- X = Don't care, V = Valid.
- WAIT F signal polarity is configured using the Set Configuration Register command.
- For further details, refer to the M58PRxxxJ and M65KA128AE datasheets.
F can be tied to VIH if the valid address has been previously latched.
- SCA = Start Column Address.
4 Maximum rating
and other relevant quality documents. Table 3. Absolute maximum ratings
5 DC and AC parameters
Figure 4. AC measurement I/O waveform Table 4. Operating and AC measurement conditions
- All voltages are referenced to V SS = 0V.
Figure 5. AC measurement load circuit characteristic values and illustrations. Table 5. Capacitance (1)
- Sampled only, not 100% tested.
6 Package mechanical
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline
Table 6. TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data
7 Part numbering
device, please contact the Numonyx Sales Office nearest to you. Table 7. Ordering information scheme ZAD = stacked TFBGA105 D stacked footprint.
8 Revision history
Table 8. Document revision history 03-Apr-2006 0.1 Initial release. LPSDRAM Power-up removed from Table 2: Bus operations. 30-Nov-2007 2 Applied Numonyx branding.