M39P0R9080E4 NUMONYX | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Description
- 2 Signal descriptions
- 2.1 A bus
- 2.1.1 Flash memory address inputs (A-A0-A-Amax)
- 2.1.2 Flash memory data Inputs/Outputs (A-DQ0-A-DQ15)
- 2.1.3 Flash memory Chip Enable input (A-E
- 2.1.4 Flash memory Output Enable (A-G )
- 2.1.5 Flash memory Write Enable (A-W )
- 2.1.6 Flash memory Write Protect input (A-WP )
- 2.1.7 Flash memory Reset (A-RP )
- 2.1.8 Flash memory Deep Power-Down (A-DPD)
- 2.1.9 Flash memory Latch Enable (A-L
- 2.1.10 Flash memory Clock (A-K)
- 2.1.11 Flash memory Wait (A-WAIT)
- 2.1.12 Flash memory A-V
- 2.1.13 Flash memory A-V DDQ supply voltage
- 2.1.14 Flash memory A-V PP program supply voltage
- 2.1.15 Flash memory A-V SS ground
- 2.2 B bus
- 2.2.1 LPSDRAM address Inputs (B-A0-B-A12)
- 2.2.2 LPSDRAM Bank Select Address Inputs (B-BA0-B-BA1)
- 2.2.3 LPSDRAM Data Inputs/Outputs (B-DQ0-B-DQ15)
- 2.2.4 LPSDRAM Chip Select (B-E
- 2.2.5 LPSDRAM Column Address Strobe (B-CAS )
- 2.2.6 LPSDRAM Row Address Strobe (B-RAS )
- 2.2.7 LPSDRAM Write Enable (B-W )
- 2.2.8 LPSDRAM Clock Input (B-K)
- 2.2.9 LPSDRAM Clock Enable (B-KE)
- 2.2.10 LPSDRAM Lower/Upper Data Input/Output Mask (B-LDQM/B-UDQM)
- 2.2.11 LPSDRAM B-V
- 2.2.12 LPSDRAM B-V DDQ supply voltage
- 2.2.13 LPSDRAM B-V SS ground
Datasheet sections
- 3 Functional description
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical
- 7 Part numbering
- 8 Revision history
Features
■ Multichip package – 1 die of 512 Mbit (32 Mb ×16) or 1 Gbit (64 Mb ×16) multiple bank, multilevel, burst) Flash memory – 1 die of 256 Mbit (4 banks of 4 Mb x16) low power synchronous dynamic RAM ■ Supply voltage –V DDF = VCCP = VDDQ = 1.7 to 1.95 V –V PPF = 9 V for fast program ■ Electronic signature – Manufacturer code: 20h – 512 Mbit device code: 8819 – 1 Gbit device code: 880F ■ ECOPACK® packages available Flash memory ■ Synchronous/asynchronous read – Synchronous Burst Read mode:
108 MHz, 66 MHz
– Asynchronous Page Read mode – Random access: 96 ns ■ Programming time – 4.2 µs typical word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple bank memory array:
64 Mbit banks (512 Mb devices)
128 Mbit banks (1Gb devices)
– Four EFA (extended flash array) blocks of
64 Kbits
■ Dual operations – program/erase in one bank while read in others – No delay between read and write operations ■ 100,000 program/erase cycles per block ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency –W P F for block lock-down – Absolute write protection with V PPF = VSS ■ Security – 64-bit unique device number – 2112-bit user programmable OTP cells ■ CFI (Common Flash Interface) LPSDRAM ■ 256 Mbit synchronous dynamic RAM – Organized as 4 banks of 4 Mwords, each 16 bits wide ■ Synchronous burst read and write – Fixed burst lengths: 1, 2, 4, 8 words or full page – Burst types: sequential and interleaved – Clock frequency: 133 MHz (7.5 ns speed) –C A S latency 3 at 133 MHz ■ Automatic and controlled precharge ■ Low power features: – PASR (partial array self refresh), – TCSR (automatic temperature compensated self refresh) – DS (driver strength) – Deep Power-Down mode ■ Auto refresh and self refresh TFBGA165 (ZAS) 9 x 11 mm FBGA www.numonyx.com
1 Description
- a 512-Mbit (M58PR512LE) or 1 Gbit (M58PR001LE) multiple bank Flash memory
- a 256-Mbit low power synchronous DRAM (the M65KA256Ax) The purpose of this document is to describe how the two memory components operate with respect to each other. It should be read in conjunction with the M58PRxxxLE and M65KA256Ax datasheets, which fully detail all the specifications required to operate the Flash memory and LPSDRAM components. The memory is offered in a stacked TFBGA165 package, and is supplied with all the bits erased (set to ‘1’).
Figure 1. Logic diagram
- The Flash memory component is connected to the A bus whereas the LPSDRAM component is on the B
- Amax is A-A24 in the M39P0R9080E4 and it is A-A25 in the M39P0R1080E4.
Table 1. Signal names
- Amax is A24 in the M39P0R9080E4 and it is A25 in the M39P0R1080E4.
Figure 2. TFBGA connections (top view through package)
Signal descriptions M39P0R9080E4, M39P0R1080E4
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1 A bus
All Flash memory signals are connected to the A bus. They are described below.
2.1.1 Flash memory ad dress inputs (A-A0-A-Amax)
Amax is the highest order Address Input. It is equal to A-A24 in the M39P0R9080E4, and to A-A25 in the M39P0R1080E4. The Address Inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the Command Interface of the Program/Erase Controller.
2.1.2 Flash memory data I nputs/Outputs (A-DQ0-A-DQ15)
The Data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation.
2.1.3 Flash memory Ch ip Enable input (A-E)
The Chip Enable input activates the memory control logic, input buffers, decoders, and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance, and the power consumption is reduced to the standby level.
2.1.4 Flash memory Output Enable (A-G )
The Output Enable input controls data outputs during the bus read operation of the memory.
2.1.5 Flash memory Write Enable (A-W )
The Write Enable input controls the bus write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first.
2.1.6 Flash memory Writ e Protect input (A-WP)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked. (See the M58PRxxxLE datasheet for details).
M39P0R9080E4, M39P0R1080E4 Signal descriptions
2.1.7 Flash memory Reset (A-RP )
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2. Refer to the M58PRxxxLE datasheet, for the value of IDD2. After Reset, all blocks are in the locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode, the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to the M58PRxxxLE datasheet).
2.1.8 Flash memory D eep Power-Down (A-DPD)
The Deep Power-Down input is used to put the Flash memory in deep power-down mode. When the Flash memory is in standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the Deep Power-Down input causes the memory to enter the deep power-down mode. When the device is in the deep power-down mode, the memory cannot be modified and the data is protected. The polarity of the A-DPD pin is determined by ECR14. The Deep Power-Down input is active Low by default.
2.1.9 Flash memory Latch Enable (A-L )
The Latch Enable input latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.1.10 Flash memory Clock (A-K)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge when Latch Enable is at V IL. Clock is ignored during asynchronous read and in write operations.
2.1.11 Flash memory Wait (A-WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in advance.
2.1.12 Flash memory A-V DD supply voltage
A-VDD provides the power supply to the internal core of the Flash memory component. It is the main power supply for all operations (read, program and erase).
Signal descriptions M39P0R9080E4, M39P0R1080E4
2.1.13 Flash memory A-V DDQ supply voltage
A-VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of A-VDD. A-VDDQ can be tied to A-VDD or can use a separate supply. A-VDDQ is sampled at the beginning of program/erase operations. If A-VDDQ is lower than VLKOQ, the device is reset.
2.1.14 Flash memory A-V PP program supply voltage
A-VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If A-VPP is kept in a low voltage range (0V to A-VDDQ) A- VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while A-VPP > VPP1 enables these functions (see the M58PRxxxLE datasheet for the relevant values). A-VPP is only sampled at the beginning of a program or erase operation; a change in its value after the operation has started does not have any effect and program or erase operations continue. If A-V PP is in the range of VPPH it acts as a power supply pin. In this condition A-VPP must be stable until the program/erase algorithm is completed.
2.1.15 Flash memory A-V SS ground
A-VSS ground is the reference for the Flash memory’s core supply. It must be connected to the system ground. Note: Each device in a system should have A-VDD, A-VDDQ and A-VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 6: AC measurement load circuit. The PCB track widths should be sufficient to carry the required A-VPP program and erase currents.
2.2 B bus
All LPSDRAM signals are connected to the B bus. They are described below.
2.2.1 LPSDRAM address Inputs (B-A0-B-A12)
The B-A0-B-A12 Address Inputs are used to select the row or column to be made active. If a row is selected, all thirteen, B-A0-B-A12 Address Inputs are used. If a column is selected, only the nine least significant Address Inputs, B-A0-B-A8, are used. In this latter case, B- A10 determines whether Auto Precharge is used. If B-A10 is High (set to ‘1’) during read or write, the read or write operation includes an auto precharge cycle. If B-A10 is Low (set to ‘0’) during read or write, the read or write cycle does not include an auto precharge cycle.
2.2.2 LPSDRAM Bank Select Address Inputs (B-BA0-B-BA1)
The B-BA0 and B-BA1 Banks Select Address Inputs select the bank to be made active. When selecting the addresses, the device must be enabled, the Row Address Strobe, B- RAS, must be Low, VIL, the Column Address Strobe, B-CAS, and B-W must be High, VIH. The address inputs are latched on the rising edge of the clock signal, B-K.
M39P0R9080E4, M39P0R1080E4 Signal descriptions
2.2.3 LPSDRAM Data Input s/Outputs (B-DQ0-B-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a read operation, or are used to input the data during a write operation.
2.2.4 LPSDRAM Ch ip Select (B-E)
The Chip Select input B-E activates the LPSDRAM state machine, address buffers and decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.2.5 LPSDRAM Column Address Strobe (B-CAS )
The Column Address Strobe, B-CAS, is used in conjunction with Address Inputs B-A8-B-A0 and B-BA1-B-BA0, to select the starting column location prior to a read or write operation.
2.2.6 LPSDRAM Row Ad dress Strobe (B-RAS)
The Row Address Strobe, B-RAS, is used in conjunction with Address Inputs B-A11-B-A0 and B-BA1-B-BA0, to select the starting address location prior to a read or write.
2.2.7 LPSDRAM Write Enable (B-W )
The Write Enable input, B-W, controls writing to the LPSDRAM.
2.2.8 LPSDRAM Clock Input ( B-K)
The Clock signal, B-K, is used to clock the read and write cycles. During normal operation, the Clock Enable pin, B-KE, is High, V IH. The clock signal B-K can be suspended to switch the device to the self refresh, power-down or deep power-down mode by driving B-KE Low, VIL.
2.2.9 LPSDRAM Clock Enable (B- KE)
The Clock Enable, B-KE, pin is used to control the synchronizing of the signals to Clock signal B-K. The signals are clocked when B-KE is High, VIH When B-KE is Low, VIL, the signals are no longer clocked and data read and write cycles are extended. B-KE is also involved in switching the device to the self refresh, power-down and deep power-down modes.
2.2.10 LPSDRAM Lower/ Upper Data Input/Output Mask (B-LDQM/B-UDQM)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals used to mask the read or write data. The DQM latency is two clock cycles for read operations and there is no latency for write operations.
2.2.11 LPSDRAM B-V DD supply voltage
B-VDD provides the power supply to the internal core of the LPSDRAM component. It is the main power supply for all operations (read and write).
Signal descriptions M39P0R9080E4, M39P0R1080E4
2.2.12 LPSDRAM B-V DDQ supply voltage
B-VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of B-VDD. B-VDDQ can be tied to B-VDD or can use a separate supply. It is recommended to power-up and power-down B-VDD and B-VDDQ together to avoid certain conditions that would result in data corruption.
2.2.13 LPSDRAM B-V SS ground
Ground, B-VSS, is the reference for the LPSDRAM’s core power supply. It must be connected to the system ground.
3 Functional description
can be operated simultaneously with no risk of bus contention. Figure 3. Functional block diagram - A bus
512 Mbit or
1 Gbit Flash
Figure 4. Functional block diagram - B bus
256 Mbit
4 Maximum rating
other relevant quality documents. Table 2. Absolute maximum ratings
5 DC and AC parameters
Figure 5. AC measurement I/O waveform Table 3. Operating and AC measurement conditions
- All voltages are referenced to V SS = 0V.
Figure 6. AC measurement load circuit
- Sampled only, not 100% tested.
characteristic values and illustrations. Table 4. Capacitance
6 Package mechanical
package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 7. TFBGA165 9 × 11 mm - 12 × 15 ball array, 0.65 mm pitch, package outline
Table 5. TFBGA165 9 × 11 mm - 12 × 15 ball array, 0.65 mm pitch, package
7 Part numbering
device, please contact the Numonyx sales office nearest to you. Table 6. Ordering information scheme ZAS = stacked TFBGA165 S stacked footprint.
8 Revision history
Table 7. Document revision history 28-Sep-2006 0.1 Initial release. 06-Oct-2006 0.2 V DDF, VCCP and VDDQ voltage ranges extended to 1.95V. Figure 7, and removed standard packing option from Table 6. 14-Nov-2007 2 Applied Numonyx branding.