M39832

M39832 STMICROELECTRONICS | Alldatasheet

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Technical content

G EF VSS W ERB RP FRB DQ15A–1 BYTE Figure 1. Logic Diagram

256 Kbit Parallel EEPROM Memory

10 YEARS DATA RETENTION

DESCRIPTION

The M39832 is a memory device combining Flash and EEPROM into a single chip and using single supply voltage. The memory is mapped in two arrays: 8 Mbit of Flash memory and 256 Kbit of EEPROM memory. Each space is independant for writing, in concurrent mode the Flash Memory can be read while the EEPROM is being written. An additional 64 bytes of EPROM are One Time Programmable. The M39832 EEPROM memory array is organized in byte only (regardless on the BYTE pin). It may be written by byte or by page of 64 bytes and the integrity of the data can be secured with the help of the Software Data Protection (SDP). TSOP48 (NE) 12 x 20 mm February 1999 1/36 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Warning: NC = Not Connected. Figure 2. TSOP Pin Connections Table 1. Signal Names M29W800 Single Voltage Flash Memory device. on the M39832 internal logic. OTP Row are always accessed Byte-wide (x8).

combination of levels on A0, A1, A6, A12 and A15. disabled and when RP is at a Low level. Data Input/Outputs (DQ8-DQ14 and DQ15A–1). outputs continue to drive the bus. + 0.5V) (for Flash memory array only).

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Table 2. Absolute Maximum Ratings (1)

Figure 3A. Top Boot Block Memory Map and Block Address Table M39832

Figure 3B. Bottom Boot Block Memory Map and Block Address Table M39832

Address Range (x8) Address Range (x16) A18 A17 A16 A15 A14 A13 A12 00000h-0FFFFh 00000h-07FFFh 0000XX X 10000h-1FFFFh 08000h-0FFFFh 0001XX X 20000h-2FFFFh 10000h-17FFFh 0010XX X 30000h-3FFFFh 18000h-1FFFFh 0011XX X 40000h-4FFFFh 20000h-27FFFh 0100XX X 50000h-5FFFFh 28000h-2FFFFh 0101XX X 60000h-6FFFFh 30000h-37FFFh 0110XX X 70000h-7FFFFh 38000h-3FFFFh 0111XX X 80000h-8FFFFh 40000h-47FFFh 1000XX X 90000h-9FFFFh 48000h-4FFFFh 1001XX X A0000h-AFFFFh 50000h-57FFFh 1010XX X B0000h-BFFFFh 58000h-5FFFFh 1111XX X C0000h-CFFFFh 60000h-67FFFh 1100XX X D0000h-DFFFFh 68000h-6FFFFh 1101XX X E0000h-EFFFFh 70000h-77FFFh 1110XX X F0000h-F7FFFh 78000h-7BFFFh 11110X X F8000h-F9FFFh 7C000h-7CFFFh 1111100 FA000h-FBFFFh 7D000h-7DFFFh 1111101 FC000h-FFFFFh 7E000h-7FFFFh 111111X Table 3A. M39832-T Block Address Table M39832

Address Range (x8) Address Range (x16) A18 A17 A16 A15 A14 A13 A12 00000h-03FFFh 00000h-01FFFh 0 0 0 0 0 0 X 04000h-05FFFh 02000h-02FFFh 0 0 0 0010 06000h-07FFFh 03000h-03FFFh 0 0 0 0011 08000h-0FFFFh 04000h-07FFFh 0 0 0 0 1 X X 10000h-1FFFFh 08000h-0FFFFh 0 0 0 1 X X X 20000h-2FFFFh 10000h-17FFFh 0 0 1 0 X X X 30000h-3FFFFh 18000h-1FFFFh 0 0 1 1 X X X 40000h-4FFFFh 20000h-27FFFh 0 1 0 0 X X X 50000h-5FFFFh 28000h-2FFFFh 0 1 0 1 X X X 60000h-6FFFFh 30000h-37FFFh 0 1 1 0 X X X 70000h-7FFFFh 38000h-3FFFFh 0 1 1 1 X X X 80000h-8FFFFh 40000h-47FFFh 1 0 0 0 X X X 90000h-9FFFFh 48000h-4FFFFh 1 0 0 1 X X X A0000h-AFFFFh 50000h-57FFFh 1 0 1 0 X X X B0000h-BFFFFh 58000h-5FFFFh 1 0 1 1 X X X C0000h-CFFFFh 60000h-67FFFh 1 1 0 0 X X X D0000h-DFFFFh 68000h-6FFFFh 1 1 0 1 X X X E0000h-EFFFFh 70000h-77FFFh 1 1 1 0 X X X F0000h-FfFFFh 78000h-7FFFFh 1 1 1 1 X X X Table 3B. M39832-B Block Address Table M39832

Table 4. Basic Operations –E R B = ’1’: no internal writing in in process. fetching opcodes) in the Flash memory array. Reset/Block Temporary Unprotect Input (RP). acheived by pulling RP to VIL for at least tPLPX . PHEL after the rising edge of RP. being programmed or the block(s) being erased. read the output of the memory. control and should be used for device selection. tion entered into the memory.

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc. RD (2,4) Read/Reset Memory Array Addr. (3,7) X Read Memory Array until a new write cycle is initiated. Data F0h Addr. (3,7) Byte AAAAh 5555h AAAAh Read Memory Array until a new write cycle is initiated.Word 5555h 2AAAh 5555h Data AAh 55h F0h AS (4) Auto Select 3+ Addr. (3,7) Byte AAAAh 5555h AAAAh Read Electronic Signature or Block Protection Status until a new write cycle is initiated. See Note 5 and 6.Word 5555h 2AAAh 5555h Data AAh 55h 90h PG Program 4 Addr. (3,7) Byte AAAAh 5555h AAAAh Program Address Read Data Polling or Toggle Bit until Program completes. Word 5555h 2AAAh 5555h Data AAh 55h A0h Program Data BE Block Erase 6 Addr. (3,7) Byte AAAAh 5555h AAAAh AAAAh 5555h Block Address Additiona l Block (8) Word 5555h 2AAAh 5555h 5555h 2AAAh Data AAh 55h 80h AAh 55h 30h 30h FAE Flash Array Erase 6 Addr. (3,7) Byte AAAAh 5555h AAAAh AAAAh 5555h AAAAh Note 9Word 5555h 2AAAh 5555h 5555h 2AAAh 5555h Data AAh 55h 80h AAh 55h 10h ES (10) Erase Suspend 1 Addr. (3,7) X Read until Toggle stops, then read all the data needed from any Block(s) not being erased then Resume Erase. Data B0h ER Erase Resume 1 Addr. (3,7) X Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time Data 30h Notes:1. Commands not interpreted in this table will default to read array mode. 2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation (see Table 14 and Figure 9). 3. X = Don’t Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Flash code. 6. Block Protection Address: A0, at VIL, A1 at VIH and A15-A18 within the Block will output the Block Protection status. 7. For Coded cycles address inputs A11-A18 are don’t care. 8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. 9. Read Data Polling, Toggle bits or FR B until Erase completes. 10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. Table 5A. Flash Instructions (EF=0, EE=1) M39832

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc. WOTP (2) Write OTP Row >3 Addr. Byte 5555h 2AAAh 5555h Addr 1 Addr 2 Addr 3 Addr 4 Word 5555h 2AAAh 5555h Data AAh 55h B0h Byte 1 Byte 2 Byte 3 Byte 4 ROTP (2) Read OTP Row >3 Addr. Byte 5555h 2AAAh 5555h Addr 1 Addr 2 Addr 3 Addr 4 Word 5555h 2AAAh 5555h Data AAh 55h 90h Byte 1 Byte 2 Byte 3 Byte 4 RT Return from OTP Read Addr. X (1) Data F0h SSDP (4) SDP Enable ≥3 Addr. Byte 5555h 2AAAh 5555h Word 5555h 2AAAh 5555h Data AAh 55h A0h SSDP (5) SDP Disable 6 Addr. Byte 5555h 2AAAh 5555h 5555h 2AAAh 5555h Word 5555h 2AAAh 5555h 5555h 2AAAh 5555h Data AAh 55h 80h AAh 55h 20h Notes:1. X = Don’t Care. 2. Once the WOTP has been initiated (first 3 Cycles), from 1 up to 64 bytes can be written in one single write cycle (See Write OTP chapter in following pages). 3. Once the ROTP has been initiated (first 3 Cycles), from 1 up to 64 bytes of the OTP can be read (See Read OTP chapter in following pages). The RT (Return) instruction MUST be sent to the device to exit ROTP mode. 4. Once SDP is set (SSDP instruction sent once), it is necessary to send SSDP prior to any byte or page to be written in the EEPROM array (See Figure 4 and EEPROM array Software Data Protection chapter in following pages). 5. See Figure 5 and EEPROM array Software Data Protection chapter in following pages. Table 5B. EEPROM Instructions (EE=0, EF=1) M39832

1. Block Address must be given on A12-A18 bits.
2. Operation performed on programming equipment.
3. The 65 Bytes User defined EEPROM Identifier are accessed on DQ0-DQ7 with A0 to A5 when

Table 6. User Bus Operations (1) Table 7. Read Electronic Signature (following AS instruction or with A9 = VID)

7 Data

6 Toggle Bit

5 Error Bit ’1’ Program or Erase Error This bit is set to ’1’ in the case of

4 Reserved

3 Erase

can be entered to the P/E.C.

2 Toggle Bit

1 Reserved

0 Reserved

Notes:Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. Table 9. Status Bit Table 8. Read Block Protection with AS Instruction (EF = 0, EE = 1)

W or EF (EE) whichever occurs first. levels applied on address inputs (A0, A1, A6). addressing the EEPROM array. Figure 4. EEPROM SDP Enable Flowcharts

Read the EEPROM Identifier The EEPROM identifier (64 bytes, user defined) can be read with a single Read operation with A6 = ’0’ and A9 = VID (See Table 6). When accessing the 64 Bytes of EEPROM Identi- fier, the only LSB addresses are decoded. The LSB addresses are A0 to A5 when BYTE = ’1’ (x16) and A–1 to A4 when BYTE = ’0’ (x8). Each Byte of the EEPROM identifier can be individually accessed in read or write mode. Read the OTP Row The OTP row is mapped in the EEPROM array EE = ’0’, EF = ’1’). Read of the OTP row (64 bytes) is by an instruction (ROTP) composed of three specific Write operations of data bytes at three specific memory locations (each location in a dif- ferent page) before reading the OTP row content (See Table 5B). When accessing the OTP row, only the LSB ad- dresses are decoded and A6 must be ’0’. The LSB addresses are A0 to A5 when BYTE = ’1’ (x16) and A–1 to A4 when BYTE = ’0’ (x8). Each Read of the OTP row has to be followed by the (RT) Return instruction (See Table 5B). Read the Flash Block Protection Status Reading the Flash block protection status is by a read operation immediatly following the AS instruc- tion (See Table 5A and Table 8). A12-A18 define the Flash block whose protection has to be veri- fied. This Read operation will output a 01h if the Flash block is protected and a 00h if the Flash block is not protected. The Flash block protection status can also be verified with a single Read operation (see chapter: Flash array specific features), with V ID on A9 (See Table 6 and Table 8). Read the Status Bits The M39832 provides several Write operation status flags which may be used to minimize the application write (or erase or program) time. These signals are available on the I/O port bits when programming (or erasing) are in progress. It should be noted that the Ready/Busy pins also reflects the status of the EEPROM Write and the Flash Pro- gramming/Erasing. Data Polling flag, DQ7. When Erasing or Pro- gramming into the Flash block (or when Writing into the EEPROM block), bit DQ7 outputs the comple- ment of the bit being entered for Program- ming/Writing on DQ7. Once the Program instruc- tion or the Write operation is performed, the true logic value is read on DQ7 (in a Read operation). Flash memory block specific features: – Data Polling is effective after the fourth W pulse (for programming) or after the sixth W pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. – During an Erase instruction, DQ7 outputs a ’0’. After completion of the instruction, DQ7 will out- put the last bit programmed (that is a ’1’ after erasing). – if the byte to be programmed is in a protected Flash sector, the instruction is ignored. – If all the Flash sectors to be erased are pro- tected, DQ7 will be set to ’0’ for about 100µs, and then return to the previous addressed byte. No erasure will be performed. – if all sectors are protected, a Bulk Erase instruc- tion is ignored. Toggle flag, DQ6. The M39832 also offers another way for determining when the EEPROM write or the Flash memory Program instruction is com- pleted. During the internal Write operation, the DQ6 will toggle from ’0’ to ’1’ and ’1’ to ’0’ on subsequent attempts to read any byte of the memory, when either G , EE or EF is low. When the internal cycle is completed the toggling will stop and the data read on DQ0-DQ7 is the addressed memory byte. The device is now acces- sible for a new Read or Write operation. The opera- tion is completed when two successive reads yield the same output data. Flash memory block specific features: a. The Toggle bit is effective after the fourth W pulse (for programming) or after the sixth W pulse (for Erase). b. If the byte to be programmed belongs to a pro- tected Flash sector, the instruction is ignored and: – if all the Flash sectors selected for erasure are protected, DQ6 will toggle to ’0’ for about 100µs, and then return to the previous ad- dressed byte. – if all sectors are protected, the Bulk Erase in- struction is ignored. M39832

Enable G High. Addresses are latched on the falling edge of W, EE whichever occurs last. Once initiated, the write operation is internally timed until completion, that is during a time tW . The status of the write operation can be found by reading the Data Polling and Toggle bits (as de- tailed in the READ chapter) or the ERB output. This Ready/Busy output is driven low from the write of the byte being written until the completion of the internal Write sequence. Write a Page in EEPROM Array The Page write allows up to 64 bytes within the same EEPROM page to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A6-A14 when BYTE is high (x16) or A5-A13 when BYTE is low (x8) must be the same for all bytes. Once initiated, the Page write opera- tion is internally timed until completion, that is dur- ing a time tWC . The status of the write operation can be seen by reading the Data Polling and Toggle bits (as de- tailed in the READ chapter) or the ER B output. This Ready/Busy output is driven low from the write of the first byte to be written until the completion of the internal Write sequence. A Page write is composed of successive Write operations which must be sequenced within a time period (between two consecutive Write operations) that is smaller than the t WLWL value. If this period of time exceeds the tWLWL value, the internal program- ming cycle will start. EEPROM Array Software Data Protection A protection instruction allows the user to inhibit all write modes to the EEPROM array: the Software Data Protection (referenced as SDP in the follow- ing). The SDP feature is useful for protecting the EEPROM memory from inadvertent write cycles that may occur during uncontrolled bus conditions. The M39832 is shipped as standard in the unpro- tected state meaning that the EEPROM memory contents can be changed by the user. After the SDP enable instruction, the device enters the Protect Mode where no further write operations have any effect on the EEPROM memory contents. The device remains in this mode until a valid SDP disable instruction is received whereby the device reverts to the unprotected state. To enable the Software Data Protection, the device has to be written (with a Page Write) with three specific data bytes at three specific memory loca- tions (each location in a different page) as shown in Figure 4 and Table 5B. This sequence provides an unlock key to enable the write action, and, at the same time, SDP continues to be set. Any further Write in EEPROM when the SDP is set will use this same sequence of three specific data bytes at three specific memory locations followed by the bytes to write. The first SDP enable sequence can be di- rectly followed by the bytes to written. Similarly, to disable the Software Data Protection the user has to write specific data bytes into six different locations with a Page Write addressing different bytes in different pages, as shown in Fig- ure 5 and Table 5B. The Software Data Protection state is non-volatile and is not changed by power on/off sequences. The SDP enable/disable instructions set/reset an inter- nal non-volatile bit and therefore will require a write time t WC , This Write operation can be monitored only on the Toggle bit (status bit DQ6) and the ERB pin. The Ready/Busy output is driven low from the first byte to be written (that is the first Write AAh, @5555h of the SDP set/reset sequence) until the completion of the internal Write sequence. Write OTP Row Writing (only one time) in the OTP row (64 bytes) is enabled by an instruction (WOTP). This instruc- tion is composed of three specific Write operations of data bytes at three specific memory locations (each location in a different page) followed by the the data to store in the OTP row (refer to Table 5B). When accessing the OTP row, the only LSB ad- dresses are decoded and A6 must be ’0’. The LSB addresses are A0 to A5 when BYTE = ’1’ (x16) and A–1 to A4 when BYTE = ’0’ (x8). Once at least one Byte of the OTP row has been written (even with FFh), the whole row becomes Read only. Write the EEPROM Block Identifier The EEPROM block identifier (64 Bytes) can be written with a single Write operation with A6 = ’0’ and the V ID level on A9 (see Table 6). When ac- cessing the 64 Bytes of EEPROM Identifier, the only LSB addresses are decoded. The LSB ad- dresses are A0 to A5 when BYTE = ’1’ (x16) and A-1 to A4 when BYTE = ’0’ (x8). Each Byte of the EEPROM identifier can be individually accessed in read or write mode. PROGRAM in the Flash ARRAY It should be noted that writing data into the EEPROM array and the Flash array is not per- formed in a similar way: the Flash memory requires an instruction (see Instruction chapter) for Erasing and another instruction for Programming one (or more) byte(s) or word(s), the EEPROM memory is directly written with a simple operation (see Opera- tion chapter). M39832

Program (PG) Instruction. This instruction uses four write cycles. Both for Byte-wide configuration and for Word-wide configuration. The Program command A0h is written to address AAAAh in the Byte-wide configuration or to address 5555h in the Word-wide configuration on the third cycle after two Coded cycles. A fourth write operation latches the Address on the falling edge of W or EF and the Data to be written on the rising edge and starts the internal operation. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing ’0’ in place of ’1’. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Program- ming at an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will toggle at the address being programmed. Auto Select (AS) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 90h to address AAAAh in the Byte-wide configuration or address 5555h in the Word-wide configuration for command set-up. A subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of A0 and A1. The manufacturer code is output when the addresses lines A0 and A1 are Low, the Flash code for Top Boot or Bottom Boot is output when A0 is High with A1 Low. The AS instruction allows access to the block pro- tection status. After giving the AS instruction, A0 is set to V IL with A1 at VIH, while A12-A18 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. The ERASE in the Flash ARRAY Flash Array Erase (FAE) Instruction. This in- struction uses six write cycles. The Erase Set-up command 80h is written to address AAAAh in the Byte-wide configuration or the address 5555h in the Word-wide configuration on the third cycle after the two Coded cycles. The Flash Array Erase Con- firm command 10h is similarly written on the sixth cycle after another two Coded cycles. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as it will be done automatically before erasing it to FFh. Read opera- tions after the sixth rising edge of W or EF output the Status Register bits. During the execution of the erase, Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bits DQ2 and DQ6 toggle during erase operation and stop when erase is completed. After completion, the Status Bit DQ5 returns ’1’ if there has been an Erase Failure. Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address AAAh in the Byte-wide configuration or address 5555h in the Word-wide configuration on third cycle after the two Coded cycles. The Block Erase Confirm com- mand 30h is similarly written on the sixth cycle after another two Coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Addi- tional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cy- cles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the Block(s) are being erased. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as it will be done automatically before erasing it to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits. During the execution of the erase , the memory accepts only the Erase Suspend ES and Read/Re- set RD instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The Toggle bit DQ2 and DQ6 toggle during the erase operation. They stop when erase is completed. After completion the Status bit DQ5 returns ’1’ if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruc- tion is necessary in order to reset the memory. M39832

Figure 8. Block Protection Flowchart

Figure 9. Block Unprotecting Flowchart reads, A6 must be kept at VIL.

Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A12-A18 is protected. Any attempt to program or erase a protected block will be ignored by the device. Remarks: – The Verify operation is a read with a simulated worst case conditions. This allows a guarantee of the retention of the Protection status – During the application life, the block protection status can be accessed with a regular Read instruction without applying a "high voltage" V ID on A9. This instruction is detailed in Table 5 and Table 8. Blocks Unprotection (See Figure 9). All protected blocks can be unprotected simultaneously on pro- gramming equipment to allow updating of bit con- tents. All blocks must first be protected before the unprotection operation. Block unprotection is acti- vated when A9, G and E are at VID and A12, A15 at VIH. Unprotection is initiated by the edge of W falling to VIL. After a delay of 10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A12-A18 has been succesfully unprotected. Each block must be sepa- rately verified by giving its address in order to ensure that it has been unprotected. Remarks: – The Verify operation is a read with a simulated worst case conditions. This allows a guarantee of the retention of the Protection status – During the application life, the Block protection status can be accessed with a regular Read instruction without "high voltage" V ID on A9. This instruction is detailed in Table 5 and Table 8. Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporary un- protection mode is activated by bringing RP to V ID. During the temporary unprotection mode the pre- viously protected blocks are unprotected. A block can be selected and data can be modified by executing the Erase or Program instruction with the RP signal held at V ID. When RP is returned to VIH, all the previously protected blocks are again pro- tected. Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded cycles. Subsequent read operations will read the memory array addressed and output the data read. A wait state of 10ms is necessary after Read/Reset prior to any valid read if the memory was in an Erase mode when the RD instruction is given. GLOSSARY Array: EEPROM array (256 Kbit) or Flash array (8 Mbit) Block: part of the Flash array (See Figure 3A and 3B). Page: 64 bytes of EEPROM Write and Program: Writing (into the EEPROM array) and programming (the Flash array is not performed in a similar way: – the Flash memory requires an instruction (see Instruction chapter) for Erasing and another in- struction for Programming one (or more) byte(s) or word(s) – the EEPROM memory is directly written with a simple operation (see Operation chapter). SDP: Software Data Protection. Used for protect- ing the EEPROM array against false Write opera- tions (as in noisy environments). POWER SUPPLY and CURRENT CONSUMP- TION Power Up. The M39832 internal logic is reset upon a power-up condition to Read memory status. Any Write operation in EEPROM is inhibited during the first 5 ms following the power-up. Either EF, EE or W must be tied to VIH during Power-up for the maximum security of the data contents and to remove the possibility of a byte being written on the first rising edge of EF, EE or W. Any write cycle initiation is locked when Vcc is below V LKO . Supply Rails. Normal precautions must be taken for supply voltage decoupling, each device in a system should have the V CC rail decoupled with a 0.1µF capacitor close to the VCC and VSS pins. The printed circuit board trace width should be sufficient to carry the VCC program and erase currents re- quired. M39832

Note: 1. When reading the Flash block when an EEPROM byte(s) is under a write cycle, the supply current is ICC1 + ICC5 . Table 12. DC Characteristics

Figure 12. Read Mode AC Waveforms

Notes:1. Sampled only, not 100% tested. 2.G may be delayed by up to tELQV - tGLQV after the falling edge of EE (or EF) without increasing tELQV . Table 13. Read AC Characteristics

Figure 13. Write AC Waveforms, W Controlled Notes:Address are latched on the falling edge of W, Data is latched on the rising edge of W. E is either EF when EE = VIH or EE when EF = VIH.

Figure 14. Write AC Waveforms, E Controlled Notes: Address are latched on the falling edge of E, Data is latched on the rising edge of E. E is either EF when EE = VIH or EE when EF = VIH.

1. Chip Enable means (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL).
2. With a 3.3KΩ pull-up resistor.

Table 14. Write AC Characteristics, Write Enable Controlled

Notes:1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV .

1. With a 3.3KΩ pull-up resistor.

Table 15. Write AC Characteristics, EE or EF Controlled

Figure 15. Data Polling DQ7 AC Waveforms Notes:1. All other timings are as a normal Read cycle.

1. DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period.

WHQ7V is the Program or Erase time.

1. During erasing operation Byte address must be within Sector being erased.

E is either EF when EE = VIH or EE when EF = VIH.

Notes:1. All other timings are defined in Read AC Characteristics table.

1. tWHQ7V is the Program or Erase time.

Table 16. Data Polling and Toggle Bit AC Characteristics (1) Table 17. Program, Erase Times and Program, Erase Endurance Cycles (Flash Block)

Figure 16. Data Toggle DQ6 AC Waveforms Notes:1. All other timings are as a normal Read cycle. 2.E is either EF when EE = VIH or EE when EF = VIH.

Figure 17. EEPROM Page Write Mode AC Waveforms, W Controlled

ORDERING INFORMATION SCHEME Devices are shipped from the factory with the memory content set at all "1’s" (FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Array Matrix T Top Boot B Bottom Boot Speed 12 120ns 15 150ns Operating Voltage W 2.7V to 3.6V Package NE TSOP48 12 x 20mm Option T Tape & Reel Packing Temp. Range 1 0 to 70 °C 6 –40 to 85 °C Example: M39832 - B 15 W NE 6 T M39832

E 1 N CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 11.90 12.10 0.469 0.476 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N4 8 4 8 CP 0.10 0.004 Drawing is not to scale. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm M39832

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