M39432 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 28
Technical content
Single Chip 4 Mbit Flash Memory and
256 Kbit Parallel EEPROM
■ Multiple Memories on a Single Chip: – 4 Mbit Flash Memory (organised as 8 sectors) – 256 Kbit EEPROM – 64 Byte One Time Programmable Memory ■ CONCURRENT Mode (Read Flash while writing to EEPROM) ■ WRITE, PROGRAM and ERASE Status Bits ■ 2.7V to 3.6V Single Supply Voltage for PROGRAM, ERASE and READ Operations ■ 100 ns Access Time (Flash and EEPROM blocks) ■ Low Power Consumption –6 0 µA Stand-by mode (maximum) – Deep Power Down mode: 6 µA (maximum), 200 nA (typical) ■ Standard Flash Memory Package ■ 100,000 Erase/Write Cycles (minimum) ■ 10 Year Data Retention (minimum)
DESCRIPTION
The M39432 is a single supply voltage memory device combining Flash memory and EEPROM on a single chip. The memory is mapped in two Figure 1. Logic Diagram Table 1. Signal Names
bytewise or by a page at a time (up to 64 bytes). help of the Software Data Protection (SDP). locations in the Flash memory block. – Verify the Flash Sector Protection Status. Figure 2. TSOP Connections Note: 1. NC = Not Connected. Table 2. Absolute Maximum Ratings Program and other relevant quality documents.
- Minimum voltage may undershoot to –2 V, during transition and for less than 20 ns.
Chip Enable (EF or EE) are driven low. outputs are disabled (G driven high). level, while the outputs continue to drive the bus. state when the Output Enable (G) is high. VID (as specified in Table 11). Program or Erase cycle in the Flash memory. Figure 3. Flash Block Sectors
up, power down and during power surges. one Chip Enable (EF or EE) must be driven low. these areas is summarized in Table 4. or EF (or EE) whichever occurs first. one of the instructions shown in Table 4. the section entitled “Instructions” on this page). Table 3. Operations
Table 4. Instructions 1 Note: 1.AAh @ 5555h means “Write the value AAh at the address 5555h”.
- This instruction can also be performed as a Verify operation with A9=VID (please see the section entitled “Flash Sector Protection
and Unprotection” on page 18).
- Addresses of additional sectors to be erased must be entered within a time-out of 80µs of each other.
10 AAh
“Writing the OTP Row” on page 11. number of bytes have been properly received. address 2AAAh, in the second cycle. that the instruction is the intended one. EEPROM are inhibited for the first 5 ms. VIH during the power-up process. Supply Current until the cycle is complete. Table 5. Device Identifier Operations
the memory enters the Automatic Stand-by state. mode until the next Reset instruction is executed. using the specific instruction shown in Table 4. accessible, until a Return instruction is executed. (Flash memory block or EEPROM block). one Chip Enable (EF or EE) must be driven low. specified in Table 5 applied to A0, A1, A6. being applied to A0, A1, A6, A16, A17 and A18. Read operation or using a Read instruction. The OTP row is mapped in the EEPROM block. Table 6. Status Bits Note: 1.X = Not a guaranteed value, can be read either as ‘1’ or ‘0’. Figure 4. Data Polling Flowchart
Flash sector as the one that is being erased. completed, is shown in the flowchart in Figure 5. Table 4. This consists of the writing of three prefix to reading the OTP row content. decoded (of which A6 must be low). the Return instruction (as shown in Table 4). ports (DQ0-DQ7), as summarized in Table 6. Figure 5. Data Toggle Flowchart
Figure 6. EEPROM SDP-Enable Flowcharts Table 7. Summary of the Use of Status Bits addressed byte. No erasure is performed.
- If all the sectors to be erased are protected, DQ6 is reset to 0 for about 100 µs, then returns to the state it was in for the previously
addressed byte. No erasure is performed.
Error flag, DQ5 (Flash memory block only). reset after a Reset instruction. controller operation during a Sector Erase cycle. block is performed as an operation (see Table 3). taken low, and the output enable (G) is held high. EE (whichever occurs the later). period (tWHRH ) is specified in Table 16. WLWL value (as specified in Table 16). Figure 7. EEPROM SDP-Disable Flowchart Table 8. Write the EEPROM Block Identifier
address (A6-A18 must be the same for all bytes). controlled phase of the Page Write cycle. caused under uncontrolled bus conditions. then returns to its unprotected state. different page) as shown in Table 4 and Figure 6. pages, as shown in Figure 7. WC ) as for the non-volatile memory. completion of the internal Page Write sequence. Table 4. These instructions write data bytes at and 64 bytes) that is to be stored in the OTP row. these, A6 must be held at 0. performed using the instruction shown in Table 4. needed when erasing a sector of Flash memory. programmed a byte at a time. Erase followed by Byte Write. The Flash memory block, though, is different.
Figure 8. Sector Protection Flowchart Note: 1. The Verify Sector Protection Status operation is specified in Table 9.
Table 9. Flash Sector Protection Table 10. Flash Unprotection (all sectors) the sectors in the Flash memory block. finished (as indicated on DQ7 and DQ6).
Figure 9. Sector Unprotecting Flowchart Note: 1. The Verify Sector Status operation is specified in Table 10.
- A6 is kept at VIH during unprotection algorithm in order to secure best unprotection verification. During all other protection status
reads, A6 must be kept at VIL.
Table 13. Read Mode AC Characteristics Note: 1. Sampled only, not 100% tested.
- G may be delayed by up to tELQV - tGLQV after the falling edge of EE (or EF) without increasing tELQV .
Table 14. Input and Output Parameters1 (TA = 25 °C, f = 1 MHz) Note: 1. Sampled only, not 100% tested.
Figure 12. Read Mode AC Waveforms (with Write Enable, W, high)
Figure 13. Write Mode AC Waveforms (W controlled) Note: 1. E signifies EF when EE = VIH, and it signifies EE when EF = VIH.
- Addresses are latched on the falling edge of W, Data are latched on the rising edge of W.
to Erase Resume and Reset instructions. sectors that was being erased. writing 30h to any address (as shown in Table 4). shown in Figure 8 and Table 9. Flash sector is ignored by the device. together (from sector 0 up to sector 7). lines, as shown in Table 10.
Figure 14. Write Mode AC Waveforms (EE or EF controlled) Note: 1. E signifies EF when EE = VIH, and it signifies EE when EF = VIH.
- Addresses are latched on the falling edge of E, Data are latched on the rising edge of E.
shown by the sequence in Figure 9. Protection instruction (as shown in Table 4). overwriting can be performed.
Table 15. Write Mode AC Characteristics (W controlled) Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV .
- With a 3.3 kΩ pull-up resistor.
- Chip Enable means (EE,EF) = (VIL,VIH) or (EE,EF) = (VIH,VIL).
- Sampled only, not 100% tested.
Table 16. Write Mode AC Characteristics (EE or EF controlled) Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV .
- With a 3.3 kΩ pull-up resistor.
Figure 15. Data Polling DQ7 AC Waveforms Note: 1. All other timings are as a normal Read cycle.
- tWHQ7V is the Program or Erase time.
- DQ7 and DQ0-DQ6 can become valid at any point during the Data Output Valid period.
- During the erasing operation, the Byte address must be within the Sector being erased.
- E signifies EF when EE = VIH, and it signifies EE when EF = VIH.
Table 17. Data Polling and Toggle Bit AC Characteristics 1 Note: 1. All other timings are defined in Table 13.
- tWHQ7V is the Program or Erase time.
Table 18. Program, Erase Times and Program, Erase Endurance Cycles (Flash Block)
Figure 16. Data Toggle DQ6 AC Waveforms Note: 1. All other timings are as a normal Read cycle.
- E signifies EF when EE = VIH, and it signifies EE when EF = VIH.
Table 19. Ordering Information Scheme with the 1 or 5 temperature ranges (0 to 70°C or –20 to 85°C) since these are covered by the 6 temperature range. Figure 17. EEPROM Page Write Mode AC Waveforms (W Controlled)
ORDERING INFORMATION
Devices are shipped from the factory with the memory content set at all ‘1’s (FFh). The notation used for the device number is as shown in Table 19. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
Figure 18. TSOP40 (NC) Note: 1. Drawing is not to scale. Table 20. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20 mm
Table 21. Revision History and -25 ranges removed. Narrowest temperature ranges 1 and 5 removed.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com