M39208 STMICROELECTRONICS | Alldatasheet
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G EF VSS W Figure 1. Logic Diagram
10 YEARS DATA RETENTION
DESCRIPTION
The M39208 is a memory device combining Flash and EEPROM into a single chip and using single supply voltage. The memory is mapped in two blocks: 2 Mbit of Flash memory and 64 Kbit of EEPROM memory. Each space is independant for writing, in concurrent mode the Flash Memory can be read while the EEPROM is being written. A0-A17 Address Inputs DQ0-DQ7 Data Input / Outputs EE EEPROM Block Enable EF Flash Block Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground Table 1. Signal Names This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Table 2. Absolute Maximum Ratings (1) Figure 2. TSOP Pin Connections of the data can be secured with the help of the Software Data Protection (SDP). EE and EF inputs respectively. and Write Enable W are driven active.
Figure 3. Flash Block Sectors outputs continue to drive the bus. + 0.5V) (for Flash memory block only). read the output of the memory. control and should be used for device selection. tion entered into the memory (see Table 4).
Table 3. Basic Operations byte is an instruction (see Instructions paragraph). of W or EF (EE) whichever occurs first. shorter than the time-out value. These instructions are detailed in Table 4. followed by a command byte or a confirmation byte. at address 2AAAh during the second cycle.
Notes:1. AAh @5555h means Write byte AAh at address 5555h.
- This instruction can also be performed as a simple Read operation with A9=VID (refer to READ chapter).
- Additional blocks to be erased must be entered within 80µs.
Table 4. Instructions (1)
unless a further Return instruction is decoded. sleep mode until a Reset instruction is decoded. first 5 ms following the power-up. EEPROM block) status and identifiers. methods: a Read operation or a Read instruction. methods: a Read operation or a Read instruction. ID level on A9 (see Table 5). Block Identifier VIL VIH VIL VIH VIH VIL VIL VID Don’t Care t.b.d. Table 5. Device Identifiers
ferent page) before reading the OTP row content. the Return instruction (see Table 4). 00h if the Flash sector is not protected. programming (or erasing) are in progress. – During an Erase instruction, DQ7 outputs a ’0’. Flash sector, the instruction is ignored. Note: X = Not guaranteed value, can be read either ’1’ or ’0’. Table 6. Status Bit
Erase Time-out flag, DQ3 (Flash block only). Programming a byte in the Flash block). edge of W, EE whichever occurs last. timed until completion, that is during a time tW . tion of the internal Write sequence. Figure 4. EEPROM SDP Enable Flowcharts
tailed in the READ chapter). that may occur during uncontrolled bus conditions. effect on the EEPROM memory contents. reverts to the unprotected state. rectly followed by the bytes to written. only on the Toggle bit (status bit DQ6). Figure 5. SDP disable Flowchart Table 7. Write the EEPROM Block Identifier
Data Polling. Polling on DQ7 is a method of check- ing whether a Program or an Erase instruction is in progress or completed (see Figure 6). When a Program instruction is in progress, data bit DQ7 is the complement of the original data bit 7; when DQ7 is identical to the old data and the Error bit DQ5 is still ’0’, the instruction is complete. To de- termine if DQ7 is valid, each poll must store the original data for comparison, and if they are the same, it can be considered that the operation was successful. The Error bit DQ5 is checked to ensure timing limits have not exceeded. When an Erase operation is in progress, DQ7 is always ’0’, and will be ’1’ when finished, so long as DQ5= ’0’. In all cases, when DQ5 is ’1’, DQ7 should be checked again, in case DQ7 changed simultane- ously with DQ5. If DQ7 = true data (Program) or DQ7 = ’1’ (Erase), the operation is successful and execution should return to the caller. A suggested second read will provide all true data (Program) or all FFh (Erase). Otherwise, this should be flagged as an error, and the device should be Reset. Data Toggle. Checking the Toggle bit DQ6 is an alternative method of checking if Program or Erase operations are in progress or completed (see Fig- ure 7). When an operation is in progress, data bit DQ6 constantly toggles for successive read opera- tions. When DQ6 no longer toggles and the Error bit DQ5 is ’0’, the operation is completed. To deter- mine if DQ6 has toggled, each polling action re- quires 2 consecutive read operations of the data, and if the data read is the same, it can be consid- ered that the operation was successful. The Error bit DQ5 is checked to ensure timing limits have not been exceeded. In all cases, when DQ5 is ’1’, DQ6 should be checked again, in case DQ6 has changed simultaneously with DQ5. If DQ6 has stopped toggling, the operation is successful and execution should return to the caller. A suggested second read will provide all true data (Program) or all FFh (Erase). Otherwise, this event should be flagged as an error, and the device should be Reset. ERASE in the Flash BLOCK It should be noted that: a. Programming any byte of one Flash sector (or bulk) requires that the Flash sector (or bulk) has been previously erased (once for all bytes within the sector or bulk) with the correct instruction (see Instructions chapter). b. Writing in the EEPROM memory is an operation triggering an automatic sequencing of byte erase followed by a byte write. Writing in EEPROM does not require a specific erase operation before writ- ing. Bulk Erase Instruction. The Bulk Erase instruc- tion uses six write operations followed by Read operations of the status register bits, as described in Table 4. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may checked by reading the status bits DQ5, DQ6 and DQ7, as detailed in the "PROGRAM in the Flash BLOCK" chapter. The Error bit (DQ5) returns a ’1’ if there has been an Erase Failure (maximum num- ber of erase cycles have been executed). It is not necessary to program the array with 00h, the M39208 will automatically do this before eras- ing to FFh. During the execution of the Bulk Erase instruction, the Flash block logic does not accept any instruc- tion. Sector Erase in Flash Block. The Sector Erase instruction uses six write operations, as described in Table 4. Additional Flash Sector Erase confirm commands and Flash sector addresses can written subsequently to erase other Flash sectors in par- allel, without further coded cycles, if the additional instruction is transmited in a shorter time than the timeout period to end of period. The input of a new Sector Erase instruction will restart the time-out period. The status of the internal timer can be monitored through the level of DQ3 (Erase time-out bit), if DQ3 is ’0’ the Sector Erase instruction has been re- ceived and the timeout is counting; if DQ3 is ’1’, the timeout has expired and the M39208 is erasing the Flash sector(s). Before and during Erase timeout, any instruction different than Erase suspend and Erase Resume will abort the instruction and reset the device to read array mode. It is not necessary to program the Flash sector with 00h as the M39208 will do this automatically before erasing (byte = FFh). During a Sector Erase, the memory status may be checked by reading the status bits DQ5, DQ6 and DQ7, as detailed in the "Program instruction" chap- ter. During the execution of the erase instruction, the Flash block logic accepts only the Reset and Erase Suspend instructions (erasure of one Flash sector may be suspended, in order to read data from another Flash sector, and then resumed). M39208
Table 8. Flash Sector Protection Table 9. Flash Unprotection Read from Flash sector not being erased is valid. at any address (see Table 4). be separately protected against Program or Erase. sector will be ignored by the device. on A9. This instruction is detailed in Table 4.
Figure 8. Sector Protection Flowchart
Figure 9. Sector Unprotecting Flowchart reads, A6 must be kept at VIL.
Note: 1. When reading the Flash block when an EEPROM byte(s) is under a write cycle, the supply current is ICC1 + ICC5 . Table 12. DC Characteristics simple operation (see Operation chapter). tions (as in noisy environments).
Figure 12. Read Mode AC Waveforms
Notes:1. Sampled only, not 100% tested. 2.G may be delayed by up to tELQV - tGLQV after the falling edge of EE (or EF) without increasing tELQV . Table 13. Read AC Characteristics
Figure 13. Write AC Waveforms, W Controlled Notes:Address are latched on the falling edge of W, Data is latched on the rising edge of W. E is either EF when EE = VIH or EE when EF = VIH.
Figure 14. Write AC Waveforms, E Controlled Notes: Address are latched on the falling edge of E, Data is latched on the rising edge of E. E is either EF when EE = VIH or EE when EF = VIH.
- Chip Enable means (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL).
Table 14. Write AC Characteristics, Write Enable Controlled
Notes:1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV . Table 15. Write AC Characteristics, EE or EF Controlled
Figure 15. Data Polling DQ7 AC Waveforms Notes:1. All other timings are as a normal Read cycle.
- DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period.
WHQ7V is the Program or Erase time.
- During erasing operation Byte address must be within Sector being erased.
E is either EF when EE = VIH or EE when EF = VIH.
Notes:1. All other timings are defined in Read AC Characteristics table. Table 16. Data Polling and Toggle Bit AC Characteristics (1) Table 17. Program, Erase Times and Program, Erase Endurance Cycles (Flash Block)
Figure 16. Data Toggle DQ6 AC Waveforms Notes:1. All other timings are as a normal Read cycle. 2.E is either EF when EE = VIH or EE when EF = VIH.
Figure 17. EEPROM Page Write Mode AC Waveforms, W Controlled
ORDERING INFORMATION SCHEME Devices are shipped from the factory with the memory content set at all "1’s" (FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Speed -10 100ns -12 120ns -15 150ns Operating Voltage W 2.7V to 3.6V Package NA TSOP32 8 x 20mm NB TSOP32 8 x 14mm Temp. Range 1 0 to 70 °C 5 –20 to 85 °C 6 –40 to 85 °C Option T Tape & Reel Packing Example: M39208 -15 W NA 1 T M39208
E 1 N CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 13.80 14.20 0.543 0.559 D1 12.30 12.50 0.484 0.492 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 Drawing is not to scale. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm M39208
E 1 N CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 Drawing is not to scale. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm M39208
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