M37736EHBGS

M37736EHBXXXGP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

l Low power dissipation (at 25 MHz frequency) l 12-bit watchdog timer l Programmable input/output, output APPLICATION Control devices for general commercial equipment such as office automation, office equipment, and others. Control devices for general industrial equipment such as communication equipment, and others. Note. Do not use the windowed EPROM version for mass production, because it is a tool for program development (for evaluation). PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS

DESCRIPTION

The M37736EHBXXXGP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the PROM, RAM, multiple-function timers, serial I/O, A-D converter, and others. In the M37736EHBXXXGP, as the multiplex method of the external bus, either of 2 types can be selected. The M37736EHBXXXGP has the same function as the M37736MHBXXXGP except that the built-in ROM is PROM. (Refer to the basic function blocks description.) For program development, the M37736EHBGS with erasable ROM that is housed in a windowed ceramic LCC is also provided.

FEATURES

l Instruction execution time PIN CONFIGURATION (TOP VIEW) ↔ P23/A19/A3/D3 ↔ P24/A20/A4/D4 ↔ P25/A21/A5/D5 ↔ P26/A22/A6/D6 ↔ P27/A23/A7/D7 ↔ P30/R/W/WEL ↔ P31/BHE/WEH ↔ P32/ALE ↔ P33/HLDA → EVL0 → EVL1 M37736EHBXXXGP VCC VSS → E/RDE → XOUT ← XIN ← RESET ← BSEL ← CNV SS ← BYTE ↔ P40/HOLD ↔ P41/RDY 100 P86/RXD 1 ↔ P85/CLK1 ↔ P84/CTS1/RTS1 ↔ P83/TXD 0 ↔ P82/RXD 0/CLKS0 ↔ P81/CLK0 ↔ P80/CTS0/RTS0/CLKS1 ↔ VCC AVCC VREF → AV SS VSS P77/AN7/XCIN ↔ P76/AN6/XCOUT ↔ P75/AN5/ADTRG ↔ P74/AN4 ↔ P73/AN3 ↔ P72/AN2 ↔ P71/AN1 ↔ P70/AN0 ↔ ↔ P92/RXD 2 → P93/TXD 2 → P94 ↔ P87/TXD 1 ↔ P90/CTS2 ↔ P91/CLK2 → P95 → P96 → P97 ↔ P00/A0/CS0 ↔ P01/A1/CS1 ↔ P02/A2/CS2 ↔ P03/A3/CS3 ↔ P04/A4/CS4 ↔ P05/A5/RSMP ↔ P06/A6/A16 ↔ P07/A7/A17 ↔ P10/A8/D8 ↔ P11/A9/D9 ↔ P12/A10/D10 ↔ P13/A11/D11 ↔ P14/A12/D12 ↔ P15/A13/D13 ↔ P16/A14/D14 ↔ P17/A15/D15 ↔ P20/A16/A0/D0 ↔ P21/A17/A1/D1 ↔ P22/A18/A2/D2 P65/TB0IN ↔ P67/TB2IN/f SUB ↔ P66/TB1IN ↔ P64/INT2 ↔ P63/INT1 ↔ P62/INT0 ↔ P61/TA4IN ↔ P60/TA4OUT ↔ P57/TA3IN ↔ P56/TA3OUT ↔ P55/TA2IN ↔ P54/TA2OUT ↔ P53/TA1IN ↔ P52/TA1OUT ↔ P51/TA0IN ↔ P50/TA0OUT ↔ P107/KI3 ↔ P106/KI2 ↔ P105/KI1 ↔ P104/KI0 ↔ P103 ↔ P102 ↔ P101 ↔ P100 ↔ P47 ↔ P46 ↔ P45 ↔ P44 ↔ P43 ↔ P42/f1 ↔ Outline 100P6S-A

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS M37736EHBXXXGP BLOCK DIAGRAM Clock input XIN Clock output XOUT Clock Generating Circuit Timer TA4(16) RAM 3968 bytes PROM

124 Kbytes

Timer TA3(16) Timer TA2(16) Timer TA1(16) P8(8) Input/Output port P8 P7(8) Input/Output port P7 X CIN XCOUT P6(8) Input/Output port P6 P5(8) Input/Output port P5 P4(8) Input/Output port P4 P3(4) Input/Output port P3 P2(8) Input/Output port P2 P1(8) Input/Output port P1 P0(8) Input/Output port P0 Timer TA0(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) UART2(9) UART1(9) UART0(9) A-D Converter(10) Instruction Register(8) Data Buffer DBH (8) Data Buffer DBL(8) Processor Status Register PS(11) Direct Page Register DPR(16) Stack Pointer S(16) Index Register Y(16) Index Register X(16) Accumulator B(16) Arithmetic Logic Unit(16) Accumulator A(16) Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Incrementer(24) Program Address Register PA(24) Data Address Register DA(24) Instruction Queue Buffer Q2(8) Program Counter PC(16) Incrementer/Decrementer(24) Program Bank Register PG(8) Data Bank Register DT((8) Input Buffer Register IB(16) Address Bus Data Bus(Even) Data Bus(Odd) XCIN XCOUT Enable output E Reset input RESET (0V) VSS (0V) AV SSCNV SS AV CC Reference voltage input VREF Bus method selection input BSEL External data bus width selection input BYTEVCC P9(8) Output port P9 P10(8) Input/Output port P10

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS FUNCTIONS OF M37736EHBXXXGP Memory size Input/Output ports Multi-function timers Interrupts Clock generating circuit Input/Output characteristic Memory expansion 100-pin ceramic LCC (with a window) (100D0) Parameter Functions Number of basic instructions 103 Instruction execution time 160 ns (the fastest instruction at external clock 25 MHz frequency) PROM 124 Kbytes RAM 3968 bytes P0 – P2, P4 – P8, P10 8-bit 5 9 P3 4-bit 5 1 Output port P9 8-bit 5 1 TA0, TA1, TA2, TA3, TA4 16-bit 5 5 TB0, TB1, TB2 16-bit 5 3 Serial I/O (UART or clock synchronous serial I/O) 5 3 A-D converter 10-bit 5 1 (8 channels) Watchdog timer 12-bit 5 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) Supply voltage 5 V ± 10% Power dissipation 47.5 mW (at external clock 25 MHz frequency) Input/Output voltage 5 V Output current 5 mA External bus mode A; maximum 16 Mbytes, External bus mode B; maximum 1 Mbytes Operating temperature range –20 to 85 °C Device structure CMOS high-performance silicon gate process 100-pin plastic molded QFP (100P6S-A)Package M37736EHBXXXGP M37736EHBGS

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS PIN DESCRIPTION XIN Clock input Input Bus method select input XOUT Clock output Output Pin Name Input/Output Functions Vcc, Power source Apply 5 V ± 10% to Vcc and 0 V to Vss. Vss CNVss CNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode._____ RESET Reset input Input When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz- crystal oscillator between XIN and XOUT . When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open._ E Enable output Output This pin functions as the enable signal output pin which indicates the access status in the internal bus. In the external bus mode B and the memory expansion mode or the microprocessor mode,___ this pin output signal RDE . BYTE External data Input In the memory expansion mode or the microprocessor mode, this pin determines whether the bus width external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L” selection input signal is input and an 8-bit width when “H” signal is input. BSEL Input In the memory expansion mode or the microprocessor mode, this pin determines the external bus mode. The bus mode becomes the external bus mode A when “H” signal is input, and the external bus mode B when “L” signal is input. AVcc, Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. AVss source input VREF Reference Input This is reference voltage input pin for the A-D converter. voltage input P00 – P07 I/O port P0 I/O In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output address (A0 – A7)___ ___ ____ at the external bus mode A, and these pins output signals CS 0 – CS 4 and RSMP, and addresses (A16, A17) at the external bus mode B. P10 – P17 I/O port P1 I/O In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output. P20 – P27 I/O port P2 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address is output. When using the external bus mode A, the address is A16 – A23. When using the external bus mode B, the address is A0 – A7. P30 – P33 I/O port P3 I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion__ ___ ____ mode or the microprocessor mode, R/W , BHE , ALE, and HLDA signals are output at the external___ ___ ____ bus mode A, and WEL , WEH , ALE, and HLDA signals are output at the external bus mode B. P40 – P47 I/O port P4 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion____ ___ mode or the microprocessor mode, P40, P41 and P42 become HOLD and RDY input pins, and a clock φ1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port. P50 – P57 I/O port P5 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3. P60 – P67 I/O port P6 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also___ ___ function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock φSUB output pin. P70 – P77 I/O port P7 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. Additionally, P76 and P77 have the function as the output pin (XCOUT ) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. P80 – P87 I/O port P8 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1. P90 – P97 Output port P9 Output Port P9 is an 8-bit I/O port. These ports are floating when reset. When writting to the port latch, these ports become the output mode. P90 – P93 also function as I/O port for UART 2. P100 – P107 I/O port P10 I/O In addition to having the same functions as port P0 in the single-chip mode, P104 – P107 also__ __ function as input pins for key input interrupt input (KI0 – KI3). Output These pins should be left open.EVL0, EVL1 ––

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS Input/Output Input Input Input Input Output Output Input Input Input I/O Input Input Input Input Input Input Input Input Input Input Output PIN DESCRIPTION (EPROM MODE) Functions Supply 5V±10% to VCC and 0V to VSS . Connect to VPP when programming or verifing. Connect to VPP when programming or verifing. Connect to VSS . Connect a ceramic resonator between XIN and XOUT . Keep open. Connect AVCC to VCC and AVSS to VSS . Connect to VSS . Port P0 functions as the lower 8 bits address input (A0 – A7). Port P1 functions as the higher 8 bits address input (A8 – A15). Port P2 functions as the 8 bits data input/output (D0 – D7). P30 functions as the most significant bit address input (A16). Connect to VSS . Connect to VSS . P50, P51, and P52 function as PGM , OE, and CE input pins respectively. Connect P53, P54, P55, and P56 to VCC . Connect P57 to VSS . Connect to VSS . Connect to VSS . Connect to VSS . Connect to VSS . Connect to VSS . Connect to VCC . Keep open. Pin VCC , VSS CNV SS BYTE RESET XIN XOUT E AV CC , AVSS VREF P00 – P07 P10 – P17 P20 – P27 P30 P31 – P33 P40 – P47 P50 – P57 P60 – P67 P70 – P77 P80 – P87 P90 – P97 P100 – P107 BSEL EVL0, EVL1 Name Power supply VPP input VPP input Reset input Clock input Clock output Enable output Analog supply input Reference voltage input Address input (A 0 – A7) Address input (A8 – A15) Data I/O (D0 – D7) Address input (A16) Input port P3 Input port P4 Control signal input Input port P6 Input port P7 Input port P8 Input port P9 Input port P10 BASIC FUNCTION BLOCKS The M37736EHBXXXGP has the same function as the M37736MHB XXXGP except that the built-in ROM is PROM. Refer to the section on the M37736MHBXXXGP.

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS Outline 100P6S-A EPROM MODE The M37736EHBXXXGP features an EPROM mode in addition to_____ its normal modes. When the RESET signal level is “L”, the chip automatically enters the EPROM mode. Table 1 list the correspondence between pins and Figure 1 shows the pin connections in the EPROM mode. The EPROM mode is the 1M mode for the EPROM that is equivalent to the M5M27C101K. When in the EPROM mode, ports P0, P1, P2, P3 0, P50, P51, P52, CNV SS , and BYTE are used for the EPROM (equivalent to the M5M27C101K). When in this mode, the built-in PROM can be programmed or read from using these pins in the same way as with the M5M27C101K. This chip does not have Device Identifier Mode, so that set the corresponding program algorithm. The program area should specify address 01000 16 – 1FFFF16. Connect the clock which is either ceramic resonator or external clock to X IN pin and XOUT pin. Table 1 Pin function in EPROM mode VCC VPP VSS Address input Data I/O ___ CE ___ OE PGM M5M27C101K VCC VPP VSS A0 – A16 D 0 – D7 ___ CE ___ OE PGM M37736EHBXXXGP VCC CNV SS , BYTE VSS Ports P0, P1, P30 Port P2 P52 P51 P50 Fig. 1 Pin connection in EPROM mode 1P67 ↔ P66 ↔ P65 ↔ P64 ↔ P63 ↔ P62 ↔ P61 ↔ P60 ↔ P57 ↔ P56 ↔ P55 ↔ P54 ↔ P53 ↔ P52 ↔ P51 ↔ P50 ↔ P107 ↔ P106 ↔ P105 ↔ P104 ↔ P103 ↔ P102 ↔ P101 ↔ P100 ↔ P47 ↔ P46 ↔ P45 ↔ P44 ↔ P43 ↔ P42 ↔ P24 ↔ P23 ↔ P2253 ↔ P2154 ↔ P2055 ↔ P1756 ↔ P1657 ↔ P1558 ↔ P1459 ↔ P1360 ↔ P1261 ↔ P1162 ↔ P1063 ↔ P0764 ↔ P0665 ↔ P0566 ↔ P0467 ↔ P0368 ↔ P0269 ↔ P0170 ↔ P0071 → P9772 → P9673 → P9574 → P9475 → P9376 ↔ P9277 ↔ P9178 ↔ P9079 ↔ P8780 31 ↔ P41 ↔ P40 ← BYTE CNV SS ← BSEL ← RESET ← XIN → XOUT → E VSS VCC → EVL1 → EVL0 ↔ P33 ↔ P32 ↔ P31 ↔ P30 ↔ P27 ↔ P26 ↔ P25 D 5 D 4 D 3 D 2 D 1 D 0 A15 A13 A12 A11 A10 A14 D 6 D 7 A16 VSS VCC VPP PGM OE CE ∗ : Connect to ceramic oscillation circuit. : It is used in the EPROM mode. 100 AV SS P70 ↔ P71 ↔ P72 ↔ P73 ↔ P74 ↔ P75 ↔ P76 ↔ P77 ↔ VSS VREF → AV CC VCC P80 ↔ P81 ↔ P82 ↔ M37736EHBGP P83 ↔ P84 ↔ P85 ↔ P86 ↔

Notice: This is not a final specification. Some parametric limits are subject to change. the CE or OE pins are in the “H” state. – D7. Set the PGM pin to a “L” level to being programming. number of pulses (0.2 5 X ms). last address has been reached. Table 2. I/O signal in each mode Note 1 : An X indicates either VIL or VIH.

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS tDFP tAH tDH tDS tAS tVPS tVCS tCES tPW tOPW tOES tOE DATA SET DATA OUTPUT VALID PROGRAM VERIFY VIH VIL VIH/VOH VIL/VOL VPP VCC VCC +1 VCC VIH VIL VIH VIL VIH VIL ADDRESS DATA VPP VCC CE PGM OE AC waveforms Programming algorithm flow chart START ADDR=FIRST LOCATION VCC =6.0 V VPP =12.5 V X=0 PROGRAM ONE PULSE OF 0.2 ms X=X+1 X=25? VERIFY BYTE LAST ADDR? VCC =VPP =*5.0 V DEVICE PASSED PROGRAM PULSE OF 0.2X ms DURATION VERIFY ALL BYTE FAIL FAIL DEVICE FAILED FAIL DEVICE FAILED YES PASS YES INCREMENT ADDR NO VERIFY BYTE PASS PASS NO *4.5 V ≤ VCC = VPP ≤ 5.5 V Test conditions for A.C. characteristics Input voltage : VIL = 0.45 V, VIH = 2.4 V Input rise and fall times (10 % – 90 %) : ≤ 20 ns Reference voltage at timing measurement : Input, Output

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS SAFETY INSTRUCTIONS (1) Sunlight and fluorescent lamp contain light that can erase written information. When using in read mode, be sure to cover the transparent glass portion with a seal or other materials (ceramic package product). (2) Mitsubishi Electric corp. provides the seal for covering the transparent glass. Take care that the seal does not touch the read pins (ceramic package product). (3) Clean the transparent glass before erasing. Fingers’ fat and paste disturb the passage of ultraviolet rays and may affect badly the erasure capability (ceramic package product). (4) A high voltage is used for programming. Take care that over- voltage is not applied. Take care especially at power on. (5) The programmable M37736EHBGP that is shipped in blank is also provided. For the M37736EHBGP, Mitsubishi Electric corp. does not perform PROM programming test and screening following the assembly processes. To improve reliability after programming, performing programming and test according to the flow below before use is recommended. ADDRESSING MODES The M37736EHBXXXGP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37736EHBXXXGP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. DATA REQUIRED FOR PROM ORDERING Please send the following data for writing to PROM. (1) M37736EHBXXXGP writing to PROM order confirmation form (2) 100P6S mark specification form (3) ROM data (EPROM 3 sets) Programming with PROM programmer Function check in target device Verify test with PROM programmer Caution : Never expose to 150 °C exceeding 100 hours. Screening (Leave at 150 °C for 40 hours) (Caution)

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vcc Power source voltage –0.3 to +7 V AVcc Analog power source voltage –0.3 to +7 V VI Input voltage RESET , CNVss, BYTE –0.3 to +12(Note) V Input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P92, P100 – P107, VREF , XIN, BSEL Output voltageP00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87,_ P90 – P97, P100 – P107, XOUT , E Pd Power dissipation Ta = 25 °C 300 mW Topr Operating temperature –20 to +85 °C Tstg Storage temperature –40 to +150 °C VI VO –0.3 to Vcc + 0.3 V –0.3 to Vcc + 0.3 V Note. When the EPROM is programmed, input voltage of pins CNVss and BYTE is 13 V respectively. Notes 1.Average output current is the average value of a 100 ms interval. 2.The sum of IOL(peak) for ports P0, P1, P2, P3, P8, and P9 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, P8, and P9 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, P7, and P10 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, P7, and P10 must be 80 mA or less. 3.Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”. 4.The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1”. Limits Min. Typ. Max. f(XIN) : Operating 4.5 5.0 5.5 f(XIN) : Stopped, f(XCIN) = 32.768 kHz 2.7 5.5 AVcc Analog power source voltage Vcc V Vss Power source voltage 0V AVss Analog power source voltage 0 V High-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____ P70 – P77, P80 – P87, P90 – P92, P100 – P107, XIN, RESET , CNVss, BYTE, BSEL, XCIN (Note 3) High-level input voltage P10 – P17, P20 – P27 (in single-chip mode) High-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____ P70 – P77, P80 – P87, P90 – P92, P100 – P107, XIN, RESET , CNVss, BYTE, BSEL, XCIN (Note 3) Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode) Low-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P100 – P107 High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P100 – P107 Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P104 – P107 Low-level peak output current P44 – P47, P100 – P103 Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P104 – P107 IOL(avg) Low-level average output current P44 – P47, P100 – P103 15 mA f(XIN) Main-clock oscillation frequency (Note 4) 25 MHz f(XCIN) Sub-clock oscillation frequency 32.768 50 kHz UnitSymbol Parameter VVcc Power source voltage VIH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg)

0.8 Vcc

0.5 Vcc

0.2Vcc 0.2Vcc 0.16Vcc –10 V V V V V V mA mA mA mA mA RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted)

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS Limits Min. Typ. Max. High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P100 – P107 High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 IOH = –10 mA 3.1 ICH = –400 µA 4.8 IOH = –10 mA 3.4 IOH = –400 µA 4.8 Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P43, P50 – P57, P60 – P67, P70 – P75, P80 – P87, P90 – P97, P104 – P107 VOL Low-level output voltage P44 – P47, P100 – P103 IOL = 20 mA 2 V Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 IOL = 10 mA 1.9 IOL = 2 mA 0.43 IOL = 10 mA 1.6 IOL = 2 mA 0.4 Hysteresis HOLD , RDY , TA0IN – TA4IN, TB0IN – TB2IN, VT+ – VT– INT0 – INT2, AD TRG , CTS 0, CTS 1, CTS 2, CLK0, 0.4 1 V CLK 1, CLK 2, KI0 – KI3 VT+ – VT– Hysteresis RESET 0.2 0.5 V VT+ – VT– Hysteresis XIN 0.1 0.4 V VT+ – VT– Hysteresis XCIN (When external clock is input) 0.1 0.4 V High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P80 – P87, P90 – P92, P100 – P107, XIN, RESET , CNVss, BYTE, BSEL Low-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60, P61, P65 – P67, XIN, RESET , CNVss, BYTE, BSEL VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor VRAM RAM hold voltage When clock is stopped. 2V Unit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Symbol Parameter Test conditions V VOH High-level output voltage E VOH High-level output voltage P30 – P32 VOL Low-level output voltage E VOL Low-level output voltage P30 – P32 VOH VOL IIL Low-level input current P104 – P107, P62 – P64 IIL IIH VOH VOL IOH = –400 µA 4.7 V V V IOL = 2 mA 0.45 V V IOL = 10 mA 2 V VI = 0 V VI = 5 V µA mA µA µA5 –1.0 –0.5–0.25 IOH = –10 mA 3 V

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS VCC = 5 V, f(XIN) = 25 MHz (square waveform), f(f2) = 12.5 MHz, f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 5 V, f(XIN) = 25 MHz (square waveform), f(XCIN) = Stopped, in operating (Note 1) VCC = 5V, f(XIN) = 25 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) VCC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) V CC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Max. Limits Typ. UnitMin. Test conditions Symbol Parameter 9.5 1.3 2.6 100 mA mA µA µA µA µA µA Power source currentI CC In single-chip mode, output pins are open, and other pins are V SS . Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. 2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”. Limits Min. Typ. Max. — Resolution V REF = VCC 10 Bits — Absolute accuracy V REF = VCC ± 3 LSB R LADDER Ladder resistance V REF = VCC 10 25 k Ω tCONV Conversion time 9.44 µs VREF Reference voltage 2 V CC V VIA Analog input voltage 0 V REF V Symbol Parameter Test conditions Unit A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS Limits Min. Max. tsu(D–E) Data input setup time (external bus mode A) 32 ns tsu(D–RDE) Data input setup time (external bus mode B) 32 ns tsu(RDY– φ1) ___ RDY input setup time 55 ns tsu(HOLD– φ1) ____ HOLD input setup time 55 ns th(E–D) Data input hold time (external bus mode A) 0 ns th(RDE–D) Data input hold time (external bus mode B) 0 ns th(φ1–RDY) ___ RDY input hold time 0n s th(φ1–HOLD) ____ HOLD input hold time 0n s Limits Min. Max. tsu(P0D–E) Port P0 input setup time 60 ns tsu(P1D–E) Port P1 input setup time 60 ns tsu(P2D-E) Port P2 input setup time 60 ns tsu(P3D–E) Port P3 input setup time 60 ns tsu(P4D–E) Port P4 input setup time 60 ns tsu(P5D–E) Port P5 input setup time 60 ns tsu(P6D–E) Port P6 input setup time 60 ns tsu(P7D–E) Port P7 input setup time 60 ns tsu(P8D–E) Port P8 input setup time 60 ns tsu(P10D–E) Port P10 input setup time 60 ns th(E–P0D) Port P0 input hold time 0n s th(E–P1D) Port P1 input hold time 0n s th(E–P2D) Port P2 input hold time 0n s th(E–P3D) Port P3 input hold time 0n s th(E–P4D) Port P4 input hold time 0n s th(E–P5D) Port P5 input hold time 0n s th(E–P6D) Port P6 input hold time 0n s th(E–P7D) Port P7 input hold time 0n s th(E–P8D) Port P8 input hold time 0n s th(E–P10D) Port P10 input hold time 0n s Limits Min. Max. tc External clock input cycle time (Note 3) 40 ns tw(H) External clock input high-level pulse width (Note 4) 15 ns tw(L) External clock input low-level pulse width (Note 4) 15 ns tr External clock rise time 8n s tf External clock fall time 8n s TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note)) Notes 1.This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input UnitSymbol Parameter UnitSymbol Parameter Single-chip mode Notes 3. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns. 4. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55. UnitSymbol Parameter Memory expansion mode and microprocessor mode

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS Limits Min. Max. tc(TA) TAiIN input cycle time 80 ns tw(TAH) TAiIN input high-level pulse width 40 ns tw(TAL) TAiIN input low-level pulse width 40 ns UnitSymbol parameter Timer A input (Count input in event counter mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 320 ns tw(TAH) TAiIN input high-level pulse width (Note) 160 ns tw(TAL) TAiIN input low-level pulse width (Note) 160 ns UnitSymbol parameter Timer A input (Gating input in timer mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 320 ns tw(TAH) TAiIN input high-level pulse width 80 ns tw(TAL) TAiIN input low-level pulse width 80 ns UnitSymbol parameter Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max. tw(TAH) TAiIN input high-level pulse width 80 ns tw(TAL) TAiIN input low-level pulse width 80 ns UnitSymbol parameter Timer A input (External trigger input in pulse width modulation mode) Limits Min. Max. tc(UP) TAiOUT input cycle time 2000 ns tw(UPH) TAiOUT input high-level pulse width 1000 ns tw(UPL) TAiOUT input low-level pulse width 1000 ns tsu(UP–TIN) TAiOUT input setup time 400 ns th(TIN–UP) TAiOUT input hold time 400 ns UnitSymbol parameter Timer A input (Up-down input in event counter mode) UnitSymbol parameter Timer A input (Two-phase pulse input in event counter mode) Limits Min. Max. tc(TA) TAj input cycle time 800 ns tsu(TAjIN–TAjOUT ) TAjIN input setup time 200 ns tsu(TAjOUT –TAjIN) TAjOUT input setup time 200 ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS Limits Min. Max. tc(AD) AD TRG input cycle time (minimum allowable trigger) 1000 ns tw(ADL) AD TRG input low-level pulse width 125 ns Limits Min. Max. tc(CK) CLK i input cycle time 200 ns tw(CKH) CLK i input high-level pulse width 100 ns tw(CKL) CLK i input low-level pulse width 100 ns td(C–Q) TXD i output delay time 80 ns th(C–Q) TXD i hold time 0n s tsu(D–C) R XD i input setup time 30 ns th(C–D) R XD i input hold time 90 ns Limits Min. Max. tc(TB) TBiIN input cycle time (one edge count) 80 ns tw(TBH) TBiIN input high-level pulse width (one edge count) 40 ns tw(TBL) TBiIN input low-level pulse width (one edge count) 40 ns tc(TB) TBiIN input cycle time (both edges count) 160 ns tw(TBH) TBiIN input high-level pulse width (both edges count) 80 ns tw(TBL) TBiIN input low-level pulse width (both edges count) 80 ns UnitSymbol Parameter Timer B input (Count input in event counter mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 320 ns tw(TBH) TBiIN input high-level pulse width (Note) 160 ns tw(TBL) TBiIN input low-level pulse width (Note) 160 ns UnitSymbol Parameter Timer B input (Pulse period measurement mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 320 ns tw(TBH) TBiIN input high-level pulse width (Note) 160 ns tw(TBL) TBiIN input low-level pulse width (Note) 160 ns UnitSymbol Parameter Timer B input (Pulse width measurement mode) Limits Min. Max. tc(AD) AD TRG input cycle time (minimum allowable trigger) 1000 ns tw(ADL) AD TRG input low-level pulse width 125 ns UnitSymbol Parameter A-D trigger input UnitSymbol Parameter Serial I/O Limits Min. Max. tw(INH) INTi input high-level pulse width 250 ns tw(INL) INTi input low-level pulse width 250 ns tw(KIL) ____ KIi input low-level pulse width 250 ns UnitSymbol Parameter Limits Min. Max. tc(CK) CLK i input cycle time 200 ns tw(CKH) CLK i input high-level pulse width 100 ns tw(CKL) CLK i input low-level pulse width 100 ns td(C–Q) TXD i output delay time 80 ns th(C–Q) TXD i hold time 0n s tsu(D–C) R XD i input setup time 30 ns th(C–D) R XD i input hold time 90 ns Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 320 ns tw(TBH) TBiIN input high-level pulse width (Note) 160 ns tw(TBL) TBiIN input low-level pulse width (Note) 160 ns UnitSymbol Parameter Timer B input (Pulse width measurement mode) UnitSymbol Parameter A-D trigger input UnitSymbol Parameter Serial I/O UnitSymbol Parameter External interrupt INTi input, key input interrupt KIi input Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS DATA FORMULAS Timer A input (Gating input in timer mode) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time tw(TAH) TAiIN input high-level pulse width tw (TAL ) TAi IN input low-level pulse width ns ns ns 8 5 109 2 · f(f2) Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Limits Min. Max.Symbol Parameter Unit ns ns ns tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width 8 5 109 2 · f(f2) 4 5 109 2 · f(f2) 4 5 109 2 · f(f2) 8 5 109 2 · f(f2) 4 5 109 2 · f(f2) 4 5 109 2 · f(f2) Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “ M37736MHBXXXGP ”.

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS Limits Min. Max. td(E–P0Q) Port P0 data output delay time 80 ns td(E–P1Q) Port P1 data output delay time 80 ns td(E–P2Q) Port P2 data output delay time 80 ns td(E–P3Q) Port P3 data output delay time 80 ns td(E–P4Q) Port P4 data output delay time 80 ns td(E–P5Q) Port P5 data output delay time 80 ns td(E–P6Q) Port P6 data output delay time 80 ns td(E–P7Q) Port P7 data output delay time 80 ns td(E–P8Q) Port P8 data output delay time 80 ns td(E–P9Q) Port P9 data output delay time 80 ns td(E–P10Q) Port P10 data output delay time 80 ns UnitSymbol Parameter Test conditions SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85°C, f(XIN) = 25 MHz (Note), unless otherwise noted) Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. Fig. 2 Measuring circuit for ports P0 – P10 and φ1 Fig. 2 P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 9 P10 φ E 50 pF

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS [External bus mode A] Memory expansion mode and microprocessor mode (VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Symbol Parameter td(E–DQ) th(E–DQ) Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Limits Wait mode Min. Max. Test conditions Unit 130 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t d(An–E) td(A–E) td(ALE–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) tw(EL) Data output delay time Data hold delay time E pulse width Floating start delay time Floating release delay time ___ BHE output delay time R/W output delay time ___ BHE hold time_ R/W hold time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 (Note 2) φ1 output delay time tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ1) td(φ1–HLDA) ____ HLDA output delay time 01 8 Notes 1.This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. Fig. 2

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS [External bus mode A] Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Max., Note), unless otherwise noted) Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time No wait Wait 1 Wait 0 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) ns ns ns ns ns ns ns ns ns ns No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 1 5 109 2 · f(f2) ns ns ns ns ns ns 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 4 5 109 2 · f(f2) ns ns 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) – 28 – 33 – 28 – 45 – 22 – 18 – 23 – 35 – 35 – 25 – 30 – 22 – 30 – 30 – 20 – 28 – 33 – 28 – 33 – 22 – 22 UnitSymbol Parameter Limits Wait mode Min. Max. td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) No wait Wait 1 Wait 0 ___ BHE output delay time R/W output delay time td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ1) φ1 output delay time R/W hold time ___ BHE hold time 0 18 ns ns ns ns ns ns ns ns Notes 1.This applies when the main-clock division selection bit = “0”. 2. f(f 2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “ M37736MHBXXXGP ”.

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS [External bus mode B] Memory expansion mode and microprocessor mode (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Symbol Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold delay time WEL /WEH pulse width Floating start delay time Floating release delay time ___ RDE pulse width ____ RSMP output delay time ____ RSMP hold time φ1 output delay time ____ HLDA output delay time Limits Wait mode Min. Max. Test conditions td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ1–RSMP) td(WE– φ1) td(RDE– φ1) td(φ1–HLDA) Notes 1.This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 130 128 (Note 2) No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Fig.2

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS [External bus mode B] Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Max., Note1), unless otherwise noted) Limits Wait mode Min. Max.Symbol Parameter Unit 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) ns ns No wait Wait 1 Wait 0 td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ1–RSMP) td(WE– φ1) td(RDE– φ1) ns 4 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) ns ns ns ns ns ns ns ns ns ns No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 1 5 109 2 · f(f2) ns ns ns ns ns ns 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 4 5 109 2 · f(f2) ns ns 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 4 5 109 2 · f(f2) 1 5 109 2 · f(f2) ns ns ns ns ns ns Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL /WEH pulse width Floating start delay time Floating release delay time ___ RDE pulse width ____ RSMP output delay time ____ RSMP hold time φ1 output delay time – 28 – 33 – 28 – 45 – 22 – 18 – 23 – 35 – 35 – 25 – 30 – 22 – 30 – 30 – 20 – 32 – 32 – 30 – 28 – 33 Notes 1.This applies when the main-clock division selection bit = “0”. 2. f(f 2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “ M37736MHBXXXGP ”.

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS TIMING DIAGRAM tw(H) td(E–PiQ) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port Pi output (i = 0 – 10) Port Pi input (i = 0 – 8, 10) Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input E XIN Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input Single-chip mode tsu(PiD–E) th(E–PiD) td(E–P1Q) tr tf tw(L) tc tsu(P1D–E) th(E–P1D) tsu(P2D–E) th(E–P2D) tsu(P3D–E) th(E–P3D) tsu(P4D–E) th(E–P4D) tsu(P5D–E) th(E–P5D) tsu(P6D–E) th(E–P6D) tsu(P7D–E) th(E–P7D) tsu(P8D–E) th(E–P8D)

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS TAiIN input TAiOUT input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN–UP) tsu(UP–TIN) TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) In event count mode TAjIN input TAjOUT input tc(TA) tsu(TAjIN–TAjOUT ) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) tsu(TAjOUT –TAjIN) In event counter mode (When two-phase pulse input is selected) t c(TB) tw(TBH) tw(TBL) TBiIN input

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(KNL) td(C–Q) tSU(D–C) th(C–D) tw(INH) AD TRG input CLK i TxD i RxD i INTi input Kli input th(C–Q)

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS Memory expansion mode and microprocessor mode (When wait bit = “1”) ( When wait bit = “0”) (When wait bit = “1” or “0” in common) Test conditions

• VCC = 5 V – 10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V RDY input E or RDE, WEL, WEH RDY input HOLD input HLDA output tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY) tsu(HOLD– 1) td( 1–HLDA) th( 1–HOLD) td( 1–HLDA) E or RDE, WEL, WEH f f f f f f f f f f f

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS td(E-φ1) td(An-E) tw(ALE) td(ALE-E) tsu(A-ALE) td(A-E) td(E-DQ) th(ALE-A) td(BHE-E) th(E-BHE) td(R/W-E) th(E-R/W) th(E-DQ) tpxz(E-DZ) tsu(D-E) th(E-D) tpzx(E-DZ) th(E-An) td(E-φ1) tw(EL) tw(H) E An ALE Am/Dm Dm IN BHE R/W Address Address Address Data Data Address Address Address tf tr tctw(L) Test conditions VCC = 5 V ± 10% Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Data input DmIN : VIL = 0.8 V, VIH = 2.5 V XIN [External bus mode A] Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”)

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS tw(ALE) tc Address tw(L) tw(H) tf tr Address Address td(E–f1) td(An–E) td(ALE–E) tsu(A–ALE) th(ALE–A) td(A–E) td(E–DQ) th(E–D) tpzx(E–DZ) th(E–BHE) tsu(D–E) Test conditions

• Vcc = 5 V – 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V Data Address Data td(E–f1) Address tpxz(E–DZ) tw(EL) th(E–An) th(E–DQ) th(E–R/W)td(R/W–E) td(BHE–E) XIN E An ALE Am/Dm Dm IN BHE R /W [External bus mode A] Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection = “1”.)

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS [External bus mode A] th(ALE–A) td(ALE–E) td(E–DQ) tw(L) tw(H) tf tctr Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) XIN Address Address Address Address Data An ALE Am/Dm Dm IN R /W td(An–E) tw(ALE) tsu(A–ALE) th(E–DQ) td(A–E) tpxz(E–DZ) tpzx(E–DZ) th(E–D)tsu(D–E) Address Data Address Test conditions

• Vcc = 5 V – 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V td(E–f1) td(E–f1) td(R/W–E) th(E–R/W) tw(EL) th(E–An) td(BHE–E) th(E–BHE) E BHE

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS [External bus mode B] Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”) tw(WE) th(WE–DQ) tw(L) tw(H) tf tr tc XIN CS 0 – CS 4 An ALE Am/Dm td(CS–WE) td(CS–RDE) th(WE –CS) th(RDE– CS) Address td(An–WE) td(An–RDE ) th(RDE –An)tw(ALE) td(ALE–WE) Address Address tsu(A–ALE) th(ALE–A) td(A–WE) td(A–RDE) td(ALE–RDE) tpxz(RDE –DZ) tpzx(RDE –DZ) Address Data Address Address WEL, WEH th(WE–An) td(WE–DQ) Dm IN RDE RSMP Test conditions

• Vcc = 5 V – 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP –WE) th(f1–RSMP) td(RSMP –RDE) Data td(RDE– f1)td(WE– f1)td(WE– f1) td(RDE– f1)

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS [External bus mode B] Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.) tctw(L) tw(H) tf tr tw(ALE) td(An–WE) Am/Dm Address td(CS–RDE) tw(RDE) td(RDE-f1) XIN Address Address CS 0 – CS 4 An ALE WEL, WEH Dm IN RDE RSMP td(WE– f1) td(RDE– f1) td(CS–WE) td(ALE–WE) th(RDE–An) tsu(A–ALE) th(ALE–A) td(A–WE) td(WE–DQ) tw(WE) td(A–RDE) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D) tsu(D–RDE) td(RSMP–WE) th(f 1–RSMP) td(RSMP–RDE) Test conditions

• Vcc = 5 V – 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V Data Address th(WE–CS) Data td(WE– f1) th(WE-An) td(ALE–RDE) td(An–RDE) th(WE–DQ) Address tpxz(RDE–DZ)

PROM VERSION OF M37736MHBXXXGP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS [External bus mode B] Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) tctr th(ALE–A) td(ALE–WE) td(WE–DQ) tw(L) tw(H) tf XIN Address Address Address Address Data CS 0 – CS 4 An ALE Am/Dm WEL , WEH Dm IN RDE RSMP td(CS–WE) th(WE–CS) td(CS–RDE) td(An–WE) tw(ALE) th(WE–An) td(An–RDE) th(RDE–An) tsu(A–ALE) th(WE–DQ) td(ALE–RDE) td(A–WE) tw(WE) td(A–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D)tsu(D–RDE) tw(RDE) td(RSMP–WE) th( 1–RSMP) td(RSMP–RDE) Address Data Address Test conditions

• Vcc = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V td(WE– 1) td(RDE– 1) td(RDE– 1)td(WE– 1) φ φ φ φ φ φ

Notice: This is not a final specification. Some parametric limits are subject to change. PROM VERSION OF M37736MHBXXXGP MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS © 1997 MITSUBISHI ELECTRIC CORP. H-LF488-A KI-9703 Printed in Japan (ROD) 2 New publication, effective Mar. 1997. Specifications subject to change without notice. Notes regarding these materials ¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. ¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. ¡ Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. ¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. ¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs! ¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. PACKAGE OUTLINE

Rev. Rev. No. date

1.00 First Edition 970611

2.00 The following are revised: 980731

REVISION DESCRIPTION LIST M37736EHBXXXGP, M37736EHBGS Datasheet (1) Revision Description Previous Version The M37736EHBXXXGP has 28 powerful addressing modes. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE- CHIP 16-BIT MICROCOMPUTERS for the details of each addressing mode. MACHINE INSTRUCTION LIST The M37736EHBXXXGP has 103 machine instructions. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE- CHIP 16-BIT MICROCOMPUTERS for details. Revised Version The M37736EHBXXXGP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37736EHBXXXGP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. (2) 80P6N mark specification form (2) 100P6S mark specification form