M37735MHLXXXHP

M37735MHLXXXHP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The M37735MHLXXXHP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the ROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on. Its strong points are the low power dissipation, the low supply voltage and the small package.

FEATURES

l Instruction execution time l Low power dissipation (At 3 V supply voltage, 12 MHz frequency) l 12-bit watchdog timer l Programmable input/output (80P6D-A;0.5 mm lead pitch) APPLICATION Control devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on. Control devices for general industrial equipment such as communication equipment, and so on. PIN CONFIGURATION (TOP VIEW) MITSUBISHI MICR OCOMPUTERS M37735MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Outline 80P6D-A, 80P6Q-A P30/WEL P32/ALE P31/WEH P33/HLDA XOUT E/RDE CNV SS RESET P40/HOLD P86/Rx D1 P87/TxD1 P00/CS0 P01/CS1 P02/CS2 P03/CS3 P04/CS4 P05/RSMP P06/A16 P07/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A0/D0 P21/A1/D1 P41/RDY P42/ 1 BYTE XIN VSS P27/A 7/D7 P26/A6/D6 P25/A5/D5 P24/A4/D4 P23/A3/D3 P22/A2/D2 P66/TB1IN P65/TB0IN P64 /INT2 P63 /INT1 P62 /INT0 P61/TA4IN P60/TA4OUT P57/TA3IN /KI3 P56 /TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2 OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P85/CLK 1 P84/CTS1/RTS1 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P76/AN6/XCOUT P75/AN5 /ADTRG /TXD 2 P74/AN4/RXD 2 P73/AN3/CLK 2 P72/AN2/CTS2 P71/AN1 P70/AN0 P67/TB2IN/ SUB M37735MHLXXXHP P43 P44 P45 P46 P77/AN7/XCIN

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37735MHLXXXHP BLOCK DIAGRAM XIN XOUT E RESET Reset input VREF CNVss BYTE P0(8) UART1(9) UART0(9) AV SS (0V) AV CC (0V) VSSVCC A-D Converter(10) XCIN XCOUT XCIN XCOUT Clock input Clock output Enable output Reference voltage input External data bus width selection input Clock Generating Circuit Instruction Register(8) Arithmetic Logic Unit(16) Accumulator A(16) Accumulatcr B(16) Index Register X(16) Index Register Y(16) Stack Pointer S(16) Direct Page Register DPR(16) Processor Status Register PS(11) Input Butter Register IB(16) Data Bank Register DT(8) Program Bank Register PG(8) Program Counter PC(16) Incrementer/Decrementer(24) Data Address Register DA(24) Program Address Register PA(24) Incrementer(24) Instruction Queue Buffer Q2(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q0(8) Data Buffer DBL(8) Data Buffer DBH (8) ROM

124 Kbytes

Timer TA3(16) Timer TA4(16) Timer TA2(16) Timer TA1(16) Timer TA0(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) Address Bus Data Bus(Odd) Data Bus(Even) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P3 Input/Output port P2 Input/Output port P1 Input/Output port P0 UART2(9)

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FUNCTIONS OF M37735MHLXXXHP Memory size Input/Output ports Multi-function timers Interrupts Clock generating circuit Power dissipation Parameter Functions Number of basic instructions 103 Instruction execution time 333 ns (the fastest instruction at external clock 12 MHz frequency) ROM 124 Kbytes RAM 3968 bytes P0 – P2, P4 – P8 8-bit 5 8 P3 4-bit 5 1 TA0, TA1, TA2, TA3, TA4 16-bit 5 5 TB0, TB1, TB2 16-bit 5 3 Serial I/O (UART or clock synchronous serial I/O) 5 3 A-D converter 10-bit 5 1 (8 channels) Watchdog timer 12-bit 5 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) Supply voltage 2.7 – 5.5 V 9 mW (at 3 V supply voltage, external clock 12 MHz frequency) 22.5 mW (at 5 V supply voltage, external clock 12 MHz frequency) Input/Output voltage 5 V Output current 5 mA Memory expansion Maximum 1 Mbytes Operating temperature range –40 to 85 °C Device structure CMOS high-performance silicon gate process Package 80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch) Input/Output characteristic

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. PIN DESCRIPTION XIN Clock input Input XOUT Clock output Output Pin Name Input/Output Functions Vcc, Power source Apply 2.7 – 5.5 V to Vcc and 0 V to Vss. Vss CNVss CNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode. RESET Reset input Input When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz- crystal oscillator between XIN and XOUT . When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. E Enable output Output In the single-chip mode, this pin functions as the enable signal output pin which indicates the access status in the internal bus. In the memory expansion mode or the microprocessor mode, this pin functions as the RDE signal output pin. BYTE External data Input In the memory expansion mode or the microprocessor mode, this pin determines whether the bus width external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L” selection input signal is input and an 8-bit width when “H” signal is input. AVcc, Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. AVss source input VREF Reference Input This is reference voltage input pin for the A-D converter. voltage input P00 – P07 I/O port P0 I/O In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output CS 0 – CS 4, RSMP signals, and address (A16, A17). P10 – P17 I/O port P1 I/O In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output. P20 – P27 I/O port P2 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address (A0 – A7) is output. P30 – P33 I/O port P3 I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion mode or the microprocessor mode, WEL , WEH , ALE, and HLDA signals are output. P40 – P47 I/O port P4 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and clock φ 1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 also functions as an I/O port. P50 – P57 I/O port P5 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3). P60 – P67 I/O port P6 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock φ SUB output pin. P70 – P77 I/O port P7 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the function as the output pin (XCOUT ) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. P80 – P87 I/O port P8 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1.

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS The M37735MHLXXXHP has the same functions as the M37735MHBXXXFP except for the package and the reset circuit. Refer to the section on the M37735MHBXXXFP. RESET CIRCUIT The microcomputer is released from the reset state when the RESET pin is returned to “H” level after holding it at “L” level with the power source voltage at 2.7 – 5.5 V. Program execution starts at the address formed by setting address A 23 – A16 to 0016, A15 – A8 to the contents of address FFFF16, and A7 – A0 to the contents of address FFFE16. Figure 1 shows an example of a reset circuit. When the stabilized clock is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.55 V or less when the power source voltage reaches 2.7 V. When a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from “L” to “H” after the main-clock oscillation is fully stabilized. The status of the internal registers during reset is the same as the M37735MHBXXXFP’s. Fig. 1 Example of a reset circuit ADDRESSING MODES The M37735MHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37735MHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders. (1) M37735MHLXXXHP mask ROM order confirmation form (2) 80P6D, 80P6Q mark specification form (3) ROM data (EPROM 3 sets) VCCRESET RESET VCC 2.7V 0.55V Power on Note. In this case, stabilized clock is input from the external to the main-clock oscillation circuit. Perform careful evalvation at the system design level before using.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Symbol Parameter Conditions Ratings Unit Vcc Power source voltage –0.3 to +7 V AVcc Analog power source voltage –0.3 to +7 V VI Input voltage RESET , CNVss, BYTE –0.3 to +12 V Input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, VREF , XIN Output voltageP00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XOUT , E Pd Power dissipation Ta = 25 °C 200 mW Topr Operating temperature –40 to +85 °C Tstg Storage temperature –65 to +150 °C ABSOLUTE MAXIMUM RATINGS VI VO –0.3 to Vcc + 0.3 V –0.3 to Vcc + 0.3 V Unit RECOMMENDED OPERATING CONDITIONS (Vcc = 2.7 – 5.5 V, Ta = –40 to +85 °C, unless otherwise noted) Notes 1.Average output current is the average value of a 100 ms interval. 2. The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”. 4. The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1”. ParameterSymbol Vcc Power source voltage Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc V V IH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg) Limits Min. Typ. Max. f(XIN) : Operating 2.7 5.5 f(XIN) : Stopped, f(XCIN) = 32.768 kHz 2.7 5.5 AVcc Analog power source voltage Vcc V Vss Power source voltage 0V AVss Analog power source voltage 0 V High-level input voltageP00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) High-level input voltage P10 – P17, P20 – P27 (in single-chip mode) High-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode) Low-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) High-level peak output current P00 – P07, P10– P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P44 – P47, P50 – P53 Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 IOL(avg) Low-level average output current P44 – P47, P50 – P53 12 mA f(XIN) Main-clock oscillation frequency (Note 4) 12 MHz f(XCIN) Sub-clock oscillation frequency 32.768 50 kHz

0.8 Vcc

0.5 Vcc

–10 V V V V V V mA mA mA mA mA

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Unit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted) Symbol Parameter Test conditions 2.5 4.7 VOH VOH –0.5 –0.18 High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 High-level output voltage P30 – P32 High-level output voltage E Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level output voltage P44 – P47, P50 – P53 Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 Low-level output voltage P30 – P32 Low-level output voltage E Hysteresis HOLD , RDY , TA0IN – TA4IN, TB0IN – TB2IN, INT0 – INT2, AD TRG , CTS 0, CTS 1, CTS 2, CLK0, CLK 1, CLK2, KI0 – KI3 Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE Low-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P53, P60, P61, P65 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE VOH 3.1 4.8 2.6 3.4 4.8 2.6 VOH VOL V V V V 0.5 1.8

1.5 VVOL

0.45 1.9 0.43 0.4 1.6 0.4 0.4 V V V 0.4 0.1 0.2 0.1 0.1 0.06 0.1 0.06 VCC = 5 V, IOH = –10 mA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –400 µA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 16 mA VCC = 3 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V, VI = 5 V VCC = 3 V, VI = 3 V VCC = 5 V, VI = 0 V VCC = 3 V, VI = 0 V VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor When clock is stopped. 0.7 0.5 0.4 0.4 0.26 0.4 0.26 VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V –0.25 –0.08 –1.0 –0.35 V V V V µA mA V VOL VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– VT+ – VT– IIH IIL IIL VRAM Low-level input current P54 – P57, P62 – P64 RAM hold voltage Min. Max.Typ. Limits µA µA V

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. VCC = 5 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 0.75 MHz), f(XCIN) : Stopped, in operating VCC = 3 V, f(XIN) = 12 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) V CC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, in operating (Note 3) VCC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped mA mA mA µA µA µA µA µA Max. 0.8 Limits Typ. 4.5 0.4 UnitMin. Test conditions Symbol Parameter ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted) When single-chip mode, output pins are open, and other pins are V SS . Power source currentI CC Limits Min. Typ. Max. — Resolution V REF = VCC 10 Bits — Absolute accuracy V REF = VCC ± 3 LSB R LADDER Ladder resistance V REF = VCC 10 25 k Ω tCONV Conversion time 19.6 µs VREF Reference voltage 2.7 V CC V VIA Analog input voltage 0 V REF V Symbol Parameter Test conditions Unit A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. 2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.

MITSUBISHI MICR OCOMPUTERS M37735MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tsu(D–RDE) Data input setup time 50 ns tsu(RDY– φ 1) RDY input setup time 80 ns tsu(HOLD– φ 1) HOLD input setup time 80 ns th(RDE–D) Data input hold time 0n s th( φ 1–RDY) RDY input hold time 0n s th( φ 1–HOLD) HOLD input hold time 0n s Limits Min. Max. tc External clock input cycle time (Note 1) 83 ns tw(H) External clock input high-level pulse width (Note 2) 33 ns tw(L) External clock input low-level pulse width (Note 2) 33 ns tr External clock rise time 15 ns tf External clock fall time 15 ns TIMING REQUIREMENTS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1)) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHZ. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input UnitSymbol Parameter Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 166 ns. 2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55. UnitSymbol Parameter Memory expansion mode and microprocessor mode Single-chip mode UnitSymbol Parameter Limits Min. Max. tsu(P0D–E) Port P0 input setup time 200 ns tsu(P1D–E) Port P1 input setup time 200 ns tsu(P2D–E) Port P2 input setup time 200 ns tsu(P3D–E) Port P3 input setup time 200 ns tsu(P4D–E) Port P4 input setup time 200 ns tsu(P5D–E) Port P5 input setup time 200 ns tsu(P6D–E) Port P6 input setup time 200 ns tsu(P7D–E) Port P7 input setup time 200 ns tsu(P8D–E) Port P8 input setup time 200 ns th(E–P0D) Port P0 input hold time 0n s th(E–P1D) Port P1 input hold time 0n s th(E–P2D) Port P2 input hold time 0n s th(E–P3D) Port P3 input hold time 0n s th(E–P4D) Port P4 input hold time 0n s th(E–P5D) Port P5 input hold time 0n s th(E–P6D) Port P6 input hold time 0n s th(E–P7D) Port P7 input hold time 0n s th(E–P8D) Port P8 input hold time 0n s

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tc(TA) TAiIN input cycle time 250 ns tw(TAH) TAiIN input high-level pulse width 125 ns tw(TAL) TAiIN input low-level pulse width 125 ns UnitSymbol Parameter Timer A input (Count input in event counter mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 666 ns tw(TAH) TAiIN input high-level pulse width (Note) 333 ns tw(TAL) TAiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer A input (Gating input in timer mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 666 ns tw(TAH) TAiIN input high-level pulse width 166 ns tw(TAL) TAiIN input low-level pulse width 166 ns UnitSymbol Parameter Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max. tw(TAH) TAiIN input high-level pulse width 166 ns tw(TAL) TAiIN input low-level pulse width 166 ns UnitSymbol Parameter Timer A input (External trigger input in pulse width modulation mode) Limits Min. Max. tc(UP) TAiOUT input cycle time 3333 ns tw(UPH) TAiOUT input high-level pulse width 1666 ns tw(UPL) TAiOUT input low-level pulse width 1666 ns tsu(UP–TIN) TAiOUT input setup time 666 ns th(TIN–UP) TAiOUT input hold time 666 ns UnitSymbol Parameter Timer A input (Up-down input in event counter mode) Limits Min. Max. tc(TA) TAjIN input cycle time 2000 ns tsu(TAjIN–TAjOUT ) TAjIN input setup time 500 ns tsu(TAjOUT –TAjIN) TAjOUT input setup time 500 ns UnitSymbol Parameter Timer A input (Two-phase pulse input in event counter mode) Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tc(CK) CLK i input cycle time 333 ns tw(CKH) CLK i input high-level pulse width 166 ns tw(CKL) CLK i input low-level pulse width 166 ns td(C–Q) TXD i output delay time 100 ns th(C–Q) TXD i hold time 0n s tsu(D–C) R XD i input setup time 65 ns th(C–D) R XD i input hold time 75 ns Limits Min. Max. tc(TB) TBiIN input cycle time (one edge count) 250 ns tw(TBH) TBiIN input high-level pulse width (one edge count) 125 ns tw(TBL) TBiIN input low-level pulse width (one edge count) 125 ns tc(TB) TBiIN input cycle time (both edges count) 500 ns tw(TBH) TBiIN input high-level pulse width (both edges count) 250 ns tw(TBL) TBiIN input low-level pulse width (both edges count) 250 ns UnitSymbol Parameter Timer B input (Count input in event counter mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 666 ns tw(TBH) TBiIN input high-level pulse width (Note) 333 ns tw(TBL) TBiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer B input (Pulse period measurement mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 666 ns tw(TBH) TBiIN input high-level pulse width (Note) 333 ns tw(TBL) TBiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer B input (Pulse width measurement mode) UnitSymbol Parameter A-D trigger input UnitSymbol Parameter Serial I/O UnitSymbol Parameter Limits Min. Max. tw(INH) INTi input high-level pulse width 250 ns tw(INL) INTi input low-level pulse width 250 ns tw(KIL) KIi input low-level pulse width 250 ns Limits Min. Max. tc(AD) AD TRG input cycle time (minimum allowable trigger) 1333 ns tw(ADL) AD TRG input low-level pulse width 166 ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. External interrupt INTi input, key input interrupt KIi input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. DATA FORMULAS Timer A input (Gating input in timer mode) 8 5 109 2 • f(f2) 4 5 109 2 • f(f2) 4 5 109 2 • f(f2) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time tw(TAH) TAiIN input high-level pulse width tw (TAL ) TAi IN input low-level pulse width ns ns ns 8 5 109 2 • f(f2) Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Limits Min. Max.Symbol Parameter Unit ns ns ns tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width 8 5 109 2 • f(f2) 4 5 109 2 • f(f2) 4 5 109 2 • f(f2) Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “M37735MHBXXXFP”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SWITCHING CHARACTERISTICS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Fig. 2 Measuring circuit for ports P0 – P8 and φ 1 Limits Min. Max. td(E–P0Q) Port P0 data output delay time 300 ns td(E–P1Q) Port P1 data output delay time 300 ns td(E–P2Q) Port P2 data output delay time 300 ns td(E–P3Q) Port P3 data output delay time 300 ns td(E–P4Q) Port P4 data output delay time 300 ns td(E–P5Q) Port P5 data output delay time 300 ns td(E–P6Q) Port P6 data output delay time 300 ns td(E–P7Q) Port P7 data output delay time 300 ns td(E–P8Q) Port P8 data output delay time 300 ns UnitSymbol Parameter Test conditions Fig. 2 Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. Single-chip mode 50 pF P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 E

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL /WEH pulse width Floating start delay time Floating release delay time RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time HLDA output delay time Limits Wait mode Min. Max. Memory expansion mode and microprocessor mode (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1)) Symbol Parameter Test conditions td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th( φ 1–RSMP) td(WE– φ 1) td(RDE– φ 1) td( φ 1–HLDA) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 120 182 182 162 123 131 298 128 295 Fig. 2 (Note 2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL /WEH pulse width Floating start delay time Floating release delay time RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time Bus timing data formulas (VCC = 2.7 – 5.5V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz (Max.), unless otherwise noted (Note1)) Limits Wait mode Min. Max.Symbol Parameter Unit 1 5 109 2 • f(f2) 3 5 109 2 • f(f2) ns ns No wait Wait 1 Wait 0 td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th( φ 1–RSMP) td(WE– φ 1) td(RDE– φ 1) ns 4 1 5 109 2 • f(f2) 3 5 109 2 • f(f2) 1 5 109 2 • f(f2) 3 5 109 2 • f(f2) 1 5 109 2 • f(f2) 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) ns ns ns ns ns ns ns ns ns ns No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 1 5 109 2 • f(f2) ns ns ns ns ns ns 1 5 109 2 • f(f2) 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) 4 5 109 2 • f(f2) ns ns 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) 4 5 109 2 • f(f2) 1 5 109 2 • f(f2) ns ns ns ns ns ns – 63 – 68 – 63 – 88 – 43 – 43 – 43 – 73 – 73 – 43 – 43 – 43 – 35 – 35 – 30 – 38 – 38 – 58 – 63 – 68 Notes 1. This applies when the main clock division selection bit = “0”. 2. f(f 2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “M37735MHBXXXFP”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tw(H) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) E XIN Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) tr tf tw(L)tc th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) TIMING DIAGRAM Single-chip mode td(E–P0Q) td(E–P2Q) td(E–P3Q) Port P0 output Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input tsu(P0D–E) tsu(P1D–E) tsu(P2D–E) tsu(P3D–E) th(E–P1D) th(E–P2D) th(E–P3D) td(E–P1Q) th(E–P0D)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. TAiIN input TAiOUT input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN–UP) tsu(UP–TIN) TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) In event count mode tc(TB) tw(TBH) tw(TBL) TBiIN input tsu(TAjIN–TAjOUT ) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) tsu(TAjOUT –TAjIN) TAjIN input TAjOUT input In event counter mode (When two-phase pulse input is selected) tc ( TA )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(KNL) td(C–Q) tsu(D–C) th(C–D) tw(INH) AD TRG input CLK i TxD i RxD i INTi input Kli input th(C–Q)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Memory expansion and microprocessor mode (When wait bit = “1”) (When wait bit = “0”) (When wait bit = “1” or “0” in common) Test conditions

• Input timing voltage : VIL = 0.2VCC , VIH = 0.8VCC
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V f 1 RDY input f 1 RDY input f 1 HOLD input HLDA output tsu(RDY– f1) th( f1–RDY) tsu(RDY– f1) th( f1–RDY) tsu(HOLD– f1) td( f1–HLDA) th( f1–HOLD) td( f1–HLDA) WEL WEH RDE WEL WEH RDE

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tw(WE) th(WE–DQ) tw(L) tw(H) tf tr tc Memory expansion and microprocessor mode (No wait : When wait bit = “1”) XIN f 1 CS 0 – CS 4 An ALE Am/Dm td(CS–WE) td(CS–RDE) th(WE –CS) th(RDE– CS) Address td(An–WE) td(An–RDE ) th(RDE –An)tw(ALE) td(ALE–WE) Address Address tsu(A–ALE) th(ALE–A) td(A–WE) td(A–RDE) td(ALE–RDE) tpxz(RDE –DZ) tpzx(RDE –DZ) Address Data Address Address WEL, WEH th(WE–An) td(WE–DQ) Dm IN RDE RSMP Test condition

• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16 VCC , VIH = 0.5 VCC tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP –WE) th( f1–RSMP) td(RSMP –RDE) Data td(RDE– f1)td(WE– f1)td(WE– f1) td(RDE– f1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tw(ALE) td(An–WE) tc Am/Dm Address td(CS–RDE) tw(RDE) td(RDE- f1) tw(L) tw(H) tf tr Memory expansion and microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.) XIN f 1 Address Address CS 0 – CS 4 An ALE WEL, WEH Dm IN RDE RSMP td(WE– f1) td(RDE– f1) td(CS–WE) td(ALE–WE) th(RDE–An) tsu(A–ALE) th(ALE–A) td(A–WE) td(WE–DQ) tw(WE) td(A–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D) tsu(D–RDE) td(RSMP–WE) th( f1–RSMP) td(RSMP–RDE) Test condition

• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16 VCC , VIH = 0.5 VCC Data Address th(WE–CS) Data td(WE– f1) th(WE-An) td(ALE–RDE) td(An–RDE) th(WE–DQ) Address

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. th(ALE–A) td(ALE–WE) td(WE–DQ) tw(L) tw(H) tf tctr Memory expansion and microprocessor mode (Wait 0 : The external memory are is accessed when wait bit = “0” and wait selection bit = “0”.) X IN f 1 Address Address Address Address Data CS 0 – CS 4 An ALE Am/Dm WEL , WEH Dm IN RDE RSMP td(CS–WE) th(WE–CS) td(CS–RDE) td(An–WE) tw(ALE) th(WE–An) td(An–RDE) th(RDE–An) tsu(A–ALE) th(WE–DQ) td(ALE–RDE) td(A–WE) tw(WE) td(A–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D)tsu(D–RDE) tw(RDE) td(RSMP–WE) th( f1–RSMP) td(RSMP–RDE) Address Data Address Test conditions

• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16 VCC , VIH = 0.5 VCC td(WE– f1) td(RDE– f1) td(RDE– f1)td(WE– f1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. PACKAGE OUTLINE

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT MICROCOMPUTER M37735MHLXXXHP MITSUBISHI ELECTRIC Date: Receipt GZZ–SH00–43B<68A0> ( ) Note : Please fill in all items marked Customer SupervisorCompany name Date issued Date: TEL 1. Confirmation Specify the name of the product being ordered. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM areas EPROM Type : (1) Set “FF16” in the shaded area. (2) Address 016 to 1016 are the area for storing the data on model designation and options.This area must be written with the data shown below. Details for option data are given next in the section describing the STP instruction option. Address and data are written in hexadecimal notation. F A E C B (hexadecimal notation) 27C201 128K 3FFFF DATA D Responsible officer Section head signature Supervisor signature Issuance signatures FF FF FF FF FF FF FF Option data Address Address Address One of the following sets of data should be written to the option data address (1016) of the EPROM you have ordered. Check @ in the appropriate box. STP instruction enable STP instruction disable 2. STP instruction option 0116 0016 Address 1016 Address 1016 3. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 80P6D Mark Specification Form (for M37735MHLXXXHP) and attach to the Mask ROM Order Confirmation Form. 4. Comments

7700 FAMILY MASK ROM ORDER CONFIRMATION FORM

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. © 1996 MITSUBISHI ELECTRIC CORP. H-LF424-A KI-9605 Printed in Japan (ROD) New publication, effective May. 1996. Specifications subject to change without notice. Notes regarding these materials ¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. ¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. ¡ Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. ¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. ¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs! ¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Rev. Rev. No. date

1.00 First Edition 970414

1.01 The following are added: 980421

• MASK ROM ORDER CONFIRMATION FORM
• MARK SPECIFICATION FORM

2.00 The following are revised: 980731

REVISION DESCRIPTION LIST M37735MHLXXXHP Datasheet (1) Revision Description Page PIN CON- FIGURATION (TOP VIEW) Right column Line 2 Line 10 Memory expan- sion mode and microprocessor mode Revised Version Outline 80P6D-A, 80P6Q-A The M37735MHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37735MHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. Previous Version Revised Version Symbol Parameter Limits UnitMin. Max. tsu(D–RDE) Data input setup time 80 ns Symbol Parameter Limits UnitMin. Max. tsu(D–RDE) Data input setup time 50 ns Previous Version Outline 80P6D-A The M37735MHLXXXHP has 28 powerful addressing modes. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE- CHIP 16-BIT MICROCOMPUTERS for the details of each addressing mode. MACHINE INSTRUCTION LIST The M37735MHLXXXHP has 103 machine instructions. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE- CHIP 16-BIT MICROCOMPUTERS for details. (2) 80P6D mark specification form (2) 80P6D, 80P6Q mark specification form