M37735MHBXXXFP

M37735MHBXXXFP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The M37735MHBXXXFP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the ROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on.

FEATURES

l Instruction execution time l Low power dissipation (at 25 MHz frequency) l 12-bit watchdog timer l Programmable input/output APPLICATION Control devices for general commercial equipment such as office automation, office equipment, and so on. Control devices for general industrial equipment such as communication equipment, and so on. PIN CONFIGURATION (TOP VIEW) MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P40/HOLD P27/A7/D7 0/AN 7/TB2 IN SUB 6/TB1 IN 5/TB0 IN 4/INT 2 3/INT 1 2/INT 0 1/TA4 IN 0/TA4 OUT 7/TA3 IN /KI3 6/TA3 OUT /KI2 5/TA2 IN /KI1 4/TA2 OUT /KI0 3/TA1 IN 2/TA1 OUT 1/TA0 IN 0/TA0 OUT 1 4 3 2 5 4/CTS 1/RTS 1 5/CLK 6/R XD 7/T XD 0/CS 0 1/CS 1 2/CS 2 3/CS 3 4/CS 4 5/RSMP 6/A 7/A 0/A 8/D 1/A 9/D 2/A 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 6362 6160 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Outline 80P6N-A 3/A 4/A 5/A 6/A 7/A 0/A 0/D 1/A 1/D 2/A 2/D 3/A 3/D 43 42 41 22 23 24 1/RDY P4 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 P75/AN5/AD TRG /TxD2 P76/AN6/XcOUT P77/AN7/XcIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS 1 P81/CLK0 P82/RXD 0/CLKS0 P83/TXD 0 RESET XOUT P32/ALE P30/WEL P31/WEH CNV SS Vss BYTE XIN P26/A6/D6 P25/A5/D5 P24/A4/D4 E/RDE P33/HLDA M37735MHBXXXFP PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.M37735MHBXXXFP BLOCK DIAGRAM XIN XOUT E RESET Reset input VREF CNVss BYTE P0(8) UART1(9) UART0(9) AV SS (0V) AV CC (0V) VSS VCC A-D Converter(10) XCIN XCOUT XCIN XCOUT Clock input Clock output Enable output Reference voltage input External data bus width selection input Clock Generating Circuit Instruction Register(8) Arithmetic Logic Unit(16) Accumulator A(16) Accumulatcr B(16) Index Register X(16) Index Register Y(16) Stack Pointer S(16) Direct Page Register DPR(16) Processor Status Register PS(11) Input Butter Register IB(16) Data Bank Register DT(8) Program Bank Register PG(8) Program Counter PC(16) Incrementer/Decrementer(24) Data Address Register DA(24) Program Address Register PA(24) Incrementer(24) Instruction Queue Buffer Q2(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q0(8) Data Buffer DBL(8) Data Buffer DBH (8) ROM

124 Kbytes

Timer TA3(16) Timer TA4(16) Timer TA2(16) Timer TA1(16) Timer TA0(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) Address Bus Data Bus(Odd) Data Bus(Even) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P3 Input/Output port P2 Input/Output port P1 Input/Output port P0 UART2(9)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. FUNCTIONS OF M37735MHBXXXFP Memory size Input/Output ports Parameter Functions Number of basic instructions 103 Instruction execution time 160 ns (the fastest instruction at external clock 25 MHz frequency) ROM 124 Kbytes RAM 3968 bytes P0 – P2, P4 – P8 8-bit 5 8 P3 4-bit 5 1 TA0, TA1, TA2, TA3, TA4 16-bit 5 5 TB0, TB1, TB2 16-bit 5 3 Serial I/O (UART or clock synchronous serial I/O) 5 3 A-D converter 10-bit 5 1 (8 channels) Watchdog timer 12-bit 5 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) Supply voltage 5 V ± 10% Power dissipation 47.5 mW (at external clock 25 MHz frequency) Input/Output voltage 5 V Output current 5 mA Memory expansion Maximum 1 Mbytes Operating temperature range –20 to 85 °C Device structure CMOS high-performance silicon gate process Package 80-pin plastic molded QFP (80P6N-A) Interrupts Clock generating circuit Multi-function timers Input/Output characteristic

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Pin Name Input/Output Functions Vcc, Power source Apply 5 V ± 10% to Vcc and 0 V to Vss. Vss CNVss CNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode. RESET Reset input Input When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz- crystal oscillator between XIN and XOUT . When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. E Enable output Output This pin functions as the enable signal output pin which indicates the access status in the internal bus. In the memory expansion mode or the microprocessor mode, this pin functions as the RDE signal output pin. BYTE External data Input In the memory expansion mode or the microprocessor mode, this pin determines whether the bus width external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L” selection input signal is input and an 8-bit width when “H” signal is input. AVcc, Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. AVss source input VREF Reference Input This is reference voltage input pin for the A-D converter. voltage input P00 – P07 I/O port P0 I/O In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output CS 0 – CS 4, RSMP signals, and address (A16, A17). P10 – P17 I/O port P1 I/O In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output. P20 – P27 I/O port P2 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address (A0 – A7) is output . P30 – P33 I/O port P3 I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion mode or the microprocessor mode, WEL , WEH , ALE, and HLDA signals are output. P40 – P47 I/O port P4 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, P40, P41 and P42 become HOLD and RDY input pins, and a clock φ 1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port. P50 – P57 I/O port P5 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3 ). P60 – P67 I/O port P6 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as a sub-clock φ SUB output pin. P70 – P77 I/O port P7 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the function as the output pin (XCOUT ) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. P80 – P87 I/O port P8 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1. PIN DESCRIPTION XOUT Clock output Output XIN Clock input Input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. BASIC FUNCTION BLOCKS The M37735MHBXXXFP contains the following peripheral devices on a single chip: ROM, RAM, CPU, bus interface unit, timers, serial I/O, A-D converter, I/O ports, clock generating circuit and others. Each of these devices is described below. MEMORY The memory map is shown in Figure 1. The address space has a capacity of 16 Mbytes and is allocated to addresses from 0 16 to FFFFFF 16. The address space is divided by 64-Kbyte unit called bank. The banks are numbered from 016 to FF16. However, banks 1016 – FF16 of the 7735 group cannot be accessed. Built-in ROM, RAM and control registers for internal peripheral devices are assigned to banks 0 16 and 116. The 124-Kbyte area from addresses 100016 to 1FFFF16 is the built-in ROM. Addresses FFD616 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors. Refer to the section on interrupts for details. The 3968-byte area allocated to addresses from 80 16 to FFF16 is the built-in RAM. In addition to storing data, the RAM is used as stack during a subroutine call or interrupts. Peripheral devices such as I/O ports, A-D converter, serial I/O, timer, and interrupt control registers are allocated to addresses from 0 16 to 7F16. Additionally, the internal ROM and RAM area can be modified by software. Refer to the section on ROM area modification function for details. A 256-byte direct page area can be allocated anywhere in bank 0 by using the direct page register (DPR). In the direct page addressing mode, the memory in the direct page area can be accessed with two words. Hence program steps can be reduced. Fig. 1 Memory map A-D/UART2 trans./rece. Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT0 Watchdog timer DBC BRK instruction Zero divide RESET Internal peripheral devices control registers refer to Fig. 2 for detail information Interrupt vector table 00000016 00FFFF16 01000016 01FFFF16 Bank 016 Bank 116 FE000016 FEFFFF16 FF000016 FFFFFF16 Bank FF16 Bank FE16 01FFFF 00FFD6 000FFF 00000016 00007F16 00008016 Internal RAM 3968 bytes Internal ROM Notes 1.Internal ROM and RAM area can be modified. (Refer to the section on ROM area modification function.) 2.Banks 1016 – FF16 cannot be accessed in the 7735 group. 001000 00FFFF16 16 16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 2 Location of internal peripheral devices and interrupt control registers 00002A UART 0 transmission interrupt control register UART 1 transmission interrupt control register INT2/Key input interrupt control register Port P1 direction register UART 0 transmit/receive mode register UART 0 baud rate register (BRG0) UART 0 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 0 transmission buffer register UART 1 transmit/receive control register 0 UART 1 transmit/receive mode register UART 1 baud rate register (BRG1) UART 1 transmit/receive control register 1 UART 0 receive buffer register UART 1 transmission buffer register UART 1 receive buffer register Port P0 register A-D register 0 A-D register 2 Port P1 register Port P0 direction register Port P2 register Port P3 register Port P4 register Port P5 register Port P6 register Port P7 register Port P8 register A-D control register 0 A-D control register 1 A-D register 1 A-D register 3 A-D register 4 A-D register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001A 00001B 00001C 00001D 00001E 00001F 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002B 00002C 00002D 00002E 00002F 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003A 00003B 00003C 00003D 00003E 00003F 00000B 00000C 00000D 00000E 00000F 00000A 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F 00004B 00004C 00004D 00004E 00004F 00004A 000044 Address (Hexadecimal notation) Address (Hexadecimal notation) Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start flag One-shot start flag Up-down flag Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Watchdog timer register Watchdog timer frequency selection flag A-D/UART 2 trans./rece. interrupt control register UART 0 receive interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register Processor mode register 1 Oscillation circuit control register 1 Serial transmit control register Port function control register Oscillation circuit control register 0 Timer A3 mode register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Reserved area (Note) A-D register 6 A-D register 7 UART 2 transmit/receive control register 1 UART 2 transmit/receive control register 0 UART 2 transmission buffer register UART 2 baud rate register (BRG2) UART 2 transmit/receive mode register Memory allocation control register Reserved area (Note) UART 2 receive buffer register Note. Do not write to this address. Reserved area (Note)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. CENTRAL PROCESSING UNIT (CPU) The CPU has ten registers and is shown in Figure 3. Each of these registers is described below. ACCUMULATOR A (A) Accumulator A is the main register of the microcomputer. It consists of 16 bits and the low-order 8 bits can be used separately. The data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. It is used as a 16-bit register when flag m is “0” and as an 8-bit register when flag m is “1”. Flag m is a part of the processor status register (PS) which is described later. Data operations such as arithmetic operation, data transfer, input/ output, etc., are executed mainly through the accumulator A. ACCUMULATOR B (B) Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A. INDEX REGISTER X (X) Index register X consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In an index addressing mode where register X is used as the index register, the contents of this address is added to obtain the real address. Also, when executing a block transfer instruction (MVP, MVN), the contents of index register X indicates the low-order 16 bits of the source data address. The third byte of the MVP or MVN is the high- order 8 bits of the source data address. INDEX REGISTER Y (Y) Index register Y consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In an index addressing mode where register Y is used as the index register, the contents of this address is added to obtain the real address. Also, when executing a block transfer instruction (MVP, MVN), the contents of index register Y indicates the low-order 16 bits of the destination data address. The second byte of the MVP or MVN is the high-order 8 bits of the destination data address. Fig. 3 Register structure 7 0 PG Program bank register (PG) 7 0 DT Data bank register (DT) Carry flag Zero frag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Negative flag Overflow flag Processor interrupt priority level (IPL) Accumulator A (A) Accumulator B (B) Index register X (X) Index register Y (Y) Stack pointer (S) Program counter (PC) Direct page register (DPR) Processor status register (PS) 0 AH AL 15 0 7 BH BL 15 0 7 XH XL 15 0 7 YH YL 15 0 7 15 0 PC 15 0 15 0 DPR 7 15 0 NIPL2 IPL0IPL1 C Z I D x m V0000 S

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. STACK POINTER (S) Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing modes. PROGRAM COUNTER (PC) Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program memory is accessed through the bus interface unit. This is described later. PROGRAM BANK REGISTER (PG) Program bank register (PG) is an 8-bit register that indicates the high- order 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (PG) is incremented by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) by using a branch instruction, the contents of the program bank register (PG) is incremented or decremented by 1 so that programs can be written without worrying about bank boundaries. DATA BANK REGISTER (DT) Data bank register (DT) is an 8-bit register. With some addressing modes, a part of the data bank register (DT) is used to specify a memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24-bit address. Addressing modes that use the data bank register (DT) to specify the address are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y. DIRECT PAGE REGISTER (DPR) Direct page register (DPR) is a 16-bit register. Its contents is used as the base address of a 256-byte direct page area. The direct page area is allocated in bank 0 16, but when the contents of DPR is FF0116 or more, the direct page area spans across bank 016 and bank 116. All direct addressing modes use the contents of the direct page register (DPR) to generate the data address. If the low-order 8 bits’ contents of the direct page register (DPR) is “00 16”, the number of cycles required to generate an address is minimized. Hence the low-order 8 bits’ contents of the direct page register (DPR) is usually set to “0016”. PROCESSOR STATUS REGISTER (PS) Processor status register (PS) is an 11-bit register. It consists of flags which indicate the result of operation and the processor interrupt priority level (IPL). Branch operations can be performed by testing flags C, Z , V, and N. The details of each processor status register bit are described below. 1. Carry flag (C) The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift or rotate instruction. This flag can be set or reset directly with the SEC, CLC instructions or with the SEP, CLP instructions. 2. Zero flag (Z) This zero flag is set when the result of an arithmetic operation or data transfer is zero and reset when it is not. This flag can be set or reset directly with the SEP or CLP instruction. 3. Interrupt disable flag ( I ) When the interrupt disable flag is “1”, all interrupts except watchdog timer, DBC , and software interrupt are disabled. This flag is automatically set to “1” when an interrupt is accepted. It can be set or reset directly with the SEI, CLI instructions or SEP and CLP instructions. 4. Decimal mode flag (D) The decimal mode flag determines whether addition and subtraction are performed in the binary or the decimal system. Binary arithmetic is performed when this flag is “0”. If it is “1”, decimal arithmetic is performed with each word treated as the 2- or 4-digit number. Arithmetic operation is performed with 4-digit number when the data length flag (m) is “0” and with 2-digit number when it is “1”. Decimal correction is automatically performed. (Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set or reset with the SEP or CLP instruction. 5. Index register length flag (x) The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is “0” and as 8- bit registers when it is “1”. This flag can be set or reset with the SEP or CLP instruction. 6. Data length flag (m) The data length flag determines whether the data has a length of 16 bits or that of 8 bits. The 16-bit length is selected when flag m is “0” and the 8-bit length is selected when it is “1”. This flag can be set or reset with the SEM, CLM instructions or with the SEP, CLP instructions.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 7. Overflow flag (V) The overflow flag is effective only when addition or subtraction is performed with treating a word as a signed binary number. When the data length flag (m) is “0”, the overflow flag is set if the result of addition or subtraction is outside the range between – 32768 and +32767. When the data length flag (m) is “1”, the overflow flag is set if the result of addition or subtraction is outside the range between –128 and +127. It is reset in the other cases. The overflow flag can also be set or reset directly with the SEP or CLV, CLP instructions. 8. Negative flag (N) The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag (m) is “0”, data bit 15 is “1”. If data length flag (m) is “1”, data bit 7 is “1”.) It is reset in the other cases. It can also be set or reset with the SEP or CLP instructions. 9. Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of 3 bits and determines the processor interrupt priority level (0 to 7). Interrupt is enabled when the interrupt priority level of the device requesting interrupt (the priority can be set using the interrupt control register) is higher than the processor interrupt priority level. When interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details. BUS INTERFACE UNIT The CPU operates on an internal clock ’s frequency. Internal clock ’s frequency is twice the bus cycle frequency. In order to speed up processing, a bus interface unit is used to pre-fetch instructions when the data bus is idle. The bus interface unit synchronizes the CPU and the bus and pre-fetches instructions. Figure 4 shows the relationship between the CPU and the bus interface unit. The bus interface unit has a program address register, a 3-byte instruction queue buffer, a data address register, and a 2-byte data buffer. The bus interface unit obtains an instruction code from the memory and stores it in the instruction queue buffer, obtains data from the memory and stores it in the data buffer, or writes the data from the data buffer to the memory. Fig. 4 Relationship between the CPU and the bus interface unit CPU Bus interface unit E ALE BYTE HOLD BHE R/W D 15 – D8 A23 – A0 D 7 – D0 D'15 – D'8 Control signal D'7 – D'0 A'23 – A'0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. The bus interface unit operates using one of the waveforms (1) to (10) shown in Figure 5. The standard waveforms are (1) and (2). The ALE signal is used to latch only the address signal from the multiplexed signal containing data and address. The E signal becomes “L” when the bus interface unit reads an instruction code or data from the memory or when it writes data to the memory. Whether to perform read or write is controlled by the W signal. The E (except for that in the single-chip mode) and R/W signals are not directly output to the outside. In the memory expansion mode or the microprocessor mode, read signal RDE and write signals WEL , WEH are output, instead of E and R/W , to the outside of the chip. During signal E is “L”, signal RDE becomes “L” (in the read cycle) or signals WEL and WEH become “L” (in the write cycle). Waveform (1) in Figure 5 is used to access a single byte or two bytes simultaneously. To read or write two bytes simultaneously, the first address accessed must be even. Furthermore, when accessing an external memory area in the memory expansion mode or the microprocessor mode, set the bus width selection input pin (BYTE) to “L” (external data bus has a width of 16 bits). The data bus in the internal memory area is always treated as the 16-bit bus independent of BYTE. Fig. 5 Bus access timing Port P2 E ALE Port P2 E ALE Internal clock φ Internal clock φ Port P2 E ALE A D A D A D A + 1 D A D A + 1 D A D A + 1 D (1) (2) (3) (4) (5) (6) Access time Access time Access time Access time Access time Access time A D D A + 1 A D A D A + 1 D (7) (8) (9) (10) Access time Access time D A A + 1 D AD A + 1 D Access time Access time A : Address D : Data During signal E is “L” in the memory expansion mode or the microprocessor mode, signal RDE becomes “L” (in the read cycle) or signals WEL and WEH become “L” (in the write cycle). Port P2 E ALE Port P2 E ALE Port P2 E ALE Port P2 E ALE Port P2 E ALE Port P2 E ALE Port P2 E ALE

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When performing 16-bit data read or write, waveform (2) is used to access each byte one by one if the conditions for simultaneously accessing two bytes are not satisfied. However, when prefetching the instruction code, if the address of the instruction code is odd, waveform (1) is used, and only one byte is read in the instruction queue buffer. Access to the even/odd address is controlled by signals BHE and A0. Signal BHE is not directly output to the outside, but write signals (WEL , WEH ) are generated corresponding to the accessed address (even or odd). Bit 2 of processor mode register 0 (address 5E 16) is the wait bit. When the external memory area is accessed in the memory expansion mode or the microprocessor mode with this bit set to “0”, the width of the E signal is extended and access time can be extended. There are two ways to extend the access time and they are selected with bit 0 of the processor mode register 1 (address 5F16). When this bit is set to “1”, the “L” width of the E signal in (1) becomes twice as long as in (3) and the access time becomes 1.5 times (wait 1). When this bit is set to “0”, the ALE signal and E signal in (1) are extended as in (7) and the access time is doubled (wait 0). However, these signals are not extended when accessing the internal memory area. When the wait bit is set to “1”, these signals are not extended when accessing any memory area regardless of the bit 0 of the processor mode register 1. Waveforms (4), (5), and (6) show the entire waveform, first half, and last half respectively of waveform (2) for wait 1. Waveforms (8), (9), and (10) show the entire waveform, first half, and last half respectively of waveform (2) for wait 0. Instruction code read, data read, and data write are described below. Instruction code read will be described first. The CPU obtains instruction codes from the instruction queue buffer and executes them. The CPU notifies the bus interface unit that it is requesting an instruction code during an instruction code request cycle. If the requested instruction code is not yet stored in the instruction queue buffer, the bus interface unit halts the CPU until more instructions than requested is stored in the instruction queue buffer. Even if there is no instruction code request from the CPU, the bus interface unit reads instruction codes from the memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruction code is stored and the bus is idle on the next cycle. This is referred to as instruction pre-fetching. Normally , when reading an instruction code from the memory, if the accessed address is even, the next odd address is read together with the instruction code and stored in the instruction queue buffer. However, in the memory expansion mode or the microprocessor mode, only one byte is read and stored in the instruction queue buffer if the following conditions are satisfied.

• The address to be read is in the external memory area when the external data bus has an 8-bit width (BYTE = “H”).
• The address to be read is odd. Therefore, waveform (1), (3) or (7) in Figure 5 is used for instruction code read. Data read and write are described below. The CPU notifies the bus interface unit when performing data read or write. At this time, the bus interface unit halts the CPU if the bus interface unit is already using the bus or if there is a request with higher priority. When data read or write is enabled, the bus interface unit uses one of the waveforms from (1) to (10) in Figure 5 to perform the operation. During data read, the CPU waits until the entire data is stored in the data buffer. The bus interface unit sends the address received from the CPU to the address bus. Then it reads the memory when the E signal is “L” and stores the result in the data buffer. During data write, the CPU writes the data in the data buffer and the bus interface unit writes it to the memory . Therefore, the CPU can proceed to the next step without waiting for write completed. The bus interface unit sends the address received from the CPU to the address bus. Then when the E signal is “L”, the bus interface unit sends the data in the data buffer to the data bus and writes it to the memory.

Notice: This is not a final specification. Some parametric limits are subject to change. is described in this section. DBC is an interrupt used only for debugging. BRK instruction all have their respective interrupt control registers. Figure 6 shows the bit configuration of the interrupt control register. DBC and watchdog timer can be cleared by software. port function control register (refer to Figure 11). Timer and UART interrupts are described in the respective section. Table 1. Interrupt sources and the interrupt vector addresses

Notice: This is not a final specification. Some parametric limits are subject to change. Table 2. Addresses of interrupt control registers are software interrupts and are not included in this list. corresponding interrupt control register with software. Figure 8 shows a diagram of the interrupt priority detection circuit. priorities are the same, the one above has priority. disable flag (I) to “0” and enable further interrupts. processor interrupt level (IPL) is set as shown in Table 3. and interrupt priority level selection bits so that they do not change.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 3. Value set in processor interrupt level (IPL) during an interrupt Table 4. Relationship between interrupt priority detection time selec- Zero divide Not change value of IPL. BRK instruction Not change value of IPL. The processor is reset when this bit is set to “1”.

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up resistors (transistors) can be added to the KI0 to KI3 pins by setting “1” to the port P5 pull-up selection bit and “0” to the contents of the port P5i (i = 4 to 7) direction register. Similarly, a pull-up resistor can be added to the INT2 pin by setting “1” to the port P6 pull-up selection bit 1 and “0” to the content of the port P64 direction register. With the key input interrupt and the pull-up function, the key input circuit is easily composed. Fig. 12 INT2 /Key input interrupt input circuit block diagram By setting the port function control register, the INT2/Key input interrupt function can be switched to the key input interrupt function which uses the KI0 to KI3 inputs. Figure 11 shows the bit configuration of the port function control register, and Figure 12 shows the INT2 /Key input interrupt input circuit block diagram. When the key input interrupt selection bit of the port function control register is “0”, a signal is input from the INT2 pin to the INT2 /Key input interrupt control circuit and the INT2 interrupt is normally performed. When the key input interrupt selection bit is “1”, signals input from the KI0 to KI3 pins are inverted, and then the logical sum of these signals is input to the INT2 interrupt control circuit. In this case, the external interrupt which uses the KI0 to KI3 pins is performed. (Pins KI0 to KI3 correspond to ports P54 to P57, respectively.) Additionally, by setting the port P6 pull-up selection bit 1 to “1”, the INT2 input is added to that logical sum, so that the external interrupt which uses the inputs KI0 to KI3 and INT2 is performed. When using the key input interrupt, it is necessary to select the edge sense which uses the falling edge by setting the INT2 /Key input interrupt control register. Because of this selection, a key input interrupt request occurs when “L” is input to one of the KI0 to KI3 and INT2 pins. The interrupt vector and the interrupt control register are common to the INT2 and key input interrupts. INT2/Key input interrupt control register Interrupt control register P64/INT2 P57/KI3 P55/KI1 P56/KI2 P54/KI0 INT2/Key input interrupt request Key input interrupt selection bit (Address 7F16) When the key input interrupt is selected, it is necessary to select the edge sense which uses falling edge. Pull–up transistor Port P5 pull-up selection bit Port P57 direction register Pull–up transistor Pull–up transistor Pull–up transistor Port P6 pull-up selection bit 1 Port P64 direction register Port P6 pull-up selection bit 1

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 11 Bit configuration of port function control register Standby state selection bit 0: Pins P0 – P3 as external bus output 1: Pins P0 – P3 as port output Sub-clock output selection bit/Timer B2 clock source selection bit Port-Xc selection bit = “0” (sub-clock not used) Timer B2 (event counter mode) clock source selection 0: TB2 IN input 1: Main clock divided by 32 Port-Xc selection bit = “1” (sub-clock used) Sub-clock output selection 0: Function as port P6 7 pin 1: Output sub-clock φ SUB from P67/TB2IN/ φ SUB pin Timer B1 internal connect selection bit 0: No internal connect 1: Internal connect to timer B2 Port P6 pull-up selection bit 0 0: With no pull-up transistor for pins P6 2/INT0, P63/INT1 1: With pull-up transistor for pins P62/INT0, P63/INT1 0: Always “0” Port P6 pull-up selection bit 1

• Key input interrupt selection bit = “0” 0: With no pull-up transistor for P64/INT2 pin 1: With pull-up transistor for P64/INT2 pin
• Key input interrupt selection bit = “1” 0: With port function, no pull-up transistor for P64/INT2 pin 1: With key input interrupt, pull-up transistor for P64/INT2 pin Port P5 pull-up selection bit 0: With no pull-up transistor for pins P5 4 – P57 1: With pull-up transistor for pins P54 – P57 Key input interrupt selection bit INT2 interrupt 1: Key input interrupt 7654 321 Port function control register Address 6D 16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. When bit 2 of the timer Ai mode register is “1”, the output is generated from TAiOUT pin. The output is toggled each time the contents of the counter reaches to 000016. When the contents of the count start flag is “0”, “L” is output from TAiOUT pin. When bit 2 is “0”, TAiOUT can be used as a normal port pin. When bit 4 is “0”, TAiIN can be used as a normal port pin. When bit 4 is “1”, counting is performed only while the input signal from the TAi IN pin is “H” or “L” as shown in Figure 16. Therefore, this can be used to measure the pulse width of the TAiIN input signal. Whether to count while the input signal is “H” or while it is “L” is determined by bit 3. If bit 3 is “1”, counting is performed while the TAi IN pin input signal is “H” and if bit 3 is “0”, counting is performed while it is “L”. Note that the duration of “H” or “L” on the TAiIN pin must be two or more cycles of the timer count sourse. When data is written to the timer Ai register with timer Ai halted, the same data is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The contents of the counter can be read at any time. When the value set in the timer Ai register is n, the timer frequency dividing ratio is 1/(n + 1). Fig. 14 Timer Ai mode register bit configuration during timer mode 0 0 : Always “00” in timer mode 0 : No pulse output (TAiOUT is normal port pin) 1 : Pulse output 0 5 : No gate function (TAiIN is normal port pin) 1 0 : Count only while TAiIN input is “L” 1 1 : Count only while TAiIN input is “H” 62 3 4 51 0 : Always “0” in timer mode Clock source selection bit 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 Timer A0 mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816 Timer A3 mode register 5916 Timer A4 mode register 5A16 Addresses

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 15 Count start flag bit configuration Fig. 16 Count waveform when gate function is available 70 654321 Count start flag (Stop at “0”, Start at “1”) Timer A0 count start flag Timer B2 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Address Selected clock source fi TAiN Timer mode register Bit 4 Bit 3 Bit 4 Bit 3 Timer mode register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (2) Event counter mode [01] Figure 17 shows the bit configuration of the timer Ai mode register during the event counter mode. In the event counter mode, the bit 0 of the timer Ai mode register must be “1” and bits 1 and 5 must be “0”. The input signal from the TAi IN pin is counted when the count start flag shown in Figure 15 is “1” and counting is stopped when it is “0”. Count is performed at the fall of the input signal when bit 3 is “0” and at the rise of the signal when it is “1”. In the event counter mode, whether to increment or decrement the count can be selected with the up-down flag or the input signal from the TAi OUT pin. When bit 4 of the timer Ai mode register is “0”, the up-down flag is used to determine whether to increment or decrement the count (decrement when the flag is “0” and increment when it is “1”). Figure 18 shows the bit configuration of the up-down flag. When bit 4 of the timer Ai mode register is “1”, the input signal from the TAi OUT pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be “0” if bit 4 is “1”. Because TAiOUT pin becomes an output pin with pulse output if bit 2 is “1”. The count is decremented when the input signal from the TAiOUT pin is “L” and incremented when it is “H”. Determine the level of the input signal from the TAi OUT pin before an effective edge is input to the TAiIN pin. An interrupt request signal is generated and the interrupt request bit of the timer Ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or FFFF16 (increment count). At the same time, timers A0 and A1 transfer the contents of the reload register to the counter and continue counting. Timers A2, A3, and A4 transfer the contents of the reload register to the counter and continue count when bit 6 of the corresponding timer Ai mode register is “0”, but when bit 6 is “1”, they continue counting without transferring the contents of the reload register to the counter. When bit 2 is “1”, the waveform of which polarity is reversed each time the counter reaches 0000 16 (decrement count) or FFFF16 (increment count) is output from TAiOUT pin. If bit 2 is “0”, the TAiOUT pin can be used as a normal port pin. However, if bit 4 is “1” and the TAiOUT pin is used as an output pin, the output from the TAiOUT pin changes the count direction. Therefore, bit 4 must be “0” unless the output from the TAi OUT pin is used to select the count direction. Data write and data read are performed in the same way as for the timer mode. That is, when data is written to timer Ai which is halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not the counter. The counter is reloaded with new data from the reload register at the next reload time and continues counting. For timers A2, A3, and A4, the contents of the reload register is not reloaded in the counter when bit 6 of the corresponding timer Ai mode register is “1”. The contents of the counter can be read at any time. Fig. 18 Up-down flag bit configuration Fig. 17 Timer Ai mode register bit configuration during event counter mode Timer A0 up-down flag 7 6543 2 1 0 4416 Addresses Up-down flag Timer A1 up-down flag Timer A2 up-down flag Timer A4 up-down flag Timer A3 two-phase pulse signal processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A2 two-phase pulse signal processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A4 two-phase pulse signal processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A3 up-down flag This bit is available for timer A3. 0 : Two-phase pulse signal processing in the same manner as timer A2 1 : Two-phase pulse signal processing in the same manner as timer A4 0 1 : Always “01” in event counter mode 7 6543 2 1 0 00 1 0 : No pulse output 1 : Pulse output 0 : Count at the falling edge of input signal 1 : Count at the rising edge of input signal 0 : Increment or decrement according to up-down flag 1 : Increment or decrement according to TAi OUT pin input signal level 0 : Always “0” in event counter mode This bit is available for times A2, A3, and A4. 0 : Reload 1 : No reload Timer A0 mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816 Timer A3 mode register 5916 Timer A4 mode register 5A16 Addresses

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 21 Timer Aj mode register bit configuration when performing two-phase pulse signal processing in event counter mode Fig. 20 Two-phase pulse signal processing operation of timer A4 Fig. 19 Two-phase pulse signal processing operation of timer A2 Furthermore, in the event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90° to timer A2, A3, or A4. There are two types of two-phase pulse signal processing operations. One uses timer A2 and the other uses timer A4. Timer A3 can select one of these two operations with bit 7 of the timer A3 mode register. In both processing operations, two kinds of pulses of which phases differ by 90° are input to the TAj OUT (j = 2 to 4) pin and TAjIN pin respectively. After the level of the TA2OUT pin changes from “L” to “H” with timer A2 used, as shown in Figure 19, the count is incremented when a rising edge is input to the TA2 IN pin and the count is decremented when the falling edge is input. For timer A4, as shown in Figure 20, when a phase related pulse with a rising edge input to the TA4 IN pin is input after the level of TA4 OUT pin changes from “L” to “H”, the count is incremented at the respective rising edge and falling edge of the TA4OUT pin and TA4IN pin. When a phase related pulse with a falling edge input to the TA4OUT pin is input after the level of TA4IN pin changes from “H” to “L”, the count is decremented at the respective rising edge and falling edge of the TA4 IN pin and TA4OUT pin. When performing this two-phase pulse signal processing, bits 0 and 4 of the timer Aj mode register must be set to “1” and bits 1, 2, 3, and 5 must be set to “0” as shown in Figure 21. Bit 7 is used to select whether to perform two-phase pulse signal processing for timer A3 in the same manner as timer A2 or as timer A4. When this bit is “0”, two-phase pulse signal processing for timer A3 is performed in the same manner as timer A2 and when it is “1”, it is performed in the same manner as timer A4. This bit is ignored for timers A2 and A4. Note that bits 5, 6, and 7 of the up-down flag (address 44 16) are the two-phase pulse signal processing selection bits for timers A2, A3, and A4, respectively. Each timer operates in the normal event counter mode when the corresponding bit is “0” and performs two-phase pulse signal processing when it is “1”. Count is started by setting the count start flag to “1”. Data write and read are performed in the same way as for the normal event counter mode. Note that the port direction register of the input port must be set to the input mode because two-phase pulse signal is input. Also, there can be no pulse output in this mode. Increment count Increment count Increment count Decrement count Decrement count TA2 OUT TA2 IN TA4 OUT TA4 IN Increment count at each edge Decrement count at each edge Increment count at each edge Decrement count at each edge Addresses 0 1 : Always “01” in event counter mode 7 6543 2 1 0 00 1 0 1 0 0 : Always “0100” when processing two-phase pulse signal Timer A2 mode register 58 Timer A3 mode register 5916 Timer A4 mode register 5A16 100 0 : Reload 1 : No reload This bit is avilable for timer A3 0 : Two-phase pulse signal processing in the same manner as timer A2 1 : Two-phase pulse signal processing in the same manner as timer A4 Decrement count

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Data write is performed in the same way as for the timer mode. When data is written in timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time and continues counting. Undefined data is read when timer Ai is read. Fig. 23 One-shot start flag bit configuration Fig. 25 Example when trigger is re-issued during pulse output Fig. 24 Pulse output example when external rising edge is selected 70 654321 One-shot start flag Timer A0 one-shot start flag Timer A4 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Address Selected clock source fi TAiIN (rising edge is selected) TAiOUT Selected clock source fi TAiIN (rising edge is selected) TAi OUT 70 654321 One-shot start flag Timer A0 one-shot start flag Timer A4 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Address Selected clock source fi TAiIN (rising edge is selected) TAiOUT Selected clock source fi TAiIN (rising edge is selected) TAi OUT In this case, the contents of the reload register is In this case, the contents of the reload register is 000416. 000316.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (4) Pulse width modulation mode [11] Figure 26 shows the bit configuration of the timer Ai mode register during the pulse width modulation mode. In the pulse width modulation mode, bits 0, 1, and 2 must be set to “1”. Bit 5 is used to determine whether to perform as the 16-bit length pulse width modulator or the 8-bit length pulse width modulator. 16- bit length pulse width modulator is selected when bit 5 is “0” and 8-bit length pulse width modulator is selected when bit 5 is “1”. The 16-bit length pulse width modulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAi IN pin (external trigger). The software trigger mode is selected when bit 4 is “0”. Pulse width modulator is started and pulse is output from the TAi OUT pin when the timer Ai start flag is set to “1”. The external trigger mode is selected when bit 4 is “1”. Pulse width modulator starts when a trigger signal is input from the TAi IN pin when the timer Ai start flag is “1”. Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is “0” and at the rise when it is “1”. When data is written to timer Ai with the pulse width modulator halted, it is written to the reload register and the counter. Then when the timer Ai start flag is set to “1” and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 27 is output continuously. Once modulation is started, triggers are not accepted. If the value in the reload register is m, the duration “H” of pulse is The reload register and the counter are both divided into 8-bit halves. The low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6 and 7. A pulse is generated when the counter reaches 0000 16 as shown in Figure 28. At the same time, the contents of the reload register is transferred to the counter, and count is continued. Fig. 26 Timer Ai mode register bit configuration during pulse width modulation mode An interrupt request signal is generated and the interrupt request bit of the timer Ai interrupt control register is set at each fall of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register is transferred to the counter just before the rise of the next output pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when bit 5 of the timer Ai mode register is “1”. selected clock frequency 5 m and the output pulse period is selected clock frequency5 (216 – 1). 76 54321 0 11 1 Timer A0 mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816 Timer A3 mode register 5916 Timer A4 mode register 5A16 Addresses 1 : Always “1” in pulse width modulation mode 0 5 : Software trigger 1 0 : Trigger at the falling of TAiIN input 1 1 : Trigger at the rising of TAiIN input Clock source selection bit 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 1 1 : Always “11” in pulse width modulation mode 0 : 16 bit pulse width modulator 1 : 8 bit pulse width modulator

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. selected clock frequency5 (n + 1). The high-order 8 bits function as an 8-bit length pulse width modulator using this pulse as input. Its operation is the same as for 16-bit length pulse width modulator except it has a length of 8 bits. If the high- order 8 bits’ contents of the reload register is m, the duration “H” of pulse is Therefore, if the low-order 8 bits of the reload register is n, the period of the generated pulse is selected clock frequency 5 (n + 1) 5 m. selected clock frequency5 (n + 1) 5 (28 – 1). Fig. 28 8-bit length pulse width modulator output pulse example Fig. 27 16-bit length pulse width modulator output pulse example And the output pulse period is Selected clock source fi TAiIN (rising edge is selected) TAiOUT 1 / fi 5 (216 – 1) 1 / fi 5 (m) This trigger is not accepted In this case, the contents of the reload register is 000316. Selected clock source fi 8-bit length pulse width modulator output (when m = 2) TAi IN (falling edge is selected) 1 / fi 5 (n + 1) (when n = 2) Prescaler output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. When timer Bi is read, the contents of the reload register is read. Note that, in this mode, the interval from the fall of the TBiIN pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer Bi overflow flag which is bit 5 of the timer Bi mode register is set to “1” when the timer Bi counter reaches 0000 16. This flag is cleared by writing to the corresponding timer Bi mode register. By reading this flag, the reason why the interrupt request signal is generated, which is the completion of measurement or the counter overflow, can be detected. An interrupt request signal may occur because the counter value is particularly undefined just after counting starts. Accordingly, make sure to detect the occurrence reason of an interrupt request signal with the timer Bi overflow flag. This flag is “1” at reset. When using timer B2 as the clock timer and using timer B1 in the internal connect mode, functions in this mode are lost. Fig. 32 Timer Bi mode register bit configuration during pulse period measurement/pulse width measurement mode Fig. 33 Pulse period measurement mode operation (example of measuring the interval from the falling edge to next falling one) Selected clock source fi TBiIN Reload register← Counter Counter← 0 Count start flag Interrupt request signal 76 54 32 10 0 1 0 1 0 : Always “10” in pulse period measurement/pulse width measurement mode 0 0 : Count from the falling edge of input signal to the next falling one 0 1 : Count from the rising edge of input signal to the next rising one 1 0 : Count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one 0 : Always “0” in pulse period measurement/pulse width measurement mode (timer B0) 5 : Not used in pulse period measurement/pulse width measurement mode (timers B1, B2) Timer Bi overflow flag Clock source selection bit 0 0 : Select f 0 1 : Select f16 1 1 : Select f512 1 0 : Select f64 Timer B0 mode register 5B16 Timer B2 mode register 5D16 Timer B1 mode register 5C16 Addresses

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. UART 0 transmit/receive mode register 3016 UART 1 transmit/receive mode register 3816 Addresses Serial I/O mode selection bits 0 0 0 : Parallel port 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART 76543 2 1 0 Internal clock/External clock selection bit 0 : Internal clock 1 : External clock Stop bit length selection bit 0 : 1 stop bit 1 : 2 stop bits Odd/even parity selection bit 0 : Odd parity 1 : Even parity Parity enable bit 0 : No parity 1 : With parity Sleep function selection bit 0 : No sleep 1 : Sleep Data bus (odd) Data bus (even) Bit converter 00 000 00 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 8 Receive register Receive buffer register UART0 (Addresses 3716, 3616) UART1 (Addresses 3F16, 3E16) UART2 (Addresses 6B16, 6A16) Receive control circuit RxDi Data bus (even) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 8 Transmisson register UART0 (Addresses 3316, 3216) UART1 (Addresses 3B16, 3A16) UART2 (Addresses 6716, 6616) control circuit Transmission Bit converter Transmission buffer register Polarity reversing circuit f 2 f 16 f 64 f 512 CLKi CTSi/RTSi 1/16 Divider UART receive Clock synchronous 1/16 Divider Clock synchronous 1/2 Divider Clock synchronous (Internal clock) Clock synchronous (External clock) 1/(n + 1) Divider External Internal Clock source selection Bit rate generator UART0 (Address 3116) UART1 (Address 3916) UART2 (Address 6516) Receive clock Transmission clock Data bus (odd) TxDi Clock synchronous (Internal clock) UART transmission (Note) (Note) (Note) (Note) Note. UART2 does not include the bit converter, the polarity reversing circuit and the RTS i output. UART 2 transmit/receive mode register 6416 Address Serial I/O mode selection bits 0 0 0 : Parallel port 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART 6543 2 1 0 Internal clock/External clock selection bit 0 : Internal clock 1 : External clock Stop bit length selection bit 0 : 1 stop bit 1 : 2 stop bits Odd/even parity selection bit 0 : Odd parity 1 : Even parity Parity enable bit 0 : No parity 1 : With parity The switch of A-D conversion interrupt and UART2 transmit/receive interrupt is performed by bits 0 to 2. When selecting a parallel port, A-D conversion interrupt is valid. When selecting a clock synchronous serial I/O port or a UART, UART2 transmit/receive interrupt is valid. Note. SERIAL I/O PORTS Three independent serial I/O ports are provided. Figure 36 shows a block diagram of the serial I/O ports. Table 5 shows the functional differences of three serial I/O ports (UART 0, 1, 2). Bits 0, 1, and 2 of the UARTi (i = 0, 1, 2) transmit/receive mode register shown in Figure 37 are used to determine whether to use port P8 or port P7 as a parallel port, a clock synchronous serial I/O port, or an asynchronous serial I/O port (UART) using start and stop bits. Fig. 36 Serial I/O port block diagram Fig. 37 UARTi transmit/receive mode register bit configuration

Notice: This is not a final specification. Some parametric limits are subject to change. Note. UART2 does not include the bit converter. the A-D conversion interrupt and UART2 transmit/receive interrupt. Figure 38 shows the connections of receiver/transmitter. Each communication method is described below. Table 5. Differences between UART0, UART1 and UART2 Note. The interrupt vector and the interrupt control register are common to the A-D conversion interrupt and UART2 transmit/receive interrupt. It is switched by a selection of UART2 function.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 39 UART0, UART1 transmit/receive control registers bit configuration UART0 transmit/receive control register 0 3416 UART1 transmit/receive control register 0 3C16 Addresses TFM CPL TxS Tx EPTY R/C CS 1 CS 0 BRG count source selection bits 00 : Select f2 01 : Select f16 10 : Select f64 11 : Select f512 CTS /RTS selection bit 0 : Select CTS 1 : Select RTS Transmission register empty bit CTS , RTS enable bit 0 : Enble CTS and RTS 1 : Disable CTS and RTS (I/O port) Data output selection bit 0 : CMOS output 1 : N-channel open-drain output CLK polarity selection bit 0 : In transferring, transmit data is output at the CLKi's falling edge or received data is input at the CLKi's rising edge. Not in transferring, CLKi level is "H". 1 : In transferring, transmit data is output at the CLKi's rising edge or received data is input at the CLKi's falling edge. Not in transferring, CLKi level is "L". Transfer format selection bit 0 : LSB first 1 : MSB first 76543210 SUM PER FER OER RI RE TI TE Transmit enable flag Transmit buffer empty flag Receive enable bit Receive completing flag Overrun error flag Framing error flag Parity error flag Error sum flag 76543210 UART0 transmit/receive control register 1 3516 UART1 transmit/receive control register 1 3D16 Addresses

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 40 UART2 transmit/receive control register bit configuration UART2 transmit/receive control register 0 6816 Addresses Tx EPTY R/C CS 1 CS 0 BRG count source selection bits 00 : Select f2 01 : Select f16 10 : Select f64 11 : Select f512 CTS enable bit 0 : Enable CTS 1 : Disable CTS (I/O port) Transmission register empty bit 76543210 SUM PER FER OER RI RE TI TE Transmit enable flag Transmit buffer empty flag Receive enable bit Receive completing flag Overrun error flag Framing error flag Parity error flag Error sum flag 76543210 UART2 transmit/receive control register 1 6916 Addresses

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. The bit 2 of the clock sending side UARTj transmit/receive control register 0 is cleared to “0” to select CTS j input. The bit 2 of the clock receiving side is set to “1” to select RTS k output. Whether to use the CTS and RTS signals is determined by bit 4 of the UART transmit/receive control register 0. Set bit 4 to “0” when CTS and RTS signals are used, and to “1” when they are not used. UART2 has the CTS input function, but that does not have the RTS output function (refer to Figure 40.) When CTS and RTS signals are not used, the CTS /RTS pin can be used as a normal port. The following describes the case when the CTS and RTS signals are used. If CTS and RTS signals are not used, the CTS j input condition is unnecessary and there is no RTS k output. Output driver format of the transmit data output pin (TXDj), which is the CMOS output or the N-channel open-drain output, is selected with bit 5 (T XS) of the UARTj transmit/receive control register 0. When bit 5 is “0”, the CMOS output format is selected. When bit 5 is “1”, the N-channel open-drain output format is selected. When the N-channel open-drain output format is selected, make sure to pull-up the data line using a pull-up resistor. CLOCK SYNCHRONOUS SERIAL COMMUNICATION A case where communication is performed between two clock synchronous serial I/O ports as shown in Figure 41 will be described. (The transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k.) Bit 0 of the UARTj transmit/receive mode register and UARTk transmit/ receive mode register must be set to “1”, and bits 1 and 2 must be “0”. The length of the transmission data is 8 bits. Bit 3 of the UART j transmit/receive mode register of the clock sending side is cleared to “0” to select the internal clock. Bit 3 of the UARTk transmit/receive mode register of the clock receiving side is set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in the clock synchronous mode. Bit 7 must always be “0”. The clock source is selected by bit 0 (CS 0) and bit 1 (CS1) of the clock sending side UARTj transmit/receive control register 0. If the contents of the bit rate genarator is n, as shown in Figure 36, the selected clock is divided by (n + 1), then by 2, passed through a transmission control circuit, and output as transmission clock CLK Therefore, when the selected clock is fi, Bit Rate = fi / {(n + 1) 5 2} On the clock receiving side, the CS0 and CS1 bits are ignored because an external clock is selected. Fig. 41 Clock synchronous serial communication UART j transmission register UART j transmission buffer register UART j receive buffer register UART j receive register RI PER SUM FER OER RE TI TE TxD j TxD k RxD j RxD k CLK j CLK k CTS j RTS k 50 55 000 1 UART j transmit/receive mode register 0TFM CPL TxS Tx EPTY 0 CS 1 CS 0 UART j transmit/receive control register 0 UART j transmit/receive control register 1 UART k transmission register UART k transmission buffer register UART k receive buffer register UART k receive register TFM CPL TxS Tx EPTY01 55 FER RI PER SUM OER RE TI TE UART k transmit/receive control register 0 UART k transmit/receive control register 1 155500 0 1 UART k transmit/receive mode register Note. UART2 does not include RTS output. The UART2 transmit/receive control register 0’s bit configuration is partialy different.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. The internal/external clock polarity is selected with bit 6 (CPL) of the UART j transmit/receive control register 0. When bit 6 is “0”, transmit data is output at the CLKj’s falling edge in transmitting, received data is input at the CLKk’s rising edge in receiving, and the CLKi level is “H” not in transferring (transmitting/receiving). When bit 6 is “1”, reversely, transmit data is output at the CLK j’s rising edge in transmitting, received data is input at the CLKk’s falling edge in receiving, and the CLKi level is “L” not in transferring. Bit transfer order of transmit/received data, which is LSB first or MSB first (Note), is selected with bit 7 (TFM) of the UART j transmit/receive control register 0. LSB first is selected when bit 7 is “0”, and MSB first is selected when bit 7 is “1”. However, UART2’s function is fixed to the function specified by TxS=CPL=TFM=“0”, and it cannot be changed. Note that, only in the UART 0 transmission mode, the transmission clock can be output not only from the CLK0 pin but also from the other output pins (CLKS0, CLKS1). Transmission clock output multiple- selection mode is set with the serial transmit control register and others. For details, refer to the section on transmission. Note. When LSB first is selected, data is transmitted/received beginning at the least significant bit (LSB). When MSB first is selected, data is transmitted/received beginning at the most significant bit (MSB). Transmission Transmission is started when the bit 0 (TEj flag) of the UARTj transmit/ receive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and the CTS j input is “L”. Transmit data is output each time when the transmission clock (CLKj) level changes from “H” to “L” with bit 6 (CPL) of the UARTj transmit/ receive control register 0 “0” or is output each time when the CLKj level changes from “L” to “H” with CPL “1”. For details, refer to Figure 42. In addition, transmit data is output beginning at the least significant bit (LSB) with bit 7 (TFM) of the UART j transmit/receive control register “0” or is output beginning at the most significant bit (MSB) with TFM “1”. The TI j flag indicates whether the transmission buffer register is empty or not. It is cleared to “0” when date is written in the transmission buffer register and set to “1” when the contents of the transmission buffer register is transferred to the transmission register. Fig. 42 Clock synchronous serial I/O timing TEj Transmission clock (CPL = “0” ) TENDj CTSj 1 / fi 5 ( n + 1 ) 5 2 Write in transmission buffer register D 0 D 1 D 2 D 3 D 4 D 5 TIj (CPL = “1” ) CLKj (TFM = “0” ) (TFM = “1” ) TXD j TXEPTY j 1 / fi 5 ( n + 1 ) 5 2 Stopped because TEj = “0” D 6 D 7 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Transmission register Transmission buffer register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. 76543 2 01

0 TE UART0 transmit/receive

0 : Receiving is disabled 3516 Address UART0 transmit/receive mode register 76543 2 0 0555 0 0 Address 3016 001 : Clock synchronous 0 : Internal clock 0 : always “0” 555 : Not used Transfer format selection bit 0 : LSB first 1 : MSB first /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 1 : Disable CTS and RTS (I/O port) Data output selection bit 0 : CMOS output 1 : N-channel open-drain output 76543 2 0 1TPM CPL TxS CS 1 CS 2 UART0 transmit/receive control register 0 Clock source selection bits 0 0 : Select f 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 5 : Not used CLK polarity selection bit 0 : In transmitting, transmit data is output at the CLK's falling edge. Not in transmitting, CLK 0 level is “H”. 1 : In transmitting, transmit data is output at the CLK0's rising edge. Not in transmitting, CLK 0 level is “L”. Address 3416 Fig. 45 Bit configuration of UART0 transmit/receive mode register and UART0 transmit/receive control register 0/1 in the transmission clock output multiple-selection mode Receive Receive starts when the bit 2 (REk flag) of the UARTk transmit/receive control register 1 is set to “1”. The RTS k output level is “H” when the REk flag is “0”, but it is “L” when the REk flag is “1” and the TIk flag is “0”. Furthermore, the RTS k output level is “H” again when receiving restarts. The TIk flag is cleared to “0” by writing dummy data into the transmission buffer register. When the RTS k output level is “L”, receiving for the receive register is enabled. UART2 does not have the RTS output function. When bit 6 (CPL) of the UARTk transmit/receive control register 0 is “0”, the contents of the receive register is shifted by 1 bit each time when the receive clock (CLK k) changes from “L” to “H”. When CPL is “1”, the contents is shifted by 1 bit each time when CLKk changes from “H” to “L”. These shifts are performed simultaneously with the data reception from the R XD k pin. When an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and the bit 3 (RI k flag) of the UARTk transmit/receive control register 1 is set to “1”. In other words, the setting of the RIk flag to “1” indicates that the receive buffer register contains the received data. When the TI k flag goes “0”, RTS k output level goes “L” to indicate that the next data can be received. When the RIk flag changes from “0” to “1”, the interrupt request bit of the UARTk receive (transmit/receive in UART2) interrupt control register is set to “1”. Bit 4 (OERk flag) of the UART k transmit/receive control register is set to “1” when the next data is transferred from the receive register to the receive buffer register while RI k flag is “1”, and the OERk flag indicates that the next data was transferred to the receive buffer register before the contents of the receive buffer register was read. The RI k flag is cleared to “0” when reading the low-order byte to the receive buffer, when writing “0” to the REk flag, or when setting to be a parallel port. The OERk flag is cleared to “0” when writing “0” to the RE k flag or when setting to be a parallel port. The FERk, PERk, and SUM k flags are ineffective in the clock synchronous communication. The received data in the receive buffer register is read into the data bus according to the LSB first (beginning at the least significant bit) when bit 7 (TEM) of the UART k transmit/receive control register 0 is “0” or according to the MSB first (beginning at the most significant bit) when bit 7 is “1”. As shown in Figure 36, with clock synchronous serial communication, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock. Therefore, the transmitter must be operating even when there is no data to be sent from UART k to UARTj.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ASYNCHRONOUS SERIAL COMMUNICATION (UART) Asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. The operation is the same for all data lengths. The following is the description for 8-bit asynchronous communication. With 8-bit asynchronous communication, the bits 2 to 0 of the UART i transmit/receive mode register must be “101”. Bit 3 is used to select an internal clock or an external clock. If bit 3 is “0”, an internal clock is selected and if bit 3 is “1”, then external clock is selected. If an internal clock is selected, the bit 0 (CS 0) and bit 1 (CS1) of UARTi transmit/receive control register 0 are used to select the clock source. When an internal clock is selected for asynchronous serial communication, the CLK i pin can be used as a normal port. If the content of the bit rate generator is n, the selected internal or external clock is divided by (n + 1), then by 16, and passed through a control circuit to create the UART transmission clock or the UART receive clock. If the selected clock is an internal clock fi or an external clock f EXT , Bit Rate = (fi or fEXT ) / {(n + 1) 5 16} Bit 4 selects 1 stop bit or 2 stop bits. The bit 5 is a selection bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum of the 1’s in the data and parity bit is always odd. In the even parity mode, the parity bit is adjusted so that the sum of the 1’s in the data and parity bit is always even. Fig. 47 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected Fig. 46 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected D 6 D 7ST D 1 D 2 D 3 D 4 D 5 P SP ST ST D 0 D 1 TE i (1 / f1 , or 1 / fEXT ) 5 (n + 1) 5 16 Transmission clock CTS i Write in transmission buffer register TIi TENDi TXD i TXEPTY i Transmission register ← Transmission buffer register Stopped because TEi = “0” Start bit Parity bit Stop bit D 0 D 6 D 7D 1 D 2 D 3 D 4 D 5 P SPD 0 TE i Transmission clock TIi TENDi TXD i TXEPTY i (1 / f1 , or 1 / fEXT ) 5 (n + 1) 5 16 Write in transmission buffer register Transmission register ← Transmission buffer register Stopped because Start bit Stop Bit Stop Bit TEi = “0” D 6ST D 1 D 2 D 3 D 4 D 5 D 8 SP ST D 0 D 1D 0 D 6 D 7D 1 D 2 D 3 D 4 D 5 SPD 0D 7 SP SPD 8ST D 2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Bit 6 is the parity enable bit which indicates whether to add parity bit or not. Bits 4 to 6 should be set or reset according to the data format of the communicating devices. Bit 7 is the sleep selection bit (refer to the next page). Bit 2 of the UART i transmit/receive control register 0 is used to determine whether to use CTS i input or RTS i output. CTS i input is used if bit 2 is “0” and RTS i output is used if bit 2 is “1”. If CTS i input is selected, the user can control whether to stop or start transmission with external CTS i input. Whether to use CTS and RTS signals is determined by bit 4 of the UART transmit/receive control register 0. Set bit 4 to “0” when CTS and RTS signals are used, and to “1” when they are not used. UART2 has the CTS input function, but that does not have the RTS output function (refer to Figure 40.) When CTS and RTS signals are not used, the CTS RTS pin can be used as a normal port. The following describes the case when the CTS and RTS signals are used. If CTS and RTS signals are not used, the CTS i input condition is unnecessary and there is no RTS i output. In addition, output driver format of the transmission data output pin X D j ), which is CMOS output or N-channel open-drain output, is selected with bit 5 (T X S) of the UART j transmit/receive control register 0. CMOS output format is selected when bit 5 is “0”, and N-channel open-drain output format is selected when bit 5 is “1”. When N-channel open-drain output format is selected, make sure to pull-up the data line using a pull-up resistor. However, UART2 does not have bit 5 (TxS) and the format is always CMOS output. In asynchronous serial communication, bits 6 and 7 of the UART j transmit/receive control register 0 must be “0”. Transmission Transmission is started when the bit 0 (TE i flag) of UART i transmit/ receive control register 1 is “1”, the bit 1 (TI i flag) is “0”, and CTS i input is “L” if CTS i input is selected. As shown in Figures 46 and 47, data is output from the T X D i pin with the start bit and the stop bit or parity bit specified by the bits 4 to 6 of UART i transmit/receive mode register. The data is output beginning at the least significant bit. The TI i flag indicates whether the transmission butter is empty or not. It is cleared to “0” when data is written in the transmission buffer and set to “1” when the contents of the transmission buffer register is transferred to the transmission register. When the transmission register becomes empty after the contents has been transmitted, data is transferred automatically from the transmission buffer register to the transmission register if the next transmission start condition is satisfied. Once transmission has started, the TE i flag, TI i flag, and CTS i signal (if CTS i input is selected) are ignored until data transmission is completed. Therefore, transmission does not stop until it completes even if the TE i flag is cleared during transmission. As shown in Figure 46, CTS i input and flags TE i and TI i , which indicate the transmission start condition, are checked while the T END i signal is “H”. Therefore, data can be transmitted continuously if the next transmission data is written in the transmission buffer register and TI i flag is cleared to 0 before the T ENDi signal goes “H”. The bit 3 (T X EPTY i flag) of the UART i transmit/receive control register 0 changes to “1” at the next cycle after the T ENDi signal goes “H” and changes to “0” when transmission starts. Therefore, this flag can be used to determine whether data transmission is completed. When the TIi flag changes from “0” to “1”, the interrupt request bit of the UART i transmission (transmit/receive in UART2) interrupt control register is set to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Receive Receive is enabled when bit 2 (REi flag) of the UARTi transmit/receive control register 1 is set to “1”. As shown in Figure 48, the frequency divider circuit at the receiving end begin to work when a start bit is arrived and the data is received. If RTS i output is selected by setting bit 2 of the UARTi transmit/receive control register 0 to “1”, the RTS i output is “H” when the REi flag is “0”. When the REi flag changes to “1”, the RTS i output goes “L” to indicate receive ready and returns to “H” once receive has started. In other words, RTS i output can be used to determine externally whether the receive register is ready to receive. (UART2 does not have the RTS output function.) The entire transmission data bits are received when the start bit passes the final bit of the receive register of the receive block shown in Figure 38. At this point, the contents of the receive register is transferred to the receive buffer register and the bit 3 of the UART i transmit/receive control register 1 (RIi flag) is set. In other words, the RIi flag indicates that the receive buffer register contains data when it is set. If RTS i output is selected, RTS i output goes “L” to indicate that the register is ready to receive the next data. The interrupt request bit of the UART i receive (transmit/receive in UART2) interrupt control register is set when the RIi flag changes from “0” to “1”. The bit 4 (OER i flag) of the UARTi transmission control register 1 is set when the next data is transferred from the receive register to the receive buffer register while the RI i flag is “1”. In other words when an overrun error occurs. If the OERi flag is “1”, it indicates that the next data has been transferred to the receive buffer register before the contents of the receive butter register has been read. Bit 5 (FER i flag) is set when the number of stop bits is less than required (framing error). Bit 6 (PER i flag) is set when a parity error occurs. Bit 7 (SUMi flag) is set when either the OERi flag, FERi flag, or the PER i flag is set. Therefore, the SUMi flag can be used to determine whether there is an error. The setting of the RI i flag, OERi flag, FERi flag, and the PERi flag is performed while transferring the contents of the receive register to the receive buffer register. The RI i, FERi, and PERi flags are cleared when reading the low-order byte of the receive buffer register or when writing “0” to the RE i flag or when setting to be a parallel port. The OER i and SUMi flags are cleared when writing “0” to the REi flag or when the setting to be a parallel port. Sleep mode The sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected through serial I/O. The sleep mode is entered when bit 7 of the UART i transmit/receive mode register is set. UART2 does not have the sleep mode. The operation of the sleep mode for an 8-bit asynchronous communication is described below. When sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asychronous communication) of the received data is “0”. Also the RI i, OERi, FERi, PER i, and the SUMi flag are unchanged. Therefore, the interrupt request bit of the UARTi receive interrupt control register is also unchanged. Normal receive operation takes place when bit 7 of the received data is “1”. The following is an example of how the sleep mode can be used. The main microcomputer first sends data with bit 7 set to “1” and bits 0 to 6 set to the address of the subordinate microcomputer which wants to communicate with. Then all subordinate microcomputers receive the same data. Each subordinate microcomputer checks the received data, clears the sleep function selection bit if bits 0 to 6 are its own address and sets the sleep bit if not. Next the main microcomputer sends data with bit 7 cleared. Then the microcomputer with the sleep bit cleared will receive the data, but the microcomputer with the sleep bit set will not. In this way, the main microcomputer is able to communicate only with the designated microcomputer. Fig. 48 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected fi or fEXT D 0 RE i R xD i Receive Clock RIi RTS i Start bit D 1 Stop bit D 7 Start bit Starting at the falling edge of start bit Check to be “L” level Get data

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. A-D CONVERTER The A-D converter is an 10-bit successive approximation converter. Figure 49 shows a block diagram of the A-D converter and Figure 50 shows the configuration of the A-D control register 0 (address 1E 16) and A-D control register 1 (address 1F16). The frequency of the A-D converter operating clock φ AD is selected by bit 7 of the A-D control register 0. When bit 7 is “0”, φ AD is the clock frequency divided by 4. That is, φ AD = f2/4. When bit 7 is “1”, φ AD is the clock frequency divided by 2 and φ AD = f2/2. The φ AD during A-D conversion must be 250 kHz or more because the comparator uses a capacity coupling amplifier. Bit 3 of A-D control register 1 is used to select whether to use the conversion result as 10 bits or as 8 bits. The conversion result is used as 10 bits when bit 3 is “1” and as 8 bits when bit 3 is “0”. When the conversion result is used as 10 bits, the low-order 8 bits of the conversion result is stored in the even address of the corresponding A-D register and the high-order two bits are stored in bits 0 and 1 of the odd address of the corresponding A-D register. Bits 2 to 7 of the A-D register odd address return “000000 2” when read. When the conversion result is used as 8 bits, the high-order 8 bits of the 10-bit A-D conversion are stored in even address of the corresponding A-D register. In this case, the A-D register odd address returns “00 16” when read. The operating mode is selected by bits 3 and 4 of A-D control register 0. The available operating modes are one-shot, repeat, single sweep, repeat sweep. Whether to connect the reference voltage input pin (V REF ) with the ladder network or not depends on bit 5 of the A-D control register 1. The V REF pin is connected when bit 5 is “0” and is disconnected when bit 5 is “1” (High impedance state). When A-D conversion is not performed, current from the V REF pin to the ladder network can be cut off by disconnecting ladder network from the VREF pin. Before starting A-D conversion, wait for 1 µs or more after clearing bit 5 to “0”. The bit of the port direction register corresponding to the analog input pin to be used must be “0” (input mode) because the analog input pin is also used as port P7. Note that when using the sub-clock (X CIN - XCOUT ) or UART2, the analog pins shared with those functions cannot be used. The operation of each mode is described below. The interrupt vector and the interrupt control register are common to the A-D conversion interrupt and UART2 transmit/receive interrupt. It is switched by a selection of UART2 function as shown in Figure 37’s note. Fig. 49 A-D converter block diagram Data bus (odd) Data bus (even) Selector AN 0 AN 1 AN 2 AN 3 AN 4 AN 5/ADTRG AN 6 AN 7 Ladder network Vref Successive approximation register Address Address 1/2 f2 1/2 A-D register 0 (2116) A-D register 1 (2316) A-D register 2 (2516) A-D register 3 (2716) A-D register 4 (2916) A-D register 5 (2B16) A-D register 6 (2D16) A-D register 7 (2F16) A-D register 0 (2016) A-D register 1 (2216) A-D register 2 (2416) A-D register 3 (2616) A-D register 4 (2816) A-D register 5 (2A16) A-D register 6 (2C16) A-D register 7 (2E16) Decoder Comparator A-D control register 1 (1F16) A-D control register 0 (1E16) VREF AV SS VREF connect selection φ AD selection φ AD

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (1) One-shot mode One-shot mode is selected when bits 3 and 4 of A-D control register 0 are “0”. The analog input pin (AN0 – AN7) is selected with bits 0 to 2 of A-D control register 0. A-D conversion can be started by a software trigger or by an external trigger. A software trigger is selected when bit 5 of A-D control register 0 is “0” and an external trigger is selected when it is “1”. When a software trigger is selected, A-D conversion is started when bit 6 (A-D conversion start flag) is set to “1”. A-D conversion ends after 59 φ AD cycles and an interrupt request bit of the A-D conversion interrupt control register is set to “1”. At the same time, the A-D conversion start flag (bit 6 of the A-D control register 0) is cleared and A-D conversion stops. The result of A-D conversion is stored in the A-D register corresponding to the selected pin. If an external trigger is selected, A-D conversion starts when the A-D conversion start flag is “1” and the AD TRG input changes from “H” to “L”. In this case, the pins that can be used for A-D conversion are AN 0 to AN4, AN6 and AN7 (a total of 7) because the AD TRG pin is also used as the analog voltage input pin (AN5). The operation is the same as with software trigger except that the A-D conversion start flag is not cleared after A-D conversion and a retrigger can be available during A-D conversion. (2) Repeat mode Repeat mode is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “0”. The operation of this mode is the same as the operation of one-shot mode except that when A-D conversion of the selected pin is complete and the result is stored in the A-D register, conversion does not stop, but is repeated. No interrupt request is issued in this mode. Furthermore, if software trigger is selected, the A-D conversion start flag is not cleared. The contents of the A-D register can be read at any time. Fig. 50 A-D control register bit configuration 765432 0 1 Address 1F16A-D control register 1 A-D sweep pin selection bits 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 – AN3 (4 pins) 1 0 : AN0 – AN5 (6 pins) 1 1 : AN0 – AN7 (8 pins) 0 : Always “0” VREF connection selection bit 0 : VREF is connected 1 : VREF is not connected Analog input selection bits 0 0 0 : Select AN 0 0 1 : Select AN1 0 1 0 : Select AN2 0 1 1 : Select AN3 1 0 0 : Select AN4 1 0 1 : Select AN5 1 1 0 : Select AN6 1 1 1 : Select AN7 A-D operation mode selection bits 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 765432 0 1 A-D control register 0 Trigger selection bit 0 : Software trigger 1 : AD TRG input trigger A-D conversion start flag 0 : Stop A-D conversion 1 : Start A-D conversion A-D conversion frequency ( φ AD ) selection flag 0 : Select f2/4 1 : Select f2/2 1E16 Address 8/10-bit mode selection bit 0 : 8-bit mode 1 : 10-bit mode

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Single sweep mode Single sweep mode is selected when bit 3 of A-D control register 0 is “0” and bit 4 is “1”. In the single sweep mode, the number of analog input pins to be swept can be selected. Analog input pins are selected by bits 1 and 0 of the A-D control register 1 (address 1F 16). Two pins, four pins, six pins or eight pins can be selected as analog input pins, depending on the contents of these bits. A-D conversion is performed only for selected input pins. After A-D conversion is performed for input of AN 0 pin, the conversion result is stored in A-D register 0, and in the same way, A-D conversion is performed for selected pins one after another. After A-D conversion is performed for all selected pins, the sweep is stopped. A-D conversion can be started with a software trigger or with an external trigger input. A software trigger is selected when bit 5 is “0” and an external trigger is selected when it is “1”. When a software trigger is selected, A-D conversion is started when A-D control register 0 bit 6 (A-D conversion start flag) is set to “1”. When A-D conversion of all selected pins ends, an interrupt request bit of the A-D conversion interrupt control register is set to “1”. At the same time, A-D conversion start flag is cleared and A-D conversion stops. If an external trigger is selected, A-D conversion starts when the A-D conversion start flag is “1” and the AD TRG input changes from “H” to “L”. In this case, the A-D conversion result which is stored in the A-D register 5 becomes invalid because the AD TRG pin is also used as the AN 5 pin. The operation by external trigger is the same as that done by software trigger except that the A-D conversion start flag is not cleared after A-D conversion and a retrigger can be available during A-D conversion. (4) Repeat sweep mode Repeat sweep mode 0 is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “1”. The difference from the single sweep mode is that A-D conversion does not stop after converting from the AN 0 pin to the selected pins, but repeats again from the AN0 pin. The repeat is performed among the selected pins. Also, no interrupt request is generated. Furthermore, if software trigger is selected, the A-D conversion start flag is not cleared. The A-D register can be read at any time.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. WATCHDOG TIMER The watchdog timer is used to detect unexpected execution sequence caused by software runaway. Figure 51 shows a block diagram of the watchdog timer. The watchdog timer includes a 12-bit binary counter. The watchdog timer counts divided clock f 32 or f512. Whether to count f32 or f512 is determined by the watchdog timer frequency selection flag shown in Figure 52. For divided clocks f32 and f512, refer to the section on clock generating circuit. f512 is selected when the flag is “0” and f32 is selected when it is “1”. The flag is cleared after reset. “FFF16” is set in the watchdog timer when “L” or 2 Vcc is applied to the RESET pin, STP instruction is executed, data is written to the watchdog timer register, or the most significant bit of the watchdog timer becomes “0”. After “FFF 16” is set in the watchdog timer, the contents of the watchdog timer is decremented by one at every cycle of f32 or f512. After 2048 counts, the most significant bit of the watchdog timer becomes “0”, and a watchdog timer interrupt request bit is set, and “FFF16” is set in the watchdog timer. Normally, a program is written so that data is written in the watchdog timer register before the most significant bit of the watchdog timer becomes “0”. If this routine is not executed due to unexpected program runaway, the most significant bit of the watchdog timer becomes eventually “0” and an interrupt is generated. The processor can be reset by setting “1” to the software reset bit (bit 3 of the processor mode register 0) described in Figure 10 on the interrupt section and generating a reset pulse. The watchdog timer stops its function when the RESET pin voltage is raised to double the Vcc voltage. The watchdog timer can also be used to recover from when the clock is stopped by the STP instruction. Refer to the section on stand-by function for more details. The watchdog timer hold the contents during a hold state and the input of the divided clock is stopped. Fig. 51 Watchdog timer block diagram Fig. 52 Watchdog timer frequency selection flag Watchdog timer frequency selection flag 0 : Select f512 1 : Select f32 6116 Addresses6 5 4 3 2 1 0 Select with the watchdog timer frequency selection flag. (If STP instruction is executed, f32 is forced to be selected when the system clock selection bit is “0”, or f8 is forced to be selected when the system clock selection bit is “1”.) Set “FFF16” Write to watchdog timer register 2 • Vcc detection circuit SQ R RESET STP instruction f512 f32 Watchog timer Hold (Address 6016) Note. When the main clock external input selection bit is “1” and the main clock or the main clock divided by 8 is selected as a system clock, or the sub-clock external input selection bit is “1” and the sub-clock is selected; the divided clock f 16 is input. (Note)

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER RESET CIRCUIT The microcomputer is released from the reset state when the RESET pin is returned to “H” level after holding it at “L” level with the power source voltage at 5 V ± 10%. Program execution starts at the address formed by setting address A23 – A16 to 0016, A15 – A8 to the contents of address FFFF16, and A7 – A0 to the contents of address FFFE16. Figure 53 shows the status of the internal registers during reset. Fig. 53 Microcomputer internal status during reset Address 0016 0000 0016 0016 0016 0016 0016 0016 00 00 0 0 ?? ? 0016 0016 0000 00 00 00 00 00 00 1000 0010 000 0 0 0016 0016 0016 0016 0016 0016 0001 00 0 0 001 001 00 0 0 00 0 0 0016 (0416)••• (0516)••• (0816)••• (0916)••• (0C16)••• (0D16)••• (1016)••• (1116)••• (1416)••• (1E16)••• (1F16)••• (3016)••• (3816)••• (3416)••• (3C16)••• (3516)••• (3D16)••• (4016)••• (4216)••• (4416)••• (5616)••• (5716)••• (5816)••• (5916)••• (5A16)••• (5B16)••• (5C16)••• (5D16)••• (5E16)••• (5F16)••• Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register A-D control register 0 A-D control register 1 UART 0 Transmit/Receive mode register UART 1 transmit/receive control register 1 UART 1 Transmit/Receive mode register UART 0 transmit/receive control register 0 UART 1 transmit/receive control register 0 UART 0 transmit/receive control register 1 Count start flag One- shot start flag Up-down flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Address (6016)••• (7F16)••• (6C16)••• (6D16)••• (6E16)••• (6F16)••• (7016)••• (7116)••• (7216)••• (7316)••• (7416)••• (7516)••• (7616)••• (7716)••• (7816)••• (7916)••• (7A16)••• (7B16)••• (7C16)••• (7D16)••• (7E16)••• Watchdog timer register Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART2 trans./rece. interrupt control register UART 0 transmission interrupt control register UART 0 receive interrupt control register UART 1 transmission interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer B2 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Processor status register (PS) Program bank register (PG) Program counter (PC H ) Program counter (PCL) Direct page register (DPR) Data bank register (DT) INT0 interrupt control register Contents of other registers and RAM are undefined during reset. Initialize them by software. ?0 0 0 0000 001 00 0 00 0 00 0 00 0 1? ? 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0016 0016 Content of FFFF16 Content of FFFE16 000016 FFF 16 INT1 interrupt control register INT2/Key input interrupt control register 0016 0 01000 (6116)••• (6316)••• (6416)••• (6816)••• Watchdog timer frequency selection flag Memory allocation control UART2 transmit/receive mode register UART2 transmit/receive control register 0 0 0 001000 000 0 (6916)••• UART2 transmit/receive control register 1 00 0 0 000 0001 00 1 0 000 0 0016

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. INPUT / OUTPUT PINS Ports P0 to P8 all have a port direction register and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of the port direction register is set to “1” and an input pin when the bit is cleared to “0”. When a pin is programmed for output, the data is written to the port latch and is output, and the contents of the port latch is read instead of the value of the pin. Therefore, a previously output value can be read correctly even when the output “L” voltage is raised by directly driving an LED or others. A pin programmed for input is floating and the value input to the pin can be read. When a pin is programmed for input, the data is written only in the port latch and the pin retains floating. Ports P5 4 to P57, and P62 – P64, however, have pull-up transistors and the port’s pull-up function can be selected by setting “1” to bits 6, 5, 3 of the port function control register (reffer to Figure 11.) A port which corresponds to a port direction register’s bit set to “0” is pulled up. A port which corresponds to a bit set to “1” is an output pin and it is not pulled up. Figures 55 and 56 show the block diagram of ports P0 to P8 and the E pin output format. In the memory expansion mode and the microprocessor mode, ports P0 to P4 are also used as address, data, and control signal pins. Refer to the section on the processor modes for more details. Figure 54 shows an example of a reset circuit. If the stabilized clock is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.9 V or less when the power source voltage reaches 4.5 V. If a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from “L” to “H” after the main-clock oscillation is fully stabilized. VCCRESET RESET VCC 4.5V 0.9V Power on Note. In this case, stabilized clock is input from the external to the main-clock oscillation circuit. Perform careful evaluation at the system design level before using. Fig. 54 Example of a reset circuit

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 55 Block diagram for ports P0 to P8 and the E pin output format (1) Data bus Data bus

• Ports P00 – P07, P10 – P17, P20 – P27, P30 – P33, P43 – P46 (Inside dotted-line not included) Ports P40, P41, P47, P51, P53, P61, P65 – P67, P86 (Inside dotted-line included) Data bus Port direction register Port latch Valid only when pins are used as TxD j pins for serial I/O communication Only P75 as analog input/LiteDiagLines /LiteDiagLines /LiteDiagLines
• Ports P83, P87 (Inside dotted-line not included. Shaded area included.) Ports P50, P52, P60, P75, P82 (Inside dotted-line included. Shaded area not included.) Port P42 (Inside dotted-line not included. Shaded area not included.) Data bus “1” Output N-channel open-drain selection (Note 1) Port latch Port direction register
• Ports P55, P57, P62 – P64 Pull-up selection Port latch Port direction register
• Ports P54, P56 /LiteDiagLines /LiteDiagLines /LiteDiagLines Output Pull-up selection Port latch Port direction register Pull-up transistor Pull-up transistor “1” /LiteDiagLines/LiteDiagLines/LiteDiagLines 2. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Notes 1. Analog input (Note 2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 56 Block diagram for ports P0 to P8 and the E pin output format (2) Data bus

• E/RDE
• Ports P55, P73, P80, P81, P84 Data bus “1” Output “0” Port direction register Port latch
• Ports P70, P71, P76, P77 (Inside dotted-line not included.) Ports P72, P74 (Inside dotted-line included.) Port latch Port direction register Analog input Sub-clock oscillation circuit (Note 1) Analog input Note 2. Only P73 as analog input (Note 2) Note 1. Only P76, P77 as sub-clock oscillation circuit Hold acknowledge

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PROCESSOR MODE The bits 0 and 1 of processor mode register 0 shown in Figure 57 are used to select any mode of the single-chip mode, the memory expansion mode, and the microprocessor mode. Ports P0 to P3 and a part of port P4 are used as I/O pins of address, data, and control signals except in the single-chip mode. Figure 58 shows the functions of ports P4 to P0 in each mode. The external memory area changes when the mode changes. Figure 59 shows the memory map for each mode. Refer to Figure 1 for the addresses of RAM and ROM. The external memory area can be accessed except in the single-chip mode. The accessing of the external memory is affected by the BYTE pin, the wait bit (bit 2 of the processor mode register 0), and the wait selection bit (bit 0 of the processor mode register 1) .These will be described next.

• BYTE pin When accessing the external memory, the level of the BYTE pin is used to determine whether to use the data bus as 8-bit width or 16- bit width. The data bus has a width of 8 bits when level of the BYTE pin is “H”, and port P2 becomes the data I/O pin. The data bus has a width of 16 bits when the level of the BYTE pin is “L”, and ports P1 and P2 become the data I/O pins. When accessing the internal memory, the data bus always has a width of 16 bits regardless of the BYTE pin level. Fig. 57 Processor mode register bit configuration Clock f 1 output selection bit 0 : No f 1 output 1 : f 1 output Processor mode bit 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select Wait bit 0 : Wait 1 : No Wait Software reset bit Reset occurs when this bit is set to “1” Interrupt priority detection time selection bit 0 0 : Internal clock f 5 7 (cycle) 0 1 : Internal clock f 5 4 (cycle) 1 0 : Internal clock f 5 2 (cycle) Test mode bit This bit must be "0" 765432 0 1

0 Processor mode register 0

16Processor mode register 1 Wait selection bit 0 : Wait 0 1 : Wait 1 765432 0 1

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. _ ___ Fig. 58 Relationship between ports P0 to P4, pin E /RDE and processor modes Notes 1. In the memory expansion mode and the microprocessor mode, signal E is not output. The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the E signal output in the single-chip ___ mode and the 1 output in the microprocessor mode. In the memory expansion mode or the microprocessor mode, signals RDE , WEL , WEH can also be fixed to “H” when the internal memory area is accessed. ALE HLDA I/O Port I/O Port I/O Port I/O Port Address Data(odd) Address A8 – A15 Address Data(even) Address Data (odd,even) I/O Port PM 1 PM 0 Mode Single-chip mode Memory expansion mode Microprocessor mode (Note 1) (Note 2) Port E/RDE Port P0 Port P1 Port P2 BYTE = “L” BYTE = “H” BYTE = “L” BYTE = “H” Port P3 Port P4 E P00 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P42 (Note 2) (Note 1)

1 P42 1

Address A17, A16P06 P07 P10 to P17 P10 to P17 P20 to P27 P20 to P27 P30 P31 P32 P33 P40 P41 P42 to P47

• In this case, bit 7 of the processor mode register 0 is “0”
• In this case, bit 7 of the processor mode register 0 is “0” Same as above except for P42
• In this case, bit 7 of the processor mode register 0 is “1” Same as above except for P4
• In this case, bit 7 of the processor mode register 0 is “1” Same as left Same as left Same as left Same as left Same as left Same as left Same as left Same as left except for port P42 which outputs 1 independent of the bit 7 of the processor mode register 0 (Note 2) RSMP (Note 2) WEH WEL HOLD I/O Port P05 CS 0 – CS4 P00 to P04 A8 to A15 E E E E E E E E E E E E E RDY

Y Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 60 Relationship between wait bit, wait selection bit, and access time

• Wait bit As shown in Figure 60, when the external memory area is accessed with the wait bit (bit 2 of the processor mode register 0 at address 16) cleared to “0”, the access time can be extended compared with no wait (the wait bit is “1”). The access time is extended in two ways and this is selected with the wait selection bit (bit 0 of the processor mode register 1 at address 16). When this bit is “1”, the access time is 1.5 times compared to that for no wait. When this bit is “0”, the access time is twice compared to that for no wait. At reset, the wait bit and the wait selection bit are “0”. The accessing of internal memory area is always performed in the no wait mode regardless of the wait bit. The processor modes are described below. Fig. 59 External memory area for each processor mode (1) Single-chip mode [00] Single-chip mode is entered by connecting the CNVss pin to Vss and starting from reset. Ports P0 to P4 all function as normal I/O ports. Port P4 2 can output clock φ 1 by setting bit 7 of the processor mode register 0 to “1”. For clock φ 1, refer to Figure 65. In this mode, signal E is output from pin E/RDE . Signal E output, however, can be stopped by setting the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) to “1” to switch the E/RDE pin function to “L” output. Table 7 shows the function of the signal output disable selection bit. (2) Memory expansion mode [01] Memory expansion mode is entered by setting the processor mode bits to “01” after connecting the CNVss pin to Vss and starting from reset. Pin E/RDE becomes the output pin for RDE . RDE is a read-enable signal and is “L” during the data read term in the read cycle. When the internal memory area is read, RDE can be fixed to “H” by setting the signal output disabe selection bit (bit 6 of the oscillation circuit control register) to “1”. Ports P0 6 and P07 become the output pins for addresses A16 and A17, respectively. Similarly, port P05 becomes the output pin for RSMP , and ports P00 to P04 become the output pins for CS 0 to CS 4, respectively. In this case, their functions as I/O ports are lost. Wait bit “0” (Wait 0) Wait bit “0” (Wait 1) Wait bit “1” (No wait) Internal clock Port P2 RDE or WEL , WEH ALE Port P2 RDE or WEL , WEH ALE Access time Access time Address Data Address Data Address Data Address Data Port P2 RDE or WEL , WEH ALE Access time Address Data Address SFR RAM Microprocessor mode The shaded area is the external memory area. Note that banks 10 16 to FF16 cannot be accessed. SFR 0016 8016 FFFFFF 16 RAM ROM Memory expansion mode FFF 16 1FFFF 16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. CS 0 to CS 4 are the chip select signals and are “L” when the address shown in Table 7 is accessed. RSMP is the ready-sampling signal which is output for the RDY input described later when the external memory area is accessed. By inputting logical AND of RSMP and CS n (n = 0 to 4) to the RDY pin, read/write term for any address areas can be extended by 1 cycle of clock φ 1. In addition, the read/write term can also be extended by 2 cycles of clock φ 1 if the above function and wait 0/1 function specified with the wait bit are used together. Port P1 has two functions depending on the level of the BYTE pin. In bose cases, the I/O port function is lost. When the BYTE pin level is “L”, port P1 functions as an address (A to A8) output pin while RDE or WEL , WEH are “H” and as an odd address data I/O pin while these signals are “L”. However, if an internal memory is read, external data is ignored while RDE is “L”. When the BYTE pin level is “H”, port P1 functions as an address output pin. Port P2 has two functions depending on the level of the BYTE pin. In bose cases, the I/O port function is lost. When the BYTE pin level is “L”, port P2 functions as an address (A to A7) output pin while RDE or WEL , WEH are “H” and as an even address data I/O pin while these signals are “L”. However, if an internal memory is read, external data is ignored while RDE is “L”. When the BYTE pin level is “H”, port P2 functions as an address (A0 to A7) output pin while RDE or WEL , WEH are “H” and as an even and odd address data I/O pin while these signals are “L”. However, if an internal memory is read, external data is ignored while RDE is “L”. Ports P30, P31, P32, and P33 become WEL , WEH , ALE, and HLDA output pins, respectively and lose their I/O port functions. WEL , WEH are the write-enable low signal and the write-enable high signal, respectively. These signals go “L” during the data write term of the write cycle, but their operations differ depending on the BYTE pin level. In the case the BYTE pin level is “L”, WEL is “L” when writing to an even address, WEH is “L” when writing to an odd address, and both WEL and WEH are “L” when writing to even and odd addresses. In the case the BYTE pin level is “H”, regardless of address, only WEL is “L”, and WEH retains “H”. WEL and WEH can also be fixed to “H” when the internal memory is accessed, same as RDE , by writing “1” to the signal output disable selection bit. ALE is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. The latch is transparent while ALE is “H” to let the address signal pass through and held while ALE is “L”. HLDA is a hold acknowledge signal and is used to notify externally when the microcomputer receives HOLD input and enters into hole state. Ports P4 0 and P41 become HOLD and RDY input pin, respectively, and lose their output pin function. HOLD is a hold request signal. It is an input signal used to put the microcomputer in hold state. HOLD input is accepted when the internal clock φ falls from “H” level to “L” level while the bus is not used. Ports P0, P1, P2, P30, P31, and pin E/RDE are floating while the microcomputer stays in hold state. These ports become floating after one cycle of internal clock φ later than HLDA signal changes to “L” level. At releasing hold state, these ports are released from floating state after one cycle of internal clock φ later than HLDA signal changes to “H” level. RDY is a ready signal. If this signal goes “L”, the internal clock φ stops at “L”. RDY is used when slow external memory is attached. Port P42 becomes a normal I/O port when bit 7 of the processor mode register 0 is “0” and becomes an output pin for clock φ 1 when bit 7 is “1”. The φ 1 output is independent of RDY and does not stop even when internal clock φ stops because of “L” input to the RDY pin.

Notice: This is not a final specification. Some parametric limits are subject to change. WEL , WEH internal/external memory area is accessed. external memory area is accessed.

03 FFFF16 03 FFFF16

07 FFFF16 07 FFFF16

Table 9. Relationship between CNVss pin input levels and processor

• Single-chip
• Memory expansion
• Microprocessor
• Microprocessor Vss Vcc

Table 7. Relationship between access addresses and chip-select signals CS 0 to CS 4 Table 8. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0) of bit 7 of the processor mode register 0. Note. Functions shown in Table 7 cannot be emulated in a debugger. For the oscillation circuit control register 0, refer to Figure 63. For the port function control register, refer to Figure 11.

Notice: This is not a final specification. Some parametric limits are subject to change. some of the control registers for the clock generating circuit. main or sub clock, as shown in Figure 65. clock drivability selection and the main clock division selection. The method of clocks switch is described bellow.

1. When this bit is “1”, the clock f2 is the direct main clock

main clock, which is selected as the system clock, oscillates. inputs AN7 and AN6, respectively. Table 10. Selection of system clock and clock f2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 63 Bit configuration of oscillation circuit control registers 0, 1 Fig. 64 How to write data in oscillation circuit control register 1 Writing data “8016” (LDM instruction) Reset clock prescaler Writing data “5516” (LDM instruction) Writing data “0Y16” (LDM instruction) CC 2 to CC0 selection bits

• How to reset clock prescaler • How to write in CC 2 to CC0 selection bits Note. “Y” is the sum of bits to be set. For example, when setting bits 2 and 1 to “1”, “Y” becomes “6”. Next instruction Oscillation circuit control register 0 XCOUT drivability selection bit 0 : LOW 1 : HIGH Main clock stop bit 0 : Main-clock oscillation is available. 1 : Main-clock oscillation is stopped. System clock selection bit Port-XC selection bit = “0” (Sub clock is not used.) 0 : Main clock is selected. 1 : Main clock divided by 8 is selected. Port-XC selection bit = “1” (Sub clock is used.) 0 : Main clock is selected. 1 : Sub clock is selected. Port-Xc selection bit 0 : Ports P7 7 and P76 are selected. (Sub clock is not used.) 1 : Pins XCIN and XCOUT are selected. (Sub clock is used.) System clock stop bit at wait state 0 : Clocks f 2 to f512 are operating at WIT state 1 : Clocks f2 to f512 stop at WIT state Signal output disable selection bit (Refer to Table 7.) Address Note. Write to the oscillation circuit control register 1 as the flow shown in Figure 64. CM 6 CM 5 CM 4 CM 3 CM 2 CM 0 76543210 Oscillation circuit control register 1 Main clock division selection bit 0 : Main clock is divided by 2. 1 : Main clock is not divided by 2. Main clock external input selection bit 0 : Main-clock oscillation circuit is operating by itself. Watchdog timer is used at returning from STP state. 1 : Main-clock is input externally. Watchdog timer is not used at returning from STP state. Sub clock external input selection bit 0 : Sub-clock oscillation circuit is operating by itself. Port P7 6 functions as XCOUT pin. Watchdog timer is used at returning from STP state. 1 : Sub-clock is input externally. Port P7 6 functions as I/O port. Watchdog timer is not used at returning from STP state. 0 : Always “0” 0 : Always “0” (However, writing data “55 16” shown in Figure 64 is possible.) Clock prescaler reset bit Address 6F16CC 0CC 1CC 200 76543210

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 65 Block diagram of clock generating circuit (Oscillation circuit control register 0 : Address 6C16) CM 2 : Main clock stop bit CM 3 : System clock selection bit CM 4 : Port-Xc selection bit CM 5 : System clock stop bit at wait state (Oscillation circuit control register 1:Address 6F16) CC 0 : Main clock division selection bit CC 1 : Main clock external input selection bit CC 2 : Sub clock external input selection bit (Port function control register : Address 6D16) PC 1 : Sub-clock output selection bit/Timer B2 clock source selection bit P76/XCOUT P77/XCIN P67/TB2IN/ φ SUB CM 4 PC 1 CM 4 CM 4 CC 2 XOUT XIN Main clock CM 4 System clock CC 0 CM 3 CM 3 CM 3 CM 2 CC 1 CM 4 CM 5 QS R STP instruction WIT instruction P42/ φ 1 CM 3 f512 f64 WDC 12-bit Watchdog timer Watchdog timer frequency selection flag Reset CC 1 CC 2 CM 3 CM 4 Interrupt disable flag Interrupt request STP instruction R QSS Q R 1 1 f2 f8 f16 f32 0 0 Sub clock (Port latch) PC 1 CM 4 Clock prescaler fC32 Timer B2 (clock timer) (In event counter mode) Internal clock φ

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 66 System clock state transition Main clock : Oscillating Sub clock : Stopped I/O ports P77 and P76 f2 : Main-clock side f : Main-clock side Main clock : Oscillating Sub clock : Stopped I/O ports P77 and P76 f2 : Main-clock side (Note 2) f : Stopped Main clock : Stopped Sub clock : Stopped I/O ports P77 and P76 WIT instruction Interrupt STP instruction Interrupt XC is selected (CM4 = “1”) Main clock : Oscillating Sub clock : Oscillating f2 : Main-clock side f : Main-clock side Main clock : Oscillating Sub clock : Oscillating f2 : Main-clock side (Note 2) f : Stopped Main clock : Stopped Sub clock : Stopped f2 : Stopped f : Stopped WIT instruction Interrupt STP intrunction Interrupt Sub clock is selected as system clock (Note 1) (CM3 = “1”) Main clock : Oscillating Sub clock : Oscillating f2 : Sub-clock side f : Sub-clock side Main clock : Oscillating Sub clock : Oscillating f2 : Sub-clock side (Note 2) f : Stopped Main clock : Stopped Sub clock : Stopped f2 : Stopped f : Stopped WIT instruction Interrupt STP intrunction Interrupt Main clock oscillation stops (CM 2 = “1”) Main clock : Stopped Sub clock : Oscillating f2 : Sub-clock side f : Sub-clock side Main clock :Stopped Sub clock :Oscillating f2 : Sub-clock side (Note 2) f : Stopped WIT instruction Interrupt Reset Main clock is selected as system clock (Note 1) (CM 3 = “0”) Main clock oscillation starts (CM 2 = “0”) Notes 1. Before selecting the main/sub clock of which oscillation already starts as the system clock, use software to fully stabilize the oscillation. 2. When the system clock stop bit at wait state (CM5) is “1”, f2 stops at wait state. Main clock : Stopped Sub clock : Stopped f2 : Stopped f : Stopped STP instruction Interrupt f : Stopped f2 : Stopped

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Note that the port-XC selection bit cannot be cleared by software when it is once set to “1”. The bit can be cleared only by reset. It is impossible to write “1” to the port-XC selection bit and the system clock selection bit at the same time. In addition, the contents of the main clock stop bit and the X COUT drivability selection bit cannot be changed when the port-XC selection bit is “0”. Figure 67 shows the system clock selection change example when using the sub clock. When the system clock selection bit is “1” after sub-clock oscillation starts, the sub clock is selected as the system clock. Make sure to select the sub clock after the sub-clock oscillation is fully stabilized. When the main clock stop bit is set to “1” after the sub clock is selected, the main-clock oscillation/input stops. By stopping the main-clock oscillation, current consumption can be further restricted. When the main clock stop bit is cleared to “0” after the main-clock oscillation stops, the main-clock oscillation/input restarts. When the system clock selection bit is “0” after the main-clock oscillation restarts, the main clock is selected as the system clock again. Make sure to select the main clock after the main-clock oscillation restarts and is fully stabilized. The X COUT drivability selection bit is a bit to select the drivability of the sub-clock oscillation circuit and is set to “1” (HIGH) after reset is released. Make sure to clear the X COUT drivability selection bit to “0” (LOW) after the sub-clock oscillation is fully stabilized. Port-Xc selection bit (CM4) System colck selection bit (CM3) Main clock stop bit (CM2) System clock Main-clock oscillation Sub-clock oscillation Oscillation stabilizing time Stop Operating Operating Operating Oscillation stabilizing time Main clock Sub clock Main clock Stopped Fig. 67 System clock selection change example

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. When the port-XC selection bit is set to “1” to use sub-clock oscillation and timer B2 is set to be in the event count mode, clock fC32 which is the sub clock (32 kHz) divided by 32 is selected as the count source of timer B2. By this selection, timer B2 can be used as the clock timer. For setting of timer B2 related registers, refer to the section on clock timer mode of timer B2. The clock prescaler in which the sub clock is divided by 32 is reset by writing “1”, in dummy, into bit 7 (clock prescaler reset bit) of the oscillation circuit control register 1. When the main clock is selected, by this function, clock f C32 of clock timer B2 can be synchronized with software. Figure 68 shows the operation timing for clock prescaler and clock timer B2. Figure 69 shows the clock f2 state transition when the port-Xc selection bit is “0” and the sub clock is not used. Fig. 69 Clock f2 state transition (when the sub clock is not used.) From the time during reset to the time reset is released, the main clock divided by 2 is being selected as the clock f 2. When the system clock selection bit is set “1” in that condition, the main clock divided by 16 is selected as the clock f2 and the clock frequency supplied for the CPU and internal peripheral devices is divided by 8 more. It makes current consumption restrict, although the operation speed slows. When the timer B2 clock source selection bit (bit 1 of the port function control register) is set to “1” and event counter mode is selected in timer B2 under the condition which the port-Xc selection bit is “0”; fc 32, which is the main clock divided by 32, is connected as a timer B’s count source. Accordingly, timer B2 can be used as a clock timer which always operates with a regular clock source shown in Figure 69. For details relating to register setting of timer B2, refer to the section “Clock timer” on timer B. Fig. 68 Operation timing for clock prescaler and clock timer B2 CC 0 = “0” CC 0 = “1” CM 3 = “0” CM 3 = “1” f2 = f(XIN) / 2 (Note 1) f2 = f(XIN) / 16f2 = f(XIN) / 2 (Note 1) f2 = f(XIN) (Note 2) f2 = f(XIN) / 8 CM 3 = “0” CC 0 = “0” CM 3 = “1” CC 0 = “1” Reset Notes 1. f2 = f(XIN) / 2 expresses that the clock f2 is the main clock divided by 2. 2. f2 = f(XIN) expresses that the clock f2 is the direct main clock, which is not divided. CC 0 = Main clock division selection bit CM 3 = System clock selection bit CM 4 = Port-Xc selection bit• In the case of not using sub clock (CM4 = “0”) Timer B2 count start flag Writing pulse of clock prescaler reset bit XCIN Timer B2 count value n (Set value) n – 1 XCIN × 31(cycle) X CIN × 32 (cycle) This applies when the main clock is selected as the system clock (System clock selection bit (CM3) = “0”). Note. Period of fc32 X CIN × 31 (cycle) (only in this term) Period of fc32 X CIN × 32 (cycle) (after this term) (Note) Clock source of clock timer(fc32)

Notice: This is not a final specification. Some parametric limits are subject to change. but the system clock, divided clocks, and internal clock φ are stopped. 2 to f512, including the watchdog timer, are stopped. the clock timer is not stopped. “0” immediately after the wait state is terminated. operation is not stopped during the wait state. φ is restarted immediately after the oscillation restarts by reset. stabilized before making the reset input “H”. Table 11. Relationship between standby state and each block’s operation

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. The wait/stop state is terminated by interrupt acceptance or reset. Accordingly, it is necessary to prepare the state in which any interrupt can be accepted before the WIT/STP instruction is executed. Additionally, it is necessary to set the system clock stop bit at wait state before the WIT instruction is executed. When the WIT/STP instruction is executed in a bus access cycle, the bus enters the non-access state (each signal of E, RDE , WEL and WEH is at “H”) because internal clock φ (or oscillation) is stopped after the read/write in this cycle is finished. Pins P00/CS 0 to P33/HLDA normally retain the state at which internal clock φ is stopped in the wait/stop state. However, only in the memory expansion mode and the microprocessor mode, arbitrary data which is set in the port P0 to P3 latches can be output from pins P0 0/CS 0 to P33/HLDA even at the wait/stop state when the following conditions are satisfied before the WIT/STP instruction execution.

• The standby state selection bit (bit 0 of the port function control register) is set to “1”.
• “FF 16” is set into the port P0 to P3 direction registers. Furthermore, when the standby state selection bit is set to “1” and bit 6 of the oscillation circuit control register 0 (signal output disable selection bit) is set to “1”, “L” level can be output from the E/RDE pin at the wait/stop state. For the signal output disable selection bit, refer to Table 8 on the processor mode section. Note that the function of arbitrary data output cannot be emulated using a debugger.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Table 12 Relationship between memory allocation selection bits and addresses corresponding to chip-select signals CS 0 and CS 1 ROM AREA MODIFICATION FUNCTION The internal ROM size and RAM size of the M37735MHBXXXFP can be modified by the memory allocation control register’s bits 0,1 and 2 shown in Figure 70. Figure 72 shows the memory allocation in which the internal ROM size and RAM size are modified. Make sure to write data in the memory allocation control register as the flow shown in Figure 71. This ROM area modification function is valid in memory expansion mode and single-chip mode. Table 12 shows the relationship between the memory allocation selection bits and addresses corresponding to chip-select signals CS 0 and CS 1. When ordering a mask ROM, Mitsubishi Electric corp. produces the mask ROM using the data within 128 Kbytes (addresses 000000 16 – 01FFFF 16). It is regardless of the selected ROM size (refer to MASK ROM ORDER CONFIRMATION FORM.) Therefore, program “FF16” to the addresses out of the selected ROM area in the EPROM which you tender when ordering a mask ROM. Address 01FFFF 16 of this microcomputer corresponds to the lowest address of the EPROM which you tender. 76543210

00 M L 2 ML 1 ML 0 Memory allocation control register

Memory allocation selection bits ROM size RAM size 0 0 0 : 124 Kbytes 3968 bytes 0 0 1 : 120 Kbytes 3968 bytes 0 1 0 : 60 Kbytes 2048 bytes 1 0 0 : 32 Kbytes 2048 bytes 1 0 1 : 16 Kbytes 2048 bytes 1 1 0 : 96 Kbytes 3968 bytes 0 0 : Always “00” (However, writing data “55 16” shown in Figure 71 is possible.) Address 6316 Note. Write to the memory allocation control register as the flow shown in Figure 71. Fig. 70 Bit configuration of memory allocation control register Memory allocation selection bitsInternal ROM area Access addresses CS 0 CS 1ML 2 ML 1 ML 0 001000 16 – 01FFFF16 00200016 – 01FFFF16 00100016 – 00FFFF16 00800016 – 00FFFF16 00C000 16 – 00FFFF16 00800016 – 01FFFF16 00100016 – 001FFF16 00088016 – 000FFF16 00088016 – 007FFF16 00088016 – 007FFF16 00100016 – 007FFF16 02000016 – 03FFFF16 02000016 – 03FFFF16 01000016 – 03FFFF16 01000016 – 03FFFF16 00800016 – 00BFFF16 01000016 – 03FFFF16 02000016 – 03FFFF16 Writing data “5516” (LDM instruction) Writing data “0Y16” (LDM instruction) ML 2, ML1, ML0 selection bits Next instruction

• How to write in memory allocation control register Note. “Y” is the sum of bits to be set. For example, when setting bit 1 to “1”, “Y” becomes “2”. Fig. 71 How to write data in memory allocation control register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Internal RAM 3968 bytes Internal RAM 3968 bytes Internal RAM 2048 bytes SFR SFR SFR (4 Kbytes) (1.9 Kbytes) Internal ROM

120 Kbytes

60 Kbytes

FFFFFF 16 FFFFFF 16 FFFFFF 16 00FFFF 16 01000016 00FFFF 16 01000016 00FFFF 16 : External memory area Internal RAM 2048 bytes Internal RAM 2048 bytes Internal RAM 3968 bytes SFR SFR SFR (45.9 Kbytes) (28 Kbytes) Internal ROM

16 Kbytes

32 Kbytes

96 Kbytes

FFFFFF 16 FFFFFF 16 FFFFFF 16 00FFFF 16 01000016 00FFFF 16 01000016 00FFFF 16 (29.9 Kbytes) 01FFFF 16 Note. Banks 1016–FF16 cannot be accessed in the 7735 group. Fig. 72 Memory allocation (modification of internal ROM and RAM area by memory allocation selection bits)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. ADDRESSING MODES The M37735MHBXXXFP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37735MHBXXXFP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders. (1) M37735MHBXXXFP mask ROM order confirmation form (2) 80P6N mark specification form (3) ROM data (EPROM 3 sets)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Symbol Parameter Conditions Ratings Unit Vcc Power source voltage –0.3 to +7 V AVcc Analog power source voltage –0.3 to +7 V VI Input voltage RESET , CNVss, BYTE –0.3 to +12 V Input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, VREF , XIN Output voltageP00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87,_ XOUT , E Pd Power dissipation Ta = 25 °C3 0 0 m W Topr Operating temperature –20 to +85 °C Tstg Storage temperature –40 to +150 °C VI VO Limits Min. Typ. Max. f(XIN) : Operating 4.5 5.0 5.5 f(XIN) : Stopped, f(XCIN) = 32.768 kHz 2.7 5.5 AVcc Analog power source voltage Vcc V Vss Power source voltage 0V AVss Analog power source voltage 0 V High-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____ P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) High-level input voltage P10 – P17, P20 – P27 (in single-chip mode) High-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____ P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode) Low-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P44 – P47, P50 – P53 Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 IOL(avg) Low-level average output current P44 – P47, P50 – P53 15 mA f(XIN) Main-clock oscillation frequency (Note 4) 25 MHz f(XCIN) Sub-clock oscillation frequency 32.768 50 kHz ABSOLUTE MAXIMUM RATINGS –0.3 to Vcc + 0.3 V –0.3 to Vcc + 0.3 V UnitSymbol Parameter RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted) VVcc Power source voltage Notes 1.Average output current is the average value of a 100 ms interval. 2.The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3.Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”. 4.The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1”.

0.8 Vcc

0.5 Vcc

0.2Vcc 0.2Vcc 0.16Vcc –10 V V V V V V mA mA mA mA mA V IH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Typ. Max. High-level output voltage P00 – P07, P10 – P17, P20 – P27, VOH P33, P40 – P47, P50 – P57,I OH = –10 mA 3 V P60 – P67, P70 – P77, P80 – P87 High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 IOH = –10 mA 3.1 ICH = –400 mA 4.8 IOH = –10 mA 3.4 IOH = –400 mA 4.8 Low-level output voltage P00 – P07, P10 – P17, P20 – P27, VOL P33, P40 – P43, P54 – P57,I OL = 10 mA 2 V P60 – P67, P70 – P75, P80 – P87 VOL Low-level output voltage P44 – P47, P50 – P53 IOL = 20 mA 2 V Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 IOL = 10 mA 1.9 IOL = 2 mA 0.43 IOL = 10 mA 1.6 IOL = 2 mA 0.4 HysteresisHOLD , RDY , TA0IN – TA4IN, TB0IN – TB2IN, VT+ – VT– INT0 – INT2, AD TRG , CTS 0, CTS 1, CTS 2, CLK0, 0.4 1 V CLK 1, CLK 2, KI0 – KI3 VT+ – VT– Hysteresis RESET 0.2 0.5 V VT+ – VT– Hysteresis XIN 0.1 0.4 V VT+ – VT– Hysteresis XCIN (When external clock is input) 0.1 0.4 V High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE Low-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P53, P60, P61, P65 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor VRAM RAM hold voltage When clock is stopped. 2V VOH High-level output voltageE Unit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) V V VOL Low-level output voltage E VOL Low-level output voltage P30 – P32 VOH High-level output voltage P30 – P32 Symbol Parameter Test conditions VOH VOL IIH IIL VI = 0 V VI = 5 V IOH = –400 mA 4.7 –1.0 –0.5–0.25 V 0.45 V V V mA mA mA mA IOL = 2 mA IIL Low-level input current P54 – P57, P62 – P64

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. VCC = 5 V, f(XIN) = 25 MHz (square waveform), f(f2) = 12.5 MHz, f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 5 V, f(XIN) = 25 MHz (square waveform), f(XCIN) = Stopped, in operating (Note 1) VCC = 5V, f(XIN) = 25 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) V CC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) VCC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Max. Limits Typ. UnitMin. Test conditions Symbol Parameter 9.5 1.3 2.6 100 mA mA mA mA mA mA mA Power source currentICC In single-chip mode, output pins are open, and other pins are V SS . Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. 2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”. Limits Min. Typ. Max. — Resolution V REF = VCC 10 Bits — Absolute accuracy V REF = VCC ± 3 LSB RLADDER Ladder resistance V REF = VCC 10 25 k Ω tCONV Conversion time 9.44 ms VREF Reference voltage 2 V CC V VIA Analog input voltage 0 V REF V Symbol Parameter Test conditions Unit A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tc External clock input cycle time (Note 3) 40 ns tw(H) External clock input high-level pulse width (Note 4) 15 ns tw(L) External clock input low-level pulse width (Note 4) 15 ns tr External clock rise time 8n s tf External clock fall time 8n s TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note)) Notes 1.This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input UnitSymbol Parameter Limits Min. Max. tsu(P0D–E) Port P0 input setup time 60 ns tsu(P1D–E) Port P1 input setup time 60 ns tsu(P2D-E) Port P2 input setup time 60 ns tsu(P3D–E) Port P3 input setup time 60 ns tsu(P4D–E) Port P4 input setup time 60 ns tsu(P5D–E) Port P5 input setup time 60 ns tsu(P6D–E) Port P6 input setup time 60 ns tsu(P7D–E) Port P7 input setup time 60 ns tsu(P8D–E) Port P8 input setup time 60 ns th(E–P0D) Port P0 input hold time 0n s th(E–P1D) Port P1 input hold time 0n s th(E–P2D) Port P2 input hold time 0n s th(E–P3D) Port P3 input hold time 0n s th(E–P4D) Port P4 input hold time 0n s th(E–P5D) Port P5 input hold time 0n s th(E–P6D) Port P6 input hold time 0n s th(E–P7D) Port P7 input hold time 0n s th(E–P8D) Port P8 input hold time 0n s UnitSymbol Parameter Single-chip mode Limits Min. Max. tsu(D–RDE) Data input setup time 32 ns tsu(RDY– φ 1) RDY input setup time 55 ns tsu(HOLD– φ 1) HOLD input setup time 55 ns th(RDE–D) Data input hold time 0n s th( φ 1–RDY) RDY input hold time 0n s th( φ 1–HOLD) HOLD input hold time 0n s UnitSymbol Parameter Memory expansion mode and microprocessor mode Notes 3. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns. 4. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tc(TA) TAiIN input cycle time 80 ns tw(TAH) TAiIN input high-level pulse width 40 ns tw(TAL) TAiIN input low-level pulse width 40 ns UnitSymbol parameter Timer A input (Count input in event counter mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 320 ns tw(TAH) TAiIN input high-level pulse width (Note) 160 ns tw(TAL) TAiIN input low-level pulse width (Note) 160 ns UnitSymbol parameter Timer A input (Gating input in timer mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 320 ns tw(TAH) TAiIN input high-level pulse width 80 ns tw(TAL) TAiIN input low-level pulse width 80 ns UnitSymbol parameter Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max. tw(TAH) TAiIN input high-level pulse width 80 ns tw(TAL) TAiIN input low-level pulse width 80 ns UnitSymbol parameter Timer A input (External trigger input in pulse width modulation mode) Limits Min. Max. tc(UP) TAiOUT input cycle time 2000 ns tw(UPH) TAiOUT input high-level pulse width 1000 ns tw(UPL) TAiOUT input low-level pulse width 1000 ns tsu(UP–TIN) TAiOUT input setup time 400 ns th(TIN–UP) TAiOUT input hold time 400 ns UnitSymbol parameter Timer A input (Up-down input in event counter mode) UnitSymbol parameter Timer A input (Two-phase pulse input in event counter mode) Limits Min. Max. tc(TA) TAj input cycle time 800 ns tsu(TAjIN–TAjOUT ) TAjIN input setup time 200 ns tsu(TAjOUT –TAjIN) TAjOUT input setup time 200 ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tw(INH) INTi input high-level pulse width 250 ns tw(INL) INTi input low-level pulse width 250 ns tw(KIL) KIi input low-level pulse width 250 ns Limits Min. Max. tc(CK) CLK i input cycle time 200 ns tw(CKH) CLK i input high-level pulse width 100 ns tw(CKL) CLK i input low-level pulse width 100 ns td(C–Q) TXD i output delay time 80 ns th(C–Q) TXD i hold time 0n s tsu(D–C) RXD i input setup time 30 ns th(C–D) RXD i input hold time 90 ns Limits Min. Max. tc(TB) TBiIN input cycle time (one edge count) 80 ns tw(TBH) TBiIN input high-level pulse width (one edge count) 40 ns tw(TBL) TBiIN input low-level pulse width (one edge count) 40 ns tc(TB) TBiIN input cycle time (both edges count) 160 ns tw(TBH) TBiIN input high-level pulse width (both edges count) 80 ns tw(TBL) TBiIN input low-level pulse width (both edges count) 80 ns UnitSymbol Parameter Timer B input (Count input in event counter mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 320 ns tw(TBH) TBiIN input high-level pulse width (Note) 160 ns tw(TBL) TBiIN input low-level pulse width (Note) 160 ns UnitSymbol Parameter Timer B input (Pulse period measurement mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 320 ns tw(TBH) TBiIN input high-level pulse width (Note) 160 ns tw(TBL) TBiIN input low-level pulse width (Note) 160 ns UnitSymbol Parameter Timer B input (Pulse width measurement mode) Limits Min. Max. tc(AD) AD TRG input cycle time (minimum allowable trigger) 1000 ns tw(ADL) AD TRG input low-level pulse width 125 ns UnitSymbol Parameter A-D trigger input UnitSymbol Parameter Serial I/O UnitSymbol Parameter Limits Min. Max. tc(CK) CLK i input cycle time 200 ns tw(CKH) CLK i input high-level pulse width 100 ns tw(CKL) CLK i input low-level pulse width 100 ns td(C–Q) TXD i output delay time 80 ns th(C–Q) TXD i hold time 0n s tsu(D–C) RXD i input setup time 30 ns th(C–D) RXD i input hold time 90 ns Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 320 ns tw(TBH) TBiIN input high-level pulse width (Note) 160 ns tw(TBL) TBiIN input low-level pulse width (Note) 160 ns UnitSymbol Parameter Timer B input (Pulse width measurement mode) UnitSymbol Parameter A-D trigger input UnitSymbol Parameter Serial I/O UnitSymbol Parameter Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 72. External interrupt INTi input, key input interrupt KIi input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. DATA FORMULAS Timer A input (Gating input in timer mode) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time tw(TAH) TAiIN input high-level pulse width tw(TAL ) TAi IN input low-level pulse width ns ns ns 8 5 109 2 · f(f2) Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Limits Min. Max.Symbol Parameter Unit ns ns ns tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width 8 5 109 2 · f(f2) 4 5 109 2 · f(f2) 4 5 109 2 · f(f2) 8 5 109 2 · f(f2) 4 5 109 2 · f(f2) 4 5 109 2 · f(f2) Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. td(E–P0Q) Port P0 data output delay time 80 ns td(E–P1Q) Port P1 data output delay time 80 ns td(E–P2Q) Port P2 data output delay time 80 ns td(E–P3Q) Port P3 data output delay time 80 ns td(E–P4Q) Port P4 data output delay time 80 ns td(E–P5Q) Port P5 data output delay time 80 ns td(E–P6Q) Port P6 data output delay time 80 ns td(E–P7Q) Port P7 data output delay time 80 ns td(E–P8Q) Port P8 data output delay time 80 ns UnitSymbol Parameter Test conditions SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85°C, f(XIN) = 25 MHz (Note), unless otherwise noted) Fig. 73 Measuring circuit for ports P0 – P8 and φ 1 Fig. 73 P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 φ E 50 pF Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Symbol Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output set up time Address hold time ALE output delay time Data output delay time Data hold delay time WEL /WEH pulse width Floating start delay time Floating release delay time RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time HLDA output delay time Limits Wait mode Min. Max. Memory expansion mode and microprocessor mode (VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Test conditions td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th( φ 1–RSMP) td(WE– φ 1) td(RDE– φ 1) td( φ 1–HLDA) Notes 1.This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 130 128 Fig. 73 (Note 2) No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Max., Note1), unless otherwise noted) Limits Wait mode Min. Max. Symbol Parameter Unit 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) ns ns No wait Wait 1 Wait 0 td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th( φ -1–RSMP) td(WE– φ 1) td(RDE– φ 1) ns 4 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) ns ns ns ns ns ns ns ns ns ns No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 1 5 109 2 · f(f2) ns ns ns ns ns ns 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 4 5 109 2 · f(f2) ns ns 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 4 5 109 2 · f(f2) 1 5 109 2 · f(f2) ns ns ns ns ns ns Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output set up time Address hold time ALE output delay time Data output delay time Data hold time WEL /WEH pulse width Floating start delay time Floating release delay time RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time – 28 – 33 – 28 – 45 – 22 – 18 – 23 – 35 – 35 – 25 – 30 – 22 – 30 – 30 – 20 – 32 – 32 – 30 – 28 – 33 Notes 1.This applies when the main-clock division selection bit = “0”. 2. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. TIMING DIAGRAM tw(H) td(E–P0Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port P0 output Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input E XIN Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input Single-chip mode tsu(P0D–E) th(E–P0D) td(E–P1Q) tr tf tw(L) tc tsu(P1D–E) th(E–P1D) tsu(P2D–E) th(E–P2D) tsu(P3D–E) th(E–P3D) tsu(P4D–E) th(E–P4D) tsu(P5D–E) th(E–P5D) tsu(P6D–E) th(E–P6D) tsu(P7D–E) th(E–P7D) tsu(P8D–E) th(E–P8D)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. TAiIN input TAiOUT input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN–UP) tsu(UP–TIN) TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) In event count mode TAjIN input TAjOUT input tc(TA) tsu(TAjIN–TAjOUT ) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) tsu(TAjOUT –TAjIN) In event counter mode (When two-phase pulse input is selected) t c(TB) tw(TBH) tw(TBL) TBiIN input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(KNL) td(C–Q) tSU(D–C) th(C–D) tw(INH) AD TRG input CLK i TxD i RxD i INTi input Kli input th(C–Q)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Memory expansion mode and microprocessor mode (When wait bit = “1”) ( When wait bit = “0”) (When wait bit = “1” or “0” in common) Test conditions

• VCC = 5 V – 10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V f 1 RDY input f 1 WEL WEH RDE RDY input f 1 HOLD input HLDA output tsu(RDY– f1) th( f1–RDY) tsu(RDY– f1) th( f1–RDY) tsu(HOLD– f1) td( f1–HLDA) th( f1–HOLD) td( f1–HLDA) WEL WEH RDE

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tw(WE) th(WE–DQ) tw(L) tw(H) tf tr tc Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”) XIN CS 0 – CS 4 An ALE Am/Dm td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) Address td(An–WE) td(An–RDE) th(RDE–An)tw(ALE) td(ALE–WE) Address Address tsu(A–ALE) th(ALE–A) td(A–WE) td(A–RDE) td(ALE–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) Address Data Address Address WEL, WEH th(WE–An) td(WE–DQ) Dm IN RDE RSMP Test condition

• Vcc = 5 V ± 10%
• Output timing voltage : V IL = 0.8 V, VIH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP–WE) th( 1–RSMP) td(RSMP–RDE) Data td(RED– 1)td(WE– 1)td(WE– 1) td(RED– 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tctw(L) tw(H) tf tr tw(ALE) td(An–WE) Am/Dm Address td(CS–RDE) tw(RDE) td(RDE- 1) Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.) XIN Address Address CS 0 – CS 4 An ALE WEL, WEH Dm IN RDE RSMP td(WE– 1) td(RDE– 1) td(CS–WE) td(ALE–WE) th(RDE–An) tsu(A–ALE) th(ALE–A) td(A–WE) td(WE–DQ) tw(WE) td(A–RDE) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D) tsu(D–RDE) td(RSMP–WE) th( 1–RSMP) td(RSMP–RDE) Test condition

• Vcc = 5 V ± 10%
• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V Data Address th(WE–CS) Data td(WE– 1) th(WE-An) td(ALE–RDE) td(An–RDE) th(WE–DQ) Address tpxz(RDE–DZ)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tctr th(ALE–A) td(ALE–WE) td(WE–DQ) tw(L) tw(H) tf Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) XIN Address Address Address Address Data CS 0 – CS 4 An ALE Am/Dm WEL , WEH Dm IN RDE RSMP td(CS–WE) th(WE–CS) td(CS–RDE) td(An–WE) tw(ALE) th(WE–An) td(An–RDE) th(RDE–An) tsu(A–ALE) th(WE–DQ) td(ALE–RDE) td(A–WE) tw(WE) td(A–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D)tsu(D–RDE) tw(RDE) td(RSMP–WE) th(ƒÓ1–RSMP) td(RSMP–RDE) Address Data Address Test conditions

• Vcc = 5 V ± 10%
• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V td(WE– 1) td(RDE– 1) td(RDE– 1)td(WE– 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE

SINGLE-CHIP 16-BIT MICROCOMPUTER M37735MHBXXXFP MITSUBISHI ELECTRIC Date: Receipt GZZ–SH00–79B<84A0> ( ) Note : Please fill in all items marked Customer SupervisorCompany name Date issued Date: TEL 1. Confirmation Specify the name of the product being ordered. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM areas EPROM Type : (1) Set “FF 16” in the shaded area. (2) Address 0 16 to 10 16 are the area for storing the data on model designation and options.This area must be written with the data shown below. Details for option data are given next in the section describing the STP instruction option. Address and data are written in hexadecimal notation. F A E C B (hexadecimal notation) 27C201 128K 3FFFF DATA D Responsible officer Section head signature Supervisor signature Issuance signatures FF FF FF FF FF FF FF Option data Address Address Address

7700 FAMILY MASK ROM ORDER CONFIRMATION FORM

One of the following sets of data should be written to the option data address (1016) of the EPROM you have ordered. Check @ in the appropriate box. STP instruction enable STP instruction disable 2. STP instruction option 0116 0016 Address 1016 Address 1016 3. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 80P6N Mark Specification Form (for M37735MHBXXXFP) and attach to the Mask ROM Order Confirmation Form. 4. Comments Note : Make sure that address 01FFFF16 of the microcomputer’s internal ROM corresponds to address 3FFFF 16 of EPROM.

(6-digit, or 7-digit) 65 40 64 41 Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s parts number can be up to 14 alphanumeric char- acters for capital letters, hyphens, commas, periods and so on. 80P6N (80-PIN QFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark C. Special Mark Required B. Customer’s Parts Number + Mitsubishi IC Catalog Name Mitsubishi IC catalog name Notes1 : If special mark is to be printed, indicate the desired lay- out of the mark in the left figure. The layout will be duplicated technically as close as possible. Mitsubishi product number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked for sorting the products. 2 : If special character fonts (e,g., customer’s trade mark logo) must be used in Special Mark, check the box be- low. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special character fonts required 65 40 64 41

© 1996 MITSUBISHI ELECTRIC CORP. H-LF425-A KI-9606 Printed in Japan (ROD) New publication, effective Jun. 1996. Specifications subject to change without notice. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS M37735MHBXXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.

03 FFFF16

07 FFFF16

Rev. Rev. No. date

1.00 First Edition 970604

1.01 The following are added: 980526

• MASK ROM ORDER CONFIRMATION FORM
• MARK SPECIFICATION FORM

2.00 The following are revised: 980731

REVISION DESCRIPTION LIST M37735MHBXXXFP Datasheet (1) Revision Description Page Right column Line 5 Fig. 1 Right column Line 12 P50 Fig. 58 P53 Table 7 Previous Version Additionally, the internal ROM area can be modi- fied by software. Note. Internal ROM area can be modified. (Refer to the section on ROM area modification function.) The CPU operates on an internal clock φ’s fre- quency which is obtained by dividing the external clock frequency f(XIN) by two. Revised Version Additionally, the internal ROM and RAM area can be modified by software. Note. Internal ROM and RAM area can be modi fied. (Refer to the section on ROM area modification function.) The CPU operates on an internal clock φ’s fre- quency. <P o r t P 0 > I / O P o r t P 06 P R S M P P 05 C C P 00 t o P E <P o r t P 0 > A d d r e s s A1 7, A1 P 06 P R S M P P 05 C C P 00 t o P E Memory expansion mode Memory expansion mode

(3) REVISION DESCRIPTION LIST M37735MHBXXXFP Datasheet Fig. 72 Memory allocation (modification of internal ROM area by memory allocation selection bit) Internal RAM 3968 bytes Internal RAM 3968 bytes Internal RAM 3968 bytes Internal RAM 3968 bytes SFR SFR SFR SFR (4 Kbytes) (28 Kbytes)(28 Kbytes) Internal ROM

56 Kbytes

64 Kbytes

01FFFF 16 01FFFF 16 01FFFF 16 FFFFFF 16 FFFFFF 16 FFFFFF 16 FFFFFF 16 00FFFF 16 01000016 00FFFF 16 01000016 00FFFF 16 01000016 00FFFF 16 ROM size : 124 Kbytes ROM size :120 Kbytes ROM size : 96 Kbytes ROM size : 32 Kbytes : External memory area Note. Banks 1016–FF16 cannot be accessed in the 7735 group. Previous version

(4) REVISION DESCRIPTION LIST M37735MHBXXXFP Datasheet Fig. 72 Memory allocation (modification of internal ROM and RAM area by memory allocation selection bits) Internal RAM 3968 bytes Internal RAM 3968 bytes Internal RAM 2048 bytes SFR SFR SFR (4 Kbytes) (1.9 Kbytes) Internal ROM FFFFFF 16 FFFFFF 16 FFFFFF 16 00FFFF 16 01000016 00FFFF 16 01000016 00FFFF 16 : External memory area Internal RAM 2048 bytes Internal RAM 2048 bytes Internal RAM 3968 bytes SFR SFR SFR (45.9 Kbytes) (28 Kbytes) Internal ROM FFFFFF 16 FFFFFF 16 FFFFFF 16 00FFFF 16 01000016 00FFFF 16 01000016 00FFFF 16 (29.9 Kbytes) 01FFFF 16 Note. Banks 1016–FF16 cannot be accessed in the 7735 group. Revised version