M37517F8HP

M37517F8HP RENESAS | Alldatasheet

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Rev.1.01 Aug 02, 2004 page 1 of 96

7517 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0087-0101Z Rev.1.01 Aug 02, 2004

DESCRIPTION

The 7517 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 7517 group is designed for battery-pack and includes serial interface functions, 8-bit timer, A/D converter, current integrator and I 2C-BUS interface.

FEATURES

(at 4 MHz oscillation frequency) G Memory size PIN CONFIGURATION (TOP VIEW) Fig. 1 M37517F8HP pin configuration (built-in 4MHz on-chip oscillator and 32kHz RC oscillator, or con- nect to external ceramic resonator or quartz-crystal oscillator) G Power source voltage (at 4 MHz oscillation frequency) (at 8 MHz oscillation frequency) (at 32 kHz oscillation frequency) G Power dissipation (at 4 MHz oscillation frequency, at 3.3 V power source voltage) (at 32 kHz oscillation frequency, at 3.3 V power source voltage) APPLICATION Battery-Pack, etc. 1 2 3 4 5 6 7 8 9 10 11 12 35 34 33 32 31 30 29 28 27 26 25 Package type : 48P6Q-A P17/(LED7) 2/INT 1/INT 0/CNTR 7/CNTR 0/S RDY1 6/S CLK 5/SCL 2/T XD 3/SCL 2/SDA CNV SS P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) VSS XOUT XIN 4/AN 5/AN 0/S IN2 1/S OUT2 2/S CLK2 3/S RDY2 4/AN 5/AN 6/AN 1/(LED 7/AN 0/(LED RESET P20/XCOUT P21/XCIN 4/INT 3/PWM 4/SDA 2/R XD P33/AN3 P32/AN2 ADV SS ADV REF VCC AV SS ISENS0 ISENS1 P31/AN1 P30/AN0 AV CC DFETCNT/P4 5 3/INT 2/S CMP2 M37517F8HP

Rev.1.01 Aug 02, 2004 page 2 of 96 Fig. 2 Functional block diagram FUNCTIONAL BLOCK RESET CNV SS CNTR Reset input P1(8) 21 23 25 20 22 24 26I/O port P 1 Timer 2 (8) Prescaler Y (8) Timer Y (8) CNTR P2(8) 68 1 0 1 3 7 9 11 14I/O port P 2 X CIN X COUT SI/O2(8) P0(8) 27 28 29 30 31 32 I/O port P 0 SI/O1(8) R A M R O M C P U A X Y S PC H PC L PS V SS 18 V CC 43 39 40 P3(6) I/O port P 335 37 36 38 I C(8) INT - INT P4(6) 48 4 135 I/O port P 4 X IN OUT X 42 Clock generating circuit Main-clock input 10-bitA/D converter ADV REF ADV SS X CIN sub-clock input PWM (8) Current integrator ISENS0 AVcc ISENS1 AVss Over current detector Timer X (8)Timer 1 (8) Prescaler X (8)Prescaler 12 (8) Main-clockoutput Reset Watchdog timer X COUT sub-clock output

Rev.1.01 Aug 02, 2004 page 3 of 96 VCC , VSS AV CC AV SS ADV SS AD VREF CNV SS RESET XIN XOUT P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04/AN8–P07/AN11 P10–P17 P20/XCOUT P21/XCIN P22/SDA 1 P23/SCL1 P24/SDA 2/RxD P25/SCL2/TxD P26/SCLK P27/CNTR 0/ SRDY1 P30/AN0– P35/AN5 P40/CNTR 1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM P45/DFETCNT ISENS0 ISENS1 PIN DESCRIPTION FunctionsNamePin

• Apply voltage of 3.3V to Vcc, and 0 V to Vss.
• Apply voltage of 3.3V to AVcc, and 0 V to AVss and ADVss.
• Reference voltage input pin for A/D converter.
• This pin controls the operation mode of the chip.
• Normally connected to VSS .
• Reset input pin for active “L”.
• Input and output pins for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• When an on-chip oscillator is used, leave the XIN pin and XOUT pin open.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• P10 to P17 (8 bits) are enabled to output large current for LED drive. Power source Table 1 Pin description Function except a port function Analog power source Analog reference voltage CNV SS input Reset input Clock input Clock output
• Serial I/O2 function pin
• Sub-clock generating circuit I/O pins (connect a resonator)
• I2C-BUS interface function pin/ Serial I/O1 function pin
• Serial I/O1 function pin
• Serial I/O1 function pin/ Timer X function pin
• A/D converter input pin
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level.
• P22 to P25 can be switched between CMOS compat- ible input level or SMBUS input level in the I2C-BUS interface function.
• P20, P21, P24 to P27: CMOS3-state output structure.
• P2 4, P25: N-channel open-drain structure in the I2C- BUS interface function.
• P22, P23: N-channel open-drain structure.
• I2C-BUS interface function pin
• 8-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 6-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• A/D converter input pin
• Timer Y function pin
• Interrupt input pin
• Interrupt input pin/SCMP2 output pin
• Interrupt input pin/PWM output pin
• Over current detector function pin
• Input pins for the current integrator and the over current detector. Connect these pins at both ends of a detection resistor, and connect ISENS0 to GND. I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 Analog input

Rev.1.01 Aug 02, 2004 page 4 of 96 CENTRAL PROCESSING UNIT (CPU) The 7517 group uses the standard 740 Family instruction set. Re- fer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. Fig. 3 Structure of CPU mode register [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B 16. CPU mode register (CPUM : address 003B16) b7 b0 Stack page selection bit 0 : 0 page 1 : 1 page Processor mode bits b1 b0 0 0 : Single-chip mode 01 : 1 0 : Not available 11 : Port X C switch bit 0 : I/O port function (stop oscillating) 1 : X CIN–XCOUT oscillation function Main clock (XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 00 : φ = f(X IN)/2 (high-speed mode) 01 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Clock source switch bit 0 : On-chip oscillation function 1 : X CIN–XCOUT oscillation function Note : All bits in this register are protected by protect mode.

Rev.1.01 Aug 02, 2004 page 5 of 96 Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Flash Memory The first 128 bytes and the last 2 bytes of flash memory are re- served for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 4 Memory map diagram 010016 000016 004016 044016 FF0016 FFDC 16 FFFE 16 FFFF 16 800016 808016 RAM 1024 bytes Flash memory 32 kbytes 0FFD 16 0FFF 16 FFD4 16 SFR area Not used Interrupt vector area Reserved memory area (128 bytes) Zero page Special page Reserved memory area SFR area Flash memory ID code Not used

Rev.1.01 Aug 02, 2004 page 6 of 96 Fig. 5 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) Interrupt control register 2 (ICON2) A/D conversion low-order register (ADL) Prescaler Y (PREY) Timer Y (TY) A/D control register (ADCON) A/D conversion high-order register (ADH) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Prescaler 12 (PRE12) Timer 2 (T2) Prescaler X (PREX) Timer X (TX) Timer 1 (T1) Timer XY mode register (TM) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) I2C start/stop condition control register (S2D) MISRG Watchdog timer control register (WDTCON) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Timer count source selection register (TCSS) Wake up current detector control register1 (WUDCON1) Current detect status register (OCDSTS) Wake up current detector control register2 (WUDCON2) ✽ Reserved : Do not write any data to the reserved area. Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) I2C additional function register (S3) MISRG2 0FFD 16 0FFE 16 0FFF 16 Flash memory control register (FCON) Reserved ✽ Reserved ✽ Discharge counter latch low-order register (DCHARGEL) Discharge counter latch high-order register (DCHARGEH) Charge counter latch low-order register (CHARGEL) Charge counter latch high-order register (CHARGEH) Short current detector control register (SCDCON) Over current detector control register (OCDCON) Current detect time set up register (OCDTIME) Current integrator control register (CINFCON) Reserved ✽ SFR protect control register (PRREG) 32kHz oscillation control register 1 (32KOSCC1) 32kHz oscillation control register 0 (32KOSCC0)

Rev.1.01 Aug 02, 2004 page 7 of 96 Pin Name Input/Output I/O Structure Non-Port Function Ref.No. Table 2 I/O port function Related SFRs I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin becomes an output pin. Port P0 Port P1 Port P3 Input/output, individual bits CMOS compatible input level CMOS 3-state output Sub-clock generating circuit CPU mode register MISRG2 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Port P2 Port P4 CMOS compatible input level CMOS/SMBUS input level (when selecting I 2C-BUS interface function) N-channel open-drain output CMOS compatible input level CMOS/SMBUS input level (when selecting I 2C-BUS interface function) CMOS 3-state output N-channel open-drain output (when selecting I 2C-BUS interface function) CMOS compatible input level CMOS 3-state output I2C-BUS interface func- tion I/O I2C-BUS interface func- tion I/O Serial I/O1 function I/O Serial I/O1 function I/O I2C control register I2C control register Serial I/O1 control register Serial I/O1 control register Serial I/O1 control register Timer XY mode register A/D control register MISRG2 Timer XY mode register Interrupt edge selection register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register PWM control register External interrupt input PWM output P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04/AN8–P07/AN11 P10–P17 P20/XCOUT P21/XCIN P22/SDA 1 P23/SCL1 Serial I/O2 control register Serial I/O2 function I/O P24/SDA 2/RxD P25/SCL2/TxD P26/SCLK P27/CNTR 0/ SRDY1 Serial I/O1 function I/O Timer X function I/O A/D conversion input Timer Y function I/O External interrupt input P30/AN0– P35/AN5 P40/CNTR 1 P41/INT0 P42/INT1 P43/INT2/SCMP2 External interrupt input SCMP2 output P44/INT3/PWM P45/DFETCNT (5) (15) (16) (17) (18) (19) A/D conversion input A/D control register, MISRG2 (13) (14) If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Short current detect control register Over current detect control register Wake up current detect control register Over current detector output

Rev.1.01 Aug 02, 2004 page 8 of 96 Fig. 6 Port block diagram (1) (4) Port P03 (1) Port P00 (2) Port P01 P01/SOUT2 P-channel output disable bit (3) Port P02 P02/SCLK2 P-channel output disable bit Direction register Data bus Port latch Direction register Data bus Port latch Data bus Port latch Direction register Data bus Port latch Direction register Serial I/O2 input Serial I/O2 transmit completion signal Serial I/O2 port selection bit Serial I/O2 output SRDY2 output enable bit Serial I/O2 ready output Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Serial I/O2 external clock input Serial I/O2 clock output (6) Port P1 Data bus Port latch Direction register (7) Port P20 (8) Port P21 Data bus Port latch Direction register Port XC switch bit Sub-clock generating circuit input (5) Ports P04–P07, P30–P35 Data bus Port latch Direction register A/D converter input Analog input pin selection bit Direction register Data bus Port latch Port XC switch bit Port P21 Port Xc switch bit 32kHz RC oscillation enable bit 32kHz RC oscillation enable bit Reference voltage

Rev.1.01 Aug 02, 2004 page 9 of 96 Fig. 7 Port block diagram (2) (10) Port P23 Data bus Port latch Direction register SDA/SCL pin selection bit I2C-BUS interface enable bit SCL output SCL input (16) Ports P41, P42 Data bus Port latch Direction register Interrupt input (15) Port P40 Data bus Port latch Direction register CNTR 1 interrupt input Pulse output mode Timer output (14) Port P27 Data bus Port latch Direction register CNTR 0 interrupt input Pulse output mode Timer output Serial I/O1 ready output Pulse output mode Serial I/O1 enable bit Serial I/O1 mode selection bit SRDY1 output enable bit (13) Port P26 Data bus Port latch Direction register Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Serial I/O1 synchronous clock selection bit Serial I/O1 external clock input Serial I/O1 clock output (12) Port P25 Data bus Port latch Direction register P-channel output disable bit Serial I/O1 enable bit Transmit enable bit SDA/SCL pin selection bit I2C-BUS interface enable bit SCL inputSerial I/O1 output SCL output (11) Port P24 SDA output SDA input SDA/SCL pin selection bit I2C-BUS interface enable bit Data bus Port latch Direction register Serial I/O1 input Serial I/O1 enable bit Receive enable bit SDA/SCL pin selection bit (9) Port P22 Data bus Port latch Direction register SDA output SDA input I2C-BUS interface enable bit

Rev.1.01 Aug 02, 2004 page 10 of 96 Fig. 8 Port block diagram (3) (18) Port P44 PWM output enable bit PWM output (17) Port P43 Data bus Port latch Direction register Data bus Port latch Direction register Serial I/O2 input/output comparison signal control bit Serial I/O2 input/output comparison signal output Interrupt input Interrupt input (19) Port P45 Data bus Port latch Direction register DFETCNT output Short current detect enable bit Over current detect enable bit Wake up current detect enable bit

Rev.1.01 Aug 02, 2004 page 11 of 96 Interrupts occur by 16 sources among 19 sources: seven external, eleven internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the in- terrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK in- struction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are auto- matically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. I Notes When the active edge of an external interrupt (INT0–INT3, SCL/ SDA, CNTR 0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take the following sequence: 1. Disable the interrupt. 2. Set the interrupt edge selection register (SCL/SDA interrupt pin polarity selection bit for SCL/SDA; the timer XY mode register for CNTR0 and CNTR1). 3. Set the interrupt request bit to “0”. 4. Accept the interrupt.

Rev.1.01 Aug 02, 2004 page 12 of 96 Generating Conditions RemarksInterrupt Source Low FFFC 16 High FFFD 16 Priority Table 3 Interrupt vector addresses and priority Vector Addresses (Note 1) Reset (Note 2) INT0 SCL, SDA INT1 INT2 INT3 Serial I/O2 At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) At detection of either rising or falling edge of SCL or SDA input External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF0 16FFF1 167 Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. I2C Timer X Timer Y Timer 1 Timer 2 Serial I/O1 reception Serial I/O1 transmission Over current detection CNTR Valid when serial I/O1 is selected Valid when serial I/O1 is selected FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDC 16FFDD 16 At detection of either rising or falling edge of INT3 input At completion of serial I/O2 data reception Valid when serial I/O2 is selected At completion of data transfer At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmis- sion buffer is empty At short current is detected, at over current is detected, or at wake up current is detected. At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input STP release timer underflow CNTR 1 A/D converter At completion of A/D conversion Valid when short current detector or over current detector, or wake up current detector is selected. External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when current integrator is selected Non-maskable software interrupt Current integration BRK instruction At end of current integration period, or at end of calibration At BRK instruction execution

Rev.1.01 Aug 02, 2004 page 13 of 96 Interrupt edge selection register INT0 active edge selection bit INT1 active edge selection bit INT2 active edge selection bit INT3 active edge selection bit Serial I/O2 / INT3 interrupt source bit Current integrate/A/D converter interrupt source bit Over current detect / Serial I/O1 transmit interrupt source bit Not used (returns “0” when read) (INTEDGE : address 003A 16) 0 : Falling edge active 1 : Rising edge active 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Interrupt request register 1 INT0 interrupt request bit SCL/SDA interrupt request bit INT 1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit I2C interrupt request bit Timer X interrupt request bit Timer Y interrupt request bitInterrupt control register 1 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C16) (ICON1 : address 003E16) Interrupt request register 2 Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit / Over current detect interrupt request bit CNTR 0 interrupt request bit CNTR 1 interrupt request bit AD converter /current integrate interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D 16) Interrupt control register 2 Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit / Over current detect interrupt enable bit CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit AD converter / current integrate interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16) 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt enable bit SCL/SDA interrupt enable bit INT 1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit I2C interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled 0 : AD converter interrupt selected 1 : Current integrate interrupt selected 0 : Serial I/O1 transmit interrupt selected 1 : Over current detect interrupt selected Fig. 9 Interrupt control Fig. 10 Structure of interrupt-related registers (1) Interrupt disable flag (I) Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset

Rev.1.01 Aug 02, 2004 page 14 of 96 The 7517 group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “00 16”, an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The out- put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register. (1) Timer Mode The timer counts the count source selected by Timer count source selection bit. (2) Pulse Output Mode The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “00 16”, the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR 0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to out- put mode. (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR 0 or CNTR 1 pin. When the CNTR 0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted. (4) Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at “H ”. If the CNTR0 (or CNTR1) ac- tive edge selection bit is “1”, the timer counts it while the CNTR0 (or CNTR1) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows. Fig. 11 Structure of timer XY mode register I Note When switching the count source by the timer 12, X or Y count source bit, the value of timer count is altered in inconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. Fig. 12 Structure of timer count source selection register Timer X count stop bit 0: Count start 1: Count stop Timer XY mode register (TM : address 002316) Timer Y operating mode bits 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR 1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode b 7 C N T R 0 a c t i v e e d g e s e l e c t i o n b i t I n t e r r u p t a t f a l l i n g e d g e C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e I n t e r r u p t a t r i s i n g e d g e C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e b 0 Timer X operating mode bits 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode b 1 b 0 b 5 b 4 T i m e r Y c o u n t s t o p b i t C o u n t s t a r t C o u n t s t o p Timer count source selection register (TCSS : address 002816) b7 b0 Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns “0” when read)

Rev.1.01 Aug 02, 2004 page 15 of 96 Q Q “1” “0” P27/CNTR 0 Q Q P40/CNTR 1 “0” “1” R R “1” “0” “0” “1” T T Prescaler X latch (8) Prescaler X (8) Timer X latch (8) Timer X (8) To timer X interrupt request bit Toggle flip-flop Timer X count stop bit Pulse width measurement mode Event counter mode To CNTR 0 interrupt request bit Pulse output mode Port P27 latchPort P27 direction register CNTR 0 active edge selection bit Timer X latch write pulse Pulse output mode Timer mode Pulse output mode Prescaler Y latch (8) Prescaler Y (8) Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit Toggle flip-flop Timer Y count stop bit To CNTR 1 interrupt request bit Pulse output mode Port P40 latchPort P40 direction register CNTR 1 active edge selection bit Timer Y latch write pulse Pulse output mode Timer mode Pulse output mode Data bus Data bus Prescaler 12 latch (8) Prescaler 12 (8) Timer 1 latch (8) Timer 1 (8) Data bus Timer 2 latch (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit CNTR 0 active edge selection bit CNTR 1 active edge selection bit Pulse width measure- ment mode Event counter mode f(XCIN) Timer 12 count source selection bit f(XIN)/16 f(XIN)/2 Timer Y count source selection bit f(XIN)/16 f(XIN)/2 Timer X count source selection bit f(XIN)/16 Fig. 13 Block diagram of timer X, timer Y, timer 1, and timer 2

Rev.1.01 Aug 02, 2004 page 16 of 96 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A 16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Fig. 14 Block diagram of clock synchronous serial I/O1 Fig. 15 Operation of clock synchronous serial I/O1 function F/F P26/SCLK Serial I/O1 status register Serial I/O1 control register P27/SRDY1 P24/RXD P25/TXD XIN Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C BRG count source selection bit Clock control circuitFalling-edge detector Transmit buffer register Data bus Address 001816 Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit shift register D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD Write pulse to receive/transmit buffer register (address 0018 16) Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

Rev.1.01 Aug 02, 2004 page 17 of 96 (2) Asynchronous Serial I/O(UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 16 Block diagram of UART serial I/O1 XIN OE PE FE Data bus Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register Data bus Transmit shift register Address 001816 Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 ST detector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 control register P26/SCLK1 Serial I/O1 status register P24/RXD P25/TXD

Rev.1.01 Aug 02, 2004 page 18 of 96 Fig. 17 Operation of UART serial I/O1 function [Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 Status Register (SIOSTS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 Control Register (SIOCON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial interface is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P2 5/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. I Note When using the serial I/O1, clear the I2C-BUS interface enable bit to “0” or the SCL/SDA pin selection bit to “0”. TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer read signal

Rev.1.01 Aug 02, 2004 page 19 of 96 Fig. 18 Structure of serial I/O1 control registers b7b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) Serial I/O1 status register Serial I/O1 control register b0 b0 BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. S RDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P2 4 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P2 4 to P27 operate as serial I/O1 pins) b7 UART control register Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) (SIOSTS : address 001916) (SIOCON : address 001A16) (UARTCON : address 001B16)

Rev.1.01 Aug 02, 2004 page 20 of 96 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selec- tion bit (b2, b1, b0) of serial I/O2 control register 1. Regarding S OUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P01/SOUT2 , P02/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 0017 16). After comple- tion of data transfer, the level of the SOUT2 pin goes to high imped- ance automatically but bit 7 of the serial I/O2 control register 2 is not set to "1" automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the S OUT2 pin does not go to high impedance after completion of data trans- fer. To cause the S OUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to "1" when S CLK2 is "H" after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt re- quest bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously re- ceived data is shifted. At transmit operation using the clock synchronous serial I/O, the S CMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, "L" is output from the SCMP2 pin. If not, "H" is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A 16). [Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2 The serial I/O2 control registers 1 and 2 are containing various se- lection bits for serial I/O2 control as shown in Figure 19. Fig. 19 Structure of Serial I/O2 control registers 1, 2 Serial I/O2 control register 1 (SIO2CON1 : address 001516) Serial I/O2 control register 2 (SIO2CON2 : address 001616) b7 b0 Optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P4

3 I/O

1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance Internal synchronous clock selection bit b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 0 0: Not available 1 0 1: Not available 1 1 0: f(X IN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: S OUT2 ,SCLK2 output pin SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock 1/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode )

Rev.1.01 Aug 02, 2004 page 21 of 96 Fig. 20 Block diagram of Serial I/O2 Fig. 21 Timing chart of Serial I/O2 XIN "1" "0" "0" "1" "0" "1" SRDY2 S CLK2 "0" "1" "1" "0" XCIN "10" "00" "01" Data bus Serial I/O2 interrupt request Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O2 register (8) Synchronous circuit Serial I/O2 port selection bit Serial I/O2 synchronous clock selection bit SRDY2 output enable bit External clock Internal synchronous clock selection bit Divider Optional transfer bits (3) P02/SCLK2 P01/SOUT2 P00/SIN2 P02 latch P01 latch P03 latch P03/SRDY2 P43/SCMP2 /INT2 Serial I/O2 I/O comparison signal control bit P43 latch Q D Main clock division ratio selection bits (Note) Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register. D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 Write-in signal to serial I/O2 register (Note 2) Serial I/O2 interrupt request bit set 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the S COUT2 pin has high impedance after transfer completion. Notes

Rev.1.01 Aug 02, 2004 page 22 of 96 Fig. 22 SCMP2 output operation SCLK2 SIN2 SOUT2 SCMP2 Judgement of I/O data comparison

Rev.1.01 Aug 02, 2004 page 23 of 96 In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I 2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Table 4 Multi-master I 2C-BUS interface functions Item Format Communication mode System clock φ = f(XIN)/2 (high-speed mode) φ = f(XIN)/8 (middle-speed mode) MULTI-MASTER I 2C-BUS INTERFACE The multi-master I2C-BUS interface is a serial communications cir- cuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 23 shows a block diagram of the multi-master I 2C-BUS in- terface and Table 4 lists the multi-master I2C-BUS interface functions. This multi-master I 2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register, the I2C start/stop condition control register and other control circuits. When using the multi-master I 2C-BUS interface, set 1 MHz or more to φ . Note: Renesas Technology Corporation assumes no responsibility for in- fringement of any third-party’s rights or originating in the use of the connection control function between the I2C-BUS interface and the ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control regis- ter (002E16). Fig. 23 Block diagram of multi-master I2C-BUS interface ✽ : Purchase of Renesas Technology Corporation‘s I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SCL clock frequency I2C address registerb7 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB Noise elimination circuit Address comparator I2C data shift register b0Data control circuit System clock (φ) Interrupt generating circuit Interrupt request signal (IICIRQ) TRX BB PIN AAS AD0 LRB b7 b0 TISS 10BIT SAD ALS BC2 BC1 BC0 Bit counter BB circuit Clock control circuit Noise elimination circuit b7 b0 ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 Internal data bus Clock division S0D AL circuit ES0 SIS I2C start/stop condition control register SIP SSC4 SSC3 SSC2 SSC1 SSC0 I2C clock control register I2C status register S2D TSEL S1D I C control register2 Serial data (SDA) Serial clock (SCL) AL MST

Rev.1.01 Aug 02, 2004 page 24 of 96 [I2C Data Shift Register (S0)] 002B16 The I2C data shift register (S0 : address 002B16) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 machine cycles are required from the rising of the SCL clock until input to this register. The I 2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of the I2C control register is “1”. The bit counter is reset by a write in- struction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 002D16) are “1”, the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled re- gardless of the ES0 bit value. [I2C Address Register (S0D)] 002C16 The I2C address register (address 002C16) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is de- tected.

• Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I 2C address reg- ister. The RWB bit is cleared to “0” automatically when the stop condi- tion is detected.
• Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bit's contents. Fig. 24 Structure of I 2C address register SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB Slave address I2C address register (S0D: address 002C16) Read/write bit b7 b0

Rev.1.01 Aug 02, 2004 page 25 of 96 Table 5 Set values of I2C clock control register and SCL frequency Fig. 25 Structure of I2C clock control register SCL frequency (Note 1) (at φ = 4 MHz, unit : kHz) Setting value of CCR4 –CCR0 Standard clock mode Setting disabled Setting disabled Setting disabled High-speed clock modeCCR4 CCR3 CCR2 CCR1 CCR0 Setting disabled Setting disabled Setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (Note 3) 166 – (Note 2) – (Note 2) [I2C Clock Control Register (S2)] 002F16 The I2C clock control register (address 002F16) is used to set ACK control, SCL mode and SCL frequency.

• Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 5.
• Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0”, the standard clock mode is selected. When the bit is set to “1”, the high-speed clock mode is selected. When connecting the bus of the high-speed mode I 2C bus stan- dard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) and 2 division clock.
• Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock ✽ is generated. When this bit is set to “0”, the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1”, the ACK non-return mode is selected. The SDA is held in the “H ” status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = “0”, the SDA is auto- matically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is auto- matically made “H ” (ACK is not returned). ✽ACK clock: Clock for acknowledgment
• Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. When this bit is set to “0”, the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1”, the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H ”) and receives the ACK bit generated by the data receiving device. Note:Do not write data into the I2C clock control register during transfer. If data is written during transfer, the I2C clock generator is reset, so that data cannot be transferred normally. 500/CCR value (Note 3) 1000/CCR value (Note 3) 17.2 16.6 16.1 Notes 1:Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). “H ” duration of the clock fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H ” duration reduction. These are value when SCL clock synchronization by the syn- chronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3: The data formula of SCL frequency is described below: φ/(8 ✕ CCR value) Standard clock mode φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 I2C clock control register (S2 : address 002F16) b7 b0 SCL frequency control bits Refer to Table 5. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock

Rev.1.01 Aug 02, 2004 page 26 of 96 Fig. 27 Structure of I2C control register [I2C Control Register (S1D)] 002E16 The I2C control register (address 002E16) controls data communi- cation format.

• Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I 2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of address 002F16)) have been transferred, and BC0 to BC2 are returned to “0002”. Also when a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits.
• Bit 3: I 2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to “0”, the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to “1”, use of the interface is enabled. When ES0 = “0”, the following is performed.
• PIN = “1”, BB = “0” and AL = “0” are set (which are bits of the I status register at address 002D16 ).
• Writing data to the I2C data shift register (address 002B16) is dis- abled.
• Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0”, the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “I 2C Status Register”, bit 1) is re- ceived, transfer processing can be performed. When this bit is set to “1”, the free data format is selected, so that slave addresses are not recognized.
• Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0”, the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address regis- ter (address 002C16) are compared with address data. When this bit is set to “1”, the 10-bit addressing format is selected, and all the bits of the I2C address register are compared with address data.
• Bit 6: SDA/SCL pin selection bit This bit selects the input/output pins of SCL and SDA of the multi- master I 2C-BUS interface.
• Bit 7: I2C-BUS interface pin input level selection bit This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. Fig. 26 SDA/SCL pin selection bit SCL SDA Multi-master I2C-BUS interface TSEL SCL 1/P23 SCL 2/TxD/P25 SDA 1/P22 SDA 2/RxD/P24 TSEL TSEL TSEL TISS TSEL

10 BIT

0 : Connect to ports P22, P23 1 : Connect to ports P24, P25 I2C control register (S1D : address 002E16) Bit counter (Number of transmit/receive bits) b2 b1 b0 000 : 8 001 : 7 010 : 6 011 : 5 100 : 4 101 : 3 110 : 2 111 : 1 I 2C-BUS interface enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format I2C-BUS interface pin input level selection bit 0 : CMOS input 1 : SMBUS input

Rev.1.01 Aug 02, 2004 page 27 of 96

• Bit 4: SCL pin low hold bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from “1” to “0”. At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (in- cluding the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0”, the SCL is kept in the “0” state and clock generation is disabled. Figure 29 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I 2C data shift register (ad- dress 002B16). (This is the only condition which the prohibition of the internal clock is released and data can be communicated ex- cept for the start condition detection.)
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately af- ter completion of slave address agreement or general call address reception
• In the slave reception mode, with ALS = “1” and immediately af- ter completion of address data reception
• Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0”, this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by detecting the start condition, and is set to “0” by detecting the stop condition. The condition of these detecting is set by the start/stop condition setting bits (SSC4–SSC0) of the I 2C start/stop condition control register (address 003016). When the ES0 bit of the I2C control register (address 002E16) is “0” or reset, the BB flag is set to “0”. For the writing function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition Gen- erating Method” described later. [I2C Status Register (S1)] 002D16 The I2C status register (address 002D16) controls the I2C-BUS in- terface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set “00002” to the low-order 4 bits, because these bits become the reserved bits at writing.
• Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned, this bit is set to “1”. Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 002B16).
• Bit 1: General call detecting flag (AD0) When the ALS bit is “0”, this bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives con- trol data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition, or reset. ✽ General call:The master transmits the general call address “0016” to all slaves.
• Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is “0”. (1)In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-or- der 7 bits of the I2C address register (address 002C16).
• A general call is received. (2)In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I2C address reg- ister (8 bits consisting of slave address and RWB bit), the first bytes agree. (3)This bit is set to “0” by executing a write instruction to the I data shift register (address 002B16) when ES0 is set to “1” or reset.
• Bit 3: Arbitration lost✽ detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1”. At the same time, the TRX bit is set to “0”, so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0”. The arbitration lost can be detected only in the master transmission mode. When ar- bitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ✽ Arbitration lost :The status in which communication as a master is dis- abled.

Rev.1.01 Aug 02, 2004 page 28 of 96 Fig. 29 Interrupt request signal generating timing Fig. 28 Structure of I2C status register

• Bit 6: Communication mode specification bit (transfer direc- tion specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0”, the reception mode is selected and the data of a transmitting device is received. When the bit is “1”, the transmis- sion mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to “1” by hardware when all the following conditions are satisfied:
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1” This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
• Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0”, the slave is specified, so that a START condition and a STOP condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1”, the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communi- cation are generated on the SCL. This bit is set to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transfer when arbi- tration lost is detected
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START condi- tion duplication preventing function (Note).
• At reset Note: START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same time after con- firming that the BB flag is “0” in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to “1” immediately after the con- tents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits in- valid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. MST I2C status register (S1 : address 002D16) Last receive bit (Note) 0 : Last bit = “0” 1 : Last bit = “1” General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected SCL pin low hold bit 0 : SCL pin low hold 1 : SCL pin low release Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode TRX BB PIN AL AAS AD0 LRB Note: These bits and flags can be read out, but cannot be written. Write “0” to these bits at writing. SCL PIN IICIRQ

Rev.1.01 Aug 02, 2004 page 29 of 96 Fig. 32 START condition detecting timing diagram START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 32, 33, and Table 8. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL re- lease time, setup time, and hold time (see Table 8). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 8, the BB flag set/ reset time. Note:When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” occurs to the CPU. START Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I2C status register (address 002D16) at the same time after writing the slave address to the I2C data shift register (address 002B16) with the condition in which the ES0 bit of the I2C control register (address 002E 16) is “1” and the BB flag is “0”, a START condition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 30, the START condition generating timing diagram, and Table 6, the START condition generating timing table. STOP Condition Generating Method When the ES0 bit of the I2C control register (address 002E16) is “1”, write “1” to the MST and TRX bits, and write “0” to the BB bit of the I2C status register (address 002D16) simultaneously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 31, the STOP condition generating timing diagram, and Table 7, the STOP condition generating timing table. Fig. 30 START condition generating timing diagram Fig. 31 STOP condition generating timing diagram Table 7 STOP condition generating timing table Item Setup time Hold time Standard clock mode 5.0 µs (20 cycles) 4.5 µs (18 cycles) Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. High-speed clock mode 3.0 µs (12 cycles) 2.5 µs (10 cycles) Table 6 START condition generating timing table Item Setup time Hold time Standard clock mode 5.0 µs (20 cycles) 5.0 µs (20 cycles) Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. High-speed clock mode 2.5 µs (10 cycles) 2.5 µs (10 cycles) Table 8 START condition/STOP condition detecting conditions Note:Unit : Cycle number of system clock φ SSC value is the decimal notation value of the START/STOP condi- tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I2C START/ STOP condition control register is set to “1816” at φ = 4 MHz. Fig. 33 STOP condition detecting timing diagram SCL release time Standard clock mode High-speed clock mode 4 cycles (1.0 µs) 2 cycles (1.0 µs) 2 cycles (0.5 µs) 3.5 cycles (0.875 µs) SSC value + 1 SSC value + 1 SSC value –1 Setup time Hold time BB flag set/ reset time SSC value + 1 cycle (6.25 µs) cycle < 4.0 µs (3.125 µs) cycle < 4.0 µs (3.125 µs) + 2 cycles (3.375 µs) I2C status register write signal /LiteDiagLines/LiteDiagLines/LiteDiagLines Hold timeSetup time SCL SDA I2C status register write signal /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Hold timeSetup time SCL SDA /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Hold timeSetup time SCL SDA BB flag /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines SCL release time BB flag set time /LiteDiagLines/LiteDiagLines/LiteDiagLines Hold timeSetup time SCL SDA BB flag /LiteDiagLines/LiteDiagLines/LiteDiagLines SCL release time BB flag reset time

Rev.1.01 Aug 02, 2004 page 30 of 96 [I2C START/STOP Condition Control Register (S2D)] 003016 The I2C START/STOP condition control register (address 003016) controls START/STOP condition detection.

• Bits 0 to 4: START/STOP condition set bits (SSC4–SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(X IN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 9. Do not set “00000 2” or an odd number to the START/STOP condi- tion set bit (SSC4 to SSC0). Refer to Table 9, the recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency. Fig. 34 Structure of I 2C START/STOP condition control register
• Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin.
• Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin.
• Bit 7: STP/Low speed mode data receive enable bit Selecting this bit “1” enables I 2C to receive the start condition ad- dress data even if the CPU is stopping or running at the low speed mode. The detecting the falling edge of the SDA pin, RC on-chip oscillator begins oscillation, and receive the start condition ad- dress data. After receiving the last bit of address data ( in case of ACK clock bit =“1”, after receiving ACK bit), SCL/SDA interrupt and I 2C interrupt are requested at the same time. And then SCL pin becomes low hold state as a result of becoming SCL pin low hold bit “0”. During this state, it is possible to start the Xin oscilla- tion. And after oscillation becomes stable, normal I 2C operation begins. If the start condition which is not satisfied the hold time of start condition is input, SCL/SDA interrupt is requested. Note: When changing the setting of the SCL/SDA interrupt pin polarity se- lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the inter- rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I 2C-BUS interface enable bit ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt. START/STOP condition control register Oscillation frequency f(XIN) (MHz) Note:Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0). Table 9 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency Main clock divide ratio System clock φ (MHz) SCL release time (µs) Setup time (µs) Hold time (µs) XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 3.375 µs (13.5 cycles) 3.125 µs (12.5 cycles) 2.5 µs (2.5 cycles) 3.25 µs (6.5 cycles) 2.75 µs (5.5 cycles) 2.5 µs (2.5 cycles) 6.75 µs (27 cycles) 6.25 µs (25 cycles) 5.0 µs (5 cycles) 6.5 µs (13 cycles) 5.5 µs (11 cycles) 5.0 µs (5 cycles) 3.375 µs (13.5 cycles) 3.125 µs (12.5 cycles) 2.5 µs (2.5 cycles) 3.25 µs (6.5 cycles) 2.75 µs (5.5 cycles) 2.5 µs (2.5 cycles) b7 b0 I2C START/STOP condition control register START/STOP condition set bit SCL/SDA interrupt pin polarity selection bit 0 : Falling edge active 1 : Rising edge active SCL/SDA interrupt pin selection bit 0 : SDA valid 1 : SCL valid STP/Low speed mode data receive enable bit 0 : disable 1 : enable SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 (S2D : address 003016)

Rev.1.01 Aug 02, 2004 page 31 of 96 I2C additional function register (1) bit 0: Time-out mode bit (TOM) Setting the time-out mode bit “1” , continuity of I2C-Bus busy state for about 125 ms (XIN = 8 MHz) makes time-out flag “1” and time-out interrupt. Restart condition resets the time-out timer. (2) bit 1: Time-out flag (TOF) Time-out flag becomes “1” when the time-out state occurs. Writing “1” to this bit, time-out timer is reset, and this bit is cleared “0” also. (3) bit 2: SM-Bus interface pin input threshold select bit (TIS2) The SM-Bus interface pin input threshold is selected by this bit. Setting this bit “0”, the SM-Bus interface pin input threshold is for SM-Bus Ver1.0 specification, and setting this bit “1”, it is for SM-Bus Ver1.1 specification. (4) Stop condition flag (SCF) This flag turns to “1”, when the stop condition is generated or detected. This bit is cleared “0” at reset, or when I 2C-Bus inter- face enable bit is “0” or writing this bit “1”. This bit is available when I2C-Bus interface enable bit is “1”. Fig. 35 I2C additional function register b7 b0 I2C additional function register Time-out mode bit (TOM) 0 : disable 1 : enable Time-out flag (TOF) 0 : Not generated 1 : Generated *Writing this bit “1”, this flag is cleared to “0”. SM-Bus interface pin input threshold select bit (TIS2) 0 : Ver1.0 (V IL=0.6V,VIH=1.4V) 1 : Ver1.1 (VIL=0.8V,VIH=2.1V) Stop condition flag (SCF) 0 : Not detect stop condition 1 : Detect stop condition *Writing this bit “1”, this flag is cleared to “0”. Not used (returns “0” when read) (S3 : address 003116)

Rev.1.01 Aug 02, 2004 page 32 of 96 Fig. 36 Address data communication format Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. (1)7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I 2C control register (address 002E16) to “0”. The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 002C16). At the time of this comparison, address com- parison of the RWB bit of the I2C address register (address 002C 16) is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 36, (1) and (2). (2)10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 002E16) to “1”. An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I 2C address register (address 002C16). At the time of this comparison, an address comparison between the RWB bit of the I2C address register (address 002C16) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is pro- cessed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I 2C status register (address 002D16) is set to “1”. After the second-byte address data is stored into the I2C data shift register (address 002B16), perform an address com- parison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I 2C address register (address 002C16) to “1” by software. This processing can make the 7-bit slave address and R/W data agree, which are re- ceived after a RESTART condition is detected, with the value of the I 2C address register (address 002C16). For the data trans- mission format when the 10-bit addressing format is selected, refer to Figure 36, (3) and (4). S Slave addressR/W A Data A/A PA Data 7 bits “0” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transnmits data to a slave-receiver S Slave addressR/W A Data A PA Data 7 bits “1” 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter 7 bits “0” 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address 1 to 8 bits 1 to 8 bits S R/W ASlave address 1st 7 bits Slave address 2nd bytes AA Data Data PA/A 7 bits “0” 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit 7 bits “1” 1 to 8 bits 1 to 8 bits S R/W ASlave address 1st 7 bits Slave address 2nd bytes A Sr Slave address 1st 7 bits R/W AData Data PA /LiteDiagLines/LiteDiagLines : Master to slave : Slave to master /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines A

Rev.1.01 Aug 02, 2004 page 33 of 96 Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. (1) Set a slave address in the high-order 7 bits of the I2C address register (address 002C16) and “0” into the RWB bit. (2) Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 002F16). (3) Set “0016” in the I2C status register (address 002D16) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting “0816” in the I2C control register (address 002E16). (5) Confirm the bus free condition by the BB flag of the I2C status register (address 002D16). (6) Set the address data of the destination of transmission in the high-order 7 bits of the I2C data shift register (address 002B16) and set “0” in the least significant bit. (7) Set “F016” in the I2C status register (address 002D16) to gener- ate a START condition. At this time, a SCL for 1 byte and an ACK clock automatically occur. (8) Set transmit data in the I2C data shift register (address 002B 16). At this time, a SCL and an ACK clock automatically oc- cur. (9) When transmitting control data of more than 1 byte, repeat step (8). (10) Set “D0 16” in the I2C status register (address 002D16) to gen- erate a STOP condition if ACK is not returned from slave reception side or transmission ends. Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. (1) Set a slave address in the high-order 7 bits of the I 2C address register (address 002C16) and “0” in the RWB bit. (2) Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 002F16). (3) Set “0016” in the I2C status register (address 002D16) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting “0816” in the I2C control register (address 002E16). (5) When a START condition is received, an address comparison is performed. (6) •When all transmitted addresses are “0” (general call): AD0 of the I2C status register (address 002D16) is set to “1” and an interrupt request signal occurs.

• When the transmitted addresses agree with the address set in (1): ASS of the I2C status register (address 002D16) is set to “1” and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C status register (address 002D16) are set to “0” and no inter rupt request signal occurs. (7) Set dummy data in the I2C data shift register (address 002B16). (8) When receiving control data of more than 1 byte, repeat step (7). (9) When a STOP condition is detected, the communication ends.

Rev.1.01 Aug 02, 2004 page 34 of 96 (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generat- ing procedure are described as the following 2 to 5. LDA — (Taking out of slave address value) SEI (Interrupt disabled) BBS 5, S1, BUSBUSY (BB flag confirming and branch process) BUSFREE: STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of START condition generating) CLI (Interrupt enabled) BUSBUSY: CLI (Interrupt enabled) 2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag confirming and branch process. 3. Use “STA $2B, STX $2B” or “STY $2B ” of the zero page ad- dressing instruction for writing the slave address value to the I 2C data shift register. 4. Execute the branch instruction of above 2 and the store instruc- tion of above 3 continuously shown the above procedure example. 5. Disable interrupts during the following three process steps:

• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions of the generat- ing procedure are described as the following 2 to 4.) Execute the following procedure when the PIN bit is “0”. LDM #$00, S1 (Select slave receive mode) LDA — (Taking out of slave address value) SEI (Interrupt disabled) STA S0 (Writing of slave address value) LDM #$F0, S1 ( Trigger of RESTART condition generating) CLI (Interrupt enabled) 2. Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I 2C data shift register. 4. Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating (4) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simulta- neously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. It is because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I 2C data shift register S0 and the I2C sta- tus register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem. I Precautions when using multi-master I2C-BUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I 2C-BUS interface are described below.
• I2C data shift register (S0: address 002B16) When executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended.
• I2C address register (S0D: address 002C16) When the read-modify-write instruction is executed for this regis- ter at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing.
• I 2C status register (S1: address 002D16) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W.
• I 2C control register (S1D: address 002E16) When the read-modify-write instruction is executed for this regis- ter at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing.
• I 2C clock control register (S2: address 002F16) The read-modify-write instruction can be executed for this regis- ter.
• I 2C START/STOP condition control register (S2D: address 003016) The read-modify-write instruction can be executed for this regis- ter.

Rev.1.01 Aug 02, 2004 page 35 of 96 PULSE WIDTH MODULATION (PWM) The 7517 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input di- vided by 2. Data Setting The PWM output pin also functions as port P44. Set the PWM pe- riod by the PWM prescaler, and set the “H ” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(X IN) (when f(XIN) = 8 MHz, count source is f(XIN) ) Output pulse “H ” term = PWM period ✕ m / 255 (when f(XIN) = 8 MHz, count source is f(XIN)) Fig. 37 Timing of PWM period Fig. 38 Block diagram of PWM function PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H ”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. 31.875 ✕ m ✕ (n+1) 255 PWM output m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(X IN) = 8 MHz, count source is f(XIN)) µs µs Data bus Count source selection bit “0” “1” PWM prescaler pre-latch PWM register pre-latch PWM prescaler latch PWM register latch Transfer control circuit PWM register XIN Port P44 latch PWM enable bit Port P44 PWM prescaler

Rev.1.01 Aug 02, 2004 page 36 of 96 Fig. 39 Structure of PWM control register Fig. 40 PWM output timing when PWM register or PWM prescaler is changed I Note The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows: sec (Count source selection bit = 0, where n is the value set in the prescaler) sec (Count source selection bit = 1, where n is the value set in the prescaler) n+1 2 • f(X IN) n+1 f(XIN) PWM control register (PWMCON : address 001D16) PWM function enable bit Count source selection bit Not used (return “0” when read) b7 b0 0: PWM disabled 1: PWM enabled 0: f(XIN) 1: f(XIN)/2 AB C B T C T2= PWM output PWM register write signal PWM prescaler write signal (Changes “H ” term from “A” to “B”.) (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. T T T2

Rev.1.01 Aug 02, 2004 page 37 of 96 [A/D Conversion Registers (ADL, ADH)] 0035 16, 003616 The A/D conversion registers are read-only registers that store the result of an A/D conversion. Do not read these registers during an A/D conversion [AD Control Register (ADCON)] 003416 The AD control register controls the A/D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A/D conversion. The value of this bit remains at “0” during an A/D conversion and changes to “1” when an A/D con- version ends. Writing “0” to this bit starts the A/D conversion. Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS and VREF into 1024 and outputs the divided voltages. Channel Selector The channel selector selects one of ports P04/AN8 to P07/AN11 and ports P30/AN0 to P35/AN5 and inputs the voltage to the com- parator. Comparator and Control Circuit The comparator and control circuit compare an analog input volt- age with the comparison voltage, and the result is stored in the A/ D conversion registers. When an A/D conversion is completed, the control circuit sets the A/D conversion completion bit and the A/D interrupt request bit to “1”. Note that because the comparator consists of a capacitor cou- pling, set f(X IN) to 500 kHz or more during an A/D conversion. When the A/D converter is operated at low-speed mode, f(XIN) and f(XCIN) do not have the lower limit of frequency, because of the A/D converter has a built-in self-oscillation circuit. Fig. 41 Structure of AD control register Fig. 42 Structure of A/D conversion registers Fig. 43 Block diagram of A/D converter AD control register (ADCON : address 003416) Analog in additional bit* Analog input pin selection bits 0 0 0 0: P3 0/AN0 0 0 0 1: P3 1/AN1 0 0 1 0: P3 2/AN2 0 0 1 1: P3 3/AN3 0 1 0 0: P3 4/AN4 0 1 0 1: P3 5/AN5 1 0 0 0: P0 4/AN8 1 0 0 1: P0 5/AN9 1 0 1 0: P0 6/AN10 1 0 1 1: P0 7/AN11 Not used (returns “0” when read) A/D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read) *Bit 0 of MISRG2 (0037 16) b7 b0 10-bit reading (Read address 003616 before 003516) (Address 003616) (Address 003516) 8-bit reading (Read only address 003516) (Address 003516) b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b7 b0 Note : The high-order 6 bits of address 003616 become “0” at reading. b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 Channel selector A/D control circuit A/D conversion low-order register Resistor ladder VREF AV SS Comparator A/D interrupt request b7 b0 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 Data bus AD control register (Address 003416) A/D conversion high-order register(Address 003616) (Address 003516) P35/AN5 P04/AN8 P05/AN9 Analog input pin selection additional bit P06/AN10 P07/AN11

Rev.1.01 Aug 02, 2004 page 38 of 96 Fig. 44 Block diagram of Current integrator Current Integrator Current integrator integrates the current which flows through sense resistor (10 mΩ ) connected between ISENS0 pin and ISENS1 pin. The current between sense resistor makes electrical potential difference between ISENS0 pin and ISENS1 pin, and it is integrated by the built-in integrator. The output of integrator is con- nected to comparator, and the integrator and comparator measures about 1 mA current. Setting the current integrate enable bit “1”, the current integrator starts the operation. Current integrate mode Setting the current integrate mode bit “0”, input of the level shift circuit is connected to the ISENS1 pin and ISENS0 pin, and the current integrator measures the electrical potential difference be- tween ISENS1 pin and ISENS0 pin. Each electrical potential of the ISENS1 pin and ISENS0 pin is added AV CC /2 by level shift circuit, and then output of the level shift circuit is input to integrator. This makes enable to minus level input to ISENS1 pin, and the current integrator can measure both polarity current. The output of the integrator is connected to the comparator. The integrator integrates input voltage between ISENS1 pin and ISENS0 pin. And when output of the integrator amounts to com- pared voltage, output of the comparator rises “H ”, and charge (discharge) counter is increased 1 count. And at the same time, electric charge of the integrator’s capacitor is discharged, then the integrator starts next integration. Charge (Discharge) counter is counting the number of the times “H ” output of the comparator during integration period (125 ms), and at the end of the period, charge (discharge) counter is latched onto charge (discharge) counter latch. Then charge (discharge) counter is cleared “0”, and starts new count. At the end of the period, current integrate inter- rupt occurs also. The current integrator has 2 set of comparator and counter for dis- charge and charge, and only discharge counter counts up in discharge state, and only charge counter counts up in charge state. The integrator and comparator are designed to sense ap- proximate 1 mA current, then 1 count of counter means approximate 1 mA Therefore reading the value of counter latch means measuring the total current which flows the sense resistor during integrate period (125 ms). The calibration integrates the current of the period selected by the calibration period selection bits, after discharging the electric charge accumulated in the capacitor of the integrator. Level shift circuit XX0 001 011 101 XX0 001 011 101 ISENS0 ISENS110m Ω b2 b1 b0 Current integrate control register XX0 : Current integrate mode 001 : Zero calibration 011 : Full calibration for discharge 101 : Full calibration for charge Calibration control signal AD conversion complete signalEdge detect XCIN 125 ms Timer 125 ms over flow Calibration control signalCalibration control circuit Charge counter Charge counter latch Discharge counter Discharge counter latch Current integrate interrupt Calibration control signal AD conversion complete signal Data Bus 10bit AD ANi 0.1V

Rev.1.01 Aug 02, 2004 page 39 of 96 Fig. 45 Current integrator timing diagram Level shift circuit output ISENS1 input Charge counter Charge counter latch Discharge counter 1.65V Integrate period 125 ms Integrate period 125 ms Count value of last integrate period Count value of last integrate period m m n 1 2 3 1 2 30nn-1n-2n-3n-4n-5n-6 2.45V 1.65V 0.85V Discharge counter latch Integrator output Discharge comparator Charge comparator Level shift circuit output ISENS1 input Discharge counter Integrator output Discharge comparator Discharge signal for integrator 2.45V 1.65V 0.8V n-3 n-2 n-1

Rev.1.01 Aug 02, 2004 page 40 of 96 Fig. 46 Calibration timing Calibration mode Setting the current integrate mode bit “1”, the input of level shift circuit is connected to internal AVSS or 0.1V for reference voltage. When the calibration selection bit is “00”, both of plus and GND in- put of level shift circuit are connected to internal AVSS , and zero calibration is operated. When the calibration selection bit is “01”, plus input of level shift circuit is connected to internal 0.1V refer- ence voltage, and GND input of level shift circuit is connected to internal AVSS , and then full calibration for discharge state is op- erated. When the calibration selection bit is “10”, plus input of level shift circuit is connected to internal AVSS , and GND input of level shift circuit is connected to 0.1V reference voltage, and the full calibration for charge state is operated. The calibration pe- riod can be selected by calibration period selection bit among at beginning of next integrate period, after setting the current in- tegrate mode bit “1”. 012 3 Integrate period 125 ms Calibration 15.625 ms -125 ms VINF input Current integrate mode bit Counter latch content flag Level shift circuit out put Integrator output Discharge comparator Discharge counter Discharge counter latch AD conversion mode bit Discharge comparator Discharge signal for integrator AD conversion completion bit Integrator output Set calibration complete flag to “1”. Integrate period 125 ms Integrate period 125 ms Current integrate mode Integrate period 125ms Calibration 15.625 ms -125 ms Integrate period 125ms AD conversion execute Count value of last integrate period 3 (Calibration result) Count value of last integrate period * * Except calibration period

Rev.1.01 Aug 02, 2004 page 41 of 96 Fig. 47 Current integrator registers The calibration starts current integration for period selected cali- bration period selection bit, after discharging electric charge which remain in integrator's capacitor. After finished calibration period, value of the discharge (charge) counter is latched to discharge (charge) counter latch, then current integrate mode bit is cleared “0”, and current integrate mode is switched to current integrate mode from calibration mode automatically. At this time the current integrate interrupt occurs. Which interrupt has occurred current in- tegrate interrupt for current integrate mode or for calibration mode can be judged by reading the counter latch content flag. The counter latch content flag shows the contents of counter latch, value for current integrate mode or value for calibration mode. Note that the contents of the counter latch is updated automati- cally at the end of next current integration or calibration. I Notes on calibration mode

• After enabling the current integrator, a first-time integrate period cannot be operated in the calibration mode.
• Do not change the value of the calibration selection bit and the calibration period selection bits during operation in the calibration mode.
• When calibration time is set as 125 ms, next current period which the calibration is completed cannot be operated in the calibration mode.
• After the current integrator is set to the calibration mode, do not disable the current integrator until the current period in the calibra- tion mode is completed. When current integration is disabled before the current period completion in the calibration mode after setting “1” to the current integrate mode bit, the current period of the first time which re-per- mitted current integration may operate in the calibration mode regardless of the setting of the current integrate mode bit. AD conversion connection mode Setting the AD conversion connection bit to “1”, AD converter comes to convert the electric charge remained in the integrator ca- pacitor at the end of current integrate or calibration period. This makes a fraction of a count possible to measure. When AD con- version connection bit is “1”, input of AD converter is connected automatically to the output of the integrator just after the end of the current integrate or calibration period, and AD conversion starts. The current integrate interrupt occurs at the end of the AD conversion. Then remained electric charge in the integrator ca- pacitor is discharged, and new current integration starts. After AD conversion completes, the input of the AD conversion is automati- cally returned previous state. Discharge counter latch low-order register (000A16) b7 b0 b7 b0 b7 b0 b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 b7 b0 Discharge counter latch high-order register (000B16) Charge counter latch low-order register (000C16) Charge counter latch high-order register (000D16) Current integrate control register (000E16) Current integrate mode bit 0 : Current integrate mode 1 : Calibration mode Calibration selection bits 00 : Zero calibration 01 : Full calibration for discharge 10 : Full calibration for charge 11 : Not used AD conversion connection bit 0 : Not connect 1 : Connect Calibration period selection bits 00 : 15.625ms 01 : 31.25ms 10 : 62.5ms 11 : 125ms Counter latch contents flag 0 : Current integrate data 1 : Calibration data Current integrate enable bit 0 : Disable 1 : Enable

Rev.1.01 Aug 02, 2004 page 42 of 96 Notes on current integrator When changing current integration into prohibition from permis- sion, incorrect interrupt may occur. Perform any one of the following by software as the measure. (1) How to control timing which disable current integrator

• When changing current integration to prohibition in the current in- tegrate mode, change the setting during “H ” of the clock signal which operates in a cycle of 125 ms.
• When changing current integration to prohibition in the calibration mode, change the setting during “H ” of the clock signal operated by cycle which is set by the calibration period selection bits. Table 10 shows the how to distinguish “H ” period of each clock signal. (2) How to invalidate interrupt after prohibition setup of current in- tegrator After changing current integration to prohibition, wait for about 61.0 ms, and then set the request flag to “0”. (3) How to check truth of interrupt request
• Check the current integrate enable bit during the current integra- tor interrupt routine. When disabling the current integrator, skip the interrupt processing. Notes on AD conversion connection mode
• When the AD conversion of the current integrator is performed, do not execute other AD conversion.
• When using the AD conversion connection mode at the time of calibration completion, do not set the AD conversion connection bit to “1” before calibration starts.
• The count value immediately after AD conversion completion of the current integrator may be incorrect. Only when the count value immediately after the AD conversion completion, such as initial proofreading etc, is unnecessary, use the AD conversion connection mode.
• The current integrator starts current integration in the low-speed clock 1-2 cycles, after setting the current integrate enable bit to “1”. After setting the current integrate enable bit to “0”, initializa- tion of 1-2 cycle period of a low-speed clock and an internal circuit is performed. Do not enable the current integrator again in this period.
• After the current integrate enable bit is set to “1”, current integra- tion starts with a delay of 1 to 2 cycles of a low-speed clock. As for the period for 1 to 2 cycle of the low-speed clock immediately after setting the current integrate enable bit to “0”, the internal cir- cuit is initialized. Do not enable the current integrator again in this period. Table 10 Mode switch timing Current integrate mode Calibration mode 12.5 ms setting 15.26 ms setting 31.25 ms setting 62.5 ms setting Mode switch timing Period for about 62.5 ms after interrupt occurrence of last integrate period Period for about 31.25 ms after interrupt occurrence of last integrate period Period for about 15.625 ms after interrupt occurrence of last integrate period Period for about 7.8127 ms after interrupt occurrence of last integrate period

Rev.1.01 Aug 02, 2004 page 43 of 96 Over current detector detects the over current which flows through the sense resistor connected between ISENS1 pin and ISENS0 pin, and turn off the discharge control FET to stop battery from dis- charging. In the low power state, and when current integrator disables, wake up current detector which detects approximate 1 mA current and generates the interrupt is also built-in. Short current detector Short current detector detects the short current (10A-47.5A) with 10 mΩ sense resistor. Setting short current detect enable bit of the short current detect control register (000F16) “1”, short current de- tector starts the operation. The compare voltage is determined by setting the short current detect voltage select bit of the short cur- rent detect control register, and the detect time is determined by setting the short current detect time set up bit of the current detect time set up register (0011 16). The potential difference between sense resistor exceeds the com- pare voltage and continue more than detect time, then short current detect flag (bit 2 of 001316) becomes “1”, and short current detect interrupt occurs. Enabling interrupt for short current detect is determined by short current interrupt enable bit. And in case of the FET control enable bit is “1”, The FET control signal is generated from DFETCNT pin with short current interrupt. The polarity of the FET control signal is determined by setting the FET control polarity switch bit (bit 5 of 000F 16). Setting the short current detect restart bit(bit 6 of 001316) “1” makes the short current detect state clear. Over current detector Over current detector detects the over current (5A-20.5A) with 10 m Ω sense resistor. Setting over current detect enable bit of the over current detect control register (001016) “1”, over current de- tector starts the operation. The compare voltage is determined by setting the over current detect voltage select bit of the over current detect control register (001016), and the detect time is determined by setting the over current detect time set up bit of the current de- tect time set up register (001016) The potential difference between sense resistor exceeds the com- pare voltage and continue more than detect time, then over current detect flag (bit 1 of 0013 16) becomes “1”, and over current detect interrupt occurs. Enabling interrupt for over current detect is determined by over current interrupt enable bit. And in case of the FET control enable bit is “1”, the FET control signal is generated from DFETCNT pin with over current interrupt. Setting the over current detect restart bit (bit 5 of 0013 16) “1” makes the over current detect state clear. Wake up current detector Wake up current detector detects approximate 1A current with 10mW sense resistor. Setting wake up current detect enable bit of the wake up current detect control register 1(0012 16) “1”, wake up current detector starts the operation. The sensing voltage is 10 times amplified and compared by the comparator. The comparator is comparing every 3.9 msec, and more than 1A current is keeping for about 62 msec, wake up current detect flag (bit 0 of 0013 16) becomes “1”, and the wake up current detect interrupt occurs. The enabling interrupt for wake up current detect is determined by wake up current detect interrupt enable bit(bit6 of 0012 16). Setting the wake up current detect restart bit “1” makes the wake up cur- rent detect state clear. The ofset calibration of the amplifier and comparator is able to be adjusted by setting the wake up current compare voltage select bit. Setting the wake up current detect calibration enable bit (bit 5 of 0014 16) “1”, calibration mode starts. In the calibration mode, in- put of level shift circuit is connected to internal GND, and it is possible to measure the comparator threshold voltage at 0 V input state, with setting wake up current detect compare voltage select bit. Then set the wake up current detect compare voltage select bit the value which is added comparator threshold voltage at 0 V state and 0.1V (1A worth voltage). SFR protect control register SFR protect control register (002916) protects SFR from changing the contents easily cause of like microcomputer runs away. When the bit of SFR protect control register is “0”, corresponded bit register is protected. In case of writing to the protected register, write “1” to the corresponded bit of protect register, then write the protected register in succession. If other register is written, the contents of SFR protect register is cleared “00”.

Rev.1.01 Aug 02, 2004 page 44 of 96 Fig. 48 Block diagram of Over current detector AV CC X10 S R Q S R Q S R Q Over current detect interrupt XCIN/128 FET ISENS1 Wake up calibration enable bit Level shift circuit Wake up current detect time counter Over current detect time counter Short current detect time counter Current detect time set up resister Over current detect status register FET control enable bit (when short current detect enable) FET control enable bit (when over current detect enable) FET control polarity switch bit Level shift circuit Short current detect voltage select bit Over current detect voltage select bit Wake up current detect voltage select bit

Rev.1.01 Aug 02, 2004 page 45 of 96 Fig. 49 Over current detector registers (1) Short current detect control register protect bit (000F16) 0 : Write disable 1 : Write enable Over current detect control register protect bit (0010 16) 0 : Write disable 1 : Write enable Current detect time set up register protect bit (0011 16) 0 : Write disable 1 : Write enable Wake up current detect control register 1 protect bit (0012 16) 0 : Write disable 1 : Write enable Over current detect status register protect bit (0013 16) 0 : Write disable 1 : Write enable Wake up current detect control register 2 protect bit (0014 16) 0 : Write disable 1 : Write enable MISRG2 protect bit (0037) 0 : Write disable 1 : Write enable CPU mode register protect bit (003B) 0 : Write disable 1 : Write enable SFR protect control register (002916) PRCR b0 b7 Short current detect control register protect bit (000F16) Short current detect voltage select bits 0000 : 0.100V 1000 : 0.300V 0001 : 0.125V 1001 : 0.325V 0010 : 0.150V 1010 : 0.350V 0011 : 0.175V 1011 : 0.375V 0100 : 0.200V 1100 : 0.400V 0101 : 0.225V 1101 : 0.425V 0110 : 0.250V 1110 : 0.450V 0111 : 0.275V 1111 : 0.475V Short current detect interrupt enable bit 0 : Disable 1 : Enable FETcontrol polarity switch bit 0 : active "L" output 1 : active "H" output FETcontrol enable bit (When short current detect enable) 0 : FET control disable 1 : FET control enable Short current detect enable bit 0 : Disable 1 : Enable Over current detect control register (001016) Short current detect voltage select bits 00000 : 0.050V 10000 : 0.130V 00001 : 0.055V 10001 : 0.135V 00010 : 0.060V 10010 : 0.140V 00011 : 0.065V 10011 : 0.145V 00100 : 0.070V 10100 : 0.150V 00101 : 0.075V 10101 : 0.155V 00110 : 0.080V 10110 : 0.160V 00111 : 0.085V 10111 : 0.165V 01000 : 0.090V 11000 : 0.170V 01001 : 0.095V 11001 : 0.175V 01010 : 0.100V 11010 : 0.180V 01011 : 0.105V 11011 : 0.185V 01100 : 0.110V 11100 : 0.190V 01101 : 0.115V 11101 : 0.195V 01110 : 0.120V 11110 : 0.200V 01111 : 0.125V 11111 : 0.205V Over current detect interrupt enable bit 0 : Disable 1 : Enable FETcontrol enable bit (When over current detect enable) 0 : FET control disable 1 : FET control enable Over current detect enable bit 0 : Disable 1 : Enable Note : Same bits in this register are not protected. Note : All bits are protected. Note : All bits are protected.

Rev.1.01 Aug 02, 2004 page 46 of 96 Fig. 50 Over current detector registers (2) Current detect time set up register (001116) Short current detect time set up bits 0000 : 0 µs 1000 : 488 µs 0001 : 61 µs 1001 : 549 µs 0010 : 122 µs 1010 : 610 µs 0011 : 183 µs 1011 : 671 µs 0100 : 244 µs 1100 : 732 µs 0101 : 305 µs 1101 : 793 µs 0110 : 366 µs 1110 : 854 µs 0111 : 427 µs 1111 : 915 µs Over current detect time set up bits 0000 : 1.0ms 1000 : 17.0ms 0001 : 3.0ms 1001 : 19.0ms 0010 : 5.0ms 1010 : 21.0ms 0011 : 7.0ms 1011 : 23.0ms 0100 : 9.0ms 1100 : 25.0ms 0101 : 11.0ms 1101 : 27.0ms 0110 : 13.0ms 1110 : 29.0ms 0111 : 15.0ms 1111 : 31.0ms Wake up current detect flag 0 : Not detected 1 : Detected Over current detect flag 0 : Not detected 1 : Detected Over current detect flag 0 : Not detected 1 : Detected Not used (returns "0" when read) Wake up current detect restart bit 0 : Invalid 1 : Restart Over current detect restart bit 0 : Invalid 1 : Restart Short current detect restart bit 0 : Invalid 1 : Restart Not used (returns "0" when read) Over current detect status register(001316) Wake up current detect control register 1 (001216) Wake up current detect compare voltage select bits Wake up current detect interrupt enable bit 0 : Disable 1 : Enable Wake up current detect enable bit 0 : Disable 1 : Enable Wake up current detect control register 2 (0014 16) Reserved (Do not write "1"to this bit) Wake up calibration enable bit 0 : Disable 1 : Enable Not used (returns "0" when read) b5 b4 b3 b2 b1 b0 0 0 X X X X Setting disabled 01000 0 1 . 4 4 01000 1 1 . 4 5 01001 0 1 . 4 6 01001 1 1 . 4 7 0.01n+1.28 11110 0 1 . 8 7 11110 1 1 . 8 9 11111 0 1 . 9 0 11111 1 1 . 9 1 Wake up current detect compare voltage select bits ncompare voltage (V) Note : All bits are protected. Note : All bits are protected. Note : All bits are protected. Note : All bits are protected.

Rev.1.01 Aug 02, 2004 page 47 of 96 The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Standard Operation of Watchdog Timer When any data is not written into the watchdog timer control reg- ister (address 0039 16) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16) and an internal reset occurs at an underflow of the watch- dog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16) may be started before an underflow. When the watchdog timer control reg- ister (address 0039 16) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watch- dog timer H count source selection bit are read. G Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L is set to “FF16”. Fig. 52 Structure of Watchdog timer control register G Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) per- mits selecting a watchdog timer H count source. When this bit is set to “0”, the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(XIN) = 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to “1”, the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to “0” after resetting. G Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) per- mits disabling the STP instruction when the watchdog timer is in operation. When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to “1”, it cannot be rewritten to “0” by program. This bit is cleared to “0” after resetting. Fig. 51 Block diagram of Watchdog timer XIN Data bus XCIN “10” “00” “01” Main clock division ratio selection bits (Note) “0” “1”1/16 Watchdog timer H count source selection bit Reset circuit STP instruction disable bit Watchdog timer H (8) “FF16” is set when watchdog timer control register is written to. Internal resetRESET Watchdog timer L (8) Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. STP instruction “FF16” is set when watchdog timer control register is written to. STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(X IN)/16 or f(XCIN)/16 Watchdog timer H (for read-out of high-order 6 bit) Watchdog timer control register (WDTCON : address 003916)

Rev.1.01 Aug 02, 2004 page 48 of 96 To reset the microcomputer, RESET pin must be held at an “L” level for 20 XIN cycles or more. Then the RESET pin is returned to an “H ” level (the power source voltage must be between 2.7 V and 3.6 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address con- tained in address FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for V CC of 2.7 V. Fig. 54 Reset sequence Fig. 53 Reset circuit example (Note) 0.2VCC Poweron VCCRESET VCCRESET Power source voltage detection circuit Power source voltage Reset input voltage Note : Reset release voltage ; Vcc=2.7 V RESET Data φ Address SYNC XIN: 8 to 13 clock cycles XIN ? ? ?? ? FFFC FFFD AD H ,L 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals. Reset address from the vector table. Notes RESET OUT

Rev.1.01 Aug 02, 2004 page 49 of 96 Fig. 55 Internal status at reset Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Port P4 direction register (P4D) Discharge counter latch low-order register (DCHARGEL) Discharge counter latch high-order register (DCHARGEH) Charge counter latch low-order register (CHARGEL) Charge counter latch high-order register (CHARGEH) Current integrato14r control register (CINFCON) Short current detector control register (SCDCON) Over current detector control register (OCDCON) Current detect time set up register (OCDTIME) Wake up current detector control register 1 (WDDCON1) Over current detect status register (OCDSTS) Wake up current detector cuntrol register 2 (WDDCON2) Serial I/O2 control register 1 (SI02CON1) Serial I/O2 control register 2 (SI02CON2) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) PWM control register (PWMCON) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) Note : X indicates Not fixed . Address Register contents 0001 000316 000516 000716 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001916 001A16 001B16 001D 16 002016 002116 002216 002316 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 0116 0016 0016 Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source select register (TCSS) SFR protect control register (PRREG) I 2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) I2C start/stop condition control register (S2D) I2C additional function register (S3) 32kHz oscillation circuit control register 0 (32KOSCC0) 32kHz oscillation circuit control register 1 (32KOSCC1) AD control register (ADCON) MISRG2 MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Processor status register Program counter (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) Address Register contents 0024 002516 002616 002716 002816 002916 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 (PS) (PCH ) (PCL) FF16 FF16 FF16 FF16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 000 0 0111 10000000 11100000 0001 000 011000 0 XXXXXXX 00111111 FFFD 16 contents FFFC 16 contents X

000 X X X X X

Rev.1.01 Aug 02, 2004 page 50 of 96 The 7517 group has four built-in oscillation circuits: high-speed on-chip oscillation circuit, an oscillation circuit can be formed by connecting a resonator between XIN and XOUT , resonator between XCIN and XCOUT, and a 32 kHz RC oscillation circuit can be formed by connecting capacitor and resistor. The oscillation source (high- speed on-chip oscillation or X IN-XOUT oscillation) can be controlled by setting the clock source switch bit (CPU mode regis- ter) and high-speed on-chip oscillation stop bit (MISRG2) and XIN switching inhibit bit (MISRG2). Immediately after power on, only the high-speed on-chip oscillation circuit starts oscillation. In case of using X IN-XOUT oscillation circuit, change the clock source switch bit after start the XIN-XOUT oscillation setting the main clock (XIN-XOUT ) stop bit (CPU mode register). When not using XIN-XOUT oscillation circuit, XIN pin and XOUT pin must be open. Setting the X IN switching inhibit bit “1” (disable switch to XIN), the clock source switch bit become invalid, and XIN-XOUT oscillation circuit becomes disabled since. When this bit is set to “1”, it can- not be rewritten to “0” by program. Setting the port Xc switch bit (CPU mode register) “1”, 32 kHz RC oscillation circuit or XCIN-XCOUT oscillation circuit starts oscilla- tion. The selection of 32 kHz RC oscillation circuit or XcIN-XCOUT oscillation circuit is selected by 32 kHz RC oscillation enable bit (MISRG2). In case of using external resonator, connect resonator to X IN pin and XOUT pin (XCIN pin and XCOUT pin). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT . Immediately after power on, XCIN and XCOUT pins function as I/O ports. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of high-speed on-chip oscilla- tion clock or XIN divided by 8. After reset, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of high-speed on-chip oscillation clock or XIN. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. I Note If you switch the mode between middle/high-speed and low- speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately af- ter power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(X IN) > 3•f(XCIN). (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN or high-speed on-chip oscillation in low-speed mode. To stop the main clock, set the main clock stop bit (bit 5 of CPU mode register) or the high-speed on-chip oscillation stop bit (bit 2 of MISRG2) to “1”. When the main clock X IN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscilla- tion to stabilize. The sub-clock X CIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. 32kHz RC oscillation circuit Setting the port Xc switch bit “1” after setting the 32 kHz RC oscil- lation enable bit “1”, the built-in 32 kHz RC oscillation circuit starts oscillation. In case of using 32 kHz RC oscillation circuit, connect 82 kΩ resistor between X CIN-XCOUT , and connect 120 pF capaci- tor between XCIN and GND. Setting appropriate value to the 32 kHz oscillation circuit control registers 0,1 it is possible to adjust the frequency error cause by evenness of resistor and capacitor value . The resistor ladder divided by 512 adjusts the frequency, and it makes possible about 50 Hz step adjustment. The theoretical frequency is calculated as follow. 32CR = 2CRln(1+2R1/R2)

Rev.1.01 Aug 02, 2004 page 51 of 96 82 kΩ120 pF 71.68 kΩ35.84 Ω 70 Ω ✕ 512 resistor ladder Vcc (1.65V) XCIN XCOUT R 1 R 2 C R 32 kHz oscillation circuit control registers 0,1 clock control circuit comparator Fig. 56 32 kHz RC oscillation circuit block diagram

Rev.1.01 Aug 02, 2004 page 52 of 96 Fig. 57 Ceramic resonator circuit Fig. 58 External clock input circuit Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H ” level, and high-speed on-chip oscillation clock or XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is “0”, the prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the oscillation stabilizing time set after STP instruction released bit is “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either high-speed on-chip oscillation clock, or X IN or XCIN divided by 16 is input to the prescaler 12 as count source. Oscillator re- starts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H ”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation us- ing the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscil- lation is stable since a wait time will not be generated. In case of using high-speed on-chip oscillation clock as main clock, the oscillation stabilizing time does not almost need. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H ” level, but the oscillator does not stop. The internal clock φ re- starts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before ex- ecuting of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the high-speed on-chip oscillation clock or X IN di- vided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruction. I Note When using XIN-XOUT oscillation by using an external resonator, in case of using the oscillation stabilizing time set after STP instruc- tion released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. Fig.59 On-chip oscillation circuit and 32kHz CR oscillation circuit XCIN XCOUT XIN XOUT C IN C OUTC CIN C COUT Rf Rd XCIN XCOUT XIN XOUT C CIN C COUT Rf Rd Open External oscillation circuit Vcc Vss XIN XOUTXCIN XCOUT 82kΩ 120pF Open Open

Rev.1.01 Aug 02, 2004 page 53 of 96 Fig. 60 System clock generating circuit block diagram (Single-chip mode) WIT instruction STP instructionSTP instruction S R Q S R QS R Q XCOUTXCIN Interrupt request Reset Interrupt disable flag l 1/2 1/4 1/2 Port XC switch bit“1” “0” XIN XOUT High-speed or middle-speed mode Main clock division ratio selection bit (Note 1) Note: Any one of high-speed mode, middle-speed mode or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. Timing φ (Internal clock) Main clock stop bit High-speed or low-speed mode Main clock division ratio selection bits (Note 1) Prescaler 12 Timer 1 Middle-speed mode Low-speed mode High-speed on-chip oscillation stop bit XIN switching inhibit bit Port XC switch bit Port XC switch bit Clock source switch bit Data bus 32kHZ RC oscillation enable bit High-speed on-chip oscillation circuit XIN-XOUT oscillation High-speed on-chip oscillation 32kHZ RC oscillation enable bit 32 kHZ oscillation control registers 0, 1

Rev.1.01 Aug 02, 2004 page 54 of 96 MISRG2(0037 16) Analog in addtional bit bit0 ADCON (0034 16) bit2 bit1 bit0

0 XXXP 3 5/AN5 - P30/AN0

32kHz RC oscillation calibration enable bit (Note 4) 0:Disabled 1:Enabled High-speed on-chip oscillation stop bit (Note 4) 0:Oscillating 1:Stopping Xin swith disable bit (Notes 3, 4) 0:Enable swith to X IN 1:Disable swith to XIN 32kHz RC oscillation enable bit (Note 4) 0:XCIN-XCOUT oscillation 1:32kHz RC oscillation Low-speed mode serial I/O2 clock source select bit 0:XCIN 1:Built-in oscillator for SI/O2 Not used (returnn"0" when read) Reserved (do not write "1") Notes 3: When this bit is set to "1", it cannot be rewritten to "0" by program. 4: This bit is protected. MISRG(0038 16) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “0116” to Timer 1, “FF16” to Prescaler 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Disabled 1: Automatic switch enabled (Notes 1, 2) Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 cycles 1: 6.5 to 7.5 cycles Middle-speed mode automatic switch start bit (depends on software) 0: Invalid 1: Automatic switch start (Note 2) Not used (return “0” when read) b7 b0 Notes 1: The microcomputer can be switched to the middle-speed mode automatically by the SCL/SDA interrupt during operation in the low-speed mode. 2: When switching from the low-speed mode to the middle-speed mode, the value of the CPU mode register also changes. Fig.61 Structure of MISRG1, MISRG2 Fig.62 32kHz oscillation control register I Notes on middle-speed mode switch set bit When the middle-speed mode automatic switch set bit is set to “1” during operation in the low-speed mode, XIN oscillation starts au- tomatically by detecting the rising edge or the falling edge of the SCL pin or the SDA pin and the microcomputer switch to the middle-speed mode. Select the timing which switch from the low- speed mode to the middle-speed mode by the middle-speed mode automatic switch wait time set bit. The timing which changes from the low-speed mode by the middle-speed mode automatic switch wait time set bit. Select according to the oscillation start character- istic of the oscillator of X IN to be used. By writing “1” in the middle-speed mode automatic switch start bit during operation in the low-speed mode, XIN oscillation starts automatically and the microcomputer changes to the middle-speed mode. b7 b6 b5 b4 b3 b2 b1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 32kHz oscillation control register 0 (003216) 32kHz oscillation control register 1 (003316)

Rev.1.01 Aug 02, 2004 page 55 of 96 Fig. 63 State transitions of system clock RESET Clock source switch bit 0 : On-chip oscillation function1 : X IN -XOUT oscillation function CM 4 : Port Xc switch bit 0 : I/O port function (stop oscillating)1 : X CIN -XCOUT oscillating function CM 5 : Main clock(XIN - XOUT ) stop bit 0 : oscillating1 : stopped CM 7,CM 6: Main clock division ratio selection bits b7 b6 0 0 : f= f(X IN )/2 (high-speed mode) 0 1 : f= f(XIN )/8 (middle-speed mode) 1 0 : f= f(XCIN )/2 (low-speed mode) 1 1 : Not available CPU mode register(003B16 CPUM CM4 "1" "0" CM "0" "1" CM "1" "0" CM 4 "1" "0" CM 6 "1" "0" CM7 "1" "0" CM4 "1" "0" CM5 "1" "0" CM 6 "1" "0"CM 6 "1" "0" CM "0" "1" CM "1" "0" High-speed on-chip oscillation stop bit 0 : oscillating1 : stopped MISRG2(003716 CM4 "1" "0" CM "0" "1" CM "0" "1" CM 4 "1" "0" CM 6 "0" "1" CM7 "1" "0" CM4 "1" "0" MISGR2 (bit2) "1" "0" CM 6 "1" "0" CM 6 "1" "0" CM 7 "1" "0" CM 6 "0" "1" CM 5 "1" "0" CM4 "1" "0" CM 5 "1" "0" CM4 "1" "0" CM 5 "0" "1" CM 5 "0" "1" MISRG2 (bit 2) "1" "0" CM 3 "1" "0" XIN oscillation high-speed mode(f( φ)=2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=1(High-speed on-chip oscillating stopped) XIN oscillation middle-speed mode(f( φ)=500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed on-chip oscillatin stopped) XIN oscillation high-speed mode(f( φ)=2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed on-chip oscillating stopped) Low-speed mode(f( φ)=16kHz) CM7=1 CM6=0 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed on-chip oscillating stopped) On-chip oscillation high-speed mode(f( φ)=approximately 2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating ) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) On-chip oscillationhigh-speed mode(f( φ)=approximately 2MHz) CM7=0 CM6=0 CM5=1(4MHz oscillating stopped) CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mo de is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 2 ms occurs by connecting Timer 1 in middle/high-speed mode. 5 : When the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 16ms occurs in low-speed mode if Timer 12 count source selec tion bit is "0". (2) After the clock is restarted, a delay of approximately 250ms occurs in low-speed mode if Timer 12 count source selec tion bit is "1". 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. CM4 "1" "0" CM 3 "1" "0" MISRG2 (bit 2) "1" "0" CM 3 "1" "0" Low-speed mode(f( φ)=16MHz) CM7=1 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed on-chip oscillating stopped) CM 3 "1" "0" MISRG2 (bit 2)"1" "0" MISRG2 (bit 2)"1" "0" Low-speed mode(f( φ)=16kHz) CM7=1 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=1(High-speed on-chip oscillating stopped) On-chip oscillating middle-speed mode(f( φ)=approximately 500kHz) CM7=0 CM6=1 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) Low-speed mode(f( φ)=16kHz) CM7=1 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) XIN oscillation high-speed mode(f( φ)=2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=0(High-speed on-chip oscillating) XIN oscillation high-speed mode(f( φ)=2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating ) CM3=1 MISRG2(bit2)=0(High-speed on-chip oscillating) XIN oscillation middle-speed mode(f( φ)=500 kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=1(High-speed on-chip oscillating stopped) XIN oscillation middle-speed mode(f( φ)=500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=0(High-speed on-chip oscillating) On-chip oscillating middle-speed mode(f( φ)=approximately 500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) On-chip oscillating middle-speed mode(f( φ)=approximately 500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) On-chip oscillating middle-speed mode(f( φ)=approximately 500kHz) CM7=0 CM6=1 CM5=1(4MHz oscillating stopped) CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) On-chip oscillation high-speedmode(f( φ)=approximately 2MHz) CM7=0 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating ) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating) XIN oscillation middle-speed mode(f( φ)=500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=0(High-speed on-chip oscillating) On-chip oscillation high-speed mode(f( φ)=approximately 2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed on-chip oscillating)

Rev.1.01 Aug 02, 2004 page 56 of 96 The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt request register, execute at least one instruction before perform- ing a BBC or BBS instruction. Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction be- fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af- fect the MUL and DIV instruction.
• The execution of these instructions does not change the con- tents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial interface In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1”. Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transmis- sion is completed. When an external clock is used as synchronous clock in serial I/ O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is “H”. A/D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A/D conversion. Do not execute the STP or WIT instruction during an A/D conver- sion. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency in high-speed mode. NOTES ON USAGE Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF 0.1µF is recom- mended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.

Rev.1.01 Aug 02, 2004 page 57 of 96 Table 11 Summary of M37517F8 (flash memory version) Item Power source voltage VPP voltage (For Program/Erase) Flash memory mode Erase block division User ROM area Boot ROM area Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Specifications Vcc = 2.7– 5.5 V (Note 1) Vcc = 2.7–3.6 V (Note 2) 4.5–5.5 V, f(X IN) = 8 MHz 3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode) 1 block (32 Kbytes) 1 block (4 Kbytes) (Note 3) Byte program Batch erasing Program/Erase control by software command 6 commands 100 times Available in parallel I/O mode and standard serial I/O mode Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation. 2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation. 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode. FLASH MEMORY MODE Summary Table 11 lists the summary of the M37517F8 (flash memory ver- sion).

Rev.1.01 Aug 02, 2004 page 58 of 96 The M37517F8 (flash memory version) has an internal new DINOR (Divided bit line NOR) flash memory that can be rewritten with a single power source when V CC is 5 V, and 2 power sources when VPP is 5 V and VCC is 3.3-5.0 V in the CPU rewrite and stan- dard serial I/O modes. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). The flash memory of the M37517F8 is divided into User ROM area and Boot ROM area as shown in Figure 64. In addition to the ordinary User ROM area to store the MCU op- eration control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application sys- tem. This Boot ROM area can be rewritten in only parallel I/O mode. Fig. 64 Block diagram of built-in flash memory 800016 Block 1 : 32 kbyte User ROM area 4 kbyte F00016 FFFF 16 FFFF 16 Boot ROM area Notes 1: The Boot ROM area can be rewritten in only parallel input/ output mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. Product name Flash memory start address M37517F8 8000 16 Parallel I/O mode 800016 Block 1 : 32 kbyte FFFF 16 CPU rewrite mode, standard serial I/O mode User ROM area 4 kbyte F00016 FFFF 16 Boot ROM area BSEL = 0 BSEL = 1 User area / Boot area selection bit = 0 User area / Boot area selection bit = 1

Rev.1.01 Aug 02, 2004 page 59 of 96 (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Process- ing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 64 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite con- trol program must be transferred to internal RAM area to be executed before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the stan- dard serial I/O mode becomes unusable.) See Figure 64 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P4 1/INT0 pin high, the CNVss pin high, the CPU starts operating using the control program in the Boot ROM area (program start address is FFFC16, FFFD 16 fixation). This mode is called the “Boot” mode. The User ROM area can be rewritten also by the control program in the Boot ROM area. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. In case of the M37517F8, it has only one block.

Rev.1.01 Aug 02, 2004 page 60 of 96 Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads the in- ternal flash memory by executing software commands. This rewrite control program must be transferred to the RAM before it can be executed. The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to the CNV SS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit 1 of address 0FFE16). Software commands are accepted once the mode is entered. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 65 shows the flash memory control register. Bit 0 is the RY/BY status flag used exclusively to read the operat- ing status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. Software commands are accepted once the mode is entered. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in the RAM for write to bit 1. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing “0”. Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in CPU rewrite mode, so that reading this flag can check whether CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the control circuit. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. To release the reset, it is necessary to set this bit to “0”. Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to “1”, Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In Boot mode, this bit is set to “1” auto- matically. Reprogramming of this bit must be in the RAM. Figure 66 shows a flowchart for setting/releasing CPU rewrite mode. Fig. 65 Structure of flash memory control register Flash memory control register (address 0FFE16) (Note 1) FMCR RY/BY status flag (FMCR0) 0: Busy (being programmed or erased) 1: Ready CPU rewrite mode select bit (FMCR1) (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag (FMCR2) 0: Normal mode 1: CPU rewrite mode Flash memory reset bit (FMCR3) (Note 3) 0: Normal operation 1: Reset User ROM area / Boot ROM area select bit (FMCR4) 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (Indefinite at read/ “0” at write) b0b7 Notes 1: The contents of flash memory control register are “XXX00001 ” just after reset release. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to “1”. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”.

Rev.1.01 Aug 02, 2004 page 61 of 96 Fig. 66 CPU rewrite mode set/release flowchart End Start Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 2) S i n g l e c h i p m o d e o r B o o t m o d e S e t C P U m o d e r e g i s t e r N o t e U s i n g s o f t w a r e c o m m a n d e x e c u t e e r a s e , p r o g r a m o r o t h e r o p e r a t i o n J u m p t o c o n t r o l p r o g r a m t r a n s f e r r e d i n R A M S u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s R A M T r a n s f e r C P U r e w r i t e m o d e c o n t r o l p r o g r a m t o R A M N o t e s1 : S e t b i t s 6 , 7 ( m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s ) o f C P U m o d e r e g i s t e r ( 0 0 3 B B e f o r e e x i t i n g t h e C P U r e w r i t e m o d e a f t e r c o m p l e t i n g e r a s e o r p r o g r a m o p e r a t i o n a l w a y s b e s u r e t o e x e c u t e t h e r e a d a r r a y c o m m a n d o r r e s e t t h e f l a s h m e m o r y W r i t e “ 0 ” t o C P U r e w r i t e m o d e s e l e c t b i t S e t C P U r e w r i t e m o d e s e l e c t b i t t o “ 1 ” ( b y w r i t i n g a n d t h e n i n s u c c e s s i o n

Rev.1.01 Aug 02, 2004 page 62 of 96 Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock φ 4.0 MHz or less using the main clock division ratio selection bits (bit 6, 7 at 003B 16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . (3) Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode be- cause they refer to the internal data of the flash memory. (4) Watchdog timer In case of the watchdog timer has been running already, the in- ternal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. (5) Reset Reset is always valid. In case of CNVSS = H when reset is re- leased, boot mode is active. So the program starts from the ad- dress contained in address FFFC 16 and FFFD16 in boot ROM area.

Rev.1.01 Aug 02, 2004 page 63 of 96 Software Commands (CPU Rewrite Mode) Table 12 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. G Read Array Command (FF 16) The read array mode is entered by writing the command code “FF 16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained intact until another command is written. G Read Status Register Command (70 16) The read status register mode is entered by writing the command code “70 16” in the first bus cycle. The contents of the status regis- ter are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. G Clear Status Register Command (50 16) This command is used to clear the bits SR1, SR4, and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “50 16” in the first bus cycle. G Program Command (40 16) Program operation starts when the command code “4016” is writ- ten in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification) will start. Whether the write operation is completed can be confirmed by reading the status register or the RY/BY Status Flag of the flash memory control register. When the program starts, the read status Table 12 List of software commands (CPU rewrite mode) register mode is entered automatically and the contents of the sta- tus register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the next command is written. ____ The RY/BY Status Flag is “0” (busy) during write operation and “1” (ready) when the write operation is completed as is the status reg- ister bit 7. At program end, program results can be checked by reading bit 4 (SR4) of the status register. Fig. 67 Program flowchart S t a r t W r i t e 4 01 S t a t u s r e g i s t e r r e a d P r o g r a m c o m p l e t e d R e a d a r r a y c o m m a n d F w r i t e N O Y E S W r i t e a d d r e s s W r i t e d a t a S R 4 = 0 ? P r o g r a m e r r o r N O YES SR7 = 1 ? or RY/BY = 1 ? W r i t e Command Program Clear status register Read array Read status register X X First bus cycle Second bus cycle FF16 7016 5016 4016 Write Write Write Write X SRDRead Write Erase all blocks 2016Write X 2016Write (Note 1) WA (Note 2) WD (Note 2) Block erase 2016Write D0 16Write BA (Note 3) Mode Address Mode Address Data (D0 to D7)(D0 to D7) (Note 4) Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address to be erased (Input the maximum address of each block.) 4: X denotes a given address in the User ROM area . Cycle number X X X X Data

Rev.1.01 Aug 02, 2004 page 64 of 96 G Erase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. Whether the erase all blocks command is terminated can be con- ____ firmed by reading the status register or the RY/BY Status Flag of flash memory control register. When the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus 0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon comple- tion of the erase operation. In this case, the read status register mode remains active until another command is written. ____ The RY/BY Status Flag is “0” during erase operation and “1” when the erase operation is completed as is the status register bit 7 (SR7). After the erase all blocks end, erase results can be checked by reading bit 5 (SR5) of the status register. For details, refer to the section where the status register is detailed. G Block Erase Command (20 16/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D0 16” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY Status Flag of flash memory control register. At the same time the block erase opera- tion starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF 16) is writ- ten. ____ The RY/BY Status Flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status reg- ister bit 7. After the block erase ends, erase results can be checked by read- ing bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. Fig. 68 Erase flowchart W r i t e 2 01 2 01 6/ D 01 B l o c k a d d r e s s E r a s e c o m p l e t e d R e a d c o m a n d F w r i t e NO Y E S S t a r t W r i t e SR5 = 0 ? E r a s e e r r o r Y E S NO 2 01 6: E r a s e a l l b l o c k s c o m m a n d D B l o c k e r a s e c o m m a n d S R 7 = 1 ? o r R Y B Y S t a t u s r e g i s t e r r e a d

Rev.1.01 Aug 02, 2004 page 65 of 96 Table 13 Definition of each bit in status register (SRD) Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 13 shows the status register. Each bit in this register is ex- plained below.

• Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready).
• Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”.
• Program status (SR4) The program status indicates the operating status of write opera- tion. When a write error occurs, it is set to “1”. The program status is set to “0” when it is cleared. If “1” is written for any of the SR5 and SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status regis- ter command (50 16) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Definition “1” “0” Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Ready Terminated in error Terminated in error Busy Terminated normally Terminated normally

Rev.1.01 Aug 02, 2004 page 66 of 96 By performing full status check, it is possible to know the execu- tion results of erase and program operations. Figure 69 shows a Fig. 69 Full status check flowchart and remedial procedure for errors full status check flowchart and the action to be taken when each error occurs. R e a d s t a t u s r e g i s t e r S R 4 = 1 a n d S N O Y E S S R 5 = 0 ? Y E S Er a s e e r r o rN O S R 4 = 0 ? Y E S N O C o m m a n d s e q u e n c e e r r o r P r o g r a m e r r o r E n d ( e r a s e , p r o g r a m ) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. N o t e: W h e n o n e o f S R 5 a n d S R 4 i s s e t t o “ 1 ” , n o n e o f t h e r e a d a r r a y , t h e p r o g r a m , e r a s e a l l b l o c k s a n d b l o c k e r a s e c o m m a n d s i s a c c e p t e d E x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d b e f o r e e x e c u t i n g t h e s e c o m m a n d s Should a program error occur, the block in error cannot be used.

Rev.1.01 Aug 02, 2004 page 67 of 96 Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check func- tion for use in standard serial I/O mode. G ROM Code Protect Function (in Parallel I/O Mode) The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control (address FFDB 16) in parallel I/O mode. Figure 70 shows the ROM code protect control (address FFDB 16). (This address exists in the User ROM area.) If one or both of the pair of ROM Code Protect Bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM Code Protect Reset Bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be read out or modified. Once the ROM code protect is turned on, the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM Code Pro- tect Reset Bits. Fig. 70 Structure of ROM code protect control ROM code protect control register (address FFDB16) ROMCP Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (ROMCR) (Note 3) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 1) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled b0b7 Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU rewrite mode.

Rev.1.01 Aug 02, 2004 page 68 of 96 ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the pro- grammer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD4 16 to FFDA16. Write a pro- gram which has had the ID code preset at these addresses to the flash memory. Fig. 71 ID code store addresses R O M c o d e p r o t e c t c o n t r o l ID7 ID6 ID5 ID4 I D 3 ID2 ID1 F F D B F F D A1 F F D 91 FFD8 16 F F D 71 F F D 61 FFD5 16 F F D 41 Address Interrupt vector area

Rev.1.01 Aug 02, 2004 page 69 of 96 (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. Use the ex- clusive external equipment flash programmer which supports the 7517 Group (flash memory version). Refer to each programmer maker’s handling manual for the details of the usage. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 64 can be rewritten. Both areas of flash memory can be oper- ated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its block is shown in Figure 64. The boot ROM area is 4 Kbytes in size. It is located at addresses F000 16 through FFFF16. Make sure program and block erase opera- tions are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Renesas factory. Therefore, using the device in standard serial I/O mode, you do not need to write to the boot ROM area.

Rev.1.01 Aug 02, 2004 page 70 of 96 (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires the exclusive external equipment (serial programmer). The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H ” to the P2 6 (SCLK ) pin and “H ” to the P41 (INT0) pin and “H ” to the CNVSS pin (apply 4.5 V to 5.5 V to Vpp from an external source), and releasing the re- set operation. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. Figure T-9 shows the pin connection for the standard serial I/O mode. In standard serial I/O mode, serial data I/O uses the four serial I/O pins S CLK , RxD, TxD and SRDY1 (BUSY). The SCLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD pin is for CMOS output. The SRDY1 (BUSY) pin outputs “L” level when ready for reception and “H ” level when re- ception starts. Serial data I/O is transferred serially in 8-bit units. In standard serial I/O mode, only the User ROM area shown in Figure 64 can be rewritten. The Boot ROM area cannot. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Outline Performance (Standard Serial I/O Mode) In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (serial programmer, etc.) using 4-wire clock-synchronized serial I/ O (serial I/O1). In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the S CLK pin, and are then input to the MCU via the RxD pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD pin. The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the S RDY1 (BUSY) pin is “H ” level. Accord- ingly, always start the next transfer after the SRDY1 (BUSY) pin is “L” level. Also, data and status registers in a memory can be read after in- putting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following explains software commands, status registers, etc.

Rev.1.01 Aug 02, 2004 page 71 of 96 Table 14 Description of pin function (Standard Serial I/O Mode) Pin Description VCC , VSS Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin. Name Power input I/O CNV SS Connect to VCC when VCC = 4.5 V to 5.5 V. RESET Reset input pin. While reset is “L” level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT CNV SS Reset input Clock input Clock output I I I O ADV REF Enter the reference voltage for AD from this pin, or open. P00 to P07 Input “H ” or “L”, or open. P10 to P17 Input “H ” or “L”, or open. P20 to P23 This pin is for serial data input. AV SS Connect AVSS to VSS .Analog power supply input AD reference voltage input Input port P0 Input port P1 Input port P2 I I I I P41 Input “H ” when RESET is released only. P40, P42 to P45 P24 This pin is for serial data output.P25 P26 This pin is for serial clock input. P27 Input port P4 Input port P4 RxD input TxD output SCLK input BUSY output I I I I P30 to P35 Input port P3 I O O Input “H ” or “L”, or open. This pin is for BUSY signal output. Input “H ” or “L”, or open. Input “H ” or “L”, or open. Connect AVCC to VCC .AV CC Analog power supply input I ADV SS Analog power supply input Connect ADVSS to VSS . ISENS0 ISENS1 Analog input I Connect the sense register. ISENS0 is connected the GND side. I

Rev.1.01 Aug 02, 2004 page 72 of 96 Fig. 72 Pin connection diagram in standard serial I/O mode 1 2 3 4 5 6 7 8 9 10 11 12 35 34 33 32 31 30 29 28 27 26 25 P17/(LED7) 2/INT 1/INT 0/CNTR 7/CNTR 0/S RDY1 6/S CLK 5/SCL 2/T XD 3/SCL 2/SDA CNV SS P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) VSS XOUT XIN 4/AN 5/AN 0/S IN2 1/S OUT2 2/S CLK2 3/S RDY2 1/(LED 0/(LED RESET P20/XCOUT P21/XCIN 4/INT 3/PWM 4/SDA 2/R XD P33/AN3 P32/AN2 ADV SS ADV REF VCC AV SS ISENS0 ISENS1 P31/AN1 P30/AN0 AV CC DFETCNT/P4 5 3/INT 2/S CMP2 M37517F8HP BUSY VCC VSS T XD R XD V PPSignal CNV SS P41 Value 4.5 to 5.5 V VCC ✽ 3 Mode setup method RESET ✽2SCLK Notes 1: Connect oscillator circuit, or open. 2: Connect to Vcc when Vcc = 4.5 V to 5.5 V. 3: It is necessary to apply Vcc only when reset is released. RESET VSS VCC P26/SCLK VCC ✽ 3

Rev.1.01 Aug 02, 2004 page 73 of 96 (Standard Serial I/O Mode) Table 15 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software 2nd byte Address (middle) 3rd byte Address (high) 4th byte Data output 5th byte Data output 6th byte Data output Data output to 259th byte Data input to 259th byte FF16 When ID is not verified 1st byte transfer Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment (programmer) to the internal flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted when the flash memory is totally blank. 4: Address high must be “0016”. commands via the RxD pin. Software commands are explained here below. Table 15 Software commands (Standard serial I/O mode)

1 Page read

4116 Address

(middle) Address (high) Data input Data input Data input Not acceptable Not acceptableA716 D0 16

7016 SRD

5016 Not

(low) Address (middle) Address (high) ID size ID1 To ID7 Acceptable FA16 Data input To required number of times Not acceptable FB 16 Version data output Version data output Version data output Version data output Version data output Version data output to 9th byte Control command

2 Page program

3 Erase all blocks

4 Read status register

5 Clear status register

6 ID code check

7 Download function

8 Version data output function

(low) Size (high) Check- sum Acceptable Not acceptable

Rev.1.01 Aug 02, 2004 page 74 of 96 G Read Status Register Command This command reads status information. When the “7016” com- mand code is transferred with the 1st byte, the contents of the status register (SRD) with the 2nd byte and the contents of status register 1 (SRD1) with the 3rd byte are read. G Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF 16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8 to A23 will be output se- quentially from the smallest address first synchronized with the fall of the clock. Fig. 73 Timing for page read Fig. 74 Timing for reading status register d a t a 0 data255 t o 6 t o FF16 SCLK RxD TxD SRDY1 (BUSY) SRD output SRD1 output SCLK RxD TxD SRDY1 (BUSY) 7016

Rev.1.01 Aug 02, 2004 page 75 of 96 Fig. 75 Timing for clear status register G Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “50 16” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the SRDY1 (BUSY) signal changes from “H ” to “L” level. G Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page pro- gram command as explained here following. (1) Transfer the “41 16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0 to D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is auto- matically written. When reception setup for the next 256 bytes ends, the S RDY1 (BUSY) signal changes from “H ” to “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Fig. 76 Timing for page program SCLK RxD TxD SRDY1 (BUSY) t o t o 6 data0 d a t a SC L K R x D T x D SR D Y B U S Y

Rev.1.01 Aug 02, 2004 page 76 of 96 G Erase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A7 16” command code with the 1st byte. (2) Transfer the verify command code “D0 16” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When erase all blocks end, the S RDY1 (BUSY) signal changes from “H ” to “L” level. The result of the erase operation can be known by reading the status register. Fig. 77 Timing for erase all blocks A

6 D0 16

L K R x D T x D SR D Y B U S Y

Rev.1.01 Aug 02, 2004 page 77 of 96 This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA 16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. Fig. 78 Timing for download F A1 P r o g r a m d a t a P r o g r a m d a t a D a t a s i z e l o w C h e c k s u m SCLK RxD TxD SRDY1 (BUSY) Data size (high)

Rev.1.01 Aug 02, 2004 page 78 of 96 G Version Information Output Command This command outputs the version information of the control pro- gram stored in the Boot ROM area. Execute the version information output command as explained here following. (1) Transfer the “FB 16” command code with the 1st byte. (2) The version information will be output from the 2nd byte on- ward. This data is composed of 8 ASCII code characters. Fig. 79 Timing for version information output FB 16 ‘ X ’ ‘V’‘ E’‘ R ’ SC L K R x D T x D SR D Y B U S Y

Rev.1.01 Aug 02, 2004 page 79 of 96 This command checks the ID code. Execute the boot ID check command as explained here following. G ID Code When the flash memory is not blank, the ID code sent from the se- rial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFD4 16 to FFDA16. Write a program into the flash memory, which already has the ID code set for these addresses. Fig. 80 Timing for ID check Fig. 81 ID code storage addresses (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”) of the 1st byte of the ID code with the 2nd, 3rd, and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) Transfer the ID code with the 6th byte onward, starting with the 1st byte of the code. ID size I D 1 I D 7F 51

6 D 41

6 F F1

L K R x D T x D SR D Y B U S Y R O M c o d e p r o t e c t c o n t r o l ID7 ID6 ID5 ID4 ID3 I D 2 ID1 F F D B F F D A1 FFD9 16 F F D 81 FFD7 16 FFD6 16 F F D F F D Address I n t e r r u p t v e c t o r a r e a

Rev.1.01 Aug 02, 2004 page 80 of 96 G Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table 16 lists the definition of each status register bit. After releas- ing the reset, the status register becomes “8016”.

• Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. After power-on and recover from deep power down mode, the se- quencer status is set to “1” (ready). This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations.
• Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”.
• Program status (SR4) The program status indicates the operating status of write opera- tion. If a program error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Definition “1”“ 0” Table 16 Definition of each bit of status register (SRD) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Ready Terminated in error Terminated in error Busy Terminated normally Terminated normally

Rev.1.01 Aug 02, 2004 page 81 of 96 G Status Register 1 (SRD1) The status register 1 indicates the status of serial communica- tions, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writ- ing the read status register command (70 16). Also, status register 1 is cleared by writing the clear status register command (5016). Table 17 lists the definition of each status register 1 bit. This regis- ter becomes “0016” when power is turned on and the flag status is maintained even after the reset. Table 17 Definition of each bit of status register 1 (SRD1)

00 Not verified

01 Verification mismatch

10 Reserved

11 Verified

SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) SR9 (bit1) SR8 (bit0) Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Data reception time out Reserved “1” Update completed Match Time out “0” Not Update Mismatch Normal operation Definition SRD1 bits Status name

• Boot update completed bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function.
• Check sum consistency bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download func- tion.
• ID check completed bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID code check.
• Data reception time out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the re- ceived data is discarded and the MCU returns to the command wait state.

Rev.1.01 Aug 02, 2004 page 82 of 96 Results from executed erase and program operations can be known by running a full status check. Figure 82 shows a flowchart of the full status check and explains how to remedy errors which occur. Fig. 82 Full status check flowchart and remedial procedure for errors Read status register S R 4 = 1 a n d S N O Y E S S R 5 = 0 ? Y E S Er a s e e r r o rN O SR4 = 0 ? Y E S N O C o m m a n d s e q u e n c e e r r o r Program error End (Erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. N o t e: W h e n o n e o f S R 5 t o S R 4 i s s e t t o “ 1 ” , n o n e o f t h e p r o g r a m , e r a s e a l l b l o c k s c o m m a n d s i s a c c e p t e d E x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d b e f o r e e x e c u t i n g t h e s e c o m m a n d s Should a program error occur, the block in error cannot be used.

Rev.1.01 Aug 02, 2004 page 83 of 96 Example Circuit Application for Standard Serial I/O Mode Figure 83 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information. Fig. 83 Example circuit application for standard serial I/O mode SRDY1 (BUSY) SCLK R XD TXD CNVss Clock input BUSY output Data input Data output M37517F8 Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. 2: In this example, the Vpp power supply is supplied from an external source (writer). To use the user’s power source, connect to 4.5 V to 5.5 V. 3: It is necessary to apply Vcc to SCLK pin only when reset is released. VPP power source input P41

Rev.1.01 Aug 02, 2004 page 84 of 96 Flash memory Electrical characteristics Table 18 Absolute maximum ratings Power source voltage Input voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45, ADV REF , AVCC , ISENS1 Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 300 25±5 –40 to 125 V V V V V V V mW Unit Ta = 25 °C All voltages are based on VSS . Output transistors are cut off. Table 19 Flash memory mode Electrical characteristics (Ta = 25 oC, VCC = 4.5 to 5.5V unless otherwise noted) VPP power source current (read) VPP power source current (program) VPP power source current (erase) VPP power source voltage VCC power source voltage Limits Parameter Min. Typ. Max.Symbol Unit VPP = VCC VPP = VCC VPP = VCC Microcomputer mode operation at VCC = 2.7 to 5.5V Microcomputer mode operation at V CC = 2.7 to 3.6V Conditions IPP1 IPP2 IPP3 VPP VCC 4.5 100 5.5 µA mA mA V 4.5 3.0 5.5 3.6 V V

Rev.1.01 Aug 02, 2004 page 85 of 96

ELECTRICAL CHARACTERISTICS

Table 20 Absolute maximum ratings (Executing flash memory mode, flash memory electrical characteristics is applied.) Power source voltage Input voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45, ADV REF , AVCC, ISENS1 Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 5.8 300 –20 to 85 –40 to 125 V V V V V V V mW Unit Ta = 25 °C All voltages are based on VSS . Output transistors are cut off. Table 21 Recommended operating conditions (1) (VCC = 3.0 to 3.6 V, Ta = –20 to 85 °C, unless otherwise noted) VCC VSS ADV REF ADV SS VIA AV CC AV SS ISENS0 ISENS1 V IH VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL 3.6 3.366 VCC VCC 3.366 0.1 VCC 5.8 VCC 5.8 VCC VCC 0.2VCC 0.3VCC 0.6 0.2VCC 0.16VCC Power source voltage At 4 MHz When using current integrator, over current detector, 32 kHz RC oscillation circuit Power source voltage A/D convert reference voltage A/D convert power source voltage Analog input voltage AN 0–AN 5, AN8–AN 11 Analog power source voltage Analog power source voltage Analog input voltage Analog input voltage “H ” input voltage P0 0–P07, P10–P17, P20–P27, P30–P35, P40–P45 “H ” input voltage (when I2C-BUS input level is selected) SDA 1, SCL1 “H ” input voltage (when I2C-BUS input level is selected) SDA 2, SCL2 “H ” input voltage (when SMBUS input level is selected) SDA 1, SCL1 “H ” input voltage (when SMBUS input level is selected) SDA 2, SCL2 “H ” input voltage RESET, X IN, CNVSS “L” input voltage P0 0–P07, P10–P17, P20–P27, P30–P35, P40–P45 “L” input voltage (when I2C-BUS input level is selected) SDA 1, SDA2, SCL1, SCL2 “L” input voltage (when SMBUS input level is selected) SDA 1, SDA2, SCL1, SCL2 “L” input voltage RESET, CNV SS “L” input voltage X IN Symbol Parameter Limits Min. V V V V V V V V V V V V V V V V V V V V Unit 3.0 3.234 2.0 ADV SS 3.234 -0.1 0.8VCC 0.7VCC 0.7VCC 1.4 1.4 0.8VCC 3.3 3.3 3.3 Typ. Max.

Rev.1.01 Aug 02, 2004 page 86 of 96 Table 22 Recommended operating conditions (2) (VCC = 3.0 to 3.6 V, Ta = –20 to 85 °C, unless otherwise noted) –80 –80 –40 –40 “H ” total peak output current P0 0–P07, P10–P17, P30–P35 (Note 1) “H ” total peak output current P20, P21, P24–P27, P40–P45 (Note1) “L” total peak output current P00–P07, P30–P35 (Note 1) “L” total peak output current P10–P17 (Note1) “L” total peak output current P20–P27,P40–P45 (Note1) “H ” total average output current P00–P07, P10–P17, P30–P35 (Note1) “H ” total average output current P20, P21, P24–P27, P40–P45 (Note1) “L” total average output current P00–P07, P30–P35 (Note1) “L” total average output current P10–P17 (Note 1) “L” total average output current P20–P27,P40–P45 (Note1) “H ” peak output current P0 0–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45 (Note 2) “L” peak output current P0 0–P07, P20–P27, P30–P35, P40–P45 (Note 2) “L” peak output current P1 0–P17 (Note 2) “H ” average output current P0 0–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45 (Note 3) “L” average output current P00–P07, P20–P27, P30–P35, P40–P45 (Note 3) “L” average output current P1 0–P17 (Note 3) Internal clock oscillation frequency (VCC = 3.0 to 3.6V) (Note 4) ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) Symbol Parameter Limits Min. UnitTyp. Max. Notes 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea- sured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3: The average output current IOL (avg), IOH (avg) are average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50%. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) –10 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz mA

Rev.1.01 Aug 02, 2004 page 87 of 96 Table 23 Electrical characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) “H ” output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45 (Note) “L” output voltage P00–P07, P20–P27, P30–P35, P40–P45 “L” output voltage P10–P17 Hysteresis CNTR 0, CNTR1, INT0–INT3 Hysteresis RxD, SCLK Hysteresis RESET “H ” input current P00–P07, P10–P17, P20, P21, P24–P27, P30–P35, P40–P45 “H ” input current ISENS0, ISENS1 “H ” input current RESET, CNVSS “H ” input current XIN “L” input current P00–P07, P10–P17, P20–P27 P30–P35, P40–P45 “L” input current ISENS0, ISENS1 “L” input current RESET,CNVSS “L” input current XIN RAM hold voltage Limits V Parameter Min. Typ. Max.Symbol Unit Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. IOH = –1.0 mA VCC = 3.0–3.6 V IOL = 1.0 mA VCC = 3.0–3.6 V IOL = 10 mA VCC = 3.0–3.6 V VI = VCC VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS VI = VSS When clock stopped Test conditions 0.4 0.5 0.3 1.0 VOH 2.0 1.0 5.0 1.0 5.0 –5.0 –1.0 –5.0 3.6 V V V V V µA µA µA µA µA µA µA µA V VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIH IIL IIL IIL IIL VRAM VCC –1.0

Rev.1.01 Aug 02, 2004 page 88 of 96 f(XIN) = 4 MHz or high-speed on-chip oscillation f(XCIN) = 32.768 kHz or 32 kHz RC oscillation Output transistors “off” Current integrator and over current detector stopped High-speed mode f(X IN) = 4 MHz or high-speed on-chip oscillation (in WIT state) f(X CIN) = 32.768 kHz or 32 kHz RC oscillation Output transistors “off” Current integrator and over current detector stopped Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz or 32kHz RC oscillation Output transistors “off” Current integrator and over current detector stopped Low-speed mode f(X IN) = stopped f(XCIN) = 32.768 kHz or 32kHz RC oscillation (in WIT state) Output transistors “off” Current integrator and over current detector stopped Middle-speed mode f(X IN) = 4 MHz or high-speed on-chip oscillation f(XCIN) = stopped Output transistors “off” Current integrator and over current detector stopped Middle-speed mode f(X IN) = 4 MHz or high-speed on-chip oscillation (in WIT state) f(X CIN) = stopped Output transistors “off” Current integrator and over current detector stopped Increment when A/D conversion is executed f(X IN) = 4 MHz or high-speed on-chip oscillation Table 24 Electrical characteristics (1) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Power source current Limits Parameter Min. Typ. Max.Symbol UnitTest conditions 5.0 ICC 2.5 mA 0.6 200 1.7 0.7 800 3.0 mA µA µA mA mA µA

Rev.1.01 Aug 02, 2004 page 89 of 96 Min. Typ. Max.Symbol UnitTest conditions Short current detector Over current detector Wake up current detector Short current detector + over current detector Short current detector + wake up current detector Over current detector + wake up current detector Short current detector + over current detector + wake up current detector Ta = 25 °C Ta = 85 °C 1000 0.1 1600 110 110 120 110 120 120 120 1.0 µA µA µA µA µA µA µA µA µA µA Increment when over current detector is executed. All oscillation stopped (in STP state) Output transistors “off” Power source currentICC Increment when current integrator is executed Limits Table 25 Electrical characteristics (2) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Rev.1.01 Aug 02, 2004 page 90 of 96 Table 26 High-speed on-chip oscillation circuit electrical characteristics (VCC = AVCC = 3.3 V ±2 %, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Parameter Min. Typ. Max.Symbol UnitTest conditions Oscillating frequency Oscillating frequency shift by temperature VCC =3.3V VCC =AV CC =3.3V, –20 to 85 °C 2.75 4.0 0.3

5.8 MHz

%/°C f4MCR f4MCRS Table 27 32 kHz RC oscillation circuit electrical characteristics (VCC = AVCC = 3.3 V ±2 %, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Parameter Min. Typ. Max.Symbol UnitTest conditions External register, and capacitor tolerance Oscillating frequency adjustment resolution Oscillating frequency shift by VCC voltage Oscillating frequency shift by temperature Oscillating frequency shift by VCC voltage and temperature Total tolerance of the resistor and capacitor Ta=25 °C VCC =AV CC =3.3V, –20 to 85 °C 0.04 0.5 0.5 0.07 kHz

Rev.1.01 Aug 02, 2004 page 91 of 96 tc(φ) µs kΩ µA µA µA Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A/D port input current Min. Typ. 100 0.5 Max. 140 5.0 5.0 High-speed mode, middle-speed mode Low-speed mode V REF = 3.3 V Table 28 A/D converter characteristics (VCC = 3.0 to 3.6 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 4MHz, f(XCIN) = 32 kHz, unless otherwise noted) UnitLimitsParameter tCONV R LADDER IVREF II(AD) Test conditionsSymbol VREF “on” VREF “off” Fig. 84 Current integrator timing diagram Table 29 Current integrator electrical characteristics (VCC = AVCC = 3.3 V ±2 %, VSS = AVSS = 0V, Ta = –20 to 85 °C, f(XIN) = 4 MHz, f(XCIN) = 32 kHz) Limits Parameter Min. Typ. Max.Symbol UnitTest conditions Integrate period ISENS1 input range Caribration time AD conversion time at AD conversion connection mode Integrate coefficient of integrator for discharge Integrate coefficient of integrator for charge Reset time of integrator for discharge Reset time of integrator for charge Count value at 0V input Internal reference voltage for discharge integrator Internal reference voltage for charge integrator linearity error after reset time caribration VCC = 3.3 V ±2 % Ta = 0 to 60 °C VCC = 3.3 V ±2 % Ta = -20 to 85 °C 0.2 125 1.35 1.35 2400 0.11 –0.09 ms V ms µs µV•sec µV•sec ns ns V V t INF V ISENS1 t CAL t CONV INF AD AC t RD t RC V REFD V REFC –0.2 15.625 0.68 0.68 –2400 0.09 –0.11 125 1.00 1.00 300 300 0.1 –0.1 tRD , tRC tRD , tRC tRD , tRC tRD , tRC tRD , tRC tCONVINF tCONVINF tCAL tINF tINF Discharge signal for the integrator AD conversion signal Note : All signals are internals. 1.65V 0.85V 2.45V Integrator output

Rev.1.01 Aug 02, 2004 page 92 of 96 Fig. 85 VISENS1 -Count value characteristics of current integrator Table 30 Over current detector electrical characteristics (VCC = AVCC = 3.3V±2%, VSS =AV SS = 0V, Ta = –20 to 85 °C, f(XIN) = 4MHz, f(XCIN) = 32MHz) Limits Parameter Min. Typ. Max.Symbol UnitConditions Short current detect voltage error Over current detect voltage error Wake up detect voltage Short current detect time error Over current detect time error Wake up detect time 58.6 T.B.D. ±15 ±15 30.5 62.5 mV mV mV µs ms nD – b = TINF • VISENS1 AD n’D – b ’= TINF • VISENS1 AD + tRD • VISENS1 VISENS1 VREFD ISENS1 input voltage nC = TINF • (VISENS1 -c) AC n’C = TINF • (VISENS1 -c) AC + tRC • (VISENS1 -c) VREFC nREFD c b = TINF • b’ TINF-tRD • b’ c = vREFD • b nREFD -b Charge Discharge Count value

Rev.1.01 Aug 02, 2004 page 93 of 96 Table 31 Timing requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Reset input “L” pulse width External clock input cycle time External clock input “H ” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H ” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H ” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H ” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H ” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input set up time Serial I/O2 clock input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD-SCLK1 ) th(SCLK1 -RxD) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SIN2-SCLK2 ) th(SCLK2 -SIN2) Limits XIN cycles ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max.Symbol Unit Note :When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). SWITCHING CHARACTERISTICS Table 32 Switching characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H ” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H ” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) tWH (SCLK1 ) tWL (SCLK1 ) td (SCLK1 -TXD) tv (SCLK1 -TXD) tr (SCLK1 ) tf (SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td (SCLK2 -SOUT2 ) tv (SCLK2 -SOUT2 ) tf (SCLK2 ) tr (CMOS) tf (CMOS) Limits ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. t C (SCLK1 )/2–50 tC (SCLK1 )/2–50 –30 tC (SCLK2 )/2–240 tC (SCLK2 )/2–240 Typ. Symbol Unit Notes 1:For tWH (SCLK1 ), tWL (SCLK1 ), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2:When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is “0”. 3:The XOUT pin is excluded. Max. 350 400 Test conditions Fig. 87

Rev.1.01 Aug 02, 2004 page 94 of 96 Fig. 87 Circuit for measuring output switching characteristics Symbol Parameter Unit MULTI-MASTER I 2C-BUS BUS LINE CHARACTERISTICS Table 33 Multi-master I2C-BUS bus line characteristics Bus free time Hold time for START condition Hold time for SCL clock = “0” Rising time of both SCL and SDA signals Data hold time Hold time for SCL clock = “1” Falling time of both SCL and SDA signals Data setup time Setup time for repeated START condition Setup time for STOP condition tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO Min. Max. Min. Max. µs µs µs ns µs µs ns ns µs µs Standard clock modeHigh-speed clock mode Note:C b = total capacitance of 1 bus line Fig. 86 Timing diagram of multi-master I2C-BUS 4.7 4.0 4.7 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1Cb (Note) 0.6 20+0.1Cb (Note) 100 0.6 0.6 300 0.9 300 Test conditions Fig. 86 Measurement output pin 100pF CMOS output tBUF tHD:STA tHD:DTA tLOW tR tF tHIGH tsu:DAT tsu:STA tHD:STA tsu:STO SCL P S Sr P SDA S: START condition Sr: RESTART condition P: STOP condition

Rev.1.01 Aug 02, 2004 page 95 of 96 Fig. 88 Timing diagram 0.2VCC tf 0.2VCC 0.8VCC 0.8VCC tr tsu(RXD-SCLK1 ), tsu(SIN2-SCLK2 ) th(SCLK1 -RXD), th(SCLK2 -SIN2) tv(SCLK1 -TXD), tv(SCLK2 -SOUT2 ) tC (SCLK1 ), tC (SCLK2 ) tWL (SCLK1 ), tWL (SCLK2 ) tWH (SCLK1 ), tWH (SCLK2 ) TXD SOUT2 R XD SIN2 SCLK1 SCLK2 0.2VCC tWL (XIN) 0.8VCC tWH (XIN) tC (XIN) XIN 0.2VCC 0.8VCC tW (RESET) RESET 0.2VCC tWL (CNTR) 0.8VCC tWH (CNTR) tC (CNTR) 0.2VCC tWL (INT) 0.8VCC tWH (INT) INT0 - INT3 CNTR 0 CNTR 1 td(SCLK1 -TXD), td(SCLK2 -SOUT2 )

Rev.1.01 Aug 02, 2004 page 96 of 96 LQFP48-P-77-0.50 – Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 48P6Q-A Plastic 48pin 7✕ 7mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 1.0 ––M D 7.4 ––M E 7.4 8°0° 0.1 1.0 0.650.50.35 9.29.08.8 9.29.08.8 0.5 7.17.06.9 7.17.06.9 0.1750.1250.105 0.270.220.17 1.4 1.7 e e E H E 48 37 H D D M D M E A F y Recommended Mount Pad A1 A2 L Detail F Lp c Lp 0.45 0.6 0.25 0.75 0.08 x A3 e b x M

REVISION HISTORY

Rev. Date Description Page Summary

7517 Group Data Sheet

Words standardized: On-chip oscillator, A/D converter, Serial interface All pages 1.00 Apr. 28, 2004 1.01 Aug. 02, 2004

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