M37513EF-XXXHP

7513 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

7513 Group

DESCRIPTION

The 7513 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 7513 group has the LCD drive control circuit, the A-D/D-A converter, the UART, and the PWM as additional functions. The various microcomputers in the 7513 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 7513 group, refer to the section on group expansion.

FEATURES

(at 8MHz oscillation frequency) G Memory size (includes key input interrupt) G LCD drive control circuit G 2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) G Power dissipation (at 8 MHz oscillation frequency, at 5 V power source voltage) (at 32 kHz oscillation frequency, at 3 V power source voltage)

APPLICATIONS

Camera, Wireless phone, etc. Fig. 1 M37513EFFS pin configuration PIN CONFIGURATION (TOP VIEW) Package type : 100D0 (Window type ceramic LCC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 515253545556575859606162636465666768697071727374757677787980 100 M37513EFFS SEG 9 1/SEG 0/SEG 2/SEG 3/SEG 4/SEG SEG SEG SEG SEG SEG SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG C V 7/AN 6/AN 5/AN 4/AN 2/S CLK21 /AN 1/S OUT2 /AN 0/S IN2 /AN 7/DA 6/DA 5/CNTR 4/CNTR 3/RTP 2/RTP 1/PWM 0/PWM 6/S CLK1 5/T XD 4/R XD 3/φ/T OUT 2/INT 1/INT 0/ADTP7 C 2 VL2 VL3 COM 0 COM 1 COM 2 VREF AV SS VCC SEG 8 SEG 0 SEG 1 SEG 2 SEG 4 SEG 5 SEG 6 SEG 7 SEG 3 P72 P73 P71 P70/INT0 XCIN XCOUT XIN XOUT VSS P27 P26 P25 P24 P23 P21 P16 P22 P20 P17 RESET SEG SEG COM 3 7/S RDY1 3/S CLK22 /AN

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN CONFIGURATION (TOP VIEW) Fig. 2 M37513M8-XXXGP/M37513M8-XXXHP pin configuration M37513M8-XXXGP M37513M8-XXXHP 1 0 P 50/ P W M 0 P 47/ SR D Y P 57/ D A2 P 46/ SC L K P 44/ R XD P 43/φ/ TO U T P 42/ I N T2 P 54/ C N T R 0 P 52/ R T P0 P 53/ R T P1 P 51/ P W M 1 P 55/ C N T R 1 P 67/ A N 7 P 66/ A N 6 P 65/ A N 5 P 64/ A N 4 P 63/ SC L K 2/ A N 3 P 62/ SC L K 1/ A N 2 P 61/ SO U T 2/ A N 1 P 60/ SI N 2/ A N 0 P 45/TXD P 41/ I N T1 P 40/ A D T P 77 3 2 3 7 5 0 7 5 S E G 1 S E G S E G S E G S E G P 0/ S E G 1 P 1/ S E G 1 P 2/ S E G 2 P 3/ S E G 2 P 4/ S E G 2 P 5/ S E G 2 P 6/ S E G 2 P 7/ S E G 2 P 1/ S E G 2 P 2/ S E G 2 P 3/ S E G 2 P 4/ S E G 3 P 5/ S E G 3 P 6/ S E G 3 P 7/ S E G 3 P 2/ S E G 3 P 3/ S E G 3 P 0/ S E G 2 P 0/ S E G 3 P 1/ S E G 3 100 26 2 8 P 70/ I N T0 XIN XO U T VS S P 27 P 26 P 25 P 24 P 23 P 22 P 21 P 20 R E S E T XCOUT XCIN P 17 P 16 P71 P 72 P73 P74 P 75 P 76 P 15/ S E G 3 P 14/ S E G 3 VC C S E G 6 S E G 7 S E G 5 S E G 3 S E G 4 S E G 2 SEG 1 S E G 0 VREF AV SS C O M 2 COM 3 C O M 1 C O M 0 VL S E G 8 S E G 9 VL C 2 C 1 VL1 S E G 1 S E G 1 S E G 1 P 56/ D A1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3 Functional block diagram Key input/key-on wake-up interrupt INT1,INT2 CNTR 0,CNTR DA ADT Data bus C P U A X Y S PC H PC L PSRESET VCC VSS Reset input ( 5 V ) ( 0 V ) R O M R A M LCD display RAM (20 bytes) I/O port P5 P4(8) I/O port P4 I/O port P2 P2(8) I/O port P0 P0(8) I/O port P1 P1(8) P6(8) I/O port P7 P7(8) Output port P3 P3(8) I/O port P6 P5(8) Sub-clock input Sub-clock output X CIN X COUT Clock generating circuitX IN OUT X Main clock input Main clock output COUT X X CIN Sub-clock output Sub-clock input SI/O1 (8) VREF AV SS A-D converter (10) Timer X(16)Timer Y(16) Timer 1(8) Timer 2(8)Timer 3(8) LCD drive control circuit V C C V V COM COM COM COM SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG φ X CIN COUT X SI/O2(8) Watchdog timer Reset PWM(8) φ INT0 D-A2 D-A1 Real time port function DA T OUT

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 1 Pin description (1) VCC , VSS FunctionPin Name Function except a port function

• LCD segment output pins Power source •Apply voltage of 2.2 V to 5.5 V to VCC , and 0 V to VSS . VREF AV SS RESET XIN XOUT VL1–VL3 C 1, C2 COM 0–COM 3 SEG 0–SEG 17 P00/SEG 26– P07/SEG 33 P10/SEG 34– P15/SEG 39 P16, P17 P20 – P27 P30/SEG 18 – P37/SEG 25 Analog refer- ence voltage Analog power source Reset input Clock input Clock output LCD power source Charge-pump capacitor pin Common output Segment output I/O port P0 I/O port P1 I/O port P2 Output port P3
• Reference voltage input pin for A-D converter and D-A converter.
• GND input pin for A-D converter and D-A converter.
• Connect to VSS .
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
• Input 0 – VL3 voltage to LCD.
• External capacitor pins for a voltage multiplier (3 times) of LCD contorl.
• LCD common output pins.
• COM 2 and COM 3 are not used at 1/2 duty ratio.
• COM 3 is not used at 1/3 duty ratio.
• LCD segment output pins.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• I/O direction register allows each 8-bit pin to be pro- grammed as either input or output.
• 6-bit I/O port with same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• I/O direction register allows each 6-bit pin to be pro- grammed as either input or output.
• 2-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port with same function as P1 6 and P17.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• 8-bit output port with same function as port P0.
• CMOS 3-state output structure.
• Port output control is enabled.
• Key input (key-on wake-up) interrupt input pins
• LCD segment output pins

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 2 Pin description (2) FunctionPin Name Function except a port function

• A-D trigger input pin
• Interrupt input pin P40/ADT P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1 , P47/SRDY1 P50/PWM 0, P51/PWM 1 P52/RTP0, P53/RTP1 P54/CNTR 0, P55/CNTR 1 P56/DA1, P57/DA2 P6 0/AN0/SIN2, P6 1/AN1/SOUT2, P6 2/AN2/SCLK21, P6 3/AN3/SCLK22 P64/AN4– P67/AN7 P70/INT0 P71–P7 7 XCOUT XCIN I/O port P4 I/O port P5 I/O port P6 Input port P7 I/O port P7 Sub-clock output Sub-clock input
• 1-bit I/O port with same function as P16 and P17.
• CMOS compatible input level.
• N-channel open-drain output structure.
• 7-bit I/O port with same function as P16 and P17.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• 8-bit I/O port with same function as P16 and P17.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• 8-bit I/O port with same function as P1 6 and P17.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• 1-bit I/O port.
• CMOS compatible input level.
• 7-bit I/O port with same function as P1 6 and P17.
• CMOS compatible input level.
• N-channel open-drain output structure.
• Sub-clock generating circuit I/O pins. (Connect a resonator. External clock cannot be used.)
• Interrupt input pins
• φ clock output pin
• Timer 2 output pin
• Serial I/O1 I/O pins
• PWM function pins
• Real time port function pins
• Timer X, Y function pins
• D-A conversion output pins
• A-D conversion input pins
• Serial I/O2 I/O pins
• A-D conversion input pins
• Interrupt input pin

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 4 Part numbering M37513 M 8 – XXX HPProduct ROM/PROM size A B C D E F : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M E : Mask ROM version : EPROM or One Time PROM version RAM size M37513M8-XXXGP/HP M37513EFGP/HP/FS ROM number Omitted in One Time PROM version shipped in blank and EPROM version. Package type HP GP FS : 100PFB-A package : 100P6Q-A package : 100D0 package : 1024 byte : 2048 bytes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Mitsubishi plans to expand the 7513 group as follows: Memory Type Support for Mask ROM, One Time PROM, and EPROM versions Memory Size Package Currently supported products are listed below. Memory Expansion Plan RemarksPackageProduct As of Nov. 2000 RAM size (bytes) 32768 (32638) (P) ROM size (bytes) ROM size for User in ( ) Fig. 5 Memory expansion plan Table 3 List of supported products M37513M8-XXXHP M37513M8-XXXGP M37513EFHP M37513EFGP M37513EFFS 1024 100PFB-A 100P6Q-A 100PFB-A 100P6Q-A 100D0 Mask ROM version Mask ROM version One Time PROM version (blank) One Time PROM version (blank) EPROM version Note: Products under development or planning: the development schedule and specifications may be revised without notice. R O M s i z e ( b y t e s ) 3 2 K 2 8 K 24 K 2 0 K 16 K 1 2 K 8 K 4 K 256 384 512 640 768 896 1 0 2 4192 RAM size (bytes) 0 4 8 19201 1 5 21 2 8 01 4 0 81 5 3 61 6 6 41 7 9 2 3 6 K 4 0 K 44 K 4 8 K 5 2 K 5 6 K 6 0 K Mass production M37513M8 Under development M37513EF 204861440 (61310)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Central Processing Unit (CPU) The 7513 group uses the standard 740 Family instruction set. Re- fer to the table of 740 Series addressing modes and machine instructions or the 740 Series Software Manual for details on the instruction set. Machine-resident 740 Series instructions are as follows: The FST and SLW instructions cannot be used. The STP , WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. A Accumulator b7 b0 b7 b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counter PCH N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig. 6 740 Family CPU register structure

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 7 Register push and pop at interrupt generation and subroutine call N o t C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s Execute JSR O n - g o i n g R o u t i n e M S P C H ) S S M S P C E x e c u t e R T S (PCL)M ( S ) S S S S S S P C H )M S S u b r o u t i n e POP return address from stack P u s h r e t u r n a d d r e s s o n s t a c k M S P S Execute RTI (PS) M (S) S S (S) (S) + 1 Interrupt Service Routine P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M (S) (PC H ) (S) (S) – 1 M (S) (PC L) S S (PCL)M ( S ) (S) (S) + 1 (S) (S) + 1 (PCH )M ( S ) P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m t o F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e Interrupt disable flag is “0”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.
• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag Z flag I flag D flag B flag T flag V flag N flag SEC CLC SEI CLI SED CLD SET CLT CLV _ _

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B 16. Fig. 8 Structure of CPU mode register N ot available P r o c e s s o r m o d e b i t s b S i n g l e c h i p m o d e S t a c k p a g e s e l e c t i o n b i t p a g e p a g e N o t u s e d r e t u r n s w h e n r e a d D o n o t w r i t e t o t h i s b i t S u b c l o c k XC I N - XC O U s t o p b i t S t o p p e d O s c i l l a t i n g M a i n c l o c k XI N - XO U s t o p b i t O s c i l l a t i n g S t o p p e d M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t XI N / h i g h s p e e d m o d e XI N / m i d d l e s p e e d m o d e I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t XI N - XO U T s e l e c t e d m i d d l e h i g h s p e e d m o d e XC I N - XC O U T s e l e c t e d l o w s p e e d m o d e CPU mode register (CPUM (CM) : address 003B16) b 7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 9 Memory map diagram 192 256 384 512 640 768 896 1024 1536 2048 00FF 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 063F16 083F16 RAM area RAM size (bytes) Address XXXX 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F000 E00016 D000 16 C000 16 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E080 16 D080 16 C080 16 B080 16 A080 16 908016 808016 708016 608016 508016 408016 308016 208016 108016 ROM area ROM size (bytes) Address YYYY 16 Address ZZZZ 16 010016 000016 004016 084016 FF0016 FFDC 16 FFFE 16 FFFF 16 XXXX 16 YYYY 16 ZZZZ 16 RAM ROM 005416 Reserved area SFR area Not used Interrupt vector area Reserved ROM area (128 bytes) Zero page Special page LCD display RAM area Reserved ROM area

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 10 Memory map of special function register (SFR) 0 0 0 01 0 0 1 0 0 2 000316 000416 0 0 5 000616 0 0 7 0 0 8 0 0 9 0 0 0 0 0 0 C 1 0 0 D 1 0 0 0 0 001016 0 1 1 001216 0 1 3 001416 0 1 5 001616 0 1 7 001816 0 1 9 001A16 001B16 0 1 C 1 0 1 D 1 001E16 0 1 P o r t P 0 ( P 0 ) P o r t P 1 ( P 1 ) Port P1 output control register (P1D) P o r t P 2 ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) P o r t P 3 ( P 3 ) P o r t P 4 ( P 4 ) Port P4 direction register (P4D) P o r t P 5 ( P 5 ) Port P5 direction register (P5D) P o r t P 6 ( P 6 ) Port P6 direction register (P6D) P o r t P 7 ( P 7 ) Port P7 direction register (P7D) Serial I/O 1 status register (SIO1STS) S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) UART control register (UARTCON) Baud rate generator (BRG) PULL register A (PULLA) PULL register B (PULLB) T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r(TB/RB) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) P o r t P 3 o u t p u t c o n t r o l r e g i s t e r ( P 3 C ) K e y i n p u t c o n t r o l r e g i s t e r ( K I C ) Serial I/O 2 control register (SIO2CON) R e s e r v e d a r e a S e r i a l I / O 2 r e g i s t e r ( S I O 2 ) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 0 2 002C 16 002D 16 0 2 0 2 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 0 3 0 3

6 Interrupt control register 2 (ICON2)

Timer 3 (T3) Timer X mode register (TXM) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Timer X (low ) (TXL) Timer Y (low ) (TYL) Timer 1 (T1) Timer 2 (T2) Timer X (high) (TXH) Timer Y (high) (TYH) Timer Y mode register (TYM) T i m e r 1 2 3 m o d e r e g i s t e r ( T 1 2 3 M ) TO U T/φ o u t p u t c o n t r o l r e g i s t e r ( C K O U T ) Segment output enable register (SEG) LCD mode register (LM) A-D control register (ADCON) A-D conversion register (low-order) (ADL) P W M c o n t r o l r e g i s t e r ( P W M C O N ) PWM prescaler (PREPWM) P W M r e g i s t e r ( P W M ) A - D c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( A D H ) D - A 1 c o n v e r s i o n r e g i s t e r ( D A 1 ) D - A 2 c o n v e r s i o n r e g i s t e r ( D A 2 ) D -A control register (DACON) W atchdog timer control register (WDTCON)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The I/O ports have direction registers which determine the input/ output direction of each individual pin. (P00–P07 and P10–P15 use bit 0 of port P0, P1 direction registers respectively.) When “1” is written to that bit, that pin becomes an output pin. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating and the value of that pin can be read. If a pin set to input is written to, only the port output latch is written to and the pin re- mains floating. Port P3 Output Control Register Bit 0 of the port P3 output control register (address 000716) en- ables control of the output of ports P30 to P37. When the bit is set to “1”, the port output function is valid. When resetting, bit 0 of the port P3 output control register is set to “0” (the port output function is invalid) and ports P3 0 to P37 are pulled up. Pull-up Control By setting the PULL register A (address 001616) or the PULL reg- ister B (address 001716), ports P1, P2, P4 to P6 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. The PULL register A setting is invalid for pins set to segment out- put on the segment output enable register. Fig. 11 Structure of PULL register A and PULL register B Not used P10–P13 pull-up P14, P15 pull-up P16, P17 pull-up P20–P23 pull-up P24–P27 pull-up PULL register A (PULLA : address 001616) b7 b0 P41–P43 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60–P63 pull-up P64–P67 pull-up Not used (return “0” when read) 0 : No pull-up 1 : Pull-up PULL register B (PULLB : address 001716) b7 b0 Note :The contents of PULL register A and PULL register B do not affect ports programmed as the output port.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Diagram No.Related SFRsInput/OutputNamePin Non-Port FunctionI/O Format Table 6 List of I/O port function (1) P00/SEG 26– P07/SEG 33 P10/SEG 34– P15/SEG 39 P16 , P17 P20–P27 P30/SEG 18– P37/SEG 25 P40/ADT P41/INT1, P42/INT2 P43/φ/TOUT P44/RX D, P45/TX D, P46/SCLK1 , P47/SRDY1 P50/PWM 0, P51/PWM 1 P52/RTP0, P53/RTP1 P54/CNTR 0 P55/CNTR 1 P56/DA1 P57/DA2 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Input/output, byte unit Input/output, 6-bit unit Input/output, individual bits Input/output, individual bits Output Input/output, individual bits Input/output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD segment output LCD segment output Key input (key-on wake-up) interrupt input LCD segment output A-D trigger input External interrupt input External interrupt input Timer output φ output Serial I/O1 function I/O Real time port function output Timer X function I/O Timer Y function input Segment output enable register PULL register A Segment output enable register PULL register A PULL register A Interrupt control register2 Key input control register Segment output enable register A-D control register Interrupt edge selection register PULL register B Interrupt edge selection register PULL register B Timer 123 mode register TOUT /φ output control register PULL register B Serial I/O1 control register Serial I/O1 status register UART control register PULL register B PWM control register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B D-A control register A-D control register PULL register B D-A control register (1) (2) (3) (4) (6) (6) (5) (15) (6) (14) (7) (8) (9) (10) (12) (11) (13) (16) (17) (17) P3 output enable register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Pin Name I/O Format Non-Port Function Related SFR S Diagram No.Input/Output Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate po- tential, a current will flow VCC to VSS through the input-stage gate. Table 7 List of I/O port function (2) P60/SIN2/AN0 P61/SOUT2 / AN 1 P62/SCLK21 / AN 2 P63/SCLK22 / AN 3 P64/AN4– P67/AN7 P70/INT0 P71–P77 COM 0–COM 3 SEG 0–SEG 17 Port P6 Port P7 Common Segment Input/ output, individual bits Input Input/ output, individual bits Output Output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level N-channel open-drain output LCD common output LCD segment output A-D conversion input Serial I/O2 function I/O A-D conversion input External interrupt input A-D control register Serial I/O2 control register A-D control register Interrupt edge selection register LCD mode register (19) (20) (21) (22) (18) (25) (15) (23) (24)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 12 Port block diagram (1) ( 1 ) P o r t s P 01– P 07 Port direction register Data bus Port latch S e g m e n t d a t a L C D d r i v e t i m i n g Port/Segment S e g m e n t / P o r t Segment Port V L1/VSS VL2/VL3/VCC Interface logic level shift circuit P o r t d i r e c t i o n r e g i s t e r ( 2 ) P o r t P 00 Port direction register D a t a b u s Port latch S e g m e n t d a t a LCD drive timing P o r t / S e g m e n t S e g m e n t / P o r t Segment P o r t V L1/VSS VL 2/ VL 3/ VC C I n t e r f a c e l o g i c l e v e l s h i f t c i r c u i t D i r e c t i o n r e g i s t e r (5) Port P3 O u t p u t c o n t r o l Data bus P o r t l a t c h S e g m e n t d a t a L C D d r i v e t i m i n g P o r t / S e g m e n t Segment/Port S e g m e n t Port V L1/VSS VL2/VL3/VCC Interface logic level shift circuit ( 3 ) P o r t s P 11– P 15 Port direction register D a t a b u s P o r t l a t c h Segment data L C D d r i v e t i m i n g Port/Segment Segment/Port Segment Port Pull-up VL1/VSS VL2/VL3/VCC Interface logic level shift circuit P o r t d i r e c t i o n r e g i s t e r (4) Port P10 Port direction register D a t a b u s P o r t l a t c h Segment data LCD drive timing Port/Segment Segment/Port Segment Port Pull-up VL1/VSS VL 2/ VL 3/ VC C Interface logic level shift circuit Direction register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 13 Port block diagram (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (8) Port P45 (9) Port P46 (10) Port P47 Data bus Serial I/O1 enable bit Transmission enable bit Serial I/O1 output P45/TxD P-channel output disable bit Port latch Direction register Pull-up control Serial I/O1 ready output Data bus Port latch Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Pull-up control (11) Ports P52, P53 Data bus Port latch Real time control bit Real time port data Direction register Pull-up control Serial I/O1 clock selection bit Data bus Serial I/O1 clock outupt Serial I/O1 clock input Serial I/O1 mode selection bit Serial I/O1 enable bit Port latch Direction register Serial I/O1 enable bit Pull-up control (7) Port P44(6) Ports P16, P17, P2, P41, P42 Except P16, P17 Data bus Direction register Port latch Pull-up control Key input interrupt input INT1, INT2 interrupt input Serial I/O1 enable bit Reception enable bit Serial I/O1 input Port latch Pull-up control Data bus Direction register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 14 Port block diagram (3) (14) Port P43 Port latchData bus TOUT /φ output control Timer output Direction register Pull-up control φ output TOUT /φ selection bit (15) Ports P40, P71–P77 Port latchData bus Direction register (16) Port P55 Data bus Direction register Port latch Pull-up control CNTR 1 interrupt input (17) Ports P56, P57 Data bus Direction register Port latch Pull-up control D-A conversion output A-D trigger input Except P71 to P77 D-A1, D-A2 output enable bit VREF input switch VREF input selection bit Except P57 (12) Ports P50,P51 Data bus Port latch PWM function enable bit PWM output Direction register Pull-up control (13) Port P54 Port latchData bus Pulse output mode Timer output CNTR 0 interrupt input Direction register Pull-up control

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 15 Port block diagram (4) ( 2 0 ) P o r t P 61 (21) Port P62 (22) Port P63 Data bus Serial I/O2 output Port latch Serial I/O2 transmit completion signal Synchronous clock selection bit Serial I/O2 port selection bit Direction register P u l l - u p c o n t r o l Analog input pin selection bit A-D conversion input P 61/ SO U T

2 P - c h a n n e l o u t p u t d i s a b l e b i t

( 2 3 ) C O M 0– C O M 3 (24) SEG0–SEG 17 VL VL2 VL VSS VL 2/ VL VL 1/ VS S T h e g a t e i n p u t s i g n a l o f e a c h t r a n s i s t o r i s c o n t r o l l e d b y t h e L C D d u t y r a t i o a n d t h e b i a s v a l u e T h e v o l t a g e a p p l i e d t o t h e s o u r c e s o f P c h a n n e l a n d N c h a n n e l t r a n s i s t o r s i s t h e c o n t r o l l e d v o l t a g e b y t h e b i a s v a l u e (25) Port P70 Data bus I N T0 i n p u t S y n c h r o n o u s c l o c k s e l e c t i o n b i t D a t a b u s Serial I/O2 clock output S e r i a l I / O 2 c l o c k i n p u t Port latch Direction register D a t a b u s Port latch D i r e c t i o n r e g i s t e r S y n c h r o n o u s c l o c k s e l e c t i o n b i t S e r i a l I O p o r t s e l e c t i o n b i t S y n c h r o n o u s c l o c k o u t p u t p i n s e l e c t i o n b i t Pull-up control Synchronous clock output pin selection bit S e r i a l I / O 2 p o r t s e l e c t i o n b i t Pull-up control A n a l o g i n p u t p i n s e l e c t i o n b i t A-D conversion input S e r i a l I / O 2 c l o c k o u t p u t Analog input pin selection bit A - D c o n v e r s i o n i n p u t ( 1 8 ) P o r t s P 64– P 67 A n a l o g i n p u t p i n s e l e c t i o n b i t A - D c o n v e r s i o n i n p u t D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r P u l l - u p c o n t r o l ( 1 9 ) P o r t P 60 D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r P u l l - u p c o n t r o l Serial I/O2 input A-D conversion input A n a l o g i n p u t p i n s e l e c t i o n b i t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Interrupts occur by seventeen sources: seven external, nine inter- nal, and one software. Interrupt Control Each interrupt except the BRK instruction interrupt has both an in- terrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts ex- cept the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time, the interrupt with highest prior- ity is accepted first. Interrupt Operation Upon acceptance of an interrupt the following operations are auto- matically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vec- tor table into the program counter. I Notes When setting the followings, the interrupt request bit may be set to “1”.

• When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A 16) Timer X mode register (address 2716) Timer Y mode register (address 2816)
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: A-D control register (address 003116) Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Table 8 Interrupt vector addresses and priority RemarksInterrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmit shift or when transmis- sion buffer is empty Interrupt Source LowHigh Priority Vector Addresses (Note 1) Reset (Note 2) INT0 INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 2 Timer 3 CNTR CNTR 1 Timer 1 INT2 Serial I/O2 Key input (Key-on wake-up) ADT A-D conversion BRK instruction FFFD 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 FFFC 16 FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR 1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At completion of serial I/O2 data transmission or reception At falling of conjunction of input level for port P2 (at input mode) At either rising or falling edge of ADT input At completion of A-D conversion At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (valid at falling) External interrupt (Valid when ADT interrupt is selected Valid when A-D interrupt is se- lected Non-maskable software interrupt

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 16 Interrupt control Fig. 17 Structure of interrupt-related registers b7 b0 Interrupt edge selection register I N T0 i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t A D T i n t e r r u p t e d g e s e l e c t i o n b i t N o t u s e d r e t u r n w h e n r e a d (INTEDGE : address 003A16) I n t e r r u p t r e q u e s t r e g i s t e r 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit I n t e r r u p t c o n t r o l r e g i s t e r 1 I N T0 i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t S e r i a l I O r e c e i v e i n t e r r u p t e n a b l e b i t S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t 0 : N o interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C 16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit Serial I/O2 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns “0” when read) ( I R E Q 2 : a d d r e s s 0 0 3 D 1 I n t e r r u p t c o n t r o l r e g i s t e r 2 C N T R 0 i n t e r r u p t e n a b l e b i t C N T R 1 i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t S e r i a l I O i n t e r r u p t e n a b l e b i t K e y i n p u t i n t e r r u p t e n a b l e b i t A D T A D c o n v e r s i o n i n t e r r u p t e n a b l e b i t N o t u s e d r e t u r n s w h e n r e a d D o n o t w r i t e t o t h i s b i t 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16) 0 : F a l l i n g e d g e a c t i v e R i s i n g e d g e a c t i v e b 7 b 0 b 7 b 0 b7 b 0 b7 b0 K e y i n p u t c o n t r o l r e g i s t e r P20 trigger valid bit P21 trigger valid bit P22 trigger valid bit P23 trigger valid bit P24 trigger valid bit P25 trigger valid bit P26 trigger valid bit P27 trigger valid bit 0 : Trigger invalid 1 : Trigger valid ( K I C : a d d r e s s 0 0 1 51 b7 b0 Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge selection bit (active edge switch bit) or the interrupt source selection bit to “1”. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Key Input Interrupt (Key-on wake-up) A Key-on wake up interrupt request is generated by applying a falling edge to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P2 0–P23. Fig. 18 Connection example when using key input interrupt and port P2 block diagram ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ Port P20 latch Port P20 direction register = “0” Port P21 latch Port P21 direction register = “0” Port P22 latch Port P22 direction register = “0” Port P23 latch Port P23 direction register = “0” Port P24 latch Port P24 direction register = “1” Port P25 latch Port P25 direction register = “1” Port P26 latch Port P27 latch Port P27 direction register = “1” Port P20 input Port P2 input Port P22 input Port P23 input Port P24 output Port P25 output Port P26 output Port P27 output PULLA register Bit 2 = “1” Port P2 input reading circuit Key input interrupt request Port PXx “L” level output ✽ P-channel transistor for pull-up ✽✽ CMOS output buffer Key input control register = “1” Key input control register = “1” Key input control register = “1” Key input control register = “1” Key input control register = “1” Key input control register = “1” Key input control register = “1” Port P26 direction register = “1” Key input control register = “1”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The 7513 group has five timers: timer X, timer Y , timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Fig. 19 Timer block diagram CNTR 0 active edge switch bit T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t R e a l t i m e p o r t c o n t r o l b i t “1” P55/CNTR 1 “0” C N T R 1 a c t i v e e d g e s w i t c h b i t “10” T i m e r Y s t o p c o n t r o l b i t F a l l i n g e d g e d e t e c t i o n Period measurement mode Timer Y interrupt request P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e Rising edge detection T i m e r Y o p e r a t i n g m o d e b i t T i m e r X i n t e r r u p t r e q u e s tTimer X mode register write signal P54/CNTR 0 Q Q T S P54 direction register P u l s e o u t p u t m o d e P54 latch Timer X stop control bit “ 0 ” “1” T i m e r X w r i t e c o n t r o l b i t Q D L a t c h Q D L a t c h “1” “ 0 ” “1” 1 0 ”T i m e r X o p e r a t i n g m o d e b i t s f ( XI N ) / 1 6 f XCI N ) i n l o w s p e e d m o d e Pulse width measurement mode C N T R 0 a c t i v e e d g e s w i t c h b i t P u l s e o u t p u t m o d e Q Q T S “ 0 ” P 43 d i r e c t i o n r e g i s t e r P 43 l a t c h“1” TOUT output active edge switch bit Timer 2 write control bit “ 0 ” 1 ” TOUT output control bit “1” P43/φ/TOUT XCIN T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t “0” “ 1 ” T i m e r 2 i n t e r r u p t r e q u e s t Timer 3 interrupt request T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t Timer 1 interrupt request D a t a b u s f ( XI N ) / 1 6 ( f ( XC I N ) / 1 6 i n l o w - s p e e d m o d e * ) CNTR 0 interrupt request T i m e r Y o p e r a t i n g m o d e b i t “ 1 1 ” R e a l t i m e p o r t c o n t r o l b i t P52 latch R e a l t i m e p o r t c o n t r o l b i t P 53 l a t c h Timer Y (low) (8) T i m e r Y h i g h Timer 3 latch (8) Timer 3 (8) Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) Timer X (low) (8) Timer X (high) (8) Timer X (low) latch (8) Timer X (high) latch (8) T i m e r Y l o w l a t c h i m e r Y h i g h l a t c h TO U T o u t p u t c o n t r o l b i t “ 0 ” 0 ” 0 ” P 52 P 53 P 52 d i r e c t i o n r e g i s t e r P53 direction register P 52 d a t a f o r r e a l t i m e p o r t P 53 d a t a f o r r e a l t i m e p o r t f X I N XCI N ) i n l o w s p e e d m o d e f X I N f XCI N ) i n l o w s p e e d m o d e f(XIN)/16 (f(XCIN)/16 in low-speed mode*) C N T R 1 i n t e r r u p t r e q u e s t * φ = XCIN divided by 2 in low-speed mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse Output Mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR 0 pin to input. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR 0 pin to input. (4) Pulse Width Measurement Mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR 0 active edge switch bit is “0”, the timer counts while the in- put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the port shared with tha CNTR0 pin to input. G Timer X write control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. I Notes on CNTR0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. G Real time port control While the real time port function is valid, data for the real time port are output from ports P52 and P5 3 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1”, data are output without the timer X.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer Before using this function, set the corresponding port direction registers to output mode. Fig. 20 Structure of timer X mode register Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid 2 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR 0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H ” output in pulse output mode Measure “H ” pulse width in pulse width measurement mode Falling edge active for CNTR 0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNTR 0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period Measurement Mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Ex- cept for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the port shared with the CNTR1 pin to input. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR 1 pin to input. (4) Pulse Width HL Continuously Measurement Mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the port shared with the CNTR 1 pin to input. I Notes on CNTR1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 21 Structure of timer Y mode register Timer Y mode register (TYM : address 002816) b7 b0 Not used (return “0” when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR 1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. G Timer 2 write control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. G Timer 2 output control When the timer 2 (T OUT ) is output enabled, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the port shared with the TOUT pin to the output. I Notes on timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 22 Structure of timer 123 mode register Timer 123 mode register (T123M :address 002916) * I n t e r n a l c l o c k φ is XCIN/2 in the low-speed mode. b 7 b 0 T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t f XI N ) o r f XC I N ) i n l o w s p e e d m o d e f XC I N ) TO U T o u t p u t a c t i v e e d g e s w i t c h b i t S t a r t a t H o u t p u t S t a r t a t L o u t p u t TO U T/φ output control bit 0 : TOUT /φ output disabled 1 : TOUT /φ output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f XC I N ) i n l o w s p e e d m o d e T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f XC I N ) i n l o w s p e e d m o d e N ot used (return “0” when read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 can be selected by setting the mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer registers. Fig. 23 Block diagram of clock synchronous serial I/O1 Fig. 24 Operation of clock synchronous serial I/O1 function P46/SCLK P47/SRDY1 P44/RX D P45/TX D f(XIN) 1/4 F/F Serial I/O1 status register Serial I/O1 control register Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 BRG count source selection bit Clock control circuitFalling-edge detector Data bus Address 001816 Shift clock Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit buffer register Transmit shift register (f(XCIN) in low-speed mode) Receive enable signal SRDY1 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TX D Serial input RX D Write signal to receive/transmit buffer register (address 001816) Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the T X D pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS f(XIN) O E PE FE D ata bus R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R eceive shift register R eceive buffer full flag (RBF) R eceive interrupt request (RI) B a u d r a t e g e n e r a t o r Frequency division ratio 1/(n+1) A d d r e s s 0 0 1 C 1 S T S P P A g e n e r a t o r Transmit buffer register D ata bus Transmit shift register Address 001816 Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 S T d e t e c t o r S P d e t e c t o r UART control register A d d r e s s 0 0 1 B1 Ch aracter length selection bit Address 001A16 BRG count source selection bit T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t Serial I/O 1 synchronous clock selection bit C l o c k c o n t r o l c i r c u i t C h a r a c t e r l e n g t h s e l e c t i o n b i t b i t s b i t s Serial I/O1 control registe r P46/SCL K S e r i a l I / O 1 s t a t u s r e g i s t e r P 44/ R XD P45/TXD (f(XCIN) in low-speed mode) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 25 Block diagram of UART serial I/O1 Fig. 26 Operation of UART serial I/O1 function TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 ✽ STD 0 D 1 SP D 0 D 1ST SP Transmit buffer write signal ✽ Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1 :Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2 :The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 :The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 :After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TX D Serial input RX D Receive buffer read signal Transmit or receive clock

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a charac- ter bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE. Writ- ing “0” to the serial I/O1 enable bit (SIOE) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to “0” at re- set, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift register shift comple- tion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON) ]001B16 This is a 5 bit register containing four control bits, which are valid when UART is selected and set the data format of an data re- ceiver/transfer, and one control bit, which is always valid and sets the output structure of the P4 5/TXD pin. [Baud Rate Generator(BRG)] 001616 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. I Notes When setting the transmit enable bit to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 27 Structure of serial I/O1 control registers BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. S RDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin. 1: P47 pin operates as SRDY1 output pin. Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P4 4–P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P4 4–P47 operate as serial I/O pins) Serial I/O1 control register (SIO1CON : address 001A 16) b7 b0 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: OE U PE U FE =0 1: OE U PE U FE =1 Not used (returns “1” when read) Serial I/O1 status register (SIO1STS : address 0019 16) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TX D P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. When an internal clock is selected as the synchronous clock of the serial I/O2, either P6 2 or P63 can be selected as an output pin of the synchronous clock. In this case, the pin that is not selected as an output pin of the synchronous clock functions as a port. [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains 8 bits which control vari- ous serial I/O2 functions. Fig. 28 Structure of serial I/O2 control register Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock select bits 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 0 0: 1 0 1: 1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: S OUT2 ,SCLK21 /SCLK22 signal output P61/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Transfer direction selection bit 0: LSB first 1: MSB first Synchronous clock selection bit 0: External clock 1: Internal clock Synchronous clock output pin selection bit 0: S CLK21 1: SCLK22 b2 b1 b0 Do not set Fig. 29 Block diagram of serial I/O2 function f(XIN) “1” “0” “0” “1” “0” “1” S CLK2 (Note) Data bus Serial I/O2 interrupt request Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O shift register 2 (8) Synchronous circuit Synchronous clock selection bit External clock Internal synchronous clock select bits Divider P63 latch P63/SCLK22 P62/SCLK21 P61/SOUT2 P60/SIN2 P62 latch P61 latch (Note) Note: It is selected by the synchronous clock selection bit, the synchronous clock output pin selection bit, and the serial I/O port selection bit. (f(XCIN) in low-speed mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 30 Timing of serial I/O2 function D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Serial I/O2 register write signal (Note 2) Serial I/O2 interrupt request bit set 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. When the external clock is selected as the transfer clock, a content of the serial I/O shift register is continued to shift during inputting a transfer clock. The SOUT2 pin does not go to high impedance after transfer completion. Notes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PULSE WIDTH MODULATION (PWM) The 7513 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input di- vided by 2. Data Setting The PWM output pin also functions as ports P50 and P51. Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an “H ” by the PWM register. If PWM count source is f(X IN) and the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1)/f(X IN) = 51 ✕ (n+1) µ s (when f(XIN) = 5 MHz) Output pulse “H ” period = PWM period ✕ m/255 (when f(XIN) = 5 MHz) PWM Operation When at least either bit 1 (PWM0 output enable bit) or bit 2 (PWM1 output enable bit) of the PWM control register is set to “1”, opera- tion starts by initializing the PWM output circuit, and pulses are output starting at an “H ”. When one PWM output is enabled and that the other PWM output is enabled, PWM output which is en- abled to output later starts pulse output from halfway. When the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Fig. 31 Timing of PWM cycle Fig. 32 Block diagram of PWM function 51 ✕ m ✕ (n+1) 255 µs PWM output m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when f(XIN) = 5 MHz) D a t a b u s C ount source selection bit “0” “ 1 ” P W M p r e s c a l e r p r e l a t c h P W M r e g i s t e r p r e l a t c h P W M p r e s c a l e r l a t c h PWM register latch Transfer control circuit P W M c i r c u i t XI N P W M 0 e n a b l e b i t P o r t P 51 P W M p r e s c a l e r PWM 1 enable bit Port P50

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 34 PWM output timing when PWM register or PWM prescaler is changed Fig. 33 Structure of PWM control register b7 b0 PWM control register (PWMCON : address 002B16) Count source selection bit 0 : f(XIN) 1 : f(XIN)/2 PWM 0 function enable bit 0 : PWM0 disabled 1 : PWM0 enabled PWM 1 function enable bit 0 : PWM1 disabled 1 : PWM1 enabled Not used (return “0” when read) T T2 CB T PWM register write signal PWM prescaler write signal (Changes from “A” to “B” during “H ” period) (Changes from “T” to “T2” during PWM period) PWM (internal) A B T C T2= stop PWM 0 function enable bit PWM 1 function enable bit PWM 0 output Port PortPWM 1 output Port stop Port When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [A-D Conversion Registers (ADL, ADH)] 0032 16, 003316 The A-D conversion registers are read-only registers that contain the result of an A-D conversion. During A-D conversion, do not read these registers. [A-D Control Register (ADCON)] 003116 The A-D control register controls the A-D conversion process. Bits 0 to 2 are analog input pin selection bits. Bit 3 is an A-D conver- sion completion bit and “0” during A-D conversion, then changes to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to “1”, A-D conver- sion is started even by a rising edge or falling edge of an ADT input. Set ports which share with ADT pin to input when using an A-D external trigger. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AV SS and VREF , and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports P67/AN7–P6 0/ AN 0, and inputs it to the comparator. [Comparator and Control Circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(X IN) to at least 500 kHz during A-D conversion. Use a clock divided the main clock XIN as the internal clock φ. Fig. 36 A-D converter block diagram Fig. 35 Structure of A-D control register Data bus A-D control register A-D conversion register Resistor ladder AV SS Comparater ADT/A-D interrupt request b7 b0 A-D control register P60/SIN2/AN0 P61/SOUT2 /AN1 P62/SCLK21 /AN2 P63/SCLK22 /AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P40/ADT VREF A-D conversion register (H) (L) P56/DA1 Channel selector A - D c o n t r o l r e g i s t e r A D C O N a d d r e s s A n a l o g i n p u t p i n s e l e c t i o n b i t s P SI N A N 0 P 61/ SO U T A N 1 P 62/ SC L K A N 2 P 63/ SC L K A N 3 P 64/ A N 4 P 65/ A N 5 P 66/ A N 6 P 67/ A N 7 A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d VR E F i n p u t s w i t c h b i t O F F O N A D e x t e r n a l t r i g g e r v a l i d b i t A D e x t e r n a l t r i g g e r i n v a l i d A D e x t e r n a l t r i g g e r v a l i d I n t e r r u p t s o u r c e s e l e c t i o n b i t I n t e r r u p t r e q u e s t a t A D c o n v e r s i o n c o m p l e t e d I n t e r r u p t r e q u e s t a t A D T i n p u t r i s i n g o r f a l l i n g R e f e r e n c e v o l t a g e i n p u t s e l e c t i o n b i t VR E F P 56/ D b 7 b 0 b 7 b9 b8 b7 b6 b5 b4 b3 b2 b9 b8 b7 b6 b5 b4 b3 b2

• 8 - b i t r e a d ( R e a d o n l y a d d r e s s 0 0 3 21 6. ) A-D conversion register (low-order) (ADL: Address 003216)
• 1 0 - b i t r e a d ( R e a d a d d r e s s 0 0 3 31 6 f i r s t . ) N ote: High-order 6 bits of address 003316 becomes “0” at reading. b1 b0 A-D conversion register (low-order) (ADL: Address 003216) A-D conversion register (high-order) (ADH: Address 003316) b7 b 0 b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The 7513 group has an on-chip D-A converter with 8-bit resolution and 2 channels (DAi (i=1, 2)). The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from DAi pin. When using the D-A converter, the corresponding port direction register bit (P5 6/DA1, P57/DA2) should be set to “0” (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V=V REF ✕ n/256 (n=0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to “0016”, the DAi output enable bits are cleared to “0”, and DAi pin goes to high impedance state. The DA output is not buffered, so connect an external buffer when driving a low-impedance load. Fig. 37 Structure of D-A control register Fig. 38 Block diagram of D-A converter Fig. 39 A-D converter, D-A converter block diagram DA 1 output enable bit/DA1 VREF ON/OFF switch DA 2 output enable bit/DA2 VREF ON/OFF switch Not used (return “0” when read) 0 : Output disabled/OFF 1 : Output enabled/ON b7 b0 D-A control register (DACON : address 003616) VREF Resistor ladder A-D conversion register (10 bits) D-A1 conversion register (8 bits) D-A2 conversion register (8 bits) R-2R resistor ladder R-2R resistor ladder D-A2 output D-A1 output (P56) (P57) D-A2 output enable switch D-A1 output enable switch VREF input ON/OFF switch Internal: D-A output External: VREF Reference voltage input select switch D-A1 VREF ON/OFF switch D-A2 VREF ON/OFF switch D-A1 conversion register (DA1: address 003416) D-A2 conversion register (DA2: address 0035 16) P56/DA1 P57/DA2 Data bus D-A i conversion register (8) R-2R resistor ladder DA i output enable bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The 7513 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. G LCD display RAM G Segment output enable register G LCD mode register G Voltage multiplier G Selector G Timing controller G Common driver G Segment driver G Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Fig. 40 Structure of LCD mode register Up to 160 pixels can be controlled for LCD display . When the LCD enable bit is set to “1” after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 9 Maximum number of display pixels at each duty ratio Duty ratio Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits Segment output enable bit 0 0 : Output ports P30–P35 1 : Segment output SEG18–SEG 23 Segment output enable bit 1 0 : Output ports P3 6, P37 1 : Segment output SEG24,SEG 25 Segment output enable bit 2 0 : I/O ports P0 0–P05 1 : Segment output SEG26–SEG 31 Segment output enable bit 3 0 : I/O ports P0 6,P07 1 : Segment output SEG32,SEG 33 Segment output enable bit 4 0 : I/O port P1 1 : Segment output SEG34 Segment output enable bit 5 0 : I/O ports P1 1–P15 1 : Segment output SEG35–SEG 39 LCD output enable bit 0 : Disable 1 : Enable Not used (return “0” when read) (Do not write “1” to this bit) Segment output enable register (SEG : address 0038 16) b7 b0 LCD mode register (LM : address 003916) Duty ratio selection bits 0 0 : Not used 0 1 : 2 duty (use COM0, COM1) 1 0 : 3 duty (use COM0–COM 2) 1 1 : 4 duty (use COM0–COM 3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disabled 1 : Voltage multiplier enabled LCD circuit divider division ratio selection bits 0 0 : 1 division of clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(X CIN)/32 1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) Note : LCDCK is a clock for a LCD timing controller. b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 41 Block diagram of LCD controller/driver Data bus Timing controller LCDdivider f(X IN )/8192 f(X CIN )/32 COM COM COM COM V SS V V V SEG SEG SEG SEG Address 0040 Address 0041 “0” “1” LCDCK LCDCK count source selection bit LCD circuit divider division ratio selection bits Bias control bit LCD enable bit Duty ratio selection bits Selector Selector Selector Selector Selector Selector LCD display RAM Address 0053 4/SEG 0/SEG 5/SEG Levelshift Levelshift Levelshift Levelshift Levelshift Levelshift Common driver Common driver Common driver Common driver C C Voltage multipliercontrol bit LevelShift LevelShift LevelShift LevelShift Segmentdriver Segmentdriver Segmentdriver Segmentdriver Segmentdriver Segmentdriver Bias control LCD output enable bit V CC (f(X CIN )/8192 in low-speed mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Voltage Multiplier (3 Times) The voltage multiplier performs threefold boosting. This circuit in- puts a reference voltage for boosting from LCD power input pin V L1. (However, when using a 1/2 bias, connect VL1 and VL2 and apply voltage by external resistor division.) Set each bit of the segment output enable register and the LCD mode register in the following order for operating the voltage mul- tiplier. 1. Set the segment output enable bits (bits 0 to 5) of the seg- ment output enable register to “0” or “1.” 2. Set the duty ratio selection bits (bits 0 and 1), the bias con- trol bit (bit 2), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register to “0” or “1.” 3. Set the LCD output enable bit (bit 6) of the segment output enable register to “1.” 4. Set the voltage multiplier control bit (bit 4) of the LCD mode register to “1.” When voltage is input to the V L1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. When using the voltage multiplier, apply 1.3 V ≤ Voltage ≤ 2.3 V to the VL1 pin. When not using the voltage multiplier,apply proper voltage to the LCD power input pins (V L1–VL3). Then set the LCD output enable bit to “1.” When the LCD output enable bit is set to “0,” the VCC voltage is applied to the VL3 pin inside of this microcomputer. The voltage multiplier control bit (bit 4 of the LCD mode register) controls the voltage multiplier. Fig. 42 Example of circuit at each bias Table 10 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias Voltage value VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD Note: VLCD is the maximum value of supplied voltage for the LCD panel. Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1–VL3), apply the voltage shown in Table 10 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). 1/2 bias V L3=VLCD VL2=VL1=1/2 VLCD VL3 VL2 C 2 C 1 VL1 1/3 bias when using the voltage multiplier VL3 VL2 C 2 C 1 VL1 1/3 bias when not using the voltage multiplier Open Open R1=R2=R3 Contrast control VL3 VL2 C 2 C 1 VL1 1/2 bias Open Open R4=R5 Contrast control VCC VCC PX X

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Common Pin and Duty Ratio Control The common pins (COM 0–COM 3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). When releasing from reset, the V CC (VL3) voltage is output from the common pins. Table 11 Duty ratio control and common pins used Duty ratio Common pins used Notes1: COM 2 and COM 3 are open. 2: COM 3 is open. Bit 1 Bit 0 COM 0, COM 1 (Note 1) Duty ratio selection bit COM 0–COM 2 (Note 2) COM 0–COM 3 Segment Signal Output Pin Segment signal output pins are classified into the segment-only pins (SEG0–SEG 17), the segment/output port pins (SEG18– SEG 25), and the segment/I/O port pins (SEG26–SEG 39). Segment signals are output according to the bit data of the LCD RAM corresponding to the duty ratio. After reset release, a V CC (=VL3) voltage is output to the segment-only pins and the seg- ment/output port pins are the high impedance condition. The seg- ment/I/O port pins(SEG 26–SEG 33). are set to input ports, and the high impedance condition.The segment/I/O port pins(SEG34– SEG 39). are set to input ports, and VCC (=VL3) is applied to them by pull-up resistor. LCD Display RAM Address 004016 to 005316 is the designated RAM for the LCD dis- play. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated in- ternally and the frame frequency can be determined with the following equation; f(LCDCK) = Frame frequency = Fig. 43 LCD display RAM map (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) (duty ratio) Bit address 76 5432 10 004016 004116 004216 004316 004416 004516 004616 SEG 1 SEG 3 SEG 5 SEG 7 SEG 9 SEG 0 SEG 2 SEG 4 SEG 6 SEG 8 SEG 10 COM 3 COM2 COM1 COM 0 SEG 12 SEG 14 SEG 16 SEG 18 SEG 20 SEG 22 SEG 24 SEG 26 SEG 28 SEG 30 SEG 32 SEG 34 SEG 36 SEG 38 SEG 21 SEG 23 SEG 25 SEG 27 SEG 11 SEG 13 SEG 15 SEG 17 SEG 19 SEG 29 SEG 31 SEG 33 SEG 35 SEG 37 SEG 39 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 COM 3 COM2 COM1 COM0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 44 LCD drive waveform (1/2 bias) Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS VL3 VSS COM 0 COM 1 COM 2 COM 3 SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1/3 duty VL3 VL2=VL1 VSS VL3 VSS OFFON ON OFF ON OFF 1/2 duty COM 0 COM 1 COM 2 SEG 0 COM 0 COM 1 SEG 0 VL3 VL2=VL1 VSS VL3 VSS OFF ON OFF ON OFF ON OFF ON COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 45 LCD drive waveform (1/3 bias) Internal signal LCDCK timing 1/4 duty Voltage level VL3 VSS COM 0 COM 1 COM 2 COM 3 SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1/3 duty OFFON ON OFF ON OFF 1/2 duty COM 0 COM 1 COM 2 SEG 0 COM 0 COM 1 SEG 0 OFF ON OFF ON OFF ON OFF ON VL3 VL2 VSS VL1 VL3 VL2 VSS VL1 VL3 VSS VL3 VL2 VSS VL1 VL3 VSS COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 6- bit watchdog timer H. At reset or writing to the watchdog timer control register (address 0037 16), the watchdog timer is set to “3FFF 16.” When any data is not written to the watchdog timer con- trol register (address 003716) after reset, the watchdog timer is in stop state. The watchdog timer starts to count down from “3FFF 16” by writing an optional value into the watchdog timer control regis- ter (address 0037 16) and an internal reset occurs at an underflow. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0037 16) may be started before an underflow. The watchdog timer does not function when an optional value has not been written to the watchdog timer control register (address 0037 16). When address 003716 is read, the following values are read: G value of high-order 6-bit counter G value of STP instruction disable bit G value of count source selection bit. When bit 6 of the watchdog timer control register (address 003716) is set to “0,” the STP instruction is valid. The STP instruction is disabled by rewriting this bit to “1.” At this time, if the STP instruc- tion is executed, it is processed as an undefined instruction, so that a reset occurs inside. This bit cannot be rewritten to “0” by programming. This bit is “0” immediately after reset. The count source of the watchdog timer becomes the system clock φ divided by 8. The detection time in this case is set to 8.19 s at f(X CIN) = 32 kHz and 65.536 ms at f(XIN) = 4 MHz. However, count source of high-order 6-bit timer can be connected to a signal divided system clock by 8 directly by writing the bit 7 of the watchdog timer control register (address 0037 16) to “1.” The detection time in this case is set to 32 ms at f(XCIN) = 32 kHz and 256 µs at f(XIN) = 4 MHz. There is no difference in the detection time between the middle-speed mode and the high-speed mode. Fig. 46 Block diagram of watchdog timer Fig. 47 Structure of watchdog timer control register Fig. 48 Timing of reset output Internal reset signal Watchdog timer detection ≅ 2 ms (f(XIN) = 4 MHZ) f(XIN) XIN Data bus XCIN “1” “0” Internal system clock selection bit “0” “1”1/16 Watchdog timer count source selection bit Reset circuit Undefined instruction Reset “3F16” is set when watchdog timer is written to. Internal reset RESET IN Reset release time wait “FF16” is set when watchdog timer is written to. STP instruction STP instruction disable bit Watchdog timer H (6) Watchdog timer L (8) b7 b0 Watchdog timer register (address 003716) WDTCON STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selecion bit 0 : Internal system clock/2048 (f(X IN)/4096) 1 : Internal system clock/8 (f(XIN)/16) Watchdog timer H (for read-out of high-order 6 bit) “3FFF 16” is set to the watchdog timer by writing values to this address.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS TOUT /φ CLOCK OUTPUT FUNCTION The internal system clock φ or timer 2 divided by 2 (TOUT output) can be output from port P43 by setting the TOUT /φ output control bit (bit 1) of the timer 123 mode register and the TOUT /φ output control register. Set bit 3 of the port P4 direction register to “1” when outputting the clock. Fig. 49 Structure of TOUT /f output-related register TOUT /φ output control bit 0 : φ clock output 1 : TOUT output Not used (return “0” when read) TOUT /φ output control register (CKOUT : address 002A16) b7 b0 Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : Start on “H ” output 1 : Start on “L” output TOUT /φ output control bit 0 : TOUT /φ output disable 1 : TOUT /φ output enable Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode✽ ) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode✽ ) Timer 1 count source selection bit 0 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode✽ ) 1 : f(XCIN) Not used (return “0” when read) ✽ : Internal clock φ is f(XCIN)/2 in low-speed mode. b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H ” level (the power source voltage should be between VCC (min.) and 5.5 V , and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address con- tained in address FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.2 V CC for VCC of VCC (min.). Fig. 50 Reset Circuit Example Fig. 51 Reset Sequence (Note) 0.2VCC Poweron VCCRESET VCCRESET Power source voltage detection circuit Power source voltage Reset input voltage Note : Reset release voltage ; V CC =VCC (min.) RESET Internal reset Address Data SYNC φ XIN FFFC FFFD AD H, AD L AD L AD H ???? XIN : about 8200 cycles Notes 1:The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ). 2:The question marks (?) indicate an undefined state that depends on the previous state. Reset address from vector table

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 52 Initial status at reset Address (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) Port P0 direction register Port P1 direction register Port P2 direction register Port P3 output control register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Key input control register PULL register A PULL register B Serial I/O1 status register Serial I/O1 control register UART control register Serial I/O2 control register Timer X (low-order) Timer X (high-order) Timer Y (low-order) Timer Y (high-order) Timer 1 Timer 2 Timer 3 Timer X mode register Timer Y mode register Timer 123 mode register TOUT /φ output control register PWM control register 000116 000316 000516 000716 000916 000B16 000D 16 000F16 001516 001616 001716 001916 001A16 001B16 001D 16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 Register contents Address Note: The contents of all other register and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 3F16 0016 0016 0016 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016 0016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 (PS) (PCH ) (PCL) A-D control register A-D conversion register (low-order) A-D conversion register (high-order) D-A1 conversion register D-A2 conversion register D-A control register Watchdog timer control register Segment output enable register LCD mode register Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter Watchdog timer (high-order) Watchdog timer (low-order) Contents of address FFFD16 Contents of address FFFC16 0816 XX 16 XX 16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 3F16 FF16 10000000 11100000 00111111 01001000

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The 7513 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No exter- nal resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accord- ingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the X IN oscillation circuit starts oscillating, and XCIN and XCOUT pins go to high impedance state. Frequency Control (1) Middle-speed Mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2) High-speed Mode The internal clock φ is half the frequency of XIN. (3) Low-speed Mode G The internal clock φ is half the frequency of XCIN. G A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscil- lation to stabilize by programming. Note: If you switch the mode between middle/high-speed and low- speed, stabilize both XIN and X CIN oscillations. The sufficient time is required for the sub-clock to stabilize, es- pecially immediately after poweron and at returning from stop mode. When switching the mode between middle/high- speed and low-speed, set the frequency on condition that f(X IN)>3f(XCIN). Fig. 53 Ceramic resonator circuit Fig. 54 External clock input circuit Oscillation Control (1) Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H ” level, and XIN and XCIN oscillators stop. The value set to the timer latch 1 and the timer latch 2 is loaded automatically to the timer 1 and the timer 2. Thus, a value generated time for stabiliz- ing oscillation should be set to the timer 1 latch and the timer 2 latch (low-order 8 bits for the timer 1, high-order 8 bits for the timer 2) before executing the STP instruction. Either X IN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0,” Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be- fore executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows timer for the clock circuit oscillation to stabilize. (2) Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H ” level. The states of XIN and XCIN are the same as the state be- fore the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. XIN XOUT External oscillation circuit Open VCC VSS C CIN C COUT Rf Rd XCIN XCOUT C IN C OUTC CIN C COUT Rf Rd XCIN XCOUT XIN XOUT

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 55 Clock generating circuit block diagram WIT instruction STP instruction Timing φ (Internal clock) S R Q STP instruction S R Q Main clock stop bit S R Q Timer 2Timer 11/2 1/4 XIN XOUT XCOUTXCIN Interrupt request Reset Timer 1 count source selection bit Timer 2 count source selection bit Low-speed mode Middle-/High-speed mode Internal system clock selection bit (Note) Middle-speed mode High-speed mode or Low-speed mode Note: When selecting the X C oscillation, set the port XC switch bit to “1” . Main clock division ratio selection bit “0” “1” “1” “0” “1” “0” Interrupt disable flag I “1” “0”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 56 State transitions of system clock Low-power dissipation mode (f(φ) =16 kHz) N o t e s 1 : S w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( D o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a l l o w . ) T h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n e d t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d T i m e r a n d L C D o p e r a t e i n t h e w a i t m o d e W h e n t h e s t o p m o d e i s e n d e d w a i t t i m e c a n b e s e t b y c o n n e c t i n g t i m e r a n d t i m e r i n m i d d l e h i g h s p e e d m o d e W h e n t h e s t o p m o d e i s e n d e d w a i t t i m e c a n b e s e t b y c o n n e c t i n g t i m e r a n d t i m e r i n l o w s p e e d m o d e W a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k XI N b e f o r e t h e s w i t c h i n g f r o m t h e l o w s p e e d m o d e t o m i d d l e h i g h s p e e d m o d e T h e e x a m p l e a s s u m e s t h a t M H z i s b e i n g a p p l i e d t o t h e XI N p i n a n d k H z t o t h e XC I N p i n φ i n d i c a t e s t h e i n t e r n a l c l o c k CM 4 : Sub-clock (XCIN–XCOUT ) stop bit 0: Stopped 1: Oscillating CM 5 : Main clock (XIN–XOUT ) stop bit 0: Oscillating 1: Stopped CM 6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM 7 : Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) CPU mode register (CPUM : address 003B16) b7 b R e s e t CM 6 “0” “1” C M 4 0 ” “ 1 ” M i d d l e s p e e d m o d e f (φ) M H z M i d d l e - s p e e d m o d e ( f (φ) = 1 M H z ) High-speed mode (f(φ) =4 MHz) High-speed mode (f(φ) =4 MHz) Low-speed mode (f(φ) =16 kHz) Low-speed mode (f(φ) =16 kHz) Low-power dissipation mode (f(φ) =16 kHz) CM 6 “0” “1” CM 6 “0” “1” CM 6 “0” “1” C M 0 ” “ 1 ” C M 0 ” “ 1 ” C M 0 ” “ 1 ” C M 0 ” “ 1 ” C M 0 ” “ 1 ” CM 7=0(8MHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=0(32kHz stoped) C M 7= M H z s e l e c t e d C M 6= H i g h s p e e d C M 5= M H z o s c i l l a t i n g C M 4= k H z s t o p e d C M 7= M H z s e l e c t e d C M 6= M i d d l e s p e e d C M 5= M H z o s c i l l a t i n g C M 4= k H z o s c i l l a t i n g CM 7=0(8MHz selected) CM 6=0(High-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) C M 7= k H z s e l e c t e d C M 6= H i g h s p e e d C M 5= M H z o s c i l l a t i n g C M 4= k H z o s c i l l a t i n g CM 7=1(32kHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) C M 7= k H z s e l e c t e d C M 6= M i d d l e s p e e d C M 5= M H z s t o p p e d C M 4= k H z o s c i l l a t i n g CM 7=1(32kHz selected) CM 6=0(High-speed) CM 5=1(8MHz stopped) CM 4=1(32kHz oscillating) C M 0 ” 1 ” C M 0 ” 1 ” C M 0 ” 1 ” C M 0 ” 1 ” C M “ 0 C M “ 1 C M “ 0 C M “ 1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupt The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt request register, execute at least one instruction before perform- ing a BBC or BBS instruction. Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction be- fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O1 continues to output the final bit from the TX D pin after transmission is completed. In serial I/O2, the S OUT2 pin goes to high impedance state after transmission is completed. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(X IN) is at least 500 kHz during an A-D conver- sion. Do not execute the STP or WIT instruction during an A-D conver- sion. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) or in one floppy disk ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built- in EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Fig. 57 Programming and testing of One Time PROM version Package 100PFB-A 100P6Q-A 100D0 Name of Programming Adapter PCA4738H-100A PCA4738G-100A PCA4738L-100A Table 12 Special programming adapter The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 57 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Caution :

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS V V “H” input voltage P0 0–P0 7, P10–P1 7, P40, P43, P45, P47, P50–P5 3, P56, P61, P64–P6 7, P71–P7 7 “H” input voltage P2 0–P2 7, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET X IN “L” input voltage P0 0–P0 7, P10–P1 7, P40, P43, P45, P47, P50–P5 3, P56, P61, P64–P6 7, P71–P7 7 “L” input voltage P2 0–P2 7, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET X IN

ELECTRICAL CHARACTERISTICS

Table 13 Absolute maximum ratings RECOMMENDED OPERATING CONDITIONS Table 14 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Power source voltage A-D, D-A conversion reference voltage Analog power source voltage Analog input voltage AN 0–AN 7 5.5 5.5 5.5 V CC +0.3 VCC VCC VSS VREF AV SS VIA Symbol Parameter Limits Min. V V V V V Unit 4.0 2.2 2.2 2.7 AV SS 5.0 5.0 5.0 Typ. Max. Power source voltage VO VO VO VO Pd Topr Tstg –0.3 to 7.0 VPower source voltage Input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7 Input voltage P40, P71–P7 7 Input voltage P70 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET , XIN Output voltage C1, C2 VCC VI Symbol Parameter Conditions Ratings Unit All voltages are based on VSS . Output transistors are cut off. VI VI VI VI VI VI VI VO VO VO Output voltage P00–P07, P10–P1 5, P30–P3 7 Output voltage P16, P17, P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7 Output voltage P40, P71–P7 7 Output voltage VL3, SEG0–SEG 17,COM 0–COM 3 Output voltage VL2 Output voltage XOUT Power dissipation Operating temperature At output port At segment output Ta = 25°C –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 7.0 –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to VCC –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to 7.0 –0.3 to V –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 V V V V V V V V V V V V V V V V mW High-speed mode f(X IN) = 8 MHz Middle-speed mode f(XIN) = 8 MHz Low-speed mode “H” input voltage “H” input voltage V IH VIH VIH VIH VIL VIL VIL VIL “L” input voltage “L” input voltage 0.7 V CC

0.8 VCC

0.3 VCC

0.2 VCC

V V V V V V

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P15, P30–P37 (Note 2) “H ” peak output current P1 6, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) P00–P07, P10–P15, P30–P37 (Note 2) “L” peak output current P1 6, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) 0, P71–P77 (Note 2) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 P00–P07, P10–P15, P30–P37 (Note 3) “L” average output current P1 6, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 3) 0, P71–P77 (Note 3) –20 –20 –10 –10 –1.0 Table 15 Recommended operating conditions (V CC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. “H ” total peak output current “H ” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H ” total average output current “H ” total average output current “L” total average output current “L” total average output current “L” total average output current Σ IOH(peak) Σ IOH(peak) Σ IOL(peak) Σ IOL(peak) Σ IOL(peak) Σ IOH(avg) Σ IOH(avg) Σ IOL(avg) Σ IOL(avg) Σ IOL(avg) IOH(peak) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA Unit Typ. Max. “H ” peak output current “L” peak output current “L” peak output current “H ” average output current “H ” average output current “L” average output current “L” average output current IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) –5.0 5.0 –0.5 –2.5 2.5 5.0 mA mA mA mA mA mA mA mA mA

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 16 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Notes1: When the oscillation frequency has a duty cycle of 50%. 2:When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Input frequency for timers X and Y (duty cycle 50%) f(CNTR 0) f(CNTR 1) Symbol Parameter Limits Min. MHz UnitTyp. Max. 32.768 4.0 Main clock input oscillation frequency (Note 1) Sub-clock input oscillation frequency (Notes 1, 2) f(X IN) f(XCIN) High-speed mode (4.0 V ≤ V CC ≤ 5.5 V) High-speed mode (2.2 V ≤ V CC ≤ 4.0 V) Middle-speed mode (10✕ VCC –4)/9 8.0 (20✕ VCC –8)/9 8.0 MHz MHz MHz MHz kHz Test conditions

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS VO = VCC Output transistors “off” VO = VSS Output transistors “off” IOL = 10 mA IOL = 3.0 mA IOL = 2.5 mA VCC = 2.2 V IOL = 5 mA IOL = 1.5 mA IOL = 1.25 mA VCC = 2.2 V VOL IOH = –1 mA IOH = –0.25 mA VCC = 2.2 V IOH = –5 mA IOH = –1.5 mA IOH = –1.25 mA VCC = 2.2 V V VCC –2.0“H ” output voltage P00–P07, P10–P15, P30–P37 Symbol Parameter Limits Min. Unit 0.5 Ty p . Max.Test conditions VOH 2.0 0.5 Table 17 Electrical characteristics (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) IOL = 10 mA IOL = 5 mA VCC = 2.2 V VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” VCC = 2.2 V, VI = VSS Pull-ups “on” VI = VSS VI = VSS “H ” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 1) “L” output voltage P00–P07, P10–P15, P30–P37 “L” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 “L” output voltage P40, P71–P77 Hysteresis INT0–INT2, ADT , CNTR0, CNTR 1, P20–P27 Hysteresis S CLK , RX D Hysteresis RESET “H ” input current P00–P07, P10–P17, P20–P27, P40–P47, P50–P57, P60–P67, P70–P77 “H ” input current RESET “H ” input current XIN “L” input current P10–P17, P20–P27,P40–P47, P50–P57, P60–P67, P70–P77 “L” input current P00–P07,P70 “L” input current RESET “L” input current XIN Output load current P30–P37 VOH VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIL IIL IIL ILEAK VCC –2.0 VCC –0.5 –60.0 –5.0 0.5 0.5 4.0 –120.0 –20.0 –4.0 2.0 0.5 0.5 5.0 5.0 –5.0 –240.0 –40.0 –5.0 –5.0 5.0 –5.0 V V V V V V V V V V µ A µ A µA µA µ A µ A µ A µA I IL VCC –0.8 VCC –0.8 V V V0.8 V0.8 0.3 V µA µA µA

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 18 Electrical characteristics (VCC =2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) V5.5

• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. UnitTyp. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC Power source current 6.4 VRAM RAM retention voltage At clock stop mode 2.0 When using voltage multiplier VL1 = 1.8 V VL1 < 1.3 V VL1 IL1 Power source voltage Power source current (VL1) (Note) Note:When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”. 1.3 1.6 15.0 4.5 0.1 1.8 3.0 10.0 3.2 22.0 9.0 1.0 10.0 2.3 6.0 50.0 mA µA µA µA µA µA V mA13 µA

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 19 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 4 V VCC = VREF = 2.7 V (Note 2) 30.5 Bits LSB LSB ±2.5 ±4.0 (Note 1) Notes1: When an internal trigger is used in middle-speed mode, it is 34 ms. 2: 4 MHz ≤ f(XIN) ≤ 5.1 MHz in high-speed mode. µ sf(XIN) = 4 MHz VREF = 5 V Conversion time Ladder resistor Reference power source input current tCONV R LADDER IVREF kΩ µA Table 20 D-A converter characteristics (VCC = 2.7 to 5.5 V, VCC = VREF , VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution VCC = VREF = 5 V VCC = VREF = 2.7 V Bits µs kΩ mA 2.5 1.0 2.0 Note:Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through the A-D resistance ladder. (Note) Setting time Output resistor t su R O 4 6.0 Absolute accuracy Analog port input currentIIA IVREF Reference power source input current µA 200 5.0 150 0.5

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 21 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) 125 250 105 105 800 370 370 220 100 1000 400 400 200 200 Note:When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H ” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H ” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT2 input “H ” pulse width INT0 to INT2 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H ” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H ” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D –S CLK1 ) th(SCLK1 –RX D) tc(SCLK2 ) twH(S CLK2 ) twL (SCLK2 ) tsu(SIN2–SCLK2 ) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. Table 22 Timing requirements 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) 125 900/(V CC –0.4) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H ” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H ” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT2 input “H ” pulse width INT0 to INT2 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H ” pulse width (Note) tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. Note:When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. tsu(SIN2–S CLK2 ) th(SCLK2 –SIN2) twL(SCLK1 ) tsu(RX D –S CLK1 ) th(SCLK1 –RX D) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H ” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time 950 400 200 2000 950 950 400 300 ns ns ns ns ns ns ns ns

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 23 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2:XOUT and XCOUT pins are excluded. Serial I/O1 clock output “H ” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H ” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 0.2 ✕ tC (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tC (SCLK1 )/2–30 tC (SCLK1 )/2–30 –30 Typ. Max. t wH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TX D) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –SOUT2 ) tv(SCLK2 –S OUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Table 24 Switching characteristics 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2:XOUT and XCOUT pins are excluded. Serial I/O1 clock output “H ” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H ” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 0.2 ✕ tC (SCLK2 ) Symbol Parameter Limits Min. tC (SCLK1 )/2–50 tC (SCLK1 )/2–50 –30 Max. t wH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TX D) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –SOUT2 ) tv(SCLK2 –S OUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Typ. tC (SCLK2 )/2–160 tC (SCLK2 )/2–160 tC (SCLK2 )/2–240 tC (SCLK2 )/2–240

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 58 Circuit for measuring output switching characteristics Measurement output pin 100 pF CMOS output Note : When bit 4 of the UART control register (address 001B16) is “1”. (N-channel open-drain output mode) N-channel open-drain output (Note) 1 kΩ 100 pF Measurement output pin

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 59 Timing diagram 0.2VCC td (SCLK -TXD) tf 0.2VCC 0.8VCC 0.8VCC tr tsu (RXD-SCLK )t h (SCLK -RXD) tv (SCLK -TXD) tC (SCLK ) tWL (SCLK ) tWH (SCLK ) TXD R XD SCLK 0.2VCC tWL (XIN) 0.8VCC tWH (XIN) tC (XIN) XIN 0.2VCC 0.8VCC tW (RESET) RESET 0.2VCC tWL (CNTR) 0.8VCC tWH (CNTR) tC (CNTR) 0.2VCC tWL (INT) 0.8VCC tWH (INT) CNTR 0, CNTR 1 INT0–INT3

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS LQFP100-P-1414-0.50 Weight(g) – 0.63 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100P6Q-A Plastic 100pin 14✕ 14mm body LQFP 0.1 0.2 – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 – –I2 0.9 – –M D 14.4 – –M E 14.4 10°0° 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 1.7 e e E H E 5026 H D D A F y 100 Lp 0.45 0.6 0.25 0.75 0.08x b x M A1 A2 L Detail F Lp c M D l2 b2 M E e Recommended Mount Pad MMP TQFP100-P-1212-0.40 Weight(g) – 0.37 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100PFB-A Plastic 100pin 12✕ 12mm body TQFP – – – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.15 0.1 0.225 – –I2 1.0 – –M D 12.4 – –M E 12.4 10°0° 0.08 0.07 1.0 0.6 0.5 0.4 14.2 14.0 13.8 14.2 14.0 13.8 0.4 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.23 0.18 0.13 1.0 0.05 1.2 e H E E D H D 76100 26 50 Fe A y A1 A2 L Lp Detail F c Lp 0.45 0.6 0.25 0.75 x b x M M D e M E Recommended Mount Pad MMP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective Feb. 2001. Specifications subject to change without notice. Notes regarding these materials

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REVISION HISTORY 7513 GROUP USER’S MANUAL Rev. Date Description Page Summary (1/1) 1.0 02/02/01 1.1 02/06/01 First edition issued. Table 1: Function explanation of I/O port P0 and I/O port P1 is revised.