M37471E8SS

7470_N RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER

740 FAMILY / 7470 SERIES

User’s Manual

keep safety first in your circuit designs ! l Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials l These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. l Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. l Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. l If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. l Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

This user’s manual describes Mitsubishi’s CMOS 8-bit microcomputers 7470/7471/7477/7478 group. After reading this manual, the user should have a through knowledge of the functions and features of the 7470/7471/7477/7478 group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For detailes of software, refer to the “SERIES MELPS 740<SOFTWARE> USER’S MANUAL.” For details of development support tools, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data book.

BEFORE USING THIS USER’S MANUAL 1. Organization This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. l CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. l CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. l CHAPTER 3 APPENDIX This chapter includes a list of registers, and necessary information for systems development using the microcomputer, the masking confirmation (mask ROM version), ROM programming confirmation, and mark specifications which are to be submitted when ordering. 2. Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: b7 b6 b5 b4 b3 b2 b1 b0 Fix these bits to “0.” Stack page selection bit Nothing is allocated for this bit. This is write enabled bit and is undefined at reading. X COUT drive capacity selection bit Main clock (XIN–XOUT ) stop bit Internal system clock selection bit P50, P51/XCIN, XCOUT selection bit 0: In page 0 area 1: In page 1 area 0: Low 1: High 0: Oscillates 1: Stops 0: XIN–XOUT selected (Ordinary mode) 1: XCIN–XCOUT selected (low-speed mode) 0: P50, P51 1: XCIN, XCOUT Name Function At resetB RW 0, 1 ? 5 Bits CPU mode register (CPUM) [Address: FB16] Bit attributes CPU mode register Contents immediately after reset release : Bit in which nothing is arranged Note 1. Contents immediately after reset release 0 “0” at reset release 1 “1” at reset release ? Undefined at reset release Note 2. Bit attributes R W (Note 1) (Note 2) Write Write enabled Write disabled Fix to “0”. Can be cleared to “0” by software but not set to “1”. Read Read enabled Undefined at reading “1” at reading “0” at reading 0

7470/7471/7477/7478 GROUP USER’S MANUAL Table of contents i Table of contents CHAPTER 1. HARDWARE

7470/7471/7477/7478 GROUP USER’S MANUALii

7470/7471/7477/7478 GROUP USER’S MANUAL Table of contents iii CHAPTER 2. APPLICATION

7470/7471/7477/7478 GROUP USER’S MANUALiv CHAPTER 3. APPENDIX

7470/7471/7477/7478 GROUP USER’S MANUAL List of tables i List of tables CHAPTER 1. HARDWARE

7470/7471/7477/7478 GROUP USER’S MANUALii CHAPTER 2. APPLICATION

7470/7471/7477/7478 GROUP USER’S MANUAL List of figures i List of figures CHAPTER 1. HARDWARE Fig. 1.11.3 Changes of contents of Program counter and Stack pointer upon acceptance

7470/7471/7477/7478 GROUP USER’S MANUALii Fig. 1.12.10 Relation between timer value change timing and read value change timing 1-82

7470/7471/7477/7478 GROUP USER’S MANUAL List of figures iii Fig. 1.14.2 Contents of A-D conversion register and reference voltage during Fig. 1.17.3 Oscillation stabilizing wait time at recovery from stop mode by reset input . 1-163 Fig. 1.20.11 IOH -VOH characteristics of programmable I/O port (CMOS output) P-channel Fig. 1.20.12 IOL -VOL characteristics of programmable I/O port (CMOS output) N-channel Fig. 1.20.13 IIL-VIL characteristics of programmable I/O port (CMOS output) pull-up

7470/7471/7477/7478 GROUP USER’S MANUALiv Fig. 1.20.14 IOH -VOH characteristics of programmable I/O port (CMOS output) P-channel Fig. 1.20.15 IOL -VOL characteristics of programmable I/O port (CMOS) N-channel side Fig. 1.20.16 IIL-VIL characteristics of programmable I/O port (CMOS output) pull-up CHAPTER 2. APPLICATION Fig. 2.3.12 Timing at which timer value and read value change in the case where two Fig. 2.4.2 Example of connections [Clock synchronous serial I/O mode, 7470/7471 Fig. 2.4.3 Example of control procedure [Clock synchronous serial I/O mode, 7470/7471 Fig. 2.4.5 Example of control procedure (1) [Byte specification mode, 7470/7471 group] 2-27 Fig. 2.4.6 Example of control procedure (2) [Byte specification mode, 7470/7471 group] 2-28 Fig. 2.4.8 Example of connections [Clock synchronous serial I/O mode, 7477/7478

7470/7471/7477/7478 GROUP USER’S MANUAL List of figures v Fig. 2.4.9 Example of control procedure [Clock synchronous serial I/O mode, 7477/7478 Fig. 2.4.10 Example of connections [Clock asynchronous serial I/O mode, 7477/7478 Fig. 2.4.11 Example of control procedure [Clock asynchronous serial I/O mode, 7477 CHAPTER 3. APPENDIX

7470/7471/7477/7478 GROUP USER’S MANUALvi

1.1 Description

1.2 Group expansion

1.3 Performance overview

1.4 Pin configuration

1.5 Pin description

1.6 Functional block diagram

1.7 Central processing unit (CPU)

1.8 Access area

1.9 Memory allocation

1.10 I/O pins

1.11 Interrupts

1.12 Timers

1.13 Serial I/O

1.14 A-D converter

1.15 Reset

1.16 Oscillation circuit

1.17 Low-power

1.18 State transitions

1.19 Built-in PROM version

1.20

Electrical characteristics

7470/7471/7477/7478 GROUP USER’S MANUAL The 7470/7471/7477/7478 group is an 8-bit single-chip microcomputer which utilizes a silicon gate CMOS processing and has a simple instruction system of the 740 family using the same memory space for ROM, RAM and I/O.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE The 7470/7471/7477/7478 group develops with the M37470M2-XXXSP as the base chip in the 7470 series. The classification of the 7470 series is as follows. 7470 series 7470 group 7471 group 7477 group 7478 group 7480 group 7481 group The 7470/7471/7477/7478 group permits group expansion as shown in Figure 1.2.1. This group expansion is all performed only by differences in memory type and capacity and the number of ports. This allows the user to select optimum elements according to the user's system. The 7470/7471/7477/7478 group supports the following in addition to the mask ROM version. (1) Support of One Time PROM version The One Time PROM version is a programmable microcomputer and can perform a one-time write operation to the built-in programmable ROM (PROM). For the details, refer to “1.19 Built-in PROM version.” (2) Support of EPROM version (with window) The built-in EPROM version is a programmable microcomputer with window and can perform write and erase operations to the built-in EPROM. For the details, refer to “1.19 Built-in PROM version.” (3) Support of emulator MCU The emulator MCU is a microcomputer designed for program development which facilitates program development and is an optimum element for system evaluation. For the details, refer to“1.20 Emulator MCU .” Table 1.2.1 shows the products which the 7470/7471/7477/7478 group supports. In this manual, when multiple models are described collectively, their names are arranged by putting “/” among them for separation. 7470 group, 7471 group → 7470/7471 group 7477 group, 7478 group → 7477/7478 group 7470 group, 7477 group → 7470/7477 group 7471 group, 7478 group → 7471/7478 group **:Under development

7470/7471/7477/7478 GROUP USER’S MANUAL1-4 Fig. 1.2.1 Memory expansion plan of 7470/7471/7477/7478 group (As of Dec. 1997) ROM size (bytes) RAM size (bytes) 16K 128 192 384 256 12K l Memory Expansion Plan of 7470/7471 group M37470M2-XXXSP M37471M2-XXXSP/FP M37470M4/E4-XXXSP M37471M4/E4-XXXSP/FP M37470M8/E8-XXXSP M37471M8/E8-XXXSP/FP M37471E8SS RAM size (bytes) 16K 192 384 12K 2560 ROM size (bytes) l Memory Expansion Plan of 7477/7478 group 128 M37477M4-XXXSP/FP M37478M4-XXXSP/FP M37477M8/E8-XXXSP/FP M37478M8/E8-XXXSP/FP M37478E8SS

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Table 1.2.1 List of supported products (As of Dec. 1997) Product M37470M2-XXXSP M37470M4-XXXSP M37470E4-XXXSP M37470M8-XXXSP M37470E8-XXXSP M37471M2-XXXSP M37471M2-XXXFP M37471M4-XXXSP M37471M4-XXXFP M37471E4-XXXSP M37471E4-XXXFP M37471M8-XXXSP M37471M8-XXXFP M37471E8-XXXSP M37471E8-XXXFP M37471E8SS M37471RSS 63.5K (Note) ROM (bytes) 4096 8192 16384 8192 4096 16384 8192 16384 RAM (bytes) 128 192 384 192 128 384 192 384 I/O Port I/O ports: 22 (Including 4 analog input pins.) Input ports: 4 I/O ports: 28 (Including 8 analog input pins.) Input ports: 8 Package 32P4B 42P4B 56P6N-A 42P4B 56P6N-A 42P4B 56P6N-A 42P4B 56P6N-A 42P4B 56P6N-A 42S1B-A 42S1M Remarks Mask ROM version One Time PROM version Mask ROM version One Time PROM version Mask ROM version One Time PROM version Mask ROM version One Time PROM version EPROM version Emulator MCU 8192 192 16384 384 16384 384 63.5K (Note) I/O ports: 18 (Including 4 analog input pins.) Input ports: 8 384 I/O ports: 20 Input ports: 16 (Including 8 analog input pins.) Note: Address space usable as a ROM area. I/O ports: 20 (Including 8 analog input pins.) Input ports: 16

7470/7471/7477/7478 GROUP USER’S MANUAL1-6 Table 1.3.1 Performance overview of 7470 group Parameter Memory size Input/ Output port ROM RAM I/O Input Serial I/O Timers PWM A-D converter M37470M2 M37470M4/E4 M37470M8/E8 Input/Output characteristics Input/Output withstand voltage Output current Operating temperature Device structure Package Interrupt Clock generating circuit Power source voltage Power dissipation Subroutine nesting Number of basic instructions Instruction execution time Clock input oscillation frequency M37470M2 M37470M4/E4 M37470M8/E8 M37470M2 M37470M4/E4 M37470M8/E8 Functions 71 (69 basic instructions of 740 family and 2 multiplication and division instructions) 0.5 µ s (the minimum instructions, at 8 MHz clock input oscillation frequency) 8 MHz (max.) 4096 bytes 8192 bytes 16384 bytes 128 bytes 192 bytes 384 bytes 8-bit 8-bit 4-bit 2-bit 4-bit 8-bit 5 1 8-bit timer 5 4 1 (in common with 2 timer) 8-bit 5 1 (4 channels) 64 levels max. 96 levels max. 192 levels max. 5 external interrupts, 6 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (an external ceramic resonator or a quartz-crystal oscillator) 2.7 V to 4.5 V (at (2.2 V CC –2) MHz clock input oscillation frequency) 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. (at 8 MHz clock input oscillation frequency) 5 V –5 mA to +10 mA (P0, P1, P2, P4: CMOS 3-state) –20 °C to +85 °C CMOS silicon gate 32-pin shrink plastic molded DIP M37470Mx/Ex-XXXSP

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Table 1.3.2 Performance overview of 7471 group Parameter Memory size Input/ Output port ROM RAM I/O Input M37471M2 M37471M4/E4 M37471M8/E8 M37471M2 M37471M4/E4 M37471M8/E8 Serial I/O Timers PWM A-D converter M37471M2 M37471M4/E4 M37471M8/E8 Input/Output characteristics Operating temperature Device structure Package Interrupt Clock generating circuit Sub-clock generating circuit Power source voltage Power dissipation M37471Mx/Ex-XXXSP M37471Mx/Ex-XXXFP M37471E8SS Subroutine nesting Number of basic instructions Instruction execution time Clock input oscillation frequency Input/Output withstand voltage Output current Functions 71 (69 basic instructions of 740 family and 2 multiplication and division instructions) 0.5 µs (the minimum instructions, at 8 MHz clock input oscillation frequency) 8 MHz (max.) 4096 bytes 8192 bytes 16384 bytes 128 bytes 192 bytes 384 bytes 8-bit 8-bit 8-bit 4-bit 4-bit 4-bit 8-bit 5 1 8-bit timer 5 4 1 (in common with 2 timer) 8-bit 5 1 (8 channels) 64 levels max. 96 levels max. 192 levels max. 5 external interrupts, 6 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (an external ceramic resonator or a quartz-crystal oscillator) Built-in circuit with internal feedback resistor (a guartz- crystal oscillator) 2.7 V to 4.5 V (at (2.2 V CC –2) MHz clock input oscillation frequency) 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. (at 8 MHz clock input oscillation frequency) 5 V –5 mA to +10 mA (P0, P1, P2, P4: CMOS 3-state) –20 °C to +85 °C CMOS silicon gate 42-pin shrink plastic molded DIP 56-pin plastic molded QFP 42-pin shrink ceramic DIP

7470/7471/7477/7478 GROUP USER’S MANUAL1-8 M37477M4 M37477M8/E8 M37477M4 M37477M8/E8 M37477Mx/E8-XXXSP M37477Mx/E8-XXXFP Clock generating circuit Power source voltage Power dissipation M37477M4 M37477M8/E8 Functions 71 (69 basic instructions of 740 family and 2 multiplication and division instructions) 0.5 µs (the minimum instructions, at 8 MHz clock input oscillation frequency) 8 MHz (max.) 8192 bytes 16384 bytes 192 bytes 384 bytes 8-bit 8-bit 2-bit 4-bit 4-bit 8-bit 5 1 (operable in UART mode) 8-bit timer 5 4 1 (in common with 2 timer) 8-bit 5 1 (4 channels) 96 level max. 192 level max. 5 external interrupts, 7 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (an external ceramic resonator or a quartz-crystal oscillator) 2.7 V to 4.5 V (at (2.2 VCC –2) MHz clock input oscillation frequency) 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. (at 8 MHz clock input oscillation frequency) 5 V –5 mA to +10 mA (P0, P1, P4: CMOS 3-state) –20 °C to +85 °C CMOS silicon gate 32-pin shrink plastic molded DIP 32-pin plastic molded SOP Table 1.3.3 Performance overview of 7477 group Number of basic instructions Instruction execution time Clock input oscillation frequency Parameter ROM RAM Memory size I/O Input Input/ Output port Serial I/O Timers PWM A-D converter Subroutine nesting Interrupt Input/Output withstand voltage Output current Input/Output characteristics Operating temperature Device structure Package

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Input/Output withstand voltage Output current Functions 71 (69 basic instructions of 740 family and 2 multiplication and division instructions) 0.5 µs (the minimum instructions, at 8 MHz clock input oscillation frequency) 8 MHz (max.) 8192 bytes 16384 bytes 192 bytes 384 bytes 8-bit 8-bit 4-bit 8-bit 4-bit 4-bit 8-bit 5 1 (operable in UART mode) 8-bit timer 5 4 1 (in common with 2 timer) 8-bit 5 1 (8 channels) 96 level max. 192 level max. 5 external interrupts, 7 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (an external ceramic resonator or a quartz-crystal oscillator) Built-in circuit with internal feedback resistor (a quartz- crystal oscillator) 2.7 V to 4.5 V (at (2.2 VCC –2) MHz clock input oscillation frequency) 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. (at 8 MHz clock input oscillation frequency) 5 V –5 mA to +10 mA (P0, P1, P4: CMOS 3-state) –20 °C to +85 °C CMOS silicon gate 42-pin shrink plastic molded DIP 56-pin plastic molded QFP 42-pin shrink ceramic DIP Package Operating temperature Device structure Input/Output characteristics Sub-clock generating circuit Power source voltage Power dissipation M37478M4 M37478M8/E8 M37478M4 M37478M8/E8 Table 1.3.4 Performance overview of 7478 group Parameter Number of basic instructions Instruction execution time Clock input oscillation frequency ROM RAM Memory size I/O Input Input/ Output port Serial I/O Timers PWM A-D converter M37478M4 M37478M8/E8 Subroutine nesting Interrupt Clock generating circuitM37478Mx/E8-XXXSP M37478Mx/E8-XXXFP M37478E8SS

7470/7471/7477/7478 GROUP USER’S MANUAL1-10 For pin connections in the EPROM mode of the built-in programmable ROM version, refer to “Figures Fig. 1.4.1 Pin configuration of 7470 group PIN CONFIGURATION (TOP VIEW) P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37470M8-XXXSP M37470E8-XXXSP P17/SRDY RESET Outline 32P4B (Note) Note: The M37470M2-XXXSP and M37470M4/E4-XXXSP are included in the 32P4B package. All of these products are pin-compatible.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.4.2 Pin configuration of 7471 group PIN CONFIGURATION (TOP VIEW) P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P30/INT0 P20/IN0 VREF VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/S RDY RESET NC NC NC NCNC NC M37471M8-XXXFP M37471E8-XXXFP P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 M37471M8-XXXSP M37471E8-XXXSP M37471E8SS P30/INT0 P51/XCOUT P50/XCIN VCC P20/IN0 VREF XIN XOUT VSS P17/SRDY RESET Outline 56P6N-A (Note 2) NC: No connection Outline 42P4B (Note 1) 42S1B-A (M37471E8SS) Notes 1 :The M37471M2-XXXSP and M37471M4/E4-XXXSP are included in the 42P4B package. All of these products are pin-compatible. 2 :The M37471M2-XXXFP and M37471M4/E4-XXXFP are included in the 56P6N-A package. All of these products are pin-compatible. 3 :The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.

7470/7471/7477/7478 GROUP USER’S MANUAL1-12 Fig. 1.4.3 Pin configuration of 7477 group PIN CONFIGURATION (TOP VIEW) P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37477M8-XXXSP M37477E8-XXXSP P17/SRDY RESET Outline 32P4B (Note 1) Notes 1 : The M37477M4-XXXSP is included in the 32P4B package. 2 : The M37477M4-XXXFP is included in the 32P2W-A package. 3 : The only differences between the 32P4B package product and the 32P2W-A package product are package shape and absolute maximum ratings. P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37477M8-XXXFP M37477E8-XXXFP P17/SRDY RESET Outline 32P2W-A (Note 2) These products are pin-compatible. These products are pin-compatible.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.4.4 Pin configuration of 7478 group PIN CONFIGURATION (TOP VIEW) P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P30/INT0 P20/IN0 VREF VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/S RDY RESET NC NC NC NCNC NC M37478M8-XXXFP M37478E8-XXXFP P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 M37478M8-XXXSP M37478E8-XXXSP M37478E8SS P30/INT0 P51/XCOUT P50/XCIN VCC P20/IN0 VREF XIN XOUT VSS P17/SRDY RESET Outline 56P6N-A (Note 2) NC: No connection Outline 42P4B (Note 1) 42S1B-A ( M37478E8SS) Notes1 : The M37478M4-XXXSP is included in the 42P4B package. 2 : The M37478M4-XXXFP is included in the 56P6N-A package. 3 : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AV SS pin. These products are pin-compatible These products are pin-compatible

7470/7471/7477/7478 GROUP USER’S MANUAL1-14 Name Power source Analog power source Reference voltage input Reset input Clock input Clock output I/O port P0 Functions

• Apply the following voltage to the V CC pin: 2.7 V to 4.5 V (at f(XIN) = (2.2 VCC –2) MHz clock input oscillation frequency) or 4.5 V to 5.5 V (at f(X IN) = 8 MHz clock input oscillation frequency).
• Apply 0 V to the VSS pin.
• Ground level input pin for the A-D converter.
• Apply the same voltage as V SS pin to the AVSS pin. Note:This pin is dedicated to 56P6N-A package products among the 7471/7478 group.
• Reference voltage input pin for the A-D converter.
• When using the A-D converter, apply 0.5 V CC (Q 2) to VCC [V].
• When not using the A-D converter, connect to VCC .
• Reset input pin
• The microcomputer is put into a reset state by keeping the RESET pin at “L” for 2 µs or more, and the reset state is released by returning the RESET pin to “H.”
• An input pin and an output pin for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between pins XIN and XOUT .
• A feedback resistor is incorporated between the X IN and the XOUT pins.
• To use an external clock input, connect the clock oscillation source to the XIN pin and leave the X OUT pin open.
• Port P0 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, a pull-up transistor is connectable in units of one bit.
• In input mode, a key-on wake up function is pro- vided.

For pin functions in the EPROM mode of the built-in programmable ROM version, refer to “1.19.2 Pin description.” Table 1.5.1 Pin description (1) Input/ Output Input Input Input Output I/O Pin V CC , VSS AV SS V REF RESET X IN X OUT P0 0–P0 7

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Table 1.5.2 Pin description (2) Name I/O port P1 I/O port P2 (7470/7471 group) Input port P2 (7477/7478 group) Input port P3 I/O port P4 Functions

• Port P1 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be connected in units of 4-bit.
• Pins P1 2 and P13 are in common with timer out- put pins T0, T1 respectively.
• In the case of the 7470/7471 group, P14–P1 7 are in common with serial I/O pins SIN, SOUT , CLK, S RDY respectirely.
• In the case of the 7470/7471 group, the outputs of pins SOUT and the SRDY can be N-channel open drain outputs.
• In the case of the 7477/7478 group, P14–P1 7 are in common with serial I/O pins RXD, TX D, SCLK , S RDY, respectively.
• Port P2 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be connected in units of 4-bit.
• Pins P2 0–P2 7 are in common with analog input pins IN0–IN7 respectively. Note: The 7470 group has only the 4 pins P20–P2 3 (IN0–IN3).
• Port P2 is an 8-bit input port.
• It is impossible to connect a pull-up transistor.
• Pins P2 0–P2 7 are in common with analog lnput pins IN0–IN7 respectively. Note: The 7477 group has only the 4 pins P20–P2 3 (IN0–IN3).
• Port P3 is a 4-bit input port.
• Pins P3 0, P31 are in common with external inter- rupt input pins INT0, INT1 respectively.
• Pins P32, P33 are in common with timer input pins CNTR 0, CNTR 1 respectively.
• Port P4 is a 4-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be connected in units of 4-bit. Note: The 7470/7477 group has only 2 pins P4 and P4 1. Input/ Output I/O I/O Input Input I/O Pin P10–P1 7 P20–P2 7 P30–P3 3 P40–P4 3

7470/7471/7477/7478 GROUP USER’S MANUAL1-16 Table 1.5.3 Pin description (3) Name Input port P5 Pin P5 0–P5 3 Input/ Output Input Functions

• Port P5 is a 4-bit input port.
• Pull-up transistor can be connected in units of 4-bit.
• Pins P50, P51 are in common with input/output pins for sub-clock generating circuit XCIN , XCOUT respectively.
• When using pins P50 and P51 as pins XCIN and X COUT , connect a quartz-crystal oscillator between pins XCIN and XCOUT .
• When using pins P50 and P51 as pins XCIN and X COUT , a feedback resistor is connected between pins XCIN and XCOUT .
• To use an external clock input, connect the clock oscillation source to the XCIN pin and leave the X COUT pin open. Note: Only the 7471/7478 group has pins P50–P5 3.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.6 Functional block diagram

Fig. 1.6.1 M37470MX /EX -XXXSP functional block diagram 1324 23 22 21 20 19 9 10 11 12 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 Byte counter(4) Serial I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 384 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) CNTR 0CNTR 1 I/O port P4 Input port P3 VREF Reference voltage input I/O port P2 I/O port P1 I/O port P0 INT1 INT0 (Note 1)(Note 2) Data bus VSS Notes 1 : 4096 bytes for M37470M2-XXXSP, and 8192 bytes for M37470M4/E4-XXXSP 2 : 128 bytes for M37470M2-XXXSP, and 192 bytes for M37470M4/E4-XXXSP M37470M8/E8-XXXSP BLOCK DIAGRAM

7470/7471/7477/7478 GROUP USER’S MANUAL1-18 Fig. 1.6.2 M37471MX/EX -XXXSP, M37471E8SS functional block diagram 19 20 XCIN XCOUT 25 22 21 VCC 181 42 24 23 33 32 31 30 29 28 27 26 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 VSS Clock generating circuit Clock input XIN Clock output XOUT Reset input RESET VCC ROM 16384 bytes Byte counter(4) Serial I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 384 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) CNTR 0CNTR 1 I/O port P4 Input port P3 VREF Reference voltage inputI/O port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) VSS Notes 1 : 4096 bytes for M37471M2-XXXSP, and 8192 bytes for M37471M4/E4-XXXSP 2 : 128 bytes for M37471M2-XXXSP, and 192 bytes for M37471M4/E4-XXXSP M37471M8/E8-XXXSP, M37471E8SS BLOCK DIAGRAM Input Port P5 Data bus

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.6.3 M37471MX /EX -XXXFP functional block diagram 18 19 XCIN XCOUT 28 23 22 VCC 1552 49 26 25 38 37 36 35 33 32 31 30 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6 48 47 46 43 42 41 40 39 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 51 21 VSS AV SS Clock generating circuit Clock input XIN Clock output XOUT Reset input RESET ROM 16384 bytes Byte counter(4) Serial I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 384 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) I/O port P4 Input port P3 VREF Reference voltage inputI/O port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Notes 1 : 4096 bytes for M37471M2-XXXFP, and 8192 bytes for M37471M4/E4-XXXFP 2 : 128 bytes for M37471M2-XXXFP, and 192 bytes for M37471M4/E4-XXXFP M37471M8/E8-XXXFP BLOCK DIAGRAM Input port P5 Data bus

7470/7471/7477/7478 GROUP USER’S MANUAL1-20 Fig. 1.6.4 M37477MX/E8-XXXSP/FP functional block diagram 14 15 18 17 16 VCC 1324 23 22 21 20 19 9 10 11 12 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 CNTR 0CNTR 1 INT1 INT0 VSS P2(4) Clock generating circuit Clock input XIN Clock output XOUT Reset input RESET ROM 16384 bytes Serial I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 384 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) I/O port P4 Input port P3 VREF Reference voltage inputInput port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Data bus Notes 1 : 8192 bytes for M37477M4-XXXSP/FP 2 : 192 bytes for M37477M4-XXXSP/FP M37477M8/E8-XXXSP/FP BLOCK DIAGRAM

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE 181 42 24 23 33 32 31 30 29 28 27 26 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 VSS P2(8) Clock generating circuit Clock input XIN Clock output XOUT Reset input RESET ROM 16384 bytes Serial I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 384 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) I/O port P4 Input port P3 VREF Reference voltage inputInput port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Notes 1 : 8192 bytes for M37478M4-XXXSP 2 : 192 bytes for M37478M4-XXXSP M37478M8/E8-XXXSP, M37478E8SS BLOCK DIAGRAM Input port P5 Fig. 1.6.5 M37478MX /E8-XXXSP, M37478E8SS functional block diagram

7470/7471/7477/7478 GROUP USER’S MANUAL1-22 Fig. 1.6.6 M37478MX/E8-XXXFP functional block diagram 18 19 XCIN XCOUT 28 23 22 VCC 1552 49 26 25 38 37 36 35 33 32 31 30 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6 48 47 46 43 42 41 40 39 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 51 21 VSS AV SS P2(8) Clock generating circuit Clock input XIN Clock output XOUT Reset input RESET ROM 16384 bytes Serial I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 384 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) I/O port P4 Input port P3 VREF Reference voltage inputInput port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Notes 1 : 8192 bytes for M37478M4-XXXFP 2 : 192 bytes for M37478M4-XXXFP M37478M8/E8-XXXFP BLOCK DIAGRAM Input port P5 Data bus

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE The CPU of 7470/7471/7477/7478 group has the following 6 registers (referred as “CPU registers”). Figure 1.7.1 shows a structure of CPU registers. Fig. 1.7.1 Structure of CPU registers Accumulator Index Register X Index Register Y Stack Pointer Program Counter Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag A X Y S PC H PC L NC ZIDBTV 815

7470/7471/7477/7478 GROUP USER’S MANUAL1-24 The CPU register states provided immediately after hardware reset are described below. l The interrupt disable flag (I) of the Processor status register (PS) is set to “1.” l The high-order 8 bits (PCH ) of the Program counter (PC) become the contents of address FFFF16 and the low-order 8 bits (PCL) become the contents of address FFFE16. The contents of the other CPU registers are undefined, so be sure to initialize the CPU registers with the program.

1.7.1 Accumulator (A)

The Accumulator is the central of microcomputer and is an 8-bit register. This accumulator is used for arithmetic operations, data transfer, temporary storage, condition judgment, and is a general-purpose register with the highest frequency of use.

1.7.2 Index register X (X), Index register Y (Y)

The Index register X and the Index register Y are 8-bit registers. In the addressing mode using these Index registers, a value resulting from adding the contents of this register to the operand becomes a real specified address. This addressing mode is used to make reference to a subroutine table or a memory table. The Index registers are provided with increment, decrement, comparison and data transfer functions and can also be used as a simplified accumulator. In the Index register X, when the index X mode flag (T) of the Processor status register is “1,” the contents of the Index register become an operand address.

1.7.3 Stack pointer (S)

The Stack pointer is an 8-bit register which is used to call a subroutine or generate an interrupt. For a branch from a routine being executed to a subroutine or an interrupt processing routine, it is necessary to temporarily store (push) in memory the return address at the termination of this processing. Usually, the internal RAM is used as the push destination, and this area is called a stack area. The stack pointer indicates an address in the stack area to which the data will be pushed next. Figure 1.7.2 shows a push operation to the stack area of the register and a pop operation from the Stack area of the register. The Program counter and registers other than the Processor status register are not automatically pushed. Accordingly, be sure to push necessary registers with the program. The PHA instruction and the PLA instruction are used for push and pop operations of the Accumulator and the PHP instruction and the PLP instruction are used for push and pop operations of the Processor status register. In the 7470/7471/7477/7478 group, the RAM in 0 page or 1 page is available as a stack area. Select it by the stack page bit (bit 2) of the CPU mode register (address 00FB 16), which will be described later (“0” for 0 page or “1” for 1 page). In some products whose RAM capacity is 192 bytes or less, RAM does not exist on 1 page, so be sure to set this bit to “0.” The stack pointer is in an undefined state immediately after hardware reset. Be sure to initialize so as not to destroy the data arranged in the RAM area.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.7.2 Register push and pop at interrupt generation and subroutine call Note : Condition for acceptance of an interrupt Interrupt disable flag is “0” (enable state) Interrupt enable bit is “1” (enable state) On-going routine M(S) (PCH ) (S) (S)–1 M(S) (PCL) (S) (S)–1 Subroutine (S) (S)+1 (PCL) M(S) (S) (S)+1 (PCH ) M(S) (PCH ) M(S) (S) (S)+1 (PCL) M(S) (S) (S)+1 (PS) M(S) (S) (S)+1 Interrupt Service Routine (S) (S)–1 M(S) (PS) (S) (S)–1 M(S) (PC (S) (S)–1 M(S) (PCH ) Execute JSR Execute RTI Execute RTS Push return address on stack Pop return address from stack Pop contents of Processor status register from stack Pop return address from stack Push contents of Processor status register on stack Push return address on stack When a subroutine is called When an interrupt is accepted Interrupt request (Note) I Flag is set from “0” to “1” Fetch the Jump Vector : Operation which is automatically performed by hardware : Operation instructed by software

7470/7471/7477/7478 GROUP USER’S MANUAL1-26

1.7.4 Program counter (PC)

The Program counter is a 16-bit counter consisting of an 8-bit register PCH and an 8-bit register PCL. This counter indicates the address at which the next instruction to be executed is stored. The contents of this counter are automatically pushed to the stack when a subroutine is called or an interrupt occurs. The high-order 8 bits (PC H ) of the program counter become the contents of address FFFF16 and the low- order 8 bits (PCL) become the contents of address FFFE16 immediately after hardware reset.

1.7.5 Processor status register (PS)

The Processor status register is an 8-bit register consisting of 5 flags to indicate the state immediately after arithmetic processing and 3 flags to determine an operation for the CPU. Each bit of the Processor status register is described below. The carry flag holds the carry or borrow from the arithmetic logical unit after arithmetic processing. This flag is also changed by the Shift instruction or Rotate instruction. This flag is set to “1” by the SEC instruction and cleared to “0” by the CLC instruction. The zero flag is set to “1” when the arithmetic processing or data transfer result is “0” and cleared to “0” in all other cases. In the decimal operation mode, this flag is invalidated. There is no instruction to change the contents of this flag. The interrupt request flag disables all instructions (except an interrupt by the BRK instruction). When this flag is “1,” the interrupt disable state is provided. This flag is set to “1” by accepting an interrupt, thereby disabling a multi-interrupt. This flag is set to “1” by the SEI instruction and cleared to “0” by the CLI instruction. This flag is set to “1” (interrupt disable state) immediately after hardware reset. The decimal mode flag determines whether addition and subtraction should be performed in binary or decimal notation. When the contents of this flag are “0,” an ordinary binary operation is performed. When they are “1,” an arithmetic operation is performed assuming that one word is a 2-digit decimal number. In a decimal operation, decimal compensation is automatically performed (decimal operation can be performed only by the ADC instruction and the SBC instruction). This flag is set to “1” by the SED instruction and cleared to “0” by the CLD instruction. This flag is put in an undefined state immediately after hardware reset. As this flag directly affects arithmetic operations, be sure to initialize it. The break flag identifies whether or not an interrupt has been caused by the BRK instruction. The BRK instruction is used for program debugging and performs the same operation as an interrupt is performed by executing the BRK instruction. The Processor status register is pushed to the stack, after the B flag is automatically set to “1” in case of the BRK instruction interrupt, or after the B flag is automatically cleared to “0” in case of the other interrupts. There is no instruction to change the contents of this flag.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE When the Index X mode flag is “0,” arithmetic operations are performed between the Accumulator and the memory. When this flag is “1,” direct arithmetic operations and direct data transfer between one memory and another, between a memory and an I/O, or between one I/O and another without passing through the accumulator. An arithmetic operation result between memory 1 directly specified by the Index register X and memory 2 specified by an operand is stored into memory 1.

1 When the T flag is “0” A ← A ] M

2 When the T flag is “1” M 1 ← M 1 ] M 2

] : Denotes an arithmetic operation A : Content of accumulataor M 1 : Contents of memory 1 directly specified by the Index register X M 2 : Contents of memory 2 specified by the operand This flag is set to "1" by the SET instruction and cleared to "0" by the CLT instruction. This flag is in the undefined state immediately after hardware resetting. This flag has a direct effect on arithmetic operations. Accordingly, be sure to initialize it. The contents of the overflow flag have significance when addition and subtraction are performed assuming that one word is a signed binary number. When an addition or subtraction result exceeds the range of +127 to –128, this flag is set to “1.” When the BIT instruction is executed for other cases, the contents of bit 6 of the executed memory are put into the overflow flag. This flag is cleared to “0” by the CLV instruction, but there is no instruction to set this flag to “1.” In the decimal operation mode, this flag is invalidated. The negative flag is set to “1” when an arithmetic processing or data transfer result is negative (bit 7 is “1”). The contents of bit 7 of the executed memory are put into this flag when the BIT instruction is executed. There is no instruction to change the contents of this flag. In the decimal operation mode, this flag is invalidated.

7470/7471/7477/7478 GROUP USER’S MANUAL1-28 In the 7470/7471/7477/7478 group, all ROM, RAM and I/O and the various control registers are located in the same memory area. Accordingly, the same instructions are used for data transfer and arithmetic operations without discriminating between a memory and an I/O. The Program counter consists of 16 bits and the access space is 64K-byte of memory area: addresses 0000 16 to FFFF16. The area of the least significant 256 bytes (addresses 000016 to 00FF16) is called the “zero page,” and memories with a high frequency of use such as internal RAM, I/O ports and timers are located here. The area of the most significant 256 bytes (addresses FF00 16 to FFFF16) is called the “special page,” and an internal ROM and interrupt vectors are located here. The zero page and the special page can be accessed with 2 bytes by using each special addressing mode. Figure 1.8.1 shows an outline of accsess area. Fig. 1.8.1 Access area Interrupt vector area ROM RAM RAM SFR area 000016 00C0 16 00FF 16 FFFF 16 FF00 16 Zero page Special page

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.8.1 Zero page (Addresses 000016 to 00FF16)

The area of 256 bytes from addresses 000016 to 00FF16 is called the zero page. The internal RAM and the special function register (SFR) are located in this area. To specify a memory or a register in this area, use the addressing mode shown in Table 1.8.1. In this area, especially, it is possible to access this area in a shorter instruction cycle by using the zero addressing mode.

1.8.2 Special page (Addresses FF00

16 to FFFF16) The area of 256 bytes from addresses FF0016 to FFFF16 is called the special page. The internal ROM and the interrupt vector area are located in this area. To specify a memory or subroutine in this area, use the addressing mode shown in Table 1.8.1. In this area, especially, it is possible to jump to this area in a shorter instruction cycle by using the special page addressing mode. Ordinary, subroutines with high frequency of use are located in this area. Table 1.8.1 Addressing mode accessible to each area Addressing mode (bytes required) Zero page (2) Zero page indirect (2) Zero page X (2) Zero page Y (2) Zero page bit (2) Zero page bit relative (3) Absolute (3) Absolute X (3) Absolute Y (3) Relative (2) Indirect (3) Indirect X (2) Indirect Y (2) Special page (2) Special page reference Other area reference Zero page reference

7470/7471/7477/7478 GROUP USER’S MANUAL1-30 The memories, I/Os and others located in the access area are explained below. l RAM An internal RAM is located in each area shown in Table 1.9.1. The internal RAM is used as a data storage area and a stack area for subroutine call and interrupt occurrence. When the RAM is used as a stack area, be careful about subroutine nesting depth and interrupt levels so that the data in the RAM is not destroyed. l Special function register (SFR) (Addresses 00C0 16 to 00FF16) The area from addresses 00C016 to 00FF16 is assigned to the SFR (Special Function Register). Various control registers such as I/O ports, timers, serial I/Os, A-D converters and interrupts are located in this SFR. Figure 1.9.3 shows the special function register (SFR)memory map. l ROM An internal ROM is located in each area shown in Table 1.9.2. The internal ROM is used to store data tables and programs. In the internal ROM, a vector area to store jump destination addresses upon a reset or occurrence of interrupt are assigned to addresses FFEA 16 to FFFF16 in the 7470/7471 group and to addresses FFE816 to FFFF16 in the 7477/7478 group. Figure 1.9.4 shows the interrupt vector memory map. Table 1.9.1 RAM area Table 1.9.2 ROM area Product M3747xM2 M3747xM4/E4 M3747xM8/E8 Range Addresses 0000 16 to 007F16 Addresses 000016 to 00BF16 Addresses 000016 to 00BF16, Addresses 010016 to 01BF16 Memory size 128 5 8-bit 192 5 8-bit 384 5 8-bit Product M3747xM2 M3747xM4 M3747xE4 M3747xM8 M3747xE8 Memory size 04K 5 8-bit 08K 5 8-bit 16K 5 8-bit Memory type Mask ROM Mask ROM Programmable ROM Mask ROM Programmable ROM Range Addresses F000 16 to FFFF16 Addresses E000 16 to FFFF16 Addresses C000 16 to FFFF16

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.9.1 Memory allocation of 7470/7471 group 000016 007F16 00C0 16 00FF 16 F00016 FF00 16 FFEA 16 FFFF 16 000016 007F16 00C0 16 00FF 16 01BF 16 C000 16 FF00 16 FFEA 16 FFFF 16 010016 Interrupt vector area RAM (128 bytes) ROM (4096 bytes) ROM (16384 bytes) Interrupt vector area SFR area SFR area RAM (192 bytes) RAM (192 bytes) Zero page Special page M37470M2 M37471M2 M37470M8/E8 M37471M8/E8 Not used 000016 007F16 00C0 16 00FF 16 E000 16 FF00 16 FFEA 16 FFFF 16 RAM (192 bytes) ROM (8192 bytes) Interrupt vector area SFR area M37470M4/E4 M37471M4/E4 Not used Not used Not used

7470/7471/7477/7478 GROUP USER’S MANUAL1-32 Fig. 1.9.2 Memory allocation of 7477/7478 group 000016 007F16 00C0 16 00FF16 01BF 16 C000 16 FF0016 FFE8 16 FFFF 16 010016 ROM (16384 bytes) Interrupt vector area SFR area RAM (192 bytes) RAM (192 bytes) Zero page Special page M37477M8/E8 M37478M8/E8 RAM (192 bytes) ROM (8192 bytes) Interrupt vector area SFR area M37477M4 M37478M4 Not used Not used FF0016 FFE8 16 FFFF 16 000016 007F16 00C0 16 00FF 16 E00016

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.9.3 Special function register (SFR) memory map 00E0 16 00E1 16 00E2 16 00E3 16 00E4 16 00E5 16 00E6 16 00E7 16 00E8 16 00E9 16 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 (Note 2) Transmit/receive buffer register Serial I/O control register Baud rate generator Port P0 direction register Port P1 direction register Port P2 direction register (Note 1) Port P4 direction register Serial I/O status register UART control register 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 Port P0 pull-up control register Edge polarity selection register Input latch register A-D conversion register Serial I/O mode register Serial I/O counter Timer 1 Timer 3 Timer 12 mode register Timer mode register 2 Interrupt request register 1 Interrupt control register 1 Port P1-P5 pull-up control register (Note 3) A-D control register Serial I/O register Timer 2 Timer 4 Timer FF register Timer 34 mode register CPU mode register Interrupt request register 2 Interrupt control register 2 Byte counter (Note 5) (Note 4) Notes 1: In the 7477/7478 group, this register is not located. 2: In the 7470/7477 group, this register is not located. 3: This address is allocated P1-P4 pull-up control register for the 7470/7477 group. 4: In the 7477/7478 group, this register is not located. 5: In the 7470/7471 group, this register is not located.

7470/7471/7477/7478 GROUP USER’S MANUAL1-34 Fig. 1.9.4 Interrupt vector memory map FFEB 16 FFEC 16 FFED 16 FFEE 16 FFEA 16 FFEF 16 FFF0 16 FFF1 16 FFF2 16 FFF3 16 FFF4 16 FFF5 16 FFF6 16 FFF7 16 FFF8 16 FFF9 16 FFFA 16 FFFB 16 FFFC 16 FFFD 16 FFFE 16 FFFF 16 FFE9 16 FFE8 16 FFEB 16 FFEC 16 FFED 16 FFEE 16 FFEA 16 FFEF 16 FFF0 16 FFF1 16 FFF2 16 FFF3 16 FFF4 16 FFF5 16 FFF6 16 FFF7 16 FFF8 16 FFF9 16 FFFA 16 FFFB 16 FFFC 16 FFFD 16 FFFE 16 FFFF 16 A-D conversion completion interrupt Serial I/O interrupt Timer 4 interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt CNTR 0 interrupt or CNTR1 interrupt INT1 interrupt or key on wake up interrpt INT0 interrupt BRK instruction interrupt RESET A-D conversion completion interrupt Serial I/O receive interrupt Timer 4 interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt CNTR 0 interrupt or CNTR1 interrupt INT1 interrupt or key on wake up interrpt INT0 interrupt BRK instruction interrupt RESET Serial I/O transmit interrupt 7470/7471 group 7477/7478 group

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE The 7470/7471/7477/7478 group is provided with the following I/O pins. l I/O port (P0 to P5) l Reset input (RESET ) l Clock input/output (XIN, XOUT , XCIN , XCOUT ) l A-D convesion reference voltage input (VREF ) l Power supply voltage input (VCC , VSS , AVSS ) Notes 1: The 7470/7477 group is not provided with port P5 and pins XCIN and XCOUT . 2: The AV SS pin is dedicated to the 56P6N-A package product. For an outline of each pin, refer to “1.5 Pin description.” 1.10.1. I/O port (1) I/O port writing and reading

2 The input-only pin and the programmable I/O port set as input port

The values (pin states) which input to the input-only pin and to the programmable I/O port set as input port can be read in by reading the Port register corresponding to each port. When data is written into the Port register corresponding to each port, it can be only written in the Port register and has no effect on the pin state.

2 The programmable I/O port set as an output port

The value written into the Port register corresponding to the programmable I/O port set as an output port is output to the outside by way of a transistor. When the Port register corresponding to each port has been read, each pin state is not read in but the value written into the Port register is read. Accordingly, if the output “H” voltage has been reduced or the output “L” voltage has been increased by an external load, the previous output value can be correctly read. Figure 1.10.1 shows the I/O port writing and reading and Table 1.10.1 shows the port register address allocation.

7470/7471/7477/7478 GROUP USER’S MANUAL1-36 Fig. 1.10.1 I/O port writing and reading Port register P5 (Note) Table 1.10.1 Port register address allocation Address 00C0 16 00C2 16 00C4 16 00C6 16 00C8 16 00CA 16 Note: The 7470/7477 group is not provided with P5. : The P channel transistor and the N channel transistor are in a cut-off state. At output : An output value can be set by writing to the Port register Port direction register ( “1” ) “H” level output “L”level output At input : A write operation is enabled to the Port register. Port register (When Writing) Port register (When Reading) Port direction register ( “0” ) Each pin state can be read in by reading the Port register. Port register. The Port register can be read out.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Port Pi direction register (PiD) (i = 0,1,2,4) [Address 00C116, 00C316, 00C516, 00C916] Port Pi direction register Port Pi direction register 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode B RWName Function Notes 1: The 7477/7478 group is not provided with the port P2 direction register (input only). The Port P4 is provided as below:

• 7470/7477 group has 2 bits of P4 0 and P41.
• 7471/7478 group has 4 bits of P40 to P43. b1b2b3b4b5b6b7 (2) Input/output selection of the programmable I/O ports An input/output selection of the programmable I/O ports is made by the Port direction register corresponding to each port. Figure 1.10.2 shows a structure of Port Pi (i = 0, 1, 2, 4) direction register. Note: Each direction register is initialized into “00 16” at reset, so that the I/O ports are put into an input state. Fig. 1.10.2 Structure of Port Pi direction register (i=0, 1, 2, 4)

7470/7471/7477/7478 GROUP USER’S MANUAL1-38 (3) Pull-up control When input has been selected by the Port direction register, pull-up control can be exerted in bit units shown in Table 1.10.1 by the Port P0 pull-up control register (address 00D016) or the Port P1–P5 pull-up control register* (address 00D116). At this time, control is exerted by turning on and off the pull-up transistor. *: The Port P1–P4 pull-up control register is arranged in the 7470/7477 group. Note: Ports other than P0 cannot be controlled in one-bit units. For example, when P1 0 is pulled up at P1 (pull-up control in units of 4 bits), P11 to P13 are also pulled up. Figure 1.10.3 shows a structure of Port P0 pull-up control register, and Figure 1.10.4 shows a structure of Port P1–P5 pull-up control register. Fig. 1.10.3 Structure of Port P0 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Name Function At resetRW Port P0 pull-up control register Port P0 pull-up control register Port P00 pull-up control bit B Port P01 pull-up control bit Port P02 pull-up control bit Port P03 pull-up control bit Port P04 pull-up control bit Port P05 pull-up control bit Port P0 6 pull-up control bit Port P0 7 pull-up control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up [Address 00D016]

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.10.4 Structure of Ports P1 to P5 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Nameb Function At resetRW Ports P1 to P5 pull-up control register [Address Ports P1 to P5 pull-up control register 3 0 4 0 0 : No pull-up 1 : Pull-up Notes Ports P10 to P13 pull-up control bit Ports P40 to P43 pull-up control bit (Note 4) Ports P24 to P27 pull-up control bit (Notes 2, 3) Ports P20 to P23 pull-up control bit (Note 2) Ports P14 to P17 pull-up control bit 1 : In the 7470/7477 group, the P1 to P4 Pull-up control register is provided. 2 : In the 7477/7478 group, nothing is allocated to these bits. They are undefined at reading. 3 : In the 7470/7477 group, nothing is allocated to these bits. They are undefined at reading. 4 : The 7470/7477 group is provided with only Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Ports P50 to P53 pull-up control bit (Note 3) 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 00D1 16] P40 and P41.

7470/7471/7477/7478 GROUP USER’S MANUAL1-40

1.10.2 Port block diagram

Fig. 1.10.5 Block diagram of Ports P0, P10 to P13 Port P13 Tr2 Pull-up control register Port P1 T34M 7 Port P12 Tr3T12M 3 Port P11 Tr4 Port P10 Tr5 Port latch Direction register Tr1-Tr5 are pull-up transistors Port P0 Tr1 Data bus Port P0 Data bus Data bus Data bus Data bus Data bus Direction register Port latch Direction register Port latch Port latch Direction register Pull-up control register Direction register Port latch Interrupt control circuit

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.10.6 Block diagram of Ports P14 to P17 (7470/7471 group) Port P14-P17 Port P17 Tr6 Port latch Direction register Data bus SM 7 SRDY SM 4 Port P16 Tr7 SM 2 CLK output SM 3 CLK input Port P15 Tr8SM 3 SOUT SM 7 Tr6-Tr9 are pull-up transistors Port P14 Tr9 SIN Data bus Direction register Port latch Direction register Port latch Data bus Data bus Data bus Direction register Port latch Pull-up control register

7470/7471/7477/7478 GROUP USER’S MANUAL1-42 Fig. 1.10.7 Block diagram of Ports P14 to P17 (7477/7478 group) Port latch Direction register SIOM SRDY SIOE SIOM SIOE Port latch Direction register SIOE TE Port latch Direction register SIOE RE Port latch Direction register Pull-up control register SCS SIOE SRDY SCLK output TXD R XD SCLK input Port P17 Port P16 Port P15 Port P14 Tr7 Tr8 Tr9 Tr6 Port P14-P17 Data bus Data bus Data bus Data bus Data bus T r6-Tr9 are pull-up transistors

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (7470/7471 group) Tr10 (7477/7478 group) Port P2 Tr10 A-D conversion circuit Tr10 and Tr11 are pull-up transistors Port P4 : Control in units of 4-bit (Control in units of 2-bit for 7470/7477 group) : Control in units of 4-bit Port P2 (7470/7471 group) Port latch Pull-up control register Direction register Port P4 Data bus Data bus Data bus Data bus Port P3 INT0, INT1 CNTR 0, CNTR1 Port P3 Data bus Multi- plexer Direction register Port latch Pull-up control register Multi- plexer Port P2 (7477/7478 group) Data bus A-D conversion circuit Port P2 Fig. 1.10.8 Block diagram of Ports P2 to P4

7470/7471/7477/7478 GROUP USER’S MANUAL1-44 Fig. 1.10.9 Block diagram of Port P5 Port P53 Tr12 Data bus Port P5 (7471/7478 group) Port P52 Tr13 Port P51 Tr14CM 4 Port P50 Tr15CM 4 CM 4 XCIN CM 4 Tr11-Tr15 are pull-up transistors Pull-up control register Data bus Data bus Data bus Data bus (7471 group) Tr11 (7478 group ) (7471 group) (7478 group) (7471 group) (7478 group) (7471 group) (7478 group) Tr12 Tr13 Tr14

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.10.3 Notes on use

When using I/O ports, note the following. (1) Modify of the content of I/O port latch When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. Reason The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit. Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed to all bits of the port latch. l As for a bit which is set as an input port: The pin state is read in the CPU, and is written to this bit after bit managing. l As for a bit which is set as an output port: The bit value is read in the CPU, and is written to this bit after bit managing. Make sure the following: l Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. l Even when a bit of a port latch which is set as an input port is not specified with a bit managing instruction, its value may be changed in case where content of the pin differs from a content of the port latch. ∗ bit managing instructions: SEB and CLB instruction (2) Pull-up control To pull-up ports by software, note the following. l When P1 is used in the serial I/O mode, the pull-up settings corresponding to P1 4 to P17 are invalidated (pull-up is impossible). Refer to the port block diagram for details. l When a port is set in the output mode, the pull-up setting corresponding to the port is invalidated (pull-up is impossible). l Ports other than P0 cannot be controlled in one-bit units. For example, when P1 0 is pulled up at P1 (pull-up control in units of 4 bits), P11 to P13 are also pulled up.

7470/7471/7477/7478 GROUP USER’S MANUAL1-46 (3) Fix of a port input level in stand-by state Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state∗, especially for the I/O ports of the N-channel open-drain. Pull-up (connect the port to VCC ) or pull-down (connect the port to VSS ) these ports through a resistor. When determining a resistance value, make sure the following: l External circuit l Variation of output levels during the ordinary operation ∗: “Stand-by state”:The stop mode by execution of the STP instruction or the wait mode by execution of the WIT instruction: Reason Even when setting as an output port with its direction register, in the following state: the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I/O port are “undefined.” This may cause power source current.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE P1 5, P17 P2 (7470/7471 group) P1 4, P16 P2 (7477/7478 group) P3 0 to P33 (Note 7) V REF AV SS Terminations (Note 1) (Note 3) (Note 1) Pull down (connect to V SS ) ports through a resistor (Note 2) (Note 5) (Note 5) (Note 6) (Note 6) (Note 8) Connect to V CC (Note 6) (Note 6) (4) Termination of unused pins Table 1.10.2 shows a termination of unused pins. Table 1.10.2 Termination of unused pins Notes 1:A pin that can be opened at the unused time has a circuit that does not allow a current to flow into itself unless any read signal is internally input even if a medium-level input is applied at the open state. 2: For programmable I/O ports, do not connect two or more ports together through a resistor to V CC or VSS . 3: Note the following when setting them to the output mode and making the pins open.

• The ports function as input ports in the period from reset release till switching the ports to the output mode by software. Accordingly, the power source current may be increased depending on the input levels of the pins.
• If the Port direction register has been changed into the input mode by runaway or noise, re-set the Port direction register to the output mode periodically by software. 4: To pull up a pin, set the Port direction register and the Port latch so that this pin may be into the input mode or “H” output state. 5: To pull down a pin, set the Port direction register, the Port pull-up control register and the Port latch so that this pin may be put in the no pull-up transistor state in the input mode or in the “L” output state. 6: These pins are connect to the V CC or VSS without a resistor when the wiring is the shortest. However, they are connect to the VCC or VSS through a resistor. In addition, the P33 pin of the built-in programmable ROM version is used in common with the VPP pin, insert a resistor of about 5 k in series and connect by the shortest wiring. 7: When using neither the P50 pin nor the P51 pin (used in common with the XCIN and XCOUT pin), set bit 4 of the CPU mode register to “0” (P50 and P51 functions). 8: To pull down a pin, set the port pull-up control register so that a pull-up transistor will not be provided for this pin. Pull-up (connect to VCC ) ports through a resistor (Note 2) (Note 4) (Note 4) (Note 6) (Note 6) Connect to V SS (Note 6) (Note 6) Open

7470/7471/7477/7478 GROUP USER’S MANUAL1-48 Interrupts are used in the following cases. l When it is requested to execute higher-priority processing than the processing routine being executed. l When it is necessary to observe any timing for processing. The 7470/7471 group can generate interrupts from 12 sources and the 7477/7478 group can generate interrupts from 13 sources.

1.11.1 Description of interrupt source

22222 Priority of interrupt

The interrupts are vector interrupts with a fixed priority sequence. When two or more interrupt requests occur at the same sampling time, they are accepted starting with the highest-priority interrupt. This priority is determined by hardware. However, a variety of priority processing can be executed by software when the interrupt control flags (interrupt enable bit and interrupt disable flag) are used.

22222 Acceptance of interrupt

The corresponding interrupt request bit is set to “1” upon occurrence of an interrupt. When the following conditions are satisfied in this state, this interrupt is accepted. For the details, refer to “1.11.3 Interrupt control.”

1 When the interrupt disable flag is cleared to “0” (interrupt enable state)

2 When the interrupt enable bit is set to “1” (interrupt enable state)

Table 1.11.1 shows an interrupt priority, interrupt sources and vector addresses. Table 1.11.1 Interrupt sources and priority Interrupt source High FFFF 16 FFFD 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 Non-maskable Polarity programmable INT 1: polarity programmable Polarity programmable BRK instruction interrupt is non- maskable software interrupt Lower FFFE 16 FFFC 16 FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 Remark Reset (Note) INT 0 interrupt INT1 interrupt or key-on wake up interrupt CNTR 0 interrupt or CNTR1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Priority Serial I/O interrupt A-D conversion completion interrupt BRK instruction interrupt 7470/7471 group 7477/7478 group Vector address Note: A reset operation is performed in the same way as an interrupt, so it is described in the table. Serial I/O receive interrupt Serial I/O transmit interrupt A-D conversion completion interrupt BRK instruction interrupt

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (1) INT interrupt When detecting a rising edge or a falling edge of each INT pin (INT0, INT1), the microcomputer generates an INT interrupt request.These polarity is selected by the edge polarity selection register (EG: Address 00D416).

22222 P30, P31 pins

The INT0 and INT1 pins are used in common with the P30 and P31 pins and always detect the levels of P30 and P31.

22222 In the stop mode/wait mode

When bit 5 of the Edge polarity selection register is “0,” a restoration can be attained by the INT interrupt from the stop mode/wait mode state provided by the STP/WIT instruction. For the details, refer to “1.17 Low-power dissipation function.”

22222 After reset

At reset release, the Edge polarity selection register is cleared to “00 16,” so the INT0 and INT1 interrupts generate the interrupt request by detecting a falling edge. At reset release, however, the Interrupt control register is put into the interrupt disable state, so any interrupt is not accepted. Note: The INT 0 and INT1 pins are used in common with input port P30 and P31, however, there is no register for switching between the INT pins and the ports, so the active edges of P30 and P3 1 are always detected. When these pins are used as ports, put the corresponding INT interrupt into the disable state. In the INT interrupt enable state, the INT interrupt is generated by a pin level change, thereby causing a program run away. (2) Key-on wake up interrupt When bit 5 of the Edge polarity selection register is “1,” the key-on wake up interrupt request is generated by applying the “L” level to any pin of P0 being an input port in the stop mode/wait mode provided by the STP/WIT instruction, so that a recovery can be attained from the stop mode/wait mode. At reset release, bit 5 of the Edge polarity selection register is cleared to “0” so that the key-on wake up interrupt request does not occur in the stop mode/wait mode. Notes 1: In modes other than the stop mode/wait mode, the key-on wake up interrupt is disabled. 2: To select the stop mode/wait mode by the STP/WIT instruction when the interrupt disable flag is cleared to “0” and bit 5 of the Edge polarity selection register is set to “1,” set every input to P0 to “H.”

7470/7471/7477/7478 GROUP USER’S MANUAL1-50 Figure 1.11.1 shows a block diagram of interrupt input and key-on wake up circuit. Fig. 1.11.1 Block diagram of interrupt input and key-on wake up circuit P33/CNTR 1 P32/CNTR 0 P30/INT0 P31/INT1 P07 P01 EG 3 EG 2 Port P33 data read circuit EG 4 CNTR interrupt request signal Port P32 data read circuit CM 7 EG 0 XIN X CIN Port P30 data read circuit INT0 interrupt request signal Port P31 data read circuit INT1 interrupt request signal Noise elimination circuit CPU stop state signal Port P0 data read circuit EG 1 EG 5 P00 Pull-up control register Direction register Note: The 7470/7477 group is not provided with the Pull-up control register Direction register Pull-up control register Direction register Noise elimination circuit XCIN pin.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (3) CNTR interrupt When detecting a rising edge or a falling edge of each CNTR pin (CNTR0, CNTR 1), the microcomputer generates an CNTR interrupt. For selecting the active edge of interrupt and the CNTR0/CNTR 1 pin, the Edge polarity selection register (EG) is used. At reset release, the Edge polarity selection register is cleared to “0016,” so the CNTR0 interrupts generate the interrupt request by detecting a falling edge. At reset release, however, the Interrupt control register is put into the interrupt disable state, so any interrupt is not accepted. Note: The CNTR 0 and CNTR 1 pins are used in common with input port P32 and P33, however there is no register for switching between the CNTR pins and the ports, so the active edges of P32 and P33 are always detected. When these pins are used as ports, put the corresponding CNTR interrupt into the disable state. In the CNTR interrupt enable state, the CNTR interrupt is generated by a pin level change, thereby causing a program run away. (4) Timer interrupt The microcomputer generates the interrupt request at the rise of the next count source after the respective timer overflows. For the details of the timer interrupt, refer to “1.12 Timers.” (5) Serial I/O interrupt There is a difference in the serial I/O interrupt between the 7470/7471 group and the 7477/7478 group.

22222 Serial I/O interrupt of 7470/7471 group

An interrupt request is generated upon termination of the serial I/O transmit/receive.

22222 Serial I/O interrupt of 7477/7478 group

The serial I/O transmit interrupt and the serial I/O receive interrupt are available. l Serial I/O transmit interrupt For the Serial I/O transmit interrupt, interrupt request generation timing can be selected by bit 3 of the Serial I/O control register (SIOCON: Address 00E2 16) as shown below. 0: The data written in the Transmit buffer is transferred to the Transmit shift register, and when the Transmit buffer becomes empty, the interrupt request is generated. 1: The interrupt request is generated when a shift operation of the Transmit shift register terminates. Note: When the transmit enable bit is set to the enable state, the Transmit buffer becomes empty and the transmit shift terminates. Accordingly, the interrupt request can be generated by selecting one of these sources. To use the transmit interrupt, set the transmit enable bit to “1,” clear the transmit interrupt request bit to “0,” and then set the transmit interrupt enable bit to the enable state. l Serial I/O receive interrupt When all data has been put in the Receive shift register and the contents of the shift register have been transferred to the Receive buffer, the interrupt request is generated. For the details of the serial I/O interrupt, refer to “1.13 Serial I/O.” (6) A-D conversion completion interrupt As soon as A-D conversion terminates, the interrupt request is generated. For the details of the A-D conversion completion interrupt, refer to “1.14 A-D Converter.” (7) BRK instruction interrupt This is the lowest-priority software interrupt without any corresponding interrupt enable flag, and not affected by the interrupt disable flag. (Non maskable) For the details, refer to “SERIES 740 SOFTWARE USER’S MANUAL.”

7470/7471/7477/7478 GROUP USER’S MANUAL1-52

1.11.2 Operation description

(1) Interrupt operation After an interrupt is accepted, the contents of the register shown below are automatically pushed to the stack area in sequence in the order of 1, 2 and 3.

1 Program counter high-order (PCH )

2 Program counter low-order (PCL)

3 Processor status register (PS)

After the above register is pushed, a branch is made to the vector address of the accepted interrupt. When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the above register which were pushed onto the stack area are popped to the respective registers in sequence in the order of 3, 2 and 1, and the processing precedent to the acceptance of the interrupt is restarted. Figure 1.11.2 shows the interrupt operation. Fig. 1.11.2 Interrupt operation Interrupt occurs (Accepting interrupt request) Executing routine RTI instruction Interrupt processing routine Suspended operation Resume processing : Operation commanded by software : Internal operation to be performed automatically Contents of Program counter (high-order) are pushed onto stack Contents of Program counter (low-order) are pushed onto stack Contents of Processor status register are pushed onto stack Contents of Processor status register are popped from stack Contents of Program counter (low-order) are popped from stack Contents of Program counter (high-order) are popped from stack

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Program counter (high-order) Program counter (low-order) (S) (from Interrupt vector area) Vector address (S) – 3 Processor status register Program counter (low-order) Program counter (high-order) Interrupt request is accepted Interrupt disable flag = “1” Interrupt disable flag = “0” S PC H PC L S PC H PC L (S) (S) – 3 (S) Stack areaProgram counter Stack pointer (2) Processing upon acceptance of interrupt When an interrupt is accepted, the following operations are automatically performed. 1 The processing being executed is interrupted.

2 The contents of the Program counter and the Processor status register are pushed to the stack

area. Figure 1.11.3 shows a change of the contents of the Program counter and the Stack pointer upon acceptance of the interrupt.

3 The vector address (start address of the interrupt processing routine) stored in the vector area

corresponding to the generated interrupt concurrently with pushing is set in the Program counter and the interrupt processing routine is executed. 4 After the interrupt processing routine is started, the corresponding interrupt request bit is automatically cleared to “0.” The interrupt disable flag is set to “1,” thereby disabling a multi-interrupt. To execute the interrupt processing routine, it is necessary to set a vector address in the vector area corresponding to each interrupt beforehand. Fig. 1.11.3 Changes of contents of Program counter and Stack pointer upon acceptance of interrupt

7470/7471/7477/7478 GROUP USER’S MANUAL1-54 Interrupt request occurs Main routine Interrupt processing routine 7 to 23 cycles (At internal system clock φ = 4 MHz , 1.75 µs to 5.75 µs) 2 cycles 5 cycles Waiting time for pipeline post- processing Push onto stack Vector fetch Interrupt operation starts 0 to 16 cycles∗ ∗: At the DIV instruction executed. (3) Timing after acceptance of interrupt The interrupt processing routine starts with the machine cycle after termination of the instruction being executed. Figure 1.11.4 shows a processing time up to the execution of the interrupt processing routine and Figure 1.11.5 shows a timing after acceptance of the interrupt. Fig. 1.11.4 Processing time up to the execution of interrupt processing routine Fig. 1.11.5 Timing after acceptance of interrupt SYNC Waiting time for pipeline postprocessing Push onto stack Vector fetch Interrupt operation starts Address bus Data bus Not used PC H PC L PS AL AH S, SPS S-2, SPSS-1, SPSPC BL BH AL, AH : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) : Vector address of each interrupt : Jump destination address of each interrupt : “00 16” or “01 (when the stack page bit is “0,” SPS is R/W SYNC BL, BH AL, AH SPS φ “010016,” and when the bit is “1,” SPS is 16” 16”)

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Serial I/O (7470/7471 group) Serial I/O receive (7477/7478 group) Serial I/O transmit (7477/7478 group) A-D conversion INT INT1 CNTR 0/CNTR 1

1.11.3 Interrupt control

Regarding interrupts other than the BRK instruction, the acceptance of them can be controlled by the interrupt request bit, the interrupt enable bit and the interrupt disable flag. This section describes interrupt control other than the BRK instruction. Figure 1.11.6 shows a interrupt control diagram.Interrupt source Address 00FC 16 00FC 16 00FC 16 00FC 16 00FC 16 00FC 16 00FC 16 00FC 16 00FD 16 00FD 16 00FD 16 Bits b6 (Note 1) b5 (Note 2) b6 (Note 2) Bits b6 (Note 1) b5 (Note 2) b6 (Note 2) Interrupt request bits Interrupt enable bits Notes 1: This bit is not provided in the 7477/7478 group. 2: This bit is not provided in the 7470/7471 group. Fig. 1.11.6 Interrupt control diagram The interrupt request bit, the interrupt enable bit and the interrupt disable flag function independently and do not affect one another. An interrupt is accepted when all the following conditions are satisfied. The priority is determined by hardware. However, a variety of priority processing can be executed by software when the above flag and bits are used. Table 1.11.2 shows a interrupt control bits for individual interrupt sources. Table 1.11.2 Interrupt control bits for individual interrupt sources Interrupt request bit Interrupt enable bit Interrupt disable flag BRK instruction Reset Interrupt accepted

7470/7471/7477/7478 GROUP USER’S MANUAL1-56 (1) Interrupt request bit The interrupt request bits are assigned to each bit of the Interrupt request register 1(IR1: Address 00FC 16) and the Interrupt request register 2(IR2: Address 00FD16). If an interrupt request occurs, the corresponding interrupt request bit is set to “1.” The interrupt request bit is held in the “1” state until the interrupt is accepted. After it is accepted, this bit is automatically cleared to “0.” The interrupt request bit can be cleared to “0” by software but cannot be set to “1” by software. (2) Interrupt enable bit The interrupt enable bits are assigned to each bit of the Interrupt control register 1 (IE1: Address 00FE 16) and the Interrupt control register 2 (IE2: Address 00FF16). The interrupt enable bit controls the acceptance of the corresponding interrupt. When the interrupt enable bit is “0,” the acceptance of the corresponding interrupt is disabled. If an interrupt request occurs when this bit is “0,” the corresponding interrupt request bit is set to “1,” but this interrupt is not accepted. In this case, the interrupt request bit is cleared to “0” by software or remains in the “1” state until the interrupt enable bit is set to “1.” When an interrupt enable bit is “1,” the corresponding interrupt is enabled. If an interrupt request occurs when this bit is “1,” this interrupt is accepted. (However, the interrupt disable flag that will be described later must be “0.”) The interrupt enable bit can be cleared to “0” or set to “1” by software. (3) Interrupt disable flag The interrupt disable flag controls the acceptance of the interrupt, and is assigned to bit 2 of the Processor status register (PS). When this flag is “1,” the interrupt disable state is provided. When this flag is “0,” the acceptance of interrupt is enable state. This flag is set to “1” by the SEI instruction and cleared to “0” by the CLI instruction. This flag is set to “1” (interrupt disable state) automatically after the interrupt processing routine. To use a multi-interrupt, set this flag to “0” by using the CLI instruction in the interrupt processing routine.

22222 Interrupt setting

Set an interrupt according to the procedure shown below. 1The interrupt disable flag is set to “1.” 2The interrupt enable bit is cleared to “0.” 3For the INT interrupt or the CNTR interrupt, set the active edge in the Edge polarity selection register. Select one of the above interrupts in bit 4 of the Edge polarity selection register because the CNTR 0 interrupt and the CNTR1 interrupt can not be used simultaneously. ( 0: CNTR0, 1: CNTR 1 ) 4The request bit of interrupt used is cleared to “0.” (Refer to “Table 1.11.2.”) 5The enable bit of interrupt used is set to “1.” (Refer to “Table 1.11.2.”) 6The interrupt disable flag is cleared to “0.”

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.11.4 Notes on use

(1) When using P30 to P33 as input ports, put the corresponding INT interrupt or the CNTR interrupt into a disable state. (2) Set the interrupt request bit and the interrupt enable bit for preparations for an interrupt in the following order. 1 Clear the interrupt request bit to “0.” (No interrupt request) 2 Set the interrupt enable bit to “1.” (Interrupt enabled) When using the INT interrupt or the CNTR interrupt, first set the interrupt detection edge and then set the above items 1 and 2. (Refer to (4) that will be described later.) (3) An interrupt request bit can be cleared to “0” by software, but is still remained at the value precedent to a change immediately after execution of the clear instruction. For this reason, when executing the BBC or BBS instruction after changing an interrupt request bit, first execute the interrupt request bit change instruction and then execute the BBC or BBS instruction after one instruction or more. (4) When the detection edge of the INT interrupt or that of the CNTR interrupt is switched, the corresponding interrupt request bit may be set to “1.” Accordingly, perform setting referring to the register setting example shown in Figure 1.11.7. Fig. 1.11.7 Example of register setting (5) Whether an interrupt is caused by the BRK instruction or not can be judged by the contents of the break flag of the Processor status register pushed on the stack area. l Break flag = “1” : An interrupt has been caused by the BRK instruction l Break flag = “0” : In case of the other interrupts Note: Make this judgment in the interrupt processing routine. (6) When an INT interrupt request is generated by executing the STP/WIT instruction in one of the following states, the stop mode/wait mode is released. l When the active edge of the INT interrupt is a rising edge and the INT pin input level is “H” l When the active edge of the INT interrupt is a falling edge and the INT pin input level is “L” Accordingly, when executing the STP/WIT instruction, it is necessary to consider the input level of the INT pin and the polarity of the INT edge. Examples of countermeasures for it are shown below. 1. An example of a countermeasure for the case where the stop mode/wait mode is released at the rising edge of the INT pin input level Point: To release the stop mode/wait mode normally, perform mode release processing in the INT interrupt processing routine only when the STP/WIT instruction was executed at the “L” INT pin input level. Clear the corresponding interrupt enable bit to “0” Set the corresponding interrupt enable bit to “1” Clear the corresponding interrupt request bit to “0” Set the interrupt active edge Execute one or more instructions (NOP instruction, and so on)

7470/7471/7477/7478 GROUP USER’S MANUAL1-58 < Main routine > In the main routine, set the INT edge polarity according to the INT pin input level just precedent to execution of the STP/WIT instruction.

1 INT interrupt disable

2 l Select the falling edge when the INT pin input level is “H.” l Select the rising edge when the INT pin input level is “L.”

3 Clear the INT interrupt request bit to “0” and enable an INT interrupt after one instruction

or more. 4 Clear the interrupt disable flag to “0.”

5 Execute the STP/WIT instruction

< INT interrupt processing routine > In the INT interrupt processing routine, change the active edge of the INT interrupt without performing release processing and proceed to the stop mode/wait mode in the case where the stop mode/wait mode is released by detecting a falling edge. l When the INT pin input level is “H” (when a rising edge is detected) Processing for releasing the stop mode/wait mode l When the INT pin input level is “L” (when a falling edge is detected) [1] Select the rising edge [2] Clear the INT interrupt request bit to “0” [3] Pop from stack [4] Perform 4 and 5 processing of the main routine. 2. An example of a countermeasure for the case where the stop mode/wait mode is released at the rising edge of the INT 0 pin input level or the falling edge of the INT1 pin input level after the same signal is input to the INT0 pin and the INT1 pin. Point: Select the INT interrupt, by the main routine, that becomes a source of release of the stop mode/wait mode according to the INT pin input level just precedent to execution of the STP/WIT instruction. < Main routine >

1 INT

0 and INT1 interrupt disable 2 Select the rising edge for the active edge of the INT0 interrupt. Select the falling edge for the active edge of the INT1 interrupt. 3 l When the INT pin input level is “H” Clear the INT 1 interrupt request bit to “0” and enable the INT1 interrupt after one instruction or more. l When the INT pin input level is “L” Clear the INT 0 interrupt request bit to “0” and enable the INT0 interrupt after one instruction or more. 4 Clear the interrupt disable flag to “0.” 5 Execute the STP/WIT instruction. (7) In ordinary operation, if the pulse width of the INT input signal is 2 internal clocks f ( f(XIN)/2 ) or more by the built-in noise elimination circuit, it is accepted as an interrupt input. Input the INT input signal with a pulse width of 100 ns or more in the stop mode and the wait mode. Reference: As a hardware-level means to prevent incorrect interrupt processing due to noise, a noise elimination circuit is incorporated in the INT 0 and INT1 pins so that no interrupt can be generated by an “H” pulse (when the rising edge is selected) or an “L” pulse (when a falling edge is selected) of one machine cycle or less in modes other than the stop mode and the wait mode. As a software-level means, the levels of the INT 0 and INT1 pins are judged at the beginning of the interrupt processing routine.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.11.8 Structure of Edge polarity selection register

1.11.5 Related registers

(1) Edge polarity selection register (EG: Address 00D416) The Edge polarity selection register selects an active edge of each INT interrupt and each CNTR interrupt selects a source of interrupt. Figure 1.11.8 shows a structure of Edge polarity selection register. b7 b6 b5 b4 b3 b2 b1 b0 Name Function At reset Edge polarity selection register (EG) [Address Edge polarity selection register 3 0 4 0 INT0 edge selection bit INT1 edge selection bit CNTR 0 edge selection bit CNTR 1 edge selection bit CNTR 0/CNTR 1 interrupt selection bit INT1 source selection bit (at STP or WIT instruction execution) 0 : P31/INT1 1 : P00 to P07 “L” level input (for key-on wake-up) 6, 7 Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. 0 : Falling edge 1 : Rising edge 0 : CNTR 1 : CNTR1 WRB ?? 5 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 00D4 16]

7470/7471/7477/7478 GROUP USER’S MANUAL1-60 (2) Interrupt request register 1 (IR1: Address 00FC16) Interrupt request register 2 (IR2: Address 00FD16) The Interrupt request register 1 and the Interrupt request register 2 consist of bits that indicate whether an interrupt request exists or not. Figure 1.11.9 shows a structure of the Interrupt request register 1 and Figure 1.11.10 shows a structure of the Interrupt request register 2. Fig. 1.11.9 Structure of Interrupt request register 1 Fig. 1.11.10 Structure of Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IR1) [Address B Name Function At resetRW Interrupt request register 1 0 0 : No interrupt request 1 : Interrupt requested 0 ]Timer 1 interrupt request bit

1 Timer 2 interrupt

2 Timer 3 interrupt

3 Timer 4 interrupt

Serial I/O receive interrupt request bit (7477/7478 group)(Note) 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Note: ] :

7 A-D conversion completion

0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested Serial I/O transmit interrupt request bit (7477/7478 group) In the 7470/7471group, nothing is allocated for bit 5. This is write disabled bit and is undefined at reading. “0” is set by software, but not “1.” Serial I/O interrupt request bit (7470/7471group) 00FC 16] b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IR2) [Address B Name Function At resetRW Interrupt request register 2 0 0 : No interrupt request 1 : Interrupt requested 0 ]INT0 interrupt request bit

1 INT 1 interrupt request

2 CNTR 0 or CNTR1

] : 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 5Nothing is allocated for these bits. There are write disabled bits and are undefined at reading. “0” is set by software, but not “1.” 00FD 16]

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (3) Interrupt control register 1 (IE1: Address 00FE16) Interrupt control register 2 (IE2: Address 00FF16) The Interrupt control register 1 and the Interrupt control register 2 control the acceptance of interrupt by source. Figure 1.11.11 shows a structure of the Interrupt control register 1 and Figure 1.11.12 shows a structure of an Interrupt control register 2. Fig. 1.11.11 Structure of Interrupt control register 1 Fig. 1.11.12 Structure of Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (IE1) [Address B Name Function At resetRW Interrupt control register 1 0 0 : Interrupt disabled 1 : Interrupt enabled 0Timer 1 interrupt enable bit Note: Serial I/O receive interrupt enable bit (7477/7478 group) (Note) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 5Serial I/O interrupt enable bit (7470/7471 group) Serial I/O transmit interrupt enable bit (7477/7478 group) Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. In the 7470/7471 group, Nothing is allocated for bit 5. This is write disabled bit and undefined at reading. 00FE 16] b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (IE2) [Address B Name Function At resetRW Interrupt control register 2 0 0 : Interrupt disabled 1 : Interrupt enabled 0INT0 interrupt enable bit

1 INT 1 interrupt enable

0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 5Nothing is allocated for these bits. There are write disabled bits and are undefined at reading. 00FF 16]

7470/7471/7477/7478 GROUP USER’S MANUAL1-62 HARDWARE The 7470/7471/7477/7478 group has four 8-bit timers (Timer 1, Timer 2, Timer 3 and Timer 4) with an 8- bit timer latch. The division ratio of the timer is 1/(n+1) when the contents of the timer latch are n (n:0 to 255). For the timer, the following modes can be selected by software setting.

• Timer mode
• Event counter mode
• Pulse output mode
• External pulse width measurement mode
• PWM mode Table 1.12.1 Modes of each timer Mode Timer Timer 1 Timer 2 Timer 3 Timer 4 Timer mode Event counter mode Pulse output mode External pulse width measurement mode PWM mode

1-637470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.12.1 Timer block diagram T12M 7 Timer 2 interrupt request Timer 3 interrupt request Timer 4 interrupt request 1/2 1/8 CM 7 EG 2 T12M 3 T12M 6, P33/CNTR 1 EG 3 P13/T1 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 EG 0 EG 1 EG 2 EG 3 T34M 7 TM2 7 EG 4 T34M 6 T34M 3 TM2 1 C F/F T12M 0 T12M 2 T12M 1 TM2 0 T12M 4 T12M 5 TM2 6 T34M 1 T34M 2 T34M 0 T34M 4 T34M 5 XCIN XIN P32/CNTR 0 P12/T0 Port latch Port latch Timer 1 latch (8) Timer 1 (8) Data bus Timer 2 latch (8) Timer 2 (8) Timer 3 latch (8) Timer 3 (8) Timer 4 latch (8) Timer 4 (8) Timer 1 interrupt request Notes 1: The 7470/7477 group is not provided with the 2: The number (ex. EG3) described the right side of the register represents the bit number of the register. XCIN pin.

7470/7471/7477/7478 GROUP USER’S MANUAL1-64 HARDWARE

1.12.1 Operation description

In a write operation, the timer latch is specified at the same time when the timer is specified. If the timer is set to n 16, the timer latch is also set to n16 (n: 0016 to FF16). After the timer starts to count, 1 the timer value is counted down as n16 → ( n-1)16 → (n-2)16 → ... → 116 → 016 → FF 16 at each rise of the count source.

2 At the next rise of the count source after “FF16,”

l (n-1)16 resulting from decrementing 1 from the timer latch value is set (reloaded) in the timer and then the timer continues to count. l When an overflow occurs, the interrupt request bit is set to “1.” Note: When the interrupt is accepted, the interrupt request bit changes from “1” to “0.” It can be clearned to “0” but cannot be set to “1” by software. Figure 1.12.2 shows a timer count timing. Fig. 1.12.2 Timer count timing n16 (n–1)1655 16 n16 016 (n–2)16 (n–3)16 Count operation stop Count start Count stop bit Timer count source Value of timer Timer interrupt request bit ReloadWriting to timer Read value of timer (55 +1)16 FF16116 FF16 (n–1)16016116

1-657470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.12.2 Description of modes

(1) Timer mode The operations of the timer modes are as explained below.

1 Start of count operation

When the count stop bit is cleared to “0,” a count operation starts. When there is a count source input, the contents of the timer are decremented by 1. Note: Because the count stop bit is “0” immediately after reset release, the count operation is automatically started after reset release.

2 Reload operation

When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer.

3 Interrupt operation

When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer.

4 Stop of count operation

When the counter stop bit is set to “1” by software, the count operation stops. (The count operation continues until the count stop bit is set to “1.”) Figure 1.12.3 shows an example of timer mode operation.

7470/7471/7477/7478 GROUP USER’S MANUAL1-66 HARDWARE Fig. 1.12.3 Example of timer mode operation (n-1)16 FF16 RLRLRL OF T A : Timer 1 interrupt enable bit Timer 1 count source A A A A RL OF OF OF Count period Count period T(s) = 1 ‚ count source frequency 5 (the timer initial value + 1) Timer mode operation example

• OF: Overflow
• RL: Reload
• n: Timer initial value Timer 1 count stop bit Value of timer 1 Down count Timer 1 interrupt request bit “1” is written“0” is written Count stop Count restart Time
• Clearing by writing “0” to the timer interrupt request bit.
• Clearing by accepting the timer interrupt request when the timer interrupt enable bit is “1.”

1-677470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE [Setting method] 1 Set a value to be used according to the count source setting for timers. The count operation of the timer is stopped. Refer to “Table 1.12.2 Setting for count stop.” Table 1.12.2 Setting for count stop

2 Count source selecting

Select a count source according to the count source setting for timers shown in Table 1.12.3 to Table 1.12.6. Note that selectable count sources are different among timers. Because the 7470/7477 group is not provided with an X CIN pin, do not select f(XCIN ) as a count source. Table 1.12.3 Setting for timer 1 count source Note: When f(XCIN ) is selected as a timer count source, f(XIN) or f(XCIN) can be selected as a system clock. Setting item Timer Timer 1 Timer 2 Timer 3 Timer 4 Timer 12 mode register (T12M: Address 00F8 16) Timer 34 mode register (T34M: Address 00F916) CPU mode register (CM: Address 00FB 16) Timer 12 mode register (T12M: Address 00F8 16) Setting item Count source to be selected f(XIN)/16 f(XCIN ) f(XCIN )/16 External clock input from CNTR 0 pin. (Note) Setting item Count source to be selected f(XIN)/16 f(XIN)/64 f(XIN)/128 f(XIN)/256 f(XCIN )/16 f(XCIN )/64 f(XCIN )/128 f(XCIN )/256 Timer 1 overflow signal CPU mode register (CM: Address 00FB 16) Timer 12 mode register (T12M: Address 00F816) Table 1.12.4 Setting for timer 2 count source

7470/7471/7477/7478 GROUP USER’S MANUAL1-68 HARDWARE Table 1.12.5 Setting for Timer 3 count source Note: When f(XCIN ) is selected as a timer count source, f(XIN) or f(XCIN ) can be selected as a system clock. Table 1.12.6 Setting for Timer 4 count source Note: If the Timer 1 overflow signal is selected as a Timer 2 count source at [b5,b4] = [1,0], the Timer 4 count source becomes the Timer 1 overflow signal regardless of bit 6 of Timer mode register 2. Setting item Count source to be selected f(XIN)/16 f(XCIN ) f(XCIN )/16 Timer 1 overflow signal Timer 2 overflow signal External clock input from CNTR 1 pin CPU mode register (CM: Address 00FB 16) Timer mode register 2 (TM2: Address 00FA16) Timer 34 mode register (T34M: Address 00F916) (Note) Setting item Count source to be selected f(XIN)/16 f(XCIN )/16 Timer 1 overflow signal Timer 2 overflow signal Timer 3 overflow signal External clock input from CNTR 1 pin CPU mode register (CM: Address 00FB 16) Timer mode register 2 (TM2: Address 00FA16) Timer 34 mode register (T34M: Address 00F916) (Note) (Note) Setting item Timer Timer 1 Timer 2 Timer 3 Timer 4 Timer 12 mode register (T12M: Address 00F8 16) Timer 34 mode register (T34M: Address 00F916) Timer Timer 1(T1) Timer 2(T2) Timer 3(T3) Timer 4(T4) Table 1.12.7 Address allocation of timer 4 When a value is set according to the count start setting shown in Table 1.12.8, the timer starts to count. Table 1.12.8 Count start setting 3 Set a count value in the timer. Refer to “Table 1.12.7 Address allocation for timer.” Address 00F0 00F1 16 00F2 16 00F3 16

1-697470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (2) Event counter mode In the event counter mode, the same operations as those in the timer mode are performed, with the exception that the signal input from the CNTR0 pin becomes a count source of Timer 1 and the signal input from the CNTR1 pin becomes a count source of Timer 3 and Timer 4. The operation in the event counter mode are described below. After the count stop bit is cleared to “0,” a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. For the active edge of count source, a rise or a fall can be selected by the edge polarity selection register (address 00D4 16). Note: Because the count stop bit is “0” immediately after reset release, the count operation is automatically started after reset release but the count source is not a CNTR pin input (operates as the timer mode). When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer. When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer. 2CNTR interrupt An interrupt request is generated from the edge of the count source input from the CNTR 0 pin or the CNTR 1 pin, so that the interrupt request is set to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer. The edge polarity selection register selects an active edge of count source and a CNTR CNTR 1 interrupt. When the counter stop bit is set to “1” by software, the count operation stops. (The count operation continues until “1” is set in the count stop bit.) Figure 1.12.4 shows an example of event counter mode operation.

7470/7471/7477/7478 GROUP USER’S MANUAL1-70 HARDWARE T RL RL RL FF16 (n-1)16 A A A A A A A A A A A A B A A A to B Timer 1 interrupt enable bit Count source (CNTR 0 pin) Count period Count period T(s) = 1 ‚ count source frequency 5 (the timer initial value + 1) Event counter mode operation example

• OF: Overflow
• RL: Reload
• n: Timer initial value Timer 1 count stop bit Value of timer 1 Down count Timer 1 interrupt request bit “1” is written “0” is written Count stop Count restart A : • Clearing by writing “0” to the Timer 1 and CNTR interrupt request bits.
• Clearing by accepting the Timer 1 and CNTR interrupt requests when the timer 1 and CNTR interrupt enable bits are “1.” Time CNTR interrupt enable bit CNTR interrupt request bit CNTR edge selection bit In this example, the CNTR interrupt request occurs at rising edge of the count source. In this example, each CNTR interrupt request does not occur during executing the CNTR interrupt processing routine. Fig. 1.12.4 Example of event counter mode operation

1-717470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE [Setting method] 1 The count operation of a timer to be used is stopped. Refer to “Table 1.12.2 Setting for count stop.” 2 Select a count source according to the event counter mode setting shown in Table1.12.9. 3 Set a count value in the timer. Refer to “Table 1.12.7 Address allocation of timer.” 4 Start a count operation of timer to be used. Refer to “Table 1.12.8 Count start setting.” Table. 1.12.9 Event counter mode setting Note: 0: The falling edge (An input, when it is inverted, becomes a count source). 1: The rising edge (An input itself becomes a count source). Timer to be used Timer 1 Timer 3 Timer 4 Edge polarity selection register (EG: Address 00D416) Select (Note) Select (Note) Timer 12 mode register (T12M: Address 00F816) Timer 34 mode register (T34M: Address 00F916) Count source CNTR 0 CNTR 1 (3) Pulse output mode The pulse output mode is a mode resulting from adding a pulse output operation to a timer mode operation. In this mode, a pulse whose polarity is inverted at each overflow is output from the T0 (Timer 1 overflow signal/2) pin and the T1 (Timer 4 overflow signal/2) pin. The operations in the pulse output mode are described below. After the count stop bit is set to “0,” a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. Note: Because the count stop bit is “0” immediately after reset release, the count operation is automatically started immediately after reset release but no pulse is output. When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer.

3 Pulse is output

• A pulse whose polarity is inverted at each overflow is output from the T 0 pin and the T1 pin.
• “H” or “L” can be selected as a level for a start of pulse output by each division flip-flop.
• A pulse output is started from the moment when the T 0 or T1 pin output is selected by the Timer 12 mode register or the Timer 34 mode register.

4 Interrupt operation

2 Timer interrupt

When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set. The acceptance of interrupt is controlled by the interrupt enable bit of each timer.

5 Stop of count operation

When “1” is set in the counter stop bit by software, the count operation stops. (The count operation continues until “1” is set in the count stop bit.) Figure 1.12.5 shows a example of pulse output mode operation.

7470/7471/7477/7478 GROUP USER’S MANUAL1-72 HARDWARE Fig. 1.12.5 Example of pulse output mode operation (n-1)16 FF16 RL RLRLRL OF T AA A A OF OF OF Timer 1 interrupt enable bit Timer 1 count source Count period Count period T(s) = 1 ‚ count source frequency 5 (the timer initial value + 1) Pulse output mode operation example

• OF: Overflow
• RL: Reload
• n: Timer initial value Timer 1 count stop bit Value of timer 1 Down count Timer 1 interrupt request bit Writing “1”Writing “0” Count stop Count restart A : • Clearing by writing “0” to the Timer 1 interrupt request bit.
• Clearing by accepting the Timer 1 interrupt request when the Timer 1 interrupt enable bit is “1.” Time Timer FF register bit 0 T0 output selected T0 pin Initial value “0”Setting to output port

1-737470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE [Setting method] 1 The count operation of a timer to be used is stopped. Refer to “Table 1.12.2 Setting for count stop.”

2 Set the pulse output mode according to the pulse output mode initial value setting shown in Table

1.12.10. However, set the timer FF register after setting timer mode register 2. Table 1.12.10 Pulse output mode initial value setting Note: 0: The initial value becomes “0.” 1: The initial value becomes “1.” 3 Set the pulse output mode according to the pulse output mode setting shown in Table 1.12.11. The T 0 output port and the T1 output port are used in common with P12 and P13, respectively. Accordingly, set the bit 2 and bit 3 of the port P1 direction register to the output mode. Table 1.12.11 Pulse output mode setting 4 Set a count value in Timer 1 (T0 output) and Timer 4 (T1 output). 5 When a value is set according to the count start setting shown in Table 1.12.8, the timer starts to count. Note: When resetting a value in the Timer FF register, be sure to observe the setting methods of the above items 1 to 5. Setting item Timer to be used Timer 1 Timer 4 Timer mode register 2 (TM2: Address 00FA 16) Timer FF mode register (TF: Address 00F716) Select (Note) Select (Note) Timer Timer 1 Timer 4 Output pin Timer 1 overflow signal / 2 Timer 4 overflow signal / 2 Timer 12 mode register (T12M: Address 00F816) Timer 34 mode register (T34M: Address 00F9 16)

7470/7471/7477/7478 GROUP USER’S MANUAL1-74 HARDWARE (4) External pulse width measurement mode The external pulse width measurement mode is used to measure a pulse width (“H” or “L”) input from the CNTR 0 or CNTR 1 pin. The operations in the external pulse width measuring mode are described below. After the count stop bit is cleared to “0,” a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. Note: Because the count stop bit is “0” immediately after reset release, the count operation is automatically started after reset release but the count source is not a CNTR pin input. At this time, the external pulse width measurement mode is not provided. When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer.

3 External pulse width measurement mode

l The “H” or “L” level of a pulse can be selected as a pulse measuring period by the Edge polarity selection register. l The difference between the initial value of the timer and the counter value at a count stop becomes a measured pulse width. l A reload operation by reading the count value is not performed automatically. To perform measurement continuously, re-set the initial value by software. When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer. 2CNTR interrupt An interrupt request is generated from the edge of the pulse input from the CNTR 0 pin or the CNTR 1 pin, so that the interrupt request bit is set to “1.” Interrupt acceptance is controlled by the interrupt enable bit. The pulse active edge and the CNTR 0/CNTR 1 interrupt are selected by the Edge polarity selection register. The count operation terminates at the falling edge (at “H” level pulse width measurement) or the falling edge (“L” level pulse width measurement) of the CNTR pin input. This operation is also terminated by setting "1" in the count stop bit by software. Figure 1.12.6 shows an example of the operation of the external pulse width measurement mode.

1-757470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.12.6 Example of operation of external pulse width measurement mode Timer 4 count source Pulse width Pulse width H(s) = 1 ‚ count source frequency 5 (the timer initial value - count value at count stop) External pulse width measurement mode operation example

• n: Timer initial value
• m: Count value at count stop Timer 4 count stop bit CNTR 0 pin m 16 FF16 H (n-1)16 H A Timer 4 interrupt enable bit Value of timer 4 Timer 4 interrupt request bit Count start A : • Clearing by writing “0” to the CNTR interrupt request bit.
• Clearing by accepting the CNTR interrupt request when the CNTR interrupt enable bit is “1.” ] : When the CNTR edge selection bit is “0,” “H” level width of the input pulse is measured. CNTR edge selection bit Count start Count stop Time CNTR interrupt enable bit CNTR interrupt request bit Setting the initial value to timer Setting the initial value to timer

7470/7471/7477/7478 GROUP USER’S MANUAL1-76 HARDWARE [Setting method] 1 The count operation of Timer 4 is stopped by setting bit 3 of the Timer 34 mode register to “1.” Refer to “Table 1.12.2 Setting for count stop.”

2 Set each register according to the external pulse width measuring mode setting shown in Table

1.12.12. 3 Set a value in the timer. Refer to “Table 1.12.7 Address allocation of timer.” 4 Clear bit 3 of the Timer 34 mode register to "0" and start the count of timer 4. Refer to “Table 1.12.8 Count start setting.” Table 1.12.12 External pulse width measurement mode setting Notes 1: 0: The count source is counted while the external pulse is “H.” 1: The count source is counted while the external pulse is “L.” 2: When the measured pulse is the CNTR1 pin, do not select the CNTR1 as the count source of Timer 4. b5 b4 b4 Select (Note 1) Timer 34 mode register (T34M: Address 00F816) Edge polarity selection register (EG: Address 00D416)Timer to be used Timer 4 Measuring pulse CNTR0 CNTR1 b5 b4 0 0 : Timer 3 overflow signal 0 1 : f (X IN)/16 or f (XCIN )/16 10 : Timer 1 or Timer 2 overflow signal 1 1 : CNTR1 pin (Note 2) Select (Note 1)

1-777470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (5) PWM mode In the PWM mode, a PWM waveform is output from the T1 pin by using Timer 3 and Timer 4. The operations in the PWM mode are described below. After the count stop bit is cleared to “0,” a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. Note: The count stop bit is “0” immediately after reset release. Accordingly, a count operation is automatically started immediately after reset release but no PWM waveform is output because the PWM mode is not provided. When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer.

3 PWM output

In the PWM mode, the following operations are performed.

1 When the PWM mode is started

• The PWM waveform starts with “L.”
• Timer 3: Counts the count sources.
• Timer 4: Stops 2When Timer 3 overflows
• The PWM waveform goes to “H.”
• Timer 3: Stops.
• Timer 4: Counts the count sources.

3 When Timer 4 overflows

• The PWM waveform goes to “L.”
• Timer 3: Counts the count sources.
• Timer 4: Stops. The “L” width of the PWM waveform is set in Timer 3 and the “H” width is set in Timer 4.

When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer. When the counter stop bit is set to “1” by software, the count operation stops. (The count operation continues until the count stop bit is set to “1.”) Figure 1.12.7 shows an example of the operation of the PWM output mode.

7470/7471/7477/7478 GROUP USER’S MANUAL1-78 HARDWARE Fig.1.12.7 Example of operation of PWM output mode Timer 3 count source Count period Timer 3 count period T3(s) = 1 ‚ timer 3 count source frequency 5 (the timer 3 initial value + 1) Timer 4 count period T4(s) = 1 ‚ timer 4 count source frequency 5 (the timer 4 initial value + 1) PWM mode operation example

• OF: Overflow
• RL: Reload
• n: Timer 3 initial value
• m: Timer 4 initial value A : • Clearing by writing “0” to the Timer 3 and Timer 4 interrupt request bits.
• Clearing by accepting the interrupt request when the Timer 3 and Timer 4 interrupt enable bits are “1.” Timer 4 interrupt enable bit Timer 4 interrupt request bit Timer 3 interrupt enable bit Timer 3 interrupt request bit Timer 4 count stop bit Timer 4 count source Note: Timer 3 and Timer 4 do not accept count sources in the period from an overflow of the respective timer till an overflow of the other timer. Because the timer read value changes at the fall of a count source, the read value in this period remains “FF 16”. (m-1)16 FF16 T1 pin Time FF16 T3T3 OF OF AA A A A B C RL RLRL (n-1)16 OF OF OF B ' B " C ' B ' B "C ' RL RL (Note) (Note) (Note) (Note) To BTo BTo B “1” is written “0” is written Time Count stop Count restart To C To C PWM output mode selectedSetting to output port Value of timer 4 Value of timer 3

1-797470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE [Setting method] 1 The count operation of a timer to be used is stopped. Refer to “Table 1.12.2 Setting for count stop.”

2 Port P13 is put into the output mode by setting bit 3 of the port P1 direction register (address

00C1 16) to “1.” 3 Select a count source of Timer 3 and Timer 4. However, don't select the Timer 3 overflow signal as a count source of Timer 4. Refer to “Table 1.12.5 Setting for Timer 3 count source” and “Table 1.12.6 Setting for Timer 4 count source.” 4 Set the bit 7 of the Timer 34 mode register to “1.” 5 Set a value in the timer. Refer to “Table 1.12.7 Address allocation of timer.” 6 Set the bit 7 of the Timer mode register 2 to “1.” 7 The count operation of a timer to be used is started. Refer to “Table 1.12.8 Count start setting.” Note: When the PWM mode is started from another mode, the PWM waveform starts with the “L” state.

1.12.3 Input latch function

There is a function which latches the levels of the INT 0, INT1, CNTR 0 and CNTR 1 pins to the input latch register when Timer 4 overflows. Using this function permits knowing the level of each pin accurately the moment when a Timer 4 overflow occurs. The polarity of each pin is selected by the edge polarity selection register, the level or the reverse level of each pin are latched to the Input latch register. Table 1.12.13 shows the Edge polarity selection register setting related to the input latch. Table 1.12.13 Edge polarity selection register setting Latched contents INT0 pin level Reverse level on INT0 pin INT1 pin level Reverse level on INT1 pin CNTR 0 pin level Reverse level on CNTR0 pin CNTR 1 pin level Reverse level on CNTR1 pin Input latch register (ILR: Address 00D616) Edge polarity selection register (EG: Address 00D4 16)

7470/7471/7477/7478 GROUP USER’S MANUAL1-80 HARDWARE

1.12.4 Updating of contents of Timer and Timer latch

After data is written to the Timer, the contents of the Timer and the Timer latch are updated.

2 Timer 1 and Timer 2

When data is written to the Timer, this data is set in the Timer and the Timer latch at the same time. As a result, after data is written to the Timer which is in count operation, the count period becomes invalid. Figure 1.12.8 shows an example of updating of the contents of Timer 1, Time 2 and Timer latch. Fig. 1.12.8 Example of updating of Timer 1, Timer 2 and Timer latch (n-1)16 FF16 RL RLRL OF (m-1)16 A A A OF OF m 16

• OF: Overflow
• RL: Reload
• n: Timer 1 initial value before updating
• m: Timer 1 initial value after updating Value of timer 1 Writing “m16” to timer 1 Example of updating of Timer 1 Timer 1 interrupt request bit Timer 1 interrupt enable bit Time
• Clearing by writing “0” to the Timer 1 interrupt request bit.
• Clearing by accepting the Timer 1 interrupt request when the Timer 1 interrupt enable bit is “1.” A : Incorrect count period

1-817470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE After data is written to the Timer which is in count operation, the written data is set only in the Timer latch but not in the Timer. After that, when the Timer overflows, a value resulting from decrementing 1 from the value of the Timer latch is written in the Timer. When data is written to the Timer being at a stop, the written data is set in both Timer and Timer latch. l In modes other than the PWM mode The same operation as “Timer 1 and Timer 2” described in the previous item is performed. Figure 1.12.9 shows an example of updating of the contents of Timer 3, Time 4 and Timer latch in PWM mode. Fig. 1.12.9 Example of updating of Timer 3, Timer 4 and Timer latch in PWM mode A A A RL RL OF (n-1)16 FF16 (m-1)16 (k-1)16 FF16 RL OF OF m 16 (h-1)16 OF RL

• OF: Overflow
• RL: Reload
• n: Timer 3 initial value before updating
• m: Timer 3 initial value after updating
• k: Timer 4 initial value before updating
• h: Timer 4 initial value after updaiting Value of timer 3 Writing “m16” to timer 3 Example of updating of Timer at PWM mode interrupt request bit interrupt enable bit Time
• Clearing by writing “0” to the Timer 3 or Timer 4 interrupt request bit.
• Clearing by accepting the Timer 3 and the Timer 4 interrupt request when the Timer 3 and the Timer 4 interrupt enable bit is “1.” Value of timer 4 Count of timer 3 Count of timer 4 Time Writing “h16” to timer 4 A : Timer 3 Timer 4 Timer 3 Timer 4 Timer 3 interrupt Timer 4 interrupt Timer 3 interrupt Count of timer 3 by rewriting timer value Count of timer 4 by rewriting timer value

7470/7471/7477/7478 GROUP USER’S MANUAL1-82 HARDWARE Fig. 1.12.10 Relation between timer value change timing and read value change timing (3) To select the CNTR pin input as Timer count source, the frequency of the CNTR count source should satisfy the condition shown in Table 1.12.14.

1.12.5 Notes on use

(1) The contents of the Timer 12 mode register (T12M: Address 00F816) and the Timer 34 mode register (T34M: Address 00F916) become “0016” at reset and each timer performs a count operation. (2) Figure 1.12.10 shows the relation between Timer value change timing and read value change timing. The Timer value changes at the rise of the count source, while the read value changes at the fall of the count source. Accordingly, the read value may be larger than the real timer value by “1.” Main clock 4MHz 8MHz Upper boundary 1MHz 2MHz Lower boundary There is no special restriction. Frequency of the CNTR count source Table 1.12.14 Frequency of CNTR 0116 0016 FF16 9816 9716 0216 0116 0016 FF16 9816 9716Timer read value Timer count source Timer value Interrupt request bit Example: Writing “9916” into Timer 1

1-837470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.12.11 Structure of Timers 1 to 4

1.12.6 Related registers

(1) Timer 1, Timer 2, Timer 3, Timer 4 (T1 to T4: Address 00F016 to 00F316) Each Timer is a register consisting of 8 bits. Read The contents (count value) of the Timer are read by reading the timer. Write When data is written to the Timer, this data is set in the Timer and the Timer latch at the same time. When data is written into the Timer being in count operation in the PWM mode, the written data is set only in the Timer latch. Refer to “1.12.4 Updating of contents of Timer and Timer latch.” ] Timer latch The Timer latch is a register that holds a value to be automatically transferred (reloaded) to the Timer as its initial value when the Timer overflows. It is impossible to read the contents of the Timer latch. Figure 1.12.11 shows a structure of Timer. Note : b7 b6 b5 b4 b3 b2 b1 b0 Timer 1, Timer 2, Timer 3, Timer 4 (T1, T2, T3, T4) [Address 00F016, 00F116, 00F216, B Function At resetRW to

• Set “0016 to FF16.”
• The value is decremented by 1 each time a count source is input.
• Each Timer values are set to the respective counter.
• The count values are read out by reading the respective timer. (Note) Timers 1 to 4 Timers 1 and 2 are undefined. Timer 3 is “FF 16.” Timer 4 is “0716.” 00F316]

7470/7471/7477/7478 GROUP USER’S MANUAL1-84 HARDWARE (2) Timer 12 mode register (T12M: Address 00F816) The Timer 12 mode register is a register consisting of bits that control a Timer count source and a count operation. Figure 1.12.12 shows a structure of Timer 12 mode register. Fig. 1.12.12 Structure of Timer 12 mode register b7 b6 b5 b4 b3 b2 b1 b0 NameB Function Timer 12 mode register (T12M) [Address Timer 12 mode register 6, 7 b7 b6 Timer 1 count stop bit At resetR W Timer 1 count source selection bit Timer 1 internal clock source selection bit P12/T0 port output selection bit Timer 2 count stop bit Timer 2 count source selection bit Timer 2 internal clock source selection bits 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : P32/CNTR 0 external clock 0 : f(XIN)/16 or f(XCIN)/16 1 : f(XCIN) (Note 2) 0 : P12 port output 1 : T0(Timer 1 overflow divided by 2) 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : Timer 1 overflow signal 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XIN)/64 or f(XCIN)/64 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 : f(XIN)/256 or f(XCIN)/256 (Note 3) Notes 1: In the 7470/7477 group, the internal clock is f(X Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X 00F8 16] IN)/16. CIN) cannot be used. Fix this bit to “0.” CIN) cannot be used.

1-857470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (3) Timer 34 mode register (T34M: Address 00F916) The Timer 34 mode register is a register consisting of bits that control a timer count source and a count operation. Figure 1.12.13 shows a structure of Timer 34 mode register. Fig. 1.12.13 Structure of Timer 34 mode register b7 b6 b5 b4 b3 b2 b1 b0 NameB Function At resetR Timer 34 mode register (T34M) [Address Timer 34 mode register Timer 3 count stop bit W Timer 3 count source selection bits Timer 4 count stop bit Timer 4 count source selection bits Timer 4 pulse width measurement mode selection bit 0 : Count start 1 : Count stop 0 : Count start 1 : Count stop Notes 1: When Timer 1 overflow is selected as a Timer 2 count source, the Timer 4 count source is the Timer 1 overflow regardless of the value of bit 6 of the Timer mode register 2. Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X CIN) cannot be used. 1, 2 b2 b1 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XCIN) 1 0 : Timer 1 overflow or Timer 2 overflow 1 1 : P3 3/CNTR 1 external clock (Note 2) b4 b3 0 0 : Timer 3 overflow 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : Timer 1 overflow or Timer 2 overflow 1 1 : P3 3/CNTR 1 external clock (Notes 1, 2) 0 : Timer mode 1 : External pulse width measurement mode P13/T1 port output selection bit 0 : P13 port 1 : T1(Timer 4 overflow divided by 2 or PWM output) 4, 5 00F916]

7470/7471/7477/7478 GROUP USER’S MANUAL1-86 HARDWARE Fig. 1.12.14 Structure of Timer mode register 2 (4) Timer mode register 2 (TM2: Address 00FA16) The Timer mode register 2 consists of bits that control a mode selection and a count source selection. Figure 1.12.14 shows a structure of Timer mode register 2. (5) Timer FF register (TF: Address 00F716) The Timer FF register consists of bits that are used for initialization in the pulse output mode. Figure 1.12.15 shows a structure of Timer FF register. Fig. 1.12.15 Structure of Timer FF register b7 b6 b5 b4 b3 b2 b1 b0 NameB Function At resetR W Timer mode register 2 (TM2) [Address 6 0 7 0 Timer 1 overflow FF set enable bit to Timer mode register 2 Timer 4 overflow FF set enable bit Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. Timer 3, timer 4 count overflow signal selection bit Timer 3, timer 4 function selection bit 0 : Set disable 1 : Set enable 0 : Set disable 1 : Set enable 0 : Timer 1 overflow 1 : Timer 2 overflow 0 : Ordinary mode 1 : PWM mode ?? 5 00FA 16] b7 b6 b5 b4 b3 b2 b1 b0 NameB Function Timer 1 division flip-flop At resetR W Timer FF register (TF) [Address Timer FF register Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. to ? 5? Timer 4 division flip-flop 0 : Initial value is “0” 1 : Initial value is “1” 0 : Initial value is “0” 1 : Initial value is “1” 00F7 16]

1-877470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (6) Input latch register (ILR: Address 00D616) The Input latch register consists of bits that latch the levels of the INT0, INT1, CNTR 0 and CNTR 1 pins when the Timer 4 overflows. Figure 1.12.16 shows a structure of Input latch register. Fig. 1.12.16 Structure of Input latch register Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. b7 b6 b5 b4 b3 b2 b1 b0 Name Function At reset Input latch register (ILR) [Address P30/INT0 latch bit Input latch register WRB to P31/INT1 latch bit P32/CNTR 0 latch bit P33/CNTR 1 latch bit ? 5 ? 5 ? 5 ? 5? When b0 of EG (Note) is “0”: reverse level on INT0 pin When b0 of EG (Note) is “1”: level on INT0 pin When b1 of EG (Note) is “0”: reverse level on INT 1 pin When b2 of EG (Note) is “0”: reverse level on CNTR0 pin When b2 of EG (Note) is “1”: level on CNTR 0 pin When b3 of EG (Note) is “0”: reverse level on CNTR 1 pin When b3 of EG (Note) is “1”: level on CNTR 1 pin Note: EG is the Edge polarity selection register. 00D6 16] When b1 of EG (Note) is “1”: level on INT 1 pin

7470/7471/7477/7478 GROUP USER’S MANUAL1-88 HARDWARE (7) Edge polarity selection register (EG: Address 00D416) The Edge polarity selection register consists of bits that control a polarity selection of each of the INT0, INT1, CNTR 0 and CNTR 1 pins and an INT1 interrupt or key on wake-up interrupt selection at stop mode or wait mode. Figure 1.12.17 shows a structure of Edge polarity selection register. Fig. 1.12.17 Structure of Edge polarity selection register b7 b6 b5 b4 b3 b2 b1 b0 Name Function At reset Edge polarity selection register (EG) [Address Edge polarity selection register 3 0 4 0 INT0 edge selection bit INT1 edge selection bit CNTR 0 edge selection bit CNTR 1 edge selection bit CNTR 0/CNTR 1 interrupt selection bit INT1 source selection bit (at STP or WIT instruction execution) 0 : P31/INT1 1 : P00 to P07 “L” level input (for key-on wake-up) 6, 7 Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. 0 : Falling edge 1 : Rising edge 0 : CNTR 1 : CNTR1 WRB ?? 5 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 00D4 16]

1-897470/7471/7477/7478 GROUP USER’S MANUAL The 7470/7471/7477/7478 group can transmit or receive 8-bit data in series by Serial I/O. The Serial I/O transmit/receive method is shown below. l In the 7470/7471 group, only the clock synchronous is available. l In the 7477/7478 group, either clock synchronous or clock asynchronous (UART) can be selected. There are differences in circuit configuration and applicable registers between them. This section explains each of them as “1.13A 7470/7471 group part” and “1.13B 7477/7478 group part.” Table 1.13.1 shows defferences between 7470/7471 group and 7477/7478 group. Table 1.13.1 7470/7471 group vs. 7477/7478 group serial I/O ] 1 SRDY and SA RDY signal : Signal that indicates a Serial I/O transfer ready state ] 2 Byte specification mode : Mode for transmitting or receiving 1-byte data of a specific cycle out of multiple-byte data to be transmitted or received. S RDY signal output SA RDY signal output ] 1 Byte specification mode 7470/7471 group 7477/7478 group

1-90 7470/7471/7477/7478 GROUP USER’S MANUAL 1.13A 7470/7471 group part 1.13A.1 Operation description The 7470/7471 group incorporates a clock synchronous Serial I/O. The 8 shift clocks obtained by the clock control circuit are used as synchronous clocks for transmitting or receiving data. The transmit operation of the transmit side and the receive operation of the receive side are simultaneously executed in synchronization with these shift clocks. l The transmit side transmits data 1 bit by 1 bit from the P1 5/SOUT pin in synchronization with the fall of each shift clock. l The receive side receives data 1 bit by 1 bit from the P14/SIN pin in synchronization with the rise of each shift clock. Figure 1.13A.1 shows a Serial I/O block diagram. Fig. 1.13A.1 Serial I/O block diagram 1/2 1/4 CM 7 Counter XCIN XIN 1/2 1/4 1/64 SM 1 SM 0SM 2 Synchronous circuitSM 5 SA RDY SRDY SM 6 S R S IN S OUT S RDY Q CLK input CLK output Serial I/O counter (3) (Address 00DE16) Serial I/O interrupt request (Address 00DE16) Byte counter (4) Data bus (Address 00DD16) Serial I/O register (8) ]: The 7470 group is not provided with the X pin. CIN

1-917470/7471/7477/7478 GROUP USER’S MANUAL

22222 Communication format

The half-duplex data communication or the full-duplex data communication are available.

22222 Synchronous clock

The internal clock or the external clock can be selected as a synchronous clock by bit 2 of the Serial I/O mode register (SM: address 00DC 16). l The synchronous clock for the case where the internal clock is selected is shown below. Notes 1: In the 7470 group, f(XCIN ) is not available. 2: When selecting a divided signal of f(XCIN ), set the system clock to the low-speed mode by bit 7 of the CPU mode register. l When the external clock is selected, the synchronous clock is an external clock input from the P16/ CLK pin. Notes on external clock selection l When writing data into the Serial I/O register, perform a write operation while the synchronous clock is at “H.” l The shift operation of the Serial I/O register is continued while the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically.) l Set the “H” and “L” widths (T WH , TWL ) of the pulse used as the external clock source to TWH , TWL [s] > 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %).

22222 Shift clock

Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer selects the internal clock and outputs the 8 shift clock pulses generated by a start of transfer operation from the P1 6/CLK pin. The other microcomputer selects the external clock and uses the clock input from the CLK pin as a synchronous clock. 22222 S RDY signal, SARDY signal A Serial I/O transfer ready status can be known to the outside by outputting the SRDY signal and the SA RDY signal.

• f(XIN)/8
• f(XIN)/16
• f(XIN)/32
• f(XIN)/512
• f(XCIN )/8
• f(XCIN )/16
• f(XCIN )/32
• f(XCIN )/512 When the system clock is f(XIN) When the system clock is f(XCIN )

1-92 7470/7471/7477/7478 GROUP USER’S MANUAL

22222 Transmit operation of Serial I/O

The transmit operation of the Serial I/O is described below. l Start of transmit operation Transmit operation begins by writing transmit data into the Serial I/O register in the transmit enable state. At the time when this data has been written, “7” is set in the Serial I/O counter (address 00DE16, bit 4 – 6), so that the synchronous clock is forced to go to “H.” ] 1: State in which the register for transmit operation has been initialized. Refer to “[Transmit setting method]” which will be described later. ] 2: When the external clock is selected, perform a write operation while the synchronous clock is at “H.” l Transmit operation 1The transmit data written in the Serial I/O register is output from the P1 5/SOUT pin in synchronization with the fall of the synchronous clock. At this time, the Serial I/O counter is decremented by 1. 2Transmit data is output starting with the least significant bit of the Serial I/O register. Each time one bit is output, the contents of the Serial I/O register are shifted by 1 in the direction of the least significant bit. 3After the transmit shift operation is completed, an interrupt request occurs at the rise of the last cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set to “1.” ] 3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter overflows). When the external clock is selected, the contents of the Serial I/O register are continuously sifted while the synchronous clock is input. Accordingly, stop it externally. l When using the S RDY output At the time when transmit data has been written, the level of the S RDY signal changes from “H” to “L” and the level of the SA RDY signal changes from “L” to “H,” by which a receive ready state can be known externally. The S RDY signal goes to “H” at the first fall of the synchronous clock and the SA RDY signal goes to “L” at the rise of the last cycle of the synchronous clock.

1-937470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.13A.2 Serial I/O transmit operation Fig. 1.13A.3 Serial I/O transmit timing chart A Synchronous clock, internal clock divided by 8 to 512, or external clock SOUT pin SRDY signal SA RDY signal Write signal to serial I/O register Serial I/O interrupt enable bit Serial I/O interrupt request bit

• Clearing by writing “0” to the Serial I/O interrupt request bit.
• Clearing by accepting the Serial I/O interrupt. D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 P15/SOUT D 0D 1D 2D 3D 4D 5D 6D 7 D 7 D 7 D 4D 5D 6D 7 P15/SOUT D 2 D 3 Synchronous clock Serial I/O register Data bus Address 00DD16 Write transmit data Serial I/O register Synchronous clock Interrupt request register 1 (Address 00FC 16) by rising edge Synchronous clock Serial I/O register

1-94 7470/7471/7477/7478 GROUP USER’S MANUAL [Transmit setting method] 1Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to “0.” 2Set the Serial I/O mode register according to “Table 1.13A.1.” 3When using the Serial I/O interrupt, [1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to “0.” [2] Set the Serial I/O interrupt enable bit to “1.” 4Write transmit data into the Serial I/O register (address 00DD 16). Note: When the external clock is selected, perform a write operation while the synchronous clock is at “H.” Table 1.13A.1 shows a Serial I/O transmit setting. Table 1.13A.1 Serial I/O transmit setting Serial I/O mode register (SM: Address 00DC 16) Bit Setting value Serial I/O port using Serial I/O Byte specification mode selection P1 5/S OUT , SRDY pin output format (Note 3) External clock Internal clock Serial I/O port (S OUT , CLK) (Note 2) Ordinary port SRDY signal output SRDY signal SA RDY signal Ordinary mode Byte specification mode CMOS output N channel open drain output Item Register to be used Synchronous clock selection S RDY signal output selection S RDY signal selection Synchronous clock (at internal clock selection) (Note 1) Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group, however, f(XCIN ) is not available. l When a divided signal of f(XIN) is selected, the system clock is f(XIN). l When a divided signal of f(XCIN ) is selected, the system clock is f(XCIN ). Select a system clock state by bit 7 of the CPU mode register. 2: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit may be set to “1.” Clear the Serial I/O interrupt request bit to “0” after one instruction or more after switching the ordinary port over to the Serial I/O port. 3: When ordinary P1 7 is selected by bit 4 of the Serial I/O mode register, the CMOS output is provided regardless of the set value of bit 7. f(XIN)/8 f(XCIN )/8 f(XIN)/16 f(XCIN )/16 f(XIN)/32 f(XCIN )/32 f(XIN)/512 f(XCIN )/512 b1 • b0

1-957470/7471/7477/7478 GROUP USER’S MANUAL

22222 Receive operation of Serial I/O

The receive operation of the Serial I/O is described below. l Start of receive operation Receive operation begins by writing the following data into the Serial I/O register (SIO: address 00DD 16)] 2 in the receive enable state.] 1

• Transmit data in the full-duplex data communication
• Arbitrary dummy data in the half-duplex data communication At the time when this data has been written, “7” is set in the Serial I/O counter (address 00DE16, bit 4 – 6), so that the synchronous clock is forced to go to “H.” ] 1: State in which the register for receive operation has been initialized. Refer to “[Receive setting method]” which will be described later. ] 2: When the external clock is selected, perform a write operation while the synchronous clock is at “H.” l Receive operation 1Receive data is input from the P1 4/SIN pin to the Serial I/O register in synchronization with the rise of the synchronous clock. At this time, the Serial I/O counter is decremented by 1. 2Receive data is input starting into the most significant bit of the Serial I/O register. Each time one bit is input, the contents of the Serial I/O register are shifted by 1 in the direction of the least significant bit. 3After the receive shift operation is completed, an interrupt request occurs at the rise of the last cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set to “1”. ] 3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter overflows). When the external clock is selected, the contents of the Serial I/O register are continuously sifted while the synchronous clock is input. Accordingly, stop it externally. l When using the S RDY output At the time when data has been written into the Serial I/O register, the level of the S RDY signal changes from “H” to “L” and the level of the SARDY signal changes from “L” to “H,” by which a receive ready state can be known externally. The S RDY signal goes to “H” at the first fall of the synchronous clock and the SARDY signal goes to “L” at the rise of the last cycle of the synchronous clock.

1-96 7470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.13A.4 Serial I/O receive operation Fig. 1.13A.5 Serial I/O receive timing chart P14/SIN D 1D 2D 3 D 0 P14/SIN D 0 D 5 D 2D 6D 7 D 3D 4 D 0D 1 Synchronous clock Serial I/O register Serial I/O register Synchronous clock Synchronous clock Serial I/O register by rising edge Interrupt request register 1 (Address 00FC16) A Synchronous clock, internal clock divided by 8 to 512, or external clock SIN pin SRDY signal Writing data to Serial I/O register Serial I/O interrupt enable bit Serial I/O interrupt request bit A:• Clearing by writing “0” to the Serial I/O interrupt request bit.

• Clearing by accepting the Serial I/O interrupt. Reading into Serial I/O register SA RDY signal D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0

1-977470/7471/7477/7478 GROUP USER’S MANUAL [Receive setting method] 1Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to “0.” 2Clear the Port P14 direction register to “0” to set it to the input mode. 3Clear the Serial I/O mode register according to “Table 1.13A.2.” 4When using the Serial I/O interrupt, [1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to “0.” [2] Set the Serial I/O interrupt enable bit to “1.” 5Write the following data into the Serial I/O register.

• Transmit data in the full-duplex data communication
• Arbitrary dummy data in the half-duplex data communication Note: When the external clock is selected, write data into the Serial I/O register while the synchronous clock is at “H.” Table 1.13A.2 shows a Serial I/O receive setting. Table 1.13A.2 Serial I/O receive setting Serial I/O mode register (SM: Address 00DC 16) Bit Setting value External clock Internal clock Ordinary port (P1 5, P16) (Note 2) Serial I/O port (SOUT , CLK) (Note 3) Ordinary port S RDY signal output S RDY signal SA RDY signal Ordinary mode Byte specification mode CMOS output N channel open drain output Item Register to be used Synchronous clock selection P1 5/S OUT , S RDY pin output format (Note 4, Note 5) Serial I/O Byte specification mode selection Serial I/O port using S RDY signal output selection S RDY signal selection Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group, however, f(X CIN ) is not available. l When a divided signal of f(XIN) is selected, the system clock is f(XIN). l When a divided signal of f(XCIN ) is selected, the system clock is f(XCIN ). Select a system clock state by bit 7 of the CPU mode register. 2: When the external clock is selected, the P16/CLK pin becomes clock input pin CLK regardless of the set value of bit 3 of the Serial I/O mode register. For this reason, only P15 is available as an ordinary port. 3: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit may be set to “1.” Clear the Serial I/O interrupt request bit to “0” after one instruction or more after switching the ordinary port over to the Serial I/O port. 4: When ordinary P1 7 is selected by bit 4 of the Serial I/O mode register, the CMOS output is provided regardless of the set value of bit 7. 5: When S OUT is selected by bit 3 of the Serial I/O mode register, the data written in the Serial I/O register is output from the SOUT pin in synchronization with the fall of the synchronous clock. Synchronous clock (at internal clock selection) (Note 1) f(X IN)/8 f(XCIN )/8 f(XIN)/16 f(XCIN )/16 f(XIN)/32 f(XCIN )/32 f(XIN)/512 f(XCIN )/512 b1 • b0

1-98 7470/7471/7477/7478 GROUP USER’S MANUAL 1.13A.2 Byte specification mode The Serial I/O of the 7470/7471 group has the byte specification mode. This mode permits transmitting or receiving specific one-byte data out of multiple-byte data transmitted or received through the Serial I/O bus.

2 Byte counter (Address 00DE

16) The Byte counter is located at the same address as that of the Serial I/O counter but the Serial I/O counter is a read-only type. So this counter is not affected by any write operation to the Byte counter. Because the Byte counter is not provided with a reload function, re-set a value to transmit or receive data continuously. 2 SA RDY When the SA RDY signal is selected in the byte specification mode, the N channel open drain is selected as its output type, and the S RDY pins of multiple microcomputers are connected, the SARDY signal goes to “H” only when all the microcomputers have become ready for data transfer.

2 Operations in the byte specification mode

After setting the Serial I/O mode register, specify a byte corresponding to the clock to be used for a Serial I/O transmit/receive in the Byte counter. Where the value written in the Byte counter is n, a Serial I/O transmit/receive is performed by the clock of the (n + 1)-th byte. l Start of transmit/receive operation A transfer operation is started by writing the data (arbitrary dummy data in the half-duplex data communication) ] 1 to be transmitted to the Serial I/O register. ] 1: When the external clock is selected, write data into the Serial I/O register when the synchronous clock is at “H.” However, if the Byte counter value is a value other than “0,” writing data is enabled even if the synchronous clock is at “L.” l Transmit/receive operation Each time the synchronous clock is input in 8 cycles, the Byte counter value is decremented by 1. 2With the synchronous clock of the next 8 cycles after the Byte counter value becomes “0,” a Serial I/O transmit/receive is performed as in the ordinary mode. After completion of the 8-bit data output, an interrupt occurs at the rise of the last cycle of the synchronous clock, so that bit 6 of the Interrupt request register (address 00FC 16) is set to “1.” 3When the Byte counter overflows, the Serial I/O transfer stops. ] 2: When the Byte counter value is a value other than 0, the output of the SOUT pin goes to “H” at the fall of the first synchronous clock. If the N channel open drain is selected as the output type of the S OUT pin, the output is put into a high-impedance state, so the SOUT pin can be connected to the SOUT pin of another microcomputer.

1-997470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.13A.6 Transmit/receive operation in byte specification mode Figure 1.13A.6 shows a transmit/receive operation in the byte specification mode. P15/SOUT D 0D 1D 2D 3D 4D 5D 6D 7 D 7 D 7 P14/SIN D 0 D5 D 2D 6D7 D3D4 D0D 1 FF16 Byte counter Synchronous clock When transmit When receive Synchronous clock Serial I/O register Serial I/O register Synchronous clock Synchronous clock8 cycles Interrupt request register 1 (Address 00FC16) by rising edge Byte counter n16 (n-1)16

1-100 7470/7471/7477/7478 GROUP USER’S MANUAL [Byte specification mode setting] For a Serial I/O transfer in the byte specification mode, refer to the setting method in the ordinary mode in “1.13A.1 Operation description,” and also take the following into consideration. l Select the byte specification mode. (Set bit 6 of the Serial I/O register to “1.”) l Be sure to select the external clock as the synchronous clock. (Clear bit 2 of the Serial I/O mode register to “0.”) [1] When data is received, the ordinary port can be selected by the Serial I/O port selection bit (bit 3 of the Serial I/O mode register). P1 6 pin is used as a external clock input pin CLK. Only P1 5 is available as an ordinary port. [2] Write data into the Serial I/O register when the synchronous clock is at “H.” However, if the Byte counter value is a value other than “0,” writing data is enabled even if the synchronous clock is at “L.” l When performing a Serial I/O transmit/receive at the n–th byte, write (n – 1) in the Byte counter. Note: Because the Byte counter is not provided with a reload function, re-set a value to transmit or receive data continuously.

1-1017470/7471/7477/7478 GROUP USER’S MANUAL 1.13A.3 Pins The 7470/7471 group uses 4 pins for data transmit, data receive, shift clock transmit/receive and receive ready signal output. All these pins are used in common with P1. A function selection is made by the Serial I/O port selection bit (bit 3) and the SRDY signal output selection bit (bit 4) of the Serial I/O mode register (SM : Address 00DC 16). The function of each pin is explained below. (1) Data transmit pin [SOUT ] Transmit data is output bit by bit. This pin is used in common with P15. When the Serial I/O port selection bit (bit 3) of the Serial I/O mode register is set to “1,” this pin becomes a Serial I/O data output pin. (2) Data receive pin [S IN] Data is input bit by bit. This pin is used in common with P14. When the port P14 direction register is put into the input mode, this pin becomes a Serial I/O data input pin. (3) Shift clock transmit/receive pin [CLK] This pin inputs (receives from the outside) or outputs (supplies to the outside) the shift clock for data transmit/receive. This pin is used in common with P1 The internal clock or the external clock can be selected by bit 2 of the Serial I/O mode register. (4) Receive enable signal output pins [SRDY ], [SARDY ] This pin informs the outside of a receive ready state. This pin is used in common with P17. l SRDY signal S RDY signal output selection bit (bit 4) of Serial I/O mode register is set to “1.” S RDY signal selection bit (bit 5) of Serial I/O mode register is cleared to “0.” When the above 2 conditions are satisfied, the level of the pin changes from “H” to “L” at the timing at which data is written into the Serial I/O register, informing the outside of a receive ready state. l SA RDY signal S RDY signal output selection bit (bit 4) of Serial I/O mode register is set to “1.” S RDY signal selection bit (bit 5) of Serial I/O mode register is set to “1.” When the above 2 conditions are satisfied, the level of the pin changes from “L” to “H” at the timing at which data is written into the Serial I/O register, informing the outside of a receive ready state. 1.13A.4 Notes on use When the external clock is selected, take the following points into consideration. 1When writing data into the Serial I/O register, perform a write operation while the synchronous clock is at “H.” 2The shift operation of the Serial I/O register is continued while the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically at the end of 8 cycles.) 3Set the “H” and “L” widths (T WH , TWL ) of the pulse used as the external clock source to TWH , TWL [s] > 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %).

1-102 7470/7471/7477/7478 GROUP USER’S MANUAL 1.13A.5 Related registers (1) Serial I/O register (SIO: Address 00DD16) The Serial I/O register is written Serial I/O transmit data or is read receive data. l When transmitting data, write transmit data into this register. l Receive data can be obtained by reading this register. Figure 1.13A.7 shows a structure of the Serial I/O register. Fig. 1.13A.7 Structure of Serial I/O register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O register (SIO) [Address B Function At resetR W Serial I/O register (7470/7471 group) to A value of “0016” to “FF16” can be set as transmit data. At the transmit, data is transmitted one bit at a time starting with the least significant bit. At the receive, data is received one bit at a time starting with the most significant bit. At transmit: At receive: 00DD 16]

1-1037470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.13A.8 Structure of Serial I/O counter and Byte counter (2) Serial I/O counter, Byte counter (Address 00DE16) The Serial I/O counter and the Byte counter are located at the same address. l Serial I/O counter (bit 4 – bit 6) The Serial I/O counter is set to “7” by writing transmit data into the Serial I/O register and counts the synchronous clock of the Serial I/O eight times. The Serial I/O counter is a read-only type and not affected by any write operation to the Byte counter. l Byte counter (bit 0 – bit 3) In the Serial I/O byte specification mode, the value written in the Byte counter is counted down at 8 cycles of the synchronous clock. When the value becomes “0,” a Serial I/O transmit/receive is performed by the synchronous clock of the next 8 cycles. Because a reload function is not available, re-set a value to transfer data continuously in the byte specification mode. Figure 1.13A.8 shows a structure of the Serial I/O counter and the Byte counter. b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O counter and Byte counter [Address B Function At resetRW Serial I/O counter and Byte counter (7470/7471 group) to Byte counter to 6 5? ?? 5 When using the byte specification mode, set a value of “0016” to “0F16.” Supposing that the value to be written into the byte counter is “n,” a Serial transmit/receive is performed with the clock of the “n + 1”-th byte. Serial I/O counter When the internal clock is selected as a synchronous clock, this counter generates 8 shift clocks. When transmit data is written into the Serial I/O register, “07 16” is set in the Serial I/O counter. Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. 00DE 16]

1-104 7470/7471/7477/7478 GROUP USER’S MANUAL (3) Serial I/O mode register (SM: Address 00DC16) The Serial I/O mode register selects a state of the clock or port to be used for a data transfer. Figure 1.13A.9 shows a structure of the Serial I/O mode register. Fig. 1.13A.9 Structure of Serial I/O mode register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O mode register (SM) [Address B At resetRW Serial I/O mode register (7470/7471 group) 0, 1 Name Function 0 0 : f(XIN)/8 or f(XCIN)/8 b1 b0Internal clock selection bits Synchronous clock selection bit Serial I/O port selection bit SRDY signal output selection bit SRDY signal selection bit Serial I/O byte specify mode selection bit P15/SOUT , SRDY output structure selection bit 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : f(XIN)/32 or f(XCIN)/32 1 1 : f(XIN)/512 or f(XCIN)/512 (Note) 0 : External clock 1 : Internal clock 0 : Ordinary I/O port (P15, P16) 1 : Serial I/O port (SOUT , CLK pin) 0 : Ordinary I/O port(P17) 1 : SRDY signal output pin 0 : SRDY signal 1 : SARDY signal 0 : Ordinary mode 1 : Byte specify mode 0 : CMOS output 1 : N-channel open-drain output Since the 7470 group is not provided with the sub-clock generating circuit, do not select f(X Note: 00DC 16] CIN).

1-1057470/7471/7477/7478 GROUP USER’S MANUAL 1.13B 7477/7478 group part 1.13B.1 Operation description The 7477/7478 group incorporates a Serial I/O that permits selecting one of the clock synchronous and the clock asynchronous. This section describes the operation in each of the clock synchronous serial I/ O and the clock asynchronous Serial I/O (UART). (1) Clock synchronous Serial I/O In the clock synchronous Serial I/O, the 8 shift clocks obtained by the clock control circuit are used as synchronous clocks for transmitting or receiving. The transmit operation of the transmit side and the receive operation of the receive side are simultaneously executed in synchronization with these shift clocks. l The transmit side transmits data bit by bit from the P1 5/TxD pin in synchronization with the fall of each shift clock. l The receive side receives data bit by bit from the P14/RxD pin in synchronization with the rise of each shift clock. Figure 1.13B.1 shows a clock synchronous Serial I/O block diagram. Fig. 1.13B.1 Clock synchronous Serial I/O block diagram F/F 1/4 1/4 P16 P14 P15P17 TXD SRDY SCLK R XD XIN Data bus Receive enable bit (RE) Serial I/O enable bit (SIOE) Address 00E016 Receive buffer register Receive shift register Shift clock Serial I/O control registerAddress 00E216 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit Serial I/O synchronous clock selection bit (SCS) Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 00E116 Data bus Address 00E016 Address 00E416 Transmit buffer register Transmit shift register Shift clock Transmit interrupt source selection bit (TIC) Dividing ratio 1/(n+1) Baud rate generator S RDY output enable bit (SRDY) BRG count source selection bit (CSS) Transmit enable bit (TE) Falling detected ] : The 7477 group is not provided with the X pin. XCIN CIN

1-106 7470/7471/7477/7478 GROUP USER’S MANUAL The half-duplex data communication or the full-duplex data communication are available for communication. The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register (SIOCON: address 00E2 16). l “0” : Baud rate generator (BRG) output divided by 4 l “1” : External clock input from the SCLK pin The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 (at “0”), f(XIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register. In the 7478 Group, f(XCIN )/4 (at “0”), f(XCIN )/16 (at “1”) can be also selected. Notes on external clock selection l When setting the transmit enable bit to “1” or writing data into the Transmit buffer register, perform a write operation while the synchronous clock is at “H.” l The shift operation of the Transmit shift register or the Receive shift register is continued while the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically at the end of 8 cycles.) l Set the “H” and “L” widths (T WH , TWL ) of the pulse used as the external clock source to TWH , TWL [s] > 8/(system clock [Hz]). For example, when a system clock is 8 MHz, use a clock of 500 kHz or less (duty ratio 50 %). Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer selects the internal clock and outputs the 8 shift clock pulses generated by a start of transmit operation from the P1 6/SCLK pin. The other microcomputer selects the external clock and uses the clock input from the P16/SCLK pin as a synchronous clock.

22222 Data transfer rate (baud rate)

In the clock synchronous Serial I/O, the expression for calculating a data transfer rate (baud rate), which is the frequency of the synchronous clock is shown below. l When the internal clock is selected (using the BRG) Baud rate [bps] = ] 1 Division ratio : Select “4” or “16” by the BRG count source selection bit. ] 2 BRG set value : 0 – 255 (0016 – FF16) ] 3 In the 7478 Group, f(XCIN ) can be also used. l When the external clock is selected Baud rate [bps] = Input clock frequency to SCLK pin The BRG is an 8-bit counter dedicated to the Serial I/O, having a reload register, and divides the count source by (n + 1) by setting the value n. As a count source, f(X IN)/4 (at “0”), f(XIN)/16 or (at “1”) can be selected by bit 0 of the Serial I/O control register. In the 7478 Group, f(X CIN )/4 (at “0”), f(XCIN )/16 (at “1”) can be also selected. f(XIN) ] 3 Division ratio ] 1 5 (BRG set value + 1) 5 4

1-1077470/7471/7477/7478 GROUP USER’S MANUAL

22222 SRDY signal

The clock synchronous Serial I/O can inform the outside that a serial transfer has become ready, by outputting the S RDY signal.

22222 Transmit operation of the clock synchronous Serial I/O

The transmit operation of the clock synchronous Serial I/O is described below. l Start of transmit operation Transmit data is transmitted by writing it into the Transmit buffer register (TB: address 00E0 16) ] 2 in the transmit enable state. ] 1 When the internal clock is selected as a synchronous clock, 8 shift clocks are generated at the time when this set value has been written. l Transmit operation 1After transmit data is written into the Transmit buffer register, ]2 the transmit buffer empty flag (bit 0) of the Serial I/O status register is cleared to “0.” 2The transmit data written in the Transmit buffer register is transferred to the Transmit shift register. ] 3 3When the data transfer from the Transmit buffer register to the Transmit shift register is completed, the transmit buffer empty flag is set to “1.” 4The transmit data transferred to the Transmit shift register is output from the P15/TxD pin in synchronization with the fall of the synchronous clock. 5When a transmit shift operation is started, the transmit shift completion flag (b2) of the Serial I/O status register is cleared to “0.” ] 5 6Data is output starting with the least significant bit of the Transmit shift register. Each time one- bit data is output, the contents of the Transmit shift register are shifted by 1 bit in the direction of the least significant bit. 7At the time when the transmit shift operation has been completed, the Transmit shift register shift completion flag is set to “1.” ] 3 ]5 ] 1: Status in which the register for transmit operation has been completed. Refer to “[Clock synchronous Serial I/O setting method]” which will be described later. ] 2: When the external clock is selected, write data into the Transmit buffer register when the synchronous clock is at “H.” ] 3: A transmit interrupt request occurs immediately after the transfer of 2 when the transmit interrupt source bit (bit 3) of the Serial I/O control register (SIOCON) is “0,” or at the time of 7 when the said bit is “1.” ] 4: While the transmit buffer empty flag is “1,” the next transmit data can be written into the Transmit buffer register. ] 5: When the internal clock is used as a synchronous clock, the shift clock supply to the Transmit shift register is automatically stopped after 8-bit data is transmitted. However, if the next transmit data is written to the Transmit buffer register while the Transmit shift register shift completion flag is “0,” the shift clock supply is continued and serial data is continuously output from the TxD pin.

1-108 7470/7471/7477/7478 GROUP USER’S MANUAL l When using the S RDY output At the time when data has been written into the Transmit buffer register, the S RDY pin changes from “H” to “L,” informing the outside of a receive ready state. The S RDY pin is restored to “H” at the first fall of the synchronous clock. l Transmit interrupt operation (valid when the Serial I/O is selected) Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the Serial I/O control register (SIOCON). 0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer register is transferred to the Transmit shift register, an interrupt request is generated. 1: When the shift operation of the Transmit shift register is completed, an interrupt request is generated. Figure 1.13B.2 shows a transmit operation of clock synchronous Serial I/O and Figure 1.13B.3 shows a transmit timing chart of clock synchronous Serial I/O. Fig. 1.13B.2 Transmit operation of clock synchronous Serial I/O P15/TxD D 7 P15/TxD D 0D 1D 2D 3D 4D 5D 6D 7 P15/TxD D 1D 2D 3D 4D 5D 6D 7 Data bus Address 00E016 Transmit data writing Transmit buffer register Serial I/O status register (Address 00E116) Transmit buffer register Transmit data transfer Transmit shift register Serial I/O status register (Address 00E1 16) Interrupt request register 1 (Address 00FC 16) Transmit shift register Synchronous clock When “0” is selected by the bit 3 of the Serial I/O control register Interrupt request register 1 (Address 00FC16) When “1” is selected by the bit 3 of the Serial I/O control register Serial I/O status register (Address 00E116) Transmit shift register Synchronous clock Transmit shift register Synchronous clock Serial I/O status register (Address 00E1 16)

1-1097470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.13B.3 Transmit timing chart of clock synchronous Serial I/O D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7TXD pin SRDY pin Synchronous clock, BRG divided by 4, or external clock Write signal to transmit buffer register : • Clearing by writing “0” to the transmit interrupt request bit.

• Clearing by accepting the transmit interrupt. Transmit buffer empty flag Transmit shift completion flag Transmit interrupt enable bit Transmit interrupt request bit : When interrupt request generation is selected, when the Transmit buffer register becomes empty by clearing the transmit interrupt source selection bit to “0”. : When interrupt request generation is selected, when the shift operation of the transmit shift register is completed by setting the transmit interrupt source selection bit to “1”. A1 A2 B1 A1 B2 A2 B2B1

1-110 7470/7471/7477/7478 GROUP USER’S MANUAL [Clock synchronous Serial I/O transmit setting method] 1Clear the Serial I/O transmit interrupt enable bit (bit 6 of Interrupt control register 1) to “0.” 2When selecting the internal clock, set the BRG value. 3Set the Serial I/O control register according to Table 1.13B.1. 4When using a Serial I/O transmit interrupt [1] Clear the Serial I/O transmit interrupt request bit (bit 6 of Interrupt request register 1) to “0.” Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O transmit interrupt request bit may be set to “1.” Clear the Serial I/O transmit interrupt request bit to “0” after one instruction or more after switching the ordinary port over to the Serial I/ O port. [2] Set the Serial I/O transmit interrupt enable bit to “1.” 5Write transmit data into the Transmit buffer register (TB: address 00E0 16). Note:When the external clock is selected, perform a write operation while the synchronous clock is at “H.” Table 1.13B.1 Clock synchronous Serial I/O transmit setting Item Serial I/O control register (SIOCON: Address 00E216) Bit Setting value Register to be used 1(Note 2) BRG count source selection (Note 1) Synchronous clock selection S RDY signal output selection Transmit interrupt request selection f(XIN)/4 f(XIN)/16 BRG output divided by 4 External clock input Ordinary port S RDY signal output Transmit buffer empty When the transmit shift operation is completed Transmit enable Disable (half-duplex data communication) Enable (full-duplex data communication) Clock synchronous 4 to P17 function as serial I/O pinsSerial I/O enable selection Clock synchronous selection Receive enable selection Transmit enable selection Notes 1 :f(XCIN )/4 (setting value : 0), f(XCIN )/16 (setting value : 1) can be selected in the 7478 Group. 2: When the external clock is selected, write “1” in bit 4 (transmit enable bit) while the synchronous clock is at “H.”

1-1117470/7471/7477/7478 GROUP USER’S MANUAL

22222 Receive operation of clock synchronous Serial I/O

The receive operation of the clock synchronous Serial I/O is described below. l Start of receive operation Receive operation begins by writing data into the Transmit buffer register (TB: address 00E0 16) ] 2 in the receive enable state. ] 1

• Transmit data in the full-duplex data communication
• Arbitrary dummy data in the half-duplex data communication l Receive operation 1Receive data is input bit by bit from the P1 4/RxD pin to the Receive shift register in synchronization with the rise of the synchronous clock. 2Receive data is input starting with the most significant bit of the Receive shift register. Each time one bit is input, the contents of the Receive shift register are shifted by 1 in the direction of the least significant bit. 3After one-byte data is completely input to the Receive shift register, the contents of the Receive shift register are transferred to the receive buffer register (RB). 4When receive data has been transferred to the receive buffer register, the receive buffer full flag (b1) of the Serial I/O status register (SIOSTS) is set to “1,” ] 4 so that a receive interrupt request is generated. ] 1: Status in which the register for receive operation has been completed. Refer to “[Clock synchronous Serial I/O receive setting method]” which will be described later. ] 2: When the external clock is selected, write data into the Transmit buffer register when the synchronous clock is at “H.” ] 3: If receive data is further input to the Receive shift register when data remains (when the receive buffer full flag is “1”) without reading out the contents of the Receive buffer register, the overrun error flag of the Serial I/O status register is set to “1.” At this time, the data of the Receive shift register is not transferred to the Receive buffer register and the original data of the Receive buffer register is held. ] 4: The receive buffer full flag is cleared to “0” by reading out the Receive buffer register. l When using the S RDY output At the time when data has been written into the Transmit buffer register, the level of the S RDY signal changes from “H” to “L” by which a receive ready state can be known externally. The S RDY signal goes to “H” at the first fall of the synchronous clock of the synchronous clock. l Receive interrupt operation (Serial I/O select only) When receive data is transferred from the receive shift register to the Receive buffer register after one-byte data is all input to the Receive shift register, an interrupt request is generated. Figure 1.13B.4 shows a receive operation of the clock synchronous Serial I/O and Figure 1.13B.5 shows a receive timing chart of the clock synchronous Serial I/O.

1-112 7470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.13B.5 Receive timing chart of clock synchronous serial I/O Fig. 1.13B.4 Receive operation of clock synchronous serial I/O P14/RxD D 1D 2D 3 D 0 P14/RxD D 5 D 2D 6D 7 D 3D 4 D 0D 1 D 0 Synchronous clock Receive shift register Synchronous clock Receive shift register Synchronous clock Receive buffer register Receive shift register Receive data transfer (Address 00E016) Serial I/O status register (Address 00E116) Interrupt request register 1 (Address 00FC16) D 0 D 1 D 2 D 3 D 4 D 5 D 6 A D 7 Synchronous clock RxD pin Reading into receive shift register Writing data to transmit shift register SRDY pin Receive buffer register read signal Receive buffer full flag Receive enable bit Receive interrupt request bit

• Clearing by writing “0” to the receive interrupt request bit.
• Clearing by accepting the receive interrupt.

1-1137470/7471/7477/7478 GROUP USER’S MANUAL [Clock synchronous Serial I/O receive setting method] 1Clear the Serial I/O receive interrupt enable bit (bit 5 of interrupt control register 1) to “0.” 2When selecting the internal clock, set the BRG value. 3Set the Serial I/O control register according to Table 1.13B.2. 4When using a Serial I/O receive interrupt [1] Clear the Serial I/O receive interrupt request bit (bit 5 of interrupt request register 1) to “0.” Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O receive interrupt request bit may be set. Clear the Serial I/O receive interrupt request bit to “0” after one instruction or more after switching the ordinary port over to the Serial I/O port. [2] Set the Serial I/O receive interrupt enable bit to “1.” 5Set the following data into the Transmit buffer register (TB).

• Transmit data in the full-duplex data communication
• Arbitrary dummy data in the half-duplex data communication Note: When the external clock is selected, perform a write operation while the synchronous clock is at “H.” Table 1.13B.2 Clock synchronous Serial I/O receive setting Item Serial I/O control register (SIOCON: Address 00E216) Bit Setting value Register to be used Receive enable selection Clock synchronous selection Serial I/O enable selection f(X IN)/4 f(XIN)/16 BRG output divided by 4 External clock input Ordinary port SRDY signal output (Note 2) Disable (half-duplex data communication) Enable (full-duplex data communication) Receive enable Clock synchronous 4 to P17 function as Serial I/O pins Notes 1: f(XCIN )/4 (setting value : 0), f(XCIN)/16 (setting value : 1) can be selected in the 7478 Group. When the receive side performs an SRDY output by using an external clock, set the receive enable bit, the S RDY output enable bit, and the transmit enable bit to “1” (transmit enable). 3: When the external clock is selected, write “1” in bit 4 (transmit enable bit) while the synchronous clock is at “H.” 1(Note 3) BRG count source selection (Note 1) Synchronous clock selection S RDY signal output selection Transmit enable selection

1-114 7470/7471/7477/7478 GROUP USER’S MANUAL (2) Clock asynchronous Serial I/O In case of the clock asynchronous Serial I/O (UART), the transmit operation of the transmit side and the receive operation of the receive side are simultaneously executed by unifying the baud rate and the transfer data format between both transmit side and receive side. Figure 1.13B.6 shows a UART block diagram. Fig. 1.13B.6 UART block diagram P14 P15P16 TXD SCLK R XD 1/16ST/SP/PA occur OE PE FE Receive enable bit (RE) Serial I/O enable bit(SIOE) Address 00E016 Receive buffer register Receive shift register Serial I/O control register Address 00E216 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit Serial I/O synchronous clock selection bit (SCS) Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 00E116 Data bus Address 00E016 Address 00E416 Transmit buffer register Transmit shift register Transmit interrupt source selection bit (TIC) Dividing ratio 1/(n+1) Baud rate generator BRG count source selection bit (CSS) Transmit enable bit (TE) Data bus Character length selection bit (CHAS) ST detected 7 bits 8 bits SP detected Character length selection bit (CHAS) UART control register Address 00E316 XCIN ] : The 7477 group is not provided with the X pin. XIN CIN

1-1157470/7471/7477/7478 GROUP USER’S MANUAL Input clock oscillation frequency to SCLK pin

2 Synchronous clock

The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register (SIOCON: address 00E2 16). l “0” : Baud rate generator (BRG) output divided by 16 l “1” : External clock input from the SCLK pin divided by 16 The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 (at “0”), f(XIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register. In the 7478 Group, f(XCIN )/4 (at “0”), f(XCIN )/16 (at “1”), can be also selected. Precaution on internal clock selection In the UART, when the internal clock is selected as a synchronous clock, the P1 6/SCLK pin can be used as port P16. Notes on external clock selection l Set the “H” and “L” widths (T WH , TWL ) of the pulse used as the external clock source to TWH , TWL [s] > 2/(f(XIN) [Hz]). For example, when f(XIN) = 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %).

2 Data transfer speed (Baud rate)

In the UART, the expression for calculating a data transfer speed (baud rate), which is the frequency of the synchronous clock is shown below. l When the internal clock is selected (using the BRG) Baud rate [bps] = ] 1 Division ratio : Select “4” or “16” by the BRG count source selection bit. ] 2 BRG set value : 0 – 255 (0016 – FF16) ] 3 In the 7478 Group, f(XCIN ) can be also used. l When the external clock is selected Baud rate [bps] = f(XIN) ] 3 Division ratio ] 1 5 (BRG set value + 1) 5 16

1-116 7470/7471/7477/7478 GROUP USER’S MANUAL The BRG is an 8-bit counter dedicated to the Serial I/O, having a reload register, and divides the count source by (n + 1) by setting the value n. As a count source, f(XIN)/4 (at “0”), f(XIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register. In the 7478 Group, f(XCIN )/4 (at “0”), f(XCIN )/16 (at “1”), can be also selected. Table 1.13B.3 shows a baud rate reference value. Table 1.13B.3 Baud rate reference value BRG set valueCount sourceBaud rate [bps] Count source BRG set value f(XIN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 300 600 1200 2400 4800 9600 15600 31200 41600 f(X IN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/4 f(XIN)/4 51(3316 ) 25(1916 ) 12(0C16) 25(1916 ) 12(0C16) 103(6716 ) 51(3316 ) 25(1916 ) 12(0C16) 25(1916 ) 12(0C16) 7(0716) 3(0316 ) 2(0216 ) At f(XIN) = 7.9872 MHz At f(X IN) = 3.9936 MHz

1-1177470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

22222 Transmit/receive data format

A transmit/receive data format can be selected by the bits of the UART control register (UARTCON).

• Start bit (ST) : 1-bit
• Data bit (DATA) : 7-bit or 8-bit
• Parity bit (PA) : Non or 1-bit
• Stop bit (SP) : 1-bit or 2-bit Figure 1.13B.7 shows a transmit/receive data format, Table 1.13B.4 shows a function of each bit of transmit data, and Figure 1.13B.8 shows all data formats. Fig. 1.13B.7 UART data format Table 1.13B.4 Each bit function of UART transmit data Name Start bit ST Data bit DATA Parity bit PA Stop bit SP Function The “L” signal for 1 bit is added by the bit indicating a start of data transmission immediately before the transmit data. This bit indicates the transmit data written in the UART transmit buffer register. The “0” data is an “L” signal and the “1” data is an “H” signal. This bit is added immediately after the data bit for improvement of data reliability. The contents of this bit change according to the contents of the parity selection bit so that the number of “1”s in the transmit data including the parity bit may always be even or odd. This bit indicates that data has been transmitted, and is added immediately after the data bit (immediately after the parity bit when the parity is valid). The “H” signal for 1 bit or 2 bits is output. D 0 D 1 D 6 D 7 PA l For 1ST-8DATA-1PA-2SP ST STSP SP D 0 D 1 LSB MSB Transmit data Data bit (8 bits) Next transmit data (at continuous output)

7470/7471/7477/7478 GROUP USER’S MANUAL1-118 HARDWARE Fig. 1.13B.8 Transmit/receive format of UART D 0 D 1 D 4 D 5ST SP LSB MSB D 2 D 3 D 6 SP D 0 D 1 D 4 D 5ST LSB MSB D 2 D 3 D 6 SP SPD 0 D 1 D 4 D 5ST LSB MSB D 2 D 3 D 6 PA SPD 0 D 1 D 4 D 5ST LSB MSB D 2 D 3 D 6 PA SP D 0 D 1 D 4 D 5ST SP LSB MSB D 2 D 3 D 7 SP D 0 D 1 D 4 D 5ST LSB MSB D 2 D 3 D 7 SP SPD 0 D 1 D 4 D 5ST LSB MSB D 2 D 3 D 7 PA SPD 0 D 1 D 4 D 5ST LSB MSB D 2 D 3 D 7 PA SP D 6 D 6 D 6 D 6 Start bit Data bit Parity bit Stop bit ST: Di: PA: SP: l For 7-bit UART mode l For 8-bit UART mode

1-1197470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

22222 Transmit operation of UART

The Transmit operation of the UART is described below. l Start of Transmit operation Transmit data is transmitted by writing it into the Transmit buffer register (TB: address 00E016) in the Transmit enable state.]1 l Transmit operation

1 After transmit data is written into the Transmit buffer register, the transmit buffer empty flag (bit

0) of the Serial I/O status register is cleared to “0.”

2 The transmit data written in the Transmit buffer register is transferred to the Transmit shift

register. When the data transfer from the Transmit buffer register to the Transmit shift register is completed, the transmit buffer empty flag is set to “1.”] 2 When the transmit interrupt source bit (bit 3) of the Serial I/O control register (SIOCON) is “0,” the interrupt request bit is set to “1,” then a transmit interrupt request occurs.

3 The transmit data transferred to the transmit shift register is output from the P15/TxD pin in

synchronization with the fall of the synchronous clock starting with the start bit. The start bit, the parity bit and the stop bit are automatically generated and output according to the contents of setting of the UART control register.

4 When a transmit shift operation is started, the transmit shift completion flag (b2) of the Serial

I/O status register is cleared to “0.” 5 Data is output starting with the least significant bit of the Transmit shift register. Each time one- bit data is output, the contents of the Transmit shift register are shifted by 1 bit in the direction of the least significant bit.

6 After one-half a cycle of the synchronous clock

] 3 after a start of stop bit transmission, the transmit shift completion flag is set to “1.” When the bit 3 of the Serial I/O control register is “1” (transmit shift operation is completed), at the time the interrupt request bit is set to “1” and the Transmit interrupt request occurs. ] 1: Status in which the register for transmit operation has been completed. Refer to the “[UART transmit setting method]” which will be described later. ] 2:While the transmit buffer empty flag is “1,” the next transmit data can be written into the Transmit buffer register. ] 3: In case of two stop bits, the stop bit output period is that of the 2nd bit.

7470/7471/7477/7478 GROUP USER’S MANUAL1-120 HARDWARE l Transmit interrupt operation (valid when the Serial I/O is selected) Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the Serial I/O control register (SIOCON). 0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer register is transferred to the Transmit shift register, an interrupt request is generated. 1: When the shift operation of the Transmit shift register is completed, an interrupt request is generated. * In case of the UART, an interrupt operation is performed in the same way as when the synchronous clock is selected. Figure 1.13B.9 shows a transmit operation of UART and Figure 1.13B.10 shows a transmit timing of UART. Fig. 1.13B.9 Transmit operation of UART D 0 P15/TxD D 1D 2D 3D 4D 5D 6D 7 1 0 ST SP P15/TxD P15/TxD D 0D 2D 3D 4D 5D 6D 7 D 1 Data bus Address 00E016 Write transmit data Transmit buffer register Serial I/O status register (Address 00E116) Transmit buffer register Transmit shift register Transfer transmit data Serial I/O status register (Address 00E116) When “0” is selected by the bit 3 of the Serial I/O control register Interrupt request register 1 (Address 00FC16) Synchronous clock Transmit shift register Serial I/O status register (Address 00E116) Synchronous clock Synchronous clock Serial I/O status register (Address 00E116) When “1” is selected by the bit 3 of the Serial I/O control register Interrupt request register 1 (Address 00FC16) Transmit shift register

1-1217470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.13B.10 Transmit timing chart of UART D 0 D 1 D 2ST D 6 SPD 7TXD pin Synchronous clock, BRG output divided by 16, or external clock divided by 16 Write signal to Transmit buffer register : • Clearing by writing “0” to the transmit interrupt request bit.

• Clearing by accepting the transmit interrupt. Transmit buffer empty flag Transmit shift completion flag Transmit interrupt enable bit Transmit interrupt request bit : When interrupt request generation is selected, when the Transmit buffer register becomes empty by clearing the transmit interrupt source selection bit to “0”. : When interrupt request generation is selected, when the shift operation of the Transmit shift register is completed by setting the transmit interrupt source selection bit to “1”. Serial I/O not used B1 A 1 B 2 A2

7470/7471/7477/7478 GROUP USER’S MANUAL1-122 HARDWARE [UART transmit setting method] 1 Clear the Serial I/O transmit interrupt enable bit (bit 6 of Interrupt control register 1) to “0.” 2 When selecting the internal clock, set the BRG value. 3 Set the Serial I/O control register according to Table 1.13B.5. 4 Set the data format according to Table 1.13B.6.

5 When using a Serial I/O transmit interrupt

[1] Clear the Serial I/O transmit interrupt request bit (bit 6 of Interrupt request register 1) to “0.” Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O transmit interrupt request may be set to “1.” Clear the Serial I/O transmit interrupt request bit to “0” after one instruction or more after switching the ordinary port over to the Serial I/O port. [2] Set the Serial I/O transmit interrupt enable bit to “1.” 6 Write transmit data into the Transmit buffer register. Table 1.13B.5 UART transmit setting Register to be used Item f (XIN)/4 f (XIN)/16 BRG output divided by 16 External clock input divided by 16 Transmit buffer empty When the transmit shift operation is completed Transmit enable Disable (Half-duplex data communication) Enable (Full-duplex data communication) Clock asynchronization 4 to P17 function as Serial I/O pins (Note 3) Serial I/O control register (SIOCON: Address 00E2 16) bit setting value (Note 2) Notes 1: f(X CIN )/4 (setting value : 0), f(XCIN )/16 (setting value : 1) can be selected in the 7478 Group. 2: When the UART is selected, this bit does not function. 3: When the internal clock is selected, the P16/SCLK pin can be used as port P16. BRG count source selection (Note 1) Synchronous clock selection S RDY signal output selection Transmit interrupt request selection Transmit enable selection Receive enable selection Clock asynchronous selection Serial I/O enable selection Table 1.13B.6 Set value of UART control register Serial data transfer format 1ST-8DATA-1SP 1ST-7DATA-1SP 1ST-8DATA-1PA-1SP 1ST-7DATA-1PA-1SP 1ST-8DATA-2SP 1ST-7DATA-2SP 1ST-8DATA-1PA-2SP 1ST-7DATA-1PA-2SP UART control register (UARTCON: Address 00E3 16) Selection (Note) Selection (Note) Note: 0: Even parity 1: Odd parity

1-1237470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

22222 Receive operation of UART

The receive operation of UART is described below. l Start of receive operation Set the receive enable bit (bit 5) of the Serial I/O control register (SIOCON) to the enable state (“1”) in the receive enable state.] 1 With this operation, the start bit is detected and serial data is received. l Receive operation

1 After a fall of the P14/RxD pin is detected, the level of the P14/RxD pin is checked after one-

half a cycle of the synchronous clock. If its level is “L,” the bit is judged as a start bit. When its level is “H,” it is judged that noise is generated, so that the the receive operation is stopped and the UART waits for the start bit.

2 Receive data is input bit by bit from the P1

4/RxD pin to the Receive shift register in synchronization with the rise of the synchronous clock.

3 Data, immediately after the start bit, is input starting with the most significant bit of the Receive

shift register. Each time one bit is received, the contents of the Receive shift register are shifted by 1 bit in the direction of the least significant bit.

4 When the specified number of bits are all input in the Receive shift register, the contents of the

Receive shift register are transferred to the Receive buffer register (RB). ] 2,]3

5 After 1/2 cycle of the shift clock after a start of stop bit reception, the receive buffer full flag

(bit 1) of the Serial I/O status register (SIOSTS) is set to “1”]4 and a receive interrupt request is generated. 6 Error flag detection is started concurrently with the occurrence of the receive interrupt request. ] 1: Status in which the register for receive operation has been completed. Refer to the “[UART receive setting method]” which will be described later. ] 2: When the data bit length is 7 bits, the contents of the Receive buffer register consist of receive data of bits 0 to 6 and “0” of bit 7 (MSB). ] 3:If receive data is further input to the Receive shift register when data remains (when the receive buffer full flag is “1”) without reading out the contents of the Receive buffer register, the overrun error flag of the Serial I/O status register is set to “1.” At this time, the data of the Receive shift register is not transferred to the Receive buffer register and the original data of the Receive buffer register is held. ] 4: The receive buffer full flag is cleared to “0” by reading out the Receive buffer register.

7470/7471/7477/7478 GROUP USER’S MANUAL1-124 HARDWARE l Receive interrupt operation (valid when the Serial I/O is selected) When receive data is transferred from the Receive shift register to the Receive buffer register after one-byte data is all input to the Receive shift register, an interrupt request is generated. * In case of the UART, an interrupt operation is performed in the same way as when the synchronous clock is selected. Figure 1.13B.11 shows a receive operation of UART and Figure 1.13B.12 shows a receive timing of UART. Fig. 1.13B.11 Receive operation of UART RxD (noise) RxD (ST) À RxD (SP) P14/RxD D 0 D 1D 2D 3 D 0 P14/RxD D 5 D 2D 6D 7 D 3D 4 D 0D 1 ˆ 000 b4b5 Synchronous clock “H” level detected fi judge as noise Synchronous clock Receive shift register Synchronous clock Synchronous clock Receive shift register Receive shift register Receive buffer register(Address 00E016) Receive data transfer Synchronous clock Serial I/O status register (Address 00E116) Interrupt request register 1 (Address 00FC16) Serial I/O status register (Address 00E116) b3(OE)=“1” when the overrun error occurs. b4(PE)=“1” when the parity error occurs. b5(FE)=“1” when the framing error occurs. b6(SE)=“1” when OE U PE U FE=1. “L” level detected fi judge as start bit ´ ¯

1-1257470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.13B.12 Receive timing chart of UART A D 6 PAR SPD 1 D 2R XD pin ST D 0 Synchronous clock : • Clearing by writing “0” to the receive interrupt request bit.

• Clearing by accepting the receive interrupt. Receive buffer full flag Receive enable bit Receive interrupt request bit Receive buffer register read out signal Receive started by falling of ST Read into Receive shift register Test that level of ST is “L” A

7470/7471/7477/7478 GROUP USER’S MANUAL1-126 HARDWARE [UART receive setting method] 1 Clear the Serial I/O receive interrupt enable bit (bit 5 of Interrupt control register 1) to “0.” 2 When selecting the internal clock, set the BRG value. 3 Set the Serial I/O control register according to Table 1.13B.7. 4 Set the data format according to Table 1.13B.6.

5 When using a Serial I/O receive interrupt

[1] Clear the Serial I/O receive interrupt request bit (bit 5 of Interrupt request register 1) to “0.” Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O receive interrupt request may be set to “1.” Clear the Serial I/O receive interrupt request bit to “0” after one instruction or more after switching the ordinary port over to the Serial I/O port. [2] Set the Serial I/O receive interrupt enable bit to “1.” 6 In the full-duplex data communication, set transmit data in the Transmit buffer register (TB). Table 1.13B.7 UART receive setting Register to be used Item f (XIN)/4 f (XIN)/16 BRG output divided by 16 External clock input divided by 16 Transmit buffer empty When the transmit shift operation is completed Disable (Half-duplex data communication) Enable (Full-duplex data communication) Receive enable Clock asynchronous 4 to P17 function as serial I/O pins (Note 3) Serial I/O control register (SIOCON: Address 00E2 16) bit setting value (Note 2) Notes 1: f(X CIN )/4 (setting value : 0), f(XCIN )/16 (setting value : 1) can be selected in the 7478 Group. 2: When the UART is selected, this bit does not function. 3: When the internal clock is selected, the P16/SCLK pin can be used as port P16. BRG count source selection (Note 1) Synchronous clock selection S RDY signal output selection Transmit interrupt request selection Transmit enable selection Receive enable selection Clock asynchronous selection Serial I/O enable selection

1-1277470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE 1.13B.2 Pins The 7477/7478 group uses 4 pins for data transmit, data receive, shift clock transmit/receive and serial I/O transfer ready signal output. All these pins are used in common with P1. A function selection is made by the serial I/O enable bit (bit 7) and the S RDY output enable bit (bit 2) of the Serial I/O control register. The function of each pin is explained below. (1) Data transmit pin[TxD] Transmit data is output bit by bit. This pin is used in common with P15. When the transfer enable bit and the serial I/O enable bit of the Serial I/O control register is set to “1,” this pin becomes a serial I/O data output pin. (2) Data receive pin [RxD] Data is input bit by bit. This pin is used in common with P1 4. When the receive enable bit and the serial I/O enable bit of serial I/O control register are set to “1,” this pin becomes a serial I/O data input pin. (3) Shift clock transmit/receive pin [S CLK ]

2 Clock synchronous

This pin inputs (receives from the outside) or outputs (supplies to the outside) the synchronous clock for data transmit/receive. When the serial I/O synchronous clock selection bit (bit 1) of the Serial I/O control register is cleared to “0” (use of internal clock), the synchronous clock is output. When the same bit is set to “1” (use of internal clock), the synchronous clock is input from the outside.

2 Clock asynchronous (UART)

When the serial I/O synchronous clock selection bit (bit 1) of the Serial I/O control register is set to “1” (use of external clock), the synchronous clock is supplied from the outside. When the same bit is cleared to “0” (use of internal clock), this pin does not function. Note : When the internal clock is selected, S CLK pin can be used as port P16. (4) Serial transfer enable signal output pin [S RDY ] This pin informs the outside of a receive enable state in the clock synchronous serial I/O. In case of the UART, this pin does not function. l S RDY signal output enable bit (bit 2) of Serial I/O control register is set to “1.” l Transmit enable bit (bit 4) of Serial I/O control register is set to “1.” When the above 2 conditions are satisfied, the level of the pin changes from “H” to “L” at the timing at which data was written into the Transmit buffer register, informing the outside of a serial transfer enable state.

7470/7471/7477/7478 GROUP USER’S MANUAL1-128 HARDWARE 1.13B.3 Notes on use (1) Notes on external clock selection In the 7477/7478 group, either the internal clock or external clock can be selected as the synchronous clock. When the external clock is selected as the synchronous clock, take the following points into consideration.

2 Clock synchronous serial I/O

1 During data transmission, when setting the transmit enable bit to “1” or writing data into the

Transmit buffer register, perform a write operation while the synchronous clock is at “H.”

2 The transmission or the shift operation of the Receive shift register is continued while the

synchronous clock is input to the serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. When the internal clock is selected, the synchronous clock stops automatically at the end of 8 cycles.

3 When the external clock is selected, set the “H” and “L” widths (T

WH , TWL ) of the pulse used as the external clock source to TWH , TWL [s] Q 8/(f(XIN) [Hz]). For example, when f(XIN) is 8 MHz, use a clock of 500 kHz or less (duty ratio 50 %).

2 UART

Set the “H” and “L” widths (TWH , TWL ) of the pulse used as the external clock source to TWH , T WL [s] Q 2/(f(XIN) [Hz]). For example, when f(XIN) is 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %). (2) When the S RDY output is performed in the clock synchronous serial I/O When the receive side using the external clock performs an S RDY output, set the receive enable bit, the SRDY output enable and the transmit enable bit to “1” (transmit enable). (3) When a serial I/O transmit interrupt or a serial I/O receive interrupt is caused

2 When using a serial I/O transmit interrupt

1 Clear the serial I/O transmit interrupt request bit (bit 6 of IR1) to “0” after one instruction or

more after setting a value in the Serial I/O control register. 2 After setting in 1, set the serial I/O transmit interrupt enable bit (bit 6 of IE1) to “1.”

2 When using a serial I/O receive interrupt

1 Clear the serial I/O receive interrupt request bit (bit 5 of IR1) to “0” after one instruction or more after setting a value in the Serial I/O control register. 2 After setting in 1, set the serial I/O receive interrupt enable bit (bit 5 of IE1) to “1.” (4) Transmit interrupt request in the transmit enable state After the transmit enable bit is set to “1,” the transmit buffer empty flag and the transmit shift completion flag are set to “1.” Accordingly, even if a transmit buffer empty state is selected or a termination of shift operation of the Transmit shift register is selected as a transmit interrupt source, an interrupt request is generated and the transmit interrupt request bit is set to “1.” For this reason, when using a transmit interrupt, set the transmit enable bit to “1,” clear the transmit interrupt request bit to “0,” and then set the transmit interrupt enable bit to “1” (enable state).

1-1297470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (5) Disabling transmission after transmission of 1-byte data In the 7477/7478 group, it is possible to make reference to the transmit shift register completion flag (TSC flag) to know that data has been transmitted. The TSC flag is “0” during data transmission, and becomes “1” after data has been transmitted. Accordingly, if data transmission is disabled at the time of confirmation of a change of the TSC flag from “0” to “1,” data transmission can be terminated after 1-byte data is transmitted. However, the TSC flag is also set to “1” when the serial I/O is enabled and does not become “0” until a synchronous clock is generated and transmitted. For this reason, if data transmission is disabled by making reference to the TSC flag at this time, data is not transmitted. Make reference to the TSC flag after a start of data transmission. The change of the TSC flag from “1” to “0” has a delay of 0.5 to 1.5 cycles of the synchronous clock. (6) Re-setting the Serial I/O control register (SIOCON) Re-set the Serial I/O control register after setting both transmit enable bit and receive enable bit to “0” to re-set the transmit circuit and the receive circuit. 1 Clear both transmit enable bit (TE) and receive enable bit (RE) to “0.” 2 Set the bit 0 to bit 3 and bit 6 of the Serial I/O control register. 3 Set both transmit enable bit (TE) and receive enable bit (RE) to “1.” (It is possible to set 2 and 3 simultaneously with the LDM instruction.) (7) Stopping data transmit/receive 2 In the following cases, clear the transmit enable bit to “0” (transmit disable). l To stop the transmit operation when data is transmitted in the clock synchronous serial I/O l To stop the transmit operation when UART data is transmitted l To stop only the transmit operation when UART data is transferred

2 In the following cases, clear receive enable bit (receive disable) or serial I/O enable bit to “0”

(serial I/O disable). l To stop the receive operation when data is received in the clock synchronous serial I/O 2 In the following cases, clear the receive enable bit to “0.” l To stop the receive operation when UART data is received. l To stop only the receive operation when UART data is transferred.

2 In the following cases, clear both transmit enable bit and receive enable bit to “0” (transfer

disable) simultaneously. l To stop the transmit operation and the receive operation when data is transferred in the clock synchronous serial I/O Note: When data is transferred in the clock synchronous serial I/O, it is impossible to stop only the transmit operation or the receive operation.

7470/7471/7477/7478 GROUP USER’S MANUAL1-130 HARDWARE (8) Processing upon occurrence of errors

2 When a parity error, a framing error or a summing error occurs

When a parity error, a framing error or a summing error occurs, the flag corresponding to each error in the Serial I/O status register is set to “1.” These flags are not cleared to “0” automatically. Clear them to “0” by software. The parity error flag, the framing error flag and the summing error flag can be cleared to “0” by one of the following two methods. l Clear the receive enable bit to “0.” l Write arbitrary dummy data into the Serial I/O status register.

2 Processing upon occurrence of overrun error

An overrun error occurs when data has all been input to the Receive shift register while data is stored in the Receive buffer register. When an overrun error occurs, the data of the Receive shift register is not transferred to the Receive buffer register and the data of the Receive buffer register is held. At this time, even if the data of the Receive buffer register is read out, the data of the Receive shift register is not transferred. Accordingly, the data of the Receive buffer register can be read out but the data of the Receive shift register cannot be read out and becomes invalid. When an overrun error occurs, clear the overrun error flag of the Serial I/O status register to “0” and then make preparations for receiving data again. The overrun error flag can be cleared by one of the following methods. l Clear the serial I/O enable bit to “0.” l Clear the receive enable bit to “0.” l Write arbitrary dummy data into the Serial I/O status register.

1-1317470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE 1.13B.4 Related registers (1) Transmit/receive buffer register (TB/RB: Address 00E016) The Transmit/receive buffer register is written serial I/O (used in common with the clock synchronous serial I/O and the UART) transmit data and is read out serial I/O receive data. l To transmit data, write this transmit data into this register. l Receive data can be obtained by reading this register. Figure 1.13B.13 shows a structure of the Transmit/receive buffer register. Fig. 1.13B.13 Structure of Transmit/receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/receive buffer register (TB/RB) [Address B Function At resetR W Transmit/receive buffer register (7477/7478 group) to A value of “0016” to “FF16” can be set as transmit data. The transmit data is transferred automatically by writing the transmit data into the Transmit shift register. When all receive data has been input into the Receive shift register, the receive data is automatically trans- ferred to the receive buffer register. At transmit: At receive: 00E0 16]

7470/7471/7477/7478 GROUP USER’S MANUAL1-132 HARDWARE Fig. 1.13B.14 Structure of Serial I/O status register (2) Serial I/O status register (SIOSTS: Address 00E116) The Serial I/O status register consists of flags for representing the buffer/register state to be used for data transfer, and error flags. l This register is a read-only type. l Bit 7 is unused and “1” at a read operation. Figure 1.13B.14 shows a structure of the Serial I/O status register. b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O status register (SIOSTS) [Address B At resetR W Serial I/O status register (7477/7478 group) Name Function Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “1.” Summing error flag (SE) 0 : (OE) U (PE) U (FE) = 0 1 : (OE) U (PE) U (FE) = 1 0 5 00E1 16]

1-1337470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Each bit of the Serial I/O status register is described below.

2 Transmit buffer empty flag (TBE, bit 0)

This flag indicates the state of the Transmit buffer register. This bit is set to “1” after the data written in the Transmit buffer register is transferred to the Transmit shift register, and cleared to “0” after data is written into the Transmit buffer register. This flag is valid in both clock synchronous serial I/O and UART.

2 Receive buffer full flag (RBF, bit 1)

This flag indicates the state of the Receive buffer register. When 1-byte data has been all input to the Receive shift register and then the receive data has been transferred from the Receive shift register to the Receive buffer register, this flag is automatically set to “1.” When the transferred data has been read out from the Receive buffer register, the flag is automatically cleared to “0.” If receive data is further input to the Receive shift register when the receive buffer full flag is “1” (without reading out the contents of the Receive buffer register), the overrun error flag is set to “1.” The receive buffer full flag is valid in both clock synchronous serial I/O and UART.

2 Transmit shift completion flag (TSC, bit 2)

This flag indicates the state of the transmit shift operation. When transmit data has been transferred to the Transmit shift register and then a shift operation has been started with the synchronous clock (transmission of the 1st bit of the transmit data), this flag is cleared to “0.” When the shift operation has been completed (completion of transmission the last bit of the transmit data), the flag is set to “1.” This flag is valid in both clock synchronous serial I/O and UART.

2 Overrun error flag (OE, bit 3)

This flag indicates the receive data read state. If receive data is further input to the Receive shift register when the receive buffer full flag is “1” (without reading out the contents of the Receive buffer register), the overrun error flag is set to “1.” This flag is cleared to “0” by any operation shown in Table 1.13B.8. This flag is valid in both clock synchronous Serial I/O and UART.

2 Parity error flag (PE, bit 4)

This flag indicates a hardware check result on the even parity or odd parity in the UART. If there is a difference between the parity of received data and the set parity, the flag is set to “1.” This flag is cleared to “0” by any operation shown in Table 1.13B.8. This flag is valid in the parity enable state in UART.

2 Framing error flag (FE, bit 5)

This flag judges a frame synchronization error in UART. When the stop bit of receive data cannot be received at the set timing, the flag is set to “1.” At stop bit detection, only the 1st stop bit is detected but the 2nd stop bit is not checked. This flag is cleared by any operation shown in Table 1.13B.8. This flag is valid in UART only.

7470/7471/7477/7478 GROUP USER’S MANUAL1-134 HARDWARE Table 1.13B.8 Error flag clear method

2 Summing error flag (SE, bit 6)

This flag judges a serial I/O error. If one of an overrun error, a parity error and a framing error occurs, the flag is set to “1.” This flag is cleared by any operation shown in Table 1.13B.8. This flag is valid in both clock synchronous serial I/O and UART. [Error flag clear method] The error flags (bit 3 to bit 6) in the Serial I/O status register can be cleared to “0” by the error flag clear methods shown in Table 1.13B.8. Error flag Overrun error flag Parity error flag Framing error flag Summing error flag Clear the receive enable bit to “0.” Write dummy data into the SIOSTS. Clear the serial I/O inter- rupt enable bit to “0.”

1-1357470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (3) Serial I/O control register (SIOCON: Address 00E216) The Serial I/O control register exerts various types of control over the serial I/O, for example, transfer mode, clocks and pin function selection. All the bits of this register can be read and written by software. Figure 1.13B.15 shows a structure of the Serial I/O control register. Fig. 1.13B.15 Structure of Serial I/O control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address B At resetRW Serial I/O control register (7477/7478 group) Name Function BRG count source selection bit (CSS) 0 : f(XIN)/4 1 : f(XIN)/16 Serial I/O synchronous clock selection bit (SCS) Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O enable bit (SIOE) Serial I/O mode selection bit (SIOM) S RDY output enable bit (SRDY) ] In the UART mode, this bit is invalid.

• In clock synchronous mode 0 : BRG output divided by 4 1 : External clock input
• In UART mode 0 : BRG output divided by 16 1 : External clock input divided by 16 0 : P17/SRDY pin operates as ordinary I/O pin 1 : P17/SRDY pin operates as SRDY output pin 0 : When transmit buffer has emptied 1 : When transmit shift operation is completed 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : Clock asynchronous serial I/O (UART) 1 : Clock synchronous 0 : Serial I/O disabled (pins operates as ordinary I/O pins P14–P17) 1 : Serial I/O enabled (pins operates as serial I/O pins RXD - SRDY ) (Note 2) Notes 1: Port P14–P17 are operates as the serial I/O pin only when the serial I/O enable bit is “1” (enable state). At this time, Port P1 7 is also used as an ordinary I/O port. In the UART mode, port P16 is used as an ordinary I/O port when the internal clock is selected. 00E2 16] (Note 1) In the 7478 Group, f(X )/4 (at “0”), f(X )/16 (at “1”) can be also selected. CIN CIN

7470/7471/7477/7478 GROUP USER’S MANUAL1-136 HARDWARE Each bit of the Serial I/O control register is described below.

2 BRG count source selection bit (CSS, bit 0)

This bit selects a count source to be input to the BRG.

• “0”: f(XIN)/4
• “1”: f(XIN)/16

2 Serial I/O synchronous clock selection bit (SCS, bit 1)

This bit selects a synchronous clock to be used for the serial I/O. l In the clock synchronous serial I/O

• “0”: The BRG output divided by 4 becomes a shift clock.
• “1”: The external clock (P1 6/SCLK pin input) becomes a synchronous clock. l In the UART
• “0”: The BRG output divided by 16 becomes a shift clock.
• “1”: The external clock (P1 6/SCLK pin input) divided by 16 becomes a synchronous clock. S RDY output enable bit (SRDY , bit 2) This bit selects whether the P17/SRDY pin is used as P17 or as serial I/O pin S RDY or S RDY output disable. l In the clock synchronous serial I/O
• “0”: SRDY pin output disable (used as port P17)
• “1”: SRDY pin output enable (used as serial I/O pin S RDY ) l In the UART The P1 7/S RDY pin is used as P17 regardless of the value of this bit.

2 Transmit interrupt request selection bit (TIC, bit 3)

This bit determines a source for generating a transmit interrupt request.

• “0”: When the contents of the Transmit buffer register are transferred to the Transmit shift register, a transmit interrupt request is generated.
• “1”: When the shift operation of the Transmit shift register terminates, a transmit interrupt request is generated.

2 Transmit enable bit (TE, bit 4)

This bit controls a transmit operation. l When the serial I/O enable bit (bit 7) is “0” (serial I/O disable) The transmit enable bit is invalid. l When the serial I/O enable bit (bit 7) is “1” (serial I/O disable) The control shown in Table 1.13B.9 is exerted. ∗1: Bit 0 of Serial I/O status register ∗2: Bit 2 of Serial I/O status register Transmit enable bit Transmit buffer empty flag Cleared to “0” Flag function is valid. Transmit shift completion flag∗2 Cleared to “0” Flag function is valid. P1 5/TX D pin function Port P15 Serial I/O data transmit pin TXD Table 1.13B.9 Transmit enable bit function

1-1377470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

2 Receive enable bit (bit 5)

This bit controls the receive operation. l When the serial I/O enable bit (bit 7) is “1” (serial I/O enable), the control shown in Table 1.13B.10 is exerted. l When the serial I/O enable bit (bit 7) is “0” (serial I/O disable), this bit is invalid. Table 1.13B.10 Receive enable bit function ∗1: Bit 1 of Serial I/O status register ∗2: Bit 3,4,5 and 6 of Serial I/O status register

2 Serial I/O mode selection bit (bit 6)

This bit selects the clock synchronous serial I/O or the UART.

• “0”: UART
• “1”: Clock synchronous serial I/O

2 Serial I/O enable bit (bit 7)

This bit selects whether each of the P14/RxD, P15/TxD, P16/SCLK and P17/S RDY pins is used as a port or a serial I/O pin. When using the serial I/O, set this bit to “1.”

• “0”: The respective pins become P1 4 to P17.
• “1”: The respective pins become serial I/O pins, RXD, TxD, SCLK , S RDY . Note: In the UART, when the internal clock is selected, the P16/SCLK pin can be used as port P16. However, for the P17/S RDY pin, take the following points into consideration.

2 In the clock asynchronous serial I/O

When using the P17/S RDY pin as serial I/O pin S RDY , set the S RDY output enable bit (bit 2) to “1.”

2 In the UART

The P1 7/S RDY pin is used as P17 regardless of the value of the serial I/O enable bit. Receive enable bit Receive buffer full flag Cleared to “0” Flag function is valid. Each error flag∗2 Cleared to “0” Flag function is valid. P1 4/RXD pin function Port P14 Serial I/O data transmit pin RXD

7470/7471/7477/7478 GROUP USER’S MANUAL1-138 HARDWARE (4) UART control register (UARTCON: Address 00E3 16) The UART control register controls the UART transfer data format. Figure 1.13B.16 shows a structure of UART control register. Fig. 1.13B.16 Structure of UART control register Each bit of the UART control register is described below.

2 Character length selection bit (CHAS, bit 0)

This bit selects a data bit length of the UART transfer data format.

• “0”: 8-bit length
• “1”: 7-bit length

2 Parity enable bit (PARE, bit 1)

This bit selects whether a parity check is made.

• “0”: No parity check (Parity error flag is invalid.)
• “1”: Parity check (Parity error flag is valid.)

2 Parity selection bit (PARS, bit 2)

This bit selects a parity type of the UART transfer data format.

• “0”: Even
• “1”: Odd

2 Stop bit length selection bit (STPS, bit 3)

This bit selects a stop bit length of the UART transfer data format.

• “0”: 1-stop bit
• “1”: 2-stop bit b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address B At resetRW UART control register (7477/7478 group) to Name Function Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “1.” Parity selection bit (PARS) 0: Even parity 1: Odd parity 1111 00E3 16]

1-1397470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.14.1 A-D converter block diagram In the 7470/7471/7477/7478 group, the following A-D converter is incorporated. l Analog input pins…… 7470/7477 group: 4 channels (in common with Port P2) 7471/7478 group: 8 channels (in common with Port P2) l Conversion method… Successive approximation comparison In the 7470/7471 group, when the A-D converter is not used, power dissipation can be suppressed by the V REF switch. (The 7477/7478 group is not provided with this function.) Figure 1.14.1 shows a block diagram of the A-D converter. b4 b0 P20/IN0 P21/IN1 P22/IN2 P23/IN3 P24/IN4 P25/IN5 P26/IN6 P27/IN7 V SS VREF Data bus (Note 2) A-D control register (Address 00D916) Channel selector Comparator A-D control circuit A-D conversion register (Address 00DA16) (Note 1) Switch tree Resistor ladder A-D conversion interrupt request VREF switch (Note 2) Notes 1. The 7470/7477 group is not provided with the P2 /IN4–P2 7/IN7 pins. 2. The 7477/7478 group is not provided with the V switch and the V connection selection bit (bit 4) of the A-D control register. REF REF

7470/7471/7477/7478 GROUP USER’S MANUAL1-140 HARDWARE

1.14.1 A-D conversion method

The A-D conversion method is of successive approximation comparison. The reference voltage V ref generated internally is compared with the analog input voltage VIN which is input from the analog input pin (P20/IN0–P27/IN7), and its result is stored into each bit of the A-D conversion register (address 00DA16) successively to obtain a digital value. [Internal operation] After A-D conversion is started, the following operations are automatically performed.

1 The contents of the A-D conversion register is set to “00

16.” 2 The most significant bit (bit 7) of the A-D conversion register is set to “1.” 3 The reference voltage Vref is input to the comparator. The reference voltage Vref is specified by the contents n of the A-D conversion register and the reference voltage VREF input from the VREF pin. An expression for the reference voltage V ref is shown below. Relational expression between Vref and VREF When n = 0 V ref = 0 When n = 1 to 255 V ref = VREF /256 × (n – 0.5) n: The values of A-D conversion register (decimal notation) 4 The reference voltage Vref and the analog input voltage VIN are compared with 8 times. Upon completion of each comparison, the comparison result is stored into the A-D conversion register. As the A-D conversion register changes, the reference voltage V ref changes. [1] Determination of the most significant bit (bit 7) of the A-D conversion register (in the 1st comparison) The reference voltage V ref and the analog input voltage VIN are compared. Bit 7 is determined according to its result as follows. If Vref < VIN , then bit 7 = “1.” If Vref > VIN , then bit 7 = “0.” [2] Determination of the bit 0 - 6 of the A-D conversion register (after the 2nd comparison). First, bit 6 of the A-D conversion register is set to “1.” Next, the reference voltage Vref is compared with the analog input voltage VIN. Bit 6 is determined according to its result as follows. If Vref < VIN , then bit 6 = “1.” If Vref > VIN , then bit 6 = “0.”

1-1417470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Likewise, bit 5 to bit 0 are determined according to comparison results of the 3rd to 8th comparisons. A digital value (contents of the A-D conversion register) corresponding to the analog input voltage V IN is determined bit by bit by these operations. Figure 1.14.2 shows the changes of the contents of the A-D conversion register and the reference voltage during A-D conversion.

5 After completion of A-D conversion, bit 3 of the A-D control register is set to “1” and an interrupt

request is generated concurrently with the completion of A-D conversion. Notes 1: An A-D conversion result can be obtained by reading the A-D conversion register after bit 3 of the A-D control register is set to “1.” 2: The A-D conversion result is held in the A-D conversion register until bit 3 of the A-D control register is set to “1” again after completion of the next A-D conversion. Fig 1.14.2 Contents of A-D conversion register and reference voltage during A-D conversion 1 0000000 12 100000 1 0000001 1234567 1 VREF VREF 512– VREF VREF VREF 512–± VREF VREF VREF VREF 512 –± ± 00000000 0 m 12 3 45678 VREF VREF VREF ± ± ± VREF 512–VREF m A-D conversion start Contents of A-D conversion register 1st comparison start 2nd comparison start 3rd comparison start 8th comparison start Reference voltage (Vref) [V] Digital value corresponding to analog input voltage : Value determined by m th (m =1 to 8) result A-D conversion completion (8th comparison completion)

7470/7471/7477/7478 GROUP USER’S MANUAL1-142 HARDWARE

2 Conversion time

l After a start of A-D conversion, this A-D conversion terminates after 50 cycles (12.5 µ s at f(XIN) = 8 MHz). l Main clock input oscillation frequency f(XIN)/2 is used as an operating clock for the A-D converter, so the A-D conversion time can be basically obtained by the following expression. A-D conversion time = f(XIN) × conversion cycle (50: cycles) Note: Because the comparator is configurated by capacity coupling, use the A-D converter in the following condition. f(XIN) > 1 MHz Accordingly, use the A-D converter in the condition that bit 7 of the CPU mode register (address 00FB16) is “0” (ordinary mode). [Setting method] In the 7470/7471 group

1 Clear the bit of the Port P2 direction register corresponding to the used analog input pin to “0”

(input mode). 2 Clear the port pull-up control bit corresponding to the used analog input pin to “0” (no pull-up). 3 Clear the A-D conversion interrupt request bit of the Interrupt request register 1 to “0.” Note: After A-D conversion is started, the A-D conversion interrupt request bit is not cleared to “0” automatically.

4 When using an A-D conversion interrupt, set the A-D conversion interrupt enable bit to “1” to

provide an interrupt enable state. 5 Set the A-D control register as follows. l Select an analog input pin by the analog input pin selection bit. l Set the VREF connection selection bit to “1” and connect VREF to a ladder resistor. 6 Wait for 1.0 µs or more as VREF stabilizing time. 7 Clear the A-D conversion end bit of the A-D control register to “0.” (With this setting, A-D conversion is started.) In the 7477/7478 group 1 Clear the A-D conversion interrupt request bit of the Interrupt request register 1 to “0.” Note: After A-D conversion is started, the A-D conversion interrupt request bit is not cleared to “0” automatically.

2 When using an A-D conversion interrupt, set the A-D conversion interrupt enable bit to “1” to

provide an interrupt enable state. 3 Set the A-D control register as follows. l Select an analog input pin by the analog input pin selection bit. l Clear the A-D conversion end bit to “0.” (With this setting, A-D conversion is started.) Don't read the contents of the A-D conversion register during A-D conversion. For register setting, refer to “Table 1.14.1 Setting at A-D Conversion.”

1-1437470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Processing after conversion 1 A termination of conversion can be verified by any of the following operations. l State of A-D conversion end bit. l State of A-D conversion interrupt request bit. l Branch to A-D conversion interrupt routine. 2 Read the A-D conversion register to obtain a conversion result. Notes 1: Be sure to connect VREF to a ladder resistor during A-D conversion (7470/7471 group). 2: A-D conversion is restarted at the time when the A-D conversion end bit (bit 3) of the A-D control register is cleared to “0” during A-D conversion. Table 1.14.1 Setting at A-D conversion Register

1 Port P2 direction register(P2D: Address 00C516)

(7470/7471 group)

2 Port P1-P4 pull-up control register (7470 group)

Port P1-P5 pull-up control register (7471 group) (Address 00D116)

3 Interrupt request register 1 (IR1: Address 00FC16)

4 Interrupt control register 1 (IE1: Address 00FE16)

5 A-D conversion control register

(ADCON: Address 00D9 16) Bit b2, b1, b0 Value Clear the bit corresponding to the used ana- log input pin (one of pins P2 0/IN0 to P27/ IN7) to “0” (input mode). Note: In the 7470 group, only pins P20/IN0 to P23/IN3 are available. 0: P20 to P23 are not pulled up. Note: When one of pins P20/IN0 to P23/IN3 is used as an analog input pin 0: P24 to P27 are not pulled up. Note: When one of pins P24/IN4 to P27/IN7 is used as an analog input pin (7471 group) 0: A-D conversion interrupt disabled 1: A-D conversion interrupt enabled

• 000: P2 0/IN0
• 001: P21/IN1
• 010: P22/IN2
• 011: P23/IN3
• 100: P24/IN4
• 101: P25/IN5
• 110: P26/IN6
• 111: P27/IN7 Set the value corresponding to the used ana- log input pin. Note: In the 7470/7477 group, only pins P2 IN0 to P23/IN3 are available. 0: During conversion (A-D conversion is started.) 1: V REF connection (7470/7471 group) Fix this bit to “0.”

7470/7471/7477/7478 GROUP USER’S MANUAL1-144 HARDWARE

1.14.2 Pins

The pins used in the A-D converter are described below. (1) Analog input pin (P20/IN0 to P27/IN7) (P20/IN0 to P23/IN3 in the 7470/7477 group) l The analog input pin is an input pin for analog voltage. l Apply a voltage of VSS (AVSS ) - VREF to this pin. l This pin is used in common with P20 to P27 (P20 to P23 in the 7470/7477 group). When using the A-D converter, select a pin to be used as an analog input pin by bit 2 to bit 0 of the A-D control register (ADCON: address 00D916). Use the A-D converter in the following condition in the 7470/7471 group.

• When the bit of the Port P2 direction register, which corresponds to the used analog input pin, is “0” (input mode)
• When the bit of the Pull-up control register, which corresponds to the used analog input pin, is “0” (no pull-up) (2) Reference voltage input pin (VREF ) l The reference voltage input pin is an input pin for reference voltage. l Input a voltage of 0.5 VCC (>2) - VCC [V]. (3) Analog power source input pin (AVSS ) l Analog power source input pin is an input pin for GND. l Apply the same potential as the VSS pin to this pin. l This pin is dedicated to the 56P6N-A package product of the 7471/7478 group.

1.14.3 Notes on use

When using the A-D converter, take the following points into consideration. 2 The comparator is configured by capacity coupling, so the charge is lost if the clock input oscillation frequency is low. l Set f(XIN) at 1 MHz or more during A-D conversion. l Don’t execute the STP instruction during A-D conversion. 2 Apply a voltage of 0.5 VCC (>2) - VCC [V] to the reference voltage input pin VREF . Note that if the reference voltage is lowered below the above valve, the A-D conversion precision will be degraded.

2 Apply the same potential as that of the V

SS pin to the analog power supply voltage input pin AVSS . The AV SS pin is dedicated to the 56P6N-A package product of the 7471/7478 group.

2 In the 7470/7471 group, clear the bit of the Port P2 direction register which corresponds to the used

analog input pin to “0” (input mode).

2 In the 7470/7471 group, clear the bit of the Pull-up control register which corresponds to the used

analog input pin to “0” (no pull-up).

1-1457470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.14.4 References

2 Definition of A-D conversion precision

The definition of A-D conversion precision is described. Refer to the definition of A-D conversion precision shown in Figure 1.14.3. (1) Relative precision l Zero transition error (VOT ) Deviation of the input voltage, at which A-D conversion output data changes from “0” to “1,” from the ideal A-D conversion characteristics between 0 and V REF V OT = (VO – 2 × V REF )/1LSB [LSB] l Full-scale transition error (VFST ) Deviation of the ideal A-D conversion characteristics between 0 and VREF of the input voltage when the A-D conversion output data changes from “255” to “254”. V FST = {(VREF – 3 × V REF ) – V254 }/1LSB [LSB] l Non-linearity error Deviation of the real A-D conversion characteristics from the ideal characteristics between V0 and V254 Non-linearity error = {Vn – (1LSB × n + VO )}/1LSB [LSB] l Differential non-linearity error Deviation of the input voltage required to change output data by “1” from the ideal characteristics between V 0 and V254 Differential non-linearity error = {(Vn+1 – Vn) – 1LSB}/1LSB [LSB] (2) Absolute precision l Absolute precision Deviation of the real A-D conversion characteristic from the ideal characteristics between 0 and V REF . Absolute precision = {Vn – 1LSB × (n + 1 2 )}/1LSB [LSB] 256 2562

7470/7471/7477/7478 GROUP USER’S MANUAL1-146 HARDWARE Fig. 1.14.3 Definition of A-D conversion precision V n: Analog input voltage when output data changes from “n” to “n + 1” (n = 0 – 254).

• 1LSB = V 254 – VO (V) → 1LSB at relative precision
• 1LSB = VREF (V) → 1LSB at absolute precision 254 256

1 LSB

3 LSB

n n+1 254 255 Output data Full-scale transition error (VFST ) Analog voltage Absolute accuracy Zero transition error (VOT ) Differential non-linearity error Non-linearity error Ideal A-D conversion characteristics between 0 and VREF Ideal A-D conversion characteristics between V 0 and V254 1LSB at relative accuracy 1LSB at absolute accuracy Actual A-D conversion characteristics

1-1477470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.14.5 Related registers

(1) A-D conversion register (AD: Address 00DA16) The A-D conversion register stores A-D conversion results. This register is a read-only type. Figure 1.14.4 shows a structure of the A-D conversion register. Fig. 1.14.4 Structure of A-D conversion register (2) A-D control register (ADCON: Address 00D916) The A-D control register consists of bits that exerts various types of control over the A-D converter. Figure 1.14.5 shows a structure of the A-D control register. b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address B At resetR W A-D conversion register to Function This is a read-only register to store A-D conversion results. 5? 00DA 16]

7470/7471/7477/7478 GROUP USER’S MANUAL1-148 HARDWARE Fig. 1.14.5 Structure of A-D control register Each bit of the A-D control register is described below. n Analog input pin selection bit (Bit 2 to 0) These bits select an analog input pin. Pins that are not used as analog input pins of P2 function as programmable I/O ports (input ports in the 7477/7478 group). n A-D conversion end bit (Bit 3) This bit indicates the operation state of the A-D converter. This bit is cleared to “0” during A-D conversion and set to “1” upon termination of A-D conversion. A-D conversion is started by clearing this bit to “0.” (At the time when the bit is cleared to “0” during A-D conversion, A-D conversion is restarted.) n V REF connect selection bit (Bit 4) (The 7477/7478 group is not provided with this bit.) This bit connects the VREF pin to a ladder resistor. When using the A-D converter, be sure to set this bit to “1.” When the A-D converter is not used, power consumption can be reduced by clearing this bit to “0.” b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address B At resetR W A-D control register 5, 6 00 0 Name Function A-D input selection bits 0 0 0 : P20/IN0 0 : Under conversion 1 : End conversion b2 b1 b0 (Note 1) A-D conversion end bit (Note 2) VREF connection selection bit ] The 7477/7478 group is not provided with this bit. This bit is undefined at reset. Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. Fix this bit to “0.” ?? 5 0 0 1 : P21/IN1 0 1 0 : P22/IN2 0 1 1 : P23/IN3 1 0 0 : P24/IN4 1 0 1 : P25/IN5 1 1 0 : P26/IN6 1 1 1 : P27/IN7 0 : The VREF pin is separated from the comparison voltage generator. 1 : The VREF pin is connected to comparison voltage generator. Notes 1: Since the 7470/7477 group is not provided with pins P24–P27, do not set.

• A-D conversion is started by setting bit 3 to “0.”
• Writing “0” into bit 3 is valid. Even if “1” is written into bit 3, this bit is not set to “1.” Accordingly, when writing a value into the A-D control register without affecting bit 3, set bit 3 to “1.” 00D9 16]

1-1497470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE The microcomputer is reset by applying the “L” level to the RESET pin for 2 µs or more when the power source voltage is within the standard value range. After that, when the “H” level is applied to the RESET pin, the reset state of the microcomputer is released, so that the program is run starting with the reset vector address.

1.15.1 Operation description

Figure 1.15.1 shows an internal processing sequence after reset release. Fig. 1.15.1 Internal processing sequence after reset release Internal clock φ FFFE 16 AHAL FFFF 16 AL,AH XIN RESET Internal reset Address bus Data bus SYNC VCC Internal clock φ :CPU reference clock frequency = f(XIN)/2 (ordinary mode immediately after reset release) AH , AL :Content of reset vector address :Undefined SYNC : CPU operation code fetch cycle (This is a internal signal, so that it cannot be observed from the external unit.) 32768 counts of XIN pin input signal 2 µs or more XIN

7470/7471/7477/7478 GROUP USER’S MANUAL1-150 HARDWARE After the “H” level is applied to the RESET pin, only the main clock oscillates regardless of the oscillation state precedent to the reset state, so that the microcomputer starts to operate in the ordinary mode. The X CIN pin and the XCOUT pin become P50 and P51, respectively. After the reset state is released, the microcomputer runs the program starting with the high-order address corresponding to the contents of address FFFF 16 and the low-order address corresponding to the contents of address FFFE16. Note: The 7470/7477 group is not provided with the XCIN and XCOUT pins. When the “H” level is applied to the RESET pin at the reset state, the contents of timer 3 and timer 4 and the count source are automatically set as shown in Table 1.15.1, so that the internal reset state is released by an overflow of timer 4. Table 1.15.1 Timer 3 and 4 at reset Item Setting value count source Timer 3 FF 16 f(XIN)/16 Timer 4 0716 overflow of timer 3

1-1517470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.15.2 Internal status immediately after reset release

Figure 1.15.2 shows an internal register status immediately after reset release. Fig. 1.15.2 Internal status immediately after reset release 0016 0016 0016 0000 0016 0016 100000 0016 0016 000 00 00 000 000 0 0 0 000000 Contents of address FFFF16 000000 Address 000000 00 0 0000 (1) Port P0 direction register (P0D) Contents of address FFFE16 (2) Port P1 direction register (P1D) (4) Port P4 direction register (P4D) (5) Port P0 pull-up control register (6) Port P1–P5 pull-up control register (In the 7470/7477 group, port P1–P4 pull-up control register) (7) Edge polarity selection register (EG) (8) A-D control register (ADCON) (13) Timer FF register (TF) (14) Timer 12 mode register (T12M) (15) Timer 34 mode register (T34M) (16) Timer mode register 2 (TM2) (17) CPU mode register (CPUM) (18) Interrupt request register 1 (IR1) (19) Interrupt request register 2 (IR2) (20) Interrupt control register 1 (IE1) (21) Interrupt control register 2 (IE2) (22) Program counter (PCH ) (23) Processor status register (PS) (3) Port P2 direction register (P2D) (The 7477/7478 group is not provided.) 0016 0000 000000 (9) Serial I/O mode register (SM) (The 7477/7478 group is not provided.) (10) Serial I/O status register (SIOSTS) (The 7470/7471 group is not provided.) 0716 (13) Timer 3 (T3) (14) Timer 4 (T4) 1 1 11 FF16 : The contents are undefined at reset release. (C116)••• (C316)••• (C516)••• (C916)••• (D016)••• (D116)••• (D416)••• (D916)••• (DC 16)••• (E116)••• (E216)••• (E316)••• (F216)••• (F316)••• (F716)••• (F816)••• (F916)••• (FA16)••• (FB16)••• (FC16)••• (FD16)••• (FE16)••• (FF16)••• (11) Serial I/O control register (SIOCON) (The 7470/7471 group is not provided.) (12) UART control register (UARTCON) (The 7470/7471 group is not provided.) (PCL) Note : Since the contents of the registers and RAM not mentioned above are undefined at reset, initialize them by software. The bits are different depending on the product. Refer to the structure of each register.

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1.15.3 Notes on use

1. The timer continues to perform a count operation after reset release. 2. After the reset state is released, the microcomputer runs the program starting with the high-order address corresponding to the contents of address FFFF 16 and the low-order address corresponding to the contents of address FFFE16. 3. After the “H” level is applied to the RESET pin, only the main clock oscillates regardless of the oscillation state precedent to the reset state, so that the microcomputer starts to operate in the ordinary mode. The XCIN pin and the XCOUT pin become P50 and P51, respectively. (The 7470/7477 group is not provided with the XCIN and XCOUT pins.) 4. When the STP instruction is executed in the ordinary mode, I/O ports are held in the state just precedent to a stop of system clock oscillation. After that, the I/O ports are put into the input mode after a reset operation of the microcomputer is performed, so that they go to the high-impedance state.

1-1537470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE The 7470/7471/7477/7478 group has the following circuits to obtain clocks required for operations.

• 7470/7477 group: Main clock oscillation circuit
• 7471/7478 group: Main clock oscillation circuit and sub-clock oscillation circuit

1.16.1 Oscillation circuit

(1) Clock generating circuit The clock generating circuit controls the oscillation of the oscillation circuit and a generated clock (internal clock φ) is supplied to the CPU and peripheral units. Figure 1.16.1 shows a clock generating circuit block diagram. Fig. 1.16.1 Clock generating circuit block diagram 1/2S R Q XIN XOUT XCIN XCOUT Timer 3 count stop bit (T34M0) T34M 1 T34M 2 Internal clock f Internal system clock selection bit (CM7) Internal system clock selection bit (CM7) Main clock (XIN–XOUT ) stop bit (CM6) STP instruction WIT instruction Timer 3 Timer 4 CNTR 1 Timer 1 or timer 2 overflow signal Timer 4 count stop bit (T34M 3) Reset Interrupt disable flag I Reset Interrupt request Timer 4 count source selection bits T34M 4 T34M 5 Timer 3 count source selection bitsSTP instruction Note : The 7470/7477 group is not provided with pins XCIN and XCOUT . S R Q S R Q

7470/7471/7477/7478 GROUP USER’S MANUAL1-154 HARDWARE This oscillation circuit can stop and start oscillation. There are two oscillation circuits (the main clock only in the 7470/7477 group) as shown above. The clock obtained by dividing a signal input to the clock input pin XIN or XCIN becomes an internal clock φ+ which is used as a reference for operations. +: The internal clock φ varies with the operation modes of the microcomputer. (2) Oscillation circuit using a ceramic resonator or a crystal oscillator An oscillation circuit can be formed by connecting a ceramic resonator or a crystal oscillator between the X IN pin and the XOUT pin and between the XCIN pin and the XCOUT pin. For a circuit example, refer to “Chapter 2 Application, 2.7 Oscillation Circuit.” Please ask the oscillator maker for information on circuit constants and then set the value recommended by the maker. (3) External clock input circuit It is also possible to supply a clock to the oscillation circuit from the outside. As an external clock to be input to the X IN and XCIN pins, use a pulse signal with a duty ratio of 50 %. At this time, make the XOUT and XCOUT pins open. For a circuit example, refer to “Chapter 2 Application, 2.7 Oscillation Circuit.” Note: Because the 7470/7477 group is not provided with the XCIN and XCOUT pins, the sub-clock f(XCIN ) is not available.

1-1557470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.16.2 Sub-clock oscillation circuit

In the 7471/7478 group, the sub-clock f(XCIN ) is available when the P50/XCIN pin and the P51/XCOUT pin are used as the XCIN pin and the XCOUT pin. The power supplied to the sub-clock oscillation circuit is given through a voltage reduction regulator to reduce power dissipation in the sub-clock mode. That is, power is reduced by reducing the voltage applied to the V CC pin by the voltage reduction regulator. The supply voltage to this oscillation circuit can be set to one of the 2 stages of high power mode and low power mode in bit 5 of the CPU mode register. Notes 1: When using the sub-clock, set f(XCIN ) < 50 kHz < f(XIN)/3. 2: When using the sub-clock f(XCIN ) in the 7471/7478 group, set the P50-P53 pull-up control bit (bit 6) of the P1-P5 pull-up control register to “0” and disconnect the pull-up transistor of the P50/XCIN pin and P51/XCOUT pin. 3: When using the sub-clock as the internal clock φ, use it in one of the following states. l Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection bit of the CPU mode register to “1”). l When fixing the XCOUT drive capacity to the Low power mode (set the XCOUT drive capacity selection bit of the CPU mode register to “0”), lower the value of the resistor Rd+ in the sub- clock oscillation circuit to a level at which the oscillation of f(XCIN ) does not stop. + “Resistor Rd”: Refer to the circuit example in “Chapter 2 Application, 2.7 Oscillation circuit.”

7470/7471/7477/7478 GROUP USER’S MANUAL1-156 HARDWARE

1.16.3 Oscillation operation

(1) Oscillation operation The microcomputer is put into the ordinary mode at reset release. At this time, only the main clock oscillates and the P50/XCIN pin and the P51/XCOUT pin function as input ports P50 and P51. Notes 1: The 7470/7477 group is not provided with XCIN and XCOUT pins. 2: When using the sub-clock f(XCIN ) in the 7471/7478 group, set the P50-P53 pull-up control bit (bit 6) of the P1-P5 pull-up control register to “0” and disconnect the pull-up transistor of the 0/XCIN pin and P51/XCOUT pin.

22222 Ordinary mode

The clock resulting from dividing a signal input to the XIN pin by 2 becomes internal clock φ. Changing the mode to the low-speed mode (7471/7478 group) Execute the following procedure.

1 Set the P5

0, P51/XCIN, XCOUT selection bit (bit 4) of the CPU mode register to “1” (XCIN, XCOUT ). 2 Set the XCOUT drive capacity selection bit (bit 5) of the CPU mode register to “1” (High power). 3 Generate oscillation stabilizing wait time of f(XCIN ) by software. 4 Set the system clock selection bit (bit 7) of the CPU mode register to “1” f(XCIN ). At that time, set the XCOUT drive capacity selection bit to “0” (low power) as required.

22222 Low-speed mode (7471/7478 group)

The clock resulting from dividing a signal input to the XCIN pin by 2 becomes internal clock φ. In the low-speed mode, a low power dissipation operation can be attained by setting the main clock IN-XOUT ) stop bit (bit 6) of the CPU mode register to “1.” Changing the mode to the ordinary mode Execute the following procedure.

1 Clear the main clock (X

IN-XOUT ) stop bit (bit 6) of the CPU mode register to “0” (oscillate). 2 Generate oscillation stabilizing wait time of f(XIN) by software. 3 Clear the system clock selection bit (bit 7) of the CPU mode register to “0” f(XIN). Notes 1: Switch between the ordinary mode and the low-speed mode after the oscillation of the main clock and the sub-clock becomes stable. For the oscillation stablizing time, ask the oscillator maker for information. 2: Use the low-speed mode in one of the following states. l Fix the X COUT drive capacity to the high power mode (set the XCOUT drive capacity selection bit of the CPU mode register to “1”). l When fixing the XCOUT drive capacity to the Low power mode (clear the XCOUT drive capacity selection bit of the CPU mode register to “0”), lower the value of the resistor Rd+ in the sub- clock oscillation circuit to a level at which the oscillation of f(XCIN ) does not stop. + Resister Rd: Refer to a example of circuit in “chapter 2 application, 2.7 Oscillation circuit.” 3: When using the sub-clock especially, it takes a long time until the oscillation becomes stable. When the ordinary mode is changed to the stop mode while the sub-clock is in the oscillation state and then the ordinary mode is restored from the stop mode, the oscillation of the sub-clock is not stabilized even if the main clock becomes stable and the CPU is restored.

1-1577470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (2) Oscillation operation in the stop mode After the stop mode is provided by execution the STP instruction, all oscillation stops. After that, when the previous mode is restored from the stop mode by inputting the reset signal or generating a restoration interrupt request, the oscillation starts. For the details of the stop mode, refer to “1.17.1 Stop mode.” (3) Oscillation operation in the wait mode When the wait mode is provided by execution the WIT instruction, the internal clock φ supplied to the CPU stops. When the previous mode is restored from the wait mode by inputting the reset signal or generating an interrupt request, the supply of internal clock φ to the CPU starts. For the details of the wait mode, refer to “1.17.2 Wait mode.” (4) State transitions of internal clock Refer to “1.18 State transitions.”

7470/7471/7477/7478 GROUP USER’S MANUAL1-158 HARDWARE

1.16.4 Oscillation stabilizing time

In the oscillation circuit using a ceramic resonator or a crystal oscillator, the oscillation becomes unstable for a certain period at a start of oscillation of the oscillator. The time required for stabilization of oscillation is called oscillation stabilizing time. A proper oscillation stabilizing wait time fit for the used oscillation circuit is required. For the oscillation stabilizing time, ask the oscillator maker for information. (1) Oscillation stabilizing wait time at power on In the 7470/7471/7477/7478 group, the oscillation stabilizing wait time for 32768 counts of the X IN pin input signal is automatically generated in the period from power on to reset release. Figure 1.16.2 shows a oscillation stabilizing wait time after power on. (2) Oscillation stabilizing wait time at recovery from stop mode In the stop mode, oscillation stops. When the previous mode is restored from the stop mode by inputting a reset signal or generating an interrupt, the oscillation stabilizing wait time for 32768 counts of the X IN pin input signal or the XCIN pin input signal is automatically generated in the same way as the power on time. l At recovery by reset, f(XIN) becomes a count source that generates oscillation stabilizing wait time. l At recovery by interrupt, the count source of timer 3 set immediately before execution of the STP instruction becomes a count source that generates oscillation stabilizing wait time. Note that when f(X IN) is the system clock, the oscillation of the f(XCIN ) side may not be stabilized after the lapse of this oscillation stabilizing wait time. For the details of the stop mode, refer to “1.17.1 Stop mode.” Note: In the 7470/7477 group, f(XCIN ) is not available. Fig. 1.16.2 Oscillation stabilizing wait time after power on XIN VCC RESET 2 ms or more Internal reset Release internal reset state 2.7V ] : At f(XIN) = (2.2 VCC – 2) MHz Oscillation stabilizing wait time 32768 counts of XIN pin input signal

1-1597470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.16.5 Notes on use

1. When inputting the external clock to the XIN pin or the XCIN pin, use a pulse signal with a duty ratio of 50 % as an input signal. At this time, make the XOUT pin and the XCOUT pin open. Refer to a example of circuit in “Chapter 2 application, 2.7 Oscillation circuit.” 2. When using the sub-clock f(XCIN ) in the 7471/7478 group, set f(XCIN ) < 50 kHz < f(XIN)/3. 3. In the 7471/7478 group, switch between the ordinary mode and the low-speed mode after the oscillation of the main clock and the sub-clock becomes stable. For the oscillation stabilizing time, ask the oscillator maker for information. 4. Use the low-speed mode in one of the following states.

• Fix the XCOUT drive capacity to the high power mode (Set the XCOUT drive capacity selection bit of the CPU mode register to “1”).
• When fixing the XCOUT drive capacity to the Low-power mode (clear the XCOUT drive capacity selection bit of the CPU mode register to “0”), lower the value of the resistor Rd+ in the sub-clock oscillation circuit to a level at which the oscillation of f(XCIN ) does not stop. + Resister Rd: Refer to a example of circuit in “Chapter 2 application, 2.7 Oscillation circuit.” 5. When using the sub-clock f(XCIN ) in the 7471/7478 group, it takes a long time until the oscillation becomes stable. When the ordinary mode is changed to the stop mode while the sub-clock is in the oscillation state and then the ordinary mode is recovered from the stop mode, the oscillation of the sub-clock is not stabilized even if the main clock becomes stable and the CPU is restored. Note: In the 7470/7477 group, the sub-clock f(X CIN ) is not available because neither XCIN pin nor XCOUT pin is provided.

7470/7471/7477/7478 GROUP USER’S MANUAL1-160 HARDWARE

1.17 Low-power dissipation function

The 7470/7471/7477/7478 group is provided with a function to put the CPU into a wait state with low-power dissipation by stopping the CPU operation by softoware. The low-power dissipation function has the following 2 modes. l Stop mode by a STP instruction l Wait mode by a WIT instruction Figure 1.17.1 shows the operation states of the microcomputer at low-power dissipation and Figure 1.17.2 shows a state transition. Fig. 1.17.1 Operation states of the microcomputer at low-power dissipation CPU Timer A-D converter Serial I/O External interrupt Peripheral device Stop Stop OperatingStop OperatingOperating STP mode Oscillation stops WIT mode Oscillation is operating Note :When using an external clock, timer and serial I/O are operating.

1-1617470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.17.2 State transition at low-power dissipation STP mode Reset Interrupt Reset release (Program execution from reset vector) Proceed to the next address of the STP or WIT instruction (Program is continued) Registers except timers 3, 4 and RAM are held. Oscillation stabilizing wait time: 32768 counts of the specified count source are counted WIT mode InterruptReset No oscillation stabilizing wait time Oscillation stabilizing wait time : f(XIN)/16 is counted Interrupt processing Registers and RAM are held. Only RAM is held and the other registers are reset.

7470/7471/7477/7478 GROUP USER’S MANUAL1-162 HARDWARE

1.17.1 Stop mode

To switch to the stop mode, execute the STP instruction. In the stop mode, the oscillation of both f(XIN) and f(XCIN ) stops and the internal clock φ stops. Accordingly, the CPU stops and the peripheral units also stop. This leads to a reduction of power dissipation. Note: In the 7470/7477 group, the f(XCIN ) is not available. (1) State of stop mode Table 1.17.1 shows a state of stop mode. Note: When the STP instruction is executed, “FF16” and “0716” are automatically set in timer 3 and timer 4, respectively. Table 1.17.1 State of stop mode State of stop mode Stop Stop State at execution STP instruction is held. When internal count source selected : Stop When external count source selected : Operate Internal clock mode: Stop External clock mode: Operate Held Held (except timer3, timer4) Held + CPU register : The following 6 registers are incorporated in the CPU.

• Accumulator
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register Item Oscillation CPU I/O port P0 to P5 Timer Serial I/O RAM SFR CPU register

1-1637470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.17.3 oscillation stabilizing wait time at recovery from stop mode by reset input (2) Releasion of stop mode The stop mode is released by inputting a reset signal or generating an interrupt request. There is a difference in restore processing from the stop mode between the use of reset input and the use of interrupt.

22222 Recovery by reset input

The microcomputer is reset by applying the "L" level to the RESET pin for 2 s or more in the stop mode, thereby releasing the stop mode. After the stop mode is released, oscillator starts. (At this time, the inside is in the reset state.) The reset state is released after 32768 counts of the X IN pin input after the “H” level is applied to the RESET pin. At a start of oscillation of the oscillator, the oscillation is unstable. It takes time before stabilization of oscillation (oscillation stabilizing time). The oscillation stabilizing wait time is secured by the time for holding this internal reset state. For the details of the reset, Refer to “1.15 Reset.” Note: When the stop mode is released, the contents of the RAM before reset are held. However, the contents of the CPU register and the SFR cannot be held but are reset. Figure 1.17.3 shows the oscillation stabilizing wait time at recovery from stop mode by reset input. RESET XIN VCC Execute STP instruction Recovered by reset input Stop mode 2 ms or more (Note) Note: No waveform may be input to X (in low-speed mode). Undefined XIN: in high-impedance state XOUT : “H” IN Oscillation stabilizing wait time : 32768 counts of XIN pin input signal

7470/7471/7477/7478 GROUP USER’S MANUAL1-164 HARDWARE

22222 Recovery by interrupt

When an interrupt request is generated in the stop mode, this stop mode is released and oscillation is started. The interrupt sources that are available for recovery are shown below. l INT0, INT1 l CNTR 0, CNTR 1 l Serial I/O at using external clock l Timer (timer 1, timer 2) at using external clock l Key input (key on wake up) However, when the above interrupt sources are used for recovery from the stop mode, perform the following setting and then execute the STP instruction to permit an interrupt to be used. [Register setting] 1 Clear the interrupt enable bit of timer 3 and timer 4 to “0.” (Disabled) 2 Set the count stop bit of timer 3 and timer 4 to “1.” (Stop)

3 Select a count source of timer 3 in consideration of the oscillation stabilizing time of the

oscillator. Note: Re-set the previous count source at recovery. 4 Clear the interrupt request bit of the interrupt source to be used for recovery to “0.” 5 Set the interrupt enable bit of the interrupt source to be used for recovery to “1.”(Enabled) 6 Clear the count stop bit of timer 3 and timer 4 to “0.” (Count starts) 7 When using the sub-clock, set the XCOUT drive capacity to high power. (Refer to “1.16.2 Sub- clock oscillation circuit.”) 8 Clear the interrupt disable flag I to “0.” (Enabled) Note: In the stop mode, A-D conversion operation stops. Accordingly, execute the STP instruction after termination of the A-D conversion. For the details of the Interrupt, refer to “1.11 Interrupts.” At a start of oscillation of the oscillator, the oscillation is unstable. It takes time before stabilization of oscillation (oscillation stabilizing time). At recovery by interrupt, the waiting time for the supply of internal clock φ to the CPU by timer 3 and timer 4+1 is automatically generated+2. The oscillation stabilizing time of the system clock side is secured by this waiting time. Figure 1.17.4 shows an example of restoration sequence from the stop mode by the INT 0 interrupt. +1: When the STP instruction is executed, “FF16” and “0716” are automatically set in the counter and latch of timer 3 and the counter and latch of timer 4, respectively. +2: The count source is supplied to timer 3 immediately after a start of oscillation, thereby starting a count operation. The supply of internal clock φ to the CPU is started when timer 4 overflows.

1-1657470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.17.4 Example of recovery sequence from stop mode by INT0 interrupt INT0 interrupt request bit INT0 pin XIN or XCIN “FF16” Timer 3 Peripheral device CPU Stop mode Timer 4 “0716”

• INT0 interrupt signal input (INT0 interrupt request occurs)
• Oscillation start
• Timer 3 count start
• STP instruction execution Stop Operating Stop Operating Oscillation stabilizing wait time 2048 counts of timer 3 count source (Note) Operating Count down l When recovering from stop mode by using INT interrupt (rising edge selected)
• Timer 4 overflow
• Start supplying internal clock f to CPU
• Accept INT0 interrupt request Note: The count source is a count source of timer 3 before execution of the instruction. STP Operating Undefined XIN, XCIN ; in high-impedance stat XOUT ; “H”

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1.17.2 Wait mode

To switch to the wait mode, execute the WIT instruction. In the wait mode, oscillation is continued but the internal clock φ stops. Accordingly, the CPU stops but the peripheral units operate since oscillation is continued. (1) State of wait mode Table 1.17.2 shows a state of wait mode. Table 1.17.2 State of wait mode State of wait mode Operate Stop State at execution WIT instruc- tion is held. Operate Operate Held Held Held Item Oscillation CPU I/O port P0 to P5 Timer Serial I/O RAM SFR CPU register ] CPU register : The following 6 registers are incorporated in the CPU.

• Accumulator
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register

1-1677470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (2) Releasion of wait mode The wait mode is released by inputting a reset signal or generating an interrupt request. There is a difference in restore processing from the wait mode between the use of reset input and the use of interrupt. n Recovery by reset input The microcomputer is reset by applying the “L” level to the RESET pin for 2 s or more in the wait mode, thereby releasing the wait mode. After the wait mode is released by inputting the reset signal, the supply of internal clock φ to the CPU is started. The reset state is released after 32768 counts of the X IN pin input signal after the “H” level is applied to the RESET pin. For the details of the reset, refer to “1.15 Reset.” Note: When the wait mode is released, the contents of the RAM before reset are held. However, the contents of the CPU register and the SFR cannot be held but are reset. Figure 1.17.5 shows the reset input time. Fig. 1.17.5 Reset input time RESET XIN VCC Execute WIT instruction Recovered by reset input Wait mode 2 µs or more (Note) Note: No waveform may be input to X (in low-speed mode).IN Oscillation stabilizing wait time : 32768 counts of XIN pin input signal

7470/7471/7477/7478 GROUP USER’S MANUAL1-168 HARDWARE In the wait mode, oscillation is continued. Accordingly, as soon as the wait mode is released, an instruction is executed. When an interrupt request is generated in the wait mode, this wait mode is released and the supply of internal clock φ to the CPU is started. At the same time, the interrupt request used for recovery is accepted, so that the interrupt processing routine is executed. The interrupt sources that are available for recovery are shown below. l INT 0, INT1 l CNTR 0, CNTR 1 l Serial I/O l A-D conversion l Timer 1 to timer 4 l Key input (key on wake up) However, when the above interrupt sources are used for recovery from the wait mode, perform the following setting and then execute the WIT instruction to permit an interrupt to be used. [Register setting] 1 Clear the interrupt request bit of the interrupt source to be used for recovery to “0.”(No request) 2 Set the interrupt enable bit of the interrupt source to be used for recovery to “1.”(Enabled) 3 Clear the interrupt disable flag I to “0.” (Enabled) For the details of the Interrupt, refer to “1.11 Interrupts.”

1-1697470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.17.3 Notes on use

[Notes on use of the stop mode]

22222 Clock after recovery

After recovery from the stop mode by interrupt, the contents of the CPU mode register before execution of the STP instruction are held. Accordingly, if both f(XIN) and f(XCIN ) were oscillating before execution of the STP instruction, the oscillation of both f(XIN) and f(XCIN ) is restarted after recovery by interrupt. In the above case, if f(X IN) is set as the system clock, the oscillation stabilizing wait time for 32768 counts of the XIN pin input signal is secured at recovery from the stop mode. Note that the f(XCIN ) clock may not be stabilized even after the lapse of the f(XIN) oscillation stabilizing wait time. Note: In the 7470/7477 group, the f(XCIN ) is not available.

22222 Interrupt processing after recovery

After recovery from the stop mode, the interrupt request bit of timer 3 and timer 4 is “1.” Clear it to “0” if necessary. The interrupt request bit of timer 1 and timer 2 may also be set to “1.” Clear it to “0” as required.

7470/7471/7477/7478 GROUP USER’S MANUAL1-170 HARDWARE Fig. 1.17.6 Structure of CPU mode register

1.17.4 Related register

(1) CPU mode register (Address 00FB 16) The CPU mode register consists of a stack page selection bit+1 and system clock control bits+2. +1: In series having a RAM capacity of 192 bytes or less, this bit is not used because no RAM is located on page 1. (Be sure to set this bit to “0.”) +2: In the 7470/7477 group, which is not provided with a sub-clock generating circuit, this bit is not used. (Be sure to set this bit to “0.”) Figure 1.17.6 shows a structure of CPU mode register. b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address B At reset R W CPU mode register 0, 1 ? 5 Name Function Fix these bits to “0.” Nothing is allocated for this bit. This is write enabled bit and is undefined at reading. Main clock (XIN–XOUT ) stop bit XCOUT drive capacity selection bit 0Stack page selection bit Internal system clock selection bit 0: In page 0 area 1: In page 1 area (Note 1) 0: Low 1: High (Note 2) 0: Oscillates 1: Stops (Note 2) 0: X IN–XOUT selected (Ordinary mode) 1: XCIN–XCOUT selected (Low speed mode) (Note 2) P50, P51/XCIN,XCOUT selection bit 0: P50, P51 1: XCIN, XCOUT (Note 2) Notes 1: In the products having a RAM capacity of 192 bytes or less, set this bit to “0.” Since the 7470/7477 group is not provided with the sub-clock generating circuit, f(X Fix these bits to “0.” 00FB 16] CIN) cannot be used.

1-1717470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE The operation modes of the 7470/7471/7477/7478 group are classified as follows. l Reset l Oridinary mode l Low-speed mode (7471/7478 group) l Sub-clock mode (7471/7478 group) l Stop mode l Wait mode Figure 1.18.1 shows a state transitions.

7470/7471/7477/7478 GROUP USER’S MANUAL1-172 HARDWARE Fig. 1.18.1 State transitions Ordinary mode State A CPUM 0 0 Reset CPUM 0 1 CPUM 1 CPUM 1 f(XIN): Stopped f(XCIN): Stopped Internal clock f: Stopped b7 b6 b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 (Note 2) (Note 3) STP instruction Interrupt (Note 1) 0 — Stop mode State F f(XIN): Oscillating f(XCIN): Stopped Internal clock f: f(XIN)/2f(XIN): Oscillating f(XCIN): Stopped Internal clock f: Stopped Wait mode State E WIT instruction Interrupt f(XIN): Oscillating f(XCIN): Oscillating Internal clock f: Stopped WIT instruction Interrupt WIT instruction Interrupt f(XIN): Oscillating f(XCIN): Oscillating Internal clock f: Stopped f(XIN): Stopped f(XCIN): Oscillating Internal clock f: Stopped Sub-clock mode State G WIT instruction Interrupt Ordinary mode State B f(XIN): Oscillating f(XCIN): Oscillating Internal clock f: f(XIN)/2 Low-speed mode State C (Note 3) (Note 4) f(XIN): Oscillating f(XCIN): Oscillating Internal clock f: f(XCIN)/2 Low-speed mode State D(Note 4) f(XIN): Stopped f(XCIN): Oscillating Internal clock f: f(XCIN)/2 STP instruction Interrupt (Note 1) STP instruction Interrupt (Note 1) STP instruction Interrupt (Note 1) f(XIN): Stopped f(XCIN): Stopped Internal clock f: Stopped f(XIN): Stopped f(XCIN): Stopped Internal clock f: Stopped f(XIN): Stopped f(XCIN): Stopped Internal clock f: Stopped

1-1737470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Notes 1: When changing from the stop mode to another mode, oscillation stabilizing wait time is generated automatically by connecting timer 3 and timer 4. 2: In the 7471/7478 group, where oscillating the stopped clock and switching the system clock, it is necessary to wait at software until oscillation is stabilized. At this time, set the bit 5 of the CPU mode register to “1” and set the XCOUT drive capacity to the high power mode. After the oscil- lation of sub-clock f(XCIN ) becomes stable, clear the bit to “0” (low power mode) as required. 3: In the 7471/7478 group, when returning from the low-speed mode to the ordinary mode, use the main clock f(XIN) as a count source of the internal clock φ (state B). After that, clear bit 4 of the CPU mode register to “0” to stop the oscillation of f(XCIN ) if necessary. 4: When using the low-speed mode in the 7471/7478 group, use it in one of the following states. l Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection bit of the CPU register to “1.”) l When fixing the XCOUT drive capacity to the low power mode (clear the XCOUT drive capacity selection bit of the CPU mode register to “0”), lower the value of the resistor Rd+ in the sub- clock oscillation circuit to a level at which the oscillation of f(XCIN ) does not stop. + “Resistor Rd”:Refer to the circuit example in “Chapter 2 Application, 2.7 Oscillation circuit.”

7470/7471/7477/7478 GROUP USER’S MANUAL1-174 HARDWARE n Reset → Ordinary mode (State A) Immediately after reset, the main clock divided by 2 (f(XIN)/2) is selected as an internal clock φ and the I/O pins XCIN and XCOUT of the sub-clock f(XCIN ) become ordinary ports. “FF16” and “0716” are set in timer 3 and timer 4 respectively, and also the main clock divided by 16 (f(XIN)/16) is selected as a count source of timer 3 and the overflow signal of timer 3 is selected as a count source of timer 4. Then a down-count is started. When timer 4 overflows, the internal reset is released and the program starts from the address specified by reset vector. n Low-speed mode (Stae C and state D) To the low-speed mode (state C and state D) using the sub-clock divided by 2 (f(X CIN )/2) as an internal clock φ, a transition is made by way of the ordinary mode (state A) state B ( state C). In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not provided. n Wait mode (State E) In this mode, all the states of registers, I/O ports and internal RAMs are held. The internal clock φ stops at “H” but the oscillator does not stop. From any of state A, state B, state C and state D, a return is made to the wait mode by executing the WIT instruction. When a return is made from the state D to the wait mode, the sub-clock mode in which only the timer function operates is provided. (In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, the sub-clock mode is not provided.) Refer to “1.17.2 Wait mode.” n Stop mode (State F) In this mode, all the states of registers, I/O ports and internal RAMs except timer 3 and timer 4 are held and the oscillation of both main sub-clock is stopped. From any of state A, B, C and D, a return is made to the stop mode by executing the STP instruction. Refer to “1.17.1 Stop mode.” n Sub-clock mode (State G) Only the clock-function is made to operate by sub-clock mode at low-power dissipation. The sub-clock mode (state G) is provided by executing the WIT instruction in the low-speed mode (state D), and restoration from this state to the low-speed mode is attached by each interrupt. In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not provided.

1-1757470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE I/O ports: 20 Input ports: 16 (Including 8 analog input pins.) 32P2W-A 42P4B 56P6N-A 42P4B 56P6N-A 42P4B 56P6N-A 42S1B-A In contrast with the mask ROM version, a microcomputer incorporating a programmable ROM is called built-in PROM version. There are two types of built-in PROM version as shown below. l One Time PROM version Writing to the built-in PROM can be performed only once. Neither erase nor rewrite operations are enabled. l Built-in EPROM version The built-in EPROM version is a programmable microcomputer with window and can perform write, erase, and rewrite operations. The built-in PROM version has the EPROM mode for writing to the built-in PROM in addition to the same functions as those of the mask ROM version. For an outline of performance, a pin configuration and a functional block diagram of the built-in PROM version, refer to “1.3 Performance overview” , “1.4 Pin configuration”, and “1.6 Functional block diagram” , respectively. The 7470/7471/7477/7478 group supports the built-in PROM versions shown in Table 1.19.1. Product name (P)ROM size (bytes) RAM size (bytes) I/O Ports Package Remarks Table 1.19.1 7470/7471/7477/7478 group built-in PROM version supporting products 384 EPROM version 8192 192 16384 One Time PROM version M37470E8-XXXSP 16384 384 M37470E4-XXXSP 8192 192 One Time PROM version I/O ports: 28 (Including 8 analog input pins.) Input ports: 8 I/O ports: 22 (Including 4 analog input pins.) Input ports: 4 32P4B M37471E4-XXXSP M37471E4-XXXFP M37471E8-XXXSP M37471E8-XXXFP M37471E8SS 384 I/O ports: 18 Input ports: 8 (Including 4 analog input pins.) M37477E8-XXXSP M37477E8-XXXFP 32P4B

16384 One Time PROM version

(As of Dec. 1997) EPROM version

7470/7471/7477/7478 GROUP USER’S MANUAL1-176 HARDWARE

1.19.1 EPROM mode

The built-in PROM version has the EPROM mode in addition to the same operation modes as those of the mask ROM version. The EPROM mode permits writing to the built-in PROM and reading from the built- in PROM. To the built-in PROM, writing, reading and erasing can be performed by the same operations as those of the M5M27C256K. EPROM mode. Table 1.19.2 Pin functions in EPROM mode Built-in PROM version V CC P33 V SS P1 1 to P17, P20 to P23, P3 0, P31, P40, P41 P0 0 to P07 V REF P32 M5M27C256K V CC V PP V SS A 0 to A14 D 0 to D7 CE OE Pin name Fig. 1.19.1 Pin connection in EPROM mode of 7470 group P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37470E4-XXXSP M37470E8-XXXSP P17/SRDY RESET Outline 32P4B A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS : Same functions as M5M27C256K (TOP VIEW)

1-1777470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.19.2 Pin connection in EPROM mode of 7471 group (1) P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 M37471E4-XXXSP M37471E8-XXXSP M37471E8SS P30/INT0 P51/XCOUT P50/XCIN VCC P20/IN0 VREF XIN XOUT VSS P17/SRDY RESET Outline 42P4B (Note) 42S1B-A (M37471E8SS) A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS : Same functions as M5M27C256K (TOP VIEW) Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.

7470/7471/7477/7478 GROUP USER’S MANUAL1-178 HARDWARE Fig. 1.19.3 Pin connection in EPROM mode of 7471 group (2) P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P30/INT0 P20/IN0 VREF VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/SRDY RESET NC NC NC NCNC NC M37471E4-XXXFP M37471E8-XXXFP Outline 56P6N-A (Note) D 5 D 6 D 7 VSS A10 VCC VSS D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 OE CE VSS : Same functions as M5M27C256K (TOP VIEW) Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin. NC: No connection

1-1797470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.19.4 Pin connection in EPROM mode of 7477 group P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37477E8-XXXSP P17/SRDY RESET P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37477E8-XXXFP P17/SRDY RESET Outline 32P2W-A (Note) A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS (TOP VIEW) : Same functions as M5M27C256K Note: The only difference between the 32P2W-A package product and the 32P4B package product are package shape, absolute maximum ratings. Outline 32P4B (Note)

7470/7471/7477/7478 GROUP USER’S MANUAL1-180 HARDWARE Fig. 1.19.5 Pin connection in EPROM mode of 7478 group (1) P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 M37478E8-XXXSP M37478E8SS P30/INT0 P51/XCOUT P50/XCIN VCC P20/IN0 VREF XIN XOUT VSS P17/SRDY RESET A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS : Same functions as M5M27C256K (TOP VIEW) Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin. NC: No connection Outline 42P4B (Note) 42S1B-A (M37478E8SS)

1-1817470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.19.6 Pin connection in EPROM mode of 7478 group (2) P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P30/INT0 P20/IN0 VREF VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/SRDY RESET NC NC NC NCNC NC M37478E8-XXXFP D 5 D 6 D 7 VSS A10 VCC VSS D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 OE CE VSS : Same functions as M5M27C256K (TOP VIEW) Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin. NC: No connection Outline 56P6N-A (Note)

7470/7471/7477/7478 GROUP USER’S MANUAL1-182 HARDWARE 0–D 7 Functions

• Apply the following voltage to the VCC pin: 2.7 V to 4.5 V (at f(XIN) = (2.2 VCC –2) MHz) or 4.5 V to 5.5 V (at f(XIN) = 8 MHz).
• Apply 0 V to the VSS pin.
• Ground level input pin for the A-D converter.
• Apply the same voltage as the VSS pin to the AV SS pin. Note:This pin is dedicated to 56P6N-A package products among the 7471/7478 group.
• Reference voltage input pin for the A-D con- verter.
• When using the A-D converter, apply 0.5 VCC (Q2) to VCC [V].
• When not using the A-D converter, connect to V CC . V REF works as CE input.
• Reset input pin
• The microcomputer is put into a reset state by keeping the RESET pin at “L” for 2 ms or more, and the reset state is released by returning the RESET pin to “H.”
• Connect to the VSS pin.
• An input pin and an output pin for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crys- tal oscillator between pins XIN and XOUT .
• A feedback resistor is incorporated between the X IN and the XOUT pins.
• To use an external clock input, connect the clock oscillation source to the XIN pin and leave the XOUT pin open.
• Port P0 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, a pull-up transistor is connect- able in units of one bit.
• In input mode, a key-on wake up function is provided.
• Port P0 works as data I/O (D 0 – D7) Mode Ordinary /EPROM Ordinary /EPROM Ordinary EPROM Ordinary EPROM Ordinary /EPROM Ordinary /EPROM Ordinary EPROM

1.19.2 Pin description

Table 1.19.3 to Table 1.19.5 show the description of pin functions in the ordinary mode and the EPROM mode. Table 1.19.3 Pin description (1) Pin V CC , VSS AV SS V REF RESET X IN X OUT P0 0–P0 7

1-1837470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE A 4–A 10 I/O port P2 (7470/7471 group) Input port P2 (7477/7478 group) Address input A 0–A 3 Functions

• Port P1 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be con- nected in units of 4-bit.
• Pins P1 2 and P1 3 are in common with timer output pins T0, T1 respectively.
• In the case of the 7470/7471 group, P14 – P17 are in common with serial I/O pins SIN, SOUT , CLK, SRDY respectively.
• In the case of the 7470/7471 group, the out- puts of pins SOUT and the SRDY can be N-channel open drain outputs.
• In the case of the 7477/7478 group, pins P1 4 – P17 are in common with serial I/O pins R XD, TXD, SCLK , S RDY, respectively.
• The P11–P1 7 pins are address (A4 – A10) input pins. Put P10 into the open state.
• Port P2 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be con- nected in units of 4-bit.
• Pins P2 0–P2 7 are in common with analog input pins IN0–IN7 respectively. Note: The 7470 group has only the 4 pins 0–P2 3 (IN0–IN3).
• Port P2 is an 8-bit input port.
• It is impossible to connect a pull-up transistor.
• Pins P2 0–P2 7 are in common with analog input pins IN0–IN7 respectively. Note: The 7477 group has only the 4 pins 0–P2 3 (IN0–IN3) are available.
• The P20 to P23 pins are address (A0–A3) input pins.
• In the case of the 7471/7478 group, put the P2 4–P2 7 pins into the open state. Mode Ordinary EPROM Ordinary EPROM Table 1.19.4 Pin description (2) Pin P1 0–P1 7 P2 0–P2 7

7470/7471/7477/7478 GROUP USER’S MANUAL1-184 HARDWARE A 11, A12 Mode input V PP input I/O port P4 Address input A 13, A14 Input port P5 Input port P5 Functions

• Port P3 is a 4-bit input port.
• Pins P30, P31 are in common with external in- terrupt input pins INT0, INT1 respectively.
• Pins P32, P33 are in common with timer input pins CNTR 0, CNTR 1 respectively.
• The P30 and P3 1 pins are the address (A11, A 12) input pins. The P3 2 pin becomes an OE input pin.
• The P33 pin is a VPP input pin and VPP is applied to it when the VPP is input and the program is verified.
• Port P4 is a 4-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be con- nected in units of 4-bit. Note: The 7470/7477 group has only 2 pins P4 and P4 1.
• The P40 to P41 pins are the address (A13, A14) input pins.
• In the case of the 7471/7478 group, put the P4 2 and P43 pins into the open state.
• Port P5 is a 4-bit input port.
• Pull-up transistor can be connected in units of 4-bit.
• Pins P5 0, P51 are in common with input/output pins for sub-clock generating circuit XCIN, XCOUT respectively.
• When using pins P50 and P5 1 as pins XCIN and XCOUT , connect a quartz-crystal oscillator between pins XCIN and XCOUT .
• When using pins P50 and P5 1 as pins XCIN and X COUT , a feedback resistor is connected between pins XCIN and XCOUT .
• To use an external clock input, connect the clock oscillation source to the XCIN pin and leave the XCOUT pin open. Note: Only the 7471/7478 group has pins P50 to P53.
• Put this port into the open state. Mode Ordinary EPROM Ordinary EPROM Ordinary EPROM Table 1.19.5 Pin description (3) Pin P3 0–P3 3 P4 0–P4 3 P5 0–P5 3

1-1857470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Note: VIL denotes an “L” input voltage and VIH denotes an “H” input voltage. CE V IL V IL V IL V IH V IH Mode

1.19.3 Writing, reading, and erasing to built-in PROM

The built-in PROM version is put into the EPROM mode by applying the “L” level to the RESET pin. Write, read and erase operations to the built-in PROM in the EPROM mode are described below. Table 1.19.6 shows input signals in each mode. (1) Reading l Apply 0 V to the RESET pin and 5 V to the VCC pin. l When an address signal (A0-A14) is input and the CE pin and the OE pin are caused to go “L”, the contents of the PROM appear to data I/O pins (D0-D7). l The data I/O pins (D0-D7) are put into a floating when either the CE pin or the OE pin is in the “H” state. (2) Writing l Apply 0 V to the RESET pin and 5 V to the VCC pin. l When the OE pin is caused to go to “H” and VPP is applied to the VPP pin, the program mode is provided. l Set an address to the address input pins (A0-A14) and give write data to the data I/O pins (D0-D7) in parallel. l In the above condition, a write operation is performed by causing the CE pin to go to “L”. When using a PROM programmer, specify an address into the following area. l Address 600016 to address 7FFF16 (for the M3747xE4) l Address 400016 to address 7FFF16 (for the M3747xE8) (3) Erasing l An erase operation is enabled only in the built-in EPROM version with window (M37471E8SS/ M37478E8SS). l Data can be erased by irradiating ultraviolet rays having a wave length of 2537Å. l The minimum amount of irradiation required for an erase operation is 15 W•s/cm2. Table 1.19.6 Input/Output signal on each mode

7470/7471/7477/7478 GROUP USER’S MANUAL1-186 HARDWARE

1.19.4 Notes on use

The notes on using the built-in PROM version are shown below. (1) All built-in PROM version products n Precautions at write operation l Be careful not to apply an overvoltage to pins because a high voltage is used for a write operation. Exercise special care when turning on the power supply. l For writing the contents of the PROM, use a dedicated programming adapter. This permits using a general-purpose PROM programmer for writing data. For details of dedicated programming adapters, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data book. n Precautions at read operation l When reading the contents of the PROM, use a dedicated programming adapter, so that reading can be performed by a general-purpose PROM programmer. For details of dedicated programming adapters, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data book.

1-1877470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (2) One Time PROM version n Precautions before use l The PROM of the One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 1.19.7 is recommended to verify programming. Fig. 1.19.7 Programming and testing of One Time PROM version (3) Built-in EPROM version n Precautions on erasing l Sunlight and fluorescent light include light that may erase the information written in the built-in PROM. When using the built-in EPROM version in the read mode, be sure to cover the transparent glass portion with a seal. l This seal to cover the transparent glass portion is prepared on our side. Be careful not to bring the seal into contact with the microcomputer lead wires when covering the portion with the seal because this seal is made of metal (aluminum). l Before erasing data, clean the transparent glass. If any finger stain or seal adhesive is stuck to the transparent glass, this prevents ultraviolet rays from passing, thereby affecting the erase characteristic adversely. Programming with PROM programmer Screening (Caution) (Leave at 150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 Hours.

1.20 Electrical characteristics

7470/7471/7477/7478 GROUP USER’S MANUAL

1.20.1 Electrical characteristics

(1) 7470 group electrical characteristics recommended operating conditions. Table 1.20.3 shows the electrical characteristics. Table 1.20.4 shows the A-D converter characteristics. Table 1.20.1 Absolute maximum ratings (7470 group) Unit V V V mW Symbol V CC V I V O Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Ratings –0.3 to +7 –0.3 to V CC +0.3 –0.3 to VCC +0.3 1000 –20 to +85 –40 to +150 Conditions All voltages are based on V SS . Output transistors are cut-off. Ta = 25 °C Table 1.20.2 Recommended operating conditions (7470 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Symbol Parameter Unit Limits Max.Typ.Min. 4.5 2.7 0.8VCC 0.7VCC 0.8VCC V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz 5.5 4.5 V CC V CC V CC 0.2VCC 0.25VCC 0.16VCC 0.12VCC –30 –30 –10 2.2VCC –2.0 5.0 Power source voltage f(XIN) = 8.0 MHz f(XIN) = (2.2VCC –2.0 )MHz Power source voltage “H” input voltage P0 0 to P07, P10 to P17, P30 to P33 “H” input voltage P20 to P23, P40, P41_______ “H” input voltage XIN, RESET “L” input voltage P00 to P07, P10 to P17, P30 to P33 “L” input voltage P20 to P23, P40, P41 “L” input voltage RESET “H” sum output current of P00 to P07 and P40 and P41 “H” sum output current of P10 to P17 and P20 to P23 “L” sum output current of P00 to P07, P40 and P41 “L” sum output current of P10 to P17 and P20 to P23 “H” peak output current 0 to P07, P10 to P17, P20 to P23, P40, P41 “L” peak output current 0 to P07, P10 to P17, P20 to P23, P40, P41 “H” average output current 0 to P07, P10 to P17, P20 to P23, P40, P41 (Note 1) “L” average output current 0 to P07, P10 to P17, P20 to P23, P40, P41 (Note 1) Notes 1: The average output current IOH (avg) or IOL (avg) are the average value during a 100 ms. 2: The oscillation frequency is at 50 % duty cycle. V CC V SS V IH V IH V IH V IL V IL V IL V IL IOH (sum) IOH (sum) IOL (sum) IOL (sum) IOH (peak) IOL (peak) IOH (avg) IOL (avg) f(CNTR) f(CLK) f(XIN) f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz V CC = 4.5 V to 5.5 V V CC = 2.7 V to 4.5 V Timer input frequency CNTR 0 (P32), CNTR 1 (P33) (Note 2) Serial I/O clock input frequency CLK (P1 6) (Note 2) Clock input oscillation frequency (Note 2)

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Table 1.20.3 Electrical characteristics (7470 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. V OH V OL V T+ – VT– V T+ – VT– V T+ – VT– IIL IIL IIL IIL IIH IIH IIH IIH ICC V RAM Test conditions “H” output voltage P0 0 to P07, P10 to P17 P2 0 to P23, P40, P41 “L” output voltage 0 to P07, P10 to P17 P2 0 to P23, P40, P41 Hysteresis P00 to P07 P3 0 to P33 Hysteresis RESET Hysteresis P14/SIN P1 6/CLK “L” input current 0 to P07, P10 to P17, P4 0, P41 “L” input current P30 to P33 “L” input current 0 to P23 X IN, RESET “H” input current 0 to P07, P10 to P17, P4 0, P41 “H” input current P30 to P33 “H” input current 0 to P23 X IN, RESET Power source current RAM retention voltage Use as S IN or CLK V I = 0 V Not use pull-up transistor V I = 0 V Use pull-up transistor V I = 0 V V I = 0 V, not use pull-up tran- sistor, not use as analog input V I = 0 V, use pull-up transistor, not use as analog input V I = 0 V X IN is at stop mode V I = VCC Not use pull-up transistor V I = VCC V I = VCC , not use pull-up tran- sistor, not use as analog input V I = VCC X IN is at stop mode V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V Ta = 25 °C Ta = 85 °C V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V, IOH = –5 mA V CC = 3 V, IOH = –1.5 mA V CC = 5 V, IOL = 10 mA V CC = 3 V, IOL = 3 mA 3.0 2.0 –0.25 –0.08 –0.25 –0.08 2.0 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 2.0 1.0 –1.0 –0.35 –1.0 –0.35 3.6 5.5 V V V V V V V V V V µA µA mA mA µA µA µA µA mA mA µA µA µA µA µA µA µA µA µA µA mA mA mA mA mA mA mA mA mA µA µA V f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz At system op- eration, A-D conversion is not executed At system op- eration, A-D conversion is executed At stop mode VCC = 5 V Stop all oscillation At wait mode

7470/7471/7477/7478 GROUP USER’S MANUAL Table 1.20.4 A-D converter characteristics (7470 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, f(XIN) = 4 MHz, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. bits LSB LSB LSB LSB LSB LSB µs µs V kΩ V ±0.9 12.5 V CC V REF Test conditions Resolution Non-linearity error Differential non-linearity error Zero transition error Full scale transition error Conversion time Reference input voltage Ladder resistance value Analog supply voltage VCC = VREF = 5.12 V, IOL (sum) = 0 mA VCC = VREF = 3.072 V, IOL (sum) = 0 mA V CC = VREF = 5.12 V V CC = VREF = 3.072 V 0.5VCC (Note) V OT V FST TCONV V REF R LADDER V IA f(XIN) = 8 MHz f(XIN) = 4 MHz Note: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect it to VCC .

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz V CC = 4.5 V to 5.5 V V CC = 2.7 V to 4.5 V (2) 7471 group electrical characteristics recommended operating conditions. Table 1.20.7 shows the electrical characteristics. Table 1.20.8 shows the A-D converter characteristics. Table 1.20.5 Absolute maximum ratings (7471 group) Unit V V V mW Symbol V CC V I V O Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Ratings –0.3 to +7 –0.3 to V CC +0.3 –0.3 to VCC +0.3 1000 (Note) –20 to +85 –40 to +150 Conditions All voltages are based on V SS . Output transistors are cut-off. Ta = 25 °C Symbol Parameter Unit Limits Max.Typ.Min. 4.5 2.7 0.8VCC 0.7VCC 0.8VCC V V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz kHz 5.5 4.5 V CC V CC V CC 0.2VCC 0.25VCC 0.16VCC 0.12VCC –30 –30 –10 2.2VCC –2.0 5.0 Power source voltage f(X IN) = 8.0 MHz f(XIN) = (2.2VCC –2.0) MHz Power source voltage Analog supply voltage “H” input voltage P0 0 to P07, P10 to P17, P30 to P33 “H” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1)_______ “H” input voltage XIN, RESET “L” input voltage P00 to P07, P10 to P17, P30 to P33 “L” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1) “L” input voltage RESET “H” sum output current of P00 to P07 and P40 to P43 “H” sum output current of P10 to P17 and P20 to P27 “L” sum output current of P00 to P07 and P40 to P43 “L” sum output current of P10 to P17 and P20 to P27 “H” peak output current 0 to P07, P10 to P17, P20 to P27, P40 to P43 “L” peak output current 0 to P07, P10 to P17, P20 to P27, P40 to P43 “H” average output current 0 to P07, P10 to P17, P20 to P27, P40 to P43 (Note 2) “L” average output current 0 to P07, P10 to P17, P20 to P27, P40 to P43 (Note 2) V CC V SS AV SS V IH V IH V IH V IL V IL V IL V IL IOH (sum) IOH (sum) IOL (sum) IOL (sum) IOH (peak) IOL (peak) IOH (avg) IOL (avg) f(CNTR) f(CLK) f(XIN) f(XCIN ) Note: The rating is 500 mW for the 56P6N-A package product. Table 1.20.6 Recommended operating conditions (7471 group) (VCC = 2.7 V to 5.5 V, VSS = AV SS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Timer input frequency CNTR 0 (P32) CNTR 1 (P33) (Note 3) Serial I/O clock input frequency CLK (P1 6) (Note 3) Clock input oscillation frequency (Note 3) Notes 1: Except when P50 is used as XCIN . 2: The average output current IOH (avg) or IOL (avg) are the average value during a 100 ms. 3: The oscillation frequency is at 50 % duty cycle. 4: Set f(XCIN ) < f(XIN)/3 when the sub-clock is used. Sub-clock input oscillation frequency (Note 3, 4)

7470/7471/7477/7478 GROUP USER’S MANUAL Table 1.20.7 Electrical characteristics (7471 group) (VCC = 2.7 V to 5.5 V, VSS = AV SS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. V OH V OL V T+ – VT– V T+ – VT– V T+ – VT– IIL IIL IIL IIL IIH IIH IIH IIH ICC V RAM Test conditions “H” output voltage P0 0 to P07, P10 to P17 P2 0 to P27, P40 to P43 “L” output voltage 0 to P07, P10 to P17 P2 0 to P27, P40 to P43 Hysteresis P00 to P07 P3 0 to P33 Hysteresis RESET Hysteresis P14/SIN P1 6/CLK “L” input current P0 0 to P07, P10 to P17, P4 0 to P43, P50 to P53 “L” input current P30 to P33 “L” input current 0 to P27 X IN, RESET “H” input current 0 to P07, P10 to P17, P4 0 to P43, P50 to P53 “H” input current P30 to P33 “H” input current 0 to P27 X IN, RESET Power source current RAM retention voltage When used as S IN or CLK V I = 0 V Not use pull-up transistor V I = 0 V Use pull-up transistor V I = 0V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V Ta = 25 °C Ta = 85 °C V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V VI = 0 V, not use pull-up tran- sistor, not use as analog input V I = 0 V, use pull-up transis- tor, not use as analog input V I = 0 V X IN is at stop mode V I = VCC Not use pull-up transistor V I = VCC VI = VCC , not use pull-up tran- sistor, not use as analog input V I = VCC X IN is at stop mode V CC = 5 V, IOH = –5 mA V CC = 3 V, IOH = –1.5 mA V CC = 5 V, IOL = 10 mA V CC = 3 V, IOL = 3 mA 3.0 2.0 –0.25 –0.08 –0.25 –0.08 2.0 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 2.0 1.0 –1.0 –0.35 –1.0 –0.35 3.6 5.5 V V V V V V V V V V µA µA mA mA µA µA µA µA mA mA µA µA µA µA µA µA µA µA µA µA mA mA mA mA mA mA µA µA mA mA mA µA µA µA µA V f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz At system op- eration, A-D conversion is executed At system op- eration, A-D conversion is not executed In low-speed mode, Ta = 25°C, low-power mode f(XCIN ) = 32 kHz At A-D conversion is not executed At wait mode, Ta = 25°C, low-power mode, f(XCIN ) = 32 kHz At stop mode, VCC = 5 V Stop all oscillation At wait mode

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Table 1.20.8 A-D converter characteristics (7471 group) (VCC = 2.7 V to 5.5 V, VSS = AV SS = 0 V, Ta = –20 °C to +85 °C, f(XIN) = 4 MHz, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. bits LSB LSB LSB LSB LSB LSB µs µs V kΩ V ±0.9 12.5 V CC V REF Test conditions Resolution Non-linearity error Differential non-linearity error Zero transition error Full scale transition error Conversion time Reference input voltage Ladder resistance value Analog input voltage V CC = VREF = 5.12 V, IOL (sum) = 0 mA V CC = VREF = 3.072 V, IOL (sum) = 0 mA V = V REF = 5.12 V V CC = VREF = 3.072 V 0.5VCC (Note) V OT V FST TCONV V REF R LADDER V IA f(XIN) = 8 MHz f(XIN) = 4 MHz Note: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect it to VCC .

7470/7471/7477/7478 GROUP USER’S MANUAL (3) 7477 group electrical characteristics recommended operating conditions. Table 1.20.11 shows the electrical characteristics. Table 1.20.12 shows the A-D converter characteristics. Table 1.20.9 Absolute maximum ratings (7477group) Unit V V V mW Symbol V CC V I V O Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Ratings –0.3 to +7 –0.3 to V CC +0.3 –0.3 to VCC +0.3 1000 (Note) –20 to +85 –40 to +150 Conditions All voltages are based on V SS . Output transistors are cut-off. Ta = 25 °C Note : The rating is 500 mW for the 32P2W-A package product. Table 1.20.10 Recommended operating conditions (7477 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) f(XIN) = 8 MHz f(XIN) = 4 MHz Symbol Parameter Unit Limits Max.Typ.Min. 4.5 2.7 0.8VCC 0.7VCC 0.8VCC V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz kHz kHz MHz MHz MHz MHz 5.5 4.5 V CC V CC V CC 0.2VCC 0.25VCC 0.16VCC 0.12VCC –30 –30 –10 500 250 2.2VCC –2.0 5.0 Power source voltage f(XIN) = 8.0 MHz f(XIN) = (2.2VCC –2.0) MHz Power source voltage “H” input voltage P0 0 to P07, P10 to P17, P30 to P33 “H” input voltage P20 to P23, P40, P41_______ “H” input voltage XIN, RESET “L” input voltage P00 to P07, P10 to P17, P30 to P33 “L” input voltage P20 to P23, P40, P41 “L” input voltage RESET “H” sum output current P00 to P07, P40 and P41 “H” sum output current P10 to P17 “L” sum output current P00 to P07, P40 and P41 “L” sum output current P10 to P17 “H” peak output current 0 to P07, P10 to P17, P40, P41 “L” peak output current 0 to P07, P10 to P17, P40, P41 “H” average output current 0 to P07, P10 to P17, P40, P41 (Note 1) “L” average output current 0 to P07, P10 to P17, P40, P41 (Note 1) V CC V SS V IH V IH V IH V IL V IL V IL V IL IOH (sum) IOH (sum) IOL (sum) IOL (sum) IOH (peak) IOL (peak) IOH (avg) IOL (avg) f(CNTR) f(SCLK ) f(XIN) Notes 1: The average output current IOH (avg) or IOL (avg) are the average value during a 100 ms. 2: The oscillation frequency is at 50 % duty cycle. Timer input frequency CNTR 0 (P32), CNTR 1 (P33) (Note 2) Serial I/O clock input frequency S CLK (P16) (Note 2) Clock input oscillation frequency (Note 2) f(X IN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz Use as clock synchro- nous serial I/O mode Use as UART mode V CC = 4.5 V to 5.5 V V CC = 2.7 V to 4.5 V

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Table 1.20.11 Electrical characteristics (7477 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. V OH V OL V T+ – VT– V T+ – VT– V T+ – VT– IIL IIL IIL IIL IIH IIH IIH IIH ICC V RAM Test conditions “H” output voltage P0 0 to P07, P10 to P17 P4 0, P41 “L” output voltage 0 to P07, P10 to P17 P4 0, P41 Hysteresis P00 to P07 P3 0 to P33 Hysteresis RESET Hysteresis P14/RxD P1 6/SCLK “L” input current P0 0 to P07, P10 to P17, P4 0, P41 “L” input current P30 to P33 “L” input current 0 to P23 X IN, RESET “H” input current 0 to P07, P10 to P17, P4 0, P41 “H” input current P30 to P33 “H” input current 0 to P23 X IN, RESET Power source current RAM retention voltage When used as RxD or S CLK V I = 0 V Not use pull-up transistor V I = 0 V Use pull-up transistor V I = 0V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V Ta = 25 °C Ta = 85 °C V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V I = 0 V, Not use as analog input V I = 0 V X IN is at stop mode V I = VCC Not use pull-up transistor V I = VCC V I = VCC Not use as analog input V I = VCC X IN is at stop mode V CC = 5 V, IOH = –5 mA V CC = 3 V, IOH = –1.5 mA V CC = 5 V, IOL = 10 mA V CC = 3 V, IOL = 3 mA 3.0 2.0 –0.25 –0.08 2.0 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 2.0 1.0 –1.0 –0.35 3.6 5.5 V V V V V V V V V V µA µA mA mA µA µA µA µA µA µA µA µA µA µA µA µA µA µA mA mA mA mA mA mA mA mA mA µA µA V f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz At system op- eration, A-D conversion is not executed At system op- eration, A-D conversion is executed At stop mode, VCC = 5 V Stop all oscillation At wait mode

7470/7471/7477/7478 GROUP USER’S MANUAL Table 1.20.12 A-D converter characteristics (7477 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. bits LSB µs µs V kΩ V 12.5 V CC V REF Test conditions Resolution Absolute accuracy Conversion time Reference input voltage Ladder resistance value Analog input voltage VCC = 4.5 V to 5.5 V, f(XIN) = 8 MHz VCC = 2.7 V to 5.5 V, f(XIN) = 4 MHz 0.5VCC (Note) T CONV V REF R LADDER V IA Note : Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect it to VCC .

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Note : The rating is 500 mW for the 56P6N-A package product. Table 1.20.14 Recommended operating conditions (7478 group) (VCC = 2.7 V to 5.5 V, VSS = AV SS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) (4) 7478 group electrical characteristics recommended operating conditions. Table 1.20.15 shows the electrical characteristics. Table 1.20.16 shows the A-D converter characteristics. Table 1.20.13 Absolute maximum ratings (7478 group) Unit V V V mW Symbol V CC V I V O Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Ratings –0.3 to +7 –0.3 to V CC +0.3 –0.3 to VCC +0.3 1000 (Note) –20 to +85 –40 to +150 Conditions All voltages are based on V SS . Output transistors are cut-off. Ta = 25 °C f(XIN) = 8 MHz f(XIN) = 4 MHz Symbol UnitLimits Max.Typ.Min. 4.5 2.7 0.8VCC 0.7VCC 0.8VCC V V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz kHz kHz MHz MHz MHz MHz kHz 5.5 4.5 V CC V CC V CC 0.2VCC 0.25VCC 0.16VCC 0.12VCC –30 –30 –10 500 250 2.2VCC –2.0 5.0 Power surce voltage f(X IN) = 8.0 MHz f(XIN) =(2.2VCC –2.0) MHz Power surce voltage Analog supply voltage “H” input voltage P0 0 to P07, P10 to P17, P30 to P33 “H” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1)_______ “H” input voltage XIN, RESET “L” input voltage P00 to P07, P10 to P17, P30 to P33 “L” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1) “L” input voltage RESET “H” sum output current of P00 to P07 and P40 to P43 “H” sum output current of P10 to P17 “L” sum output current of P00 to P07 and P40 toP43 “L” sum output current of P10 to P17 “H” peak output current 0 to P07, P10 to P17, P40 to P43 “L” peak output current 0 to P07, P10 to P17, P40 to P43 “H” average output current 0 to P07, P10 to P17, P40 to P43 (Note 2) “L” average output current 0 to P07, P10 to P17, P40 to P43 (Note 2) V CC V SS AV SS V IH V IH V IH V IL V IL V IL V IL IOH (sum) IOH (sum) IOL (sum) IOL (sum) IOH (peak) IOL (peak) IOH (avg) IOL (avg) f(CNTR) f(SCLK ) f(XIN) f(XCIN ) Notes 1: Except when P50 is used as XCIN . 2: The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms. 3: The oscillation frequency is at 50 % duty cycle. 4: Set f(XCIN ) < f(XIN)/3 when the sub-clock is used. f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz Parameter Timer input frequency CNTR 0 (P32), CNTR 1 (P33) (Note 3) Serial I/O clock input frequency S CLK (P16) (Note 3) Clock input oscillation frequency (Note 3) V CC = 4.5 V to 5.5 V V CC = 2.7 V to 4.5 V Use as clock synchro- nous serial I/O mode Use as UART mode Sub-clock input oscillation frequency (Notes 3, 4)

7470/7471/7477/7478 GROUP USER’S MANUAL Table 1.20.15 Electrical characteristics (7478 group) (VCC = 2.7 V to 5.5 V, VSS = AV SS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. V OH V OL V T+ – VT– V T+ – VT– V T+ – VT– IIL IIL IIL IIL IIH IIH IIH IIH ICC V RAM Test conditions “H” output voltage P0 0 to P07, P10 to P17 P4 0 to P43 “L” output voltage 0 to P07, P10 to P17 P4 0 to P43 Hysteresis P00 to P07 P3 0 to P33 Hysteresis RESET Hysteresis P14/RxD P1 6/SCLK “L” input current P0 0 to P07, P10 to P17, P4 0 to P43, P50 to P53 “L” input current P30 to P33 “L” input current 0 to P27 X IN, RESET “H” input current 0 to P07, P10 to P17, P4 0 to P43, P50 to P53 “H” input current P30 to P33 “H” input current 0 to P27 X IN, RESET Power source current RAM retention voltage When used as RxD or SCLK V I = 0 V Not use pull-up transistor V I = 0 V Use pull-up transistor V I = 0V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V Ta = 25 °C Ta = 85 °C V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V I = 0 V Not use as analog input V I = 0 V X IN is at stop mode V I = VCC , Not use pull-up transistor V I = VCC V I = VCC Not use as analog input V I = VCC X IN is at stop mode V CC = 5 V, IOH = –5 mA V CC = 3 V, IOH = –1.5 mA V CC = 5 V, IOL = 10 mA V CC = 3 V, IOL = 3 mA 3.0 2.0 –0.25 –0.08 2.0 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 2.0 1.0 –1.0 –0.35 3.6 5.5 V V V V V V V V V V µA µA mA mA µA µA µA µA µA µA µA µA µA µA µA µA µA µA mA mA mA mA mA mA µA µA mA mA mA µA µA µA µA V f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz At system op- eration, A-D conversion is not executed At system op- eration, A-D conversion is executed At low-speed mode, T a = 25°C, low- power mode, f (X CIN ) = 32 kHz, A-D conversion is not executed At wait mode, Ta = 25°C, low- power mode, f (XCIN ) = 32 kHz At stop mode, VCC = 5 V Stop all oscillation At wait mode

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Note : Set the VREF voltage to 0.5 V or more and 2 V or more. When using no A-D converter, connect it to VCC . Table 1.20.16 A-D converter characteristics (7478 group) (VCC = 2.7 V to 5.5 V, VSS = AV SS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted) Symbol Parameter UnitLimits Max.Typ.Min. bits LSB µÊs ʵs V kΩ V 12.5 V CC V REF Test conditions Resolution Absolute accuracy Conversion time Reference input voltage Ladder resistance value Analog input voltage V CC = 4.5 V to 5.5 V, f(XIN) = 8 MHz V CC = 2.7 V to 5.5 V, f(XIN) = 4 MHz 0.5VCC (Note) T CONV V REF R LADDER V IA

7470/7471/7477/7478 GROUP USER’S MANUAL

1.20.2 Timing requirements, switching characteristics

(1) 7470/7471 group timing requirements, switching characteristics Table 1.20.17 shows the timing requirements and switching characteristics of the 7470/7471 group. Figure 1.20.1 shows the timing chart. Table 1.20.17 Timing requirements and switching characteristics (7470/7471 group) (VCC = 4.0 V to 5.5 V, VSS = 0V, Ta = –20 °C to +85°C, f(XIN) = 4 MHz) Symbol tc(CLK) tWH (CLK) tWL (CLK) tsu(SIN–CLK) th(CLK-S IN) td(CLK-S OUT ) Parameter Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O input set up time Serial I/O input hold time Serial I/O output delay time UnitLimits Max.Typ.Min. 1000 400 400 200 200 ns ns ns ns ns ns150 Fig. 1.20.1 Timing chart (7470/7471 group) 0.2VCC 0.2VCC 0.2VCC 0.2VCC 0.8VCC 0.8VCC 0.8VCC 0.8VCC 0.8VCC tc(CLK) tWL (CLK) t WH (CLK) td(CLK-SOUT ) SIN CLK SOUT tsu(SIN-CLK) t h(CLK-SIN)

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (2) 7477/7478 group timing requirements, switching characteristics Table 1.20.18 shows the timing requirements and switching characteristics of the 7477/7478 group. Figure 1.20.2 shows the timing chart. Table 1.20.18 Timing requirements and switching characteristics (7477/7478 group) (VCC = 4.5 V to 5.5 V, VSS = 0V, Ta = –20 °C to +85°C, f(XIN) = 8 MHz) Symbol tc(SCLK ) tWH (SCLK ) tWL (SCLK ) tsu(RXD–S CLK ) th(SCLK -RXD) td(SCLK -TXD) tc(SCLK ) tWH (SCLK ) tWL (SCLK ) Parameter Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O input set up time Serial I/O input hold time Serial I/O output delay time Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width UnitLimits Max.Typ.Min. 2000 880 880 160 500 220 220 ns ns ns ns ns ns ns ns ns 100 Clock syn- chronous Clock asyn- chronous Fig. 1.20.2 Timing chart (7477/7478 group) 0.2VCC 0.2VCC 0.2VCC 0.2VCC 0.8VCC 0.8VCC 0.8VCC 0.8VCC 0.8VCC tc(SCLK ) tWL (SCLK ) tWH (SCLK ) td(SCLK -TXD) R XD SCLK TX D tsu(RXD-SCLK )t h(SCLK -RXD)

7470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.20.3 Power source current standard characteristics measuring circuit ICC A M3747x VCC VSS 0 V to 5.5 V XOUTXIN ICC A M3747x VCC VSS 0 V to 5.5 V XCOUTXCIN

1 In ordinary mode (f(X ) = 8 MHz, 4 MHz)2 In low-speed mode (f(X ) = 32 kHz, 7471/7478 group)IN CIN

1.20.3 Power source current standard characteristics

The power source current standard characteristics described in this section are mentioned as an characteristic example of the 7470/7471/7477/7478 group but not guaranteed by us. For standard values, refer to “1.20.1 Electrical characteristics.” Figure 1.20.3 shows the power source current standard characteristics measuring circuit.

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (1) 7470/7471 group power source current standard characteristics Fig. 1.20.4 ICC – VCC characteristics (f(XIN) = 8 MHz, 7470/7471 group) Fig. 1.20.5 ICC – VCC characteristics (f(XIN) = 4 MHz, 7470/7471 group) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 In ordinary mode In wait mode In stop mode Power source voltage VCC [V] Power source current ICC [mA] [Measuring condition : 25 °C, f(XIN) = 8 MHz] 0.0 Power source voltage V [V]CC Power source current ICC [mA] In ordinary mode In wait mode In stop mode 1.0 2.0 3.0 4.0 5.0 [Measuring condition : 25 °C, f(X ) = 4 MHz]IN

7470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.20.6 ICC – VCC characteristics (f(XCIN ) = 32 kHz, 7471 group) 0.0 In low-speed mode In wait mode In stop mode 20.0 10.0 40.0 30.0 Power source current ICC [mA] [Measuring condition : 25 °C, f(X ) = 32 kHz] Power source voltage V [V]CC CIN

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE (2) 7477/7478 group power source current standard characteristics Fig. 1.20.8 ICC – VCC characteristics (f(XIN) = 4 MHz, 7477/7478 group) Fig. 1.20.7 ICC – VCC characteristics (f(XIN) = 8 MHz, 7477/7478 group) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0.0 In ordinary mode In wait mode In stop mode Power source current ICC [mA] [Measuring condition : 25 °C, f(X ) = 8 MHz]IN Power source voltage V [V]CC 1.0 2.0 3.0 4.0 5.0 0.0 In ordinary mode In wait mode In stop mode Power source current ICC [mA] [Measuring condition : 25 °C, f(X ) = 4 kHz]IN Power source voltage V [V]CC

7470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.20.9 ICC – VCC characteristics (f(XCIN ) = 32 kHz, 7478 group) 10.0 20.0 30.0 0.0 In low-speed mode In wait mode In stop mode Power source current ICC [mA] [Measuring condition : 25 °C, f(X ) = 32 kHz] Power source voltage V [V]CC CIN

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE

1.20.4 Port standard characteristic

The port standard characteristics described in this section are mentioned as a characteristic example of the 7470/7471/7477/7478 group but not guaranteed by us. For standard values, refer to “1.20.1 Electrical characteristics.” Figure 1.20.10 shows the port standard characteristic measuring circuits. Fig. 1.20.10 Port standard characteristic measuring circuits IOL A VCC VSS P00 M3747x IOH VCC VSS P00 M3747x A VCC VSS P00 M3747x IIL

1 IOH –VOH characteristic

0 V to 5.5 V A 0 V to 5.5 V

2 IOL –VOL characteristic

3 IIL–VIL characteristic

0 V to 5.5 V

7470/7471/7477/7478 GROUP USER’S MANUAL (1) 7470/7471 group port standard characteristic Fig. 1.20.11 IOH – VOH characteristics of programmable I/O port (CMOS output) P-channel side (7470/7471 group) Fig. 1.20.12 IOL – VOL characteristics of programmable I/O port (CMOS output) N-channel side (7470/7471 group) 0.0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 VCC = 5 V VCC = 3 V “H” output current IOH [mA] [Measuring condition : Port P00, 25 °C] “H” output voltage V –VCC [V]OH 10.0 20.0 30.0 40.0 50.0 60.0 VCC = 5 V VCC = 3 V “L” output current IOL [mA] [Measuring condition : Port P00, 25 °C] “L” output voltage V [V]OL

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.20.13 IIL – VIL characteristics of programmable I/O port (CMOS output) pull-up transistor (7470/7471 group) 0.0 –0.7 VCC = 5 V VCC = 3 V Supply current IIL [mA] 0.07/div [Measuring condition : Port P00, 25 °C] Supply voltage V –VCC [V]IL

7470/7471/7477/7478 GROUP USER’S MANUAL (2) 7477/7478 group port standard characteristic Fig. 1.20.14 IOH – VOH characteristics of programmable I/O port (CMOS output) P-channel side (7477/7478 group) Fig. 1.20.15 IOL – VOL characteristics of programmable I/O port (CMOS) N-channel side (7477/7478 group) 0.0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 VCC = 5 V VCC = 3 V “H” output current IOH [mA] [Measuring condition : Port P00, 25 °C] “H” output voltage V –VCC [V]OH 10.0 20.0 30.0 40.0 50.0 60.0 VCC = 5 V VCC = 3 V “L” output current IOL [mA] [Measuring condition : Port P00, 25 °C] “L” output voltage V [V]OL

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.20.16 IIL – VIL characteristics of programmable I/O port (CMOS output) pull-up transistor (7477/7478 group) 0.0 –0.6 VCC = 5 V VCC = 3 V Supply current IIL [mA] 0.12/div [Measuring condition : Port P00, 25 °C] Supply voltage V –VCC [V]IL

7470/7471/7477/7478 GROUP USER’S MANUAL

1.20.5 A-D conversion standard characteristic

(1) Relative precision (7470/7471 group) Figure 1.20.17 to Figure 1.20.18 show the A-D conversion standard characteristics on the relative precision of the 7470/7471 group. In the graph, the lower line indicates a deviation from the ideal value at the point where the output code changes, namely, relative precision error (ERROR). For example, in Figure 1.20.17, the change of “3F 16 to 4016” of the output code occurs ideally at the point of IN0 = 757.32 mV. However, since the relative precision error is -3.567 mV, “757.32 - 3.567 = 753.753 mV” represents a measuring change point. In the graph, the upper line indicates an input voltage width (1 LSB WIDTH) in which the output code is the same. For example, in Figure 1.20.17, since the measured value of input voltage width, when the output code is “3F 16”, is 10.701 mV, the differential nonlinear error on the relative precision Fig. 1.20.17 A-D conversion standard characteristics, relative precision error (1) +1LSB -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. VCC = 3.1 [V] , XIN = 4.0 [MHZ] , Temp. = 25.0 [deg. C] ZERO TRANSITION ERROR 2.25 [mV] FULL - SCALE TRANSITION ERROR 25.5 [mV] : 1LSB WIDTH : ERROR Relative precision VREF = 3.072 [V] ANALOG INPUT IN 0 ] ] ] M37471M8 A/D CONV. ERROR & STEP WIDTH ] ] ] 11.890 -11.89 8 1 62 43 24 04 85 66 47 28 08 89 6 1 0 4 1 1 2 1 2 0 1 2 8 128 +1LSB -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. 11.890 -11.89 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.20.18 A-D conversion standard characteristics, relative precision error (2) +1LSB -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. VCC = 5.2 [V] , XIN = 4.0 [MHZ] , Temp. = 25 [deg. C] ZERO TRANSITION ERROR 7.5 [mV] FULL - SCALE TRANSITION ERROR 18.75 [mV] : 1LSB WIDTH : ERROR Relative precision VREF = 5.12 [V] ANALOG INPUT IN 0 ]]] M37471M8 A/D CONV. ERROR & STEP WIDTH ]]] 19.896 -19.89 8 1 62 43 24 04 85 66 47 28 08 89 6 1 0 4 1 1 2 1 2 0 1 2 8 128 +1LSB -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. 19.896 -19.89 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256

7470/7471/7477/7478 GROUP USER’S MANUAL (2) Absolute precision Figure 1.20.19 to Figure 1.20.23 show the A-D conversion standard characteristics on the absolute precision of the 7470/7471/7477/7478 group. In the graph, the lower line indicates a deviation from the ideal value at the point where the output code changes, namely, absolute precision error (ERROR). For example, in Figure 1.20.17, the change of “3F 16 to 4016” of the output code occurs ideally at the point of IN0 = 762 mV. However, since the absolute precision error is -8.4 mV, “762 - 8.4 = 753.6 mV represents the measuring change point. In the graph, the upper line indicates an input voltage with (1 LSB WIDTH) in which the output code is the same. For example, since the measured value of input voltage width, when the output code is “3F Fig. 1.20.19 A-D conversion standard characteristics, absolute precision error (1) -2LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. VCC = 3.1 [V] , XIN = 4.0 [MHZ] , Temp. = 25.0 [deg. C] : 1LSB WIDTH : ERROR Absolute precision VREF = 3.072 [V] ANALOG INPUT IN 0 ]]] M37471M8 A/D CONV. ERROR & STEP WIDTH ]]] -24 -36 -12 -24 -36 -12 8 1 62 43 24 04 85 66 47 28 08 89 6 1 0 4 1 1 2 1 2 0 1 2 8 128 -2LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 24 +2LSB 24 +2LSB

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.20.20 A-D conversion standared characteristics, absolute precision error (2) -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. VCC = 5.2 [V] , XIN = 4.0 [MHZ] , Temp. = 25 [deg. C] : 1LSB WIDTH : ERROR Absolute precision VREF = 5.12 [V] ANALOG INPUT IN 0 ]]] M37471M8 A/D CONV. ERROR & STEP WIDTH ]]] -20 -30 -10 -20 -30 -10 8 1 62 43 24 04 85 66 47 28 08 89 6 1 0 4 1 1 2 1 2 0 1 2 8 128 -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 20 +1LSB 20 +1LSB

7470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.20.21 A-D conversion standard characteristics, absolute precision error (3) -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. VCC = 3.1 [V] , XIN = 4.0 [MHZ] , Temp. = 25 [deg. C] : 1LSB WIDTH : ERROR Absolute precision VREF = 3.072 [V] ANALOG INPUT IN 0 ]]] M37478M8 A/D CONV. ERROR & STEP WIDTH ]]] -12 -18 -12 -18 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 128 -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 12 +1LSB 12 +1LSB

7470/7471/7477/7478 GROUP USER’S MANUAL HARDWARE Fig. 1.20.22 A-D conversion standard characteristics, absolute precision error (4) -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. VCC = 5.2 [V] , XIN = 4.0 [MHZ] , Temp. = 25 [deg. C] : 1LSB WIDTH : ERROR Absolute precision VREF = 5.12 [V] ANALOG INPUT IN 0 ]]] M37478M8 A/D CONV. ERROR & STEP WIDTH ]]] -20 -30 -10 -20 -30 -10 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 128 -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 20 +1LSB 20 +1LSB

7470/7471/7477/7478 GROUP USER’S MANUAL Fig. 1.20.23 A-D conversion standard characteristics, absolute precision error (5) -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. VCC = 5.2 [V] , XIN = 8.0 [MHZ] , Temp. = 25 [deg. C] : 1LSB WIDTH : ERROR Absolute precision VREF = 5.12 [V] ANALOG INPUT IN 0 ]]] M37478M8 A/D CONV. ERROR & STEP WIDTH ]]] -20 -30 -10 -20 -30 -10 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 128 -1LSB 1LSB WIDTH [ mV ] ERROR [ mV ] STEP No. 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 20 +1LSB 20 +1LSB

2.1 I/O pins

2.2 Interrupts

2.3 Timers

2.4 Serial I/O

2.5 A-D converter

2.6 Reset

2.7 Oscillation circuit

2.8 Low-power

2.9 Countermeasures

2.10 Notes on programming

2.11 Differences between

2.12 Example of application

7470/7471/7477/7478 GROUP USER’S MANUAL2-2 APPLICATION 7470 7471 7477 74782.1 I/O pins

2.1.1 I/O port

(1) Port register Table 2.1.1 shows a memory allocation of port register corresponding to each port. Table 2.1.1 Port register memory allocation Port 7470 group 00C0 16 00C2 16 00C4 16 00C6 16 00C8 16 7471 group 00C0 16 00C2 16 00C4 16 00C6 16 00C8 16 00CA 16 7477 group 00C0 16 00C2 16 00C4 16 00C6 16 00C8 16 7478 group 00C0 16 00C2 16 00C4 16 00C6 16 00C8 16 00CA 16 Address of port register Note: In the 7470/7477 group, P2 is 4 bits of b0 - b3 and P4 is 2 bits of b0 and b1. In the 7471/7478 group, P5 is 4 bits of b0 - b3. In Chapter 2, each page describes the corresponding products by using the following table. 7470 7471 7477 7478 M37470Mx/Ex-XXXSP M37471Mx/Ex-XXXSP/FP M37477Mx/E8-XXXSP/FP Non-corresponding products Corresponding products M37478Mx/E8-XXXSP/FP 5 5

2-37470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 7478(2) Port Pi direction register (i = 0 to 5) Switching between input and output for programmable I/O ports is performed by the port direction register corresponding to each port. Table 2.1.2 shows a memory allocation of the port direction register corresponding to each port and Figure 2.1.1 shows an example of port direction register setting. Port 7470 group 00C1 16 00C3 16 00C5 16 00C9 16 Address of port direction register Note: In the 7470 group, P2 is 4 bits of b0 - b3 and P4 is 2 bits of b0 and b1. In the 7477 group, P4 is 2 bits of b0 and b1. Table 2.1.2 Port direction register memory allocation 7471 group 00C1 16 00C3 16 00C5 16 00C9 16 7477 group 00C1 16 00C3 16 00C9 7478 group 00C1 16 00C3 16 00C9 Fig. 2.1.1 Example of port direction register setting ,,,, 10111 000When “6A16” ( ) is set in the Port P0 direction register Port P0 I/O direction P07 P06 P05 P04 P03 P02 P01 P00 Input Output Output Input Output Input Output Input b7 b0

7470/7471/7477/7478 GROUP USER’S MANUAL2-4 APPLICATION 7470 7471 7477 7478(3) Pull-up control register The ports shown in Table 2.1.3 can be pulled up by software. A pull-up operation can be performed by the P0 pull-up control register (address 00D016) and P1-P5 pull-up control register (address 00D1 16). Table 2.1.3 I/O ports that permit pull-up by software Register Device 7470 group 7471 group 7477 group 7478 group Port P0 pull-up control register Control by 1-bit unit *: In the 7470/7477 group, the P1-P4 pull-up control register is arranged. Note: In the 7470 group, P2 is 4 bits of b0 - b3 and P4 is 2 bits of b0 and b4. In the 7477 group, P4 is 2 bits of b0 and b1. In the 7471/7478 group, P5 is 4 bits of b0 - b3. Port P1-P5 pull-up control register* Control by 4-bit unit P1, P2, P4 P1, P2, P4, P5 P1, P4 P1, P4, P5 ,,,,

2-57470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Timer 12 mode register (T12M: Address 00F816) Timer 34 mode register (T34M: Address 00F916) A-D control register (ADCON: Address 00D916) A-D control register A-D control register A-D control register A-D control register A-D control register A-D control register A-D control register Edge polarity selection register (EG: Address 00D4 16) Edge polarity selection register Edge polarity selection register, Timer 12 mode register Edge polarity selection register, Timer 34 mode register CPU mode register (CPUM: Address 00FB 16) CPU mode register 7470/7471 group Serial I/O mode register (SM: Address 00DC 16) Serial I/O mode register Serial I/O mode register Serial I/O mode register

2.1.2 Notes on use

When using I/O pins, take the following points into consideration. (1) Double function ports Table 2.1.4 shows double function ports. For setting, refer to a structure of each register. Table 2.1.4 Double function port and control register Pin P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 P3 1 P3 2 P3 3 P5 0 P5 1 Double function port S RDY IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 INT0 INT1 CNTR 0 CNTR 1 X CIN X COUT 7470/7471 group S IN S OUT CLK 7477/7478 group R X D TXD S CLK 7477/7478 group Serial I/O control register (SIOSTS: Address 00E216) Serial I/O control register Serial I/O control register Serial I/O control register Note: In the 7470/7477 group, P2 is 4 bits of b0 to b3. The 7470/7477 group is not provided with P5.

7470/7471/7477/7478 GROUP USER’S MANUAL2-6 APPLICATION 7470 7471 7477 7478(2)Description of Pull-up control When pulling up a port by software, take the following points into consideration. l When P1 is used in the serial I/O mode, the pull-up settings corresponding to P14 to P17 are invalidated. (Pull-up is impossible.) l Pull-up control is exerted in the following bit units. P0 : 1-bit unit P1 to P5 : 4-bit unit When using an external pull-up resistor and software pull-up control for the same port in combined form, use P0, which can be controlled in bit units. (3)Notes on external circuit design for I/O ports

1 When designing an external circuit for I/O ports, be sure to set the following items within the

standard value range. l Sum output current l Peak output current l Average output current Figure 2.1.2 shows the example of external circuit design for I/O port. Fig. 2.1.2 Example of external circuit design for I/O port

2 When performing multiple key-in operations by forming a key matrix, design in consideration of

the port input current for multiple key-in operations. 2 For other notes, refer to “1.10 I/O Pins.” M3747x P00 R 0=250 WIOL0 =12 mA P02 P01 R 1=250 W R 2=250 WIOL2 =12 mA IOL1 =12 mA 10 ms 10 ms VCC =5 V “L” average output current (within 100 ms) 12 mA5 10 ms5 5 “L” sum output current IOL0 +IOL1 +IOL2 =36 mA < “L” peak output current IOL0 =IOL1 =IOL2 =12 mA < = 6 mA <100 ms Maximum standard value 60 mA 20 mA 10 mA ] : LED (VF= 2 V) used Ports P00 – P02 Timing of LED on (duty ratio: 50 %)

2-77470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.2.1 Memory map of interrupt related registers

2.2.1 Memory allocation

Figure 2.2.1 shows a memory map of interrupt related registers. ,,,, Address Edge polarity selection register (EG) Interrupt request register 1 (IR1) Interrupt request register 2 (IR2) Interrupt control register 1 (IE1) Interrupt control register 2 (IE2) 00D4 16 00FC 16 00FD 16 00FE 16 00FF 16

7470/7471/7477/7478 GROUP USER’S MANUAL2-8 APPLICATION 7470 7471 7477 74782.2.2. Processor status register (PS) The Processor status register consists of 8 bits. Figure 2.2.2 shows the structure of the Processor status register. Bit 2 related to interrupts is described below.

2 Interrupt disable flag: b2

The interrupt disable flag controls the acceptance of interrupt requests other than the BRK instruction. When this flag is “1,” the acceptance of interrupt requests is disabled. When the flag is “0,” the acceptance of interrupt requests is enabled. The instruction to set this flag to “1” is the SEI instruction and the instruction to set this flag to “0” is the CLI instruction. At a branch to an interrupt processing routine, this flag is automatically set to “1,” thereby multiple interrupts are disabled. To use multiple interrupt, set this flag to “0” by using the CLI instruction in the interrupt processing routine. Fig. 2.2.2 Structure of Processor status register b7 b2 b0 b7 b0 Processor status register Undefined Processor status register (PS) Unde- fined Flag name : Carry flag : Zero flag : Interrupt disable flag : Decimal mode flag : Break flag : Index X mode flag : Overflow flag : Negative flag C Z I D B T V N b The value in denotes the initial value immediately after reset release.

2-97470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 74782.2.3 Application example (1)External event detection by CNTR To detect a rising edge or a falling edge of the level of an input pin by using a pin other than the INT0 pin and the INT1 pin, it is possible to use the CNTR pin. Examples of use are shown below. l When the CNTR 0 pin is used <Interrupt source> CNTR interrupt +1 <Setting> 1 Set the edge polarity selection register.

• Select a CNTR0 edge polarity.
• Select CNTR0 as an interrupt source. 2 Clear the CNTR interrupt request bit to “0.” 3 Execute the NOP instruction. 4 Set the CNTR interrupt enable bit to “1.” l When the CNTR 1 pin is used <Interrupt source> Timer 3 interrupt+1,+2 <Setting> 1 Stop the count operation of timer 3. 2 Select CNTR1 as a count source of timer 3. 3 Select a CNTR1 edge polarity by the Edge polarity selection register. 4 Set timer 3 to “0.” 5 Clear the timer 3 interrupt request bit to “0.” 6 Set the timer 3 interrupt enable bit to “1.” 7 Start the count operation of timer 3. +1: It is possible to use the CNTR0 pin for a timer interrupt and the CNTR1 pin for a CNTR interrupt. +2: It is possible to use timer 4 as an interrupt source.

2.2.4 Notes on use

2 For notes on use, refer to “1.11 Interrupts.” ,,,,

7470/7471/7477/7478 GROUP USER’S MANUAL2-10 APPLICATION ,,,,

2.3.1 Memory allocation

Figure 2.3.1 shows a memory map of timer related registers. Fig. 2.3.1 Memory map of timer related registers 00F016 00F116 00F716 00F216 00FC 16 00FD 16 00FE 16 00FF16 00D4 16 00D5 16 00D6 16 00F916 00FA 16 00FB 16 00F816 00F316 Address Edge polarity selection register (EG) Input latch register (ILR) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer FF register (TF) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer mode register 2 (TM2) CPU mode register (CPUM) Interrupt request register 1 (IR1) Interrupt request register 2 (IR2) Interrupt control register 1 (IE1) Interrupt control register 2 (IE2)

2-117470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 74782.3.2 Application example (1) Each mode of timer For timers 1, 2, 3 and 4, the following 5 operation modes are available. For each timer mode and the details of it, refer to “1.12 Timers.”

1 Timer mode

2 Event counter mode

3 Pulse output mode

4 External pulse width measurement mode

5 PWM mode

Each timer mode has relation to the T0, T1, CNTR 0 and CNTR 1 pins as shown in Table 2.3.1. There are some modes that cannot be used for some combinations of timer and pin. Consider this when designing timers. Table 2.3.1 Relation between timer-used pins and modes Pin Timer Timer 1 Timer 2 Timer 3 Timer 4 Pulse output mode PWM mode Pulse output mode CNTR 0 Event counter mode External pulse width measurement mode CNTR 1 Event counter mode Event counter mode External pulse width measurement mode ,,,,

7470/7471/7477/7478 GROUP USER’S MANUAL2-12 APPLICATION 7470 7471 7477 7478(2) Example of use of each mode An example of use of each mode is shown below.

1 Timer mode: One-second measurement (timer function)

Outline:Divide the clock by the timer. Count one second by a timer 1 interrupt that is generated at an internal of 0.4 ms. Cause the timer to count up at each second. Specifications: Divide f(XCIN ) = 32 kHz by timer 1 to generate an interrupt. Check the value of the counter that counts with an timer 1 interrupt by the main routine. If one second has elapsed, execute timer count-up processing. Figure 2.3.2 shows an example of control procedure. × , × ,

2-137470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.3.2 Example of control procedure [Clock function] RESET Y N N Y RTI Y N Initialization Set the interrupt disable flag (each interrupt disabled) Clear the timer 1 interrupt enable bit (timer 1 interrupt disabled) Set the timer 12 mode register 5 1 05555 1 Timer 1 count stop Timer 1 count source ← Internal clock Timer 1 internal clock count source ← f(XCIN) Set the CPU mode register 55 05 11 5 0 Fixed to “0” Select XCIN, XCOUT XCOUT drive capacity ← High power Wait the f(XCIN) oscillation stabilizing time Set the Timer 1 to “7F16” Set the Timer 12 mode register 5 1 05555 0 T12M (Address 00F816) Timer 1 count start Clear the timer 1 interrupt request bit Set the timer 1 interrupt enable bit (Timer 1 interrupt enabled) Clear the interrupt disable flag (each interrupt enabled) Clock stop ? 1 second has elapsed ? (1 second counter = 250 ?) Clear 1 second counter Clock count up (second–year) Clear 1 second counter Set the Timer 1 to “7F16” Clear the Timer 1 interrupt request bit Processing for timer set is completed ? Timer 1 interrupt 1 second counter + 1 Interrupt at every 0.4 ms l For concrete time, ask the oscillator manufacture for information. Count by interrupt processing l 1 second = 1/32 kHz 5 (127+1) 5 250 Dividing ratio 7F16= When re-starting the clock from zero second after completing to set the clock, set timers again. Set the timer so that every processing within the loop marked may be executed in a period of 1 second or less. l l T12M (Address 00F816) CPUM (Address 00FB16)

7470/7471/7477/7478 GROUP USER’S MANUAL2-14 APPLICATION Fig. 2.3.3 Example of measurement method of frequency

2 Event counter mode: Frequency measurement

Outline:The frequency of the pulse input to the CNTR0 pin (“H” active) is measured by the number of events in a certain period. Specifications:A count operation is started specifying the count source of timer 1 as CNTR0. Timer 2 (count source: f(XIN)/64) detects 1 ms and the frequency of the pulse input to CNTR0 is calculated from the number of events counted within 1 ms. Note: The number of events of an input pulse is specified as 255 or less within 1 ms. Figure 2.3.3 shows an example of measurement method of frequency and Figure 2.3.4 shows an example of control procedure. ,,,, CNTR 0 kHz Timer 2 interrupt request bit Count start Count stop Count start Count stopX times X times 1 ms l Pulse frequency of CNTR 1 ms has elapsed 0 input =

2-157470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.3.4 Example of control procedure [Frequency measurement] RTIRTS Frequency measurement routine Clear the timer 2 interrupt enable bit (Timer 2 interrupt disabled) Set the Timer 12 mode register 55 555 1 5 1 Timer 1 count stop Timer 2 count stop Set the Timer 12 mode register 0 5 1101 5 1 Timer 1 count source ‹ CNTR 0 Timer 2 count source ‹ Internal clock Timer 2 internal clock count source ‹ f(XIN)/64 Set the Edge polarity selection register 5 1 55555 5 EG (Address 00D416) CNTR 0 rising edge selected Set the Timer 1 to “FF16” Set the Timer 2 to “7C16” Clear the timer 2 interrupt request bit Set the timer 2 interrupt enable bit (Timer 2 interrupt enabled) Set the Timer 12 mode register 0 5 1100 5 0 Timer 1 count start Timer 2 count start Timer 2 interrupt Read timer 1 Set the Timer 12 mode register 0 5 1101 5 1 T12M (Address 00F816) Timer 1 count stop Timer 2 count stop According to required accuracy, the event count value within 1 ms is detected repeatedly, and its results are averaged. (Timer 1 set value FF16) – (Timer 1 read value) ‹ Event count value within 1 ms T12M (Address 00F816) T12M (Address 00F816) T12M (Address 00F816)

7470/7471/7477/7478 GROUP USER’S MANUAL2-16 APPLICATION 7470 7471 7477 7478 Pulse output mode: Piezoelectric buzzer output Outline: The pulse output function of the timer is applied for a piezoelectric buzzer output. Specifications: A square wave obtained by dividing the clock f(XIN) = 8 MHz into about 2 kHz is output from the T0 pin. While the buzzer output stops, the level of the T0 pin is fixed at “H.” and setting of the division ratio. Figure 2.3.7 shows an example of control procedure. Fig. 2.3.6 Connection of timer and setting of division ratio Fig. 2.3.5 Example of a peripheral circuit [Pulse output mode] M3747x While the piezoelectric buzzer output stops, the “H” level is output. 250 ms 250 ms Set the division ratio so that the underflow period of timer 1 may be equal to this value. f(XIN) 8MHz 1/16 1/125 T01/2 Timer 1Fix

2-177470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.3.7 Example of control procedure [Piezoelectric buzzer output] N RESET Y 16 5 (124+1) 5 2

8 MHz

Set the interrupt disable flag (each interrupt disabled) Clear the timer 1 interrupt enable bit (Timer 1 interrupt disabled) Set the Timer 12 mode register 5 00555 1 1 T12M (Address 00F816) Timer 1 count stop Timer 1 count source ‹ Internal clock Timer 1 internal clock count source ‹ f(XIN)/16 T0 output selected Initialization Set the Timer mode register 2 55 55555 1 TM2 (Address 00FA16) Timer 1 division flip flop set enabled Set the Timer FF register 55 55555 0 TF (Address 00F716) Timer 1 division flip flop initial value 0 Set the port P12 as an output Port P12 ‹ “H” Set the Timer 1 to “7C16” Set the Timer 1 interrupt enable bit (Timer 1 interrupt enabled) Clear the interrupt disable flag (each interrupt enabled) Main processing Output unit A piezoeletric buzzer is requested ? Y (= 0 Request) N (= No request)[ Buzzer output stop Port P12 ‹ “H” Set the Timer 1 to “7C16” [ Buzzer output start [ A piezoelectric buzzer output stops. [ 2 kHz = Fixed dividion ratio Count by interrupt processing Timer 1 overflow divided by 2 7C 16 [ A piezoelectric buzzer request generated in the main processing is processed in the output unit. Immediately after no request? Set the Timer 12 mode register 5 0 0555 11 T12M (Address 00F816) Timer 1 count stop Set the Timer 12 mode register 5 00555 10 T12M (Address 00F816) Timer 1 count start

7470/7471/7477/7478 GROUP USER’S MANUAL2-18 APPLICATION Fig. 2.3.8 Example of peripheral circuit [Pulse width measurement mode]

4 Pulse width measurement mode: Feedback control of phase control

Outline: The phase control signal is adjusted by using the pulse width measurement mode. Specifications: The M3747x controls a load by phase control. At this time, the width of the pulse output from the load as a feedback signal is measured. With this result, the control over the load is compensated. Figure 2.3.8 shows an example of peripheral circuit and Figure 2.3.9 shows an example of control procedure. ,,,, M3747x CNTR 0 Port VAC Load

2-197470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.3.9 Example of control procedure [Pulse width measurement mode] ,,,, Y N RTS Pulse width measurement routine Read Timer 4 (Timer 4 set value FF16) – (Timer 4 read value) ‹ Input pulse “H” width measurement value [ Measurement completed Set the Timer 34 mode register 55 5555 1 5 Timer 4 count stop Set the Edge polarity selection register 5 0 555 0 5 5 Select the measurement of CNTR0 “H” width Interrupt ‹ CNTR 0 selected Set the Timer 4 to “FF16” Clear the CNTR interrupt request bit Set the Timer 34 mode register 5 551 55 0 5 T34M (Address 00F916) Timer 4 count start Set the Timer 34 mode register 5 551 55 1 5 T34M (Address 00F916) Timer 4 count source ‹ select according to an input pulse External pulse width measurement mode selected Set the Timer 34 mode register 5 551 55 1 5 T34M (Address 00F916) Timer 4 count stop CNTR interrupt request ? T34M (Address 00F916) EG (Address 00D416)

7470/7471/7477/7478 GROUP USER’S MANUAL2-20 APPLICATION 7470 7471 7477 74785 PWM mode: Analog output Outline: An analog output is performed by using the PWM function of the timer. Specifications: A count source of Timer 3 and Timer 4 is selected and a PWM waveform is output from the T1 pin. The PWM waveform is converted into an analog voltage by the external circuit of the T1 pin, and then this voltage is output. Note: The analog voltage to be output varies depending on the duty of the PWM waveform. Figure 2.3.10 shows an example of peripheral circuit and Figure 2.3.11 shows an example of control procedure. Fig. 2.3.10 Example of peripheral circuit [PWM mode] ,,,, M3747x 3 : 2 5 V

2-217470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.3.11 Example of control procedure [PWM mode] RTS Analog output routine Set the Timer 34 mode register 55 5555 11 Timer 3 count stop Timer 4 count stop Set the Timer 4 Set the Timer mode register 2 1 555555 5 Select PWM mode Set the Timer 34 mode register 1 55555 11 Select timer 3 count source Select timer 4 count source Select T 1 output Set the Timer 34 mode register 1 5 5555 00 Timer 3 count start Timer 4 count start Set port P1 Set the Timer 3 T34M (Address 00F916) T34M (Address 00F916) TM2 (Address 00FA16) T34M (Address 00F916) 3 as an output

7470/7471/7477/7478 GROUP USER’S MANUAL2-22 APPLICATION 7470 7471 7477 74782.3.3 Notes on use

2 When using a 16-bit counter by using two timers, take the following points into consideration

according to “1.12.5 Notes on use (2).” l The timing at which the timer value and the read value change, when two 8-bit timers are connected in series, is shown in Figure 2.3.12, taking the case where timer 1 and timer 2 are connected as an example (When Timer 1 and Timer 2 are connected and the set value of the Timer 1 is 2 16 and the set value of the Timer 2 is 116). The count source of timer 2 is the overflow signal of timer 1. In this case, the read value of timer 2 changes at the fall of the count source. When Timer 1 and Timer 2 are read continuously as a 16-bit counter, the count source of timer 2 changes at the falling edge of the count source of timer 1, so the A section can not be distinguished from the B section. Likewise, the C section cannot be distinguished from the D section. Fig. 2.3.12 Timing at which timer value and read value change in the case where two timers are connected in series 2 For other notes on use, refer to “1.12 timers.” ,,,, 0F F

10 F F

2-237470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.4.1 Memory map of serial I/O related registers in 7470/7471 group 2.4.1 7470/7471 group memory allocation Figure 2.4.1 shows a memory map of serial I/O related registers in the 7470/7471 group. 5 5 00FC 16 00FD 16 00FE 16 00FF16 00DC 16 00DD 16 00DE 16 Address Serial I/O mode register (SM) Serial I/O register (SIO) Serial I/O counterByte counter Interrupt request register 1 (IR1) Interrupt control register 1 (IE1)

7470/7471/7477/7478 GROUP USER’S MANUAL2-24 APPLICATION 7470 7471 7477 74782.4.2 Application example (1) Clock synchronous serial I/O mode Outline:Clock synchronous communication is performed among the 7470/7471 group. Specifications: M3747x 1…… Transmit side in half-duplex communication

• Synchronous clock: f(XIN)/16
• Port P17 is used as an S RDY signal input pin. M3747x 2…… Receive side in half-duplex communication
• Synchronous clock: External clock
• S RDY signal output Figure 2.4.2 shows an example of connections and Figure 2.4.3 shows an example of control procedure. Fig. 2.4.2 Example of connections [Clock synchronous serial I/O mode, 7470/7471 group] ,, ×× P17 CLK SOUTSIN SRDY SIN CLK SOUT M3747x M3747x1 2 Full-duplex communication Half-duplex communication Use No use fi fi

2-257470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.4.3 Example of control procedure [Clock synchronous serial I/O mode, 7470/7471 group] ,, ×× M3747x 1 M3747x 2 Set the Serial I/O mode register SM (Address 00DC16) Synchronous clock ‹ External clock Select SOUT , CLK S RDY signal output Select SRDY signal Mode ‹ Ordinary mode CMOS output Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 to input Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled) Clear the serial I/O interrupt request bit Write the transmit data into the Serial I/O register (Write the dummy data in the half-duplex communication) 0 0 50011 5 Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P17 to input Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled) Clear the serial I/O interrupt request bit Port P17 = “L” ? Write the transmit data into the Serial I/O register Set the Serial I/O mode register SM (Address 00DC16) Internal clock ‹ f(XIN)/16 Synchronous clock ‹ Internal clock Select SOUT , CLK Select port P17 Mode ‹ Ordinary mode CMOS output 01 00 5 01 1 N Y Serial I/O interrupt Serial I/O interrupt

7470/7471/7477/7478 GROUP USER’S MANUAL2-26 APPLICATION 7470 7471 7477 7478(2)Byte specification mode Outline: Among the 7470/7471 group, transfer is performed for two or more microcomputers by using the clock synchronous byte specification mode. Specifications: Transmit side M3747x1

• Synchronous clock: f(XIN)/32
• Port P17 is used as an S RDY signal input pin.
• Port P10 is used as an transmit preparation command signal output pin. Receive side M3747x2 , M3747x3 , M3747x4
• Synchronous clock: External clock
• SA RDY signal output
• Port P10 is used as an transmit preparation command signal output pin. control procedure. Fig. 2.4.4 Example of connections [Byte specification mode, 7470/7471 group] ,, ×× 00001110 P17 CLK S OUT P10 11111000 CLK SIN P10SRDY (SARDY ) 11111000 CLK SIN P10 11111000 CLK S IN P10 SA RDY CLK SRDY (SARDY ) SRDY (SARDY ) Transmit side (M3747x1) Serial I/O mode register
• Set port P17 as an input
• Connect a pull-up transistor to port P17
• Set port P10 as an output (Port P10: Transmit preparation command signal) Serial I/O mode register Serial I/O mode register Serial I/O mode register Receive side 1 (M3747x2) Receive side 2 (M3747x 3) Receive side 3 (M3747x 4) Byte counter (Initial value) = 0 Byte counter (Initial value) = 1 Byte counter (Initial value) = 2 Serial data Transmit/receive preparation command signal
• Set port P10 as an input (Port P10: Transmit/receive preparation command signal)
• Set port P14 as an input
• Set port P10 as an input (Port P10: Transmit/receive preparation command signal)
• Set port P1 4 as an input
• Set port P10 as an input (Port P10: Transmit/receive preparation command signal)
• Set port P1 4 as an input

2-277470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.4.5 Example of control procedure (1) [Byte specification mode, 7470/7471 group] ,, ×× oCgJE ^ M¤P úlO Zbg Transmit side (M3747x1) Write the dummy data into the Serial I/O register Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P17 as an input Write the transmit data to receive side 1 into the Serial I/O register Set the serial I/O mode register Internal clock ‹ f(XIN)/32 Synchronous clock ‹ Internal clock Select SOUT , CLK Select port P17 Mode ‹ Ordinary mode CMOS output 0 110001 0 N Y Receive side 1 (M3747x2) Connect a pull-up transistor to port P1 Set port P10 as an output Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled) Clear the serial I/O interrupt request bit Transmit preparation signal port P1 ‹ “L” Transmit preparation signal port P1 ‹ “H” Port P17 = “H” ? Write the transmit data to receive side 2 into the Serial I/O register Write the transmit data to receive side 3 into the Serial I/O register Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 as an input Set port P10 as an input Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled) Clear the serial I/O interrupt request bit Transmit preparation signal port P10 ‹ “L” ? Set the initial value of “0” of the receive side 1 in the byte counter Set the Serial I/O mode register SM (Address 00DC16) Synchronous clock ‹ External clock Select SOUT , CLK Select SRDY signal output pin. Select SARDY signal Mode ‹ Byte specify mode N-channel open-drain output 1 001111 0 N Y Serial I/O interruptSerial I/O interrupt Serial I/O interrupt Serial I/O interrupt SM (Address 00DC16)

7470/7471/7477/7478 GROUP USER’S MANUAL2-28 APPLICATION Fig. 2.4.6 Example of control procedure (2) [Byte specification mode, 7470/7471 group] ,, ×× oCgJE ^ M¤P úlO Zbg oCgJE ^ M¤P úlO Zbg Write the dummy data into the Serial I/O register N Y Receive side 2 (M3747x3) Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 as an input Set port P10 as an input Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled) Clear the serial I/O interrupt request bit Set the initial value of “1” of the receive side 2 in the Byte counter Set the Serial I/O mode register SM (Address 00DC16) Synchronous clock ‹ External clock Select SOUT , CLK Select SRDY signal output pin Select SARDY signal Mode ‹ Byte specify mode N-channel open-drain output 1 001111 0 N Y Write the dummy data into the Serial I/O register Set the initial value of “2” of the receive side 3 in the Byte counter Transmit preparation signal port P10 ‹ “L” ? Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled) Clear the serial I/O interrupt request bit Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 as an input Set port P10 as an input Set the Serial I/O mode register SM (Address 00DC16) Synchronous clock ‹ External clock Select SOUT , CLK Select SRDY signal output pin. Select SARDY signal Mode ‹ Byte specify mode N-channel open-drain output 1 001111 0 Receive side 3 (M3747x4) Serial I/O interrupt Serial I/O interrupt Transmit preparation signal port P10 ‹ “L” ?

2-297470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 74782.4.3 7477/7478 group memory allocation Figure 2.4.7 shows a memory map of serial I/O related registers in the 7477/7478 group. ×× ,, Fig. 2.4.7 Memory map of serial I/O related registers in 7477/7478 group 00FC 16 00FD 16 00FE 16 00FF16 00E216 00E316 00E416 00E016 00E116 Address Transmit/receive buffer register (TB/RB) Serial I/O control register (SIOCON) Serial I/O status register (SIOSTS) Baud rate generator (BRG) UART control register (UARTCON) Interrupt control register 1 (IE1) Interrupt request register 1 (IR1)

7470/7471/7477/7478 GROUP USER’S MANUAL2-30 APPLICATION ×× ,,

2.4.4 Application examples

(1) Clock synchronous serial I/O mode Outline: Clock synchronous communication is performed among the 7477/7478 group. Specifications: M3747x1…… Transmit side in half-duplex communication.

• Synchronous clock: BRG output (f(XIN)/4 or f(XIN)/16)/4.
• Port P17 is used as an S RDY signal input pin. M3747x 2…… Receive side in half-duplex communication
• Synchronous clock: External clock
• S RDY signal output Figure 2.4.8 shows an example of connections and Figure 2.4.9 shows an example of control procedure. Fig. 2.4.8 Example of connections [Clock synchronous serial I/O mode, 7477/7478 group] P17 SCLK SRDY RxD SCLK TxD RxD TxD M3747x 1 M3747x 2 Use fi Full-duplex communication No use fi Half-duplex communication

2-317470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.4.9 Example of control procedure [Clock synchronous serial I/O mode, 7477/7478 group] ×× ,, Write the transmit data into the Transmit buffer register (Write the dummy data in the half-duplex communication) M3747x 2 Serial I/O transmit interrupt Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enabled) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enabled) Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit Set baud rate generator Set the Serial I/O control register Select BRG count source Synchronous clock ‹ External clock SRDY output enabled Select transmit interrupt source Transmit enabled Receive enabled Clock synchronous serial I/O selected Serial I/O enabled 1 11111 5 5 Serial I/O receive interrupt NOP Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disabled) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disabled) M3747x 1 Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disable) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disable) Set port P17 as an input NOP Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enable) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enable) Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit Write the transmit data into the Transmit buffer register Y N Port P17 = “L” ? Set the Serial I/O control register Select BRG count source Synchronous clock ‹ BRG output divided by 4 SRDY output disabled Select transmit interrupt source Transmit enabled Receive enabled Clock synchronous serial I/O selected Serial I/O enabled 10 0111 55 SIOCON (Address 00E216) SIOCON (Address 00E216) Serial I/O receive interrupt Serial I/O transmit interrupt

7470/7471/7477/7478 GROUP USER’S MANUAL2-32 APPLICATION Fig. 2.4.10 Example of connections [Clock asynchronous serial I/O mode, 7477/7478 group] ×× ,, (2)Clock asynchronous serial I/O mode Outline: Clock asynchronous communication is performed among the 7477/77478 groups. Specifications: M3747x1…… Transmit side in half-duplex communication

• Baud rate: bps M3747x 2……Receive side in half-duplex communication
• Baud rate: bps “XX16” is a set value of the baud rate generator. Figure 2.4.10 shows an example of connections and Figure 2.4.11 shows an example of control procedure. f(XIN) f(XIN) RxDTxD RxD TxD M3747x 1 M3747x 2 Use fi Full-duplex communication No use fi Half-duplex communication

2-337470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.4.11 Example of control procedure [Clock asynchronous serial I/O mode, 7477/7478 group] ×× ,, Write the transmit data to the Transmit buffer register in the full-duplex communication Serial I/O transmit interrupt Set the Serial I/O control register BRG count source ‹ f(XIN)/4 Synchronous clock ‹ BRG output divided by 16 Select transmit interrupt source Transmit enabled Receive enabled Clock asynchronous serial I/O selected Serial I/O enabled 1 5 0011 5 0 Serial I/O receive interrupt Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disabled) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disabled) M3747x 1 Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disabled) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disabled) NOP Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enabled) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enabled) Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit Write the transmit data into the Transmit buffer register Set the Serial I/O control register BRG count source ‹ f(XIN)/4 Synchronous clock ‹ BRG output divided by 16 Select transmit interrupt source Transmit enabled Receive enabled Clock asynchronous serial I/O selected Serial I/O enabled 1 5 0011 5 0 M3747x 2 Serial I/O transmit interrupt Set baud rate generator (Set “55 16” to BRG) Set baud rate generator (Set “55 16” to BRG) NOP Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enabled) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enabled) SIOCON (Address 00E216) SIOCON (Address 00E216) Serial I/O receive interrupt

7470/7471/7477/7478 GROUP USER’S MANUAL2-34 APPLICATION 7470 7471 7477 74782.4.5 Notes on use 2 For notes on use, refer to “1.13 Serial I/O.” ,,,,

2-357470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 74782.5 A-D converter

2.5.1 Memory allocation

Figure 2.5.1 shows a memory map of A-D conversion related registers. Fig. 2.5.1 Memory map of A-D conversion related registers ,,,, 00FC 16 00FD 16 00FE 16 00FF16 00D9 16 00DA 16 Address A-D control register (ADCON) A-D conversion register (AD) Interrupt request register 1 (IR1) Interrupt control register 1 (IE1)

7470/7471/7477/7478 GROUP USER’S MANUAL2-36 APPLICATION 7470 7471 7477 74782.5.2 Application examples (1) A-D conversion value determination methods For improvement of the accuracy of A-D conversion results, we recommend you perform sampling several times to determine a value. The following A-D conversion value sampling methods are available (m, n: Arbitrary values based on the specification). Example: 1Sampling 2 n times 2Moving sampling 2n times 3Sampling (2n + 2) times For value determination, the following methods are available. Example: [1] The sum of sampling result is divided by sampling times. [2] After execution of sampling (2n + 2) times, the minimum value and the maximum value are excluded and then the remaining values are added and then divided by 2n times. [3] When updating the average value calculated by [1]or [2], this average value is not updated if the difference from the previous value is ± m or more. In “2.5.2 Application examples, (2) Example of A-D conversion setting,” an example of using the sampling methods 2 + 3 and the determination method [3] is shown. ,,,,

2-377470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 7478(2) Example of A-D conversion setting An example of A-D conversion setting using the sampling methods 2 + 3 and the determination method [3] described on the previous page is shown below. Specifications: After execution of 6-time moving sampling the maximum value and the minimum value are excluded and then the remaining values are added. This result is divided by 4 (times). If the difference from the previous value is less than ±5, the value is updated. If the same difference is ±5 or more, it is not updated. Figure 2.5.2 shows an example of control procedure. ,,,, Fig. 2.5.2 Example of A-D conversion control procedure (ADRAM) ‹ AB16 RTS A816 A916A616 AB 16A716 A816 Sampling point A-D conversion result Minimum value Maximum value A-D conversion routine Clear the A-D conversion interrupt request bit Set the A-D control register 00 055 11 0 ADCON (Address 00D916) AD input pin ‹ P20/IN0 End conversion V REF is connected (Note 1) Fixed to “0” Set the port P20 as an input After execution of 6-time samplings to this time, the minimum value and the maximum value are excluded and then the remaining values are added. 2: Performs this operation only in the 7470/7471 group. A termination of A-D conversion is verified by the state of the A-D conversion completion bit, the state of the A-D conversion completion interrupt request bit and a branch to the A-D conversion completion interrupt processing routine. Wait the VREF stabilizing time (1.0 ms or more) (Note 2) Set the A-D control register 0 0055 10 0 ADCON (Address 00D916) Clear the A-D conversion completion bit Notes 1: The 7477/7478 group is not provided with this bit. A-D conversion completed ? (Note 3) The contents of A-D conversion register is read and stored into RAM. A816+A9 16+A7 16+A8 16=2A0 16 Total of 4-time sampling 2A016 =A8 164 Compare with the previous fixed value Renewal of fixed value less than –5 N Y –5 or more

7470/7471/7477/7478 GROUP USER’S MANUAL2-38 APPLICATION 7470 7471 7477 74782.5.3 Notes on use n The analog input internal equivalent circuit is shown in Figure 2.5.3. For correct A-D conversion, it is necessary that the internal capacitor should be completely charged within the specified time. The maximum value of output impedance of the analog input source required to terminate capacitor charging within this time is shown below.

• At f(X IN) = 4 MHz, Approximately 10 kΩ
• At f(XIN) = 8 MHz, Approximately 2 kΩ If the maximum value of output impedance exceeds the above value, take a proper measure, for example, insert a capacitor (0.1 µ F to 1 µF) between analog input pin and VSS . Fig. 2.5.3 Analog input internal equivalent circuit n For other notes on use, refer to “1.14 A-D converter.” VREFVSS VSS VCC SW1 (Note 2) SW2 R=4 kΩ ±60% C 2=6 pF ±30% VSS C 1=10 pF ±50 %Port P2i/INi (i=0 to 7) (Note 1) Amplifier Reference voltage generation circuit Switch tree Resistor ladder VREF switch (Note 3) Notes 1: This is a parasitic diode of the output transistor. 2: SW1 is turned on only when the analog input pin is selected. 3: The VREF switch is not provided in the 7477/7478 group.

2-397470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 7478

2.6.1 Reset circuit

Figure 2.6.1 shows an example of reset circuit. Fig. 2.6.1 Example of reset circuit

2.6.2 Notes on use

2 For notes on use, refer to “1.15 Reset.” ,,,, VCCRESET M3747x VCCRESET M3747x 32P 42P 56P RESET VCC 18 25 28 17 22 23 Supply voltage detection circuit RESET, V CC pin number

7470/7471/7477/7478 GROUP USER’S MANUAL2-40 APPLICATION 7470 7471 7477 7478 (1) Oscillation circuit using a ceramic resonator An oscillation circuit can be formed by connecting a ceramic resonator or a crystal oscillator between the XIN pin and the XOUT pin and between the XCIN pin and the XCOUT pin. Figure 2.7.1 shows an example of oscillation circuit using a ceramic resonator. Regarding such circuit constants as R d, CIN and COUT , ask the oscillator maker for information and then set the recommended value. Fig. 2.7.1 Example of Oscillation circuit using ceramic resonator (2) External clock input To the main clock and timer clock oscillation circuits, clocks can also be supplied from the outside. Figure 2.7.2 shows an example of circuits in this case. At this time, make the X OUT (XCOUT ) pin open. As an external clock to be input to the XIN (XCIN ) pin, use a pulse signal with a duty ratio of 50 %. Fig. 2.7.2 Example of external clock input circuit Note: The XCIN and the XCOUT pin are not provided in the 7470/7477 group. C IN C OUT XIN XOUT R d C IN C OUT R d 7470/7477 group 7471/7478 group 14 15 19 24 20 23 (18) (25) (26) XIN XOUT XCIN XCOUT R d' (19) C CIN C COUT Note: The number in parentheses denotes the case of a flat package. VCC VSS C IN C OUT XIN XOUT R d 7470/7477 group 7471/7478 group 14 15 19 24 20 23 (18) (25) (26) XIN XOUT XCIN XCOUT (19) VCC VSS Note: The number in parentheses denotes the case of a flat package. Open External oscillation circuit Open External oscillation circuit Duty ratio 50% Duty ratio 50%

2-417470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION

2.8 Low-power dissipation function

7470 7471 7477 74782.8 Low-power dissipation function

2.8.1 CPU mode register

The CPU mode register consists of a stack page selection bit+1 and internal system clock control bits+2. +1: In the products having a RAM capacity of 192 bytes or less, a RAM is not arranged on page 1, so this bit is not available. (Be sure to set this bit to “0.”) +2: In the 7470/7477 group, which is not provided with a sub-clock (f(XCIN )) generating circuit, f(XCIN ) is not used. (Be sure to set this bit to “0.”) Figure 2.8.1 shows a structure of CPU mode register. Fig. 2.8.1 Structure of CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address B At reset R W CPU mode register 0, 1 ? 5 Name Function Fix these bits to “0.” Nothing is allocated for this bit. This is write enabled bit and is undefined at reading. Main clock (XIN–XOUT ) stop bit XCOUT drive capacity selection bit 0Stack page selection bit Internal system clock selection bit 0: In page 0 area 1: In page 1 area (Note 1) 0: Low 1: High (Note 2) 0: Oscillates 1: Stops (Note 2) 0: X IN–XOUT selected (Ordinary mode) 1: XCIN–XCOUT selected (Low speed mode) (Note 2) P50, P51/XCIN,XCOUT selection bit 0: P50, P51 1: XCIN, XCOUT (Note 2) Notes 1: In the products having a RAM capacity of 192 bytes or less, set this bit to “0.” Since the 7470/7477 group is not provided with the sub-clock generating circuit, f(X Fix these bits to “0.” 00FB 16] CIN) cannot be used.

7470/7471/7477/7478 GROUP USER’S MANUAL2-42 APPLICATION 7470 7471 7477 74782.8.2 Application examples As examples of application, examples of setting between modes are shown below. (1) Ordinary mode → Stop mode → Ordinary mode (2) Ordinary mode → Wait mode → Ordinary mode (3) Ordinary mode → Low speed mode (4) Low speed mode → Ordinary mode Note: In the 7470/7477 group, which is not provided with a sub-clock generating circuit, the low- speed mode is not available. ,,,,

2-437470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.8.2 Example of control procedure [Ordinary mode → Stop mode → Ordinary mode] (1) Ordinary mode → Stop mode → Ordinary mode Specifications: The stop mode is executed by the STP instruction. Restoration to the ordinary mode is attained by INT0 interrupt. Figure 2.8.2 shows an example of control procedure. Clear the timer 3 interrupt enable bit (timer 3 interrupt disabled) Clear the timer 4 interrupt enable bit (timer 4 interrupt disabled) Stop the timer 3 and timer 4 and select the timer 3 count source (Set the Timer 34 mode register) RTI 55 5555 11 Select the timer 3 count source Set the interrupt disable flag (each interrupt disabled) Clear the interrupt disable flag (each interrupt enabled) INT0 interrupt Set the return interrupt source Clear the INT 0 interrupt request bit Execute the NOP instruction Set the INT0 interrupt enable bit (INT0 interrupt enabled) Set the timer 3 and 4 count state (Set the Timer 34 mode register) 55 5555 00 T34M (Address 00F916) Timer 3 count Timer 4 count Execute the STP instruction Clear the interrupt disable flag (each interrupt enabled) Re-set the timer 3 and 4 Timer 34 mode register Timer 3 register Timer 4 register T34M (Address 00F916)

7470/7471/7477/7478 GROUP USER’S MANUAL2-44 APPLICATION 7470 7471 7477 7478(2) Ordinary mode → Wait mode → Ordinary mode Specifications: The wait mode is executed by the WIT instruction. Restoration to the ordinary mode is attained by INT0 interrupt. Figure 2.8.3 shows an example of control procedure. Fig. 2.8.3 Example of control procedure [Ordinary mode → Wait mode → Ordinary mode] RTI Clear the interrupt disable flag (each interrupt enable) INT0 interrupt Set the return interrupt source Clear the INT0 interrupt request bit Execute the NOP instruction Set the INT0 interrupt enable bit (INT0 interrupt enable) Execute the WIT instruction The next address of the WIT instruction

2-457470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 7478(3) Ordinary mode → Low speed mode Specifications: The system clock is switched from the main clock (f(XIN) = 8 MHz) to the sub- clock (f(XCIN ) = 32 kHz). The main clock is stopped. Figure 2.8.4 shows an example of control procedure. Fig. 2.8.4 Example of control procedure [Ordinary mode → Low speed mode] × , × , Set the CPU mode register 0 5 0011 5 0 CPUM (Address 00FB16) Fixed to “0” XCIN, XCOUT selected XCOUT drive capacity High power selected Main clock oscillation System clock Ordinary mode selected Wait f(XCIN) oscillation stabilizing time [ For certain time, ask the oscillator manufacturer for information. Set the CPU mode register 1 5 0111 5 0 CPUM (Address 00FB16) Fixed to “0” XCIN, XCOUT selected XCOUT drive capacity High power selected Main clock stop System clock Low speed mode selected

7470/7471/7477/7478 GROUP USER’S MANUAL2-46 APPLICATION Fig. 2.8.5 Example of control procedure [Low speed mode → Ordinary mode] (4) Low speed mode → Ordinary mode Specifications: The system clock is switched from the sub-clock (f(XCIN ) = 32 kHz) to the main clock (f(XIN) = 8 MHz). The sub-clock is stopped. Figure 2.8.5 shows an example of control procedure. × , × , Set the CPU mode register 1 5 0011 5 0 CPUM (Address 00FB16) Fixed to “0” XCIN, XCOUT selected XCOUT drive capacity High power selected Main clock oscillation System clock Low-speed mode selected Wait f(XIN) oscillation stabilizing time [ For certain time, ask the oscillator manufacturer. Set the CPU mode register 0 5 00 5 0 5 0 CPUM (Address 00FB16) Fixed to “0” 0, P51 selected Main clock oscillation System clock Ordinary mode selected

2-477470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION ,,,,

2.8.3 Notes on use

2 For notes on use, refer to “1.17 Low-power dissipation function.”

7470/7471/7477/7478 GROUP USER’S MANUAL2-48 APPLICATION

2.9 Countermeasures against noise

,,,, Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.

2.9.1 Shortest wiring length

The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Reason The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Fig. 2.9.1 Wiring for the RESET pin Reset circuit Reset circuit V SSVSS VSS RESET VSS RESET 7470/7471/ group 7470/7471/ group Noise N.G. O.K.

2-497470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.9.2 Wiring for clock I/O pins (2) Wiring for clock input/output pins l Make the length of wiring which is connected to clock I/O pins as short as possible. l Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. l Separate the VSS pattern only for oscillation from other VSS patterns. Reason A microcomputer’s operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. ,,,, XIN XOUT VSS An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the VSS line for oscillation from other V Noise XIN XOUT VSS XIN XOUT VSS O.K.N.G. SS lines

7470/7471/7477/7478 GROUP USER’S MANUAL2-50 APPLICATION 7470 7471 7477 7478(3) Wiring for the VPP pin of the One Time PROM version and the EPROM version l Make the length of wiring which is connected to the V PP pin as short as possible. l Connect an approximately 5 kΩ resistor to the VPP pin in serial. l The P3 3 pin is also used as the VPP pin. Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the V PP pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. Fig. 2.9.3Wiring for the V PP pin of the One Time PROM and the EPROM version ,,,, 7470/7471/7477/7478 group P33/VPP Approximately 5kΩ

2-517470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 74782.9.2 Connection of a bypass capacitor across the Vss line and the Vcc line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: l Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. l Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. l Use lines with a larger diameter than other signal lines for VSS line and VCC line.

2.9.3 Wiring to analog input pins

l Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. l Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the V SS pin at equal length. Reason Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. If a capacitor between an analog input pin and the V SS pin is grounded at a position far away from the VSS pin, noise on the GND line may enter a microcomputer through the capacitor. Fig. 2.9.5Analog signal line and a resistor and a capacitor Fig. 2.9.4Bypass capacitor across the VSS line and the VCC line VSS VCC VSSVCC Chip Chip VSSVCC Thermistor (Note) Microcomputer Analog input pin Note : The resistor is for dividing resistance with a thermister. VSS Noise N.G. O.K.

7470/7471/7477/7478 GROUP USER’S MANUAL2-52 APPLICATION 7470 7471 7477 74782.9.4 Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. <Reason> In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Fig. 2.9.7Wiring to a signal line where potential levels change frequently Fig. 2.9.6Wiring for a large current signal line XIN XOUT VSS M Microcomputer Mutual inductance Large current GND XIN XOUT VSS CNTRDo not cross

2-537470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 74782.9.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware> l Connect a resistor of 100 Ω or more to an I/O port inseries. <Software> l As for an input port, read data several times by a program for checking whether input levels are equal or not. l As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. l Rewrite data to direction registers and pull-up control registers (only the product having it) at fixed periods. When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. Fig. 2.9.8 Setup for I/O ports ,,,, Direction register Port latch Data bus I/O port pins Noise Noise O.K. N.G.

7470/7471/7477/7478 GROUP USER’S MANUAL2-54 APPLICATION 7470 7471 7477 74782.9.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. <The main routine> l Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N + 1 Q (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. l Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. l Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine> l Decrements the SWDT contents by 1 at each interrupt processing. l Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed periods (at the fixed interrupt processing count). l Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value N. ,,,,

2-557470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION Fig. 2.9.9 Watchdog timer by software Main routine Main routine errors Interrupt processing routine Interrupt processing Interrupt processing routine errors Main processing ← N (SWDT) ← (SWDT)—1 (SWDT) = N ? ≤ 0 ? > 0 ≤ 0 RTI Return= N ≠ N CLI (SWDT) (SWDT)

7470/7471/7477/7478 GROUP USER’S MANUAL2-56 APPLICATION 7470 7471 7477 74782.10 Notes on programming

2.10.1 Processor status register

Fig. 2.10.1 Initialization of flags in PS (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S + 1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction should be executed after every PLP instruction. (1) Initialization of processor status register After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1.” Therefore, flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. Fig. 2.10.2 Stack memory contents after PHP instruction execution Fig. 2.10.3 Note to execute by PLP instruction ,,,, Main program Flags initializing Reset NOP instruction PLP instruction Saved PS (S) (S) + 1

2-577470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION 7470 7471 7477 74782.10.2 Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal results in decimal mode. To calculate in decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (2) Note on flags in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The Carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a bor- row, the C flag must be initialized before each calculation. Fig. 2.10.4 Note for decimal operation ,,,,

2 For other notes, refer to the notes described in

each section. Set D Flag to “1” ADC or SBC instruction NOP instruction SEC , CLC , or CLD instruction

7470/7471/7477/7478 GROUP USER’S MANUAL2-58 APPLICATION

2.11 Differences between 7470/7471 group and 7477/7478 group

7470 7471 7477 74782.11 Differences between 7470/7471 group and 7477/7478 group Table 2.11.1 shows differences between the 7470/7471 group and the 7477/7478 group. Exercise due care at substitution. Table 2.11.1 Differences between 7470/7471 group and 7477/7478 group RAM size ROM size 32-pin SOP Operating temperature range Interrupt source types Serial I/O Byte specification mode Port P2 Software pull-up control A-D conversion V REF OFF function 7470/7471 group 128/192/384 bytes 4K/8K/16K byte N -20 to 85°C Clock synchronous Y General I/O port / Analog input P0, P1, P2, P4, P5 Y 7477/7478 group 192/384 bytes 8K/16K byte Y -20 to 85 °C Clock synchronous / UART N General input port / Analog input P0, P1, P4, P5 N

2-597470/7471/7477/7478 GROUP USER’S MANUAL APPLICATION

2.12 Example of application circuit

Fig. 2.12.1 Application circuit example (cleaner) ××× M37470M2 Power source (AC 100 V) Power source for control (DC 5 V) Zero cross detection Dust sensor Thermistor Key input Photo triac LED Mode display Power display BCR BCR Vcc AD AD PORT PORT PORT INT PORT ON/OFF High Low Auto ON/OFF High Low Photo triac Blower motor Auto Brush motor

3.1 Control registers

3.2 Mask ROM ordering

3.3 ROM programming

3.4 Mark specification form

3.5 Package outline

3.6 SFR memory map

3.7 Pin configuration

7470/7471/7477/7478 GROUP USER’S MANUAL3-2 APPENDIX Fig. 3.1.1 Structure of Port Pi direction register (i=0, 1, 2, 4) Fig. 3.1.2 Structure of Port P0 pull-up control register At reset Port Pi direction register (PiD) (i = 0,1,2,4) [Address 00C116, 00C316, 00C516, 00C916] Port Pi direction register Port Pi direction register 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode B RWName Function Notes 1: The 7477/7478 group is not provided with the port P2 direction register (input only). The Port P4 is provided as below:

• 7470/7477 group has 2 bits of P4 0 and P41
• 7471/7478 group has 4 bits of P40 to P43. b1b2b3b4b5b6b7 b7 b6 b5 b4 b3 b2 b1 b0 Name Function At resetRW Port P0 pull-up control register Port P0 pull-up control register Port P00 pull-up control bit B Port P01 pull-up control bit Port P02 pull-up control bit Port P03 pull-up control bit Port P04 pull-up control bit Port P05 pull-up control bit Port P0 6 pull-up control bit Port P0 7 pull-up control bit 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up [Address 00D016]

3-37470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.1.3 Structure of Ports P1 to P5 pull-up control register Fig. 3.1.4 Structure of Edge polarity selection register b7 b6 b5 b4 b3 b2 b1 b0 Nameb Function At resetRW Ports P1 to P5 pull-up control register [Address Ports P1 to P5 pull-up control register 3 0 4 0 0 : No pull-up 1 : Pull-up Notes Ports P10 to P13 pull-up control bit Ports P40 to P43 pull-up control bit (Note 4) Ports P24 to P27 pull-up control bit (Notes 2, 3) Ports P20 to P23 pull-up control bit (Note 2) Ports P14 to P17 pull-up control bit 1 : In the 7470/7477 group, the P1 to P4 Pull-up control register is provided. 2 : In the 7477/7478 group, nothing is allocated to these bits. They are undefined at reading. 3 : In the 7470/7477 group, nothing is allocated to these bits. They are undefined at reading. 4 : The 7470/7477 group is provided with only Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Ports P50 to P53 pull-up control bit (Note 3) 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 00D1 16] P40 and P41. b7 b6 b5 b4 b3 b2 b1 b0 Name Function At reset Edge polarity selection register (EG) [Address Edge polarity selection register 3 0 4 0 INT0 edge selection bit INT1 edge selection bit CNTR 0 edge selection bit CNTR 1 edge selection bit CNTR 0/CNTR 1 interrupt selection bit INT1 source selection bit (at STP or WIT instruction execution) 0 : P31/INT1 1 : P00 to P07 “L” level input (for key-on wake-up) 6, 7 Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. 0 : Falling edge 1 : Rising edge 0 : CNTR 1 : CNTR1 WRB ?? 5 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 00D4 16]

7470/7471/7477/7478 GROUP USER’S MANUAL3-4 APPENDIX Fig. 3.1.5 Structure of Input latch register Fig. 3.1.6 Structure of A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address B At resetR W A-D control register 5, 6 00 0 Name Function A-D input selection bits 0 0 0 : P20/IN0 0 : Under conversion 1 : End conversion b2 b1 b0 (Note 1) A-D conversion end bit (Note 2) VREF connection selection bit ] The 7477/7478 group is not provided with this bit. This bit is undefined at reset. Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. Fix this bit to “0.” ?? 5 0 0 1 : P21/IN1 0 1 0 : P22/IN2 0 1 1 : P23/IN3 1 0 0 : P24/IN4 1 0 1 : P25/IN5 1 1 0 : P26/IN6 1 1 1 : P27/IN7 0 : The VREF pin is separated from the comparison voltage generator. 1 : The VREF pin is connected to comparison voltage generator. Notes 1: Since the 7470/7477 group is not provided with pins P24–P27, do not set.

• A-D conversion is started by setting bit 3 to “0.”
• Writing “0” into bit 3 is valid. Even if “1” is written into bit 3, this bit is not set to “1.” Accordingly, when writing a value into the A-D control register without affecting bit 3, set bit 3 to “1.” 00D9 16] Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. b7 b6 b5 b4 b3 b2 b1 b0 Name Function At reset Input latch register (ILR) [Address P30/INT0 latch bit Input latch register WRB to P31/INT1 latch bit P32/CNTR 0 latch bit P33/CNTR 1 latch bit ? 5 ? 5 ? 5 ? 5? When b0 of EG (Note) is “0”: reverse level on INT0 pin When b0 of EG (Note) is “1”: level on INT0 pin When b1 of EG (Note) is “0”: reverse level on INT1 pin When b1 of EG (Note) is “1”: level on INT1 pin When b2 of EG (Note) is “0”: reverse level on CNTR 0 pin When b2 of EG (Note) is “1”: level on CNTR 0 pin When b3 of EG (Note) is “0”: reverse level on CNTR 1 pin When b3 of EG (Note) is “1”: level on CNTR 1 pin Note: EG is the Edge polarity selection register. 00D6 16]

3-57470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.1.7 Structure of A-D conversion register Fig. 3.1.8 Structure of Serial I/O mode register b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address B At resetR W A-D conversion register to Function This is a read-only register to store A-D conversion results. 5? 00DA 16] b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O mode register (SM) [Address B At resetRW Serial I/O mode register (7470/7471 group) 0, 1 Name Function 0 0 : f(XIN)/8 or f(XCIN)/8 b1 b0Internal clock selection bits Synchronous clock selection bit Serial I/O port selection bit SRDY signal output selection bit SRDY signal selection bit Serial I/O byte specify mode selection bit P15/SOUT , SRDY output structure selection bit 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : f(XIN)/32 or f(XCIN)/32 1 1 : f(XIN)/512 or f(XCIN)/512 (Note) 0 : External clock 1 : Internal clock 0 : Ordinary I/O port (P15, P16) 1 : Serial I/O port (SOUT , CLK pin) 0 : Ordinary I/O port(P17) 1 : SRDY signal output pin 0 : SRDY signal 1 : SARDY signal 0 : Ordinary mode 1 : Byte specify mode 0 : CMOS output 1 : N-channel open-drain output Since the 7470 group is not provided with the sub-clock generating circuit, do not select f(X Note: 00DC 16] CIN).

7470/7471/7477/7478 GROUP USER’S MANUAL3-6 APPENDIX Fig. 3.1.10 Structure of Serial I/O counter and Byte counter Fig. 3.1.9 Structure of Serial I/O register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O register (SIO) [Address B Function At resetR W Serial I/O register (7470/7471 group) to A value of “0016” to “FF16” can be set as transmit data. At the transmit, data is transmitted one bit at a time starting with the least significant bit. At the receive, data is received one bit at a time starting with the most significant bit. At transmit: At receive: 00DD 16] b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O counter and Byte counter [Address B Function At resetRW Serial I/O counter and Byte counter (7470/7471 group) to Byte counter to 6 5? ?? 5 When using the byte specification mode, set a value of “0016” to “0F16.” Supposing that the value to be written into the byte counter is “n,” a Serial transmit/receive is performed with the clock of the “n + 1”-th byte. Serial I/O counter When the internal clock is selected as a synchronous clock, this counter generates 8 shift clocks. When transmit data is written into the Serial I/O register, “07 16” is set in the Serial I/O counter. Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. 00DE 16]

3-77470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.1.12 Structure of Serial I/O status register Fig. 3.1.11 Structure of Transmit/receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/receive buffer register (TB/RB) [Address B Function At resetR W Transmit/receive buffer register (7477/7478 group) to A value of “0016” to “FF16” can be set as transmit data. The transmit data is transferred automatically by writing the transmit data into the Transmit shift register. When all receive data has been input into the Receive shift register, the receive data is automatically trans- ferred to the receive buffer register. At transmit: At receive: 00E0 16] b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O status register (SIOSTS) [Address B At resetR W Serial I/O status register (7477/7478 group) Name Function Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “1.” Summing error flag (SE) 0 : (OE) U (PE) U (FE) = 0 1 : (OE) U (PE) U (FE) = 1 0 5 00E1 16]

7470/7471/7477/7478 GROUP USER’S MANUAL3-8 APPENDIX Fig. 3.1.13 Structure of Serial I/O control register Fig. 3.1.14 Structure of UART control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address B At resetRW Serial I/O control register (7477/7478 group) Name Function BRG count source selection bit (CSS) 0 : f(XIN)/4 or f(XCIN)/4 1 : f(XIN)/16 or f(XCIN)/16 Serial I/O synchronous clock selection bit (SCS) Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O enable bit (SIOE) Serial I/O mode selection bit (SIOM) S RDY output enable bit (SRDY) ] In the UART mode, this bit is invalid.

• In clock synchronous mode 0 : BRG output divided by 4 1 : External clock input
• In UART mode 0 : BRG output divided by 16 1 : External clock input divided by 16 0 : P17/SRDY pin operates as ordinary I/O pin 1 : P17/SRDY pin operates as SRDY output pin 0 : When transmit buffer has emptied 1 : When transmit shift operation is completed 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : Clock asynchronous serial I/O (UART) 1 : Clock synchronous 0 : Serial I/O disabled (pins operates as ordinary I/O pins P14–P17) 1 : Serial I/O enabled (pins operates as serial I/O pins RXD - SRDY ) (Note) Note:Port P14–P17 are operates as the serial I/O pin only when the serial I/O enable bit is “1” (enable state). At this time, Port P17 is also used as an ordinary I/O port. In the UART mode, port P16 is used as an ordinary I/O port when the internal clock is selected. 00E2 16] b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address B At resetRW UART control register (7477/7478 group) to Name Function Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “1.” Parity selection bit (PARS) 0: Even parity 1: Odd parity 1111 00E3 16]

3-97470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.1.16 Structure of Timer FF register Fig. 3.1.15 Structure of Timers 1 to 4 Note : b7 b6 b5 b4 b3 b2 b1 b0 Timer 1, Timer 2, Timer 3, Timer 4 (T1, T2, T3, T4) [Address 00F016, 00F116, 00F216, B Function At resetRW to

• Set “0016 to FF16.”
• The value is decremented by 1 each time a count source is input.
• Each Timer values are set to the respective counter.
• The count values are read out by reading the respective timer. (Note) Timers 1 to 4 Timers 1 and 2 are undefined. Timer 3 is “FF 16.” Timer 4 is “0716.” 00F316] b7 b6 b5 b4 b3 b2 b1 b0 NameB Function Timer 1 division flip-flop At resetR W Timer FF register (TF) [Address Timer FF register Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. to ? 5? Timer 4 division flip-flop 0 : Initial value is “0” 1 : Initial value is “1” 0 : Initial value is “0” 1 : Initial value is “1” 00F7 16]

7470/7471/7477/7478 GROUP USER’S MANUAL3-10 APPENDIX Fig. 3.1.18 Structure of Timer 34 mode register Fig. 3.1.17 Structure of Timer 12 mode register b7 b6 b5 b4 b3 b2 b1 b0 NameB Function Timer 12 mode register (T12M) [Address Timer 12 mode register 6, 7 b7 b6 Timer 1 count stop bit At resetR W Timer 1 count source selection bit Timer 1 internal clock source selection bit P12/T0 port output selection bit Timer 2 count stop bit Timer 2 count source selection bit Timer 2 internal clock source selection bits 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : P32/CNTR 0 external clock 0 : f(XIN)/16 or f(XCIN)/16 1 : f(XCIN) (Note 2) 0 : P12 port output 1 : T0(Timer 1 overflow divided by 2) 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : Timer 1 overflow signal 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XIN)/64 or f(XCIN)/64 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 : f(XIN)/256 or f(XCIN)/256 (Note 3) Notes 1: In the 7470/7477 group, the internal clock is f(X Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X 00F8 16] IN)/16. CIN) cannot be used. Fix this bit to “0.” CIN) cannot be used. b7 b6 b5 b4 b3 b2 b1 b0 NameB Function At resetR Timer 34 mode register (T34M) [Address Timer 34 mode register Timer 3 count stop bit W Timer 3 count source selection bits Timer 4 count stop bit Timer 4 count source selection bits Timer 4 pulse width measurement mode selection bit 0 : Count start 1 : Count stop 0 : Count start 1 : Count stop Notes 1: When Timer 1 overflow is selected as a Timer 2 count source, the Timer 4 count source is the Timer 1 overflow regardless of the value of bit 6 of the Timer mode register 2. Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X CIN) cannot be used. 1, 2 b2 b1 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XCIN) 1 0 : Timer 1 overflow or Timer 2 overflow 1 1 : P3 3/CNTR 1 external clock (Note 2) b4 b3 0 0 : Timer 3 overflow 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : Timer 1 overflow or Timer 2 overflow 1 1 : P3 3/CNTR 1 external clock (Notes 1, 2) 0 : Timer mode 1 : External pulse width measurement mode P13/T1 port output selection bit 0 : P13 port 1 : T1(Timer 4 overflow divided by 2 or PWM output) 4, 5 00F916]

3-117470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.1.20 Structure of CPU mode register Fig. 3.1.19 Structure of Timer mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 NameB Function At resetR W Timer mode register 2 (TM2) [Address 6 0 7 0 Timer 1 overflow FF set enable bit to Timer mode register 2 Timer 4 overflow FF set enable bit Nothing is allocated for these bits. These are write disabled bits and are undefined at reading. Timer 3, timer 4 count overflow signal selection bit Timer 3, timer 4 function selection bit 0 : Set disable 1 : Set enable 0 : Set disable 1 : Set enable 0 : Timer 1 overflow 1 : Timer 2 overflow 0 : Ordinary mode 1 : PWM mode ?? 5 00FA 16] b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address B At reset R W CPU mode register 0, 1 ? 5 Name Function Fix these bits to “0.” Nothing is allocated for this bit. This is write enabled bit and is undefined at reading. Main clock (XIN–XOUT ) stop bit XCOUT drive capacity selection bit 0Stack page selection bit Internal system clock selection bit 0: In page 0 area 1: In page 1 area (Note 1) 0: Low 1: High (Note 2) 0: Oscillates 1: Stops (Note 2) 0: X IN–XOUT selected (Ordinary mode) 1: XCIN–XCOUT selected (Low speed mode) (Note 2) P50, P51/XCIN,XCOUT selection bit 0: P50, P51 1: XCIN, XCOUT (Note 2) Notes 1: In the products having a RAM capacity of 192 bytes or less, set this bit to “0.” Since the 7470/7477 group is not provided with the sub-clock generating circuit, f(X Fix these bits to “0.” 00FB 16] CIN) cannot be used.

7470/7471/7477/7478 GROUP USER’S MANUAL3-12 APPENDIX Fig. 3.1.22 Structure of Interrupt request register 2 Fig. 3.1.21 Structure of Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IR1) [Address B Name Function At resetRW Interrupt request register 1 0 0 : No interrupt request 1 : Interrupt requested 0 ]Timer 1 interrupt request bit Serial I/O receive interrupt request bit (7477/7478 group)(Note) 5 0 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Note: ] : 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested Serial I/O transmit interrupt request bit (7477/7478 group) In the 7470/7471group, nothing is allocated for bit 5. This is write disabled bit and is undefined at reading. “0” is set by software, but not “1.” Serial I/O interrupt request bit (7470/7471group) 00FC 16] b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IR2) [Address B Name Function At resetRW Interrupt request register 2 0 0 : No interrupt request 1 : Interrupt requested 0 ]INT0 interrupt request bit ] : 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested 5Nothing is allocated for these bits. There are write disabled bits and are undefined at reading. “0” is set by software, but not “1.” 00FD 16]

3-137470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.1.24 Structure of Interrupt control register 2 Fig. 3.1.23 Structure of Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (IE1) [Address B Name Function At resetRW Interrupt control register 1 0 0 : Interrupt disabled 1 : Interrupt enabled 0Timer 1 interrupt enable bit Note: Serial I/O receive interrupt enable bit (7477/7478 group) (Note) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O interrupt enable bit (7470/7471 group) Serial I/O transmit interrupt enable bit (7477/7478 group) Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. In the 7470/7471 group, Nothing is allocated for bit 5. This is write disabled bit and undefined at reading. 00FE 16] b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (IE2) [Address B Name Function At resetRW Interrupt control register 2 0 0 : Interrupt disabled 1 : Interrupt enabled 0INT0 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 5Nothing is allocated for these bits. There are write disabled bits and are undefined at reading. 00FF 16]

7470/7471/7477/7478 GROUP USER’S MANUAL3-14 APPENDIX

3.2 Mask ROM ordering method

GZZ-SH02-91B<9YA0> Receipt

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37470M2-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. 27128 27256 000016 000F16 001016 2FFF16 300016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37470M2–’ to addresses 000016 to 000F16. ASCII codes ‘M37470M2–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘0’ = 3016 ‘M’ = 4D16 ‘2’ = 3216 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM type (indicate the type used) 27512 000016 000F16 001016 6FFF16 700016 7FFF16 EPROM address 000016 000F16 001016 EFFF16 F00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37470M2–’ Area for ASCII codes of the name of the product ‘M37470M2–’ Area for ASCII codes of the name of the product ‘M37470M2–’ ROM (4K) ROM (4K) ROM (4K)

3-157470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M37470M2-XXXSP MITSUBISHI ELECTRIC Mask ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (32P4B for M37470M2-XXXSP) and attach to the mask ROM confirmation form. 27256 27512 a*=a$8000 a .BYTEa ‘M37470M2–’ a*=a$0000 a .BYTEa ‘M37470M2–’ 27128 a*=a$C000 a .BYTEa ‘M37470M2–’ EPROM type The pseudo-command h 3. Comments GZZ-SH02-91B<9YA0> (2/2)

7470/7471/7477/7478 GROUP USER’S MANUAL3-16 APPENDIX GZZ-SH02-92B<9YA0> Receipt SINGLE-CHIP MICROCOMPUTER M37470M4-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37470M4–’ to addresses 000016 to 000F16. ASCII codes ‘M37470M4–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘0’ = 3016 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM type (indicate the type used) 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37470M4–’ Area for ASCII codes of the name of the product ‘M37470M4–’ Area for ASCII codes of the name of the product ‘M37470M4–’ ROM (8K) ROM (8K) ROM (8K)

3-177470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M37470M4-XXXSP MITSUBISHI ELECTRIC Mask ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (32P4B for M37470M4-XXXSP) and attach to the mask ROM confirmation form. 27256 27512 a*=a$8000 a .BYTEa ‘M37470M4–’ a*=a$0000 a .BYTEa ‘M37470M4–’ 27128 a*=a$C000 a .BYTEa ‘M37470M4–’ EPROM type The pseudo-command h 3. Comments (2/2) GZZ-SH02-92B<9YA0>

7470/7471/7477/7478 GROUP USER’S MANUAL3-18 APPENDIX GZZ-SH02-93B<9YA0> Receipt SINGLE-CHIP MICROCOMPUTER M37470M8-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37470M8–’ to addresses 000016 to 000F16. ASCII codes ‘M37470M8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘0’ = 3016 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM type (indicate the type used) 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37470M8–’ ROM (16K) Area for ASCII codes of the name of the product ‘M37470M8–’ ROM (16K)

3-197470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37470M8–’ a*=a$0000 a .BYTEa ‘M37470M8–’ SINGLE-CHIP MICROCOMPUTER M37470M8-XXXSP MITSUBISHI ELECTRIC Mask ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (32P4B for M37470M8-XXXSP) and attach to the mask ROM confirmation form. h 3. Comments GZZ-SH02-93B<9YA0>

7470/7471/7477/7478 GROUP USER’S MANUAL3-20 APPENDIX GZZ-SH02-94B<9YB0> Receipt Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : 27128 27256 000016 000F16 001016 2FFF16 300016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37471M2–’ to addresses 000016 to 000F16. ASCII codes ‘M37471M2–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘1’ = 3116 ‘M’ = 4D16 ‘2’ = 3216 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM type (indicate the type used) Microcomputer name : M37471M2-XXXFP 27512 000016 000F16 001016 6FFF16 700016 7FFF16 EPROM address 000016 000F16 001016 EFFF16 F00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37471M2–’ Area for ASCII codes of the name of the product ‘M37471M2–’ Area for ASCII codes of the name of the product ‘M37471M2–’ ROM (4K) ROM (4K) ROM (4K) SINGLE-CHIP MICROCOMPUTER M37471M2-XXXSP/FP MITSUBISHI ELECTRIC

3-217470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37471M2-XXXSP, 56P6N for M37471M2-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 a*=a$8000 a .BYTEa ‘M37471M2–’ a*=a$0000 a .BYTEa ‘M37471M2–’ 27128 a*=a$C000 a .BYTEa ‘M37471M2–’ EPROM type The pseudo-command h 3. Comments (2/2) GZZ-SH02-94B<9YB0> SINGLE-CHIP MICROCOMPUTER M37471M2-XXXSP/FP MITSUBISHI ELECTRIC

7470/7471/7477/7478 GROUP USER’S MANUAL3-22 APPENDIX GZZ-SH02-95B<9YB0> Receipt SINGLE-CHIP MICROCOMPUTER M37471M4-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37471M4–’ to addresses 000016 to 000F16. ASCII codes ‘M37471M4–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘1’ = 3116 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM type (indicate the type used) M37471M4-XXXFP 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37471M4–’ Area for ASCII codes of the name of the product ‘M37471M4–’ Area for ASCII codes of the name of the product ‘M37471M4–’ ROM (8K) ROM (8K) ROM (8K)

3-237470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M37471M4-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH02-95B<9YB0> Mask ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37471M4-XXXSP, 56P6N for M37471M4-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 a*=a$8000 a .BYTEa ‘M37471M4–’ a*=a$0000 a .BYTEa ‘M37471M4–’ 27128 a*=a$C000 a .BYTEa ‘M37471M4–’ EPROM type The pseudo-command h 3. Comments

7470/7471/7477/7478 GROUP USER’S MANUAL3-24 APPENDIX GZZ-SH02-96B<9YB0> Receipt SINGLE-CHIP MICROCOMPUTER M37471M8-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37471M8–’ to addresses 000016 to 000F16. ASCII codes ‘M37471M8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘1’ = 3116 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM type (indicate the type used) M37471M8-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37471M8–’ Area for ASCII codes of the name of the product ‘M37471M8–’ ROM (16K) ROM (16K)

3-257470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37471M8–’ a*=a$0000 a .BYTEa ‘M37471M8–’ SINGLE-CHIP MICROCOMPUTER M37471M8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH02-96B<9YB0> Mask ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37471M8-XXXSP, 56P6N for M37471M8-XXXFP) and attach to the mask ROM confirmation form. h 3. Comments

7470/7471/7477/7478 GROUP USER’S MANUAL3-26 APPENDIX (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M37477M4–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. data ROM 8192 bytes M37477M4-XXXSP GZZ-SH06-67B<2XA1> Receipt SINGLE-CHIP MICROCOMPUTER M37477M4-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘7’ = 3716 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM type (indicate the type used) Microcomputer name : M37477M4-XXXFP 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Product name ASCII code : ‘M37477M4–’ Product name ASCII code : ‘M37477M4–’ data ROM 8192 bytes data ROM 8192 bytes Product name ASCII code : ‘M37477M4–’

3-277470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M37477M4-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH06-67B<2XA1> Mask ROM number We recommend the use of the following pseudo-command to set the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (32P4B for M37477M4-XXXSP, 32P2W for M37477M4-XXXFP) and attach it to the mask ROM confirmation form. 27256 27512 a*=a$8000 a .BYTEa ‘M37477M4–’ a*=a$0000 a .BYTEa ‘M37477M4–’ 27128 a*=a$C000 a .BYTEa ‘M37477M4–’ EPROM type The pseudo-command h 3. Comments (2/2)

7470/7471/7477/7478 GROUP USER’S MANUAL3-28 APPENDIX GZZ-SH06-68B<2XA1> Receipt SINGLE-CHIP MICROCOMPUTER M37477M8-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27256 27512 M37477M8-XXXSP M37477M8-XXXFP Checksum code for entire EPROM (hexadecimal notation) (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M37477M8–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘7’ = 3716 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) data ROM 16384 bytes 000016 000F16 001016 3FFF16 400016 7FFF16 Product name ASCII code : ‘M37477M8–’ data ROM 16384 bytes 000016 000F16 001016 BFFF16 C00016 FFFF16 Product name ASCII code : ‘M37477M8–’

3-297470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37477M8–’ a*=a$0000 a .BYTEa ‘M37477M8–’ SINGLE-CHIP MICROCOMPUTER M37477M8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH06-68B<2XA1> Mask ROM number 27256 27512EPROM type The pseudo-command (2/2) h 3. Comments We recommend the use of the following pseudo-command to set the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (32P4B for M37477M8-XXXSP, 32P2W for M37477M8-XXXFP) and attach it to the mask ROM confirmation form.

7470/7471/7477/7478 GROUP USER’S MANUAL3-30 APPENDIX GZZ-SH06-70B<2XA0> Receipt SINGLE-CHIP MICROCOMPUTER M37478M4-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478M4-XXXSP M37478M4-XXXFP Checksum code for entire EPROM (hexadecimal notation) (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M37478M4–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘8’ = 3816 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM type (indicate the type used) data ROM 8192 bytes 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 EPROM address 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Product name ASCII code : ‘M37478M4–’ Product name ASCII code : ‘M37478M4–’ data ROM 8192 bytes data ROM 8192 bytes Product name ASCII code : ‘M37478M4–’

3-317470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M37478M4-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH06-70B<2XA0> Mask ROM number (2/2) 27256 27512 a*=a$8000 a .BYTEa ‘M37478M4–’ a*=a$0000 a .BYTEa ‘M37478M4–’ 27128 a*=a$C000 a .BYTEa ‘M37478M4–’ EPROM type The pseudo-command h 3. Comments We recommend the use of the following pseudo-command to set the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M37478M4-XXXSP, 56P6N for M37478M4-XXXFP) and attach it to the mask ROM confirmation form.

7470/7471/7477/7478 GROUP USER’S MANUAL3-32 APPENDIX GZZ-SH06-71B<2XA0> Receipt SINGLE-CHIP MICROCOMPUTER M37478M8-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27256 27512 M37478M8-XXXSP M37478M8-XXXFP Checksum code for entire EPROM (hexadecimal notation) (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M37478M8–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘8’ = 3816 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) Product name ASCII code : ‘M37478M8–’ data ROM 16384 bytes Product name ASCII code : ‘M37478M8–’ data ROM 16384 bytes

3-337470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37478M8–’ a*=a$0000 a .BYTEa ‘M37478M8–’ SINGLE-CHIP MICROCOMPUTER M37478M8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH06-71B<2XA0> Mask ROM number 27256 27512EPROM type The pseudo-command (2/2) We recommend the use of the following pseudo-command to set the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M37478M8-XXXSP, 56P6N for M37478M8-XXXFP) and attach it to the mask ROM confirmation form. h 3. Comments

7470/7471/7477/7478 GROUP USER’S MANUAL3-34 APPENDIX

3.3 ROM programming ordering method

EPROM address EPROM address EPROM address EPROM type (indicate the type used) GZZ-SH03-60B<06A0> Receipt

740 FAMILY ROM PROGRAMMING CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37470E4-XXXSP MITSUBISHI ELECTRIC ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37470E4–’ to addresses 000016 to 000F16. ASCII codes ‘M37470E4–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘0’ = 3016 ‘E’ = 4516 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 27512 000016 000F16 001016 5FFF16 600016 7FFF16 000016 000F16 001016 DFFF16 E00016 FFFF16 Area for ASCII codes of the name of the product ‘M37470E4–’ Area for ASCII codes of the name of the product ‘M37470E4–’ Area for ASCII codes of the name of the product ‘M37470E4–’ ROM (8K) ROM (8K) ROM (8K) h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.

3-357470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M37470E4-XXXSP MITSUBISHI ELECTRIC GZZ-SH03-60B<06A0> ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer). 27256 27512 a*=a$8000 a .BYTEa ‘M37470E4–’ a*=a$0000 a .BYTEa ‘M37470E4–’ 27128 a*=a$C000 a .BYTEa ‘M37470E4–’ EPROM type The pseudo-command h 3. Comments

7470/7471/7477/7478 GROUP USER’S MANUAL3-36 APPENDIX EPROM address EPROM address EPROM type (indicate the type used) GZZ-SH02-97B<9YA0> Receipt SINGLE-CHIP MICROCOMPUTER M37470E8-XXXSP MITSUBISHI ELECTRIC ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37470E8–’ to addresses 000016 to 000F16. ASCII codes ‘M37470E8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘0’ = 3016 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 000016 000F16 001016 BFFF16 C00016 FFFF16 Area for ASCII codes of the name of the product ‘M37470E8–’ ROM (16K) Area for ASCII codes of the name of the product ‘M37470E8–’ ROM (16K)

3-377470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37470E8–’ a*=a$0000 a .BYTEa ‘M37470E8–’ SINGLE-CHIP MICROCOMPUTER M37470E8-XXXSP MITSUBISHI ELECTRIC GZZ-SH02-97B<9YA0> ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. 27256 27512EPROM type The pseudo-command (2/2) h 3. Comments Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer).

7470/7471/7477/7478 GROUP USER’S MANUAL3-38 APPENDIX EPROM addressEPROM address EPROM address EPROM type (indicate the type used) M37471E4-XXXSP GZZ-SH03-59B<06B0> Receipt SINGLE-CHIP MICROCOMPUTER M37471E4-XXXSP/FP MITSUBISHI ELECTRIC ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37471E4–’ to addresses 000016 to 000F16. ASCII codes ‘M37471E4–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘1’ = 3116 ‘E’ = 4516 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) M37471E4-XXXFP 27512 000016 000F16 001016 5FFF16 600016 7FFF16 000016 000F16 001016 DFFF16 E00016 FFFF16 Area for ASCII codes of the name of the product ‘M37471E4–’ Area for ASCII codes of the name of the product ‘M37471E4–’ Area for ASCII codes of the name of the product ‘M37471E4–’ ROM (8K) ROM (8K) ROM (8K)

3-397470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX SINGLE-CHIP MICROCOMPUTER M37471E4-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH03-59B<06B0> ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. (2/2) 27256 27512 a*=a$8000 a .BYTEa ‘M37471E4–’ a*=a$0000 a .BYTEa ‘M37471E4–’ 27128 a*=a$C000 a .BYTEa ‘M37471E4–’ EPROM type The pseudo-command h 3. Comments Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for M37471E4-XXXSP or the 56P6N Mark Specification Form the M37471E4-XXXFP.

7470/7471/7477/7478 GROUP USER’S MANUAL3-40 APPENDIX EPROM address EPROM address EPROM type (indicate the type used) M37471E8-XXXSP GZZ-SH02-98B<9YB0> Receipt SINGLE-CHIP MICROCOMPUTER M37471E8-XXXSP/FP MITSUBISHI ELECTRIC ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37471E8–’ to addresses 000016 to 000F16. ASCII codes ‘M37471E8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘1’ = 3116 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) M37471E8-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 000016 000F16 001016 BFFF16 C00016 FFFF16 Area for ASCII codes of the name of the product ‘M37471E8–’ Area for ASCII codes of the name of the product ‘M37471E8–’ ROM (16K) ROM (16K)

3-417470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37471M8–’ a*=a$0000 a .BYTEa ‘M37471M8–’ SINGLE-CHIP MICROCOMPUTER M37471E8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH02-98B<9YB0> ROM number Recommend to writing the following pseudo-command to the start address of the assembler source program. 27256 27512EPROM type The pseudo-command (2/2) h 3. Comments Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37471E8-XXXSP or the 56P6N Mark Specification Form for the M37471E8-XXXFP.

7470/7471/7477/7478 GROUP USER’S MANUAL3-42 APPENDIX GZZ-SH06-79B<2XA1> Receipt SINGLE-CHIP MICROCOMPUTER M37477E8-XXXSP/FP MITSUBISHI ELECTRIC ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27256 27512 M37477E8-XXXSP M37477E8-XXXFP Checksum code for entire EPROM (hexadecimal notation) (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M37477E8–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘7’ = 3716 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) data ROM 16384 bytes 000016 000F16 001016 3FFF16 400016 7FFF16 Product name ASCII code : ‘M37477E8–’ data ROM 16384 bytes 000016 000F16 001016 BFFF16 C00016 FFFF16 Product name ASCII code : ‘M37477E8–’

3-437470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37477E8–’ a*=a$0000 a .BYTEa ‘M37477E8–’ SINGLE-CHIP MICROCOMPUTER M37477E8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH06-79B<2XA1> ROM number We recommend the use of the following pseudo-command to the start address of the assembler source program. 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM will not be processed. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37477E8-XXXSP or the 32P2W Mark Specification Form for the M37477E8-XXXFP. h 3. Comments

7470/7471/7477/7478 GROUP USER’S MANUAL3-44 APPENDIX GZZ-SH06-81B<2XA0> Receipt SINGLE-CHIP MICROCOMPUTER M37478E8-XXXSP/FP MITSUBISHI ELECTRIC ROM number Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : 27256 27512 M37478E8-XXXSP M37478E8-XXXFP Checksum code for entire EPROM (hexadecimal notation) (1) Set the data in the unused area (the shaded area of the diagram) to “FF16”. (2) The ASCII codes of the product name “M37478E8–” must be entered in addresses 000016 to 000816. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘7’ = 3716 ‘8’ = 3816 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 (1/2) EPROM address EPROM address EPROM type (indicate the type used) Product name ASCII code : ‘M37478E8–’ data ROM 16384 bytes Product name ASCII code : ‘M37478E8–’ data ROM 16384 bytes

3-457470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX a*=a$8000 a .BYTEa ‘M37478E8–’ a*=a$0000 a .BYTEa ‘M37478E8–’ SINGLE-CHIP MICROCOMPUTER M37478E8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH06-81B<2XA0> ROM number We recommend the use of the following pseudo-command to the start address of the assembler source program. 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM will not be processed. (2/2) h 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37478E8-XXXSP or the 56P6N Mark Specification Form for the M37478E8-XXXFP. h 3. Comments

7470/7471/7477/7478 GROUP USER’S MANUAL3-46 APPENDIX 32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo. Special logo required Mitsubishi lot number (6-digit or 7-digit) q Mitsubishi IC catalog name C. Special Mark Required q B. Customer’s Parts Number + Mitsubishi catalog name Mitsubishi lot number (6-digit or 7-digit) q Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,  , . (periods), and , (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required

3-477470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX 32P2W-A (32-PIN SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark Mitsubishi lot number (6-digit or 7-digit) q C. Special Mark Required B. Customer’s Parts Number + Mitsubishi catalog name Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) q q 3 : The standard Mitsubishi font is used for all characters except for a logo. Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 13 characters : . (periods),, (com- mas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required

7470/7471/7477/7478 GROUP USER’S MANUAL3-48 APPENDIX q q Mitsubishi lot number (6-digit or 7-digit) Mitsubishi lot number (6-digit or 7-digit) q 42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo. Special logo required Mitsubishi IC catalog name C. Special Mark Required B. Customer’s Parts Number + Mitsubishi catalog name Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 15 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,  , . (periods), and , (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required

3-497470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX (6-digit or 7-digit) q 56P6N-A (56-PIN QFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark B. Customer’s Parts Number + Mitsubishi IC catalog name q Mitsubishi IC catalog name Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 11 characters : . (period), and , (comma) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required 3 : The standard Mitsubishi font is used for all characters except for a logo. 5 : Arrangement of Mitsubishi IC catalog name and Mitsubishi lot number is dependent on number of Mitsubishi IC catalog name and that Mitsubishi logo is required or not. Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required C. Special Mark Required q

7470/7471/7477/7478 GROUP USER’S MANUAL3-50 APPENDIX Enter the catalog number of the microcomputer for which this mark specification is intended. (If you do not know the ROM code number, enter XXX in its place.) The catalog number of the microcomputer A. Standard Mitsubishi Mark Customer specified part number will be printed together with the ROM code number on the top line. Enter the desired part number left aligned in the box below. (up to 10 characters) SHRINK DIP MARK SPECIFICATION FORM for One Time PROM version microcomputers M Mitsubishi lot number (6-digit or 7-digit) Mitsubishi catalog name (blank model number before writing) RXXX Note2 : Note1 : The following characters can be used in the part number : Uppercase alphabet, numbers, ampersand, hyphen, period, comma, +, /, (, ),  ( will be printed at 1.5 x character width) 2 : XXX is the ROM code number. B. Special Mark Required If you desire anything other than the standard Mitsubishi mark, it will be treated as a special mark. Special marks will take longer to produce and should be avoided if possible. If a special mark is to be printed, indicate the desired layout of the mark in the figure below. The layout will be duplicated as closely as possible. Note1 : If the customer’s trademark logo must be used in the Special Mark, please submit a clean original logo. Note that special marks require extra cost and time to produce.

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7470/7471/7477/7478 GROUP USER’S MANUAL3-52

3-537470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Figure 3.6.1 shows the special function register (SFR) memory map. Fig. 3.6.1 SFR memory map 00E0 16 00E1 16 00E2 16 00E3 16 00E4 16 00E5 16 00E6 16 00E7 16 00E8 16 00E9 16 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 (Note 2) Transmit/receive buffer register Serial I/O control register Baud rate generator Port P0 direction register Port P1 direction register Port P2 direction register (Note 1) Port P4 direction register Serial I/O status register UART control register 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 Port P0 pull-up control register Edge polarity selection register Input latch register A-D conversion register Serial I/O mode register Serial I/O counter Timer 1 Timer 3 Timer 12 mode register Timer mode register 2 Interrupt request register 1 Interrupt control register 1 Port P1-P5 pull-up control register (Note 3) A-D control register Serial I/O register Timer 2 Timer 4 Timer FF register Timer 34 mode register CPU mode register Interrupt request register 2 Interrupt control register 2 Byte counter (Note 5) (Note 4) Notes 1: In the 7477/7478 group, this register is not located. 2: In the 7470/7477 group, this register is not located. 3: This address is allocated P1-P4 pull-up control register for the 7470/7477 group. 4: In the 7477/7478 group, this register is not located. 5: In the 7470/7471 group, this register is not located.

7470/7471/7477/7478 GROUP USER’S MANUAL3-54 APPENDIX Fig. 3.7.1 Pin configuration of 7470 group P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37470M8-XXXSP M37470E8-XXXSP P17/SRDY RESET Outline 32P4B (Note) Note: The M37470M2-XXXSP and M37470M4/E4-XXXSP are included in the 32P4B package. All of these products are pin-compatible.

3-557470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.7.2 Pin configuration of 7471 group P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P30/INT0 P20/IN0 VREF VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/S RDY RESET NC NC NC NCNC NC M37471M8-XXXFP M37471E8-XXXFP P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 M37471M8-XXXSP M37471E8-XXXSP M37471E8SS P30/INT0 P51/XCOUT P50/XCIN VCC P20/IN0 VREF XIN XOUT VSS P17/S RDY RESET Outline 56P6N-A (Note 2) NC: No connection Outline 42P4B (Note 1) 42S1B-A (M37471E8SS) Notes 1 :The M37471M2-XXXSP and M37471M4/E4-XXXSP are included in the 42P4B package. All of these products are pin-compatible. 2 :The M37471M2-XXXFP and M37471M4/E4-XXXFP are included in the 56P6N-A package. All of these products are pin-compatible. 3 :The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.

7470/7471/7477/7478 GROUP USER’S MANUAL3-56 APPENDIX Fig. 3.7.3 Pin configuration of 7477 group P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37477M8-XXXSP M37477E8-XXXSP P17/SRDY RESET Outline 32P4B (Note 1) Notes 1 : The M37477M4-XXXSP is included in the 32P4B package. 2 : The M37477M4-XXXFP is included in the 32P2W-A package. 3 : The only differences between the 32P4B package product and the 32P2W-A package product are package shape and absolute maximum ratings. P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 VCC P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37477M8-XXXFP M37477E8-XXXFP P17/SRDY RESET Outline 32P2W-A (Note 2) These products are pin-compatible. These products are pin-compatible.

3-577470/7471/7477/7478 GROUP USER’S MANUAL APPENDIX Fig. 3.7.4 Pin configuration of 7478 group P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P30/INT0 P20/IN0 VREF VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/S RDY RESET NC NC NC NCNC NC M37478M8-XXXFP M37478E8-XXXFP P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 M37478M8-XXXSP M37478E8-XXXSP M37478E8SS P30/INT0 P51/XCOUT P50/XCIN VCC P20/IN0 VREF XIN XOUT VSS P17/SRDY RESET Outline 56P6N-A (Note 2) NC: No connection Outline 42P4B (Note 1) 42S1B-A(M37478E8SS) Notes1 : The M37478M4-XXXSP is included in the 42P4B package. 2 : The M37478M4-XXXFP is included in the 56P6N-A package. 3 : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AV SS pin. These products are pin-compatible These products are pin-compatible

USER’S MANUAL 7470/7471/7477/7478 Group Jan. First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1998 MITSUBISHI ELECTRIC CORPORATION

User’s Manual 7470/7471/7477/7478 Group © 1998 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Jan. 1998. Specifications subject to change without notice.

Rev. Rev. No. date

1.0 First Edition 980131

REVISION DESCRIPTION LIST 7470/71, 7477/78 USER’S MANUAL (1/1) Revision Description