M37272E8FP

M3727GM6 RENESAS | Alldatasheet

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER REJ03B0132-0100Z Rev.1.00 Apr 01, 2001 Rev.1.00 Apr 01, 2001 page 1 of 127 REJ03B0132-0100Z M3727GM6/M8–XXXSP/FP M37272E8SP/FP 1. DESCRIPTION The M3727GM6/M8-XXXSP/FP are single-chip microcomputers de- signed with CMOS silicon gate technology. They have a OSD, data slicer, and I 2C-BUS interface, so it is useful for a channel selection system for TV with a closed caption decoder. The features of the M37272E8SP/FP are similar to those of the M3727GM6/M8-XXXSP/FP except that these chips have a built-in PROM which can be written electrically. The difference between M3727GM6-XXXSP/FP and M3727GM8-XXXSP/FP are the ROM size and RAM size. Accordingly, the following descriptions will be for the M3727GM6-XXXSP/FP. 2. FEATURES

• Memory size (M3727GM6-XXXSP/FP ) 32K bytes (M3727GM8-XXXSP/FP, M37272E8SP/FP) (M3727GM6-XXXSP/FP ) 1152 bytes (M3727GM8-XXXSP/FP, M37272E8SP/FP) (*ROM correction memory included)
• Minimum instruction execution time
• Power dissipation (at VCC = 5.5V, 8 MHz oscillation frequency, OSD on, and Dataslicer on) (at V CC = 5.5V, 32 kHz oscillation frequency)
• Closed caption data slicer
• OSD function (It is possible to display 3 lines or more by software) OSD mode: 16 ✕ 20 dots OSD mode: 8 kinds Display position Horizontal: 128 levels Vertical: 512 levels CC mode: smooth italic, underline, flash, automatic solid space OSD mode: border Smoth roll-up Window function 3. APPLICATION TV with a closed caption decoder

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 2 of 127 REJ03B0132-0100Z 8.12 TABLE OF CONTENTS 14. MULTI-MASTER I 2C-BUS BUS LINE CHARACTERISTICS ....99

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 3 of 127 REJ03B0132-0100Z P06/INT2/AD4 XOUT P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 HL F VHOLD CV IN CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC P17/AD3 M3727GM6/M8-XXXSP M37272E8SP (AVCC )NC( ) ...M37272E8SP 4. PIN CONFIGURATION Outline 42P4B Fig. 4.1 Pin Configuration (1) (Top View) Outline 42P2R-A/E Fig. 4.2 Pin Configuration (2) (Top View) (AVCC )NC P06/INT2/AD4 XOUT P50/HSYN C P51/VSYN C P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 HL F VHOLD CV IN CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC P17/AD3 M3727GM6/M8-XXXFP M37272E8FP ( ) ...M37272E8FP Note: Only 14th pin is NC pin of M3727GM6/ M8-XXXSP. This pin is AVcc pin of M37272E8SP. But NC pin of M3727GM6/M8-XXXSP is not connect to the inside of IC. You can apply to Vcc. Note: Only 14th pin is NC pin of M3727GM6/ M8-XXXFP. This pin is AVcc pin of M37272E8FP. But NC pin of M3727GM6/M8-XXXFP is not connect to the inside of IC. You can apply to Vcc.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 4 of 127 REJ03B0132-0100Z 5. FUNCTIONAL BLOCK DIAGRAM Fig. 5.1 Functional Block Diagram of M3727G (AV CC NC ( )...M37272E8SP/FP X IN X OUT OSC1/X CIN OSC2/X COUT P0 (8) INT1 INT2 INT3 P1 (8) PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 PWM TIM2TIM3 CV IN 17 V HOLD HLF P2 (8) I/O port P1 I/O port P2 P3 (2) SDA2 SDA1 SCL2 SCL1 SI/O SIN SCLK SOUT P5 (6) Output ports P5 2–P5 Output for display 1HSYNC VSYNC R G B OUT1 OUT2 I/O ports P3 0, P3 AD1–6 Data slicer Control signal Clock input Clock output X IN X OUT Reset input V CC V SS CNV SS Pins for data slicer Clock output for OSD/sub-clock output I/O ports P2 6, P2 Clock input for OSD/sub-clock input A-D comparator 8-bit arithmetic and logical unit Accumulator A (8) Timer 6T6 (8)Timer 5T5 (8)Timer 4T4 (8)Timer 3T3 (8)Timer 2T2 (8)Timer 1T1 (8)Timer count source selection circuit Instructionregister (8)Instructiondecoder OSDcircuit Processor statusregisterPS (8) StackpointerS (8) IndexregisterY (8) IndexregisterX (8) ROM ProgramcounterPC L (8) ProgamcounterPC H (8) RAM Data bus Clock generating circuit RESET CV IN Address bus I/O port P0 ROM correction circuit Multi-masterI2C-BUS interface Input ports P5 0, P5 Synchronous signal input

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 5 of 127 REJ03B0132-0100Z Number of basic instructions Instruction execution time Clock frequency Memory size Input/Output ports Serial I/O Multi-master I2C-BUS interface A-D comparator PWM output circuit Timers ROM correction function Subroutine nesting Interrupt Clock generating circuit Data slicer ROM RAM OSD ROM OSD RAM 0–P17 P20–P27 P30, P31 P50, P51 P52–P55 M3727GM6-XXXSP/FP M3727GM8-XXXSP/FP , M37272E8SP/FP M3727GM6-XXXSP/FP M3727GM8-XXXSP/FP , M37272E8SP/FP I/O I/O I/O I/O Input Output 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre- quency)

8 MHz (maximum)

1024 bytes (ROM correction memory included) 1152 bytes (ROM correction memory included) 10K bytes 128 bytes 8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) 8-bit ✕ 1 (CMOS input/output structure, however, N-channel open-drain output structure, when P1 1–P14 are used as multi-master I2C-BUS inter- face, can be used as OSD output pin, A-D input pins, INT input pin, multi- master I2C-BUS interface) 8-bit ✕ 1 (P2 is CMOS input/output structure, however, N-channel open- drain output structure when P20 and 21 are used as serial output, can be used as serial input/output pins, timer external clock input pins, OSD clock input/output pin, sub-clock input/output pins) 2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins) 2-bit ✕ 1 (can be used as OSD input pins) 4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins) 8-bit ✕ 1 1 (2 systems) 6 channels (6-bit resolution) 8-bit ✕ 6 8-bit timer ✕ 6 2 vectors 128 levels (maximum) <17 types> INT external interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1, OSD interrupt ✕ 1, Multi-master I 2C-BUS interface interrupt ✕ 1, Data slicer interrupt ✕ 1, f(XIN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK instruction interrupt ✕ 1, reset ✕ 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz- crystal oscillator) Built-in Parameter 6. PERFORMANCE OVERVIEW Table 6.1 Performance Overview Functions

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 6 of 127 REJ03B0132-0100Z 32 characters ✕ 2 lines CC mode: 16 ✕ 26 dots (character display area : 16 ✕ 20 dots) OSD mode: 16 ✕ 20 dots 254 kinds CC mode: 1 kinds OSD mode: 8 kinds 1 screen: 8 kinds (per character unit) Horizontal: 128 levels, Vertical: 512 levels 5V ± 10% 137.5mW typ. ( at oscillation frequency f(X IN) = 8 MHz, fOSC = 27 MHz) <165mW typ. > < > ..When use M37272E8SP/FP 55mW typ. ( at oscillation frequency f(X IN) = 8 MHz) <82.5mW typ. > < > ..When use M37272E8SP/FP 0.33 mW typ. ( at oscillation frequency f(X CIN) = 32 kHz, f(XIN) = stopped) 0.055 mW ( maximum ) –10 °C to 70 °C CMOS silicon gate process 42-pin plastic molded DIP 42-pin plastic molded SSOP Power source voltage Power dissipation Number of display characters Dot structure Kinds of characters Kinds of character sizes 1 screen : 8 Character font coloring Display position Functions Table 6.2 Performance Overview (Continued) OSD function Parameter In high-speed mode In low-speed mode In stop mode Operating temperature range Device structure Package M3727GM6/M8-XXXSP, M37272E8FP M3727GM6/M8-XXXSP , M37272E8FP OSD ON OSD OFF OSD OFF Data slicer ON Data slicer OFF Data slicer OFF

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 7 of 127 REJ03B0132-0100Z Pin Name Input/ FunctionsOutput VCC , (AVCC ) Power source Apply voltage of 5 V ± 10 % to (typical) V CC (AVCC), and 0 V to VSS . VSS ( ) .. Only M37272E8SP/FP CNV SS CNV SS This is connected to VSS . RESET Reset input Input To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should be maintained for the required time. XIN Clock input Input This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT Clock output Output X OUT . If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. P00/PWM0– I/O port P0 I/O Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually P05/PWM5, programmed as input or output. At reset, this port is set to input mode. The output structure P06/INT2/AD4, is N-channel open-drain output. (See note 1) P07/INT1 PWM output Output Pins P0 0–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output structure is N-channel open-drain output. External interrupt Input Pins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 respectively. input Analog input Input P0 6 pin is also used as analog input pin AD4. P10/OUT2, I/O port P1 I/O Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output P11/SCL1, structure is CMOS output. (See note 1) P12/SCL2, OSD output Output Pins P1 0 is also used as OSD output pin OUT2. The output structure is CMOS output. P13/SDA1, Multi-master I/O Pins P1 1–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master P14/SDA2, I2C-BUS interface I 2C-BUS interface is used. The output structure is N-channel open-drain output. P15/AD1/INT3, Analog input Input Pins P1 0, P15–P17 are also used as analog input pin AD8, AD1–AD3 respectively. P16/AD2, External interrupt Input P1 5 pin is also used as INT external interrupt input pin INT3. P17/AD3 input P20/SCLK ,I /O port P2 I/O Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output P21/SOUT , structure is CMOS output. (See note 1) P22/SIN, Serial I/O synchronous I/O P2 0 pin is also used as serial I/O synchronous clock input/output pin SCLK . The output P23/TIM3, clock input/output port structure is N-channel open-drain output. P24/TIM2, Serial I/O data I/O P2 1 pin is also used as serial I/O data output pin SOUT . The output structure is open-drain P25, output output. P26/OSC1/ Serial I/O data inputInput P2 2 pin is also used as serial I/O data input pin SIN. XCIN, External clock Input Pins P23 and P24 are also used as timer external clock input pins TIM3 and TIM2 P27/OSC2/ input for timer respectively. XCOUT Clock input for OSD Input P2 6 pin is also used as OSD clock input pin OSC1. (See note 2) Clock output for OSD Output P2 7 pin is also used as OSD clock input pin OSC2. The output structure is CMOS output. (See note 2) Sub-clock input Input P2 6 pin is also used as sub-clock input pin XCIN. Sub-clock output Output P2 7 pin is also used as sub-clock output pin XCOUT . 7. PIN DESCRIPTION Table 7.1 Pin Description

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 8 of 127 REJ03B0132-0100Z Pin Name Input/ FunctionsOutput P30/AD5, I/O port P3 I/O Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port 0. P31/AD6 The output structure can be selected either CMOS output or N-channel open-drain output structure. (See notes 1, 3) Analog input Input Pins P3 0 and P31 are also used as analog input pins AD5 and AD6 respectively. P50/HSYNC , Input port P5 Input Pin P5 0 and P51 are 2-bit input ports. P51/VSYNC H SYNC input Input Pin P5 0 is also used as HSYNC input. This is a horizontal synchronous signal input for OSD. VSYNC input Input Pin P5 1 is also used as VSYNC input. This is a vertical synchronous signal input for OSD. P52/R, Output port P5 Output Ports P5 2–P55 are a 4-bit output port. The output structure is CMOS output. P53/G, P54/B, OSD output Output Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output P55/OUT1 structure is CMOS output. CV IN I/O for data slicer Input Input composite video signal through a capacitor. VHOLD Input Connect a capacitor between VHOLD and Vss. HLF I/O Connect a filter using of a capacitor and a resistor between HLF and Vss. Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 2: To switch output functions, set the raster color register and OSD control register. When pins P26 and P27 are used as the OSD clock input/output pins, set the corresponding bits of the port P2 direction register to “0” (input mode). 3: To switch output structures, set bits 2 and 3 of the port P3 direction register, When “0,” CMOS output ; when “1,” N-channel open-drain output. Table 7.2 Pin Description (continued)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 9 of 127 REJ03B0132-0100Z Fig. 7.1 I/O Pin Block Diagram (1) N-channel open-drain output Ports P00–P07 Note :Each port is also used as follows : P0 0–P05 : PWM0–PWM5 P0 6 : INT2/AD4 P0 7 : INT1 Ports P00–P07 Data bus Direction register Port latch

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 10 of 127 REJ03B0132-0100Z Fig. 7.2 I/O Pin Block Diagram (2) Internal circuit P52–P55P 50, P 51 I n t e r n a l c i r c u i t CMOS input Ports P50, P51 Note :Each pin is also used as follows : P50 : HSYNC P51 : VSYNC CMOS output Ports P52–P55 Note :Each pin is also used as follows : P52 : R P53 : G P54 : B P55 : OUT1 CMOS output Ports P1, P2, P30, P31 Notes 1:Each port is also used as follows : P10 : OUT2 P11 : SCL1 P12 : SCL2 P13 : SDA15 P14 : SDA2 P15 : AD1/INT3 P16 : AD2 P17 : AD3 2: The output structure of ports P30 and P31 can be selected either CMOS output or N-channel open- drain output structure (when selecting N-channel open-drain, it is the same with P00–P07). 3: The output structure of ports P11–P14 is N-channel open-drain output when using as multi-master I2C-BUS interface (when selecting N-channel open-drain, it is the same with P00–P07). 4: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial output (when selecting N-channel open-drain, it is the same with P00–P07). P20 : SCLK P21 : SOUT P22 : SIN P23 : TIM3 P24 : TIM2 P30 : AD5 P31 : AD6 Ports P1, P2, P30, P31 D i r e c t i o n r e g i s t e r P o r t l a t c hD a t a b u s

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 11 of 127 REJ03B0132-0100Z 8. FUNCTIONAL DESCRIPTION

8.1 CENTRAL PROCESSING UNIT (CPU)

This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used.

8.1.1 CPU Mode Register

The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allo- cated at address 00FB 16. Fig. 8.1.1 CPU Mode Register b 7b6 b 5b 4b 3 b 2b 1b 0 B A f t e r r e s e t RW CPU M ode Register 0 , 1 3, 4 Name F u n c t i o n s Processor mode bits (CM0, CM1) 0 0: Single-chip mode 0 1: 1 0: Not available 1 1: Fix these bits to “1.” 1Stack page selection bit (CM2) (See note) b1 b0 0 : 0 p a g e p a g e 1 00 5 1 6 0Main Clock (XIN–XOUT ) stop bit (CM6) C P U m o d e r e g i s t e r ( C M ) [ A d d r e s s 0 0 F B1 R W RW R W R W RW XCOUT drivability selection bit (CM5) 0 : L O W d r i v e H I G H d r i v e 0 : O s c i l l a t i n g S t o p p e d 7 0Internal system clock selection bit (CM7) RW0 : X I N – XO U T s e l e c t e d h i g h s p e e d m o d e XC I N – XC O U T s e l e c t e d h i g h s p e e d m o d e Note: This bit is set to “1” after the reset release.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 12 of 127 REJ03B0132-0100Z

8.2 MEMORY

8.2.1 Special Function Register (SFR) Area

The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.

8.2.2 RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

8.2.3 ROM

ROM is used for storing user programs as well as the interrupt vector area.

8.2.4 OSD RAM

RAM for display is used for specifying the character codes and col- ors to display.

8.2.5 OSD ROM

ROM for display is used for storing character data.

8.2.6 Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

8.2.7 Zero Page

The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.

8.2.8 Special Page

The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.

8.2.9 ROM Correction Vector

This is used as the program jump destination addresses for ROM correction. Fig. 8.2.1 Memory Map (M3727GM6/M8-XXXSP/FP, M37272E8SP/FP) 000016 00C0 16 00FF16 087F16 SFR1 area Not used FFFF 16 FFDE 16 FF0016 080016 Interrupt vector areaSpecial page OSD RAM (128 bytes) Zero page 020016 020F16 SFR2 area Not used 030016 00BF 16 010016 01FF16 05BF 16 Not used 3BFF 16 140016 800016 Not used ROM correction function Vector 1: address 030016 Vector 2: address 032016 032016 053F16 A00016 OSD ROM (10K bytes) M3727GM8- XXXSP/FP RAM (1024 bytes) M3727GM6- XXXSP/FP, M37272E8SP/FP RAM (1152 bytes) ■ M3727GM6/M8-XXXSP/FP, M37272E8SP/FP Note:Refer to Table 8.11.3 OSD RAM. M3727GM8- XXXSP/FP M37272E8SP/FP ROM (32K bytes) M3727GM6- XXXSP/FP ROM (24K bytes)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 13 of 127 REJ03B0132-0100Z Fig. 8.2.2 Memory Map of Special Function Register 1 (SFR1) (1) S F R A r e a a d d r e s s e s C t o D D 01 D1 16 D 21 D 31 D4 16 D5 16 D6 16 D 71 D8 16 D 91 DA 16 D B1 D C 1 DD 16 D E1 DF 16 C 01 C 11 C 21 C3 16 C 41 C5 16 C 61 C7 16 C 81 C 91 C B1 C C 1 C D 1 C E1 CF 16 CA 16 A d d r e s s Port P5 (P5) Caption data register 3 (CD3) Caption data register 4 (CD4) OSD c ontrol register (OC) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) R egister Port P0 (P0) Port P0 direction register (D0) Horizontal position register (HP) Block control register 1 (BC1) Block control register 2 (BC2) Vertical position register 1 (VP1) Vertical position register 2 (VP2) Window register 1 (WN1) Interrupt input polarity control register (R E) b7 b 0 Bit allocation St ate immediately after reset b 7b 0 OSD port control register (PF) Window register 2 (WN2) I/O polarity control register (PC) Raster color register (RC) : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t <State immediately after reset> “ 1 ” i m m e d i a t e l y a f t e r r e s e t : Fix this bit to “0” (do not write “1”) <Bit allocation> F u n c t i o n b i t N o f u n c t i o n b i t : Fix this bit to “1” (do not write “0”) N ame : 0016 0016 0016 ??000000 PF2PF3PF4PF5PF7 INT1INT2INT3 P 0P31 P30DP31DP30CT3SC P31C 0016 0016 0016 4016 OC4OC5 O C C 3O C 0 O C 1OC6 B C 0BC11BC12BC13B C C C 6BC17 B C 0BC21BC22BC23B C C C 6BC27 V P 0VP11VP12VP13V P P P 6VP17 V P 0VP21VP22VP23V P P P 6VP27 WN10WN11WN12WN13WN14WN15WN16WN17 WN20WN21WN22WN23WN24WN25WN26WN27 RC0RC1RC2RC7

00 RC3RC4

CDH20CDH21CDH22CDH23CDH24CDH25CDH26CDH27 HP 4HP 5 HP 2HP 3 HP 0HP1HP6 P C 4P C 5 PC 2P C 3 P C 0PC1P C 60 0016 0016 0016 0016 0016 0016 0 01

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 14 of 127 REJ03B0132-0100Z Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (2) F016 F 11 F 21 F 31 F 41 F 51 F 61 F 71 F816 F916 F A1 FB 16 F C 1 FD 16 F E1 F F1 E016 E 11 E 21 E 31 E416 E516 E616 E716 E 81 E 91 E B1 E C 1 ED 16 EE 16 EF 16 E A1 Address S e r i a l I / O r e g i s t e r ( S I O ) A - D c o n t r o l r e g i s t e r 1 ( A D 1 ) T i m e r 5 ( T 5 ) T i m e r 6 ( T 6 ) Timer 1 (T1) C a p t i o n d a t a r e g i s t e r 1 ( C D 1 ) Caption position register (CPS) D a t a s l i c e r t e s t r e g i s t e r 2 Clock run-in detect register (CRD) D a t a c l o c k p o s i t i o n r e g i s t e r ( D P S ) R e g i s t e r Data slicer control register 1 (DSC1) D a t a s l i c e r c o n t r o l r e g i s t e r 2 ( D S C 2 ) Timer 2 (T2) T i m e r 3 ( T 3 ) T i m e r 4 ( T 4 ) Timer mode register 1 (TM1) T i m e r m o d e r e g i s t e r 2 ( T M 2 ) I d a t a s h i f t r e g i s t e r S I2C c o n t r o l r e g i s t e r S D I2C c l o c k c o n t r o l r e g i s t e r S I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) Data slicer test register 1 Synchronous signal counter register (HC) A-D control register 2 (AD2) CPU mode register (CPUM) b 7b 0 Bit allocation S t a t e i m m e d i a t e l y a f t e r r e s e t b7 b 0 S F R A r e a a d d r e s s e s E t o F C a p t i o n d a t a r e g i s t e r 2 ( C D 2 ) S e r i a l I / O m o d e r e g i s t e r ( S M ) I s t a t u s r e g i s t e r S I2C a d d r e s s r e g i s t e r S D : “0” immediately after reset I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t <State immediately after reset> : “1” immediately after reset F i x t h i s b i t t o “ 0 ” d o n o t w r i t e <Bit allocation> Function bit : N o f u n c t i o n b i t F i x t h i s b i t t o “ 1 ” d o n o t w r i t e N a m e : TM20T M 2 1TM22TM23T M 2 4 TM10T M 1 1TM12TM13T M 1 4 CM2 TM1RTM2RTM3RTM4ROSDRVSCRI N R C K I N R DSRS1R T M 1 ET M 2 ETM3ET M 4 EOSDEVSCE IN1ED S ES EIN2E T M 2 5 0016 F F1 FF16 0716 0716 TM15T M 1 6TM17 T M 2 6T M 2 7 S A D 0S A D 1SAD2SAD3S A D 4S A D 5S A D 6R B W LRBA D A SALPINB BT R XM S T B C 0B C 1BC2E S OALS BSEL0BSEL1 CCR0CCR1C C R 2C C R 3C C R 4A C K 0 01 CK RIN2RIICRTM56R I N E CKEI I C ET M 5 6 ET M 5 6 C 00C M M M SM0SM1SM2SM3 A D C 1 0AD C 11AD C 12A D C 1 4 A D C 2 0A D C 2 1AD C 22A D C 2 5 SM5SM6 A D C 2 4A D C 23 10BIT SAD F A S T M O D E 0 01 F F DSC10DSC11DSC12 DSC20D S C 2 3D SC 24D S C 2 5 C R D 3CRD4C R D 5CRD6C R D 7 DPS3D P S 4D P S 5DPS6D P S 7 CPS0CPS3CPS4CPS5 CPS1 CPS2CPS6CPS7 HC0HC3HC4HC5 HC1 HC2 000? 0 1100 1 00 0000 0 01 C D H 1 0C D H 1 3C D H 1 4CDH15 CDH11 CDH12C D H 1 6C D H 1 7 CD L10CD L13CD L14CD L15 CDL11 CD L12CD L16CD L17 0016 D1D 2D3D 4D5D 7D 0 0000?00 0 00 0 01 0 0? ACK BIT 0 91 3C 16

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 15 of 127 REJ03B0132-0100Z Fig. 8.2.4 Memory Map of Special Function Register 2 (SFR2) 2 0 01 20116 20216 20316 2 0 41 2 0 51 2 0 61 2 0 71 2 0 81 2 0 91 2 0 B1 2 0 C 1 20D 16 20E16 20F16 2 0 A1 A d d r e s s P W M m o d e r e g i s t e r 2 ( P M 2 ) ROM correction address 1 (low-order) ROM correction enable register (RCR) PWM2 register (PWM2) P W M 4 r e g i s t e r ( P W M 4 ) P W M 5 r e g i s t e r ( P W M 5 ) Register P W M 0 r e g i s t e r ( P W M 0 ) PWM1 register (PWM1) P W M m o d e r e g i s t e r 1 ( P M 1 ) R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) b 7b 0 Bit allocation t a t e i m m e d i a t e l y a f t e r r e s e t b7 0 S F R A r e a a d d r e s s e s 016 t o F16) PWM3 register (PWM3) R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) ROM correction address 2 (low-order) 0 i m m e d i a t e l y a f t e r r e s e t : Indeterminate immediately after reset S t a t e i m m e d i a t e l y a f t e r r e s e t > 1 i m m e d i a t e l y a f t e r r e s e t : Fix this bit to 0 (do not write 1 ) < B i t a l l o c a t i o n > F u n c t i o n b i t : No function bit : Fix this bit to 1 (do not write 0 ) N a m e : 0016 0 01 PM13 ? ?? 0PM10 P M 2 5 M 2 4 M 2 3 M 2 0 0016 0016 0016 0016 0016 0016 RCR1 RCR0

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 16 of 127 REJ03B0132-0100Z Fig. 8.2.5 Internal State of Processor Status Register and Program Counter at Reset b 7 b0 b 7 b 0 R e g i s t e r Processor status register (PS) B i t a l l o c a t i o nS t a t e i m m e d i a t e l y a f t e r r e s e t Program counter (PCH ) Program counter (PCL) C o n t e n t s o f a d d r e s s F F F F1 C ontents of address FFFE16 : Fix to this bit to “0” (do not write to “1”) <Bit allocation> <S t a t e i m m e d i a t e l y a f t e r r e s e t> F u n c t i o n b i t : N o f u n c t i o n b i t : Fix to this bit to “1” (do not write to “0”) N a m e : “ 0 ” i m m e d i a t e l y a f t e r r e s e t : Indeterminate immediately after reset “ 1 ” i m m e d i a t e l y a f t e r r e s e t

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 17 of 127 REJ03B0132-0100Z Priority

8.3 INTERRUPTS

Interrupts can be caused by 17 different sources consisting of 4 ex- ternal, 11 internal, 1 software, and reset. Interrupts are vectored in- terrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, ① The contents of the program counter and processor status regis- ter are automatically stored into the stack. ➁ The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” ➂ The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are ac- cepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt control.

8.3.1 Interrupt Causes

(1) VSYNC , OSD interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. (2) INT1 to INT3 external interrupts The INT1 to INT3 interrupts are external interrupt inputs, the sys- tem detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The in- put active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00DC 16) : when this bit is “0,” a change from LOW to HIGH is detected; when it is “1,” a change from HIGH to LOW is detected. Note that both bits are cleared to “0” at reset. (3) Timers 1 to 4 interrupts An interrupt is generated by an overflow of timers 1 to 4. Vector Addresses FFFF 16, FFFE16 FFFD 16, FFFC16 FFFB 16, FFFA16 FFF9 16, FFF816 FFF7 16, FFF616 FFF5 16, FFF416 FFF3 16, FFF216 FFF1 16, FFF016 FFEF 16, FFEE16 FFED 16, FFEC16 FFEB 16, FFEA16 FFE9 16, FFE816 FFE7 16, FFE616 FFE5 16, FFE416 FFE3 16, FFE216 FFDF 16, FFDE16 Interrupt Source Reset OSD interrupt INT1 external interrupt Data slicer interrupt Serial I/O interrupt Timer 4 interrupt f(X IN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt INT3 external interrupt INT2 external interrupt Multi-master I 2C-BUS interface interrupt Timer 5 • 6 interrupt BRK instruction interrupt Remarks Non-maskable Active edge selectable Active edge selectable Active edge selectable Source switch by software (see note) Non-maskable Table 8.3.1 Interrupt Vector Addresses and Priority Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 18 of 127 REJ03B0132-0100Z (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe- riod. Set bit 0 of the PWM mode register 1 to “0.” (6) Data slicer interrupt An interrupt occurs when slicing data is completed. (7) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (8) Timer 5 • 6 interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (9) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction R e s e t I n t e r r u p t r e q u e s t

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 19 of 127 REJ03B0132-0100Z Fig. 8.3.2 Interrupt Request Register 1 Fig. 8.3.3 Interrupt Request Register 2 b 7b 6 b 5b4b 3 b 2b 1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 0 0 F C 1 BN a m e F u n c t i o n s After reset RW Interrupt Request Register 1 0 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d T i m e r 1 i n t e r r u p t r e q u e s t b i t T M R 1T i m e r 2 i n t e r r u p t r e q u e s t b i t T M R 2T i m e r 3 i n t e r r u p t r e q u e s t b i t T M R

3 T i m e r 4 i n t e r r u p t

r e q u e s t b i t T M R 4O SD interrupt request bit (OSDR) 5V SYNC interrupt request bit (VSCR)

6 I N T 3 e x t e r n a l i n t e r r u p t

r e q u e s t b i t V S C R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ ✽: “0” can be set by software, but “1” cannot be set. R R R R R R R RNothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” b 7b 6b 5b 4b 3 b 2b 1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 0 0 F D BN a m eF u n c t i o n s A f t e r r e s e t RW I n t e r r u p t R e q u e s t R e g i s t e r 2

0 I N T 1 e x t e r n a l i n t e r r u p t

r e q u e s t b i t I N I R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d

1 D a t a s l i c e r i n t e r r u p t

r e q u e s t b i t D S R

2 Serial I/O interrupt

request bit (S1R)

4 INT2 external interrupt

request bit (IN2R) 7F i x this bit to “0.” 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d R R R R ✽ R R ✽ R W f(XIN)/4096 interrupt request bit (CKR) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d Multi-master I2C-BUS interrupt request bit (IICR) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d

6 Timer 5 • 6 interrupt

request bit (TM56R) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 20 of 127 REJ03B0132-0100Z Fig. 8.3.4 Interrupt Control Register 1 b 7b 6 b 5b 4b 3 b 2b1b 0 I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 0 0 F E1 BN a m eF u n c t i o n s After reset RW I n t e r r u p t C o n t r o l R e g i s t e r 1

0 T i m e r 1 i n t e r r u p t

e n a b l e b i t T M E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d

1 T i m e r 2 i n t e r r u p t

e n a b l e b i t T M E

2 T i m e r 3 i n t e r r u p t

e n a b l e b i t T M E

4 O S D i n t e r r u p t e n a b l e b i t

O S D E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d RW RW RW RW RW 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” T i m e r 4 i n t e r r u p t e n a b l e b i t T M E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 5 VS Y N C i n t e r r u p t e n a b l e b i t V S C E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 0R W e n a b l e b i t I N E 0 : Interrupt disabled 1 : Interrupt enabled 0R W Fig. 8.3.5 Interrupt Control Register 2 b7b6 b5b4b3 b2b1b0 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 0 0 F F1 BN a m eF u n c t i o n s After reset RW I n t e r r u p t C o n t r o l R e g i s t e r 2 e n a b l e b i t I N E 0 : Interrupt disabled 1 : Interrupt enabled e n a b l e b i t D S E

2 S e r i a l I / O i n t e r r u p t

e n a b l e b i t S E

4 I N T 2 e x t e r n a l i n t e r r u p t

e n a b l e b i t I N E 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW RW RW f ( X I N ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t C K E 0 : Interrupt disabled 1 : Interrupt enabled 5 M u l t i m a s t e r I2C B U S i n t e r f a c e i n t e r r u p t e n a b l e b i t I I C E 0 : Interrupt disabled 1 : Interrupt enabled 0R W

6 T i m e r 5 • 6 i n t e r r u p t

e n a b l e b i t T M E 0 : Interrupt disabled 1 : Interrupt enabled 0R W

7 T i m e r 5 • 6 i n t e r r u p t

s w i t c h b i t T M C 0 : Timer 5 1 : Timer 6 0R W

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 21 of 127 REJ03B0132-0100Z Fig. 8.3.6 Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (RE) [Address 00DC16] B Name Functions After reset R W Interrupt Input Polarity Register INT1 polarity switch bit (INT1) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity to INT2 polarity switch bit (INT2) INT3 polarity switch bit (INT3) Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 RW RW RW 0 : Positive polarity 1 : Negative polarity

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 22 of 127 REJ03B0132-0100Z

8.4 TIMERS

This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the correspond- ing timer latch (addresses 00F0 16 to 00F316 : timers 1 to 4, addresses 00EE 16 and 00EF16 : timers 5 and 6), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse, after the count value reaches “00 16”.

8.4.1 Timer 1

Timer 1 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• f(XIN)/4096 or f(XCIN)/4096
• External clock from the TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow.

8.4.2 Timer 2

Timer 2 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F4 16). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.

8.4.3 Timer 3

Timer 3 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• f(XCIN)
• External clock from the TIM3 pin The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow.

8.4.4 Timer 4

Timer 4 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• f(XCIN) The count source of timer 3 is selected by setting bits 1 and 4 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.

8.4.5 Timer 5

Timer 5 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• Timer 2 overflow signal
• Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F4 16) and bit 7 of the timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either f(X IN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow.

8.4.6 Timer 6

Timer 6 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00F4 16). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for timer 6, the timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow. At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN) ✽ /16 is not selected as the timer 3 count source. So set both bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before the execution of the STP instruction (f(XIN) ✽ /16 is selected as timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. ✽: When bit 7 of the CPU mode register (CM 7) is “1,” f(XIN) becomes f(XCIN).

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 23 of 127 REJ03B0132-0100Z Fig. 8.4.2 Timer Mode Register 2 b7b6 b5b4b3 b2b1b0 Timer mode register 2 (TM2) [Address 00F516] B After resetRW Timer Mode Register 2 Name Functions Timer 3 count source selection bit (TM20) 0 RW 1, 4Timer 4 count source selection bits (TM21, TM24) 0R W2 Timer 3 count stop bit (TM22) 0: Count start 1: Count stop Timer 4 count stop bit (TM23) 0: Count start 1: Count stop

5 Timer 5 count stop bit

(TM25) 0: Count start 1: Count stop

6 Timer 6 count stop bit

(TM26) 0: Count start 1: Count stop RW RW RW RW RW7 Timer 5 count source selection bit 1 (TM27) 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Count source selected by bit 6 of TM1 00 : f(XIN)/16 or f(XCIN)/16 (See note) 01 : f(XCIN) 10 : 11 : (b6 at address 00C716) External clock from TIM3 pin b4 b1 00 : Timer 3 overflow signal 01 : f(XIN)/16 or f(XCIN)/16 (See note) 10 : f(XIN)/2 or f(XCIN)/2 (See note) 11 : f(XCIN) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Fig. 8.4.1 Timer Mode Register 1 b7b6 b5b4b3 b2b1b0 Timer mode register 1 (TM1) [Address 00F416] B After reset W Timer Mode Register 1 Name Functions Timer 1 count source selection bit 1 (TM10) 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Count source selected by bit 5 of TM1 Timer 2 count source selection bit 1 (TM11) 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin Timer 1 count stop bit (TM12) 0: Count start 1: Count stop Timer 2 count stop bit (TM13) 0: Count start 1: Count stop Timer 2 count source selection bit 2 (TM14) R WR WR WR WR WR0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 1 overflow

5 Timer 1 count source

selection bit 2 (TM15) 0: f(XIN)/4096 or f(XCIN)/4096 (See note) 1: External clock from TIM2 pin 0W R

6 Timer 5 count source

selection bit 2 (TM16) 0: Timer 2 overflow 1: Timer 4 overflow 0W R 7T imer 6 internal count source selection bit (TM17) 0W R0: f(X IN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 24 of 127 REJ03B0132-0100Z Fig. 8.4.3 Timer Block Diagram Timer 1 (8) CM7 TM15 Timer 1 latch (8) TM10 TM12 TM14 TM11 TM13 Timer 2 (8) Timer 2 latch (8) Timer 3 (8) Timer 3 latch (8) Timer 4 (8) Timer 4 latch (8) Timer 5 (8) Timer 5 latch (8) Timer 6 (8) Timer 6 latch (8) Data bus Timer 1 interrupt request Timer 2 interrupt request Timer 3 interrupt request Reset STP instruction TM20 TM22 T3SC Timer 4 interrupt requestTM24 TM23 TM21 TM16 Timer 5 interrupt requestTM27 TM25 Timer 6 interrupt requestTM17 TM26 TM21 X CIN X IN TIM2 TIM3 Selection gate: Connected to black side at reset TM1 : Timer mode register 1 TM2 : Timer mode register 2 T3SC : Timer 3 count source switch bit (address 00C7 16) CM : CPU mode register Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. FF16 0716 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 25 of 127 REJ03B0132-0100Z Serial I/O shift register (8) Data bus Serial I/O interrupt request Selection gate: Connect to black side at reset.Synchronous circuit Frequency divider 1/81/4 1/16 SM1 SM0 Serial I/O counter (8) SM5 : LSB MSB S SM2 1/2XIN SIN S OUT S CLK XCIN CM7 1/2 Note : When the data is set in the serial I/O register (address 00EA (See note) CM : CPU mode register SM : Serial I/O mode register 16), the register functions as the serial I/O shift register. P20 Latch SM3 P21 Latch SM3 SM6

8.5 SERIAL I/O

This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchro- nous clock I/O pin (S CLK ), and data output pin (SOUT ) also function as port P4, data input pin (SIN) also functions as port P20–P22. Bit 3 of the serial I/O mode register (address 00EB16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN pin for serial I/O, set the corresponding bit of the port P2 direction register (address 00C5 16) to “0.” Fig. 8.5.1 Serial I/O Block Diagram The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 26 of 127 REJ03B0132-0100Z Internal clock : The serial I/O counter is set to “7” during the write cycle into the serial I/O register (address 00EA16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the S IN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.” Fig. 8.5.2 Serial I/O Timing (for LSB first) Synchronous clock Transfer clock Serial I/O register write signal S e r i a l I / O o u t p u t SO U T D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (Note) S e r i a l I / O i n p u t SI N N o t e : W h e n a n i n t e r n a l c l o c k i s s e l e c t e d , t h e SO U T p i n i s a t h i g h - i m p e d a n c e a f t e r t r a n s f e r i s c o m p l e t e d . Interrupt request bit is set to “1” External clock : The an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an exter- nal clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an inter- nal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2:When an external clock is used as the synchronous clock, write trans- mit data to the serial I/O register when the transfer clock input level is HIGH.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 27 of 127 REJ03B0132-0100Z Fig. 8.5.3 Serial I/O Mode Register b 7b6 b 5b 4b 3 b 2b 1b 0 Serial I/O mode register (SM) [Address 00EB16] BN a m eF u n c t i o n s After reset RW S e r i a l I O M o d e R e g i s t e r 0 , 1 Internal synchronous clock selection bits (SM0, SM1) b 1 b 0 f X I N ) o r f XC I N ) f XI N ) o r f XC I N ) f XI N ) o r f XC I N ) f XI N ) o r f XC I N )

2 Synchronous clock

selection bit (SM2)

3 Port function

selection bit (SM3)

5 Transfer direction

selection bit (SM5) 0 : P 20, P 21 SC L SO U T 0 : E x t e r n a l c l o c k I n t e r n a l c l o c k 0: LSB first 1: MSB first Fix this bit to “0.” Transfer clock input pin selection bit (SM6) 0 : I n p u t s i g n a l f r o m SI N p i n I n p u t s i g n a l f r o m SO U T p i n RW RW RW R W RW RW 7 Fix this bit to “0.” 0R W

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 28 of 127 REJ03B0132-0100Z Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I 2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Format Communication mode SCL clock frequency φ : System clock = f(XIN)/2 Note :We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).

8.6 MULTI-MASTER I2C-BUS INTERFACE

The multi-master I2C-BUS interface is a serial communications cir- cuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS in- terface and Table 8.6.1 shows multi-master I2C-BUS interface func- tions. This multi-master I 2C-BUS interface consists of the I2C address reg- ister, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface I2C address register (S0D)b7 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Noise elimination circuit Serial data (SDA) Address comparator I C data shift register Data control circuit I2C clock control register (S2) System clock(φ) Interrupt generating circuit Interrupt request signal (IICIRQ) MST TRX BB PIN AL AAS AD0 LRB I C status register (S1) b7 b0 BSEL1 BSEL0 10BIT SAD ALS BC2 BC1 BC0 I2C control register (S1D) Bit counter BB circuit Clock control circuit Noise elimination circuit Serial clock (SCL) b7 b0 ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 Internal data bus Clock division AL circuit ESO

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8.6.1 I2C Data Shift Register

The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I 2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00F916) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift regis- ter is always enabled regardless of the ESO bit value. Note:To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Fig. 8.6.2 Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00F616] B Functions After reset R W I C D a t a S h i f t R e g i s t e r t o T h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a I n d e t e r m i n a t e N ote: 2T o w r i t e d a t a i n t o t h e I C d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e M S T b i t t o s l a v e m o d e k e e p a n i n t e r v a l o f m a c h i n e c y c l e s o r m o r e N am e D 0 t o D 7 R W

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8.6.2 I2C Address Register

The I2C address register (address 00F716) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the START condition are detected. (1) Bit 0: read/write bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. (2) Bits 1 to 7: slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. Fig. 8.6.3 I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0

0 R ead/write bit

(RBW) t o S l a v e a d d r e s s S A D t o S A D <O nly in 10-bit addressing (in slave) mo de> The last significant bit of address data is comp ared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after R ESTART condition (write state) <In both mo des> The address data is compared. I2C A d d r e s s R e g i s t e r I2C a d d r e s s r e g i s t e r S D A d d r e s s F B Nam e Functions After resetR W R W

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8.6.3 I2C Clock Control Register

The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. (1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. (2) Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan- dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. (3) Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). ✽ACK clock: Clock for acknowledgement Fig. 8.6.4 I2C Address Register (4) Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note:Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2 : address 00FA16) I2C Clock Control Register to SCL frequency control bits (CCR0 to CCR4) SCL mode specification bit (FAST MODE) 0: Standard clock mode 1: High-speed clock mode 0Standard clock mode B Name Functions After resetRW ACK bit (ACK BIT) ACK clock bit (ACK) 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock High speed clock mode Setup disabled Setup disabled00 to 02 Setup disabled 33303 Setup disabled 25004 100 400 (See note)05 83.3 16606 500/CCR value 1000/CCR value ... 17.2 34.51D 16.6 33.31E 16.1 32.31F (at φ = 4 MHz, unit : kHz) Note: At 4000kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Setup value of CCR4– CCR0 RW RW RW RW

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8.6.4 I2C Control Register

The I2C control register (address 00F916) controls the data commu- nication format. (1) Bits 0 to 2: bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “000 2” and the address data is always transmitted and received in 8 bits. (2) Bit 3: I2C interface use enable bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ESO = “0,” the following is performed.

• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I status register at address 00F816 ).
• W riting data to the I2C data shift register (address 00F616) is dis- abled. (3) Bit 4: data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that ad- dress data is recognized. When a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to “8.6.5 I 2C Status Register,” bit 1) is received, trans- mission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recog- nized. (4) Bit 5: addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address register (ad- dress 00F716) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. (5) Bits 6 and 7: connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5). Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1 Note: Set the corresponding direction register to “1” to use the port as multi-master I2C-BUS interface. “ 0 ” B S E L SCL/P11 SCL2/P12 “0” “1” BSEL1 “ 0 ” B S E L SDA1/P1 3 SDA2/P1 4 “ 0 ” B S E L M u l t i - m a s t e r I2C B U S i n t e r f a c e S C L SDA

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 33 of 127 REJ03B0132-0100Z Fig. 8.6.6 I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 t o B i t c o u n t e r N u m b e r o f t r a n s m i t r e c i e v e b i t s B C t o B C b 2 b 1 b 0

3 I2C-BU S interface use

enable bit (ESO) 0 : Disabled 1 : Enabled

4 D ata format selection

bit(ALS) 0 : Addressing mode 1 : Free data format

5 A d d r e s s i n g f o r m a t s e l e c t i o n

b i t B I T S A D 0 : 7 - b i t a d d r e s s i n g f o r m a t b i t a d d r e s s i n g f o r m a t 6, 7 C onnection control bits between I C-BUS interface and ports b 7 b 6 C o n n e c t i o n p o r t ( S e e n o t e ) N o n e S C L S D A S C L S D A S C L S D A S C L S D A I2C c o n t r o l r e g i s t e r S D a d d r e s s F I2C C o n t r o l R e g i s t e r B N a m e F u n c t i o n s After reset R W N o t e : W h e n u s i n g p o r t s P 11- P 14 a s I C - B U S i n t e r f a c e , t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m C M O S o u t p u t t o N c h a n n e l o p e n d r a i n o u t p u t R W R W R W R W R W

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8.6.5 I2C Status Register

The I2C status register (address 00F816) controls the I2C-BUS inter- face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) Bit 0: last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00F616). (2) Bit 1: general call detecting flag (AD0) This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. ✽General call: The master transmits the general call address “00 16” to all slaves. (3) Bit 2: slave address comparison flag (AAS) This flag indicates a comparison result of address data. ■ In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions.

• The address data immediately after occurrence of a START con- dition matches the slave address stored in the high-order 7 bits of the I 2C address register (address 00F716).
• A general call is received. ■ In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition.
• When the address data is compared with the I2C address regis- ter (8 bits consists of slave address and RBW), the first bytes match. ■ The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616). (4) Bit 3: arbitration lost✽ detecting flag (AL) n the master transmission mode, when a device other than the mi- crocomputer sets the SDA to “L,”, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ✽Arbitration lost: The status in which communication as a master is disabled. (5) Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the PIN bit. When detecting the STOP condition in slave, the multi-master I 2C-BUS interface interrupt request bit (IR) is set “0” to “1” (interrupt request) regardless of falling of PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in any one of the following conditions.
• W riting “1” to the PIN bit
• Executing a write instruction to the I 2C data shift register (address 00F616). (See note)
• When the ESO bit is “0”
• At reset Note: It takes 8 BCLK cycles or more until PIN bit become “1” after write in- structions are executed to these registers. The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception (6) Bit 5: bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I 2C control register (address 00F916) is “0” and at reset, the BB flag is kept in the “0” state. (7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I 2C control register (address 00F916) is “0” in the slave reception mode is selected, the TRX bit is set to “1” (trans- ___ mit) if the least significant bit (R/W bit) of the address data transmit- ___ ted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention function (Note).
• W ith MST = “0” and when a START condition is detected.
• W ith MST = “0” and when ACK non-return is detected.
• At reset

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 35 of 127 REJ03B0132-0100Z (8) Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are gener- ated, and also the clocks required for data communication are gen- erated on the SCL. The MST bit is cleared to “0” in one of the following conditions.

• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing function (Note).
• At resetFig. 8.6.7 I2C Status Register b 7 b 6 b 5 b 4 b3 b 2 b1 b 0 I2C s t a t u s r e g i s t e r S A d d r e s s F I2C S t a t u s R e g i s t e r 6 , 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode B N a m e F u n c t i o n s After resetR W C o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s T R X M S T 0 : Bus free 1 : Bus busy B u s b u s y f l a g ( B B ) 0 : Interrupt request issued 1 : No interrupt request issued I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t P I N 0 : N ot detected 1 : Detected A r b i t r a t i o n l o s t d e t e c t i n g f l a g A L S e e n o t e 0 : Address mismatch 1 : Address match S l a v e a d d r e s s c o m p a r i s o n f l a g A A S S e e n o t e 0 : N o general call detected 1 : General call detected G e n e r a l c a l l d e t e c t i n g f l a g A D S e e n o t e 0 : Last bit = “0 ” 1 : Last bit = “1 ” L a s t r e c e i v e b i t ( L R B ) S e e n o t e N o t e : T h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . Indeterm inate R— RW R W

0 R W

( S e e n o t e ) ( S e e n o t e ) (See note) (See note) Fig. 8.6.8 Interrupt Request Signal Generation Timing SC L PIN I I C I R Q Note:The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device.

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8.6.6 START Condition Generation Method

When the ESO bit of the I2C control register (address 00F916) is “1,” execute a write instruction to the I2C status register (address 00F816) to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the high- speed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table. Fig. 8.6.9 START Condition Generation Timing Diagram I2C status register write signal Hold timeSetup time S C L S D A B B f l a g Set tim e for BB flag

8.6.7 STOP Condition Generation Method

When the ESO bit of the I2C control register (address 00F916) is “1,” execute a write instruction to the I2C status register (address 00F816) for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP condition genera- tion timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table. Fig. 8.6.10 STOP Condition Generation Timing Diagram Table 8.6.2 START Condition/STOP Condition Generation Tim- ing Table Item Setup time (START condition) Setup time (STOP condition) Hold time Set/reset time for BB flag Standard Clock Mode 5.0 µs (20 cycles) 4.25 µs (17 cycles) 5.0 µs (20 cycles) 3.0 µs (12 cycles) High-speed Clock Mode 2.5 µs (10 cycles) 1.75 µs (7 cycles) 2.5 µs (10 cycles) 1.5 µs (6 cycles) Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. I2C status register write signal H o l d t i m eS e t u p t i m e SCL SDA BB flag R eset tim e for BB flag

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 37 of 127 REJ03B0132-0100Z

8.6.8 START/STOP Condition Detect Conditions

The START/STOP condition detect conditions are shown in 8.6.3 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. Fig. 8.6.11 START Condition/STOP Condition Detect Timing Dia- gram Standard Clock Mode 6.5 µs (26 cycles) < SCL release time 3.25 µs (13 cycles) < Setup time 3.25 µs (13 cycles) < Hold time High-speed Clock Mode 1.0 µs (4 cycles) < SCL release time 0.5 µs (2 cycles) < Setup time 0.5 µs (2 cycles) < Hold time Table 8.6.3 START Condition/STOP Condition Detect Conditions Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the num- ber of φ cycles. H o l d t i m eS e t u p t i m e S C L S D A S T A R T c o n d i t i o n SDA (STOP condition) S C L r e l e a s e t i m e Hold timeS e t u p t i m e

8.6.9 Address Data Communication

There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective ad- dress communication formats is described below. (1) 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I 2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I 2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2). (2) 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I 2C address register (address 00F716). At the time of this comparison, an address com- parison between the RBW bit of the I2C address register (address 00F716) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the sec- ond-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I 2C address register (address 00F716) to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmis- sion format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4).

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 38 of 127 REJ03B0132-0100Z

8.6.10 Example of Master Transmission

An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and “0” in the RBW bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00FA16). ➂ Set “1016” in the I2C status register (address 00F816) and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00F916). ➄ Set the address data of the destination of transmission in the high- order 7 bits of the I 2C data shift register (address 00F616) and set “0” in the least significant bit. ➅ Set “F016” in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ➆ Set transmit data in the I 2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. ➇ When transmitting control data of more than 1 byte, repeat step ➆ . ➈ Set “D016” in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition will be generated.

8.6.11 Example of Slave Reception

An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. ➀ Set a slave address in the high-order 7 bits of the I 2C address register (address 00F716) and “0” in the RBW bit. ➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00FA16). ➂ Set “1016” in the I2C status register (address 00F816) and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00F916). ➄ When a START condition is received, an address comparison is made. ➅ •When all transmitted address are“0” (general call): AD0 of the I 2C status register (address 00F816) is set to “1”and an interrupt request signal occurs.

• When the transmitted addresses match the address set in ➀ : ASS of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs.
• In the cases other than the above: AD0 and AAS of the I2C status register (address 00F816) are set to “0” and no interrupt request signal occurs. ➆ Set dummy data in the I2C data shift register (address 00F616). ➇ When receiving control data of more than 1 byte, repeat step ➆ . ➈ When a STOP condition is detected, the communication ends.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 39 of 127 REJ03B0132-0100Z Fig. 8.6.12 Address Data Communication Format SS l a v e a d d r e s s A D a t aA D a t aA / A PR / W 7 b i t s“ 0 ”1 t o 8 b i t s1 t o 8 bits SS l a v e a d d r e s s A D a t a AD a t a AP 7 b i t s“ 1 ”1 t o 8 b i t s1 t o 8 bits 1 ) A m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r S S l a v e a d d r e s s s t b i t s A A D a t a 7 b i t s“ 0 ”8 b i t s1 t o 8 bits (2) A master-receiver receives data from a slave-transmitter S l a v e a d d r e s s n d b y t e A D a t aA / A P 1 t o 8 b i t s S S l a v e a d d r e s s s t b i t s A A 7 b i t s“ 0 ”8 b i t s7 b i t s (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S l a v e a d d r e s s n d b y t e Data 1 to 8 bits Sr Slave address 1st 7 bits A Data A P 1 t o 8 b i t s“1” (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S: S TART conditionP : STOP condition A: A C K b i t R / W : Read/Write bit Sr : Restart condition From master to slave From slave to master R / W R / W R/W R/W

8.6.12 Precautions when using multi-master

(1) Read-modify-write instruction The precautions when the raead-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. 2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended.

• I2C address register (S0D) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because hardware changes the read/write bit (RBW) at the above timing.
• I2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. 2C control register (S1D) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because hardware changes the bit counter (BC0–BC2) at the above timing. 2C clock control register (S2) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure us- ing multi-master ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➄ ). LDA — (Taking out of slave address value) SEI (Interrupt disabled) BBS 5,S1,BUSBUSY (BB flag confirming and branch process) BUSFREE: STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of START condition generating) CLI (Interrupt enabled) BUSBUSY: CLI (Interrupt enabled) ➁ Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing the slave address value to the I 2C data shift register. ➂ Use “LDM” instruction for setting trigger of START condition gener- ating. ➃ W rite the slave address value of above ➁ and set trigger of START condition generating of above ➂ continuously shown the above procedure example. ➄ Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 40 of 127 REJ03B0132-0100Z (3) RESTART condition generating procedure ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➅ .) Execute the following procedure when the PIN bit is “0.” LDM #$00, S1 (Select slave receive mode) LDA —( Taking out of slave address value) SEI (Interrupt disabled) STAS 0( W riting of slave address value) LDM #$F0, S1 (Trigger of RESTART condition generating) CLI (Interrupt enabled) ➁ Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. ➂ The SCL pin is released by writing the slave address value to the I 2C data shift register. Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing. ➃ Use “LDM” instruction for setting trigger of RESTART condition gen- erating. ➄ W rite the slave address value of above ➂ and set trigger of RE- START condition generating of above ➃ continuously shown the above procedure example. ➅ Disable interrupts during the following two process steps:

• Writing of slave address value
• Trigger of RESTART condition generating (4) STOP condition generating procedure ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➃ .) SEI (Interrupt disabled) LDM #$C0, S1 (Select master transmit mode) NOP (Set NOP) LDM #$D0, S1 (Trigger of STOP condition generating) CLI (Interrupt enabled) ➁ W rite “0” to the PIN bit when master transmit mode is select. ➂ Execute “NOP” instruction after setting of master transmit mode. Also, set trigger of STOP condition generating within 10 cycles af- ter selecting of master trasmit mode. ➃ Disable interrupts during the following two process steps:
• Select of master transmit mode
• Trigger of STOP condition generating (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not ex- ecute an instruction to set the MST and TRX bits to “0” from “1” si- multaneously when the PIN bit is “1.” It is because it may become the same as above. (6) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 41 of 127 REJ03B0132-0100Z

8.7 PWM OUTPUT FUNCTION

This microcomputer is equipped with six 8-bit PWMs (PWM0– PWM5). PWM0–PWM5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs (for f(XIN) = 8 MHz) and repeat period of 1024 µs (for f(XIN) = 8 MHz). Figure 8.7.1 shows the PWM block diagram. The PWM timing gen- erating circuit applies individual control signals to PWM0–PWM5 us- ing f(X IN) divided by 2 as a reference signal.

8.7.1 Data Setting

When outputting PWM0–PWM5, set 8-bit output data to the PWMi register (i means 0 to 5; addresses 020016 to 020516).

8.7.2 Transmitting Data from Register to PWM

Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register.

8.7.3 Operating of 8-bit PWM

The following explains PWM operation. First, set the bit 0 of PWM mode register 1 (address 020816) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM5 are also used as pins P00–P05. Set the correspond- ing bits of the port P0 direction register to “1” (output mode). And select each output polarity by bit 3 of PWM mode register 1 (address 0208 16). Then, set bits 5 to 0 of PWM mode register 2 (address 020916) to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 17 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (2 8) segments. The 8 kinds of pulses relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 17 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 17 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH cannot be output, i.e. 256/256.

8.7.4 Output after Reset

At reset, the output of ports P00–P05 is in the high-impedance state, and the contents of the PWM register and the PWM circuit are unde- fined. Note that after reset, the PWM output is undefined until setting the PWM register.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 42 of 127 REJ03B0132-0100Z Fig. 8.7.1 PWM Block Diagram PM10 XIN b7 b0 PM13 P00 PM20 D0 0 PWM0 P01 PM21 D0 1 PWM1 P02 PM22 D0 2 PWM2 P03 PM23 D0 3 PWM3 P04 PM24 D0 4 PWM4 P05 PM25 D0 5 PWM5 PM1 PM2 : PWM mode register 1 (address 020816) : PWM mode register 2 (address 020916) : Port P0 register (address 00C016) : Port P0 direction register (address 00C116) Selection gate: Connected to black side at reset. is as same contents with the others. PWM1 register (Address 020116) PWM2 register (Address 020216) PWM3 register (Address 020316) PWM4 register (Address 020416) PWM5 register (Address 020516) PWM timing generating circuit Data bus PWM0 register (Address 020016) 8-bit PWM circuit Inside of

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 43 of 127 REJ03B0132-0100Z Fig. 8.7.2 PWM Timing (a) Pulses showing the weight of each bit 13579 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 5 5 41 22 02 8 3 64 45 2 6 06 87 68 49 21 0 0 1 0 8 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 16 48 80 112 144 176 208 240 104 120 136 152 168 184 200 216 232 248 160 224 192 Bit 7 26 1 0 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 2 06 210 214 218 222 226 230 234 238 242 246 250 254 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 128 Bit 0 PWM output t = 4 µs T = 1024 µs f(X IN ) = 8 MHz (b) Example of 8-bit PWM t (0) (1) (24) FF (255) T = 256 t

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 44 of 127 REJ03B0132-0100Z b7b6 b5b4b3 b2b1b0 PWM mode register 2 (PM2) [Address 020916] B After resetRW PWM Mode Register 2 Name Functions P00/PWM0 output selection bit (PM20) 0 : P00 output 1 : PWM0 output P02/PWM2 output selection bit (PM22) 0 : P02 output 1 : PWM2 output P03/PWM3 output selection bit (PM23) 0 : P03 output 1 : PWM3 output P04/PWM4 output selection bit (PM24) 0 : P04 output 1 : PWM4 output

5 P05/PWM5 output

selection bit (PW25) 0: P05 output 1: PWM5 output 6, 7Fix these bits to “0.” P01/PWM1 output selection bit (PM21) 0 : P01 output 1 : PWM1 output RW RW RW RW RW RW RW Fig. 8.7.3 PWM Mode Register 1 Fig. 8.7.4 PWM Mode Register 2 b7b6 b5b4b3 b2b1b0 PWM mode register 1 (PM1) [Address 020816] B After resetR W PWM Mode Register 1 1, 2 Name Functions PWM output polarity selection bit (PM13) Indeterminate Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 : Positive polarity 1 : Negative polarity R W R — RW PWM counts source selection bit (PM10) 0 : Count source supply 1 : Count source stop to IndeterminateNothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R —

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 45 of 127 REJ03B0132-0100Z

8.8 A-D COMPARATOR

A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 8.8.1. The reference voltage “V ref” for D-A conversion is set by bits 0 to 5 of A-D control register 2 (address 00ED16). The comparison result of the analog input voltage and the reference voltage “V ref” is stored in bit 4 of A-D control register 1 (address 00EC 16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of A-D control register 1 and write the digital value corresponding to V ref to be compared to the bits 0 to 5 of A-D control register 2. The voltage comparison starts by writ- ing to A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ✕ 8). Fig. 8.8.1 A-D Comparator Block Diagram A-D control register 1 Bits 0 to 2 Comparator control Data bus Bit 4 Switch tree A-D control register 2 Resistor ladder Compa- rator Analog signal switch Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A-D control register 1 AD1 AD2 AD3 AD4 AD5 AD6

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 46 of 127 REJ03B0132-0100Z Fig. 8.8.2 A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EC16] B After resetRW A-D Control Register 1 to Analog input pin selection bits (ADC10 to ADC12) Name Functions b2 b1 b0 0 0 0 : AD1 0 0 1 : AD2 0 1 0 : AD3 0 1 1 : AD4 1 0 0 : AD5 1 0 1 : AD6 1 1 0 : 1 1 1 :

4 Storage bit of comparison

result (ADC14) 0: Input voltage < reference voltage 1: Input voltage > reference voltage Indeterminate Do not set. 3 This bit is a write disable bit. When this bit is read out, the value is “0.” RW RW R — to Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are “0.” R — Fig. 8.8.3 A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00ED16] B After reset RW A-D Control Register 2 to 6, 7 Name Functions D-A converter set bits (ADC20 to ADC25) b0b1b2 b3 b4 b5 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” 000000 00000 0000 111 11111 111111 : 3/128Vcc : 5/128Vcc : 123/128Vcc : 125/128Vcc : 127/128Vcc : 1/128Vcc RW

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 47 of 127 REJ03B0132-0100Z Fig. 8.9.2 ROM Correction Enable Register Fig. 8.9.1 ROM Correction Address Registers

8.9 ROM CORRECTION FUNCTION

This can correct program data in ROM. Up to 2 addresses can be corrected, a program for correction is stored in the ROM correction vector in RAM as the top address. The ROM correction vectors are 2 vectors. Vector 1 : address 0300 Vector 2 : address 032016 Set the address of the ROM data to be corrected into the ROM cor- rection address register. When the value of the counter matches the ROM data address in the ROM correction vector as the top address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register. Notes 1:Specify the first address (op code address) of each instruction as the ROM correction address. 2:Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3:Do not set the same ROM correction address to vectors 1 and 2. 020A 16ROM correction address 1 (high-order) 020B 16ROM correction address 1 (low-order) 020C 16ROM correction address 2 (high-order) 020D 16ROM correction address 2 (low-order) b7 b6 b5 b4 b3 b2 b1 b0 ROM correction enable register (RCR) [Address 020E16] B After resetRW ROM Correction Enable Register

0 Vector 1 enable bit (RC0)

0: Disabled 1: Enabled

1 Vector 2 enable bit (RC1) 0: Disabled

1: Enabled to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” RW RW

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 48 of 127 REJ03B0132-0100Z

8.10 DATA SLICER

This microcomputer includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a com- posite video signal. A composite video signal which makes the sync chip’s polarity negative is input to the CV IN pin. When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00E016) to “0.” These set- tings can realize the low-power dissipation. Fig. 8.10.1 Data Slicer Block Diagram Composite video signal 1 MΩ Sync pulse counter register (address 00E916) Data slicer control register 2 (address 00E116) Data slicer control register 1 (address 00E016) Clock run-in defect register (address 00E4 16) Caption position register (address 00E616) Data clock position register (address 00E516) Interrupt request generating circuit Data slicer interrupt request Synchronizing signal counter Synchronizing separation circuit Sync slice circuit Clamping circuit Low-pass filter Timing signal generating circuit Clock run-in determination circuit Data slice line specification circuit Start bit detecting circuit Data clock generating circuit 16-bit shift register Caption data register 1 (address 00E216) Caption data register 2 (address 00E316) Data bus Comparator 0.1 µF 470 Ω 560 pF CV IN 1 µF 1 kΩ 200 pF H SYNC HLF Reference voltage generating circuit VHOLD 1000 pF high-order low-order Data slicer ON/OFF Caption data register 4 (address 00CF16) Caption data register 3 (address 00CE 16) External circuit Note :Make the length of wiring which is connected to V HOLD , HLF, and CVIN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 49 of 127 REJ03B0132-0100Z

8.10.1 Notes When not Using Data Slicer

When bit 0 of data slicer control register 1 (address 00E016) is “0,” terminate the pins as shown in Figure 8.10.2. Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State When both bits 0 and 2 of data slicer control register 1 (address 00E016) are “1,” terminate the pins as shown in Figure 8.10.3. Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State <When data slicer circuit and timing signal generating circuit is in OFF state> <When using a reference clock generated in timing signal generating circuit as OSD clock> Connect the same external circuit as when using data slicer to HLF pin. Leave VHOLD pin open. Pull-up CVIN to VCC through a resistor of 5 kΩ or more. VHOLD CV IN Open 5 kΩ or more HLF 1 kΩ 200pF1 µF 17✽( ) ... M37272E8SP/FP ✽(Apply the same voltage as VCC to AVCC pin.) ✽(AV CC ) ✽(AV CC ) HLF VHOLD CV IN Open Open Leave HLF pin open. Leave V HOLD pin open. Pull-down CVIN pin to VSS through a resistor of 5 kΩ or more. 5 kΩ or more ✽(Apply the same voltage as VCC to AVCC pin.) ✽( ) ... M37272E8SP/FP

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 50 of 127 REJ03B0132-0100Z Fig. 8.10.4 Data Slicer Control Register 1 Fig. 8.10.5 Data Slicer Control Register 2 b 7b 6b 5b 4b 3b 2b1b 0 D a t a s l i c e r c o n t r o l r e g i s t e r 1 ( D S C 1 ) [ A d d r e s s 0 0 E 01 D a t a S l i c e r C o n t r o l R e g i s t e r 1 00 RW 0R W 2R e f e r e n c e c l o c k s o u r c e s e l e c t i o n b i t D S C 0: Video signal 1: HSYNC signal 0R W 0R W 0 RW 0: Stopped 1: Operating D a t a s l i c e r a n d t i m i n g s i g n a l g e n e r a t i n g c i r c u i t c o n t r o l b i t D S C F i x t h e s e b i t s t o “ 0 . ”3 , 4 00 0 10 : F 2 1: F1 S e l e c t i o n b i t o f d a t a s l i c e r e f e r e n c e v o l t a g e g e n e r a t i n g f i e l d D S C F i x t h e s e b i t s t o “ 1 . ”5 , 6 D e f i n i t i o n o f f i e l d s 1 ( F 1 ) a n d 2 ( F 2 ) H sep Vsep F1: H s e p Vs e p F B After reset R WName Functions 0R WF i x t h i s b i t t o “ 0 . ”7 b7 b6 b5 b4 b3 b2 b1 b0 D a t a s l i c e r c o n t r o l r e g i s t e r 2 ( D S C 2 ) [ A d d r e s s 0 0 E 11 R W D a t a S l i c e r C o n t r o l R e g i s t e r 2

0 I n d e t e r m i n a t e R —

I n d e t e r m i n a t e R — I n d e t e r m i n a t e R — 0 : D a t a i s n o t l a t c h e d y e t a n d a c l o c k r u n i n i s n o t d e t e r m i n e d D a t a i s l a t c h e d a n d a c l o c k r u n i n i s d e t e r m i n e d C a p t i o n d a t a l a t c h c o m p l e t i o n f l a g D S C F i x t h i s b i t t o “ 1 . ”

2 R e a d - o n l yT e s t b i t

30 : F 2 F F i e l d d e t e r m i n a t i o n f l a g D S C 40 : M e t h o d ( 1 ) M e t h o d V e r t i c a l s y n c h r o n o u s s i g n a l V s e g e n e r a t i n g m e t h o d s e l e c t i o n b i t D S C 50 : M atch 1: Mismatch V - p u l s e s h a p e d e t e r m i n a t i o n f l a g D S C Indeterminate R — 6 0 R WFix this bit to “o.” B A f t e r r e s e tF u n c t i o n sN am e D e f i n i t i o n o f f i e l d s 1 ( F 1 ) a n d 2 ( F 2 ) H s e p Vs e p F H s e p Vs e p F R —7 R ead-onlyT e s t b i t I n d e t e r m i n a t e

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 51 of 127 REJ03B0132-0100Z

8.10.2 Clamping Circuit and Low-pass Filter

The clamp circuit clamps the sync chip part of the composite video signal input from the CVIN pin. The low-pass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video signal is input requires a capacitor (0.1 µF) coupling outside. Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1 M Ω. In addition, we recommend to install externally a simple low- pass filter using a resistor and a capacitor at the CVIN pin (refer to Figure 8.10.1).

8.10.3 Sync Slice Circuit

This circuit takes out a composite sync signal from the output signal of the low-pass filter.

8.10.4 Synchronous Signal Separation Circuit

This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. (1)Horizontal Synchronous Signal (H sep) A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync signal. (2)Vertical Synchronous Signal (V sep) As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of the data slicer control register 2 (address 00E1 16).

• Method 1 The LOW level width of the composite sync signal is measured. If this width exceeds a certain time, a Vsep signal is generated in synchronization with the rising of the timing signal immediately after this LOW level.
• Method 2 The LOW level width of the composite sync signal is measured. If this width exceeds a certain time, it is detected whether a falling of the composite sync sig- nal exits or not in the LOW level period of the timing signal immediately after this LOW level. If a falling exists, a V sep signal is generated in synchronization with the rising of the timing signal (refer to Figure 8.10.6). Figure 8.10.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the composite sync signal. As shown in Figure 8.10.7, when the A level matches the B level, this bit is “0.” In the case of a mismatch, the bit is “1.” Fig. 8.10.6 Vsep Generating Timing (method 2) C o m p o s i t e s T i m i n g s i g n a l V sep signal M e a s u r e L O W p e r i o d A Vsep signal is generated at a rising of the timing signal imm ediately after the LOW level width of the composite sync signal exceeds a certain time.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 52 of 127 REJ03B0132-0100Z

8.10.5 Timing Signal Generating Circuit

This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 1 (address 00E0 16) to “1.” The reference clock can be used as a display clock for OSD function in addition to the data slicer. The H SYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00E016). For the pins HLF, connect a resistor and a capacitor as shown in Figure 8.10.1. Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be gener- ated. Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep sig- nals become unstable. For this reason, take stabilization time into con- sideration when programming. Fig. 8.10.7 Determination of V-pulse Waveform Composite sync signal AB Bit 5 of DSC2

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 53 of 127 REJ03B0132-0100Z

8.10.6 Data Slice Line Specification Circuit

(1) Specification of data slice line This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their data. The caption position register (address 00E616) is used for each setting (refer to Table 8.10.1). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is sliced. The values of “0016” to “1F16” can be set in the caption position register (at setting only 1 appropriate line). Figure 8.10.8 shows the signals in the vertical blanking interval. Figure 8.10.9 shows the structure of the caption position register. (2) Specification of line to set slice voltage The reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular line (refer to Table 8.10.1). The field to generate slice voltage is specified by bit 1 of data slicer control register 1. The line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to Table 8.10.1). Fig. 8.10.8 Signals in Vertical Blanking Interval (3) Field determination The field determination flag can be read out by bit 3 of data slicer control register 2. This flag charge at the falling edge of Vsep. Video signal Vertical blanking interval Composite video signal Count value to be set in the caption position register (“0F16” in this case) H sep V sep H sep Magnified drawing Clock run-in Start bit + 16-bit data Start bit Window for deteminating clock-run-in Composite video signal Line 21 1 appropriate line is set by the caption position register (when setting line 19)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 54 of 127 REJ03B0132-0100Z Fig. 8.10.9 Caption Position Register Field and Line to Generate Slice Voltage

• F ield specified by bit 1 of DSC1
• Line 21 (total 1 line)
• F ield specified by bit 1 of DSC1
• A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3)
• F ield specified by bit 1 of DSC1
• Line 21 (total 1 line)
• F ield specified by bit 1 of DSC1
• Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) Field and Line to Be Sliced Data
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2)
• Both fields of F1 and F2
• A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3)
• Both fields of F1 and F2
• Line 21 (total 1 line)
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) CPS Notes 1:DSC1 is data slicer control register 1. CPS is caption position register. 2:Set “0016” to “1016” to bits 4 to 0 of CPS. 3:Set “0016” to “1F16” to bits 4 to 0 of CPS. Table 8.10.1 Specification of Data Slice Line b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616] Caption Position Register to

bits(CPS0 to CPS4) 6, 7 Refer to the corresponding Table (Table 8.10.1). Slice line mode specification bits (in 1 field) (CPS6, CPS7) 5 0: Data is not latched yet and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Caption data latch completion flag 2 (CPS5) IndeterminateR B After resetFunctionsNam e R W

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 55 of 127 REJ03B0132-0100Z

8.10.7 Reference Voltage Generating Circuit

The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. (1) Reference voltage generating circuit This circuit generates a reference voltage (slice voltage) by us- ing the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. Connect a capacitor between the V HOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be gener- ated. (2) Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the refer- ence voltage generating circuit, and converts the composite video signal into a digital value. Fig. 8.10.10 Clock Run-in Detect Register

8.10.8 Start Bit Detecting Circuit

This circuit detects a start bit at line decided in the data slice line specification circuit. The detection of a start bit is described below. ➀ A sampling clock is generated by dividing the reference clock out- put by the timing signal. ➁ A clock run-in pulse is detected by the sampling clock. ➂ After detection of the pulse, a start bit pattern is detected from the comparator output.

8.10.9 Clock Run-in Determination Circuit

This circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. The reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 00E4 16). Read out these bits after the occurrence of a data slicer interrupt (refer to “8.10.12 Interrupt Request Generating Circuit”). Figure 8.10.10 shows the structure of clock run-in detect register. b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00E416] R W Clock Run-in Detect Register to 0R —Test bits to Number of reference clocks to be counted in one clock run-in pulse period. Clock run-in detection bit (CRD3 to CRD7) 0R — Read-only B After resetFunctionsName

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 56 of 127 REJ03B0132-0100Z

8.10.10 Data Clock Generating Circuit

This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. The data clock stores cap- tion data to the 16-bit shift register. When the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. This flag is reset at a falling of the vertical synchronous signal (V sep). Fig. 8.10.11 Data Clock Position Register b 7 b 6 b 5 b 4 b 3 b2 b 1 b 0 D a t a c l o c k p o s i t i o n r e g i s t e r ( D P S ) [ A d d r e s s 0 0 E 51 D a t a C l o c k P o s i t i o n R e g i s t e r 01 R WF i x t h i s b i t t o “ 0 . ” 1 F i x t h i s b i t t o “ 1 . ” 0 R W 100 B After resetFunctionsN ame R W

3 D ata clock position set

bits (DPS3 to DPS7)

1 R W

t o 2 F i x t h i s b i t t o “ 0 . ” 0 R W

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 57 of 127 REJ03B0132-0100Z 8.10.11 16-bit Shift Register The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. The contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00E3 16) and data register 4 (address 00CF16). The contents of the low-order 8 bits can be obtained by reading out data register 1 (address 00E216) and data register 3 (address 00CE16), respectively. These registers are reset to “0” at a falling of Vsep. Read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to “8.10.12 Inter- rupt Request Generating Circuit”).

8.10.12 Interrupt Request Generating Circuit

The interrupt requests as shown in Table 8.10.3 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 00E6 16). Read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request. Slice Line Specification Mode CPS Completion Flag 1 (bit 0 of DSC2) Completion Flag 2 (bit 5 of CPS) Caption Data Registers 1, 2 Caption Data Registers 3, 4 Line 21 A line specified by bits 4 to 0 of CPS Line 21 Line 21 A line specified by bits 4 to 0 of CPS Invalid Invalid A line specified by bits 4 to 0 of CPS 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of CPS 16-bit data of line 21 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of CPS Invalid Invalid 16-bit data of a line specified by bits 4 to 0 of CPS Contents of Caption Data Latch Completion Flag Contents of 16-bit Shift Register bit 7 bit 6 CPS: Caption position register DSC2: Data slicer control register 2 Table 8.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register Caption position register Occurence Souces of Interrupt Request at End of Data Slice Line After slicing line 21 After a line specified by bits 4 to 0 of CPS After slicing line 21 After slicing line 21 Table 8.10.3 Occurence Sources of Interrupt Request

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 58 of 127 REJ03B0132-0100Z Fig. 8.10.12 Sync Pulse Counter Register

8.10.13 Synchronous Signal Counter

The synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal V sep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “1F16,” “1F16” is stored into the latch. Fig. 8.10.13 Synchronous Signal Counter Block Diagram The latch value can be obtained by reading out the sync pulse counter register (address 00E916). A count source is selected by bit 5 of the sync pulse counter register. The synchronous signal counter is used when bit 0 of PWM mode register 1 (address 020816). Figure 8.10.12 shows the structure of the sync pulse counter and Figure 8.10.13 shows the synchronous signal counter block diagram. b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E916] R W Sync Pulse Counter Register to 6, 7 0 R Count value (HC0 to HC4) 5 0R WCount source (HC5) 0: H SYNC signal 1: Composite sync signal B After resetFunctionsName Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are 0. Reset 5-bit counter Latch (5 bits) f(XIN)/213 Composite sync signal H SYNC signal Counter Sync pulse counter register Data busSelection gate : connected to black side when reset.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 59 of 127 REJ03B0132-0100Z

8.11 OSD FUNCTIONS

Table 8.11.1 outlines the OSD functions. This microcomputer incorporates an OSD circuit of 32 characters ✕ 2 lines. And also, there are 2 display modes and they are selected by a block unit. The display modes are selected by bits 0 and 1 of block control register i (i = 1 and 2). The features of each mode are described below. Table 8.11.1 Features of Each Display Mode Number of display characters 32 characters ✕ 2 lines Dot structure 16 ✕ 26 dots (Character display area : 16 ✕ 20 dots) 16 ✕ 20 dots Kinds of characters 254 kinds Kinds of character sizes 1 kinds 8 kinds Pre-divide ratio (See note) ✕ 2 (fixed) ✕ 2, ✕ 3 Dot size 1T C ✕ 1/2H 1T C ✕ 1/2H, 1TC ✕ 1H, 2TC ✕ 2H, 3TC ✕ 3H Attribute Smooth italic, under line, flash Border (black) Character font coloring 1 screen : 8 kinds (per character unit) Character background coloring 1 screen : 8 kinds (per character unit) OSD output R, G, B Raster coloring Possible (per character unit) Function Auto solid space function Window function Display position Horizontal: 128 levels, Vertical: 512 levels Display expansion (multiline display) Possible Parameter Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to 8.11.2 Dot Size). Display mode CC mode (Closed caption mode) OSD mode (Border OFF) (On-screen display mode)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 60 of 127 REJ03B0132-0100Z The OSD circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by inter- rupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. shows the block diagram of the OSD circuit. Figure 8.11.3 shows the OSD control register. Figure 8.11.4 shows the block control register i. Fig. 8.11.1 Configuration of OSD Character Display Area 16 dots 26 dots 20 dots Underline area✽ Blank area✽ ✽: Displayed only in CCD mode. Blank area✽ 20 dots OSD mode CC mode 16 dots

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 61 of 127 REJ03B0132-0100Z Fig. 8.11.2 Block Diagram of OSD Circuit D i s p l a y o s c i l l a t i o n c i r c u i t O S C 1 OSC2 H S Y N C VSYNC RAM for OSD 2 bytes ✕ 32 characters ✕ 2 lines D a t a b u s R O M f o r O S D d o t s d o t s c h a r a c t e r s Shift register 16-bit D a t a s l i c e r c l o c k C l o c k f o r O S D O u t p u t c i r c u i t R G B O S D C o n t r o l c i r c u i t O U T 1 O U T 2 Control registers for OSD (address 00D016) (address 00D116) (addresses 00D216, 00D3 16) (addresses 00D416, 00D5 16) (addresses 00D616, 00D7 16) (address 00D816) (address 00D916) OSD control register Horizontal position register Block control register i Vertical position register i Window register i I/O polarity control register Raster color register

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 62 of 127 REJ03B0132-0100Z Fig. 8.11.3 OSD Control Register b7 b6 b5b4 b3 b2b1 b0 OSD control register (OC) [Address 00D016] B Name Functions After resetR W OSD Control Register 0O SD control bit (OC0) (See note) 0 : All-blocks display off 1 : All-blocks display on

1 Automatic solid space

control bit (OC1) 0 : OFF 1 : ON 2 0 : OFF 1 : ON 4O SD mode clock selection bit (OC4) Window control bit (OC2) RW RW RW RW RW 3 0 : Data slicer clock 1 : Clock from OSC1 pin CC mode clock selection bit (OC3) 5, 6OSC1 clock selection bit (OC5, OC6) 0 0: 32 kHz oscillating 0 1: Do not set. 1 0: LC oscillating, Ceramic oscillating 1 1: Do not set. b6 b5 0 : Data slicer clock 1 : Clock from OSC1 pin 7 Fix this bit to 0. 0R W 0R W Note: Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC .

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 63 of 127 REJ03B0132-0100Z Fig. 8.11.4 Block Control Register i b7 b6 b5b4 b3 b2b1 b0 Block control register i (BCi) (i=1, 2) [Addresses 00D216 and 00D316] Block Control register i 0, 1 Display mode selection bits (BCi0, BCi1) (See note 1) Indeterminate 2, 3 Dot size selection bits (BCi2, BCi3) b4 b3 b2 Pre-divide RatioDot Size

4 Pre-divide ratio

selection bit (BCi4) 7W indow top/bottom boundary control bit (BCi7) Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.” Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.” 2: Tc is OSD clock cycle divided in pre-divide circuit. 3: H is HSYNC . OUT1/OUT2 output control bit (BCi5) (See note 1) 0: OUT1 output control 1: OUT2 output control

6 Vertical display start

(BCi6) BC16: Block 1 BC26: Block 1 b1 b0 0 0: Display OFF 0 1: CC mode 1 0: OSD mode (Border OFF) 1 1: OSD mode (Border ON) ✕ 2 ✕ 3 1Tc ✕ 1/2H 1Tc ✕ 1H 2Tc ✕ 2H 3Tc ✕ 3H 1Tc ✕ 1/2H 1Tc ✕ 1H 2Tc ✕ 2H 3Tc ✕ 3H BC17: Window top boundary BC27: Window bottom boundary B Name Functions After resetRW RW IndeterminateRW IndeterminateRW IndeterminateRW IndeterminateRW IndeterminateRW

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 64 of 127 REJ03B0132-0100Z

8.11.1 Display Position

The display positions of characters are specified in units called a “block.” There are 2 blocks, blocks 1 and 2. Up to 32 characters can be displayed in each block (refer to “8.11.5 Memory for OSD”). The display position of each block can be set in both horizontal and vertical directions by software. The display start position in the horizontal direction can be selected for all blocks in common from 128-step display positions in units of OSC (TOSC = OSD oscillation cycle). The display start position in the vertical direction for each block can be selected from 512-step display positions in units of 1 T H ( TH = H SYNC cycle). Blocks are displayed in conformance with the following rules:

• When the display position of block 1 is overlapped with that of block 2 (Figure 8.11.5 (b)), the block 1 is displayed on the front.
• When another block display position appears while one block is displayed (Figure 8.11.5 (c)), the block with a larger set value as the vertical display start position is displayed. Fig. 8.11.5 Display Position (HP) V P 2 B l o c k 1 B l o c k 2 ( a ) E x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d B l o c k 1 ( b ) E x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 ( B l o c k 2 i s n o t d i s p l a y e d ) (HP) V P 1 V P 2 ( c ) E x a m p l e w h e n b l o c k 2 o v e r l a p s i n p r o c e s s o f b l o c k 1 B l o c k 1 Block 2 N ote: VP 1 or VP 2 indicates the vertical display start position of display block 1 or 2. VP 1 ( H P ) V P 1 = V P 2

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 65 of 127 REJ03B0132-0100Z The vertical display start position is determined by counting the hori- zontal sync signal (HSYNC ). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of H SYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of H SYNC and VSYNC signals can select with the I/O po- larity control register (address 00D816). Fig. 8.11.6 Supplement Explanation for Display Position W h e n b i t s 0 a n d 1 o f t h e I / O p o l a r i t y c o n t r o l r e g i s t e r a d d r e s s D a r e s e t t o n e g a t i v e p o l a r i t y VS Y N C s i g n a l i n p u t VS Y N C c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o [µs a t f XI N ) M H z Period of counting H SYNC signal (See note 2) H SYNC signal input Not count 12345 N o t e s 1 : T h e v e r t i c a l p o s i t i o n i s d e t e r m i n e d b y c o u n t i n g f a l l i n g e d g e o f H S Y N C s i g n a l a f t e r r i s i n g e d g e o f VS Y N C c o n t r o l s i g n a l i n t h e m i c r o c o m p u t e r : D o n o t g e n e r a t e f a l l i n g e d g e o f H S Y N C s i g n a l n e a r r i s i n g e d g e o f VS Y N C c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o a v o i d j i t t e r : T h e p u l s e w i d t h o f VS Y N C a n d H S Y N C n e e d s m a c h i n e c y c l e s o r m o r e m a c h i n e c y c l e s o r m o r e 8 ma chine cycles or more

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 66 of 127 REJ03B0132-0100Z Fig. 8.11.7 Vertical Position Register i (i = 1 and 2) The vertical display start position for each block can be set in 512 steps (where each step is 1TH (TH : HSYNC cycle)) as values “0016” to “FF16” in vertical position register i (i = 1 and 2) (addresses 00D416 and 00D516) and values “0” or “1” in bit 6 of block control register i (i = 1 and 2) (addresses 00D216 and 00D316). The vertical position registers is shown in Figure 8.11.7. b7 b6 b5 b4 b3 b2 b1 b0 to R W Vertical Position Register i Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516] B Name Functions After reset RW InderterminateVertical display start position control bits (VPi0 to VPi7) (See note) Vertical display start position = T H ✕ (BCi6 ✕ 162 + n) (n: setting value, TH : HSYNC cycle, BCi6: bit 6 of block control register i) Note: Set values except “0016” to VPi when BCi6 is “0.”

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 67 of 127 REJ03B0132-0100Z The horizontal display start position is common to all blocks, and can be set in 128 steps (where 1 step is 4TOSC , TOSC being the OSD oscillation cycle) as values “0016” to “FF16” in bits 0 to 6 of the hori- zontal position register (address 00D116). The horizontal position reg- ister is shown in Figure 8.11.8. Fig. 8.11.8 Horizontal Position Register Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different pre-divide ratios, their horizontal dis- play start position will not match. 2 : The horizontal start position is based on the OSD clock source cycle selected for each block. Accordingly, when 2 blocks have different OSD clock source cycles, their horizontal display start position will not match. 3 : When setting “00 16” to the horizontal position register, it needs ap- proximately 62TOSC (= Tdef) interval from a rising edge (when nega- tive polarity is selected) of HSYNC signal to the horizontal display start position. Fig. 8.11.9 Notes on Horizontal Display Start Position TO S C ’ ✕ N T O S C ✕ N H S Y N C 1 TC T C 1TC N o t e 1 N o t e 2 B l o c k 2 ( P r e - d i v i d e r a t i o = 2 , c l o c k s o u r c e = d a t a s l i c e r c l o c k ) B l o c k 3 ( P r e - d i v i d e r a t i o = 3 , c l o c k s o u r c e = d a t a s l i c e r c l o c k ) Block 4 (Pre-divide ratio = 3, clock source = OSC1) Td e f Td e N : V a l u e o f h o r i z o n t a l p o s i t i o n r e g i s t e r ( d e c i m a l n o t a t i o n ) TC : O S D c l o c k c y c l e d i v i d e d i n p r e d i v i d e c i r c u i t TO S C : O S D o s c i l l a t i o n c y c l e Td e f : TO S C b7 b6 b5b4 b3 b2b1 b0 Horizontal position register (HP) [Address 00D116] BN a m e Horizontal Position Register Horizontal display start position control bits (HP0 to HP6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Functions After reset R W Horizontal display start positions 128 steps (0016 to 7F16) (1 step is 4TOSC ) RW to Note: The setting value synchronizes with the V SYNC .

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 68 of 127 REJ03B0132-0100Z Fig. 8.11.10 Block Diagram of Dot Size Control Circuit

8.11.2 Dot Size

The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size con- trol circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1T C . The dot size of each block is specified by bits 2 to 4 of the block control register i. Refer to Figure 8.11.4 (the structure of the block control register). The block diagram of dot size control circuit is shown in Figure 8.11.10. Fig. 8.11.11 Definition of Dot Sizes D a t a s l i c e r c l o c k H S Y N C O S C 1 O C 3 o r O C 4 Synchronous circuit Cycle ✕ 3 P r e - d i v i d e c i r c u i t C l o c k c y c l e T C H o r i z o n t a l d o t s i z e c o n t r o l c i r c u i t Vertical dot size control circuit OSD control circuit C y c l e ✕ 2 “0” “1” B C i 4 N o t e : T o u s e d a t a s l i c e r c l o c k , s e t b i t 0 o f d a t a s l i c e r c o n t r o l r e g i s t e r 1 t o “ 1 . ” 1 dot Scanning line of F1(F2) Scanning line of F2(F1) 1/2H 1 H H T C2TC1 T T C

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 69 of 127 REJ03B0132-0100Z b7 of raster color register OSD control register I/O Port

8.11.3 Clock for OSD

As a clock for display to be used for OSD, it is possible to select one of the following 3 types.

• Data slicer clock output from the data slicer (approximately 26 MHz)
• OSC1 clock supplied from the pins OSC1 and OSC2
• Clock from the ceramic resonator or the LC oscillator from the pins OSC1 and OSC2 This OSD clock for each block can be selected by the following bits : bit 7 of the raster color register (address 00D9 16), bits 3 to 6 of the clock source control register (addresses 00D016). A variety of char- acter sizes can be obtained by combining dot sizes with OSD clocks. When not using the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins can be used as sub-clock I/O pins or port P2. Fig. 8.11.12 Block Diagram of OSD Selection Circuit Table 8.11.2 Setting for P26/OSC1/XCIN, P27/OSC2/XCOUT OSD clock I/O Pin Sub-clock I/O Pin Function Register “0” “10” “ 0 ” D a t a s l i c e r c i r c u i t Data slicer clock (See note) OSC1 clock C eramic · LC O s c i l l a t i n g m o d e f o r O S D O C 6 , O C 5 “ 1 ” 1 ” OC3 OC4 C C m o d e b l o c k OSD mode block N o t e : T o u s e d a t a s l i c e r c l o c k , s e t b i t 0 o f d a t a s l i c e r c o n t r o l r e g i s t e r 1 t o “ 1 . ”

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8.11.4 Field Determination Display

To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchro- nizing signal waveform of interlacing system. The dot line 0 or 1 (re- fer to Figure 8.11.14) corresponding to the field is displayed alter- nately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are nega- tive-polarity inputs will be explained. A field determination is deter- mined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the V SYNC control signal (refer to Figure 8.11.6) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the compar- ing time, it is regarded as even field. When the time is shorter, it is regarded as odd field The contents of this field can be read out by the field determination flag (bit 6 of the I/O polarity control register at address 00D8 16). A dot line is specified by bit 5 of the I/O polarity control register (refer to Figure 8.11.14). However, the field determination flag read out from the CPU is fixed to “0” at even field or “1” at odd field, regardless of bit 5. Fig. 8.11.13 I/O Polarity Control Register 0 : “ ” at even field “ ” at odd field 1 : “ ” at even field “ ” at odd field b7 b6 b5 b4 b3 b2 b1 b0 I/O polarity control register (PC) [Address 00D816] B Name Functions After resetR W I/O Polarity Control Register 0H SYNC input polarity switch bit (PC0) 0 : Positive polarity input 1 : Negative polarity input 1 0 : Positive polarity input 1 : Negative polarity input

2 R, G, B output polarity

switch bit (PC2) 0 : Positive polarity output 1 : Negative polarity output

3 OUT1 output polarity

switch bit (PC3) 0 : Positive polarity output 1 : Negative polarity output

4 OUT2 output polarity

switch bit (PC4) 0 : Positive polarity output 1 : Negative polarity output

5 Display dot line selection

bit (PC5) (See note)

06 Field determination flag

(PC6) 0 : Even field 1 : Odd field 7 0 VSYNC input polarity switch bit (PC1) RW RW RW RW RW RW RWFix this bit to “0.” Note: Refer to the corresponding figure (8.11.14).

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 71 of 127 REJ03B0132-0100Z Fig. 8.11.14 Relation between Field Determination Flag and Display Font Both HSYNC signal and VSYNC signal are negative-polarity input Field Even Odd Field determination flag(Note) Display dot line selection bit Display dot line 0 (T2 > T1) 1 (T3 < T2) When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208 16) to “0.” OSD ROM font configuration diagram Dot line 0 Dot line 1 Odd Dot line 0 Dot line 1 (n -1) field (Odd-numbered) 0.25 to 0.50[µs] at f(XIN) = 8 MHz CC mode 13 57 9 1 1 1 3 1 5 24 681 0 12 14 16 13 5 7 9 1 1 1 3 1 524 6 8 1 0 12 14 16 OSD mode H SYNC V SYNC and V SYNC control signal in microcom- puter Upper : VSYNC signal Lower : VSYNC control signal in micro- computer (n) field (Even-numbered) (n +1) field (Odd-numbered) When the display dot line selection bit is “0,” the “ ” font is displayed at even field, the “ ” font is displayed at odd field. Bit 6 of the I/O polarity control register can be read as the field determination flag : “1” is read at odd field, “0” is read at even field. Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in the microcomputer.

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8.11.5 Memory for OSD

There are 2 types of memory for OSD : OSD ROM used to store character dot data and OSD RAM used to specify the characters and colors to be displayed. <M3727GM6/M8-XXXSP/FP , M37272E8SP/FP> OSD ROM : addresses 1400 16 to 3BFF16 OSD RAM : addresses 080016 to 087F16 Fig. 8.11.15 Character Font Data Storing Address O S D R O M a d d r e s s o f c h a r a c t e r f o n t d a t a AD 15 AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 L i n e n u m b e r C h a r a c t e r c o d e F o n t b i t = 0 A t o 1 D 1 t o F a n d c a n n o t b e u s e d L e f t a r e a R i g h t a r e a O S D R O M a d d r e s s b i t L i n e n u m b e r / c h a r a c t e r c o d e f o n t b i t 0 L i n e n u m b e rC haracter code F o n t b i t 0A 000016

7 F F 01

B 12 601 C 16 F F 81 F F 01 3 0 0 3 8 0 C 01 E 01 0 7 0 1 4 0 3 8 0 1 C 1 600C 16 0 0 0 D A B C b0b7 b 0b7 L i n e n u m b e r L e f t a r e a Right area D a t a i n O S D R O M Character font AD 16 (1) OSD ROM (addresses 140016 to 3BFF16) The dot pattern data for OSD characters is stored in OSD ROM. To specify the kinds of the character font, it is necessary to write the character code into the OSD RAM. Data of the character font is specified shown in Figure 8.11.15.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 73 of 127 REJ03B0132-0100Z Notes 1 : The 80-byte addresses corresponding to the character code “7F16” and “8016” in OSD ROM are the test data storing area. Set data to the area as follows. <Test data storing area> ■ M37272M6/M8-XXXSP/FP , M37272E8SP/FP addresses 100016 + (4 + 2n) ✕ 10016 + FE16 to 100016 + (5 + 2n) ✕ 10016 + 0116 (n = 0 to 19) (1)Mask version (M3727GM6/M8-XXXSP/FP) Set “FF16” to the area (We stores the test data to this area and the different data from “FF16” is stored for the actual products.) When using our font editor, the test data is written automatically. (2)EPROM version (M37272E8SP/FP) Set the test data to the area. When using our font editor, the test data is written automatically. 150016 (9016), 150116 (A116) 170016 (0016), 170116 (A216) 190016 (4816), 190116 (A316) 1B0016 (0016), 1B0116 (A416) 1D00 16 (2416), 1D0116 (A516) 1F0016 (0016), 1F0116 (A616) 210016 (1216), 210116 (A716) 230016 (0016), 230116 (A816) 250016 (0916), 250116 (A916) 270016 (0016), 270116 (AA16) 290016 (8116), 290116 (AB16) 2B0016 (1816), 2B0116 (AC16) 2D00 16 (0016), 2D0116 (AD16) 2F0016 (4216), 2F0116 (AE16) 310016 (2416), 310116 (AF16) 330016 (0016), 330116 (B016) 350016 (8116), 350116 (B116) 370016 (0C16), 370116 (B216) 390016 (0616), 390116 (B316) 3B0016 (0016), 3B0116 (B416) 2 : The character code “0916” is used for “transparent space” when displaying Closed Caption. Therefore, set “0016” to the 40-byte addresses corresponding to the character code “0916.” <Transparent space font data storing area> ■ M3727GM6/M8-XXXSP/FP, M37272E8SP/FP addresses 1000 16 + (4 + 2n) ✕ 10016 + 1216 to 100016 + (4 + 2n) ✕ 10016 + 1316 (n = 0 to 19) addresses 141216 and 141316 addresses 161216 and 161316 addresses 381216 and 381316 addresses 3A1216 and 3A1316 14FE 16 (0916), 14FF16 (5116) 16FE 16 (0016), 16FF16 (5216) 18FE 16 (1216), 18FF16 (5316) 1AFE 16 (0016), 1AFF16 (5416) 1CFE 16 (2416), 1CFF16 (5516) 1EFE 16 (0016), 1EFF16 (5616) 20FE 16 (8816), 20FF16 (5716) 22FE 16 (0016), 22FF16 (5816) 24FE 16 (9016), 24FF16 (5916) 26FE 16 (4816), 26FF16 (5A16) 28FE 16 (2416), 28FF16 (5B16) 2AFE 16 (0016), 2AFF16 (5C16) 2CFE 16 (2416), 2CFF16 (5D16) 2EFE 16 (4816), 2EFF16 (5E16) 30FE 16 (0016), 30FF16 (5F16) 32FE 16 (4816), 32FF16 (5016) 34FE 16 (9016), 34FF16 (5116) 36FE 16 (0016), 36FF16 (5216) 38FE 16 (0116), 38FF16 (5316) 3AFE 16 (8016), 3AFF16 (5416) <“FF16”> address (test data) ■ M37272E8SP/FP <“8016”> address (test data)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 74 of 127 REJ03B0132-0100Z Table 8.11.3 Contents of OSD RAM Block Character Code Specification Color Code Specification 31st character 3rd character 30th character 2nd character 32nd character 31st character 3rd character 30th character 1st character 2nd character 32nd character 081E16 080216 081D 16 080116 081F16 085E16 084216 085D 16 084016 084116 085F16 083E16 082216 083D 16 082116 083F16 087E16 086216 087D 16 086016 086116 087F16 Block 1 Display Position (from left) Block 2 1st character 080016 082016 (2) OSD RAM The RAM for OSD is allocated at addresses 080016 to 087F16, and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. Table 8.11.3 shows the contents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write the color code 1 at 082016. The structure of the OSD RAM is shown in Figure 8.11.16.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 75 of 127 REJ03B0132-0100Z Fig. 8.11.16 Bit structure of OSD RAM Bit name Control of character color R Control of character color G Control of character color B OUT1/OUT2 control Flash control Underline control Italic control Bit RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RA0 RA1 RA2 RA3 RA4 RA5 RA6 Function Character code in OSD ROM 0: Color signal output OFF 1: Color signal output ON 0: Flash OFF 1: Flash ON 0: Underline OFF 1: Underline ON 0: Italic OFF 1: Italic ON Bit name Control of character color R Control of character color G Control of character color B OUT1/OUT2 control Control of background color R Control of background color G Control of background color B CC mode Function Character code in OSD ROM 0: Color signal output OFF 1: Color signal output ON 0: Color signal output OFF 1: Color signal output ON OSD mode Notes 1: Read value of bits 7 of the color code is “0.” 2: For OUT1/OUT2 control, refer to “8.11.8 OUT1/OUT2 signal.” 3: “7F16” and “8016” cannot be used as character code. Character code Character code (See note 2) (See note 2) R A 6 R A 5 R A 4 R A 3 R A 2 R A 1 R A

0 RF7 R

F 6 R F 5 R F 4 R F 3 R F 2 R F F b B l o c k s 1 , 2 C h a r a c t e r c o d e ( S e e n o t e 3 )C o l o r c o d e 1 ( S e e n o t e 1 )

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 76 of 127 REJ03B0132-0100Z

8.11.7 Character background color

The character background color can be displayed in the character display area only in the OSD mode. The character background color for each character is specified by the color code. <7 kinds> Specified by bits 4 (R), 5 (G), and 6 (B) of the color code Note : The character background color is displayed in the following part : (character display area)–(character font)–(border). Accordingly, the character background color does not mix with these color signal.

8.11.6 Character color

The color for each character is displayed by the color code. <7 kinds> Specified by bits 0 (R), 1 (G), and 2 (B) of the color code

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 77 of 127 REJ03B0132-0100Z

8.11.8 OUT1, OUT2 signals

The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by display mode, bit 5 of the block control register i (refer to Figure 8.11.4) and RA3 of OSD RAM. The setting values for Fig. 8.11.17 Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 8.11.17. Note : When OUT2 signal is output, set bit 7 of OSD port control register (refer to Figure 8.11.28) to “1.” (OUT1 output is controlled by RA3) OUT1 = FONT/B O RDER D i s p l a y M o d e O U T 1 / O U T 2 O u t p u t C o n t r o l B i t b O U T 1 / O U T 2 C o n t r o l Output Waveform (A-A') OSD CC (OUT2 output is controlled by RA3) OUT2 = “L” OUT1 = AREA OUT2 = “L” OUT1 = FONT/B O RDER OUT2 = “L” OUT1 = FONT/B O RDER OUT2 = AREA OUT1 = FONT OUT2 = “L” OUT1 = AREA OUT2 = “L” OUT1 = FONT OUT2 = “L” OUT1 = FONT OUT2 = AREA A A ' (OUT1 output is controlled by RA3) (OUT2 output is controlled by RA3) I n t h e O S D m o d e B o r d e r O F F O U T o u t p u t s t o o n l y t h e f o n t a r e a A R E A U T O U T o u t p u t s t o e n t i r e d i s p l a y a r e a o f c h a r a c t e r F O N T n t h e C C m o d e O U T o u t p u t s t o f o n t a r e a : W h e n t h e a u t o m a t i c s o l i d s p a c e f u n c t i o n i s O F F i n t h e C C m o d e A R E A o u t p u t s a c c o r d i n g t o b i t o f c o l o r c o d e W h e n i t i s O N t h e s o l i d s p a c e i s a u t o m a t i c a l l y o u t p u t b y a c h a r a c t e r c o d e r e g a r d l e s s o f R A Block Control Register i R A 3 o f O S D R A M

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8.11.9 Attribute

The attributes (border, flash, underline, italic) are controlled to the character font. The attributes to be controlled are different depend- ing on each mode. (1) Under line The underline is output at the 23th and 24th dots in vertical direction only in the CC mode. The underline is controlled by RA5 of OSD RAM. The color of underline is the same color as that of the charac- ter font. (2) Flash The character font and the underline are flashed only in the CC mode. The flash is controlled by RA4 of OSD RAM. As for character font part, the character output part is flashed, the character background part is not flashed. The flash cycle bases on the V SYNC count.

• VSYNC cycle ✕ 48 ≈ 800 ms (at display ON)
• VSYNC cycle ✕ 16 ≈ 267 ms (at display OFF) (3) Italic The italic is made by slanting the font stored in OSD ROM to the right only in the CC mode. The italic is controlled by RA6 of OSD RAM. The display example of the italic and underline is shown in Figure 8.11.8. In this case, “R” is displayed. Notes 1: When setting both the italic and the flash, the italic character flashes. 2: The boundary of character color is displayed in italic. However, the boundary of character background color is not affected by the italic (refer to Figure 8.11.19). 3: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 8.11.19).

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 79 of 127 REJ03B0132-0100Z Fig. 8.11.18 Example of Attribute Display (in CC Mode) C o l o r c o d e B i t 6 R A B i t 5 R A C o l o r c o d e B i t 6 R A B i t 5 R A C o l o r c o d e B i t 6 R A B i t 5 R A C o l o r c o d e B i t 6 R A B i t 5 R A ( a ) O r d i n a r y( b ) U n d e r l i n e ( c ) I t a l i c ( p r e - d i v i d e r a t i o = 1 )( d ) I t a l i c ( p r e - d i v i d e r a t i o = 2 ) f l a s hf l a s hf l a s h O F FO F F O NO N C o l o r c o d e B i t 6 R A B i t 5 R A B i t 4 R A 111 ( e ) U n d e r l i n e a m d I t a l i c a n d f l a s h

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 80 of 127 REJ03B0132-0100Z Fig. 8.11.19 Example of Italic Display 10 0 1 1 0 1 ( R e f e r t o “ 8 . 1 1 . 9 N o t e s 2 , 3 ” )( R e f e r t o “8.11.9 Notes 2, 3”) R A 6 o f O S D R A M N o t e s 1 : T h e d o t t e d l i n e i s t h e b o u n d a r y o f c h a r a c t e r c o l o r . W h e n b i t o f O S D c o n t r o l r e g i s t e r i s 6 t h c h r a c t e r

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 81 of 127 REJ03B0132-0100Z (4) Border The border is output around of character font (all bordered) in the OSD mode. The border ON/OFF is controlled by bit 0 and 1 of the block control register i (refer to Figure 8.11.4). The OUT1 signal is used for border output. The horizontal size (x) of border is 1T C (OSD clock cycle divided in pre-divide circuit) regardless of the character font dot size. The verti- cal size (y) different depending on the screen scan mode and the vertical dot size of character font. Notes 1 : The border dot area is the shaded area as shown in Figure 8.11.20. 2 : When the border dot overlaps on the next character font, the charac- ter font has priority (refer to Figure 8.11.22 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 8.11.22 B). 3 : The border in vertical out of character area is not displayed (refer to Figure 8.11.22). Fig. 8.11.20 Example of Border Display Fig. 8.11.21 Horizontal and Vertical Size of Border A l l b o r d e r e d 1 6 d o t s 2 0 d o t s OSD mode 1 d o t w i d t h o f b o r d e r 1 d o t w i d t h o f b o r d e r Character font area y x 1 / 2 H 1H, 2H, 3H 1 / 2 H 1 H Vertical dot size of character fontB o r d e r d o t s i z e H o r i z o n t a l s i z e ( x ) V e r t i c a l s i z e ( y ) T c ( O S D c l o c k c y c l e d i v i d e d i n p r e d i v i d e c i r c u i t

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 82 of 127 REJ03B0132-0100Z Fig. 8.11.22 Border Priority Character boundary B Character boundary A Character boundary B

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 83 of 127 REJ03B0132-0100Z

8.11.10 Multiline Display

This microcomputer can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register (addresses 00D216, 00D3 16), an OSD interrupt request does not occur (refer to Figure 8.11.23 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 8.11.23 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 8.11.23 (C)). Fig. 8.11.23 Note on Occurence of OSD Interrupt (B) (C) Block 1 (on display) Block 2 (on display) Block 1’ (on display) Block 2’ (on display) Block 1 (on display) Block 2 (on display) Block 1’ (off display) Block 2’ (off display) “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” No “OSD interrupt request” Block 1 Block 2 “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” Block 1 Block 2 Block 1’ On display (OSD interrupt request occurs at the end of block display) Off display (OSD interrupt request does not occur at the end of block display) In CC mode Window No “OSD interrupt request” No “OSD interrupt request” (A)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 84 of 127 REJ03B0132-0100Z Notes : The character code “0916” is used for “transparent space” when dis- playing Closed Caption. Therefore, set “0016” to the 40-byte addresses corresponding to the character code “0916.” <Transparent space font data storing area> ■ M3727GM6/M8-XXXSP/FP, M37272E8SP/FP addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to 100016 + (4 + 2n) ✕ 10016 + 1316 (n = 0 to 19) addresses 141216 and 141316 addresses 161216 and 161316 addresses 381216 and 381316 addresses 3A1216 and 3A1316

8.11.11 Automatic Solid Space Function

This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area :

• Any character area except character code “09 16 ”
• Character area on the left and right sides of the above character This function is turned on and off by bit 1 of the OSD control register (refer to Figure 8.11.3). Fig. 8.11.24 Display Screen Example of Automatic Solid Space 90 90 61 61 06 0 16 1
• • •
• • • W h e n s e t t i n g t h e c h a r a c t e r c o d e “ 0 51 6” a s t h e c h a r a c t e r A , “ 0 61 6” a s t h e c h a r a c t e r B . ( O S D R A M ) D i s p l a y s c r e e n ) 1 s t c h a r a c t e r 2 n d c h a r a c t e r No blank output 31st character 3 2 n d c h a r a c t e r T h e s o l i d s p a c e i s a u t o m a t i c a l l y o u t p u t o n t h e l e f t s i d e o f t h e 1 s t c h a r a c t e r a n d o n t h e r i g h t s i d e o f t h e n d c h a r a c t e r b y s e t t i n g t h e s t a n d n d o f t h e c h a r a c t e r c o d e

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 85 of 127 REJ03B0132-0100Z

8.11.12 Window Function

This function sets the top and bottom boundary of display limit on a screen. The window function is valid only in the CC mode. The top boundary is set by the window registers 1 and bit 7 of block control register 1. The bottom boundary is set by window registers 1 and bit 7 of block control register 2. This function is turned on and off by bit 2 of the OSD control register (refer to Figure 8.11.3). Fig. 8.11.25 Example of Window Function OSD mode Window FG H IJ CC mode KLMNO CC mode PQRST CC mode OSD mode Bottom boundary of window Top boundary of window Screen A BCDE UVW XY

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 86 of 127 REJ03B0132-0100Z Fig. 8.11.26 Window Register 1 Fig. 8.11.27 Window Register 2 b7 b6 b5 b4 b3 b2 b1 b0 to R W Window Register 1 Window register 1 (WN1) [Address 00D616] B Name Functions After reset RW InderterminateWindow top boundary control bits (WN10 to WN17) Window top border position = T H ✕ (BC17 ✕ 162 + n) (n: setting value, TH : HSYNC cycle, BC17: bit 7 of block control register 1) Notes 1: Set values except “0016” to WN1 when BC17 is “0.” 2: Set values fit for the following condition: WN1 < WN2. b7 b6 b5 b4 b3 b2 b1 b0 to R W Window Register 2 Window register 2 (WN2) [Address 00D716] B Name Functions After reset RW InderterminateWindow bottom boundary control bits (WN20 to WN27) Window bottom border position = T H ✕ (BC27 ✕ 162 + n) (n: setting value, TH : HSYNC cycle, BC27: bit 7 of block control register 2) Note: Set values fit for the following condition: WN1 < WN2.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 87 of 127 REJ03B0132-0100Z

8.11.13 OSD Output Pin Control

The OSD output pins R, G, B and OUT1 can also function as ports P52–P55. Set corresponding bit of the OSD port control register (ad- dress 00CB16) to “0” to specify these pins as OSD output pins, or set it to “1” to specify it as a general-purpose port P5. The OUT2 can also function as port P1 0. Set bit 0 of the port P1 direction register (address 00C316) to “1” (output mode). After that, set bit 7 of the OSD port control register to “1” to specify the pin as OSD output pin, or set it to “0” to specify as port P1 The input polarity of the HSYNC , VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the I/O polarity con- trol register (address 00D8) . Set a bit to “0” to specify positive polar- ity; set it to “1” to specify negative polarity (refer to Figure 8.11.13). The structure of the OSD port control register is shown in Figure 8.11.28. Fig. 8.11.28 OSD Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD port control register (PF) [Address 00CB16] B Nam e Functions After resetR W OSD Port Control Register 2 0 30 : G signal output 1 : Port P53 output Fix these bits to 0. R R W R W R W 0, 1 Port P53 output signal selection bit (PF3) 4 0 : B signal output 1 : Port P54 output

0 R WPort P54 output signal

selection bit (PF4) 0R W 0 : R signal output 1 : Port P52 output Port P52 output signal selection bit (PF2) 5 0 : OUT1 signal output 1 : Port P53 output Port P55 output signal selection bit (PF5) 70 : Port P10 output 1 : OUT2 signal output Port P10 output signal selection bit (PF7) 0N othing is assigned. This bit is write disable bit. When this bit is read out, the value is 0.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 88 of 127 REJ03B0132-0100Z

8.11.14 Raster Coloring Function

An entire screen (raster) can be colored by setting the bits 4 to 0 of the raster color register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 8 raster colors can be obtained. When the character color/the character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2), specified for the character color/the character background color, takes priority of the raster color. This ensures that character color/character back- ground color is not mixed with the raster color. The raster color register is shown in Figure 8.11.29, the example of raster coloring is shown in Figure 8.11.30. Fig. 8.11.29 Raster Color Register b7 b6 b5b4 b3 b2b1 b0 Raster color register (RC) [Address 00D916] BN a m e Functions After resetR W Raster Color Register 0R aster color R control bit (RC0) 0 : No output 1 : Output

1 Raster color G

control bit (RC1) 0 : No output 1 : Output 2 0 : No output 1 : Output 4R aster color OUT2 control bit (RC4) Raster color B control bit (RC2) RW RW RW RW RW 3 0 : No output 1 : Output Raster color OUT1 control bit (RC3) 5, 6 0 : No output 1 : Output Fix these bits to “0.” 0R W 0R W Note: Either OSD clock source or 32 kHz oscillating clock is selected by bits 5 and 6 of the OSD control register. Port function selection bit (RC7) 0 : OSC1/XCIN, OSC2/X COUT 1 : P26, P27

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 89 of 127 REJ03B0132-0100Z Fig. 8.11.30 Example of Raster Coloring H S Y N C A 'A O U T 1 R G B : C h a r a c t e r c o l o r “ R E D ” ( R + O U T 1 + O U T 2 ) : B o r d e r c o l o r “ B L A C K ” ( O U T 1 + O U T 2 ) : B a c k g r o u n d c o l o r “ M A G E N T A ” ( R + B + O U T 1 + O U T 2 ) : R a s t e r c o l o r “ B L U E ” ( B + O U T 1 + O U T 2 ) S i g n a l s a c r o s s A A O U T 2

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 90 of 127 REJ03B0132-0100Z Fig.8.12.1 Sequence at Detecting Software Runaway Detection

8.12 SOFTWARE RUNAWAY DETECT FUNCTION

This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. ➀ The CPU generates an undefined instruction decoding signal. ➁ The device is internally reset because of occurrence of the unde- fined instruction decoding signal. ➂ As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be invalid. A D H , A D L01,S–201,S–1 P C H PC L PS A D HAD L PC ? U n d e f i n e d i n s t r u c t i o n d e c o d e U n d e f i n e d i n s t r u c t i o n d e c o d i n g s i g n a l o c c u r s I n t e r n a l r e s e t s i g n a l o c c u r s φ S Y N C A d d r e s s Data Re set sequence 01,S FFFE 16 FFFF 16 : Invalid P r o g r a m c o u n t e r S : S t a c k p o i n t e r P C AD L, ADH : J u m p d e s t i n a t i o n a d d r e s s o f r e s e t

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 91 of 127 REJ03B0132-0100Z 8.13. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 V ± 10 %, hold the RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 8.13.2, reset is released and the program starts form the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are An example of the reset circuit is shown in Figure 8.13.1. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. Fig.8.13.2 Reset Sequence Fig.8.13.1 Example of Reset Circuit Power source voltage 0 V Reset input voltage 0 V 4 . 5 V . 9 V P o w e r o n V c c RESET V s s M i c r o c o m p u t e r 3 0.1 µF M5 1953AL XIN φ RESET Internal RESET SYNC Address Data 3 2 7 6 8 c o u n t o f XI N c l o c k c y c l e S e e n o t e Re set address from the vector table ? ? 01, S 01, S-101, S-2 FFFE FFFF A D H , A D L Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 92 of 127 REJ03B0132-0100Z

8.14 CLOCK GENERATING CIRCUIT

This microcomputer has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external re- sistor is needed between X IN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT . When using XCIN-XCOUT as sub-clock, clear bits 5 and 6 of the OSD control register to “0.” To supply a clock signal externally, input it to the X IN (XCIN) pin and make the XOUT (XCOUT ) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock φ is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock φ to low-speed operation mode, set bit 7 of the CPU mode register to “1.”

8.14.1 OSCILLATION CONTROL

(1) Stop Mode The built-in clock generating circuit is shown in Figure 120. When the STP instruction is executed, the internal clock φ stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and “FF16” is set in timer 3 and “0716” is set in timer 4. Select f(XIN)/16 or f(XCIN)/ 16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to “0” before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction. The oscillator restarts when external interrupt is accepted. However, the internal clock φ keeps its HIGH level until timer 4 overflows, al- lowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. (2) Wait Mode When the WIT instruction is executed, the internal clock φ stops in the HIGH level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (See note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid.

• VSYNC interrupt
• OSD interrupt
• All timer interrupts using external clock input from port pin as count source
• All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source
• All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source
• f(XIN)/4096 interrupt
• Multi-master I2C-BUS interface interrupt
• Data slicer interrupt
• A-D conversion interrupt Fig.8.14.1 Ceramic Resonator Circuit Example Fig.8.14.2 External Clock Input Circuit Example (3) Low-speed Mode If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to “1.” When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the X CIN-XCOUT drivability can be reduced, allowing even lower power consumption. To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode regis- ter (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to “1” by software before executing. XC I N XIN C CIN Microcomputer XC O U T R f R d C COUT XOUT C IN C OUT XC I N M i c r o c o m p u t e r E x t e r n a l o s c i l l a t i o n c i r c u i t o r e x t e r n a l p u l s e XC O U T XI N XO U T Open Open E x t e r n a l o s c i l l a t i o n c i r c u i t Vcc Vss Vcc Vss

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 93 of 127 REJ03B0132-0100Z Fig.8.14.3 Clock Generating Circuit Block Diagram XC I N XC O U T O S C 1 c l o c k s e l e c t i o n b i t s S e e n o t e s I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t S e e n o t e s I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t S e e n o t e s M a i n c l o c k ( XI N – XO U T) s t o p b i t ( S e e n o t e s 1 , 3 ) R SQ STP instruction W I T i n s t r u c t i o n R S Q Reset Interrupt disable flag I Interrupt request R SQ Reset STP instruction T i m i n g φ I n t e r n a l c l o c k T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t S e e n o t e s “ 1 ” Time r 3 count stop bit (See notes 1, 2) T i m e r 4 c o u n t s t o p b i t S e e n o t e s T i m e r 3T i m e r 4 1/2 1 / 8 X O U TXI N 1 ” “0” 0 ” N o t e s 1 : T h e v a l u e a t r e s e t i s “ 0 . ” R e f e r t o t i m e r m o d e r e g i s t e r R e f e r t o t h e C P U m o d e r e g i s t e r R e f e r t o t h e O S D c o n t r o l r e g i s t e r

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 94 of 127 REJ03B0132-0100Z Fig.8.14.4 State Transitions of System Clock Reset The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The φindicates the internal clock. WIT instruction CM7 : Internal system clock selection bit 0 : XIN-XOUT selected (high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) CPU mode register (Address : 00FB16) CM6 : Main clock (XIN—XOUT ) stop bit 0 : Oscillating 1 : Stopped

8 MHz oscillating

φ is stopped ( H ) Timer operating f(φ) = 4 MHz

8 MHz stopped

φis stopped ( H ) φis stopped ( H ) Timer operating (See note 3) f(φ) = 16kHz φis stopped ( H ) φ= stopped ( H ) f(φ) = 16 kHz φis stopped ( H ) Timer operating (See note 3) Interrupt STP instruction Interrupt (See note 1) WIT instruction Interrupt WIT instruction Interrupt STP instruction Interrupt (See note 2) STP instruction Interrupt (See note 2) CM7 = 1 CM7 = 0 CM6 = 1 CM6 = 0 External INT, timer interrupt, or SI/O interrupt External INT Notes 1:When the STP state is ended, a delay of approximately 4 ms is automatically generated by timer 3 and timer 4. 2:The delay after the STP state ends is approximately 1s. 3:When the internal clock φdivided by 8 is used as the timer count source, the frequency of the count source is 2 kHz. The program must allow time for 8 MHz oscillation to stabilize High-speed operation start mode

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 95 of 127 REJ03B0132-0100Z RESET Vss Vcc Circuit example 1 RESET Vss Vcc Circuit example 2 Note :Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage.

8.15 DISPLAY OSCILLATION CIRCUIT

The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 6 of the OSD control register (address 00D0 16).

8.17 ADDRESSING MODE

The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 <Software> User’s Manual for details.

8.18 MACHINE INSTRUCTIONS

There are 71 machine instructions. Refer to SERIES 740 <Soft- ware> User’s Manual for details. 9. PROGRAMMING NOTES

• The divide ratio of the timer is 1/(n+1).
• Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions.
• After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed.
• An NOP instruction is needed immediately after the execution of a PLP instruction.
• In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1µF) directly between the V CC pin–VSS pin, AVCC pin–VSS pin, and the VCC pin–CNVSS pin, using a thick wire.
• M3727GM6/M8-XXXSP and M37272E8SP/FP are compatible, but please attention differences as follows: Fig.8.15.1 Display Oscillation Circuit

8.16 AUTO-CLEAR CIRCUIT

When a power source is supplied, the auto-clear function will oper- ate by connecting the following circuit to the RESET pin. Fig.8.16.1 Auto-clear Circuit Example OSC2OSC1 L C1 C2 Parameter Spec of1 4th pins M37272E8SP/FP AVcc M3727GM6/M8-XXXSP/FP NC (Non connection) OSD : OFF Data slicer : OFF OSD : ON Data slicer : ON Power souce voltage When System operate f(X IN) : 8MFz Normal 15 mA 30mA Max. 30 mA 45 mA Normal 10 mA 25 mA Max. 25 mA 40 mA ✽ Need to apply 5V±10%, because 14th pin of M37272E8SP/FP is AVcc pin. M3727GM6/M8-XXXSP/FP is the non connection pin, but it is not connect to the inside of IC. You can apply voltage.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 96 of 127 REJ03B0132-0100Z Symbol VCC , AVCC VI VI VO IOH IOL1 IOL2 IOL3 Pd Topr Tstg Symbol Parametear 10. ABSOLUTE MAXIMUM RATINGS 11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Ratings –0.3 to 6 –0.3 to 6 –0.3–VCC + 0.3 –0.3–VCC + 0.3 0 to 1 (See note 1) 0 to 2 (See note 2) 0 to 6 (See note 2) 0 to 10 (See note 3) 550 –10 to 70 –40 to 125 Parametear Power source voltageVCC , AVCC Input voltage CNVSS Input voltage P00–P07, P10–P17, P20–P27, P30, P31, P50, P51, XIN, RESET, CVIN Output voltage P00–P07, P10–P17, P20–P27, P30, P31, P52–P55, XOUT Circuit current P10–P17, P20–P27, P30, P31 P52–P55 Circuit current P00–P07, P10, P15–P17, P20–P23, P26, P27, P52–P55 Circuit current P11–P04 Circuit current P24, P25, P30, P31 Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS . Output transistors are cut off. Ta = 25 °C Min. 4.5

0.8 VCC

0.7 VCC

7.9 26.5 15.262 1.5 Typ. 5.0 8.0 27.0 15.734 2.0 Max. 5.5 VCC VCC

0.4 VCC

0.3 VCC

0.2 VCC

8.1 27.0 100 400 16.206 2.5 Limits V CC , AVCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 f(XIN) f(XCIN) fOSC fhs1 fhs2 fhs3 fhs4 VI Power source voltage (See note 4) Power source voltage HIGH Input voltage P00–P07, P10–P17, P20–P27, P30, P31, P50, P51, RESET, XIN HIGH Input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) LOW Input voltage P0 0–P07, P10–P17, P20–P27, P30, P31 LOW Input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) LOW Input voltage (See note 6) P50, P51, RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK HIGH average output current (See note1)P10–P17, P20–P27, P30, P31, P52–P55 LOW average output current (See note 2)P00–P07, P10, P15–P17, P20–P23, P26, P27, P52–P55 LOW average output current (See note 2)P11–P14 LOW average output current (See note 3)P24, P25, P30, P31 Oscillation frequency (for CPU operation) (See note 5) XIN Oscillation frequency (for sub-clock operation) XCIN Oscillation frequency (for OSD) OSC1 Input frequency TIM2, TIM3, INT1, INT2, INT3 Input frequency S CLK Input frequency SCL1, SCL2 Input frequency Horizontal sync. signal of video signal Input amplitude video signal CV IN V V V V V V V mA mA mA mA MHz kHz MHz kHz MHz kHz kHz V Unit V V V V mA mA mA mA mW Unit

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 97 of 127 REJ03B0132-0100Z Max. 200 100 0.4 3.0 0.4 0.6 1.3 VCC = 5.5V, f(XIN) = 8MHz (The upper row : M3727GM6/M8) (The lower row : M37272E8) VCC = 5.5V, f(XIN) = 0, f(XCIN) = 32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32 kHz, Low-power dissipation mode set V CC = 5.5V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V 12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Notes 1:The total current that flows out of the IC must be 20 mA or less. 2:The total input current to IC (IOL1 + IOL2 + IOL3 ) must be 30 mA or less. 3:The total average input current for ports P30, P31, P24 and P25 to IC must be 20 mA or less. 4:Connect 0.1 µF or more capacitor externally between the power source pins VCC –VSS (and AVCC –VSS ) so as to reduce power source noise. 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6:P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins. 7:Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports

• When the same limits: I/O port name.
• When the limits of functins except ports are different from I/O port limits: function pin name. HIGH output voltage P10–P17, P20–P27, P30, P31, P52–P55, LOW output voltage P00–P07, P10, P15–P17, P20–P23, P26, P27, P52–P55 LOW output voltage P24, P25, P30, P31 LOW output voltage P11–P14 Hysteresis (See note 6) RESET, P50, P51, INT1, INT2, INT3, TIM2, TIM3, SIN, SCLK , SCL1, SCL2, SDA1, SDA2 HIGH input leak current P00–P07, P10–P17, P20–P27, P30, P31, RESET, P50, P51, LOW input leak current P00–P07, P10–P17, P20–P27, P30, P31, P50, P51, RESET HIGH output leak current P00–P05 (Only M37272E8SP/FP version) I2C-BUS • BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) ICC Symbol Parametear Test conditions OSD OFF Data slicer OFF OSD ON Data slicer ON Stop mode W ait mode System operation Power source current VOH VOL VT+ –VT– IIZH IIZL IOZH R BS Test circuit Min. 2.4 Limits IOL = 3 mA IOL = 6 mA Typ. 0.5 Unit mA µA mA µA V V V µA µA µA 130 Ω 6 10 25 (15) (30) 25 40 (30) (45)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 98 of 127 REJ03B0132-0100Z Fig.12.1 Measure Circuits V s s V c c V VOH or VOL IO H o r IO L 4 . 5 V E a c h o u t p u t p i n A f t e r s e t t i n g e a c h o u t p u t p i n t o H I G H l e v e l w h e n m e a s u r i n g V O H a n d t o L O W l e v e l w h e n m e a s u r i n g VO e a c h p i n i s m e a s u r e d Vss Vcc 5 . 0 V Each input pin V s s V c c5 . 5 V Each input pin A IIZH or IIZL A V s s V c c XI N XOUT O S C 1 O S C 2 Icc 8 . 0 0 M H z P o w e r s o u r c e v o l t a g e P i n VC C i s m a d e t h e o p e r a t i o n s t a t e a n d i s m e a s u r e d t h e c u r r e n t w i t h a c e r a m i c r e s o n a t o r V s s V c c VB S 4 . 5 V S C L 1 o r S D A 1 IB S A R B S = VB IB S S C L 2 o r S D A 2 R B S V s s V c c5 . 5 V AE a c h o u t p u t p i n N o t e : O n l y M 3 7 2 7 2 E 8 S P / F P v e r s i o n . IOZ H 12 V A f t e r s e t t i n g e a c h o u t p u t p i n O F F s t a t e , e a c h p i n i s m e a s u r e d .

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 99 of 127 REJ03B0132-0100Z 13. A-D CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Resolution Non-linearity error Differencial non-linearity error Zero transition error Full-scale transition error Max. ±0.9 bits LSB LSB LSB LSB Min. Limits UnitTest conditionsParameterSymbol V VFST IOL (SUM) = 0 mA Typ. 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Max. 1000 300 Min. 1.3 0.6 1.3 20+0.1C b 0.6 20+0.1Cb 100 0.6 0.6 Max. 300 0.9 300 µs µs µs ns µs µs ns ns µs µs UnitStandard clock mode High-speed clock modeParameterSymbol Note: Cb = total capacitance of 1 bus line Fig.14.1 Definition Diagram of Timing on Multi-master I2C-BUS Min. 4.7 4.0 4.7 4.0 250 4.7 4.0 S D A SCL P tB U F S tHD ;STA tL O W tR tHD ;DAT tH IGH tF tSU ;DAT tSU ;STA Sr P tSU ;STOtHD ;STA S Sr P : Start condition : Restart condition : Stop condition

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 100 of 127 REJ03B0132-0100Z 15. PROM PROGRAMMING METHOD The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a general- purpose PROM programmer using a special programming adapter. The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 15.1 is recommended to verify programming. Fig. 15.1 Programming and Testing of One Time PROM Version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Name of Programming Adapter PCA7429G02 PCA7427 Product M37272E8SP M37272E8FP

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 101 of 127 REJ03B0132-0100Z 16. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion:

• Mask ROM Order Confirmation Form
• Mark Specification Form
• Data to be written to ROM, in EPROM form (28-pin DIP Type 27512, three identical copies) or FDK

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 102 of 127 REJ03B0132-0100Z 17. ONE TIME PROM VERSION M37272E8SP/FP MARKING M37272E8SP XXXXXXX XXXXXXX is lot number M37272E8FP XXXXXXX XXXXXXX is lot number

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 103 of 127 REJ03B0132-0100Z 18. APPENDIX Pin Configuration (TOP VIEW) P06/INT2/AD4 XOUT P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 HL F VHOLD CV IN CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC P17/AD3 M3727GM6/M8-XXXSP M37272E8SP (AVCC )NC( ) ...M37272E8SP Outline 42P4B Outline 42P2R-A/E (AVCC )NC P06/INT2/AD4 XOUT P50/HSYN C P51/VSYN C P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 HL F VHOLD CV IN CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC P17/AD3 M3727GM6/M8-XXXFP M37272E8FP ( ) ...M37272E8FP Note: Only 14th pin is NC pin of M3727GM6/ M8-XXXSP. This pin is AVcc pin of M37272E8SP. But NC pin of M3727GM6/M8-XXXSP is not connect to the inside of IC. You can apply to Vcc. Note: Only 14th pin is NC pin of M3727GM6/ M8-XXXFP. This pin is AVcc pin of M37272E8FP. But NC pin of M3727GM6/M8-XXXFP is not connect to the inside of IC. You can apply to Vcc.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 104 of 127 REJ03B0132-0100Z Memory Map 000016 00C0 16 00FF16 087F16 SFR1 area Not used FFFF 16 FFDE 16 FF0016 080016 Interrupt vector areaSpecial page OSD RAM (128 bytes) Zero page 020016 020F16 SFR2 area Not used 030016 00BF 16 010016 01FF16 05BF 16 Not used 3BFF 16 140016 800016 Not used ROM correction function Vector 1: address 030016 Vector 2: address 032016 032016 053F16 A00016 OSD ROM (10K bytes) M3727GM8- XXXSP/FP RAM (1024 bytes) M3727GM6- XXXSP/FP, M37272E8SP/FP RAM (1152 bytes) ■ M3727GM6/M8-XXXSP/FP, M37272E8SP/FP Note:Refer to Table 8.11.3 OSD RAM. M3727GM8- XXXSP/FP M37272E8SP/FP ROM (32K bytes) M3727GM6- XXXSP/FP ROM (24K bytes)

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 105 of 127 REJ03B0132-0100Z Memory Map of Special Function Register (SFR) S F R A r e a a d d r e s s e s C t o D D 01 D 11 D 21 D3 16 D 41 D5 16 D 61 D7 16 D 81 D 91 D A1 D B1 D C 1 D D 1 D E1 DF 16 C 01 C 11 C2 16 C 31 C4 16 C 51 C 61 C 71 C8 16 C 91 CB 16 CC 16 C D 1 C E1 CF 16 C A1 A d d r e s s Port P5 (P5) Caption data register 3 (CD3) C a p t i o n d a t a r e g i s t e r 4 ( C D 4 ) OSD c ontrol register (OC) P o r t P 1 ( P 1 ) P o r t P 1 d i r e c t i o n r e g i s t e r ( D 1 ) P o r t P 3 ( P 3 ) Port P3 direction register (D3) P o r t P 2 ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( D 2 ) R e g i s t e r P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( D 0 ) H o r i z o n t a l p o s i t i o n r e g i s t e r ( H P ) B l o c k c o n t r o l r e g i s t e r 1 ( B C 1 ) B l o c k c o n t r o l r e g i s t e r 2 ( B C 2 ) Vertical position register 1 (VP1) Vertical position register 2 (VP2) W i n d o w r e g i s t e r 1 ( W N 1 ) I n t e r r u p t i n p u t p o l a r i t y c o n t r o l r e g i s t e r ( R E ) b7 b0 B i t a l l o c a t i o nS t a t e i m m e d i a t e l y a f t e r r e s e t b7 b0 O S D p o r t c o n t r o l r e g i s t e r ( P F ) Window register 2 (WN2) I/O polarity control register (PC) R a s t e r c o l o r r e g i s t e r ( R C ) : “0” immediately after reset : Indeterminate imm ediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) B i t a l l o c a t i o n > F u n c t i o n b i t : No function bit : Fix this bit to “1” (do not write “0”) N ame : 0016 0016 0 01 ??000000 PF2PF3PF4PF5PF7 I N T 1I N T 2I N T 3 P 3 0P 3 1 P30DP31DP30CT3SC P 3 1 C 0 0 0016 OC4OC5 OC2 OC3 OC0 OC1OC6 B C 1 0B C 1 1B C 1 2B C 1 3B C 1 4B C 1 5B C 1 6B C 1 7 B C 2 0B C 2 1B C 2 2B C 2 3B C 2 4B C 2 5B C 2 6B C 2 7 V P 1 0V P 1 1V P 1 2V P 1 3VP14VP15VP16VP17 VP20VP21VP22VP23VP24VP25VP26VP27 W N 1 0W N 1 1WN12W N 1 3W N 1 4W N 1 5WN16WN17 W N 2 0W N 2 1WN22W N 2 3W N 2 4W N 2 5WN26WN27 RC0RC1RC2R C 7

00 R C 3R C 4

CD L20CD L21CD L22CD L23CD L24CD L25CD L26CD L27 CDH20CDH21C D H 2 2CDH23CDH24CDH25C D H 2 6C D H 2 7 H P 4H P 5 HP 2HP 3 H P 0H P 1H P 6 PC 4PC 5 PC 2PC 3 PC 0PC1P C 60 0016 0016 0016 0016 0016

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 106 of 127 REJ03B0132-0100Z F016 F 11 F216 F 31 F 41 F516 F 61 F716 F 81 F 91 FA 16 F B1 F C 1 FD 16 F E1 F F1 E016 E 11 E216 E 31 E 41 E516 E616 E716 E816 E 91 EB 16 E C 1 ED 16 E E1 E F1 E A1 Address Serial I/O register (SIO) A - D c o n t r o l r e g i s t e r 1 ( A D 1 ) T i m e r 5 ( T 5 ) Timer 6 (T6) T i m e r 1 ( T 1 ) C a p t i o n d a t a r e g i s t e r 1 ( C D 1 ) C a p t i o n p o s i t i o n r e g i s t e r ( C P S ) D a t a s l i c e r t e s t r e g i s t e r 2 C l o c k r u n - i n d e t e c t r e g i s t e r ( C R D ) Data clock position register (DPS) Register D a t a s l i c e r c o n t r o l r e g i s t e r 1 ( D S C 1 ) D a t a s l i c e r c o n t r o l r e g i s t e r 2 ( D S C 2 ) T i m e r 2 ( T 2 ) Timer 3 (T3) T i m e r 4 ( T 4 ) T i m e r m o d e r e g i s t e r 1 ( T M 1 ) T i m e r m o d e r e g i s t e r 2 ( T M 2 ) I 2C data shift register (S0) I2C c o n t r o l r e g i s t e r S D I2C c l o c k c o n t r o l r e g i s t e r S I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) Interrupt control register 1 (ICON1) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) Data slicer test register 1 S y n c h r o n o u s s i g n a l c o u n t e r r e g i s t e r ( H C ) A-D control register 2 (AD2) C P U m o d e r e g i s t e r ( C P U M ) b 7b 0 Bit allocation St ate immediately after reset b7 b 0 S F R A r e a a d d r e s s e s E t o F Caption data register 2 (CD2) Serial I/O mode register (SM) I2C status register (S1) I2C a d d r e s s r e g i s t e r S D : “ 0 ” i m m e d i a t e l y a f t e r r e s e t I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t <State immediately after reset> “ 1 ” i m m e d i a t e l y a f t e r r e s e t : Fix this bit to “0” (do not write “1”) <Bit allocation> F u n c t i o n b i t N o f u n c t i o n b i t : Fix this bit to “1” (do not write “0”) N a m e : TM20T M 2 1TM22TM23TM24 TM10T M 1 1TM12TM13TM14 CM2 TM1RTM2RTM3RTM4ROSDRVSCRIN3R CK0 IN1RDSRS 1 R TM1ET M 2 ET M 3 ETM4EO S D EV S C E IN1EDSES EI N E T M 2 5 0016 F F1 0716 FF16 0716 T M 1 5TM16T M 1 7 TM26T M 2 7 S A D 0S A D 1SAD2S A D 3SAD4S A D 5S A D 6R B W LRBAD0A A SA LPINBBT R XM S T BC0BC1BC2ESOALSBSEL0B S E L 1 CCR0CCR1CCR2CCR3CCR4ACK 0 01 0016 CK RI N 2 RIICRTM56R I N E CKEIICETM56ETM56C 00CM7 C M 5CM6 SM0SM1S M 2SM3 AD C 10AD C 11AD C 12AD C 14 A D C 2 0A D C 2 1A D C 2 2A D C 2 5 SM5S M 6 AD C 24A D C 23 1 0 B I T S A D FAST MODE 0 01 0016 F F DSC10DSC11DSC12 DSC20D SC 23D SC 24D S C 2 5 CRD3CRD4CRD5C R D 6C R D 7 DPS3DPS4DPS5DPS6DPS7 CPS0CPS3CPS4C P S 5C P S 1C P S 2CPS6C P S 7 HC0HC3H C 4H C 5H C 1H C 2 000? 0 1100 1 00 0000 0 01 C D H 1 0C D H 1 3C D H 1 4CDH15 C D H 1 1CDH12C D H 1 6C D H 1 7 C D L 1 0CD L13CD L14C D L 1 5C D L 1 1CD L12C D L 1 6C D L 1 7 0016 0 01 0016 0016 0016 0016 D 1D2D 4D5D 6D7 D 0 0000?00 0 00 0 01 0 0? A C K B I T 0 91 C

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 107 of 127 REJ03B0132-0100Z 2 0 01 20116 20216 20316 2 0 41 2 0 51 2 0 61 2 0 71 2 0 81 2 0 91 2 0 B1 2 0 C 1 20D 16 20E16 20F16 2 0 A1 A d d r e s s P W M m o d e r e g i s t e r 2 ( P M 2 ) ROM correction address 1 (low-order) ROM correction enable register (RCR) PWM2 register (PWM2) P W M 4 r e g i s t e r ( P W M 4 ) P W M 5 r e g i s t e r ( P W M 5 ) Register P W M 0 r e g i s t e r ( P W M 0 ) PWM1 register (PWM1) P W M m o d e r e g i s t e r 1 ( P M 1 ) R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) b 7b 0 Bit allocation t a t e i m m e d i a t e l y a f t e r r e s e t b7 0 S F R A r e a a d d r e s s e s 016 t o F16) PWM3 register (PWM3) R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) ROM correction address 2 (low-order) 0 i m m e d i a t e l y a f t e r r e s e t : Indeterminate immediately after reset S t a t e i m m e d i a t e l y a f t e r r e s e t > 1 i m m e d i a t e l y a f t e r r e s e t : Fix this bit to 0 (do not write 1 ) < B i t a l l o c a t i o n > F u n c t i o n b i t : No function bit : Fix this bit to 1 (do not write 0 ) N a m e : 0016 0 01 PM13 ? ?? 0PM10 P M 2 5 M 2 4 M 2 3 M 2 0 0016 0016 0016 0016 0016 0016 RCR1 RCR0

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 108 of 127 REJ03B0132-0100Z Internal State of Processor Status Register and Program Counter at Reset b 7 b 0 b7 b0 R e g i s t e r P r o c e s s o r s t a t u s r e g i s t e r ( P S ) Bit allocation S t a t e i m m e d i a t e l y a f t e r r e s e t P r o g r a m c o u n t e r ( P C H ) P r o g r a m c o u n t e r ( P C C o n t e n t s o f a d d r e s s F F F F1 C o n t e n t s o f a d d r e s s F F F E1 : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o <B i t a l l o c a t i o n> <State immediately after reset> F u n c t i o n b i t : N o f u n c t i o n b i t F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “0” immediately after reset I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “1” immediately after reset

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 109 of 127 REJ03B0132-0100Z Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: V a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e B i t a t t r i b u t e s ( N o t e 1 ) ( N o t e 2 )B i t p o s i t i o n 2 : B i t a t t r i b u t e s • • • • • • T h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e I n t h e f i g u r e t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : Bit in which nothing is assigned N o t e s 1 : V a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e a f t e r r e s e t r e l e a s e a f t e r r e s e t r e l e a s e I n d e t e r m i n a t e I n d e t e r m i n a t e a f t e r r e s e t r e l e a s e R cannot be set. W b 7b6 b 5b 4b 3 b 2b 1b 0 B A f t e r r e RW C P U M o d e R e g i s t e r 0 , 1 3, 4 N a m eF u n c t i o n s Processor mode bits (CM0, CM1) 0 0 : S i n g l e - c h i p m o d e N o t a v a i l a b l e Fix these bits to “1.” 1Stack page selection bit (See note) (CM2) b 1 b 0 0: 0 page 1: 1 page 5 1Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is “1.” 6, 7 0Clock switch bits (CM6, CM7) 0 0 : f ( X I N ) = 8 M H z f XI N ) M H z f XI N ) M H z D o n o t s e t b 7 b 6 C P U m o d e r e g i s t e r ( C P U M ) ( C M ) [ A d d r e s s 0 0 F B1 R W RW RW R W RW < E x a m p l e >

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 110 of 127 REJ03B0132-0100Z Address 00C116, 00C316, 00C516 Address 00C716 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 Port Pi direction register (PiD) (i=0,1,2) [Addresses 00C 116, 00C 316, 00C 516] B N ame F u n c t i o n s A f t e r r e s e tR W P o r t P i D i r e c t i o n R e g i s t e r 00 : Port Pi0 input mode 1 : Port Pi0 output mode 1 0 : Port Pi1 input mode 1 : Port Pi1 output mode 2 0 : Port Pi2 input mode 1 : Port Pi2 output mode 30 : Port Pi3 input mode 1 : Port Pi3 output mode 40 : Port Pi4 input mode 1 : Port Pi4 output mode 5 0 : Port Pi5 input mode 1 : Port Pi5 output mode 60 : Port Pi6 input mode 1 : Port Pi6 output mode 70 : Port Pi7 input mode 1 : Port Pi7 output mode P o r t P i d i r e c t i o n r e g i s t e r R W R W R W R W R W R W R W R W b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (P3D) [Address 00C716] BN ame Functions After resetRW Port P3 Direction Register 00 : Port P30 input mode 1 : Port P30 output mode 1 0 : Port P31 input mode 1 : Port P31 output mode 20 : CMOS output 1 : N-channel open-drain output Port P3 direction register Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are 0. RW RW RW R4, 5, Port P30 output structure selection bit (P30C) 3 0 : CMOS output 1 : N-channel open-drain output 0R WPort P31 output structure selection bit (P30C) 6 Refer to Timer section.Timer 3 count source selection bit (T3SC) 0R W

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 111 of 127 REJ03B0132-0100Z b7 b6 b5 b4 b3 b2 b1 b0 OSD port control register (PF) [Address 00CB16] BN a m e Functions After resetR W OSD Port Control Register 2 0 30 : G signal output 1 : Port P53 output Fix these bits to 0. R R W R W R W 0, 1 Port P53 output signal selection bit (PF3) 4 0 : B signal output 1 : Port P54 output selection bit (PF4) 0R W 0 : R signal output 1 : Port P52 output Port P52 output signal selection bit (PF2) 5 0 : OUT1 signal output 1 : Port P53 output Port P55 output signal selection bit (PF5) 70 : Port P10 output 1 : OUT2 signal output Port P10 output signal selection bit (PF7) 0N othing is assigned. This bit is write disable bit. When this bit is read out, the value is 0. Address 00CB 16 Address 00D016 b7 b6 b5b4 b3 b2b1 b0 OSD control register (OC) [Address 00D016] B Name Functions After resetR W OSD Control Register 0O SD control bit (OC0) (See note) 0 : All-blocks display off 1 : All-blocks display on control bit (OC1) 0 : OFF 1 : ON 2 0 : OFF 1 : ON 4O SD mode clock selection bit (OC4) Window control bit (OC2) RW RW RW RW RW 3 0 : Data slicer clock 1 : Clock from OSC1 pin CC mode clock selection bit (OC3) 5, 6OSC1 clock selection bit (OC5, OC6) 0 0: 32 kHz oscillating 0 1: Do not set. 1 0: LC oscillating, Ceramic oscillating 1 1: Do not set. b6 b5 0 : Data slicer clock 1 : Clock from OSC1 pin 7 Fix this bit to 0. 0R W 0R W Note: Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC .

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 112 of 127 REJ03B0132-0100Z b7 b6 b5b4 b3 b2b1 b0 Block control register i (BCi) (i=1, 2) [Addresses 00D216 and 00D316] Block Control register i 0, 1 Display mode selection bits (BCi0, BCi1) (See note 1) Indeterminate 2, 3 Dot size selection bits (BCi2, BCi3) b4 b3 b2 Pre-divide RatioDot Size selection bit (BCi4)

7 Window top/bottom

(BCi7) Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.” Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.” 2: Tc is OSD clock cycle divided in pre-divide circuit. 3: H is HSYNC . OUT1/OUT2 output control bit (BCi5) (See note 1) 0: OUT1 output control 1: OUT2 output control (BCi6) BC16: Block 1 BC26: Block 1 b1 b0 0 0: Display OFF 0 1: CC mode 1 0: OSD mode (Border OFF) 1 1: OSD mode (Border ON) ✕ 2 ✕ 3 1Tc ✕ 1/2H 1Tc ✕ 1H 2Tc ✕ 2H 3Tc ✕ 3H 1Tc ✕ 1/2H 1Tc ✕ 1H 2Tc ✕ 2H 3Tc ✕ 3H BC17: Window top boundary BC27: Window bottom boundary B Name Functions After resetRW RW IndeterminateRW IndeterminateRW IndeterminateRW IndeterminateRW IndeterminateRW Address 00D116 Address 00D216, 00D316 b7 b6 b5b4 b3 b2b1 b0 Horizontal position register (HP) [Address 00D116] BN a m e Horizontal Position Register Horizontal display start position control bits (HP0 to HP6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Functions After reset R W Horizontal display start positions 128 steps (0016 to 7F16) (1 step is 4TOSC ) RW to Note: The setting value synchronizes with the V SYNC .

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 113 of 127 REJ03B0132-0100Z Address 00D416, 00D516 Address 00D616 Address 00D716 b7 b6 b5 b4 b3 b2 b1 b0 to R W Vertical Position Register i Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516] B Name Functions After reset RW InderterminateVertical display start position control bits (VPi0 to VPi7) (See note) Vertical display start position = T H ✕ (BCi6 ✕ 162 + n) (n: setting value, TH : HSYNC cycle, BCi6: bit 6 of block control register i) Note: Set values except “0016” to VPi when BCi6 is “0.” b7 b6 b5 b4 b3 b2 b1 b0 to R W Window Register 1 Window register 1 (WN1) [Address 00D616] B Name Functions After reset RW InderterminateWindow top boundary control bits (WN10 to WN17) Window top border position = T H ✕ (BC17 ✕ 162 + n) (n: setting value, TH : HSYNC cycle, BC17: bit 7 of block control register 1) Notes 1: Set values except “0016” to WN1 when BC17 is “0.” 2: Set values fit for the following condition: WN1 < WN2. b7 b6 b5 b4 b3 b2 b1 b0 to R W Window Register 2 Window register 2 (WN2) [Address 00D716] B Name Functions After reset RW InderterminateWindow bottom boundary control bits (WN20 to WN27) Window bottom border position = T H ✕ (BC27 ✕ 162 + n) (n: setting value, TH : HSYNC cycle, BC27: bit 7 of block control register 2) Note: Set values fit for the following condition: WN1 < WN2.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 114 of 127 REJ03B0132-0100Z 0 : “ ” at even field “ ” at odd field 1 : “ ” at even field “ ” at odd field b7 b6 b5 b4 b3 b2 b1 b0 I/O polarity control register (PC) [Address 00D816] B Name Functions After resetR W I/O Polarity Control Register 0H SYNC input polarity switch bit (PC0) 0 : Positive polarity input 1 : Negative polarity input 1 0 : Positive polarity input 1 : Negative polarity input 2R , G, B output polarity switch bit (PC2) 0 : Positive polarity output 1 : Negative polarity output 3O UT1 output polarity switch bit (PC3) 0 : Positive polarity output 1 : Negative polarity output 4O UT2 output polarity switch bit (PC4) 0 : Positive polarity output 1 : Negative polarity output 5D isplay dot line selection bit (PC5) (See note)

6 Field determination flag

(PC6) 0 : Even field 1 : Odd field 7 0 VSYNC input polarity switch bit (PC1) RW RW RW RW RW RW RWFix this bit to “0.” Note: Refer to the corresponding figure (8.11.14). Address 00D916 Address 00D816 b7 b6 b5b4 b3 b2b1 b0 Raster color register (RC) [Address 00D916] B Name Functions After resetR W Raster Color Register

0 Raster color R

control bit (RC0) 0 : No output 1 : Output control bit (RC1) 0 : No output 1 : Output 2 0 : No output 1 : Output

4 Raster color OUT2

control bit (RC4) Raster color B control bit (RC2) RW RW RW RW RW 3 0 : No output 1 : Output Raster color OUT1 control bit (RC3) 5, 6 0 : No output 1 : Output Fix these bits to “0.” 0R W 0R W Note: Either OSD clock source or 32 kHz oscillating clock is selected by bits 5 and 6 of the OSD control register. Port function selection bit (RC7) 0 : OSC1/XCIN, OSC2/X COUT 1 : P26, P27

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 115 of 127 REJ03B0132-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (RE) [Address 00DC16] B Name Functions After reset R W Interrupt Input Polarity Register INT1 polarity switch bit (INT1) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity to INT2 polarity switch bit (INT2) INT3 polarity switch bit (INT3) Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 RW RW RW 0 : Positive polarity 1 : Negative polarity b 7b 6b 5b 4b 3b 2b 1b 0 D a t a s l i c e r c o n t r o l r e g i s t e r 1 ( D S C 1 ) [ A d d r e s s 0 0 E 01 D a t a S l i c e r C o n t r o l R e g i s t e r 1 00 RW 0R W 2R e f e r e n c e c l o c k s o u r c e s e l e c t i o n b i t D S C 0: Video signal 1: HSYNC signal 0R W 0R W 0 RW 0: Stopped 1: Operating D a t a s l i c e r a n d t i m i n g s i g n a l g e n e r a t i n g c i r c u i t c o n t r o l b i t D S C F i x t h e s e b i t s t o “ 0 . ”3, 4 00 0 10 : F 2 1: F1 S e l e c t i o n b i t o f d a t a s l i c e r e f e r e n c e v o l t a g e g e n e r a t i n g f i e l d D S C F i x t h e s e b i t s t o “ 1 . ”5, 6 D e f i n i t i o n o f f i e l d s 1 ( F 1 ) a n d 2 ( F 2 ) H sep Vsep F1: H sep Vsep F2: B A f t e r r e s e t R WN a m eF unctions 0R WF i x t h i s b i t t o “ 0 . ”7 Address 00DC 16 Address 00E016

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 116 of 127 REJ03B0132-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00E416] R W Clock Run-in Detect Register to 0R —Test bits to Number of reference clocks to be counted in one clock run-in pulse period. Clock run-in detection bit (CRD3 to CRD7) 0R — Read-only B After resetFunctionsName b 7 b 6 b 5 b 4 b 3 b2 b1 b0 D a t a s l i c e r c o n t r o l r e g i s t e r 2 ( D S C 2 ) [ A d d r e s s 0 0 E 11 R W D ata Slicer C ontrol R egister 2 I n d e t e r m i n a t e R — I n d e t e r m i n a t e R — 0: D ata is not latched yet and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. C a p t i o n d a t a l a t c h c o m p l e t i o n f l a g D S C F i x t h i s b i t t o “ 1 . ”

2 R ead-onlyT e s t b i t

30 : F2 1: F1 F i e l d d e t e r m i n a t i o n f l a g D S C 40 : M ethod (1) 1: Method (2) V e r t i c a l s y n c h r o n o u s s i g n a l V s e g e n e r a t i n g m e t h o d s e l e c t i o n b i t D S C 50 : M atch 1: Mismatch V-pulse shape determination flag (DSC25) Indeterminate R — 6 0 R WF i x t h i s b i t t o “ o . ” B A f t e r r e s e tF u n c t i o n sN am e D efinition of fields 1 (F1) and 2 (F2) H sep Vsep F1: H sep Vsep F2: R —7 R ead-onlyTest bit Indeterminate Address 00E416 Address 00E116

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 117 of 127 REJ03B0132-0100Z b 7 b6 b 5 b4 b 3 b 2 b 1 b 0 D ata clock position register (DPS) [Address 00E516] D a t a C l o c k P o s i t i o n R e g i s t e r 01 R WFix this bit to “0.” 1 Fix this bit to “1.” 0 R W 100 B A f t e r r e s e tF u n c t i o n sN a m e R W bits (DPS3 to DPS7) 2 Fix this bit to “0.” 0 R W b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616] Caption Position Register to bits(CPS0 to CPS4) 6, 7 Refer to the corresponding Table (Table 8.10.1). Slice line mode specification bits (in 1 field) (CPS6, CPS7) 5 0: Data is not latched yet and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Caption data latch completion flag 2 (CPS5) IndeterminateR B After resetFunctionsNam e R W Address 00E516 Address 00E616 Address 00E916 b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E916] R W Sync Pulse Counter Register to 6, 7 0 R Count value (HC0 to HC4) 5 0R WCount source (HC5) 0: H SYNC signal 1: Composite sync signal B After resetFunctionsName Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are 0.

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 118 of 127 REJ03B0132-0100Z b 7b 6 b 5b 4b 3 b 2b 1b 0 S e r i a l I / O m o d e r e g i s t e r ( S M ) [ A d d r e s s 0 0 E B1 BN a m eF u n c t i o n s A f t e r r e s e t RW S e r i a l I O M o d e R e g i s t e r 0 , 1 I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s S M S M b 1 b 0 f XI N ) o r f XC I N ) f XI N ) o r f XC I N ) f XI N ) o r f XC I N ) f XI N ) o r f XC I N )

2 S y n c h r o n o u s c l o c k

s e l e c t i o n b i t S M

3 P o r t f u n c t i o n

s e l e c t i o n b i t S M

5 T r a n s f e r d i r e c t i o n

s e l e c t i o n b i t S M 0 : P 20, P 21 SC L SO U T 0 : E x t e r n a l c l o c k I n t e r n a l c l o c k 0 : L S B f i r s t M S B f i r s t F i x t h i s b i t t o “ 0 . ” T r a n s f e r c l o c k i n p u t p i n s e l e c t i o n b i t S M 0 : I n p u t s i g n a l f r o m SI N p i n I n p u t s i g n a l f r o m SO U T p i n RW RW RW R W RW RW 7 F i x t h i s b i t t o “ 0 . ” 0R W b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EC16] B After resetRW A-D Control Register 1 to Analog input pin selection bits (ADC10 to ADC12) Name Functions b2 b1 b0 0 0 0 : AD1 0 0 1 : AD2 0 1 0 : AD3 0 1 1 : AD4 1 0 0 : AD5 1 0 1 : AD6 1 1 0 : 1 1 1 : result (ADC14) 0: Input voltage < reference voltage 1: Input voltage > reference voltage Indeterminate Do not set. 3 This bit is a write disable bit. When this bit is read out, the value is “0.” RW RW R — to Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are “0.” R — Address 00EC16 Address 00EB16

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 119 of 127 REJ03B0132-0100Z b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00ED16] B After reset RW A-D Control Register 2 to 6, 7 Name Functions D-A converter set bits (ADC20 to ADC25) b0b1b2 b3 b4 b5 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” 000000 00000 0000 111 11111 111111 : 3/128Vcc : 5/128Vcc : 123/128Vcc : 125/128Vcc : 127/128Vcc : 1/128Vcc RW b7b6 b5b4b3 b2b1b0 Timer mode register 1 (TM1) [Address 00F416] B After reset W Timer Mode Register 1 Name Functions Timer 1 count source selection bit 1 (TM10) 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Count source selected by bit 5 of TM1 Timer 2 count source selection bit 1 (TM11) 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin Timer 1 count stop bit (TM12) 0: Count start 1: Count stop Timer 2 count stop bit (TM13) 0: Count start 1: Count stop Timer 2 count source selection bit 2 (TM14) R WR WR WR WR WR0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 1 overflow selection bit 2 (TM15) 0: f(XIN)/4096 or f(XCIN)/4096 (See note) 1: External clock from TIM2 pin 0W R selection bit 2 (TM16) 0: Timer 2 overflow 1: Timer 4 overflow 0W R

7 Timer 6 internal count

(TM17) 0W R0: f(X IN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Address 00ED16 Address 00F416

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 120 of 127 REJ03B0132-0100Z b7b6 b5b4b3 b2b1b0 Timer mode register 2 (TM2) [Address 00F516] B After resetRW Timer Mode Register 2 Name Functions Timer 3 count source selection bit (TM20) 0 RW 1, 4Timer 4 count source selection bits (TM21, TM24) 0R W Timer 3 count stop bit (TM22) 0: Count start 1: Count stop Timer 4 count stop bit (TM23) 0: Count start 1: Count stop (TM25) 0: Count start 1: Count stop (TM26) 0: Count start 1: Count stop RW RW RW RW RW7 Timer 5 count source selection bit 1 (TM27) 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Count source selected by bit 6 of TM1 00 : f(XIN)/16 or f(XCIN)/16 (See note) 01 : f(XCIN) 10 : 11 : (b6 at address 00C716) External clock from TIM3 pin b4 b1 00 : Timer 3 overflow signal 01 : f(XIN)/16 or f(XCIN)/16 (See note) 10 : f(XIN)/2 or f(XCIN)/2 (See note) 11 : f(XCIN) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Address 00F516 Address 00F616 b7 b 6 b 5 b 4 b 3 b 2 b 1 b0 I C d a t a s h i f t r e g i s t e r 1 ( S 0 ) [ A d d r e s s 0 0 F 61 B F u n c t i o n s After reset R W I C D a t a S h i f t R e g i s t e r t o T h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a I n d e t e r m i n a t e N ote: 2T o w r i t e d a t a i n t o t h e I C d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e M S T b i t t o s l a v e m o d e k e e p a n i n t e r v a l o f m a c h i n e c y c l e s o r m o r e N a m e D 0 t o D 7 R W

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 121 of 127 REJ03B0132-0100Z b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0

0 R e a d / w r i t e b i t

R B W t o S l a v e a d d r e s s S A D t o S A D < O n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > T h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r S T A R T c o n d i t i o n r e a d s t a t e W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r R E S T A R T c o n d i t i o n w r i t e s t a t e <In both mo des> The address data is compared. I2C A d d r e s s R e g i s t e r I2C a d d r e s s r e g i s t e r S D A d d r e s s F B Nam e F u n c t i o n s A f t e r r e s e tR W R W b 7 b 6 b 5 b 4 b3 b2 b1 b 0 I2C s t a t u s r e g i s t e r S A d d r e s s F I2C S t a t u s R e g i s t e r 6 , 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode B N a m e F u n c t i o n s After resetR W C o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s T R X M S T 0 : Bus free 1 : Bus busy B u s b u s y f l a g ( B B ) 0 : Interrupt request issued 1 : No interrupt request issued I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t P I N 0 : N ot detected 1 : Detected A r b i t r a t i o n l o s t d e t e c t i n g f l a g A L S e e n o t e 0 : Address mismatch 1 : Address match S l a v e a d d r e s s c o m p a r i s o n f l a g A A S S e e n o t e 0 : N o general call detected 1 : General call detected G e n e r a l c a l l d e t e c t i n g f l a g A D S e e n o t e 0 : Last bit = “0 ” 1 : Last bit = “1 ” L a s t r e c e i v e b i t ( L R B ) S e e n o t e N o t e : T h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . Indeterm inate R— RW R W ( S e e n o t e ) ( S e e n o t e ) ( S e e n o t e ) ( S e e n o t e ) Address 00F716 Address 00F816

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 122 of 127 REJ03B0132-0100Z b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t o B i t c o u n t e r N u m b e r o f t r a n s m i t r e c i e v e b i t s B C t o B C b 2 b 1 b 0

3 I2C

B U S i n t e r f a c e u s e e n a b l e b i t E S O 0 : D i s a b l e d E n a b l e d

4 D a t a f o r m a t s e l e c t i o n

b i t A L S 0 : A d d r e s s i n g m o d e F r e e d a t a f o r m a t b i t B I T S A D 0 : 7 - b i t a d d r e s s i n g f o r m a t b i t a d d r e s s i n g f o r m a t 6 , 7 C o n n e c t i o n c o n t r o l b i t s b e t w e e n I C B U S i n t e r f a c e a n d p o r t s b 7 b 6 C o n n e c t i o n p o r t ( S e e n o t e ) N o n e S C L S D A S C L S D A S C L S D A S C L S D A I2C c o n t r o l r e g i s t e r S D a d d r e s s F I2C C o n t r o l R e g i s t e r B N a m e F u n c t i o n s A f t e r r e s e t R W N o t e : W h e n u s i n g p o r t s P 11- P 14 a s I C - B U S i n t e r f a c e , t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m C M O S o u t p u t t o N c h a n n e l o p e n d r a i n o u t p u t R W R W R W R W R W b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2 : address 00FA16) I2C Clock Control Register to SCL frequency control bits (CCR0 to CCR4) SCL mode specification bit (FAST MODE) 0: Standard clock mode 1: High-speed clock mode 0Standard clock mode BN ame Functions After resetRW ACK bit (ACK BIT) ACK clock bit (ACK) 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock High speed clock mode Setup disabled Setup disabled00 to 02 Setup disabled 33303 Setup disabled 25004 100 400 (See note)05 83.3 16606 500/CCR value 1000/CCR value ... 17.2 34.51D 16.6 33.31E 16.1 32.31F (at φ = 4 MHz, unit : kHz) Note: At 4000kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Setup value of CCR4– CCR0 RW RW RW RW Address 00F916 Address 00FA16

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 123 of 127 REJ03B0132-0100Z b 7b 6 b 5b4b 3 b 2b 1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 0 0 F C 1 BN a m e F u n c t i o n s After reset RW Interrupt Request Register 1 0 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d T i m e r 1 i n t e r r u p t r e q u e s t b i t T M R 1T i m e r 2 i n t e r r u p t r e q u e s t b i t T M R 2T i m e r 3 i n t e r r u p t r e q u e s t b i t T M R r e q u e s t b i t T M R 4O S D i n t e r r u p t r e q u e s t b i t O S D R 5V S Y N C i n t e r r u p t r e q u e s t b i t V S C R r e q u e s t b i t V S C R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t R R R R R R R RN o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s b 7b6 b 5b 4b 3 b 2b 1b 0 B A f t e r r e s e t RW C P U M o d e R e g i s t e r 0 , 1 3, 4 Name F u n c t i o n s Processor mode bits (CM0, CM1) 0 0: Single-chip mode 0 1: 1 0: Not available 1 1: Fix these bits to “1.” 1Stack page selection bit (CM2) (See note) b1 b0 0 : 0 p a g e p a g e 1 00 5 1 6 0Main Clock (XIN–XOUT ) stop bit (CM6) C P U m o d e r e g i s t e r ( C M ) [ A d d r e s s 0 0 F B1 R W RW R W R W RW XCOUT drivability selection bit (CM5) 0 : L O W d r i v e H I G H d r i v e 0 : O s c i l l a t i n g S t o p p e d 7 0Internal system clock selection bit (CM7) RW0 : X I N – XO U T s e l e c t e d h i g h s p e e d m o d e XC I N – XC O U T s e l e c t e d h i g h s p e e d m o d e Note: This bit is set to “1” after the reset release. Address 00FB16 Address 00FC16

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 124 of 127 REJ03B0132-0100Z b 7b 6b 5b 4b 3 b 2b 1b 0 Interrupt request register 2 (IREQ2) [Address 00FD BN a m eF u n c t i o n s A f t e r r e s e t RW I n t e r r u p t R e q u e s t R e g i s t e r r e q u e s t b i t I N I R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d r e q u e s t b i t D S R request bit (S1R) request bit (IN2R) 7F i x this bit to “0.” 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 16] R R R R ✽ R R ✽ R W f(XIN)/4096 interrupt request bit (CKR) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d Multi-master I2C-BUS interrupt request bit (IICR) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d request bit (TM56R) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d b 7b 6 b 5b 4b 3 b 2b1b 0 I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 0 0 F E1 BN a m eF u n c t i o n s After reset RW I n t e r r u p t C o n t r o l R e g i s t e r 1 e n a b l e b i t T M E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d e n a b l e b i t T M E e n a b l e b i t T M E O S D E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d RW RW RW RW RW 7 N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s T i m e r 4 i n t e r r u p t e n a b l e b i t T M E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 5 VS Y N C i n t e r r u p t e n a b l e b i t V S C E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 0R W e n a b l e b i t I N E 0 : I n t e r r u p t d i s a b l e d I n t e r r u p t e n a b l e d 0R W Address 00FD16 Address 00FE16

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 125 of 127 REJ03B0132-0100Z b 7b 6 b 5b 4b 3 b 2b1b 0 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 0 0 F F1 BN a m e F u n c t i o n s After reset RW I n t e r r u p t C o n t r o l R e g i s t e r

0 INT1 external interrupt

enable bit (IN1E) 0 : Interrupt disabled 1 : Interrupt enabled

1 Data slicer interrupt

enable bit (DSE) enable bit (S1E) enable bit (IN2E) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW RW RW f(X IN)/4096 interrupt enable bit (CKE) 0 : Interrupt disabled 1 : Interrupt enabled

5 Multi-master I2C-BUS

interface interrupt enable bit (IICE) 0 : Interrupt disabled 1 : Interrupt enabled 0R W enable bit (TM56E) 0 : Interrupt disabled 1 : Interrupt enabled 0R W

7 Timer 5 • 6 interrupt

switch bit (TM56C) 0 : Timer 5 1 : Timer 6 0R Wb7b6 b5b4b3 b2b1b0 PWM mode register 1 (PM1) [Address 020816] B After resetR W PWM Mode Register 1 1, 2 Name Functions PWM output polarity selection bit (PM13) Indeterminate Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 : Positive polarity 1 : Negative polarity R W R — RW PWM counts source selection bit (PM10) 0 : Count source supply 1 : Count source stop to IndeterminateNothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R — Address 00FF16 Address 020816

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 126 of 127 REJ03B0132-0100Z b7b6 b5b4b3 b2b1b0 PWM mode register 2 (PM2) [Address 020916] B After resetRW PWM Mode Register 2 Name Functions P00/PWM0 output selection bit (PM20) 0 : P00 output 1 : PWM0 output P02/PWM2 output selection bit (PM22) 0 : P02 output 1 : PWM2 output P03/PWM3 output selection bit (PM23) 0 : P03 output 1 : PWM3 output P04/PWM4 output selection bit (PM24) 0 : P04 output 1 : PWM4 output selection bit (PW25) 0: P05 output 1: PWM5 output 6, 7Fix these bits to “0.” P01/PWM1 output selection bit (PM21) 0 : P01 output 1 : PWM1 output RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 ROM correction enable register (RCR) [Address 020E16] B After resetRW ROM Correction Enable Register 0: Disabled 1: Enabled 1: Enabled to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” RW RW Address 020916 Address 020E16

M3727GM6/M8–XXXSP/FP M37272E8SP/FP Rev.1.00 Apr 01, 2001 page 127 of 127 REJ03B0132-0100Z 19. PACKAGE OUTLINE SDIP42-P-600-1.78 Weight(g) JEDEC Code 4.1 Alloy 42/Cu Alloy 42P4B Plastic 42pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 –1 . 778 – – 15.24 – 3.0 – – 0° –1 5 ° –– 5 . 5 e 42 22 211 E ce1 A2A1 bb1 b2e L A SEATING PLANE D MMP SSOP42-P-450-0.80 Weight(g) JEDEC Code 0.63 Alloy 42/Cu Alloy 42P2R-A/E Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters HE .350 .050 .130 .317 .28 .6311 .30 .271 .02 .40 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .50 .20 .717 .68 .2312 .70 .150 b2 –. 5 0– 0° –1 0 ° e 42 22 211 HE E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G –Z1 0.75 0.9 z b G MMP

REVISION HISTORY

Rev. Date Description Page Summary M3727GM6/M8–XXXSP/FP M37272E8SP/FP

1.00 Apr 01,2001 – First edition issued

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