M37225MA

M37225M6 RENESAS | Alldatasheet

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M37225M6/M8/MA/MC–XXXSP, M37225ECSP SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER REJ03B0136-0100Z Rev.1.00 Nov 01, 2000 Rev.1.00 Nov 01, 2000 page 1 of 124 REJ03B0136-0100Z 1. DESCRIPTION The M37225M6/M8/MA/MC–XXXSP are single-chip microcomput- ers designed with CMOS silicon gate technology. They have a OSD, I 2C-BUS interface, PWM output, and 12 V withstand, so it is useful for a channel selection system for TV. The features of the M37225ECSP are similar to those of the M37225M6-XXXSP except that the chip has a built-in PROM which can be written electrically. The differences amang M37225M6/M8/ MA/MC–XXXSP are the ROM, RAM size. Accordingly, the following descriptions will be for the M37225M6-XXXSP. 2. FEATURES G Memory size 32K bytes (M37225M8-XXXSP) 40K bytes (M37225MA–XXXSP) 48K bytes (M37225MC–XXXSP , M37225ECSP) 2048 bytes (M37225MA/MC–XXXSP , M37225ECSP) (✽ ROM correction memory included) G Minimum instruction execution time G Power dissipation (at V CC = 5.5V, 8 MHz oscillation frequency, and OSD on) G Immediate return mode from wait state G OSD function (It is possible to display 3 lines or more by software) Character display area 16 ✕ 20 dots SPRITE display: 1 kinds Display position Horizontal: 64 levels Vertical :255 levels SPRITE display function Wallpaper function Window function Corresponding to bi-scan mode 3. APPLICATION TV

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 2 of 124 REJ03B0136-0100Z TABLE OF CONTENTS

8.6 MULTI-MASTER I

14.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 3 of 124 REJ03B0136-0100Z 4. PIN CONFIGURATION Outline 42P4B Fig. 4.1 Pin Configuration (Top View) P 06/ I N T 2 / A - D 4 XO U T H S Y N C / P 50 VS Y N C / P 51 P 00/ P W M 0 P 01/ P W M 1 P 02/ P W M 2 P 03/ P W M 3 P 04/ P W M 4 P 05/ P W M 5 P 07/ I N T 1 P 23/ T I M 3 P 24/ T I M 2 P 25 P 26 P 27 D A 1 / P 35 P 32/ A - D 7 C N VS S XI N VS S R E S E T R / P 52 G / P 53 B / P 54 O U T 1 / P 55 P 20/ SC L K P 21/ SO U T( /SI N ) P 22/ SI N P 10/ OU T 2 / A - D 8 P 11/ S C L 1 P 12/ S C L 2 P 13/ S D A 1 P 14/ S D A 2 P 16/ A - D 2 P 30/ A - D 5 P 31/ A - D 6 O S C 1 / P 33 O S C 2 / P 34 VC C P 17/ D A 2 /A - D3 P 15/ I N T 3 / A - D 1 M 3 7 2 2 5 M 6 / M 8 / M A / M C - X X X S P M E C S P

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 4 of 124 REJ03B0136-0100Z 5. FUNCTIONAL BLOCK DIAGRAM Fig. 5.1 Functional Block Diagram of M37225 O U T C l o c k i n p u t C l o c k o u t p u t X I N X O U T R e s e t i n p u t V C C V S S C N V S S I n p u t p o r t s P P O S C O S C C l o c k i n p u t f o r O S D P W M P W M P W M P W M P W M P W M P 5 B G R HS Y N C VS Y N C 1 4 b i t P W M c i r c u i t b i t P W M c i r c u i t A c c u m u l a t o r A T i m e r T T i m e r T T i m e r T T i m e r T T i m e r c o u n t s o u r c e s e l e c t i o n c i r c u i t T I M T I M I n s t r u c t i o n r e g i s t e r I n s t r u c t i o n d e c o d e r C o n t r o l s i g n a l O S D c i r c u i t S t a c k p o i n t e r S I n d e x r e g i s t e r X P r o c e s s o r s t a t u s r e g i s t e r P S b i t a r i t h m e t i c a n d l o g i c a l u n i t R O M P r o g r a m c o u n t e r P C L P r o g r a m c o u n t e r P C H R A MD a t a b u s C l o c k g e n e r a t i n g c i r c u i t R E S E T O u t p u t p o r t s P 52–P O S D o u t p u t A d d r e s s b u s S I O SI N SC L K SO U T I N T I N T I N T I O p o r t s P 30–P 32, P 1 7 2 6 2 7 1 6 P 4 0 4 1 4 2 2 0 1 9 2 5 2 2 2 1 1 8 2 4 2 3 I n d e x r e g i s t e r Y M u l t i m a s t e r I2C B U S i n t e r f a c e R O M c o r r e c t i o n f u n c t i o n S y n c s i g n a l i n p u t I n p u t p o r t s P 50, P S D A S D A S C L S C L A D c o n v e r t e r I O p o r t P 2 9 3 0 3 1 3 2 3 3 3 4 3 5 P I O p o r t P 1 4 1 3 1 2 1 1 3 6 3 7 3 8 P I O p o r t P P 1 4 b i t P W M c i r c u i t O U T C l o c k o u t p u t f o r O S D

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 5 of 124 REJ03B0136-0100Z Number of basic instructions Instruction execution time Clock frequency Memory size Input/Output ports Serial I/O Multi-master I2C-BUS interface A-D converter PWM output circuit Timers ROM correction function Subroutine nesting Interrupt Clock generating circuit ROM RAM OSD ROM OSD RAM 0–P05 P06, P07 0, P31, P35 P32 P33, P34 P50, P51 P52–P55 I/O I/O I/O I/O I/O I/O Input Input Output 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre- quency)

8 MHz (maximum)

1024 bytes (ROM correction memory included) 2048 bytes (ROM correction memory included) 15K bytes 96 bytes 6-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM output pins) 2-bit ✕ 1 (N-channel open-drain output structure, can be used as INT input pins, A-D input pin) 8-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin, INT input pin, A-D input pins, DA output pin, multi-master I 2C-BUS interface) 8-bit ✕ 1 (CMOS input/output structure, can be used as serial I/O pins, timer external clock input pins) 3-bit ✕ 1 (CMOS output structure, or N-channel open-drain output struc- ture, can be used as A-D input pins, DA output pin) 1-bit ✕ 1 (N-channel open-drain output structure, can be used as A-D input pin) 2-bit ✕ 1 (Can be used as OSD clock input/output pins) 2-bit ✕ 1 (N-channel open-drain output structure, can be used as horizonal

• vertical synchronous sibnal input pins) 4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins) 8-bit ✕ 1 1 (2 systems) 8 channels (8-bit resolution) 14-bit ✕ 2, 8-bit ✕ 6 8-bit timer ✕ 4 3 vectors 128 levels (maximum) <16 types> INT external interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1, OSD interrupt ✕ 1, Multi-master I 2C-BUS interface interrupt ✕ 1, f(XIN)/4096 interrupt ✕ 1, SPRITE OSD interrupt ✕ 1, A-D conversion inter- rupt ✕ 1, VSYNC interrupt ✕ 1, BRK instruction interrupt ✕ 1, reset ✕ 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz- crystal oscillator) Parameter 6. PERFORMANCE OVERVIEW M37225M6-XXXSP M37225M8-XXXSP M37225MA-XXXSP M37225MC-XXXSP , M37225ECSP M37225M6/M8-XXXSP M37225MA/MC-XXXSP, M37225ECSP Table 6.1 Performance Overview Functions

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 6 of 124 REJ03B0136-0100Z Power source voltage Power dissipation Number of display characters Dot structure Kinds of characters Kinds of character sizes Character font coloring Display position Functions Table 6.2 Performance Overview (Continued) OSD function 24 characters ✕ 2 lines 16 ✕ 20 dots 381 kinds 3 kinds 1 screen : 8 kinds (per character unit) Horizontal : 64 levels, Vertical : 255 levels 5V ± 10% 165 mW typ. ( at oscillation frequency f(X IN) = 8 MHz, fOSC = 8 MHz) 110 mW typ. ( at oscillation frequency f(XIN) = 8 MHz) 1.65 mW ( maximum ) –10 °C to 70 °C CMOS silicon gate process 42-pin plastic molded SDIP Parameter OSD ON OSD OFF In stop mode Operating temperature range Device structure Package

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 7 of 124 REJ03B0136-0100Z Pin Name Input/ FunctionsOutput VCC , Power source Apply voltage of 5 V ± 10 % to (typical) V CC , and 0 V to VSS . VSS CNV SS CNV SS This is connected to VSS . RESET Reset input Input To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should be maintained for the required time. XIN Clock input Input This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT Clock output Output X OUT . If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. P00/PWM0– I/O port P0 I/O Port P0 is an 8-bit I/O port with dire ction register allowing each I/O bit to be individually P05/PWM5 , programmed as input or output. At reset, this port is set to input mode. The output structure P06/INT2/A-D4, is N-channel open-drain output. (See note 1) P07/INT1 PWM output Output Pins P0 0–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output structure is N-channel open-drain output. External interrupt Input P ins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 input respectively. Analog input Input P0 6 pin is also used as analog input pin A-D4. P10/OUT2/A-D8, I/O port P1 I/O P ort P1 is an 8-bit I/O port and has basically the same functions as port P0. The P11/SCL1, output structure is CMOS output. (See note 1) P12/SCL2, OSD output Output Pins P1 0 is also used as OSD output pin OUT2. The output structure is CMOS output. P13/SDA1, Multi-master I/O Pins P1 1–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master P14/SDA2, I2C-BUS interface I 2C-BUS interface is used. The output structure is N-channel open-drain output. P15/INT3/A-D1, Analog input Input Pins P1 0, P15–P17 are also used as analog input pin A-D8, A-D1–A-D3 respectively. P16/A-D2, External interrupt Input P1 5 pin is also used as INT external interrupt input pin INT3. P17/DA2/A-D3 input DA output Output Pins P1 7 is also used as 14-bit PWM output pin DA2. The output structure is CMOS output. P20/SCLK , I/O port P2 I/O Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The P21/SOUT (/SIN), output structure is CMOS output. (See note 1) P22/SIN, Serial I/O synchronous I/O P2 0 pin is also used as serial I/O synchronous clock input/output pin SCLK . The output P23/TIM3, clock input/output port structure is N-channel open-drain output. P24/TIM2, Serial I/O data I/O P2 1 pin is also used as serial I/O data input/output pin SOUT (/SIN). The output P25–P27 input/output structure is N-channel open-drain output. Serial I/O data inputInput P2 2 pin is also used as serial I/O data input pin SIN. External clock Input P ins P23 and P24 are also used as timer external clock input pins TIM3 and TIM2 input for timer respectively. P30/A-D5, I/O port P3 I/O Ports P3 0–P32 and P35 are a 3-bit I/O port and has basically the same functions as port 0 P31/A-D6, (see note 1). Either CMOS output or N-channel open-drain output structure can be selected P32/A-D7, as ports P3 0, P31 and P3 5. The output structure of port P32 is N-channel DA1/P35 open-drain output structure.(See notes 1, 2) Analog input Input Pins P3 0–P32 are also used as analog input pins A-D5–A-D7 respectively. DA output Output P3 5 pin is also used as 14-bit PWM output pin DA1. The output structure is CMOS output. At reset, output is undefined. OSC1/P3 3, Input port P3 Input Pins P3 3 and P34 are a 2-bit input port. OSC2/P3 4, Clock input for OSD Input P3 3 pin is also used as OSD clock input pin OSC1. Clock output for OSD Output P3 4 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. 7. PIN DESCRIPTION Table 7.1 Pin Description

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 8 of 124 REJ03B0136-0100Z Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 2: To switch output structures, set by the following bits. P30 : bit 6 of port P3 direction register P31 : bit 7 of port P3 direction register P35 : bit 5 of port P35 output mode control register When “0,” CMOS output; when “1,” N-channel open-drain output. Pin Name Input/ FunctionsOutput H SYNC /P50, Input port P5 Input Ports P5 0 and P51 are a 2-bit input port. VSYNC /P51 H SYNC input Input This is a horizontal synchronizing signal input for OSD. VSYNC input Input This is a vertical synchronizing signal input for OSD. R/P52, Output port P5 Output Ports P5 2–P55 are a 4-bit output port. The output structure is CMOS output. G/P53, B/P54, OSD output Output Pins P5 2–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output OUT1/P5 5 structure is CMOS output. At reset, output is LOW. Table 7.2 Pin Description (continued)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 9 of 124 REJ03B0136-0100Z Fig. 7.1 I/O Pin Block Diagram (1) N-channel open-drain output Ports P00–P05 Note :Each port is also used as follows : P0 0–P05 : PWM0–PWM5 N-channel open-drain output Ports P06, P07, P32 Note :Each port is also used as follows : P06 : INT2/A-D4 P07 : INT1 CMOS output Ports P1, P2, P30, P31, P35 Notes 1:Each port is also used as follows : P10 : OUT2/AD8 P2 2 : SIN P11 : SCL1 P2 3 : TIM3 P12 : SCL2 P2 4 : TIM2 P13 : SDA1 P3 0 : A-D5 P14 : SDA2 P3 1 : A-D6 P15 : INT3/A-D1 P35 : DA1 P16 : A-D2 P17 : DA2/A-D3 P20 : SCLK P21 : SOUT /(SIN) 2: Either CMOS output or N-channel open- drain output structure can be selected as ports P30, P31 and P35 (when selecting N-channel open-drain, it is the same with N-channel open-drain output below). P o r t s P 1 , P 2 , P 30, P 31 D a t a b u s P o r t s P 00 –P 05 D a t a b u s P o r t s P 06, P 07, P 32 D a t a b u s Direction register P o r t l a t c h D i r e c t i o n r e g i s t e r P o r t l a t c h D i r e c t i o n r e g i s t e r P o r t l a t c h

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 10 of 124 REJ03B0136-0100Z P50, P51 Internal circuit D a t a b u s I n t e r n a l c i r c u i t P 52– P 55 D a t a b u s P o r t l a t c h P 33, P 34 D a t a b u s CMOS output Ports P52–P55 Note :Each pin is also used as follows : P52 : R P53 : G P54 : B P55 : OUT1 Schmidt input Ports P50, P51 Note :Each pin is also used as follows : P50 : HSYNC P51 : VSYNC Fig. 7.2 I/O Pin Block Diagram (2) Input Ports P33, P34 Note :Each pin is also used as follows : P33 : OSC1 P34 : OSC2

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 11 of 124 REJ03B0136-0100Z 8. FUNCTIONAL DESCRIPTION

8.1 CENTRAL PROCESSING UNIT (CPU)

This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used.

8.1.1 CPU Mode Register

The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allo- cated at address 00FB 16. Fig. 8.1.1 CPU Mode Register C P U M o d e R e g i s t e r b7b6 b5b4b3 b2b1b0 B A f t e r r e s e t R W 0 , 1 3 t o 5 N a m e Functions Processor mode bits (CM0, CM1) 0 0: Single-chip mode 0 1: 1 0: Not available 1 1: Fix these bits to “1.” 1Stack page selection bit (CM2) (See note) b1 b0 0: 0 page 1: 1 page 1 00 6, 7 0 C P U m o d e r e g i s t e r ( C M ) [ A d d r e s s 0 0 F B1 R W R W R W R W Note: This bit is set to “1” after the reset release. 100 F i x t h e s e b i t s t o “ 0 . ”

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 12 of 124 REJ03B0136-0100Z

8.2 MEMORY

8.2.1 Special Function Register (SFR) Area

The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.

8.2.2 RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

8.2.3 ROM

ROM is used for storing user programs as well as the interrupt vector area.

8.2.4 OSD RAM

RAM for display is used for specifying the character codes and col- ors to display.

8.2.5 OSD ROM

ROM for display is used for storing character data.

8.2.6 Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

8.2.7 Zero Page

The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.

8.2.8 Special Page

The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.

8.2.9 ROM Correction Vector

This is used as the program jump destination addresses for ROM correction.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 13 of 124 REJ03B0136-0100Z Fig. 8.2.1 Memory Map (M37225M6/M8-XXXSP) 0 0 0 01 0 0 C 01 0 0 F F1 0 1 F F1 SFR area 0 2 1 71 0 2 1 D 1 0 2 4 01 0 2 E 01 0 1 0 01 0 2 4 F1 0 2 C 01 R O M c o r r e c t i o n f u n c t i o n V e c t o r a d d r e s s C V e c t o r a d d r e s s E V e ct o r a d d r e s s I M M M X X X S P ( 1 0 2 4 b y t e s ) 0 8 7 71 080016OSD RAM (96 byres) (See note) 800016 F F F F1 F F D E1 F F 0 01 I n t e r r u p t v e c t o r a r e a Special page A00016 M 3 7 2 2 5 M 8 - X X X S P R O M K b y t e s M 3 7 2 2 5 M 6 - X X X S P R O M K b y t e s 00BF 16 Note: Refer to Table 8.10.3 OSD RAM. 1 0 0 0 01 1 3 B F F1 1 1 4 0 01 154FF16 1540016 1 5 6 F F1 1 5 6 0 01 OSD ROM (15K bytes)

1 F F F F1

2 page register (1) Not used 2 page register (2) Not used Not used Not used Not used Not used Not used N o t u s e d N o t u s e d Not used Not used Not used N o t u s e d Not used N o t u s e d Not used Not used Not used N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 14 of 124 REJ03B0136-0100Z Fig. 8.2.2 Memory Map (M37225MA/MC-XXXSP, M37225ECSP) 0 0 0 01 0 0 C 01 0 0 F F1 0 1 F F1 S F R a r e a Z e r o p a g e 0 2 1 71 0 2 1 D 1 0 2 4 01 0 1 0 01 0 2 4 F1 400016 FFFF 16 F F D E1 F F 0 01 M 3 7 2 2 5 M C - X X X S P M E C S P R O M K b y t e s R A M b y t e s N o t e : R e f e r t o T a b l e 8 . 1 0 . 3 O S D R A M . 1 0 0 0 01 1 3 B F F1 1 1 4 0 01 1 5 4 F F1 1540016 1 5 6 F F1 1 5 6 0 01 O S D R O M K b y t e s I M 3 7 2 2 5 M A / M C - X X X S P , M 3 7 2 2 5 E C S P 0 2 E 01 0 2 C 01 0 7 F F1 0 3 0 01 0 8 7 71 0 8 0 01 0 9 0 01 09FF16 O S D R A M b y t e s S e e n o t e N o t u s e d 2 p a g e r e g i s t e r ( 1 ) N o t u s e d 2 p a g e r e g i s t e r ( 2 ) N o t u s e d R O M c o r r e c t i o n f u n c t i o n V e c t o r a d d r e s s C V e c t o r a d d r e s s E V e c t o r a d d r e s s N o t u s e d Not used I n t e r r u p t v e c t o r a r e a Special page N o t u s e d Not used Not used N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d Not used Not used Not used N o t u s e d N o t u s e d N o t u s e d Not used N o t u s e d N o t u s e d N o t u s e d N o t u s e d Not used N o t u s e d M 3 7 2 2 5 M A - X X X S P R O M K b y t e s 6 0 0 01

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 15 of 124 REJ03B0136-0100Z Fig. 8.2.3 Memory Map of Special Function Register (SFR) (1) I S F R a r e a a d d r e s s e s C t o D D 01 D1 16 D 21 D 31 D 41 D 51 D 61 D 71 D8 16 D 91 D A1 DB 16 DC 16 D D 1 D E1 D F1 C 01 C 11 C 21 C3 16 C4 16 C 51 C 61 C 71 C 81 C9 16 C B1 C C 1 CD 16 C E1 C F1 CA 16 A d d r e s s Port P5 (P5) O S D p o r t c o n t r o l r e g i s t e r ( P F ) D A 1 - H r e g i s t e r ( D A 1 - H ) D A 1 - L r e g i s t e r ( D A 1 - L ) PWM0 register (PWM0) Port P1 (P1) P o r t P 1 d i r e c t i o n r e g i s t e r ( D 1 ) Port P3 (P3) P o r t P 3 d i r e c t i o n r e g i s t e r ( D 3 ) Port P2 (P2) P o r t P 2 d i r e c t i o n r e g i s t e r ( D 2 ) R e g i s t e r P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( D 0 ) PWM1 register (PWM1) P W M 2 r e g i s t e r ( P W M 2 ) P W M 3 r e g i s t e r ( P W M 3 ) PWM4 register (PWM4) P W M o u t p u t c o n t r o l r e g i s t e r 1 ( P W ) b 7 b 0 Bit allocation State immediately after reset 0016 b7 b0 0016 0016 000??000 S e r i a l I / O m o d e r e g i s t e r ( S M ) Serial I/O register (SIO) 0016 Port P35 output m ode control register (P3S) T e s t r e g i s t e r Interrupt input polarity register (IP) P W M o u t p u t c o n t r o l r e g i s t e r 2 ( P N ) I2C d a t a s h i f t r e g i s t e r S I2C c o n t r o l r e g i s t e r S D I2C c l o c k c o n t r o l r e g i s t e r S I2C status register (S1) I2C address register (S0D) A D c o n v e r s i o n r e g i s t e r ( A D ) A D c o n t r o l r e g i s t e r ( A D C O N ) P52 SEL 00P53 SEL P54 SEL P55 SEL O U T2 SEL0 P52 OUT P 5 3 O U T P 5 4 O U T P 5 5 O U T P 5 0 I N P 5 1 I N

00 P35S

P 3 1 SP 3 0 SP 3 5 DP 3 2 D P31D P30D P32 P31 P30P35 P34INP 33IN ? 0 ??00 ??0 P W 0PW1PW2P W 3P W 4P W 5PW6P W 7 PN2P N N 0016 0016 0016 SAD 0SAD 1SAD 2SAD 3SAD 4SAD 5SAD 6 RB W LRBA D 0AASALP I NBBTRXM S T BC0B C 1BC2E S OA L SB S E L 0B S E L 1 1 0 B I T S A D D 1D2D3D 4D5D 6D7 D PN5 00 00

00 POL3 POL2 POL1 OCG1OCG0

01 100? ?0 0016 0016 S M 0SM1SM2S M M 5SM6 0 C C R 0C C R 1C C R 2C C R 3C C R 4AC K FAST M O D E ACK BIT AD IN 000 AD IN 1AD IN 2AD STRA D V R E F 0816 0016 0016 00 ?00010 : Fix to this bit to “0” (do not write to “1”) B i t a l l o c a t i o n > < S t a t e i m m e d i a t e l y a f t e r r e s e t > Function bit : N o f u n c t i o n b i t : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “1” immediately after reset

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 16 of 124 REJ03B0136-0100Z Fig. 8.2.4 Memory Map of Special Function Register (SFR) (2) F 01 F 11 F 21 F316 F 41 F 51 F 61 F 71 F816 F916 F A1 F B1 FC 16 F D 1 F E1 F F1 E 01 E 11 E 21 E 31 E 41 E 51 E616 E716 E816 E916 E B1 EC 16 ED 16 EE 16 E F1 E A1

6 OSD control register (OC)

Color register 5 (CO5) Color register 7 (CO7) Color register 8 (CO8) Timer 1 (T1) Block 2V register (B2VP) Color register 1 (CO1) Color register 2 (CO2) SPRITE H register (SHP) SPRITE V register (SVP) Block H register (BHP) Block 1V register (B1VP) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) PWM5 register (PWM5) Block 1 control register (B1C) Interrupt request register 1 (IR EQ 1) Interrupt request register 2 (IR EQ 2) Interrupt control register 1 (IC O N 1) Interrupt control register 2 (IC O N 2) Color register 3 (CO3) Color register 4 (CO4) Color register 6 (CO6) CPU mode register (CM) b 7 b 0 S C 0S C 1SC2SC3 OC0OC1OC2 T M 2 0T M 2 1TM22TM23T M 2 4 T M 1 0T M 1 1TM12TM13T M 1 4 CM2 TM1RTM2RTM3RTM4RO SD RVSCRIT3R C K 0MSR IT1RI T 2 RS1R T M 1 ET M 2 ETM3ETM4EO SD EV S C EIT3E IT1EIT2ES1EMSE TM25 b 7 b 0 C K F F1 0716 F F1 0 71 00 ?? ? TM15 01 11 0 01 0016 0 01 0 01 0? ?

3 C 1

SPRITE control register (SC) O SD I/O polarity control register (O PC ) Test register Test register ADE ADR SPE SPR IICR B 2 C 0B 2 C 1B2C2B2C3B 2 C 4 B1C0B1C1B1C2B1C3B1C4 0016 0016 C K 000 ?? ?0? ?Block 2 control register (B2C) BH P0BH P1B H P 2B H P 3BH P4B H P 5 B1VP0B1VP1B 1 V P 2B 1 V P 3B1VP4B 1 V P 5B 1 V P 6B 1 V P 7 B2VP0B2VP1B 2 V P 2B 2 V P 3B2VP4B 2 V P 5B 2 V P 6B 2 V P 7 S C 4SC5S C 6S C 7 SH P0SH P1SH P2SH P3SH P4SH P5SH P6 SVP0SVP1S V P 2S V P 3SVP4S V P 5SVP6S V P 7 OC3OC4OC5OC6OC7 O PC 0O PC 1O P C 2O P C 3O PC 4O P C 5O PC 6O P C 7 CO11CO12CO13CO15 CO21CO22CO23CO25 CO14 CO24 CO16 CO26 CO10 CO20 CO31CO32CO33CO35 CO34CO36 CO30 CO41C O 4 2CO43CO45 C O 4 4C O 4 6C O 4 0 CO51C O 5 2CO53CO55 CO61CO62CO63CO65 C O 5 4 CO64 C O 5 6 CO66 CO50 CO60 CO71C O 7 2CO73CO75 C O 7 4C O 7 6C O 7 0 CO81CO82CO83CO85 CO84CO86 CO80 0 01 0 01 0016 I S F R a r e a a d d r e s s e s E t o F A d d r e s s R e g i s t e r Bit allocation S t a t e i m m e d i a t e l y a f t e r r e s e t : Fix to this bit to “0” (do not write to “1”) B i t a l l o c a t i o n > < S t a t e i m m e d i a t e l y a f t e r r e s e t > Function bit : No function bit : Fix to this bit to “1” (do not write to “0”) N a m e : : “0” immediately after reset : Indeterminate immediately after reset : “ 1 ” i m m e d i a t e l y a f t e r r e s e t IICE SH P7

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 17 of 124 REJ03B0136-0100Z Fig. 8.2.5 Memory Map of 2 Page Register Area b 7 b0 b7 b0 2 1 01 21116 2 1 21 2 1 31 2 1 41 2 1 51 2 1 61 2 1 71 2 1 81 21916 21B16 2 1 C 1 2 1 D 1 2 1 E1 2 1 F1 21A16 R O M correction enable register (R C R ) R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) R O M c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) R O M correction address 2 (high-order) R O M correction address 2 (low -order) RCR1RCR0 0 0 0016 0016 0016 0 0016 2 4 01 2 4 11 24216 24316 2 4 41 2 4 61 2 4 51 L e f t b o r d e r c o n t r o l r e g i s t e r ( L B R ) B B R 0 2 4 71 2 4 91 24816 T e s t r e g i s t e r 0 01 24A16 2 4 B1 2 4 C 1 6 ? 2 4 E1 2 4 D 1 24F16 R i g h t b o r d e r c o n t r o l r e g i s t e r ( R B R ) T o p b o r d e r c o n t r o l r e g i s t e r ( T B R ) B o t t o m b o r d e r c o n t r o l r e g i s t e r ( B B R ) 0 01 BBR1BBR2B B R 3B B R 4B B R 5BBR6B B R 7 T B R 0TBR1TBR2T B R 3T B R 4T B R 5TBR6T B R 7 RBR0RBR1R B R 2R B R 3R B R 4R B R 5RBR6 LBR0LBR1L B R 2L B R 3L B R 4L B R 5LBR6 D A2-L register (D A2L) D A 2 - H r e g i s t e r ( D A 2 H ) 0016 0 01 I p a g e r e g i s t e r a r e a a d d r e s s e s t o t o A d d r e s s R e g i s t e r B i t a l l o c a t i o nS t a t e i m m e d i a t e l y a f t e r r e s e t : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o < Bit allocation >< S t a t e i m m e d i a t e l y a f t e r r e s e t > F u n c t i o n b i t : No function bit : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N am e : : “ 0 ” i m m e d i a t e l y a f t e r r e s e t : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “ 1 ” i m m e d i a t e l y a f t e r r e s e t 0000 R O M correction address 3 (high-order) R O M c o r r e c t i o n a d d r e s s 3 (l o w- o r d e r ) 0 01 0 01 RCR2

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 18 of 124 REJ03B0136-0100Z Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset b 7 b 0 b 7 b 0 R e g i s t e r P r o c e s s o r s t a t u s r e g i s t e r ( P S ) Bit allocation S t a t e i m m e d i a t e l y a f t e r r e s e t P r o g r a m c o u n t e r ( P C H ) P r o g r a m c o u n t e r ( P C L) Contents of address FFFF16 C o n t e n t s o f a d d r e s s F F F E1 : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o B i t a l l o c a t i o n > < S t a t e i m m e d i a t e l y a f t e r r e s e t F u n c t i o n b i t : N o f u n c t i o n b i t : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “ 1 ” i m m e d i a t e l y a f t e r r e s e t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 19 of 124 REJ03B0136-0100Z Priority

8.3 INTERRUPTS

Interrupts can be caused by 16 different sources consisting of 3 ex- ternal, 14 internal, 1 software, and reset. Interrupts are vectored in- terrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, x The contents of the program counter and processor status regis- ter are automatically stored into the stack. ➁ The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” ➂ The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are ac- cepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt control.

8.3.1 Interrupt Causes

(1) VSYNC , OSD, SPRITE OSD Interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. The SPRITE OSD interrupt occurs at the completion of SPRITE display. (2) INT1 to INT3 External Interrupts The INT1 to INT3 interrupts are external interrupt inputs, the sys- tem detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The in- put active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00CD 16) : when this bit is “0,” a change from LOW to HIGH is detected; when it is “1,” a change from HIGH to LOW is detected. Note that both bits are cleared to “0” at reset. (3) Timers 1 to 4 Interrupts An interrupt is generated by an overflow of timers 1 to 4. Vector Addresses FFFF 16, FFFE16 FFFD 16, FFFC16 FFFB 16, FFFA16 FFF9 16, FFF816 FFF7 16, FFF616 FFF5 16, FFF416 FFF3 16, FFF216 FFF1 16, FFF016 FFEF 16, FFEE16 FFED 16, FFEC16 FFEB 16, FFEA16 FFE9 16, FFE816 FFE7 16, FFE616 FFE5 16, FFE416 FFE3 16, FFE216 FFDF 16, FFDE16 Interrupt Source Reset OSD interrupt INT2 external interrupt INT1 external interrupt SPRITE OSD interrupt Timer 4 interrupt f(X IN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I 2C-BUS interface interrupt INT3 external interrupt A-D conversion interrupt BRK instruction interrupt Remarks Non-maskable Active edge selectable Active edge selectable Active edge selectable Non-maskable Table 8.3.1 Interrupt Vector Addresses and Priority

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 20 of 124 REJ03B0136-0100Z (4) Serial I/O Interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 Interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe- riod. Set bit 0 of the PWM mode register 1 to “0.” (6) Multi-master I2C-BUS Interface Interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (7) A-D Conversion Interrupt The A-D conversion interrupt occurs at the completion of A-D conversion. (8) BRK Instruction Interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 21 of 124 REJ03B0136-0100Z Fig. 8.3.2 Interrupt Request Register 1 b 7b 6 b 5b 4b 3 b 2b1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 0 0 F C BNam e Functions After reset RW I n t e r r u p t R e q u e s t R e g i s t e r 0 0 : N o interrupt request issued 1 : Interrupt request issued T i m e r 1 i n t e r r u p t r e q u e s t b i t T M R

1 T i m e r 2 i n t e r r u p t

r e q u e s t b i t T M R

2 Timer 3 interrupt

request bit (TM3R)

3 Timer 4 interrupt

request bit (TM4R)

4 OSD interrupt request

bit (OSDR)

5 VSYNC interrupt

request bit (VSCR) 6 M u l t i m a s t e r I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t I I C R 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o interrupt request issued 1 : Interrupt request issued 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ ✽: “0” can be set by software, but “1” cannot be set. R R R R R R R RINT3 external interrupt request bit (IT3R) 0 : N o interrupt request issued 1 : Interrupt request issued Fig. 8.3.3 Interrupt Request Register 2 b 7b 6b 5b 4b 3 b 2b 1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 0 0 F D BNam e Functions A f t e r r e s e t RW I n t e r r u p t R e q u e s t R e g i s t e r 2

0 INT1 external interrupt

request bit (IT1R) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d

2 S e r i a l I / O i n t e r r u p t

r e q u e s t b i t S R 4 f ( XI N ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t M S R 7 F i x t h i s b i t t o “ 0 . ” 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t 0 ✽ 0 ✽ 0 ✽ 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 16] R R R R ✽ R R — R W S P R I T E O S D i n t e r r u p t r e q u e s t b i t S P R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d

6 A - D c o n v e r s i o n i n t e r r u p t

r e q u e s t b i t A D R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” INT2 external interrupt request bit (IT2R)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 22 of 124 REJ03B0136-0100Z Fig. 8.3.4 Interrupt Control Register 1 b 7b 6 b 5b 4b 3 b 2b 1b0 I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 0 0 F E1 BName F u n c t i o n s RW I n t e r r u p t C o n t r o l R e g i s t e r

0 T i m e r 1 i n t e r r u p t

e n a b l e b i t T M E 0 : Interrupt disabled 1 : Interrupt enabled e n a b l e b i t T M E

2 T i m e r 3 i n t e r r u p t

e n a b l e b i t T M E

4 O S D i n t e r r u p t e n a b l e b i t

O S D E 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW RW RW R T i m e r 4 i n t e r r u p t e n a b l e b i t T M E 0 : Interrupt disabled 1 : Interrupt enabled 5 VS Y N C i n t e r r u p t e n a b l e b i t V S C E 0 : Interrupt disabled 1 : Interrupt enabled 0 RW 6 0 : Interrupt disabled 1 : Interrupt enabled 0 RW A f t e r r e s e t I N T 3 e x t e r n a l i n t e r r u p t e n a b l e b i t I T E M ulti-m aster I2C -BU S interface interrupt enable bit (IIC E) 0 : Interrupt disabled 1 : Interrupt enabled W Fig. 8.3.5 Interrupt Control Register 2 b 7b6 b 5b 4b 3 b 2b 1b 0 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 0 0 F F1 BN a m eF u n c t i o n s A f t e r r e s e tRW I n t e r r u p t C o n t r o l R e g i s t e r 2

0 I N T 1 e x t e r n a l i n t e r r u p t

e n a b l e b i t I T E 0 : Interrupt disabled 1 : Interrupt enabled

1 I N T 2 e x t e r n a l i n t e r r u p t

e n a b l e b i t I T E e n a b l e b i t S E 4 f ( XI N ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t M S E 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 RW RW RW RW RW S P R I T E O S D i n t e r r u p t e n a b l e b i t S P E 0 : Interrupt disabled 1 : Interrupt enabled 5 F i x t h i s b i t t o “ 0 . ” 0 R e n a b l e b i t A D E 0 : Interrupt disabled 1 : Interrupt enabled 0 RW 7 0 R—N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s W

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 23 of 124 REJ03B0136-0100Z Fig. 8.3.6 Interrupt Input Polarity Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 Interrupt input polarity register (IP) [Address 00CD 16] b N a m e Function A f t e r r e s e t R W I n t e r r u p t I n p u t P o l a r i t y R e g i s t e r INT1 polarity switch bit (POL1) 0 : Positive polarity 1 : Negative polarity 6, 7

0 R W

s w i t c h b i t P O L I N T 3 p o l a r i t y s w i t c h b i t P O L Fix these bits to “0.” 0 WR 0 WR 0 , 1 O S D c l o c k s e l e c t i o n b i t s O C G O C G Since the main clock is used as the clock for OSD, the oscillation frequency is limited. Because of this, the character size in width (horizonal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P3 and P34 respectively. The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode.

• a ceramic resonator only for OSD and a feedback resistor
• a quartz-crystal oscillator only for OSD and a feedback resistor b 1 The clock for OSD is supplied by connecting RC or LC across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. Function b 0 O S D o s c i l l a t i o n f r e q u e n c y f XI N ) The clock for OSD is supplied by connecting LC across the pins OSC1 and OSC2. In the bi-scan mode, be sure to set this. Fix this bit to “0.” 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 24 of 124 REJ03B0136-0100Z

8.4 TIMERS

This microcomputer has 4 timers: timers 1 to 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the correspond- ing timer latch (addresses 00F0 16 to 00F316 : timers 1 to 4), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse, after the count value reaches “00 16.”

8.4.1 Timer 1

Timer 1 can select one of the following count sources:

• f(X IN)/16
• f(XIN)/4096 or f(XCIN)/4096 The count source of timer 1 is selected by setting bit 0 of timer mode register 1 (address 00F416). Timer 1 interrupt request occurs at timer 1 overflow.

8.4.2 Timer 2

Timer 2 can select one of the following count sources:

• f(X IN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F4 16). When timer 1 overflow sig- nal is a count source for the timer 2, the timer 1 functions as an 8-bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.

8.4.3 Timer 3

Timer 3 can select one of the following count sources:

• f(XIN)/16
• External clock from the HSYNC pin
• External clock from the TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of timer mode register 2 (address 00F5 16). Timer 3 interrupt request occurs at timer 3 overflow.

8.4.4 Timer 4

Timer 4 can select one of the following count sources:

• f(X IN)/16
• f(XIN)/2
• Timer 3 overflow signal The count source of timer 3 is selected by setting bits 1 and 4 of timer mode register 2 (address 00F5 16). When timer 3 overflow sig- nal is a count source for the timer 4, the timer 3 functions as an 8-bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. At reset, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set both bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. However, when setting “1” to bit 5 of timer mode register 1 (address 00F4 16), timers 3 and 4 are not set the above value, the STP state is set by executing the STP instruction. This allows to program the time to return from the STP state.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 25 of 124 REJ03B0136-0100Z Fig. 8.4.2 Timer Mode Register 2 b 7b 6 b 5b 4b 3 b 2b 1b 0 T i m e r m o d e r e g i s t e r 2 ( T M 2 ) [ A d d r e s s 0 0 F 51 B After reset RW Timer Mode Register 2 N a m e F u n c t i o n s T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t T M 0 RW

1 Timer 4 internal

selection bit (TM21) 0 RW Timer 3 count stop bit (TM22) 0: Count start 1: Count stop T i m e r 4 c o u n t s t o p b i t T M 0: Count start 1: Count stop

4 T i m e r 4 c o u n t s o u r c e

s e l e c t i o n b i t T M 0: Internal clock source 1: f(XIN)/2

5 T i m e r 3 e x t e r n a l c o u n t

s o u r c e s e l e c t i o n b i t T M 0 : T I M 3 p i n i n p u t H S Y N C p i n i n p u t RW RW RW RW 0 : f ( XI N ) / 1 6 E x t e r n a l c l o c k s o u r c e 0 : T i m e r 3 o v e r f l o w s i g n a l f XI N ) 6 , 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R Fig. 8.4.1 Timer Mode Register 1 b 7b 6 b 5b 4b 3 b 2b 1b 0 T i m e r m o d e r e g i s t e r 1 ( T M 1 ) [ A d d r e s s 0 0 F 41 B A f t e r r e s e t W T i m e r M o d e R e g i s t e r N a m e Functions T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t T M 0 : f ( XI N ) / 1 6 f XI N ) T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t T M 0 : I n t e r r u p t c l o c k s o u r c e E x t e r n a l c l o c k f r o m T I M p i n T i m e r 1 c o u n t s t o p b i t T M 0 : C o u n t s t a r t C o u n t s t o p Timer 2 count stop bit (TM13) 0: Count start 1: Count stop T i m e r 2 i n t e r n a l c o u n t s o u r c e s e l e c t i o n b i t T M R WR WR WR WR WR0 : f ( XI N ) / 1 6 T i m e r o v e r f l o w 5 < A t e x e c u t i o n o f S T P i n s t r u c t i o n T i m e r s a n d a u t o s e t d i s a b l e b i t T M 0 : A u t o s e t e n a b l e d A u t o s e t d i s a b l e d 0 WR 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 26 of 124 REJ03B0136-0100Z Fig. 8.4.3 Timer Block Diagram Timer 1 (8) 1 / 4 0 9 6 1 / 2 1/8 Timer 1 latch (8) T M 1 0 T M 1 2 T M 1 4 TM11 T M 1 3 Timer 2 (8) Timer 2 latch (8) Timer 3 (8) Timer 3 latch (8) Timer 4 (8) Timer 4 latch (8) Data bus T i m e r 1 i n t e r r u p t r e q u e s t T i m e r 2 i n t e r r u p t r e q u e s t T M 2 0 T M 2 2 TM25 T M 2 4 T M 2 3 TM21 XI N T I M 2 T I M 3 S e l e c t i o n g a t e : C o n n e c t e d t o b l a c k s i d e a t r e s e t TM1 : Timer mode register 1 TM2 : Timer mode register 2 N o t e s1 : H I G H p u l s e w i d t h o f t i m e r e x t e r n a l c l o c k i n p u t s T I M 2 a n d T I M 3 n e e d s 4 m a c h i n e c y c l e s o r m o r e . W h e n t h e e x t e r n a l c l o c k s o u r c e i s s e l e c t e d t i m e r s a n d a r e c o u n t e d a t a r i s i n g e d g e o f i n p u t s i g n a l I n t h e s t o p m o d e o r t h e w a i t m o d e e x t e r n a l c l o c k i n p u t s T I M a n d T I M c a n n o t b e u s e d FF16 0716 H SYN C Reset Timer 3 interrupt request Timer 4 interrupt request S T P i n s t r u c t i o n T M

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8.5 SERIAL I/O

This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchro- nous clock I/O pin (S CLK ), and data output pin (SOUT ) also function as port P4, data input pin (SIN) also functions as port P2. Bit 3 of the serial I/O mode register (address 00DC16) selects whether the synchronous clock is supplied internally or externally (from the S CLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 4, 16, 32, or 64. To use SIN pin for serial I/O, set the corresponding bit of the port P2 direction regis- ter (address 00C516) to “0.” Fig. 8.5.1 Serial I/O Block Diagram The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock. Serial I/O shift register (8) Data bus Serial I/O interrupt request S y n c h r o n o u s c i r c u i t F r e q u e n c y d i v i d e r 1/321/4 1/64 SM1 SM0 S e r i a l I / O c o u n t e r ( 8 ) S M 5 : L S B MSB S S M 2 S M 6 XI N SI N SOUT SCLK SM3 P21 latch P20 latch SM3 (Address 00DD16) (See note) S M : S e r i a l I / O m o d e r e g i s t e r Note : When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register. Selection gate : C o n n e c t e d t o b l a c k s i d e a t r e s e t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 28 of 124 REJ03B0136-0100Z Internal clock : The serial I/O counter is set to “7” during the write cycle into the serial I/O register (address 00DD16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S OUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.” Fig. 8.5.2 Serial I/O Timing (for LSB first) Synchronous clock Transfer clock Serial I/O register write signal Serial I/O output SOUT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (Note) Serial I/O input SIN Note :When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Interrupt request bit is set to “1” External clock : The an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an exter- nal clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an inter- nal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2:When an external clock is used as the synchronous clock, write trans- mit data to the serial I/O register when the transfer clock input level is HIGH.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 29 of 124 REJ03B0136-0100Z Fig. 8.5.3 Serial I/O Mode Register b7b6 b5b4b3 b2b1b0 S e r i a l I / O m o d e r e g i s t e r ( S M ) [ A d d r e s s 0 0 D C 1 BN a m eF u n c t i o n s A f t e r r e s e t RW S e r i a l I / O M o d e R e g i s t e r 0 , 1I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s S M S M b1 b0 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64

2 S y n c h r o n o u s c l o c k

s e l e c t i o n b i t S M

3 S e r i a l I / O p o r t

s e l e c t i o n b i t S M

5 T r a n s f e r d i r e c t i o n

s e l e c t i o n b i t S M 0 : P 20, P 21 SC L SO U T 0 : E x t e r n a l c l o c k I n t e r n a l c l o c k 0 : L S B f i r s t M S B f i r s t 0 RW RW RW R W RW RW 4 F i x t h i s b i t t o “ 0 . ” 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0R — Serial input pin selection bit (SM6) 0: Input signal from SIN pin. 1: Input signal from SO U T pin.

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8.5.1 Serial I/O Common Transmission/Recep-

By writing “1” to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 8.5.4 shows signals on serial I/O common transmission/re- ception mode. Note:When receiving the serial data after writing “FF16” to the serial I/O regis- ter. Fig. 8.5.4 Signals on Serial I/O Common Transmission/Reception Mode Serial I/O shift register (8) “ 1 ” “ 0 ” ClockSC L K SO U T SI N S M 6 S M : S e r i a l I / O m o d e r e g i s t e r

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 31 of 124 REJ03B0136-0100Z Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I 2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Format Communication mode SCL clock frequency φ : System clock = f(XIN)/2 Note :We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I 2C control register at address 00DA16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).

8.6 MULTI-MASTER I2C-BUS INTERFACE

The multi-master I2C-BUS interface is a serial communications cir- cuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I 2C-BUS in- terface and Table 8.6.1 shows multi-master I2C-BUS interface func- tions. This multi-master I 2C-BUS interface consists of the I2C address reg- ister, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface I2C address register (S0D)b7 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Noise elimination circuit Serial data (SDA) Address comparator I C data shift register Data control circuit I2C clock control register (S2) System clock(φ) Interrupt generating circuit Interrupt request signal (IICIRQ) MST TRX BB PIN AL AAS AD0 LRB I C status register (S1) b7 b0 BSEL1 BSEL0 10BIT SAD ALS BC2 BC1 BC0 I2C control register (S1D) Bit counter BB circuit Clock control circuit Noise elimination circuit Serial clock (SCL) b7 b0 ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 Internal data bus Clock division AL circuit ESO

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8.6.1 I2C Data Shift Register

The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I 2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00DA16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00D916) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift regis- ter is always enabled regardless of the ESO bit value. Note:To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Fig. 8.6.2 Data Shift Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0

0 R e a d / w r i t e b i t

R B W t o S l a v e a d d r e s s S A D t o S A D <O nly in 10-bit addressing (in slave) mode> The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) I n b o t h m o d e s > T h e a d d r e s s d a t a i s c o m p a r e d I2C A d d r e s s R e g i s t e r I2C a d d r e s s r e g i s t e r S D A d d r e s s D B Nam e F u n c t i o n s After resetR W R W

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8.6.2 I2C Address Register

The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the START condition are detected. (1) Bit 0: read/write bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. (2) Bits 1 to 7: slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. Fig. 8.6.3 I2C Address Register b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 R B W to Slave address (SAD0 to SAD6) < O n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > T h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r S T A R T c o n d i t i o n r e a d s t a t e W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r R E S T A R T c o n d i t i o n w r i t e s t a t e 0< I n b o t h m o d e s > T h e a d d r e s s d a t a i s c o m p a r e d I2C A d d r e s s R e g i s t e r I2C address register (S0D) [Address 00D816] B N a m e F u n c t i o n s A f t e r r e s e tR W R W

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8.6.3 I2C Clock Control Register

The I2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL frequency. (1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. (2) Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan- dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. (3) Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). ✽ACK clock: Clock for acknowledgement Fig. 8.6.4 I2C Address Register (4) Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note:Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. b 7 b 6 b5 b 4 b 3 b 2 b 1 b0 I2C clock control register (S2) [Address 00DB16] I2C C l o c k C o n t r o l R e g i s t e r t o S C L f r e q u e n c y c o n t r o l b i t s C C R t o C C R SCL mode specification bit (FAST MODE) 0 : S t a n d a r d c l o c k m o d e H i g h s p e e d c l o c k m o d e 0S t a n d a r d c l o c k m o d e B N a m e F u n c t i o n s A f t e r r e s e t R W A C K b i t A C K B I T A C K c l o c k b i t A C K 0 : A C K i s r e t u r n e d . A C K i s n o t r e t u r n e d 0 : N o A C K c l o c k A C K c l o c k High speed clock mode S e t u p d i s a b l e d Setup disabled00 to 02 S e t u p d i s a b l e d 33303 S e t u p d i s a b l e d 25004 100 400 (See note)05 83.3 16606 C C R v a l u e 1000/C C R value . . . 17.2 3 4 . 51D 16.6 33.31E 16.1 32.31F ( a t φ = 4 M H z , u n i t : k H z ) N o t e : A t 4 0 0 k H z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . p e r i o d p e r i o d I n t h e o t h e r c a s e s t h e d u t y i s a s b e l o w p e r i o d p e r i o d S e t u p v a l u e o f C C R C C R

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8.6.4 I2C Control Register

The I2C control register (address 00DA16) controls the data commu- nication format. (1) Bits 0 to 2: bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “000 2” and the address data is always transmitted and received in 8 bits. (2) Bit 3: I2C interface use enable bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ESO = “0,” the following is performed.

• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I status register at address 00D916 ).
• Writing data to the I2C data shift register (address 00D716) is dis- abled. (3) Bit 4: data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that ad- dress data is recognized. When a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to “8.6.5 I 2C Status Register,” bit 1) is received, trans- mission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recog- nized. (4) Bit 5: addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address register (ad- dress 00D816) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. (5) Bits 6 and 7: connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5). Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1 “0” “1” BSEL0 P11/SCL1 P12/SCL2 “ 0 ” B S E L “ 0 ” B S E L P13/SDA1 P14/SDA2 “0” “1” BSEL1 M u l t i - m a s t e r I2C B U S i n t e r f a c e S C L S D A

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 36 of 124 REJ03B0136-0100Z Fig. 8.6.6 I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 t o B i t c o u n t e r N u m b e r o f t r a n s m i t r e c i e v e b i t s B C t o B C b 2 b 1 b 0

3 I2C-BUS interface use

enable bit (ESO) 0: Disabled 1: Enabled

4 D a t a f o r m a t s e l e c t i o n

b i t A L S 0 : A d d r e s s i n g f o r m a t F r e e d a t a f o r m a t

5 A d d r e s s i n g f o r m a t s e l e c t i o n

b i t B I T S A D 0 : 7 - b i t a d d r e s s i n g f o r m a t b i t a d d r e s s i n g f o r m a t 6, 7 C onnection control bits between I C-BUS interface and ports (BSEL0, BSEL1) b7 b6 C onnection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2 I2C control register (S1D) [Address 00DA16] I2C Control Register B N a m e F u n c t i o n s After reset R W R W R W R W R W R W N o t e W h e n u s i n g p o r t s P 11- P a s I2C B U S i n t e r f a c e t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m C M O S o u t p u t t o N c h a n n e l o p e n d r a i n o u t p u t

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8.6.5 I2C Status Register

The I2C status register (address 00D916) controls the I2C-BUS inter- face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) Bit 0: last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00D716). (2) Bit 1: general call detecting flag (AD0) This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. ✽General call: The master transmits the general call address “00 16” to all slaves. (3) Bit 2: slave address comparison flag (AAS) This flag indicates a comparison result of address data. I In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions.

• The address data immediately after occurrence of a START con- dition matches the slave address stored in the high-order 7 bits of the I 2C address register (address 00D816).
• A general call is received. I In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition.
• When the address data is compared with the I 2C address regis- ter (8 bits consists of slave address and RBW), the first bytes match. I The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00D716). (4) Bit 3: arbitration lost✽ detecting flag (AL) n the master transmission mode, when a device other than the mi- crocomputer sets the SDA to “L,”, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ✽Arbitration lost: The status in which communication as a master is disabled. (5) Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the PIN bit. When detecting the STOP condition in slave, the multi-master I2C-BUS interface interrupt request bit (IR) is set to “0” (interrupt re- quest) regardless of falling of PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in any one of the following conditions.
• Writing “1” to the PIN bit
• Executing a write instruction to the I2C data shift register (address 00D7 16).
• When the ESO bit is “0”
• At reset Note: It takes 8 BCLK cycles or more until PIN bit become “1” after write in- structions are executed to these registers. The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception (6) Bit 5: bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I 2C control register (address 00DA16) is “0” and at reset, the BB flag is kept in the “0” state. (7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00DA16) is “0” in the slave reception mode is selected, the TRX bit is set to “1” ___ (transmit) if the least significant bit (R/W bit) of the address data trans- ___ mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 38 of 124 REJ03B0136-0100Z (8) Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are gener- ated, and also the clocks required for data communication are gen- erated on the SCL. The MST bit is cleared to “0” in one of the following conditions.

• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing function (Note).
• At reset Fig. 8.6.7 I2C Status Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 I2C s t a t u s r e g i s t e r S A d d r e s s D I2C S t a t u s R e g i s t e r 6 , 7 b 7 b 6 S l a v e r e c i e v e m o d e S l a v e t r a n s m i t m o d e M a s t e r r e c i e v e m o d e M a s t e r t r a n s m i t m o d e B N a m e F u n c t i o n s A f t e r r e s e tR W C o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s T R X M S T 0 : B u s f r e e B u s b u s y B u s b u s y f l a g ( B B ) 0 : I n t e r r u p t r e q u e s t i s s u e d N o i n t e r r u p t r e q u e s t i s s u e d I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t P I N 0 : N o t d e t e c t e d D e t e c t e d A r b i t r a t i o n l o s t d e t e c t i n g f l a g A L S e e n o t e 0 : A d d r e s s m i s m a t c h A d d r e s s m a t c h S l a v e a d d r e s s c o m p a r i s o n f l a g A A S S e e n o t e 0 : N o g e n e r a l c a l l d e t e c t e d G e n e r a l c a l l d e t e c t e d G e n e r a l c a l l d e t e c t i n g f l a g A D S e e n o t e 0 : L a s t b i t = “ 0 ” L a s t b i t L a s t r e c e i v e b i t ( L R B ) S e e n o t e N o t e : T h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . I n d e t e r m i n a t e R — R — R — R — R W R W

( S e e n o t e ) ( S e e n o t e ) ( S e e n o t e ) ( S e e n o t e ) Fig. 8.6.8 Interrupt Request Signal Generation Timing SC L PIN IICIRQ Note:The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device.

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8.6.6 START Condition Generation Method

When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes “000 2” and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the high- speed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table. Fig. 8.6.9 START Condition Generation Timing Diagram I2C status register write signal Set time for BB flag Hold timeSetup time SCL SDA BB flag Setup time

8.6.7 STOP Condition Generation Method

When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP condition genera- tion timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table. Fig. 8.6.10 STOP Condition Generation Timing Diagram Table 8.6.2 START Condition/STOP Condition Generation Tim- ing Table Item Setup time (START condition) Setup time (STOP condition) Hold time Set/reset time for BB flag Standard Clock Mode 5.0 µs (20 cycles) 4.25 µs (17 cycles) 5.0 µs (20 cycles) 3.0 µs (12 cycles) High-speed Clock Mode 2.5 µs (10 cycles) 1.75 µs (7 cycles) 2.5 µs (10 cycles) 1.5 µs (6 cycles) Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. I2C status register write signal Reset time for BB flag Hold timeSetup time SCL SDA BB flag

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8.6.8 START/STOP Condition Detect Conditions

The START/STOP condition detect conditions are shown in 8.6.3 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. Fig. 8.6.11 START Condition/STOP Condition Detect Timing Dia- gram Standard Clock Mode 6.5 µs (26 cycles) < SCL release time 3.25 µs (13 cycles) < Setup time 3.25 µs (13 cycles) < Hold time High-speed Clock Mode 1.0 µs (4 cycles) < SCL release time 0.5 µs (2 cycles) < Setup time 0.5 µs (2 cycles) < Hold time Table 8.6.3 START Condition/STOP Condition Detect Conditions Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the num- ber of φ cycles. Hold timeSetup time SCL SDA (START condition) SDA (STOP condition) SCL release time Hold timeSetup time

8.6.9 Address Data Communication

There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective ad- dress communication formats is described below. (1) 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I 2C address register (address 00D816). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00D816) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2). (2) 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I 2C address register (address 00D816). At the time of this comparison, an address com- parison between the RBW bit of the I2C address register (address 00D8 16) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I 2C status register (address 00D916) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00D716), make an address comparison between the sec- ond-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I 2C address register (address 00D816) to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00D816). For the data transmis- sion format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4).

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8.6.10 Example of Master Transmission

An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. ➀ Set a slave address in the high-order 7 bits of the I 2C address register (address 00D816) and “0” in the RBW bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00DB16). ➂ Set “1016” in the I2C status register (address 00D916) and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ➄ Set the address data of the destination of transmission in the high- order 7 bits of the I2C data shift register (address 00D716) and set “0” in the least significant bit. ➅ Set “F016” in the I2C status register (address 00D916) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ➆ Set transmit data in the I 2C data shift register (address 00D716). At this time, an SCL and an ACK clock automatically occurs. ➇ When transmitting control data of more than 1 byte, repeat step ➆ . ➈ Set “D016” in the I2C status register (address 00D916). After this, if ACK is not returned or transmission ends, a STOP condition will be generated.

8.6.11 Example of Slave Reception

An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. ➀ Set a slave address in the high-order 7 bits of the I 2C address register (address 00D816) and “0” in the RBW bit. ➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00DB16). ➂ Set “1016” in the I2C status register (address 00D916) and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ➄ When a START condition is received, an address comparison is made. ➅ •When all transmitted address are“0” (general call): AD0 of the I2C status register (address 00D916) is set to “1”and an interrupt request signal occurs.

• When the transmitted addresses match the address set in ➀ : ASS of the I2C status register (address 00D916) is set to “1” and an interrupt request signal occurs.
• In the cases other than the above: AD0 and AAS of the I2C status register (address 00D916) are set to “0” and no interrupt request signal occurs. ➆ Set dummy data in the I2C data shift register (address 00D716). ➇ When receiving control data of more than 1 byte, repeat step ➆ . ➈ When a STOP condition is detected, the communication ends.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 42 of 124 REJ03B0136-0100Z Fig. 8.6.12 Address Data Communication Format S Slave address A Data A Data A/A PR/W 7 bits “0” 1 to 8 bits 1 to 8 bit s S Slave address A Data A Data AP 7 bits “1” 1 to 8 bits 1 to 8 bit s (1) A master-transmitter transmits data to a slave-receiver S Slave address 1st 7 bits A A Data 7 bits “0” 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address 2nd byte A Data A/ A P 1 to 8 bits S Slave address 1st 7 bits A A 7 bits “0” 8 bits 7 bit s (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address 2nd byte Data 1 to 8 bits Sr Slave address 1st 7 bits A Data A P 1 to 8 bits“1” (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition P : STOP condition A : ACK bit R/W : Read/Write bit Sr : Restart condition From master to slave From slave to master R/W R/W R/W R/W

8.6.12 Precautions when using multi-master

(1) Read-modify-write instruction The precautions when the raead-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below.

• I2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. 2C address register (S0D) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because hardware changes the read/write bit (RBW) at the above timing. 2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. 2C control register (S1D) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because hardware changes the bit counter (BC0–BC2) at the above timing. 2C clock control register (S2) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure us- ing multi-master ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➄ ). LDA — (Taking out of slave address value) SEI (Interrupt disabled) BBS 5,S1,BUSBUSY (BB flag confirming and branch process) BUSFREE: STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of START condition generating) CLI (Interrupt enabled) BUSBUSY: CLI (Interrupt enabled) ➁ Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing the slave address value to the I 2C data shift register. ➂ Use “LDM” instruction for setting trigger of START condition gener- ating. ➃ Write the slave address value of above ➁ and set trigger of START condition generating of above ➂ continuously shown the above procedure example. ➄ Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 43 of 124 REJ03B0136-0100Z (3) RESTART condition generating procedure ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➅ .) Execute the following procedure when the PIN bit is “0.” LDM #$00, S1 (Select slave receive mode) LDA — (Taking out of slave address value) SEI (Interrupt disabled) STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of RESTART condition generating) CLI (Interrupt enabled) ➁ Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. ➂ The SCL pin is released by writing the slave address value to the I 2C data shift register. Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing. ➃ Use “LDM” instruction for setting trigger of RESTART condition gen- erating. ➄ Write the slave address value of above ➂ and set trigger of RE- START condition generating of above ➃ continuously shown the above procedure example. ➅ Disable interrupts during the following two process steps:

• Writing of slave address value
• Trigger of RESTART condition generating (4) STOP condition generating procedure ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➃ .) SEI (Interrupt disabled) LDM #$C0, S1 (Select master transmit mode) NOP (Set NOP) LDM #$D0, S1 (Trigger of STOP condition generating) CLI (Interrupt enabled) ➁ Write “0” to the PIN bit when master transmit mode is select. ➂ Execute “NOP” instruction after setting of master transmit mode. Also, set trigger of STOP condition generating within 10 cycles af- ter selecting of master trasmit mode. ➃ Disable interrupts during the following two process steps:
• Select of master transmit mode
• Trigger of STOP condition generating (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not ex- ecute an instruction to set the MST and TRX bits to “0” from “1” si- multaneously when the PIN bit is “1.” It is because it may become the same as above. (6) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem.

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8.7 PWM OUTPUT FUNCTION

This microcomputer is equipped with two 14-bit PWMs (DA1, DA2) and six 8-bit PWMs (PWM0–PWM5). DA1 and DA2 have a 14-bit resolution with the minimum resolution bit width of 0.25 µs and a repeat period of 4096 µs (for f(XIN) = 8 MHz). PWM0–PWM5 have the same circuit structure and an 8-bit resolution with minimum reso- lution bit width of 4 µs and repeat period of 1024 µs (for f(XIN) = 8 MHz). Figure 8.7.1 shows the PWM block diagram. The PWM timing gen- erating circuit applies individual control signals to DA1, DA2 and PWM0–PWM5 using f(X IN) divided by 2 as a reference signal.

8.7.1 Data Setting

When outputting DA1, first set the high-order 8 bits to the DA1-H register (address 00CE 16), then the low-order 6 bits to the DA1-L register (address 00CF16). When outputting DA1, first set the high- order 8 bits to the DA2-H register (address 024E16), then the low- order 6 bits to the DA2-L register (address 024F16). When outputting PWM0–PWM5, set 8-bit output data to the PWMi register (i means 0 to 5; addresses 00D0 16 to 00D416, 00F616).

8.7.2 Transferring Data from Registers to PWM

Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. Also, data transfer from the DA1 register (addresses 00CE 16 and 00CF 16) to the 14-bit PWM circuit is executed at writing data to the DA1-L register (address 00CF16). Reading from the DA1-H register (address 00CE16) means reading this transferred data. Data trans- fer from the DA2 register (addresses 024E16 and 024F16) to the 14- bit PWM circuit is executed at writing data to the DA2-L register (ad- dress 024F 16). Reading from the DA2-H register (address 024E16) means reading this transferred data. Accordingly, it is possible to confirm the data being output from the DAi (i = 1, 2) output pin by reading the DAi (i = 1, 2) register.

8.7.3 Operating of 8-bit PWM

The following explains PWM operation. First, set the bit 0 of PWM output control register 1 (address 00D5 16) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM5 are also used as pins P0 0–P0 5, respectively. For PWM0–PWM5, set the corresponding bits of the ports P0 direction register to “1” (output mode). And select each output polarity by bit 3 of PWM output control register 2 (address 00D6 16). Then, set bits 2 to 7 of PWM output control register 1 to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is com- posed of 256 (2 8) segments. The 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 8.7.2 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the con- tents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH output cannot be output, i.e. 256/256.

8.7.4 Operating of 14-bit PWM

For DA1, as with 8-bit PWM, set the bit 0 of PWM output control register 1 (address 00D5 16) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. Next, se- lect the output polarity by bit 2 of PWM output control register 2 (ad- dress 00D6 16). Then, the 14-bit PWM outputs from the DA1 output pin by setting bit 1 of PWM output control register 1 to “0” (at reset, this bit already set to “0” automatically) to select the DA1 output. For DA2 as with DA1, set the bit 0 of PWM output control register 1 (address 00D5 16) to “0” (at reset, bit 0 is already set to “0” automati- cally), so that PWM count source is supplied. Next, select the output polarity by bit 4 of PWM output control register 2 (address 00D6 16). Then, the 14-bit PWM outputs from the DA2 output pin by setting bit 5 of PWM output control register 1 to “0” (at reset, this bit already set to “0” automatically) to select the DA2 output. The output example of the 14-bit PWM is shown in Figure 8.7.3. The 14-bit PWM divides the data of the DAi latch (i = 1, 2) into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data “D H .” A HIGH area with a length t ✕ DH (HIGH area of funda- mental waveform) is output every short area of “t” = 256τ = 64 µs (τ is the minimum resolution bit width of 250 ns). The HIGH level area increase interval (tm ) is determined with the low-order 6-bit data “DL.” The HIGH are of smaller intervals “tm ” shown in Table 5 is longer by t than that of other smaller intervals in PWM repeat period “T” = 64t. Thus, a rectangular waveform with the different HIGH width is output from the DAi pins (i = 1, 2). Accordingly, the PWM output changes by τ unit pulse width by changing the contents of the DAi-H and DAi-L registers (i = 1, 2). A length of entirely HIGH cannot be output, i. e. 256/256.

8.7.5 Output after Reset

At reset, the output of ports P00–P05 and P17 are in the high-imped- ance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is unde- fined until setting the PWM register. LSB Table 8.7.1 Relation Between the Low-order 6-bit Data and High- level Area Increase Interval Area Longer by τ than That of Other tm (m = 0 to 63) Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 Low-order 6 bits of Data 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 45 of 124 REJ03B0136-0100Z Fig. 8.7.1 PWM Block Diagram PWM 1 register (Address 00D116) 1/2XIN PWM timing generating circuit PWM register (Address 00D016) b 8-bit PWM circuit PN3 P00 P W D0 0 P W M P01 P W D0 1 P W M P02 P W D0 2 P W M P03 P W D0 3 P W M P04 PW6 D0 4 P W M P05 PW7 D0 5 P W M P W M 2 r e g i s t e r A d d r e s s D P W M 3 r e g i s t e r A d d r e s s D P W M 4 r e g i s t e r A d d r e s s D P W M 5 r e g i s t e r A d d r e s s F D a t a b u s I n s i d e o f i s a s s a m e c o n t e n t s w i t h t h e o t h e r s S e l e c t i o n g a t e : C o n n e c t e d t o b l a c k s i d e a t r e s e t P a s s g a t e P W : P W M m o d e r e g i s t e r 1 [ a d d r e s s 0 0 D 51 P N : P W M m o d e r e g i s t e r a d d r e s s D D P o r t P d i r e c t i o n r e g i s t e r a d d r e s s C P P o r t P r e g i s t e r a d d r e s s C P P o r t P r e g i s t e r a d d r e s s C P P o r t P r e g i s t e r a d d r e s s C PW 0 14-bit PWM circuit PN4 P17 PW1 MSB DA2-H register (Address 024E16) DA2 latch (14 bits) D A L r e g i s t e r S e e n o t e A d d r e s s L S B 6 14 DA2 b7 b0 N ote: DAi-L register is also used as low-order 6 bits of DAi latch (i = 1, 2). 14-bit PWM circuit P N 2 P P W MSB DA1-H register (Address 00CE16) D A l a t c h b i t s D A L r e g i s t e r S e e n o t e A d d r e s s C L S B 6 14 D A b7 b

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 46 of 124 REJ03B0136-0100Z Fig. 8.7.2 PWM Timing (a) Pulses showing the weight of each bit 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 112 144 176 208 240 104 120 136 152 168 184 200 216 232 248 160 224 192 Bit 7 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 128 Bit 0 PWM output t = 4 µs T = 1024 µs f(X IN ) = 8 MHz (b) Example of 8-bit PWM t (0) (1) (24) FF (255) T = 256 t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 47 of 124 REJ03B0136-0100Z Fig. 8.7.3 14-bit PWM Timing (f(XIN) = 8 MHz) 0.25 µs b 7b 0b 6b 5b 4b 3b 2b 1 0 0010110 b 1 3b 6 00 010110 b0b 5 101000 Set “2C16” to DAi-H register. [ D A i - H r e g i s t e r D H A t w r i t i n g o f D A i - L b 0b 6b 5b 4b 3b 2b 1 010100 Set “2816” to DAi-L register. [DAi-L register] D L A t w r i t i n g o f D A i - L These bits decide HIGH level area of fundamental waveform. T h e s e b i t s d e c i d e s m a l l e r i n t e r v a l “ t m ” i n w h i c h H I G H l e v a l a r e a i s H I G H l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m τ Minimum resolution bit width 0.25 µs High-order 8-bit value of DAi latch✕H I G H l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m FF 00 D3FE FD … D6 D4 02 01D5 14-bit PWM output 8-bit counter 0.25 µs✕ 44 FF 00 D3FE FD D6 D4 02 01D5 14-bit PWM output 8 - b i t c o u n t e r 0.25 µs✕ 45 Fundamental waveform W a v e f o r m o f s m a l l e r i n t e r v a l “ t m ” s p e c i f i e d b y l o w - o r d e r 6 b i t s F u n d a m e n t a l w a v e f o r m o f s m a l l e r i n t e r v a l t m w h i c h i s n o t s p e c i f i e d b y l o w o r d e r b i t s i s n o t c h a n g e d 1 4 - b i t P W M o u t p u t Low-order 6-bit output of DAi latch 0 . 2 5 µs✕ 4 4 τ = 0.25 µs T = 4096 µs Repeat period t0 t1 t2 t3 t4 t5 t59 t6 0 t6 1 t6 2 t63 [ D A i l a t c h ] …… … b 7 2C 2B 2A 03 02 01 00 2C 2B 2A 03 02 01 00…… N o t e : i i n d i c a t e s 0 o r 1 .

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 48 of 124 REJ03B0136-0100Z Fig. 8.7.4 PWM Output Control Register 1 Fig. 8.7.5 PWM Output Control Register 2 b7b6 b5b4b3 b2b1b0 PWM output control register 2 (PN) [Address 00D6 B A f t e r r e s e t RW P W M O u t p u t C o n t r o l R e g i s t e r 2 0 , 1 N a m e Functions D A 1 o u t p u t p o l a r i t y s e l e c t i o n b i t P N 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y P W M o u t p u t p o l a r i t y s e l e c t i o n b i t P N F i x t h e s e b i t s t o “ 0 . ” D A 2 o u t p u t p o l a r i t y s e l e c t i o n b i t P N 0 : Output LOW 1 : Output HIGH 6 , 7 0F i x t h e s e b i t s t o “ 0 . ” 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y 16] R RW RW RW RW 0000

5 P 17/ D A 2 o u t p u t

s e l e c t i o n b i t P N 0 : P 17 D A 0 RW W b7b 6 b 5b 4b 3 b 2b 1b0 P W M o u t p u t c o n t r o l r e g i s t e r 1 ( P W ) [ A d d r e s s 0 0 D 5 B After reset RW PWM Output Control Register 1 Name F u n c t i o n s D A1, D A2, PW M count source selection bit (PW 0) 0 : C o u n t s o u r c e s u p p l y C o u n t s o u r c e s t o p P 00/ P W M 0 o u t p u t s e l e c t i o n b i t P W 0 : P 00 o u t p u t P W M o u t p u t P 01/ P W M 1 o u t p u t s e l e c t i o n b i t P W 0: P01 output 1: PWM1 output P02/PWM2 output selection bit (PW4) 0 : P 02 o u t p u t P W M o u t p u t

5 P03/PWM3 output

selection bit (PW5) 0 : P 03 o u t p u t P W M o u t p u t

6 P04/PWM4 output

selection bit (PW6) 0 : P 04 o u t p u t P W M o u t p u t D A 1 o u t p u t / P 35 s e l e c t i o n b i t P W 0 : D A 1 o u t p u t P o u t p u t

7 P05/PWM5 output

selection bit (PW7) 0 : P 05 o u t p u t P W M o u t p u t 16] RW RW RW RW RW RW RW RW

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 49 of 124 REJ03B0136-0100Z

8.8 A-D CONVERTER

8.8.1 A-D Conversion Register (AD)

A-D conversion reigister is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion.

8.8.2 A-D Control Register (ADCON)

The A-D control register controls A-D conversion. Bits 2 to 0 of this register select analog input pins. When these pins are not used as anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D conversion completion bit, A-D conversion is started by writing “0” to this bit. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Bit 4 controls connection between the resistor ladder and V CC . When not using the A-D converter, the resistor ladder can be cut off from the internal VCC by setting this bit to “0,” accordingly providing low- power dissipation.

8.8.3 Comparison Voltage Generator (Resistor

Ladder) The voltage generator divides the voltage between VSS and VCC by 256, and outputs the divided voltages to the comparator as the refer- ence voltage Vref.

8.8.4 Channel Selector

The channel selector connects an analog input pin, selected by bits 2 to 0 of the A-D control register, to the comparator.

8.8.5 Comparator and Control Circuit

The conversion result of the analog input voltage and the reference voltage “V ref” is stored in the A-D conversion register. The A-D con- version completion bit and A-D conversion interrupt request bit are set to “1” at the completion of A-D conversion. Fig. 8.8.1 A-D Converter Block Diagram A-D control register (address 00DF16) A - D c o n t r o l c i r c u i t D a t a b u s Sw itch tree A-D conversion interrupt request R esistor ladder C ompa- rator C h a n n e l s e l e c t o r A - D c o n v e r s i o n r e g i s t e r A-D 1 A - D 2 A-D 3 A - D 4 (address 00DE 16) b 7 b 0 VSS VCC A-D 5 A - D 6 A - D 7 A-D 8

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 50 of 124 REJ03B0136-0100Z Fig. 8.8.2 A-D Control Register A - D C o n t r o l R e g i s t e r b 7 b6 b 5 b 4 b 3 b 2 b 1 b 0 A-D control register (ADCON) [Address 00DF16] B A f t e r r e s e tRW t o A n a l o g i n p u t p i n s e l e c t i o n b i t s A D I N t o A D I N N a m eF u n c t i o n s b 2 b 1 b 0 A D A D A D A D A D A D A D A D

4 VCC connection selection bit

(ADVREF) 0 : O F F O N 6 N othing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. RW RW

3 A - D c o n v e r s i o n c o m p l e t i o n

b i t A D S T R 0 : C o n v e r s i o n i n p r o g r e s s C o n v e r t i o n c o m p l e t e d 1 RW 7 F i x t h i s b i t t o “ 0 . ” RW I n d e t e r m i n a t e 5 F i x t h i s b i t t o “ 0 . ” RW0

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 51 of 124 REJ03B0136-0100Z Note: VREF indicates the reference voltage (= Vcc). Fig. 8.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion

8.8.6 Conversion Method

➀ Set the A-D conversion interrupt request bit to “0” (even when A- D conversion is started, the A-D conversion interrupt reguest bit is not set to “0” automatically). ➁ When using A-D conversion interrupt, enable interrupts by setting A-D conversion interrupt enable bit to “1” and setting the interrupt disable flag to “0.” ➂ Set the V CC connection selection bit to “1” to connect VCC to the resistor ladder. ➃ Select analog input pins by the analog input selection bit of the A-D control register. ➄ Set the A-D conversion completion bit to “0.” This write operation starts the A-D conversion. Do not read the A-D conversion regis- ter during the A-D conversion. ➅ Verify the completion of the conversion by the state (“1”) of the A-D conversion completion bit, the state (“1”) of A-D conversion interrupt reguest bit, or the occurrence of an A-D conversion in- terrupt. ➆ Read the A-D conversion register to obtain the conversion re- sults. Note :When the ladder resistor is disconnect from VCC , set the VCC connec- tion selection bit to “0” between steps ➅ and ➆ .

8.8.7 Internal Operation

When the A-D conversion starts, the following operations are auto- matically performed. ➀ The A-D conversion register is set to “00 16.” ➁ The most significant bit of the A-D conversion register becomes “1, ” and the comparison voltage “Vref” is input to the comparator. At this point, Vref is compared with the analog input voltage “VIN .” ➂ Bit 7 is determined by the comparison results as follows. When V ref < VIN : bit 7 holds “1” When V ref > VIN : bit 7 becomes “0” With the above operations, the analog value is converted into a digi- tal value. The A-D conversion terminates in a maximum of 50 ma- chine cycles (8.5 µs at f(XIN) = 8 MHz) after it starts, and the conver- sion result is stored in the A-D conversion register. An A-D conversion interrupt request occurs at the same time as A-D conversion completion, the A-D conversion interrupt request bit be- comes “1.” The A-D conversion completion bit also becomes “1.” Table 8.8.1 Expression for V ref and VREF A-D conversion register contents “n” (decimal notation) 1 to 255 Vref (V) VREF VREF 512 VREF VREF VREF 512 VREF VREF VREF VREF 512 VREF VREF VREF VREF 512 VREF 256 12 3 45678 1 0000000 12 100000 10000001 1234567 1 –±± 00000 000 Contents of A-D conversion register Reference voltage (Vref) [V] 0A-D conversion start 1st comparison start 3rd comparison start 8th comparison start 2nd comparison start Digital value corresponding to analog input voltage. A-D conversion completion (8th comparison completion) ±± ± : Value determined by mth (m = 1 to 8) resultm VREF 256 ✕ (n – 0.5)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 52 of 124 REJ03B0136-0100Z [LSB] [LSB]

8.8.8 Definition of A-D Conversion Accuracy

The definition of A-D conversion accuracy is described below (refer to Figure 8.8.4). (1) Relative Accuracy

• Zero transition error (V0T) The deviation of the input voltage at which A-D conversion output data changes from “0” to “1,” from the corresponding ideal A-D conversion characteristics between 0 and V REF .
• Non-linearity error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between V 0 and V254. 1LSB V0T = (VREF – 3/2 ✕ VREF /256) – V254 1LSB VFST = Non-linearity error = [LSB] [LSB]
• EDifferential non-linearity error The deviation of the input voltage required to change output data by “1,” from the corresponding ideal A-D conversion characteris- tics between 0 and V REF . (2) Absolute Accuracy
• EAbsolute accuracy error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between 0 and V REF . Vn – (1LSB ✕ n + V0) 1LSB [LSB]Differential non-linearity error = (Vn+1 – Vn) – 1LSB 1LSB Absolute accuracy error = 1LSB A with respect to absolute accuracy = 1LSB with respect to relative accuracy = Note: The analog input voltage “Vn” at which A-D conversion output data changes from “n” to “n + 1” (n ; 0 to 254) is as follows (refer to Figure 8.8.4) : V254 – V0 254 VREF 256 [V] [V] Fig. 8.8.4 Definition of A-D Conversion Accuracy
• Full-scale transition error (VFST ) The deviation of the input voltage at which A-D conversion output data changes from “255” to “254,” from the corresponding ideal A- D conversion characteristics between 0 and V REF . Vn – 1LSBA ✕ (n + 1/2) 1LSB A Output code Analog input voltage (mV) 20 40 80 100 120 140 160 180 200 220 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 + 2LSB – 2LSB Absolute accuracy Limitless resolution A-D conversion characteristics Ideal A-D conversion characteristics

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 53 of 124 REJ03B0136-0100Z Fig. 8.9.2 ROM Correction Enable Register Fig. 8.9.1 ROM Correction Address Registers

8.9 ROM CORRECTION FUNCTION

This can correct program data in ROM. Up to 3 addresses can be corrected, a program for correction is stored in the ROM correction vector in RAM as the top address. The ROM correction vectors are 3 vectors. Vector 1 : address 02C0 Vector 2 : address 02E016 Vector 3 : address 030016 Set the address of the ROM data to be corrected into the ROM cor- rection address register. When the value of the counter matches the ROM data address in the ROM correction vector as the top address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register. Notes 1:Specify the first address (op code address) of each instruction as the ROM correction address. 2:Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3:Do not set the same ROM correction address to vectors 1 to 3. 021716ROM correction address 1 (high-order) 0 2 1 81 6R O M c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) 0 2 1 91 6R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) 0 2 1 A1 6R O M c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) 0 2 1 C 1 6R O M c o r r e c t i o n a d d r e s s 3 ( h i g h - o r d e r ) 0 2 1 D 1 6R O M c o r r e c t i o n a d d r e s s 3 ( l o w - o r d e r ) b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) [ A d d r e s s 0 2 1 B1 B After reset RW R O M C o r r e c t i o n E n a b l e R e g i s t e r

0 V e c t o r 1 e n a b l e b i t ( R C R 0 )

0 : D i s a b l e d E n a b l e d 0 RW

1 Vector 2 enable bit (RCR 1) 0: Disabled

1: Enabled 0 RW t o F i x t h e s e b i t s t o “ 0 . ” 0 RW 0000

2 V e c t o r 3 e n a b l e b i t ( R C R 2 ) 0

E n a b l e d 0 RW

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 54 of 124 REJ03B0136-0100Z

8.10 OSD FUNCTIONS

This OSD function can display the following 3 types:

• “Block display ” (24 characters ✕ 2 lines)
• “SPRITE display” (display only a character) or “Raster patterning display” (display a character on entire screen side by side)
• “Raster flat display” (coloring entire screen) The above displays can be overlapped at the same time. The priority is : SPRITE display > Block display > Raster flat display or Block display > Raster patterning display > Raster flat display Note that raster patterning display and SPRITE display cannot be used simultaneously. Figure 8.10.2 shows the block diagram of OSD circuit, Figure 8.10.3 shows the configuration of OSD character display area, Figure 8.10.4 shows the OSD control register. Fig. 8.10.1 Display Types of OSD Function O S D F u n c t i o n DD ii ss pp ll aa yy TT yy pp ee DD ii ss pp ll aa yy MM oo dd ee S P R I T E d i s p l a y s e e n o t e B l o c k d i s p l a y O S D m o d e B U T T O N m o d e DD ii ss pp ll aa yy LL ee vv ee ll DD ii ss pp ll aa yy PP rr ii oo rr ii tt yy T o p M i d d l e A l l b o r d e r e d S h a d o w b o r d e r e d II nn tt ee rr rr uu pp tt RR ee qq uu ee ss tt S P R I T E O S D i n t e r r u p t O S D i n t e r r u p t B o t t o m N o t e R a s t e r p a t t e r n i n g d i s p l a y a n d S P R I T E d i s p l a y c a n n o t b e u s e d s i m u l t a n e o u s l y R a s t e r f l a t d i s p l a y A l l b o r d e r e d S h a d o w b o r d e r e d R a s t e r p a t t e r n i n g d i s p l a y S e e n o t e T o p M i d d l B o t t o m S e e n o t e

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 55 of 124 REJ03B0136-0100Z Fig. 8.10.2 Block Diagram of OSD Circuit Display ocsillation circuit O S C 1 H S Y N C VS Y N C OSD RAM 15 bits ✕ 24 characters ✕ 2 lines D a t a b u s OSD ROM 16 dots ✕ 20 dots ✕ 381 characters Shift register M a i n c l o c k XI N C l o c k f o r O S D O u t p u t c i r c u i t R G B O S D c o n t r o l c i r c u i t OUT1 Control registers for OSD O S D p o r t c o n t r o l r e g i s t e r I n t e r r u p t i n p u t p o l a r i t y r e g i s t e r B l o c k H r e g i s t e r B l o c k i V r e g i s t e r S P R I T E c o n t r o l r e g i s t e r S P R I T E H r e g i s t e r S P R I T E V r e g i s t e r C o l o r r e g i s t e r i O S D c o n t r o l r e g i s t e r O S D I O p o l a r i t y r e g i s t e r B l o c k i c o n t r o l r e g i s t e r L e f t b o r d e r r e g i s t e r R i g h t b o r d e r r e g i s t e r T o p b o r d e r r e g i s t e r B o t t o m b o r d e r r e g i s t e r (Address 00CB16) (Address 00CD16) (Address 00E016) (Addresses 00E116, 00E216) (Address 00E316) (Address 00E416) (Address 00E516) (Addresses 00E616 to 00E916, 00EC 16 to 00EF16) (Address 00EA16) (Address 00EB16) (Addresses 00F916, 00FA16) (Address 024016) (Address 024116) (Address 024516) (Address 024616) OUT2

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 56 of 124 REJ03B0136-0100Z Fig. 8.10.3 Configuration of OSD Character Display Area 16 dots 2 0 d o t s 1 6 d o t s 2 0 d o t s

• B l o c k D i s p l a y ( O S D M o d e ) • B l o c k D i s p l a y ( B U T T O N M o d e )
• S P R I T E D i s p l a y : BUTTON display area (displayed only in BUTTON mode) 2 d o t s 2 d o t s Fig. 8.10.4 OSD Control Register b3 b2 (See notes 3 and 4) 0 0 : Standard 0 1 : Standard + 1TOSC 1 0 : Standard + 2TOSC 1 1 : Standard + 3TOSC b 7b 6b 5b 4b 3b 2b 1b 0 OSD control register (OC) [Address 00EA16] BN a m e F u n c t i o n s After resetR W O S D C o n t r o l R e g i s t e r

0 OSD control bit

(OC0) (See note 1) 0 : A l l - b l o c k s d i s p l a y O F F A l l b l o c k s d i s p l a y O N

1 B o r d e r t y p e s e l e c t i o n

b i t O C 0 : All bordered 1 : Shadow bordered (See note 2) 2 , 3 0 4W i n d o w c o n t r o l b i t O C Window horizontal position minute adjustment bit (OC2, OC3) RW RW RW RW 6R a s t e r c o l o r O U T 1 c o n t r o l b i t O C 0 : W i n d o w O F F W i n d o w O N 0R W

5 S c a n m o d e s e l e c t i o n

b i t O C 0R W0 : N o r m a l s c a n m o d e B i s c a n m o d e S e e n o t e Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC . 2 : Shadow border is output at right and bottom side of the font. 3 : TOSC = OSD oscillation cycle 4 : These bits are vallid for both left border and right border (for detail, refer to “(8) Window Function.”) 5 : When setting to bi-scan mode, connect LC between pins OSC1 and OSC2. 0 : N o o u t p u t O u t p u t 7R a s t e r c o l o r O U T 2 c o n t r o l b i t O C 0R W0 : N o o u t p u t O u t p u t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 57 of 124 REJ03B0136-0100Z (1) Clock for OSD As a clock for display to be used for OSD, it is possible to select one of the following 3 types.

• Main clock from the pins X IN and XOUT
• Clock from the LC or RC oscillator supplied from the pins OSC1 and OSC2
• Clock from the ceramic resonator or the quartz-crystal oscillator from the pins OSC1 and OSC2 The clock for display to be used for OSD can be selected by bits 0 and 1 of the interrupt input polarity register (address 00CD 16). And besides, when selecting main clock, set the oscillation frequency to 8 MHz. Fig. 8.10.5 Interrupt Input Polarity Register b7 b 6 b5 b 4 b 3 b 2 b 1 b 0 I n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( I P ) [ A d d r e s s 0 0 C D 1 b N a m e F u n c t i o n A f t e r r e s e t R W I n t e r r u p t I n p u t P o l a r i t y R e g i s t e r I N T 1 p o l a r i t y s w i t c h b i t P O L 0 : Positive polarity 1 : Negative polarity 6 , 7

s w i t c h b i t P O L I N T 3 p o l a r i t y s w i t c h b i t P O L F i x t h e s e b i t s t o “ 0 . ” 0 WR 0 WR 0 , 1 O S D c l o c k s e l e c t i o n b i t s O C G O C G Since the main clock is used as the clock for OSD, the oscillation frequency is limited. Because of this, the character size in width (horizonal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P3 and P34 respectively. The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode.

• a ceramic resonator only for OSD and a feedback resistor
• a quartz-crystal oscillator only for OSD and a feedback resistor The clock for OSD is supplied by connecting RC or LC across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. F u n c t i o n O S D o s c i l l a t i o n f r e q u e n c y f XI N ) The clock for OSD is supplied by connecting LC across the pins OSC1 and OSC2. In the bi-scan mode, be sure to set this. F i x t h i s b i t t o “ 0 . ” 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 58 of 124 REJ03B0136-0100Z (2) Scan mode This microcomputer has the bi-scan mode for corresponding to HSYNC of double-speed frequency. In the bi-scan mode, the vertical start display position and the vertical dot size is two times as compared with the normal scan mode. The scan mode is selected by bit 5 of the OSD control register (refer to Figure 8.10.3). Parameter Bit 5 of OSD Control Register Vertical Display Start Position Vertical Dot Size Table 8.10.1 Setting for Scan Mode Normal Scan Value of vertical position register ✕ 1H OSC ✕ 1H 2TOSC ✕ 2H 3TOSC ✕ 3H Bi-Scan Value of vertical position register ✕ 2H 1TOSC ✕ 2H 2TOSC ✕ 4H 3TOSC ✕ 6H Scan Mode Notes 1: TOSC = OSD oscillation cycle 2: H = HSYNC

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 59 of 124 REJ03B0136-0100Z (3) OSD input/output pin control The OSD output pins R, G, B, OUT1 and OUT2 can also function as ports P52, P53, P54, P55, P10 respectively. Switch either OSD out- put function or port function by the OSD port control register (ad- dress 00CB 16). The input polarity of the HSYNC , VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the OSD I/O polarity register (address 00EB 16). Set a bit to “0” to specify positive polarity; Fig. 8.10.6 OSD I/O Polarity Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 O S D I O p o l a r i t y r e g i s t e r O P C A d d r e s s E B N ame F u n c t i o n s A f t e r r e R W O S D I O P o l a r i t y R e g i s t e r

0 H S

Y N C i n p u t p o l a r i t y s w i t c h b i t O P C 0 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t 1 0 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t

2 R / G / B o u t p u t p o l a r i t y s w i t c h

b i t O P C 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t 3 0 VS Y N C i n p u t p o l a r i t y s w i t c h b i t O P C R W R W R W R W

4 O U T 2 o u t p u t p o l a r i t y

s w i t c h b i t O P C 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

5 R a s t e r c o l o r R c o n t r o l

b i t O P C 0 : N o o u t p u t O u t p u t

6 R a s t e r c o l o r G c o n t r o l b i t

O P C

7 R a s t e r c o l o r B c o n t r o l b i t

O P C 0 : N o o u t p u t O u t p u t R W R W R W R W O U T 1 o u t p u t p o l a r i t y s w i t c h b i t O P C 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t 0 : N o o u t p u t O u t p u t set it to “1” to specify negative polarity. Figure 8.10.6 shows the OSD I/O polarity register and Figure 8.10.7 shows the OSD port control register. Fig. 8.10.7 OSD Port Control Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 O S D p o r t c o n t r o l r e g i s t e r ( P F ) [ A d d r e s s 0 0 C B1 b N a m e F u n c t i o n s A f t e r r e s e t R W O S D P o r t C o n t r o l R e g i s t e r 0 , 10 R WF i x t h e s e b i t s t o “ 0 ” 2 0 : R s i g n a l o u t p u t P o r t P o u t p u t

3 P o r t P 53

s e l e c t i o n b i t P S E L 0 : G s i g n a l o u t p u t P o r t P o u t p u t

4 P o r t P 54

s e l e c t i o n b i t P S E L 0 : B s i g n a l o u t p u t P o r t P o u t p u t

5 P o r t P 55

s e l e c t i o n b i t P S E L 0 : O U T 1 s i g n a l o u t p u t P o r t P o u t p u t

6 P o r t P 10

s e l e c t i o n b i t O U T S E L 0 : P o r t P 10 s i g n a l o u t p u t O U T o u t p u t s e l e c t i o n b i t P S E L

70 R WF i x t h i s b i t t o “ 0 ”

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 60 of 124 REJ03B0136-0100Z Fig. 8.10.8 Block i Control Register (i = 1, 2) b 2b 1b 0 D i s p l a y m o d e ✕ 0 0 D i s p l a y O F F 0 0 1 O S D m o d e n o b o r d e r 0 1 0 B U T T O N m o d e n o b o r d e r 1 0 1 O S D m o d e b o r d e r 1 1 0 B U T T O N m o d e b o r d e r b7 b6 b5b4 b3 b2b1 b0 B l o c k i c o n t r o l r e g i s t e r ( B i C ) ( i = 1 , 2 ) [ A d d r e s s e s 0 0 F 91 6, 0 0 F A1 BName Functions After reset R W B l o c k i C o n t r o l R e g i s t e r t o D i s p l a y m o d e s e l e c t i o n b i t s B i C t o B i C Indeterm inate 3, 4 D o t s i z e s e l e c t i o n b i t B i C B i C RW RW N o t e s 1 : TO S C = O S D o s c i l l a t i o n c y c l e H H S Y NC b 4b 3 D o t s i z e 0 0 1 TO S C ✕ H 0 1 D o n o t s e t 1 0 2 TO S C ✕ H 1 1 3 TO S C ✕ H t o 0N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e I n d e t e r m i n a t e

8.10.1 Block Display

There are 2 display modes and they are selected by a block unit. The display modes are selected by bits 0 to 2 of block i control register (i = 1, 2). The features of each mode are described below. There are an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Table 8.10.2 Features of Each Display Style of Block Display 1 s c r e e n : 8 k i n d s ( p e r c h a r a c t e r u n i t ) K i n d s o f c h a r a c t e r s i z e s D o t s i z e A t t r i b u t e C h a r a c t e r f o n t c o l o r i n g C h a r a c t e r b a c k g r o u n d c o l o r i n g N o t e s 1 : TO S C = O S D o s c i l l a t i o n c y c l e H H S Y N C T h e S P R I T E d i s p l a y i s n o t e f f e c t e d b y t h e w i n d o w f u n c t i o n O S D m o d e O n s c r e e n d i s p l a y m o d e B l o c k d i s p l a y B U T T O N m o d e B U T T O N d i s p l a y m o d e D i s p l a y s t y l e P a r a m e t e r N u m b e r o f d i s p l a y c h a r a c t e r s 2 c h a r a c t e r s l i n e s D o t s t r u c t u r e K i n d s o f c h a r a c t e r s 3 8 1 k i n d s B o r d e r ( p e r b l o c k u n i t ) 3 k i n d s TO S C ✕ H TO S C ✕ H TO S C ✕ H p e r b l o c k u n i t S e e n o t e s d o t s C h a r a c t e r d i s p l a y a r e a : ( 1 6 d o t s + 4 d o t s ) ( 2 0 d o t s + 4 d o t s ) 1 s c r e e n : 8 k i n d s ( p e r c h a r a c t e r u n i t ) O S D o u t p u t R , G , B D i s p l a y e x p a n s i o n m u l t i l i n e d i s p l a y ) P o s s i b l e D i s p l a y p o s i t i o nH o r i z o n t a l : 6 4 l e v e l s , V e r t i c a l : 2 5 5 l e v e l s D i s p l a y m o d e I B o r d e r p e r b l o c k u n i t I B U T T O N d i s p l a y p e r c h a r a c t e r u n i t I B l o c k s h a d o w d i s p l a y p e r c h a r a c t e r u n i t R a s t e r c o l o r i n gP o s s i b l e ( p e r s c r e e n u n i t ) O t h e r fu n c t i o n s I C o r r e s p o n d i n g t o b i s c a n I W i n d o w f u n c t i o n S e e n o t e d o t s

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 61 of 124 REJ03B0136-0100Z (1) Display position The display positions of characters are specified by a block. There are 2 blocks, blocks 1 and 2. Up to 24 characters can be displayed in each block (refer to “(3) Memory for OSD”). The display position of each block can be set in both horizontal and vertical directions by software. The display start position in the horizontal direction can be set for all blocks in common in 64-step display positions in units of 4T OSC (TOSC = OSD oscillation cycle). The display start position in the vertical direction for each block can be set in 255-step display positions in units of 1 H ( H = HSYNC cycle). Blocks are displayed in conformance with the following rules:

• When the display position of block 1 is overlapped with block 2 (Figure 8.10.9 (b)), block 1 is displayed on the front.
• When another block display position appears while one block is . displayed (Figure 8.10.9 (c)), the block with a larger set value as the vertical display start position is displayed. For the display position of SPRITE display, it is necessary to set in- dependently, and it is possible to set display positions independently. Refer to “8.10.2 SPRITE Display.” Fig. 8.10.9 Display Position B H P B2VP B l o c k 1 Block 2 ( a ) E x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d B H P B 1 V P = B 2 V P B l o c k 1 ( b ) E x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 ( B l o c k 2 i s n o t d i s p l a y e d ) B H P B1VP B2VP ( c ) E x a m p l e w h e n b l o c k 2 o v e r l a p s i n p r o c e s s o f b l o c k 1 B l o c k 1 B l o c k 2 N o t e s 1 : B 1 V P o r B 2 V P i n d i c a t e s t h e v e r t i c a l d i s p l a y s t a r t p o s i t i o n o f d i s p l a y b l o c k s 1 a n d 2 . B H P i n d i c a t e s t h e h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n o f d i s p l a y b l o c k s a n d B1VP

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 62 of 124 REJ03B0136-0100Z The vertical display start position is determined by counting the hori- zontal sync signal (HSYNC ). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of H SYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of H SYNC and VSYNC signals can select with the OSD I/ O polarity register (address 00EB16). Fig. 8.10.10 Supplement Explanation for Display Position W h e n b i t s 0 a n d 1 o f t h e I / O p o l a r i t y c o n t r o l r e g i s t e r a d d r e s s a r e s e t t o n e g a t i v e p o l a r i t y VS Y N C s i g n a l i n p u t VS Y N C c o n t r o l s i g n a l i n m i c r o c o m p u t e r 0.25 to 0.50 [µs] ( at f(XIN) = 8MHz) (See note 2) Not count 12345 N o t e s 1 :T h e v e r t i c a l p o s i t i o n i s d e t e r m i n e d b y c o u n t i n g f a l l i n g e d g e o f H S Y N C s i g n a l a f t e r r i s i n g e d g e o f VS Y N C c o n t r o l s i g n a l i n t h e m i c r o c o m p u t e r D o n o t g e n e r a t e f a l l i n g e d g e o f H S Y N C s i g n a l n e a r r i s i n g e d g e o f VS Y N C c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o a v o i d j i t t e r T h e p u l s e w i d t h o f VS Y N C a n d H S Y N C n e e d s m a c h i n e c y c l e s o r m o r e 8 machine cycles or more 8 m a c h i n e c y c l e s o r m o r e H SYNC signal input P e r i o d o f c o u n t i n g H S Y N C s i g n a l Fig. 8.10.11 Block i V Register (i = 1, 2) The vertical display start position for each block can be set in 255 steps (where each step is 1H (H: HSYNC cycle)) as values “0116” to “FF16” in block i V register (i = 1, 2) (addresses 00E116 to 00E216). When setting the block i V register to “0116,” the display is started at 18H of count value of HSYNC signal. The vertical display start posi- tion here indicates the top position of character display area in OSD/ BUTTON mode. The block i V register is shown in Figures 8.10.11. b 7b 6b 5b 4b 3b 2b 1b 0 Block i V register (BiVP) (i = 1, 2) [Addresses 00E116 and 00E216] BN a m eF u n c t i o n s After reset R W B l o c k i V R e g i s t e r t o Control bits of vertical display start positions (BiVP0 to BiVP7) (See note 1) I n d e t e r m i n a t e RW N o t e : S e t v a l u e s e x c e p t “ 0 01 6” t o B i V P . V e r t i c a l d i s p l a y s t a r t p o s i t i o n s H d e f H n n s e t t i n g v a l u e H d e H H H S Y N C )

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 63 of 124 REJ03B0136-0100Z The horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4TOSC , TOSC being the OSD oscillation cycle) as values “0016” to “3F16” in the block H register (address 00E016). The block H register is shown in Figure 8.10.13. Fig. 8.10.13 Block H Register b 7b 6b 5b 4b 3b 2b 1b 0 H o r i z o n t a l p o s i t i o n r e g i s t e r ( H P ) [ A d d r e s s 0 0 E 01 BName Functions B l o c k H R e g i s t e r C o n t r o l b i t s o f h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n s B H P t o B H P S e e n o t e to Note: The setting value synchronizes with the VSYNC . 6 , 7 N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e After resetRW 0R W 0R — H orizontal display start positions = Tdef1 + 4TO SC ✕ n (n: setting value, Tdef1: 31TOSC , TOSC : OSD oscillation cycle) Fig. 8.10.12 Notes on Vertical Display Start Position N v : V a l u e o f b l o c k V r e g i s t e r i d e c i m a l H d e f : H VS Y N C ( W h e n s e t t i n g “ 0 11 6” t o b l o c k i V r e g i s t e r , v e r t i c a l d i s p l a y s t a r t p o s i t i o n f o r e a c h m o d e ) s c r e e n H S Y N C H d e f N V 1 7 1 8 O S D m o d e BUTTON mode V e r t i c a l d i s p l a y s t a r t p o s i t i o n When bits 0 and 1 of OSD I/O polarity register (address 00EB16) are “1” (negative polarity)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 64 of 124 REJ03B0136-0100Z Fig. 8.10.14 Notes on Horizontal Display Start Position

• • •
• • • H S Y N C H o r i z o n t a l d i s p l a y s t a r t p o s i t i o n TO S C ✕ N HTd e f B U T T O N m o d e TO S C ✕ H ) BUTTON mode ( 2TOSC ✕ 2H) N H : V a l u e o f b l o c k H r e g i s t e r d e c i m a l TO S C : O S D o s c i l l a t i o n c y c l e Td e f TO S C W i d t h o f B U T T O N d i s p l a y a r e a ( 2 d o t s ) O S D m o d e BUTTON mode ( 3TOSC ✕ 3H) When setting the block H register to “0016,” it needs 31TOSC (= Tdef1) from a rising edge (negative polarity) of HSYNC signal to horizontal display start position. The horizontal display start position here indi- cates the left position of the 1st character’s BUTTON display area in BUTTON mode. When also changing character size, the horizontal display start position is the same. In OSD mode, display position is shifted for BUTTON display area (for 2 dots) from that of the same character size in BUTTON mode.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 65 of 124 REJ03B0136-0100Z (2) Dot size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size con- trol circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (OSC1, main clock from pin X IN) in the pre-divide circuit. The dot size is specified by bits 3 and 4 of the block i control register. Fig. 8.10.15 Block Diagram of Dot Size Control Circuit Fig. 8.10.16 Definition of Dot Sizes Refer to Figure 8.10.8 (the block i control register). The block diagram of dot size control circuit is shown in Figure 8.10.15. 1 dot

1 H Scanning line of F1(F2)

Scanning line of F2(F1)2 H 3 H 3 TO S C2TOSC1 TO S C O S D c o n t r o l c i r c u i t S y n c h r o n o u s c i r c u i t H o r i z o n t a l d o t s i z e c o n t r o l c i r c u i tM a i n c l o c k XI N H S Y N C O S C 1 O C G 0 = “ 1 ” V e r t i c a l d o t s i z e c o n t r o l c i r c u i t C l o c k c y c l e TO S C O C G 1 = “ 0 ”

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 66 of 124 REJ03B0136-0100Z (3) Memory for OSD There are 2 types of memory for OSD : OSD ROM (addresses 1140016 to 13BFF16 and 1540016 to 17AFF16) used to specify character dot data and OSD RAM (addresses 080016 to 0877) used to specify the characters, colors, and attribute. The following describes each type of memory. Fig. 8.10.17 Character Font Data Storing Address ➀ OSD ROM (addresses 1140016 to 13BFF16, 1540016 to 17AFF16) The dot pattern data for OSD characters is stored in the charac- ter font area in the OSD ROM. To specify the kinds of the char- acter font, it is necessary to write the character code (based on OSD ROM address) into the OSD RAM. The modes are selected by bit 3 of the OSD control register 3 for each screen. The character font data storing address is shown in Figure 8.10.17. OSD ROM address of character font data A D 1 6 A D 1 5 A D 1 4 A D 1 3 A D 1 2 AD 11 A D 1 0 AD 9 AD 8 A D 7 AD 6 AD 5 A D 4 A D 3 AD 2 A D 1 A D 0O S D R O M a d d r e s s b i t 1L i n e n u m b e r F o n t b i t L i n e n u m b e r / C h a r a c t e r c o d e F o n t b i t C h a r a c t e r c o d e ( l o w - o r d e r 8 b i t s )0 L i n e n u m b e r = “ 0 A1 6” t o “ 1 D 1 C h a r a c t e r c o d e t o a n d c a n n o t b e u s e d F o n t b i t L e f t a r e a R i g h t a r e a Character code (high- order 1) Character font L i n e n u m b e r O S D R O M d a t a 0 0 0 01

7 F F 01

7 F F 81

L e f t a r e a R i g h t a r e ab0b7 b 0b7 0 A B C D E F 1 3 1 4 1 5 1 6 1 7 1 8 D A B C

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 67 of 124 REJ03B0136-0100Z 1st character 2nd character 3rd character 16th character 17st character 24nd character 1st character 2nd character 3rd character 16th character 17st character 24nd character Note: The 120-byte addresses corresponding to the character code “07F16,” “08016” and “17F16” in OSD ROM are the test data storing area. Set “FF16” to the area. (We stores the test data to this area and the different data from “FF16” is stored for the actual products.) <The test data storing area>

• 1100016 + (4 + 2n) ✕ 10016 + FE16 to 1100016 + (5 + 2n) ✕ 10016 + 0116
• 1500016 + (4 + 2n) ✕ 10016 + FE16 and 1500016 + (4 + 2n) ✕ 10016 + 0116 (n = 0 to 19) Address area addresses 114FE16 to 1150116 addresses 116FE16 to 1170116 addresses 138FE16 to 1390116 addresses 13AFE16 to 13B0116 addresses 154FE16 and 154FF16 addresses 156FE16 and 156FF16 addresses 178FE16 and 178FF16 addresses 17AFE16 and 17AFF16 ➁ OSD RAM (addresses 080016 to 087716) The OSD RAM for character is allocated at addresses 080016 to 084716, 085016 to 085716, 086016 to 086716, 087016 to 087716, and is divided into a display character code specification part 087016 to 087716, and color/attribute specification part for each block. Tables 8.10.3 shows the contents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 0800 16, write color/attribute code at 081016. The structure of the OSD RAM is shown in Figure 8.10.18. Table 8.10.3 Contents of OSD RAM Block Character Code Specification Color/Attribute Code Specification Block 1 Display Position (from left) Block 2 080016 080116 080216 080F16 084016 084716 082016 082116 082216 082F16 086016 086716 081016 081116 081216 081F16 085016 085716 083016 083116 083216 083F16 087016 087716

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 68 of 124 REJ03B0136-0100Z Fig. 8.10.18 Structure of OSD RAM C h a r a c t e r c o d e C o l o r c o d e N o t u s e d O U T c o n t r o l F i x t o Ch a r a c t e r c o d e i n O S D R O M R A A 2 R A 00 0 o l o r r e g i s t e r 00 1 o l o r r e g i s t e r 01 0 o l o r r e g i s t e r 01 1 o l o r r e g i s t e r 10 0 o l o r r e g i s t e r 10 1 o l o r r e g i s t e r 11 0 o l o r r e g i s t e r 11 1 o l o r r e g i s t e r O U T b l a n k o u t p u t O F F O U T b l a n k o u t p u t O N Ch a r a c t e r c o d e i n O S D R O M R A A 2 R A 00 0 o l o r r e g i s t e r 00 1 o l o r r e g i s t e r 01 0 o l o r r e g i s t e r 01 1 o l o r r e g i s t e r 10 0 o l o r r e g i s t e r 10 1 o l o r r e g i s t e r 11 0 o l o r r e g i s t e r 11 1 o l o r r e g i s t e r R A A o B U T T O N b l o c k s h a d o w d i s p l a y N B U T T O N d i s p l a y F F B U T T O N d i s p l a y l o c k s h a d o w d i s p l a y O U T b l a n k o u t p u t O F F O U T b l a n k o u t p u t O N C h a r a c t e r c o d e C o l o r c o d e A t t r i b u t e c o d e O U T c o n t r o l F i x t o B l o c k s 1 a n d 2 B U T T O N M o d e B i t n a m eF u n c t i o nB i t M o d e R F 0 R F R F R F R F R F R F R F R F R A R A R A R A R A R A R A O S D M o d e N o t e s 1 : A t t r i b u t e c o d e i s v a l i d i n o n l y B U T T O N m o d e . D o n o t u s e c h a r a c t e r c o d e s A n d a l s o d o n o t u s e c h a r a c t e r c o d e s t o F t h e s e c o d e s a r e n o t i n c l u d e d i n O S D R O M a r e a b 7b 0b 7 b 0 R A 6R A 5R A 4R A 3R A 2R A 1R F 8R F 7R F 6R F 5R F 4R F 3R F 2R F 1R F 0 C o l o r c o d e C h a r a c t e r c o d e 1 ( S e e n o t e 2 ) O U T 2 c o n t r o l A t t r i b u t e c o d e S e e n o t e Bit name Function

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 69 of 124 REJ03B0136-0100Z (4) Character color Character colors are specified by RA1 to RA3 of OSD RAM. Color data are set by color register i (CO1 to CO8: addresses 00E616 to 00E916, 00EC16 to 00EF16) in advance, and 8 kinds of color regis- ter i are specified by color codes. (5) Character background color Character background are specified by color register i as same as character color. Note : The character background is displayed in the following part: (character display area) – (character font) — (border) – (BUTTON display area) Accordingly, the character background color and the color signal for these sections cannot be mixed. Fig. 8.10.19 Color register i (i = 1 to 8) (6) OUT1, OUT2 signals OUT1 signal is used to erase a back ground TV image. The output waveform of OUT1 signal is controlled by combining the following bits; the display mode selection bits (bits 0 to 2 of the block i control register), the border type selection bit (bit 1 of the OSD control regis- ter), and the OUT1 output control bit (bit 6 of color register i). Figure 8.10.20 and 8.10.21 shows the output example of R, G, B, and OUT1. OUT2 signal is used to change the luminance of a background TV image. The output waveform of OUT2 signal is blank output and is controlled per character unit by RA6 of OSD RAM. b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0 C o l o r r e g i s t e r i ( C O 1 t o C O 8 ) ( i = 1 t o 8 ) [ A d d r e s s e s 0 0 E 61 6 t o 0 0 E 91 6, 0 0 E C 1 6 t o 0 0 E F1 B N ame F u n c t i o n s A f t e r r e s e t R W C olor Register i

0 Indeterm inate R W

1 G signal output selection

bit (COi1) 0 : N o o u t p u t O u t p u t R W

2 B s i g n a l o u t p u t s e l e c t i o n

b i t C O i 0 : N o o u t p u t O u t p u t R W

3 R s i g n a l o u t p u t ( b a c k g r o u n d )

s e l e c t i o n b i t C O i 0 : N o o u t p u t O u t p u t R W

4 G s i g n a l o u t p u t ( b a c k g r o u n d )

s e l e c t i o n b i t C O i 0 : N o o u t p u t O u t p u t R W

5 B s i g n a l o u t p u t ( b a c k g r o u n d )

s e l e c t i o n b i t C O i 0: N o output 1: Output R W

6 O U T 1 o u t p u t c o n t r o l b i t

C O i 0 : C h a r a c t e r o u t p u t B l a n k o u t p u t R W 7 0 R — R s i g n a l o u t p u t s e l e c t i o n b i t C O i 0 : N o o u t p u t O u t p u t N othing is assined. This bit is a write disable bit. When this bit is read out, the value is “0.” Indeterm inate Indeterm inate Indeterm inate Indeterm inate Indeterm inate Indeterm inate

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 70 of 124 REJ03B0136-0100Z Fig. 8.10.20 Output Example of R, G, B and OUT1 (Character Color: Green, Character Background Color: Blue) (In OSD Mode) D i s p l a y m o d e O S D c o l o r r e g i s t e r i b 6 b 5 b 4 b 3 b 2 b 1 O S D ( N o t b o r d e r e d O S D B o r d e r e d G o u t p u t F O N T F O N T F O N T F O N T O U T o u t p u t = A R E A F O N T B O R D E R F O N T B o u t p u t ( b a c k g r o u n d o u t p u t N o o u t p u t L S e e n o t e A R E A F O N T N o o u t p u t L S e e n o t e A R E A F O N T B O R D E R D i s p l a y e x a m p l e b 0 0 0 0 0 A R E A N o t e s w h e n p o s i t i v e p o l a r i t y i s s e l e c t e d E x a m p l e s o f a l l b o r d e r e d d i s p l a y a r e s h o w n G R E E N G B L U E B B L A C K O U T W H I T E R G B O S D m o d e c h a r a c t e r d i s p l a y a r e a A R E A B U T T O N m o d e c h a r a c t e r d i s p l a y a r e a F O N T f o n t p a t t e r n o u t p u t A R E A c h a r a c t e r d i s p l a y a r e a i n O S D m o d e B O R D E R b o r d e r p a t t e r n o u t p u t a r o u n d F O N T B U T T O N b u t t u n d i s p l a y o u t p u t a r o u n d A R E A

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 71 of 124 REJ03B0136-0100Z Fig. 8.10.21 Output Example of R, G, B and OUT1 (Character Color: Green, Character Background Color: Blue) (In BUTTON Mode) b 6 b 5 b 4 b 3 b 2 b 1 b 0 F O N T B U T T O N F O N T B U T T O N F O N T B U T T O N A R E A B U T T O N F O N T B O R D E R B U T T O N B U T T O N B U T T O N A R E A B U T T O N F O N T 0 0 0 A R E A B U T T O N F O N T B O R D E R A R E A B U T T O N F O N T B U T T O N F O N T B U T T O N N o t e s w h e n p o s i t i v e p o l a r i t y i s s e l e c t e d E x a m p l e s o f a l l b o r d e r e d d i s p l a y a r e s h o w n E x a m p l e s o f B U T T O N d i s p l a y b y R A a n d R A o f O S D R A M a r e s h o w n G R E E N G B L U E B B L A C K O U T W H I T E R G B O S D m o d e c h a r a c t e r d i s p l a y a r e a A R E A B U T T O N m o d e c h a r a c t e r d i s p l a y a r e a F O N T f o n t p a t t e r n o u t p u t A R E A c h a r a c t e r d i s p l a y a r e a i n O S D m o d e B O R D E R b o r d e r p a t t e r n o u t p u t a r o u n d F O N T B U T T O N b u t t u n d i s p l a y o u t p u t a r o u n d A R E A D i s p l a y m o d e O S D c o l o r r e g i s t e r i O S D ( N o t b o r d e r e d O S D B o r d e r e d G o u t p u t O U T o u t p u t B o u t p u t ( b a c k g r o u n d o u t p u t D i s p l a y e x a m p l e

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 72 of 124 REJ03B0136-0100Z (7) Attribute (block display) The attributes (border, BUTTON display, block shadow display) are controlled to the character font. The display mode is specified per block unit by bits 0 to 2 of the block i control register. The attributes to be controlled are different depending on each mode. Fig. 8.10.22 Border Priority ➀ Border The border is output in the OSD and BUTTON modes. The all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected per screen unit by bit 1 of OSD control register (refer to Figure 8.10.4). The ON/OFF switch for borders can be controlled per block unit by bit 2 of the block i control register (refer to Fig- ure 8.10.8). The OUT1 signal is used for border output. The horizontal size (x) of border is 1T OSC (TOSC : OSD oscillation cycle) regardless of the character font dot size. The vertical size (y) is 1H (2H in the bi-scan mode) regardless of character font. Notes 1:The border dot area is the shaded area as shown in Figure 8.10.23. In BUTTON mode, it is possible to display in vertical out of character area of 20 dots. 2:When the border dot overlaps on the next character font, the charac- ter font has priority (refer to Figure 8.10.22 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 8.10.22 B). 3:The border in vertical out of character area is not displayed in OSD mode (refer to Figure 8.10.22). C h a r a c t e r b o u n d a r y B C h a r a c t e r b o u n d a r y A C h a r a c t e r b o u n d a r y B P r i o r i t y l e v e l : B U T T O N d i s p l a y b l o c k s h a d o w d i s p l a y F O N T d i s p l a y b o r d e r d i s p l a y c h a r a c t e r b a c k g r o u n d d i s p l a y

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 73 of 124 REJ03B0136-0100Z A l l b o r d e r 16 dots 2 0 d o t s Character font area B O R D E R F O N T Shadow border Border dot ( =1TOSC ) W i d t h o f b o r d e r d o t ( = 1 H ) S e e n o t e Note: It is possible in only BUTTON mode. B o r d e r d i s p l a y a r e a T h i s i s d i s p l a y e x a m p l e w h e n 1 TO S C ✕ 1 H o f d o t s i z e . Border dot ( =1TOSC ) W i d t h o f b o r d e r d o t ( = 1 H ) S e e n o t e Fig. 8.10.23 Border Display Example and Border Area

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 74 of 124 REJ03B0136-0100Z ➁ BUTTON display There are 2 kinds of displays; ON BUTTON display and OFF BUTTON display. The BUTTON display is controlled per charac- ter unit by RA4 and RA5 of OSD RAM. The BUTTON display area is around the character display area in the BUTTON mode. The ON/OFF BUTTON is displayed by outputting white (R + G + B) or black (OUT) to this area. The horizontal size (x) of BUTTON display area is for 2 dots re- gardless of the character font dot size. The vertical size (y) is for 2 dots regardless of the vertical dot size of character font. Fig. 8.10.24 ON/OFF BUTTON Display and Block Shadow Display ➂ Block shadow display The block shadow is displayed to the character display area in the BUTTON mode. The block shadow display is controlled per character unit by RA4 and RA5 of OSD RAM. FIgure 8.10.24 shows each display example. The BUTTON/block shadow can be displayed to the character area where combined ar- bitrary (within 24 characters for a block). Set each character in this case, too. Set “0” to all attribute codes between ON BUTTON, OFF BUTTON and block shadow displays. O N B U T T O NO F F B U T T O N 2 0 d o t s 1 6 d o t s BUTTON display area (= 2 dots) BUTTON display area (= 2 dots) = Character font display area 1 6 d o t s 2 2 d o t s Shadow display area ( = 2 dots) S h a d o w d i s p l a y a r e a d o t s

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 75 of 124 REJ03B0136-0100Z Fig. 8.10.25 Attribute Codes and Display Examples N o t e s 1 : W h e n R A 4 = R A 5 = “ 1 , ” s h a d o w b o r d e r c a n b e d i s p l a y e d i n c h a r a c t e r d i s p l a y a r e a W h e n R A R A c h a r a c t e r b a c k g r o u n d c o l o r c a n b e c o l o r e d i n a l l d i s p l a y a r e a k i n d s o f d i s p l a y O N b u t t o n O F F b u t t o n a n d b l o c k s h a d o w c a n b e d i s p l a y e d w i t h i n t h e s a m e b l o c k B e s u r e t o s e t a t t r i b u t e s b e t w e e n t h e s e d i s p l a y t o

• • • A t t r i b u t e c o d e R A 5 A t t r i b u t e c o d e R A = Character display area in OSD mode ( S e e n o t e s 2 , 3 )( S e e n o t e 1 )

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 76 of 124 REJ03B0136-0100Z (8) Multiline display This microcomputer can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display 3 lines or more by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the block i V registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line ex- ceeds the block.Fig. 8.10.26 Note on Occurence of OSD Interrupt Notes 1:An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register i (addresses 00F9 and 00FA16), an OSD interrupt request does not occur (refer to Fig- ure 8.10.26 (A)). 2:When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 8.10.26 (B)). 3:On the screen setting window, an OSD interrupt occurs even at the end of the block (off display) out of window (refer to Figure 12.11.36 (C)). (B) (C) Block 1 (on display) Block 2 (on display) Block 1' (on display) Block 2' (on display) Block 1 (on display) Block 2 (on display) Block 1' (off display) Block 2' (off display) “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” No “OSD interrupt request” Block 1 Block 2 “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” Block 1 Block 2 Block 1' On display (OSD interrupt request occurs at the end of block display) Off display (OSD interrupt request does not occur at the end of block display) Window No “OSD interrupt request” No “OSD interrupt request” (A)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 77 of 124 REJ03B0136-0100Z (9) Window function The window function can be set windows on-screen, and output OSD within only the area where the window is set. The ON/OFF for vertical window function is performed by bit 4 of the OSD control register. The top boundary is set by the top border con- trol register (TBR) and the bottom boundary is set by bottom border control register (BBR). The left boundary is set by the left border control register (LBR), and the right boundary is set by the right bor- der control register (RBR). The left and right boundarys can be adjusted minutely by bits 2 and 3 of the OSD control register (address 00EA 16). Note: The SPRITE display is not effected by the window function. Fig. 8.10.27 Example of window function W i n d o w FG HIJ KLMNO PQRST B o t t o m b o u n d a r y o f w i n d o w Top boundary of window Screen Window R i g h t b o u n d a r y o f w i n d o w 4TO SC ✕ RBR + 1TO SC ✕ WH 4 TO S C ✕ L BR + 1 TO S C ✕ WHTd e f H S Y N C H def TBR B B R VS Y N C L B R : V a l u e o f l e f t b o r d e r c o n t r o l r e g i s t e r R B R : V a l u e o f r i g h t b o r d e r c o n t r o l r e g i s t e r W H : V a l u e t o o f w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t TO S C : O S D o s c i l l a t i o n c y c l e Td e f 4 : TO S C T B R : V a l u e o f t o p b o r d e r c o n t r o l r e g i s t e r B B R : V a l u e o f b o t t o m b o r d e r c o n t r o l r e g i s t e r H d e f : H H : H S Y N C L e f t b o u n d a r y o f w i n d o w

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 78 of 124 REJ03B0136-0100Z Fig. 8.10.29 Bottom Border Control Register Fig. 8.10.28 Top Border Control Register b 7b 6b 5b 4b 3b 2b 1b 0 Top border control register (TBR) [Address 024516] BN a m eF u n c t i o n s After resetRW T o p B o r d e r C o n t r o l R e g i s t e r t o C o n t r o l b i t s o f t o p b o r d e r T B R t o T B R T o p b o r d e r p o s i t i o n H d e f H n n s e t t i n g v a l u e H d e H H H S Y N C ) I n d e t e r m i n a t e RW Notes 1: Set values except “0016” to TBR. 2: Set values fit for TBR ≤ BBR. b 7b 6b 5b 4b 3b 2b 1b 0 Bottom border control register (BBR) [Address 024616] BN a m eF u n c t i o n sA f t e r r e s e tR W B o t t o m B o r d e r C o n t r o l R e g i s t e r to C o n t r o l b i t s o f b o t t o m b o r d e r B B R t o B B R I n d e t e r m i n a t e RWBottom border position = Hdef + H ✕ n (n: setting value, Hdef: 17H, H: HSYNC ) Notes 1: Set values except “0016” to BBR. 2: Set values fit for TBR ≤ BBR.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 79 of 124 REJ03B0136-0100Z Fig. 8.10.30 Left BorderControl Register Fig. 8.10.31 Right Border Control Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 Left border control register (LBR) [Address 024016] B N a m e Functions L e f t B o r d e r C o n t r o l R e g i s t e r C ontrol bits of left border (LBR0 to LBR6) t o Left border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕ W H (n: setting value, Tdef4: 4TOSC , TOSC : OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit) N o t h i n g i s a s s i g n e d . T h i s b i t i s w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s i n d e t e r m i n a t e A f t e r r e s e t R W

0 R —

N ote: Set values fit for LBR ≤ RBR . b7 b6 b5 b4 b3 b2 b1 b0 Right border control register (RBR) [Address 024116] B N a m e F u n c t i o n s R i g h t B o r d e r C o n t r o l R e g i s t e r C o n t r o l b i t s o f l e f t b o r d e r R B R t o R B R to N o t h i n g i s a s s i g n e d . T h i s b i t i s w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s i n d e t e r m i n a t e A f t e r r e s e t R W N o t e : S e t v a l u e s f i t f o r L B R ≤ R B R . Right border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕ W H (n: setting value, Tdef4: 4TOSC , TOSC : OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 80 of 124 REJ03B0136-0100Z

8.10.2 SPRITE Display

This is especially suitable for cursor and other displays as its func- tion allows for display in any position, regardless of the validity of other OSDs or display positions. Each SPRITE font is ROM font con- sisting of 16 horizontal dots ✕ 20 vertical dots, and there are 4 kinds. When SPRITE display overlaps with other OSDs, SPRITE display is always given priority. Fig. 8.10.32 SPRITE Display Example B R I G H T N E S S T I N T S O U N D M O N A U R A L S T E R E O U S E R S E L E C T S P R I T E d i s p l a y S P R I T E f o n t 1 S P R I T E f o n t 2 N o t e : S P R I T E f o n t s 1 a n d 2 a r e d i s p l a y e d b y s y n t h e s i z i n g . S y n t h e s i s S P R I T E f o n t s 1 a n d 2 ( p e r S P R I T E f o n t u n i t ) K i n d s o f c h a r a c t e r s i z e s D o t s i z e C h a r a c t e r f o n t c o l o r i n g Notes 1: It is possible to set in any position regardless of vertical display positions of the block display. The vertical display start positions of the SPRITE display is the same as that of the block display. 2: It is possible to set in any position regardless of horizontal display position of block display. 3: It is the same display area as OSD mode (refer to “Figure 8.10.3”). 4: As for character font data storing address refer to “8.10.1 Block Display (3) Memory for OSD.” The characters of character codes “F816” to “FF16” can be also used for the block display. 5: Refer to “8.10.1 Block Display (2) Dot size.” The dot size in the bi-scan mode is 1TOSC ✕ 2H. 6: Refer to “8.10.1 Block Display (4) Character color.” Only color registers 1 to 4 can be specified. 7: H = HSYNC 8: TOSC = OSD oscillation cycle FeaturesP a r a m e t e r N u m b e r o f d i s p l a y c h a r a c t e r s 1 characters ✕ 1 line (display by synthesizing 2 kinds of characters) D o t s t r u c t u r e K i n d s o f c h a r a c t e r s 4 kinds (Character code = “F816” to “FF16”) (See note 4) 1 k i n d TO S C ✕ H S e e n o t e s 16 ✕ 20 dots (See note 3) O t h e r fu n c t i o n sC o r r e s p o n d i n g t o b i - s c a n O S D o u t p u t R , G , B Display position Horizontal: 253 levels (See note 2), Vertical: 255 levels (See note 1) Table 8.10.4 Features of SPRITE Display To display SPRITE font, OSD ROM font data for 2 characters is used. These 2 fonts can be colored with any color and can be displayed by synthesizing as a character. The features and display example of SPRITE display are shown below. Notes 1: The SPRITE display is not effected by the window function. 2: The SPRITE display cannot output character background color or OUT2.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 81 of 124 REJ03B0136-0100Z Fig. 8.10.33 SPRITE H Register Fig. 8.10.35 SPRITE V Register b 7b 6b 5b 4b 3b 2b 1b 0 S P R I T E H r e g i s t e r ( S H P ) [ A d d r e s s 0 0 E 41 BN a m eF u n c t i o n s S P R I T E H R e g i s t e r t o H o r i z o n t a l d i s p l a y s t a r t p o s i t i o n c o n t r o l b i t s o f S P R I T E O S D S H P t o S H P H orizontal display start position = Tdef2 + 2TO SC n (n: setting value, Tdef2: 2TO SC , TO SC : O SD oscillation cycle) A f t e r r e s e tR W RW0 N o t e s 1 : S e t v a l u e s e x c e p t “ 0 01 6” t o “ 0 21 6” t o S H P . W h e n s e l e c t i n g r a s t e r p a t t e r n i n g d i s p l a y s e t t i n g v a l u e i s s y n c h r o n i z e d w i t h VS Y N C s i g n a l w h e n s e l e c t i n g S P R I T E d i s p l a y i t i s n o t s y n c h r o n i z e d b 7b 6b 5b 4b 3b 2b 1b 0 S P R I T E V r e g i s t e r ( S V P ) [ A d d r e s s 0 0 E 51 B Name Functions S P R I T E V R e g i s t e r t o H orizontal display start position control bits of SPR ITE O SD (SVP0 to SVP7) (See note 1) H o r i z o n t a l d i s p l a y s t a r t p o s i t i o n H d e f + H n n s e t t i n g v a l u e H d e H H H S Y N C ) Note: Set values except “0016” to the SVP. After reset R W RWIndeterm inate Fig. 8.10.34 Note on Horizontal Display Start Position of SPRITE Display N H ' : value of SPRITE H register (decimal) (see note) TOSC : OSD oscillation cycle Tdef2: 2TOSC Note: Do not set “0” to “2” to NH '. H S Y N C 2TO S C ✕ NH 'Td e W h e n s e t t i n g t h e S P R I T E H r e g i s t e r t o t h e i n t e r v a l o f Td e TO S C ✕ TO S C i s n e c e s s a r y f r o m a r i s i n g e d g e n e g a t i v e p o l a r i t y t o h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 82 of 124 REJ03B0136-0100Z Fig. 8.10.35 SPRITE Control Register b 7 b 6 b5 b4 b 3 b 2 b 1 b 0 S P R I T E c o n t r o l r e g i s t e r ( S C ) [ A d d r e s s 0 0 E 31 B N ame F u n c t i o n s A f t e r r e s e t R W S P R I T E C o n t r o l R e g i s t e r 0, 1 4 , 5 S P R I T E f o n t 1 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t S C S C 0 WR WR N o t e : T h i s b i t i s v a l i d w h e n b i t 0 o f t h e O S D c o n t r o l r e g i s t e r t o “ 1 . ” 2, 3 S P R I T E f o n t 2 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t S C S C 0 WR 6, 7 SPRITE/raster patterning control bit (SC6, SC7) (See note) WR S P R I T E f o n t s e l e c t i o n b i t S C S C SC 5 SC 4 Ch aracter code SPRITE1 SPRITE2 F816 FA 16 FC 16 FE 16 F916 FB 16 FD 16 FF16 S C 1 S C 0 C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r S C 3 S C 2 C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r SC 7 SC 6 0 0: Display OFF 0 1: Do not set 1 0: SPRITE display 1 1: Raster patterning display

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 83 of 124 REJ03B0136-0100Z

8.10.3 Raster Display

The raster display is displayed on the lower layer than the SPRITE and block layers. There are 2 kinds of displays; the flat display and the patterning display. In the raster flat display, an entire screen (raster) can be colored by setting the following bits; bits 5 to 7 of the OSD I/O polarity register and bits 6 and 7 of the OSD control register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 8 raster colors can be obtained. In the raster patterning display, SPRITE fonts are displayed repeat- edly on an entire screen (raster). At this time, set “1” to bits 6 and 7 of the SPRITE control register. Horizontal display start positions of the raster patterning display are set by the SPRITE H register. At this time, setting value is synchro- nized with V SYNC signal. Characters for patterning are set by bits 4 and 5 of the SPRITE con- trol register and coloring are set by bits 0 to 3. The raster color is output on the background of SPRITE font. Fig. 8.10.36 Raster Flat Display Example Note that the raster patterning display and the SPRITE display can- not be used at the same time. When the character color/the character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2), specified for the character color/the character background color, takes priority of the raster color. This ensures that the character color/the character background color is not mixed with the raster color. The raster flat display example is shown in Figure 8.10.36, the raster patterning display example is shown in Figure 8.10.37. H S Y N C A'A OUT1 R G B : Character color “RED” (R + OUT1 + OUT2) : Border color “BLACK” (OUT1 + OUT2) : Background color “MAGENTA” (R + B + OUT1 + OUT2) : Raster color “BLUE” (R + OUT1 + OUT2) Signals across A-A' OUT2

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 84 of 124 REJ03B0136-0100Z Fig. 8.10.37 Raster Patterning Display Example H S Y N C Td e f2 2TOSC ✕ NH' s c r e e n S P R I T E f o n t R a s t e r c o l o r “ B L U E ” ( B + O U T 1 ) S P R I T E f o n t c o l o r B L A C K O U T S P R I T E f o n t c o l o r W H I T E R G B O U T ( S e e n o t e ) N o t e : D o n o t s e t “ 0 ” t o “ 2 ” t o N H ' . N H ' : Value of SPRITE H register (decimal) (See note) TOSC : OSD oscillation cycle Tdef2 : 2TOSC W h e n s e t t i n g “ 0 31 6” t o S P R I T E H r e g i s t e r , i t i s n e e d Td e f 2 + 2 TO S C ✕ 3 TO S C i n t e r v a l s f r o m a r i s i n g e d g e n e g a t i v e p o l a r i t y o f H S Y N C s i g n a l t o a h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 85 of 124 REJ03B0136-0100Z AD H , AD L 01,S–201,S–1 PC H PC L PS AD HAD L PC ? :Undefined instruction decode Undefined instruction decoding signal occurs.Internal reset signal occurs. φ SYNC Address Data Reset sequence 01,S FFFE 16 FFFF 16 : Invalid : Program counter S : Stack pointer PC ADL, ADH : Jump destination address of reset Fig.8.11.1 Sequence at Detecting Software Runaway Detection

8.11 SOFTWARE RUNAWAY DETECT FUNCTION

This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. ➀ The CPU generates an undefined instruction decoding signal. ➁ The device is internally reset because of occurrence of the unde- fined instruction decoding signal. ➂ As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be invalid.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 86 of 124 REJ03B0136-0100Z 8.12. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 V ± 10 %, hold the RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 8.12.2, reset is released and the program starts form the address formed by using the content of address FFFF 16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are An example of the reset circuit is shown in Figure 8.12.1. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. Fig.8.12.2 Reset Sequence Fig.8.12.1 Example of Reset Circuit Power source voltage 0 V Reset input voltage 0 V 4.5 V 0.9 V Poweron Vcc RESET Vss Microcomputer 3 0.1 µF M51953AL XIN φ RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (See note 3) Reset address from the vector table ? ? 01, S 01, S-101, S-2 FFFE FFFF AD H , AD L Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 87 of 124 REJ03B0136-0100Z

8.13 CLOCK GENERATING CIRCUIT

The built-in clock generating circuit is shown in Figure 8.13.3. When the STP instruction is executed, the internal clock φ stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and “FF 16” is set in timer 3 and “0716” is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to “0” before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before ex- ecution of the STP instruction). The oscillator restarts when external interrupt is accepted. However, the internal clock φ keeps its HIGH until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock φ stops in the HIGH but the oscillator continues running. This wait state is re- leased when an interrupt is accepted (See note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to “1” before executing the STP or the WIT instructions. Note: In the wait mode, the following interrupts are invalid.

• VSYNC interrupt
• OSD interrupt
• Timer 2 interrupt using external clock input from TIM2 pin as count source
• Timer 3 interrupt using external clock input from TIM3 pin as count source
• Timer 4 interrupt using f(X IN)/2 as count source
• Timer 1 interrupt using f(XIN)/4096 as count source
• f(XIN)/4096 interrupt
• Multi-master I2C-BUS interface interrupt
• A-D conversion interrupt
• SPRITE interrupt A circuit example using a ceramic resonator (or a quartz-crystal os- cillator) is shown in Figure 8.13.1. Use the circuit constants in accor- dance with the resonator manufacture’s recommended values. A cir- cuit example with external clock input is shown in Figure 8.13.2. In- put the clock to the X IN pin, and open the XOUT pin. Fig.8.13.1 Ceramic Resonator Circuit Example Fig.8.13.2 External Clock Input Circuit Example X IN XOUT C IN Microcomputer C OUT X IN Microcomputer Vcc Vss External oscillation circuit Fig.8.13.3 Clock Generating Circuit Block Diagram Interrupt request Interrupt disable flag I Reset SQ RSTP instruction SQ R WIT instruction SQ R STP instruction Reset Internal clock φ 1/2 1/8 Timer 3 Timer 4 XOUTXIN TM20 TM22 Selection gate : Connected to black side at reset. TM2 : Timer mode register 2

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 88 of 124 REJ03B0136-0100Z RESET Vss Vcc Circuit example 1 RESET Vss Vcc Circuit example 2 Note :Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage.

8.14 DISPLAY OSCILLATION CIRCUIT

The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 0 and 1 of the interrupt input polarity register (address 00CD 16).

8.16 ADDRESSING MODE

The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 <Software> User’s Manual for details.

8.17 MACHINE INSTRUCTIONS

There are 71 machine instructions. Refer to SERIES 740 <Soft- ware> User’s Manual for details. 9. PROGRAMMING NOTES

• The divide ratio of the timer is 1/(n+1).
• Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions.
• After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed.
• An NOP instruction is needed immediately after the execution of a PLP instruction.
• In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1µF) directly between the V CC pin–VSS pin, AVCC pin–VSS pin, and the VCC pin–CNVSS pin, using a thick wire. Fig.8.14.1 Display Oscillation Circuit

8.15 AUTO-CLEAR CIRCUIT

When a power source is supplied, the auto-clear function will oper- ate by connecting the following circuit to the RESET pin. Fig.8.15.1 Auto-clear Circuit Example OSC2OSC1 L C1 C2

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 89 of 124 REJ03B0136-0100Z Power source voltage VCC Input voltage CNV SS Input voltage P0 0–P07, P10–P17, P20–P27, P30–P35, OSC1, XIN, P50, P51,______ RESET Output voltage P0 6, P07, P10–P17, P20–P27, P30–P32, P35, P52–P55, XOUT , OSC2 Output voltage P0 0–P05 Circuit current P5 2–P55, P10–P17, P20–P27, P30, P31, P35 Circuit current P5 2–P55, P06, P07, P10, P15–P17, P20–P23, P30–P32, P35 Circuit current P1 1–P14 Circuit current P0 0–P05 Circuit current P2 4, P27 Power dissipation Operating temperature Storage temperature Symbol V CC , AVCC VI VI VO VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg 10. ABSOLUTE MAXIMUM RATINGS Conditions All voltages are based on VSS . Output transistors are cut off. Parametear T a = 25 °C Unit V V V V V mA mA mA mA mA mW Ratings –0.3 to 6 –0.3 to 6 –0.3 to V CC + 0.3 –0.3 to VCC + 0.3 –0.3 to 13 0 to 1 (See note 1) 0 to 2 (See note 2) 0 to 6 (See note 2) 0 to 1 (See note 2) 0 to 10 (See note 3) 550 –10 to 70 –40 to 125 Power source voltage (See note 4), During CPU, OSD, data slicer operation Power source voltage HIGH input voltage P0 0–P07, P10–P17, P20–P27, P30–P35, SIN, SCLK , P50, P51, RESET, XIN, OSC1, TIM2, TIM3, INT1–INT3 HIGH input voltage SCL1, SCL2, SDA1, SDA2 LOW input voltage P0 0–P07, P10–P17, P20–P27, P30–P35 LOW input voltage SCL1, SCL2, SDA1, SDA2 LOW input voltage (See note 6) P5 0, P51, RESET, TIM2, TIM3, INT1–INT3, XIN, OSC1, SIN, SCLK HIGH average output current (See note 1) P52–P55, P10–P17, P20–P27, P30, P31, P35 LOW average output current (See note 2) P52–P55, P06, P07, P10, P15–P17, P30–P32, P35 LOW average output current (See note 2) P11–P14 LOW average output current (See note 2) P00–P05 LOW average output current (See note 3) P24–P27 Oscillation frequency (for CPU operation) (See note 5) XIN Oscillation frequency (for OSD) OSC1 Input frequency TIM2, TIM3 Input frequency S CLK Input frequency SCL1, SCL2 Limits Min. 4.5 0.8VCC 0.7VCC 7.9 5.0 5.0 7.9 Typ. 5.0 8.0 8.0 8.0 8.0 Max. 5.5 V CC VCC

0.4 VCC

0.3 VCC

0.2 VCC

8.1 9.0 17.0 8.1 100 400 V V V V V V V mA mA mA mA mA MHz MHz kHz MHz MHz 11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) VCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) fosc fhs1 fhs2 fhs3 Symbol Parameter Unit RC oscillating mode LC oscillating mode Ceramic oscillating mode

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 90 of 124 REJ03B0136-0100Z Power source current HIGH output voltage P52–P55, P10–P17, P20–P27,P30, P31, P35 LOW output voltage P52–P55, P00–P07, P10, P15–P17, P20–P23, P30–P32, P35 LOW output voltage P24–P27 LOW output voltage P11–P14 Hysteresis (See note 6) RESET, P50, P51, TIM2, TIM3, INT1–INT3, SCL1, SCL2, SDA1, SDA2, S IN, SCLK HIGH input leak current RESET , P00–P07, P10–P17, P20–P27, P30–P35, P50, P51 LOW input leak current RESET , P00–P07, P10–P17, P20–P27, P30–P35, P50, P51 HIGH input leak currentP00–P05 I2C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) Max. 300 0.4 3.0 0.4 0.6 1.3 130 Limits Min. 2.4 12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) ICC VOH VOL VT+ – VT– IIZH IIZL IOZH R BS Typ. 0.5 Symbol Parameter Test conditions Unit System operation Stop mode V CC = 5.5 V, f(XIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VI = 12 V VCC = 4.5 V OSD OFF OSD ON Test circuit VCC = 5.5 V, f(XIN) = 8 MHz mA mA V V V µA µA µA Ω Notes 1:The total current that flows out of the IC must be 20 mA or less. 2:The total input current to IC (IOL1 + IOL2 + IOL3 ) must be 30 mA or less. 3:The total average input current for ports P24–P27 to IC must be 20 mA or less. 4:Connect 0.1 µF or more capacitor externally between the power source pins VCC –VSS so as to reduce power source noise. Also connect 0.1 µF or more capacitor externally between the pins VCC –CNV SS . 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6:P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins. 7:Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports

• When the same limits: I/O port name.
• When the limits of functins except ports are different from I/O port limits: function pin name. IOL = 3 mA IOL = 6 mA

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 91 of 124 REJ03B0136-0100Z Fig.12.1 Measure Circuits V s s V c c V VO H o r VO L IO H o r IO L 4 . 5 V E a c h o u t p u t p i n After setting each output pin to HIGH level when measuring VOH and to LOW level when measuring VOL , each pin is measured. V s s V c c 5 . 0 V Each input pin V s s V c c VB S 4 . 5 V S C L 1 o r S D A 1 IB S A R B S = VB IB S S C L 2 o r S D A 2 R B S V s s V c c 5 . 5 V Each input pin A IIZH or IIZL V s s V c c 5 . 5 V AE a c h o u t p u t p i n A f t e r s e t t i n g e a c h o u t p u t p i n O F F s t a t e , e a c h p i n i s m e a s u r e d IOZ H 1 2 V A V s s V c cXI N XOUT O S C 1 O S C 2 Icc 8 . 0 0 M H z P o w e r s o u r c e v o l t a g e Pin VCC is made the operation state and is measured the current, with a ceramic resonator.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 92 of 124 REJ03B0136-0100Z 13. A-D CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Resolution Absolute accuracy (excludig guantization error) Conversion time Ladder resistor Analog input voltage Max. ±2.5 12.5 V REF bits LSB µs kΩ V Min. 12.25 Limits UnitTest conditionsParameterSymbol TCONV R LADDER VIA Vcc = 5 V Typ. 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Max. 1000 300 Min. 1.3 0.6 1.3 20+0.1C b 0.6 20+0.1Cb 100 0.6 0.6 Max. 300 0.9 300 µs µs µs ns µs µs ns ns µs µs UnitStandard clock mode High-speed clock modeParameterSymbol Note: Cb = total capacitance of 1 bus line Fig.14.1 Definition Diagram of Timing on Multi-master I2C-BUS Min. 4.7 4.0 4.7 4.0 250 4.7 4.0 SDA SCL P tBUF S tHD ;STA tLOW tR tHD ;DAT tHIGH tF tSU ;DAT tSU ;STA Sr P tSU ;STOtHD ;STA S Sr P : Start condition : Restart condition : Stop condition

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 93 of 124 REJ03B0136-0100Z 15. PROM PROGRAMMING METHOD The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a general- purpose PROM programmer using a special programming adapter. Product M37225ECSP Name of Programming Adapter PCA7408 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 15.1 is recommended to verify programming. Fig. 15.1 Programming and Testing of One Time PROM Version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours.

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 94 of 124 REJ03B0136-0100Z 16. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion:

• Mask ROM Order Confirmation Form
• Mark Specification Form
• Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies) or FDK

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 95 of 124 REJ03B0136-0100Z 17. ONE TIME PROM VERSION M37225ECSP MARKING M37225ECSP XXXXXX XXXXXX is lot number

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 96 of 124 REJ03B0136-0100Z 18. APPENDIX Pin Configuration (TOP VIEW) Outline 42P4B P06/INT2/A-D4 XO U T H S Y N C / P 50 VS Y N C / P 51 P 00/ P W M 0 P 01/ P W M 1 P 02/ P W M 2 P 03/ P W M 3 P 04/ P W M 4 P 05/ P W M 5 P 07/ I N T 1 P 23/ T I M 3 P 24/ T I M 2 P 25 P 26 P 27 D A 1 / P 35 P 32/ A - D 7 C N VS S XI N VS S R E S E T R / P 52 G / P 53 B / P 54 O U T 1 / P 55 P 20/ SC L K P 21/ SO U T( /SI N ) P 22/ SI N P 10/ OU T 2 / A - D 8 P 11/ S C L 1 P 12/ S C L 2 P 13/ S D A 1 P 14/ S D A 2 P 16/ A - D 2 P 30/ A - D 5 P 31/ A - D 6 O S C 1 / P 33 O S C 2 / P 34 VC C P 17/ D A 2 /A - D3 P 15/ I N T 3 / A - D 1 M 3 7 2 2 5 M 6 / M 8 / M A / M C - X X X S P M E C S P

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 97 of 124 REJ03B0136-0100Z Memory Map 000016 00C0 16 00FF16 01FF16 SFR area 021716 021D 16 024016 02E016 010016 024F16 02C0 16 ROM correction function Vector 1: address 02C016 Vector 2: address 02E016 Vector 3: address 030016 I M 3 7 2 2 5 M 6 / M 8 - X X X S P ( 1 0 2 4 b y t e s ) 087716 080016O S D R A M b y r e s S e e n o t e 800016 FFFF 16 FFDE 16 FF0016 Interrupt vector areaS p e c i a l p a g e A00016 M37225M8- XXXSP ROM (32K bytes) M 3 7 2 2 5 M 6 - X X X S P R O M K b y t e s 00BF 16 N o t e : R e f e r t o T a b l e 8 . 1 0 . 3 O S D R A M . 1 0 0 0 01 1 3 B F F1 1 1 4 0 01 1 5 4 F F1 1 5 4 0 01 1 5 6 F F1 1 5 6 0 01 OSD ROM (15K bytes) 2 p a g e r e g i s t e r ( 1 ) N o t u s e d 2 p a g e r e g i s t e r ( 2 ) N o t u s e d N o t u s e d N o t u s e d Not used N o t u s e d N o t u s e d N o t u s e d Not used Not used N o t u s e d N o t u s e d Not used N o t u s e d N o t u s e d Not used N o t u s e d Not used N o t u s e d Not used N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 98 of 124 REJ03B0136-0100Z 0 0 0 01 0 0 C 01 0 0 F F1 0 1 F F1 SFR area Zero page 0 2 1 71 0 2 1 D 1 0 2 4 01 0 1 0 01 0 2 4 F1 4 0 0 01 F F F F1 F F D E1 F F 0 01 M37225MC-XXXSP M37225ECSP ROM (48K bytes) RAM (2048 bytes) N o t e : R e f e r t o T a b l e 8 . 1 0 . 3 O S D R A M . 1 0 0 0 01 1 3 B F F1 1 1 4 0 01 1 5 4 F F1 1 5 4 0 01 1 5 6 F F1 1 5 6 0 01 OSD ROM (15K bytes) M A M C X X X S P M E C S P 0 2 E 01 0 2 C 01 0 7 F F1 0 3 0 01 0 8 7 71 0 8 0 01 090016 0 9 F F1 O S D R A M b y t e s S e e n o t e Not used 2 page register (1) Not used 2 page register (2) Not used R O M c o r r e c t i o n f u n c t i o n V e c t o r a d d r e s s C V e c t o r a d d r e s s E V e c t o r a d d r e s s Not used Not used Interrupt vector areaSpecial page N o t u s e d N o t u s e d N o t u s e d N o t u s e d Not used N o t u s e d Not used N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d N o t u s e d M37225MA-XXXSP ROM (40K bytes) 6 0 0 01

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 99 of 124 REJ03B0136-0100Z Memory Map of Special Function Register (SFR) I SFR area (addresses C016 to DF16) D 01 D1 16 D 21 D3 16 D 41 D 51 D 61 D 71 D 81 D 91 D A1 DB 16 D C 1 D D 1 D E1 DF 16 C0 16 C1 16 C2 16 C 31 C 41 C 51 C 61 C 71 C 81 C 91 C B1 C C 1 CD 16 C E1 CF 16 C A1 A d d r e s s P o r t P 5 ( P 5 ) OSD port control register (PF) D A 1 - H r e g i s t e r ( D A 1 - H ) D A 1 - L r e g i s t e r ( D A 1 - L ) PWM0 register (PWM0) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) P o r t P 3 d i r e c t i o n r e g i s t e r ( D 3 ) Port P2 (P2) Port P2 direction register (D2) R e g i s t e r Port P0 (P0) Port P0 direction register (D0) P W M 1 r e g i s t e r ( P W M 1 ) P W M 2 r e g i s t e r ( P W M 2 ) P W M 3 r e g i s t e r ( P W M 3 ) P W M 4 r e g i s t e r ( P W M 4 ) P W M o u t p u t c o n t r o l r e g i s t e r 1 ( P W ) b7 b0 Bit allocation State immediately after reset 0016 b 7 b0 0 01 0 01 000??000 S e r i a l I / O m o d e r e g i s t e r ( S M ) Serial I/O register (SIO) 0 01 P o r t P35 o u t p u t m o d e c o n t r o l r e g i s t e r ( P 3 S ) Test register Interrupt input polarity register (IP) P W M o u t p u t c o n t r o l r e g i s t e r 2 ( P N ) I2C d a t a s h i f t r e g i s t e r S I2C c o n t r o l r e g i s t e r S D I2C c l o c k c o n t r o l r e g i s t e r S I2C status register (S1) I2C address register (S0D) A D c o n v e r s i o n r e g i s t e r ( A D ) A D c o n t r o l r e g i s t e r ( A D C O N ) P 5 2 S E L 00P 5 3 S E L P54 SEL P55 SEL O U T 2 S E P 5 2 O U T P 5 3 O U T P54 OUT P55 OUT P 5 0 I N P 5 1 I N P 3 1 SP 3 0 SP 3 5 DP 3 2 D P31D P30D P 3 2P 3 1 P 3 0P 3 5 P 3 4 I NP 3 3 I N ? 0 ??00 ??0 P W 0P W 1PW2PW3PW4P W 5P W 6PW7 PN2PN3PN4 0 01 0 01 0 01 SAD 0SAD 1SAD 2SAD 3SAD 4SAD 5SAD 6 RB W L R BA D 0AASALP I NB BT R XMST B C 0B C 1B C 2ESOALSBSEL0B S E L 1 10BIT SAD D 1D2D3D4D 5D6D 7D 0 PN5 00 00

00 POL3 P O L 2P O L 1 OCG1OCG0

01 100? ?0 0 01 0 01 SM0SM1SM2SM3SM5SM6 0 C C R 0C C R 1C C R 2C C R 3C C R 4AC K FAST M O D E ACK BIT A D I N 000 AD IN 1AD IN 2AD STRA D V R E F 0 81 0 01 0016 00 ?00010 : Fix to this bit to “0” (do not write to “1”) B i t a l l o c a t i o n > < S t a t e i m m e d i a t e l y a f t e r r e s e t > Function bit : No function bit : Fix to this bit to “1” (do not write to “0”) N a m e : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “ 1 ” i m m e d i a t e l y a f t e r r e s e t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 100 of 124 REJ03B0136-0100Z F 01 F 11 F216 F 31 F416 F 51 F 61 F716 F 81 F916 FA 16 F B1 F C 1 FD 16 F E1 F F1 E 01 E 11 E 21 E 31 E 41 E516 E 61 E 71 E816 E 91 E B1 EC 16 ED 16 E E1 EF 16 EA 16 OSD control register (OC) Color register 5 (CO5) C o l o r r e g i s t e r 7 ( C O 7 ) C o l o r r e g i s t e r 8 ( C O 8 ) T i m e r 1 ( T 1 ) B l o c k 2 V r e g i s t e r ( B 2 V P ) C o l o r r e g i s t e r 1 ( C O 1 ) Color register 2 (CO2) SPRITE H register (SHP) SPRITE V register (SVP) B l o c k H r e g i s t e r ( B H P ) B l o c k 1 V r e g i s t e r ( B 1 V P ) Timer 2 (T2) T i m e r 3 ( T 3 ) T i m e r 4 ( T 4 ) T i m e r m o d e r e g i s t e r 1 ( T M 1 ) Timer mode register 2 (TM2) P W M 5 r e g i s t e r ( P W M 5 ) Block 1 control register (B1C) I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) Interrupt request register 2 (IR EQ 2) I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) Color register 3 (CO3) C o l o r r e g i s t e r 4 ( C O 4 ) C o l o r r e g i s t e r 6 ( C O 6 ) CPU mode register (CM) b 7 b 0 S C 0SC1SC2S C 3 O C C 1OC2 TM20T M 2 1TM22TM23TM24 TM10T M 1 1TM12TM13TM14 CM2 TM1RTM2RTM3RTM4RO SD RVSCRIT3R C K S R I T 1 RI T 2 RS1R TM1ET M 2 ET M 3 ETM4EO SD EV S C EI T 3 E I T 1 EIT2ES1EM S E T M 2 5 b 7 b0 C K F F1 0 71 F F1 0 71 00 ?? ? T M 1 5 01 11 0 01 0 01 0 01 0 01 0? ? 3C 16 0 01 0 01 0016 0 01 S P R I T E c o n t r o l r e g i s t e r ( S C ) O SD I/O polarity control register (O PC ) T e s t r e g i s t e r T e s t r e g i s t e r A D E A D R SPE SPR IICR B2C0B 2 C 1B2C2B2C3B2C4 B1C0B1C1B1C2B1C3B1C4 0016 0016 CK000 ?? ?0? ?B l o c k 2 c o n t r o l r e g i s t e r ( B 2 C ) B H P 0B H P 1BH P2B H P 3B H P 4BH P5 B 1 V P 0B 1 V P 1B1VP2B 1 V P 3B 1 V P 4B1VP5B 1 V P 6B1VP7 B 2 V P 0B 2 V P 1B2VP2B 2 V P 3B 2 V P 4B2VP5B 2 V P 6B2VP7 SC4S C 5SC6S C 7 SH P0SH P1SH P2SH P3SH P4SH P5SH P6 S V P 0S V P 1SVP2S V P 3S V P 4SVP5S V P 6SVP7 O C C C C C O PC 0O PC 1O PC 2O PC 3O PC 4O PC 5O PC 6O PC 7 C O 1 1CO12CO13C O 1 5 C O 2 1CO22CO23C O 2 5 CO14 CO24 C O 1 6 C O 2 6 C O 1 0 C O 2 0 CO31CO32CO33CO35 CO34CO36 CO30 CO41CO42CO43CO45 CO44CO46 CO40 CO51CO52CO53CO55 C O 6 1CO62CO63C O 6 5 CO54 CO64 CO56 C O 6 6 CO50 C O 6 0 CO71CO72CO73CO75 CO74CO76 CO70 C O 8 1CO82CO83C O 8 5C O 8 4C O 8 6C O 8 0 0016 0 01 0016 I SFR area (addresses E016 to FF16) A d d r e s s Register B i t a l l o c a t i o n State immediately after reset : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o B i t a l l o c a t i o n > < S t a t e i m m e d i a t e l y a f t e r r e s e t > Function bit : N o f u n c t i o n b i t : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “ 0 ” i m m e d i a t e l y a f t e r r e s e t : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “ 1 ” i m m e d i a t e l y a f t e r r e s e t IICE SH P7

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 101 of 124 REJ03B0136-0100Z b 7 b 0b 7 b 0 2 1 01 21116 21216 2 1 31 2 1 41 21516 2 1 61 2 1 71 21816 2 1 91 21B16 2 1 C 1 2 1 D 1 2 1 E1 21F16 2 1 A1 R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) R O M correction address 1 (low -order) R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) R O M correction address 2 (low -order) RCR1R C R 0 0016 0016 0016 0 0016 2 4 01 24116 2 4 21 2 4 31 2 4 41 24616 2 4 51 Left border control register (LBR) B B R 0 2 4 71 2 4 91 24816 T e s t r e g i s t e r 0016 2 4 A1 2 4 B1 24C 16 ? 2 4 E1 2 4 D 1 2 4 F1 R ight border control register (R BR ) Top border control register (TBR ) B o t t o m b o r d e r c o n t r o l r e g i s t e r ( B B R ) 0016 B B R 1BBR2BBR3B B R 4BBR5BBR6B B R 7 TBR0TBR1TBR2TBR3TBR4TBR5TBR6TBR7 RBR0RBR1RBR2RBR3RBR4RBR5RBR6 L B R 0L B R 1LBR2LBR3L B R 4LBR5LBR6 D A 2 - L r e g i s t e r ( D A 2 L ) D A 2 - H r e g i s t e r ( D A 2 H ) 0016 0016 I p a g e r e g i s t e r a r e a a d d r e s s e s t o t o A d d r e s s R e g i s t e r B i t a l l o c a t i o nS t a t e i m m e d i a t e l y a f t e r r e s e t : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o B i t a l l o c a t i o n >< State immediately after reset > Function bit : N o f u n c t i o n b i t : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N am e : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “1” immediately after reset 0000 R O M correction address 3 (high-order) R O M c o r r e c t i o n a d d r e s s 3 (l o w- o r d e r ) 0016 0016 R C R 2

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 102 of 124 REJ03B0136-0100Z Internal State of Processor Status Register and Program Counter at Reset b7 b 0 b7 b 0 R e g i s t e r Processor status register (PS) B i t a l l o c a t i o nS t a t e i m m e d i a t e l y a f t e r r e s e t P r o g r a m c o u n t e r ( P C H ) Program counter (PCL) Contents of address FFFF16 C o n t e n t s o f a d d r e s s F F F E1 : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o < Bit allocation > < S t a t e i m m e d i a t e l y a f t e r r e s e t F u n c t i o n b i t : No function bit : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N am e : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “ 1 ” i m m e d i a t e l y a f t e r r e s e t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 103 of 124 REJ03B0136-0100Z Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: V a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e Bit attributes (Note 1) ( N o t e 2 )B i t p o s i t i o n 2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : : B i t i n w h i c h n o t h i n g i s a s s i g n e d N o t e s 1 : V a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e a f t e r r e s e t r e l e a s e a f t e r r e s e t r e l e a s e I n d e t e r m i n a t e I n d e t e r m i n a t e a f t e r r e s e t r e l e a s e R cannot be set. W b 7b 6 b5b 4b 3 b 2b 1b 0 B After re RW C P U M o d e R e g i s t e r 0 , 1 3 , 4 N a m e Functions P r o c e s s o r m o d e b i t s C M C M ) 0 0 : S i n g l e - c h i p m o d e N o t a v a i l a b l e F i x t h e s e b i t s t o “ 1 . ” 1S t a c k p a g e s e l e c t i o n b i t S e e n o t e C M b1 b0 0: 0 page 1: 1 page 1 00 5 1N o t h i n g i s a s s i g n e d . T h i s b i t i s w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s 6, 7 0Clock switch bits (CM6, CM7) 0 0 : f ( XI N ) = 8 M H z f XI N ) M H z f XI N ) M H z D o n o t s e t b7 b6 C P U m o d e r e g i s t e r ( C P U M ) ( C M ) [ A d d r e s s 0 0 F B1 R W RW RW R W RW < E x a m p l e >

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 104 of 124 REJ03B0136-0100Z Addresses 00C116, 00C316, 00C516 Address 00C716 b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 Port P3 direction register (D3) [Address 00C 716] B N a m e F u n c t i o n s After reset R W Port P3 Direction Register 00 : Port P30 input mode 1 : Port P30 output mode 1 0 : Port P31 input mode 1 : Port P31 output mode P o r t P 3 d i r e c t i o n r e g i s t e r R W R W R W2 50 : Port P35 input mode 1 : Port P35 output mode P o r t P 3 d i r e c t i o n r e g i s t e r 0 R W

7 P o r t P 31 o u t p u t m o d e

s e l e c t i o n b i t P S i n d e t e r m i n a t eN othing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate.R —3 , 4 0 : Port P32 input mode 1 : Port P32 output mode 6 0 : CMOS output 1 : N -channel open-drain output P o r t P 30 o u t p u t m o d e s e l e c t i o n b i t P S 0 : CMOS output 1 : N -channel open-drain output b R W 0 0 W 1 0 W 2 0 W 3 0 W 4 0 W 5 0 W 6 0 W 7 0 W R R R R R R R R Port Pi Direction Register b7b6 b5b4b3 b2 b1b0 Port Pi direction register (Di) (i=0,1,2) [Addresses 00c116,00C316,00C516] Name Functions Port Pi direction register0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode After reset

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 105 of 124 REJ03B0136-0100Z Address 00C916 Address 00CB 16 b7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 O S D p o r t c o n t r o l r e g i s t e r ( P F ) [ A d d r e s s 0 0 C B1 b N ame F u n c t i o n s A f t e r r e s e t R W O S D P o r t C o n t r o l R e g i s t e r 0 , 10 R WF i x t h e s e b i t s t o “ 0 ” 2 0 : R signal output 1 : Port P52 output

3 Port P53 output signal

selection bit (P53SEL) 0 : G signal output 1 : Port P53 output

4 Port P54 output signal

selection bit (P54SEL) 0 : B signal output 1 : Port P54 output

5 Port P55 output signal

selection bit (P55SEL) 0 : OUT 1 signal output 1 : Port P55 output

6 Port P10 output signal

selection bit (OUT2SEL) 0 : Port P10 signal output 1 : OUT2 output s e l e c t i o n b i t P S E L

70 R WFix this bit to “0”

b 7 b6 b 5 b 4 b 3 b 2 b 1 b 0 P o r t P 35 o u t p u t m o d e c o n t r o l r e g i s t e r ( P 3 S ) [ A d d r e s s 0 0 C 91 B N a m e Functions A f t e r r e s e t R W P o r t P 35 O u t p u t M o d e C o n t r o l R e g i s t e r 0 to 3 I n d e t e r m i n a t e 0 : CMOS output 1 : N-channel open-drain output Fix this bit to “0” R — R W R5 Port P35 output mode selection bit (P35S) N othing is assigned. These bits are w rite disable bits. W hen these bits are read out, the values are indeterm inate. 6 , 7 0 R WF i x t h e s e b i t s t o “ 0 ” 00 0 W

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 106 of 124 REJ03B0136-0100Z Address 00CD 16 b7 b 6 b5 b 4 b 3 b 2 b 1 b 0 I n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( I P ) [ A d d r e s s 0 0 C D 1 b N a m e F u n c t i o n A f t e r r e s e t R W Interrupt Input Polarity Register INT1 polarity switch bit (POL1) 0 : Positive polarity 1 : Negative polarity 6, 7 s w i t c h b i t P O L I N T 3 p o l a r i t y s w i t c h b i t P O L F i x t h e s e b i t s t o “ 0 . ” 0 WR 0 WR 0 , 1 O S D c l o c k s e l e c t i o n b i t s O C G O C G Since the main clock is used as the clock for OSD, the oscillation frequency is limited. Because of this, the character size in width (horizonal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P3 and P34 respectively. The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode.

• a ceramic resonator only for OSD and a feedback resistor
• a quartz-crystal oscillator only for OSD and a feedback resistor b 1 The clock for OSD is supplied by connecting RC or LC across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. F u n c t i o n O S D o s c i l l a t i o n f r e q u e n c y f XI N ) The clock for OSD is supplied by connecting LC across the pins OSC1 and OSC2. In the bi-scan mode, be sure to set this. Fix this bit to “0.” 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 107 of 124 REJ03B0136-0100Z Address 00D516 b7b 6 b 5b 4b 3 b 2b 1b0 P W M o u t p u t c o n t r o l r e g i s t e r 1 ( P W ) [ A d d r e s s 0 0 D 5 B After reset RW PWM Output Control Register 1 Name F u n c t i o n s D A1, D A2, PW M count source selection bit (PW 0) 0 : C o u n t s o u r c e s u p p l y C o u n t s o u r c e s t o p P 00/ P W M 0 o u t p u t s e l e c t i o n b i t P W 0 : P 00 o u t p u t P W M o u t p u t P 01/ P W M 1 o u t p u t s e l e c t i o n b i t P W 0: P01 output 1: PWM1 output P02/PWM2 output selection bit (PW4) 0 : P 02 o u t p u t P W M o u t p u t selection bit (PW5) 0 : P 03 o u t p u t P W M o u t p u t selection bit (PW6) 0 : P 04 o u t p u t P W M o u t p u t D A 1 o u t p u t / P 35 s e l e c t i o n b i t P W 0 : D A 1 o u t p u t P o u t p u t selection bit (PW7) 0 : P 05 o u t p u t P W M o u t p u t 16] RW RW RW RW RW RW RW RW b7b6 b5b4b3 b2b1b0 PWM output control register 2 (PN) [Address 00D6 B A f t e r r e s e t RW P W M O u t p u t C o n t r o l R e g i s t e r 2 0 , 1 N a m e Functions D A 1 o u t p u t p o l a r i t y s e l e c t i o n b i t P N 0 : Positive polarity 1 : Negative polarity P W M o u t p u t p o l a r i t y s e l e c t i o n b i t P N F i x t h e s e b i t s t o “ 0 . ” D A 2 o u t p u t p o l a r i t y s e l e c t i o n b i t P N 0 : Output LOW 1 : Output HIGH 6 , 7 0F i x t h e s e b i t s t o “ 0 . ” 0 : Positive polarity 1 : Negative polarity 16] R RW RW RW RW 0000 s e l e c t i o n b i t P N 0 : P17 1 : DA2 0 RW W Address 00D616

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 108 of 124 REJ03B0136-0100Z Address 00D716 b 7 b 6 b 5 b 4 b 3 b 2 b1 b0 I2C d a t a s h i f t r e g i s t e r S A d d r e s s D B F u n c t i o n s A f t e r r e s e t R W I C Data Shift Register t o T h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a I n d e t e r m i n a t e N ote: 2T o w r i t e d a t a i n t o t h e I C d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e M S T b i t t o s l a v e m o d e k e e p a n i n t e r v a l o f m a c h i n e c y c l e s o r m o r e N a m e D 0 to D 7 R W Address 00D816 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 R B W t o S l a v e a d d r e s s S A D t o S A D <O nly in 10-bit addressing (in slave) mode> The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) I n b o t h m o d e s > T h e a d d r e s s d a t a i s c o m p a r e d I2C A d d r e s s R e g i s t e r I2C a d d r e s s r e g i s t e r S D A d d r e s s D B Nam e F u n c t i o n s After resetR W R W

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 109 of 124 REJ03B0136-0100Z Address 00D916 Address 00DA 16 b7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 I2C s t a t u s r e g i s t e r S A d d r e s s D I2C S t a t u s R e g i s t e r 6 , 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode B N a m e Functions After resetR W C ommun ication mode specification bits (TRX, MST) 0 : Bus free 1 : Bus busy B u s b u s y f l a g ( B B ) 0 : Interrupt request issued 1 : No interrupt request issued I2C-BUS interface interrupt request bit (PIN) 0 : N ot detected 1 : Detected A r b i t r a t i o n l o s t d e t e c t i n g f l a g A L S e e n o t e 0 : Address mismatch 1 : Address match S l a v e a d d r e s s c o m p a r i s o n f l a g A A S S e e n o t e 0 : N o general call detected 1 : General call detected G e n e r a l c a l l d e t e c t i n g f l a g A D S e e n o t e 0 : Last bit = “0 ” 1 : Last bit = “1 ” L a s t r e c e i v e b i t ( L R B ) S e e n o t e N o t e : T h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . I n d e t e r m i n a t e R— RW R W ( S e e n o t e ) ( S e e n o t e ) ( S e e n o t e ) ( S e e n o t e ) b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 t o B i t c o u n t e r N u m b e r o f t r a n s m i t r e c i e v e b i t s B C t o B C b 2 b 1 b 0

3 I2C

B U S i n t e r f a c e u s e e n a b l e b i t E S O 0 : D i s a b l e d E n a b l e d b i t A L S 0 : A d d r e s s i n g f o r m a t F r e e d a t a f o r m a t b i t B I T S A D 0 : 7 - b i t a d d r e s s i n g f o r m a t b i t a d d r e s s i n g f o r m a t 6 , 7 C o n n e c t i o n c o n t r o l b i t s b e t w e e n I C B U S i n t e r f a c e a n d p o r t s B S E L B S E L b 7 b 6 C o n n e c t i o n p o r t ( S e e n o t e ) N o n e S C L S D A S C L S D A S C L S D A S C L S D A I2C c o n t r o l r e g i s t e r S D A d d r e s s D I2C Control Register B N a m e F u n c t i o n s After reset R W R W R W R W R W R W N o t e W h e n u s i n g p o r t s P 11- P a s I2C B U S i n t e r f a c e t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m C M O S o u t p u t t o N c h a n n e l o p e n d r a i n o u t p u t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 110 of 124 REJ03B0136-0100Z Address 00DB 16 b 7 b 6 b5 b 4 b3 b 2 b 1 b 0 I2C clock control register (S2) [Address 00DB16] I2C C l o c k C o n t r o l R e g i s t e r t o S C L f r e q u e n c y c o n t r o l b i t s C C R t o C C R S C L m o d e s p e c i f i c a t i o n b i t F A S T M O D E 0 : S t a n d a r d c l o c k m o d e H i g h s p e e d c l o c k m o d e 0S t a n d a r d c l o c k m o d e B N a m e F u n c t i o n s A f t e r r e s e t R W ACK bit (ACK BIT) A C K c l o c k b i t A C K 0: ACK is returned. 1: ACK is not returned. 0 : N o A C K c l o c k A C K c l o c k High speed clock mode S e t u p d i s a b l e d Setup disabled00 to 02 S e t u p d i s a b l e d 33303 S e t u p d i s a b l e d 25004 100 400 (See note)05 83.3 16606 C C R v a l u e 1000/C C R value . . . 17.2 3 4 . 51D 16.6 33.31E 16.1 32.31F (at φ = 4 MH z, unit : kHz) N o t e : A t 4 0 0 k H z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . p e r i o d p e r i o d I n t h e o t h e r c a s e s t h e d u t y i s a s b e l o w p e r i o d p e r i o d S e t u p v a l u e o f C C R C C R

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 111 of 124 REJ03B0136-0100Z Address 00DC 16 b7b6 b5b4b3 b2b1b0 S e r i a l I / O m o d e r e g i s t e r ( S M ) [ A d d r e s s 0 0 D C 1 BN a m eF u n c t i o n s A f t e r r e s e t RW S e r i a l I / O M o d e R e g i s t e r 0 , 1I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s S M S M b1 b0 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 s e l e c t i o n b i t S M s e l e c t i o n b i t S M s e l e c t i o n b i t S M 0 : P 20, P 21 SC L SO U T 0 : E x t e r n a l c l o c k I n t e r n a l c l o c k 0 : L S B f i r s t M S B f i r s t 0 RW RW RW R W RW RW 4 F i x t h i s b i t t o “ 0 . ” 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0R — Serial input pin selection bit (SM6) 0: Input signal from SIN pin. 1: Input signal from SO U T pin. A - D C o n t r o l R e g i s t e r b 7 b6 b 5 b 4 b 3 b 2 b 1 b 0 A - D c o n t r o l r e g i s t e r ( A D C O N ) [ A d d r e s s 0 0 D F1 B A f t e r r e s e tRW t o A n a l o g i n p u t p i n s e l e c t i o n b i t s A D I N t o A D I N N a m eF u n c t i o n s b 2 b 1 b 0 A D A D A D A D A D A D A D A D 4 VC C c o n n e c t i o n s e l e c t i o n b i t A D V R E F 0 : O F F O N 6 N othing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. RW RW b i t A D S T R 0 : C o n v e r s i o n i n p r o g r e s s C o n v e r t i o n c o m p l e t e d 1 RW 7 F i x t h i s b i t t o “ 0 . ” RW I n d e t e r m i n a t e 5 F i x t h i s b i t t o “ 0 . ” RW0 Address 00DF16

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 112 of 124 REJ03B0136-0100Z Address 00E016 b 7b 6b 5b 4b 3b 2b 1b 0 B l o c k i V r e g i s t e r ( B i V P ) ( i = 1 , 2 ) [ A d d r e s s e s 0 0 E 11 6 a n d 0 0 E 21 BN a m eF u n c t i o n s After reset R W B l o c k i V R e g i s t e r t o Control bits of vertical display start positions (BiVP0 to BiVP7) (See note 1) I n d e t e r m i n a t e RW N o t e : S e t v a l u e s e x c e p t “ 0 01 6” t o B i V P . V e r t i c a l d i s p l a y s t a r t p o s i t i o n s H d e f H n n s e t t i n g v a l u e H d e H H H S Y N C ) Addresses 00E116 and 00E216 b 7b 6b 5b 4b 3b 2b 1b 0 H o r i z o n t a l p o s i t i o n r e g i s t e r ( H P ) [ A d d r e s s 0 0 E 01 BN a m e F u n c t i o n s B l o c k H R e g i s t e r C o n t r o l b i t s o f h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n s B H P t o B H P S e e n o t e t o N o t e : T h e s e t t i n g v a l u e s y n c h r o n i z e s w i t h t h e VS Y N C . 6 , 7 N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e A f t e r r e s e tRW 0R W 0R — H orizontal display start positions = Tdef1 + 4TO SC ✕ n (n: setting value, Tdef1: 31TOSC , TOSC : OSD oscillation cycle)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 113 of 124 REJ03B0136-0100Z Address 00E316 b7 b 6 b5 b4 b 3 b 2 b 1 b 0 S P R I T E c o n t r o l r e g i s t e r ( S C ) [ A d d r e s s 0 0 E 31 B N ame F u n c t i o n s A f t e r r e s e t R W S P R I T E C o n t r o l R e g i s t e r 0, 1 4 , 5 S P R I T E f o n t 1 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t S C S C 0 WR WR N ote : This bit is valid when bit 0 of the OSD control register to “1.” 2, 3 S P R I T E f o n t 2 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t S C S C 0 WR 6, 7 SPRITE/raster patterning control bit (SC6, SC7) (See note) WR S P R I T E f o n t s e l e c t i o n b i t S C S C SC 5 SC 4 Ch aracter code SPRITE1 SPRITE2 F816 FA 16 FC 16 FE 16 F 91 F F D 1 F S C 1 S C 0 C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r S C 3 S C 2 C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r C o l o r r e g i s t e r SC 7 SC 6 0 0: Display OFF 0 1: Do not set 1 0: SPRITE display 1 1: Raster patterning display

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 114 of 124 REJ03B0136-0100Z Address 00E416 b7 b6 b5b4 b3 b2b1 b0 S P R I T E H r e g i s t e r ( S H P ) [ A d d r e s s 0 0 E 41 BName Functions SPRITE H Register t o H orizontal display start position control bits of SPR ITE O SD (SH P0 to SH P7) H orizontal display start position = Tdef2 + 2TO SC n (n: setting value, Tdef2: 2TO SC , TO SC : O SD oscillation cycle) After reset R W RW0 N o t e s 1 : S e t v a l u e s e x c e p t “ 0 01 6” t o “ 0 21 6” t o S H P . W h e n s e l e c t i n g r a s t e r p a t t e r n i n g d i s p l a y s e t t i n g v a l u e i s s y n c h r o n i z e d w i t h VS Y N C s i g n a l w h e n s e l e c t i n g S P R I T E d i s p l a y i t i s n o t s y n c h r o n i z e d Address 00E516 b 7b 6b 5b 4b 3b 2b 1b 0 S P R I T E V r e g i s t e r ( S V P ) [ A d d r e s s 0 0 E 51 BN a m e Functions S P R I T E V R e g i s t e r t o H o r i z o n t a l d i s p l a y s t a r t p o s i t i o n c o n t r o l b i t s o f S P R I T E O S D S V P t o S V P S e e n o t e H o r i z o n t a l d i s p l a y s t a r t p o s i t i o n H d e f + H n n s e t t i n g v a l u e H d e H H H S Y N C ) N o t e : S e t v a l u e s e x c e p t “ 0 01 6” t o t h e S V P . After reset R W RWI n d e t e r m i n a t e

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 115 of 124 REJ03B0136-0100Z Addresses 00E616 to 00E916 and 00EC16 to 00EF16 b7 b6 b5 b4 b3 b2 b1 b0 C o l o r r e g i s t e r i ( C O 1 t o C O 8 ) ( i = 1 t o 8 ) [ A d d r e s s e s 0 0 E 61 6 t o 0 0 E 91 6, 0 0 E C 1 6 t o 0 0 E F1 B N ame F u n c t i o n s A f t e r r e s e t R W C olor Register i

1 G s i g n a l o u t p u t s e l e c t i o n

b i t C O i 0 : N o o u t p u t O u t p u t R W b i t C O i 0 : N o o u t p u t O u t p u t R W s e l e c t i o n b i t C O i 0 : N o o u t p u t O u t p u t R W s e l e c t i o n b i t C O i 0 : N o o u t p u t O u t p u t R W s e l e c t i o n b i t C O i 0: N o output 1: Output R W C O i 0 : C h a r a c t e r o u t p u t B l a n k o u t p u t R W 7 0 R — R s i g n a l o u t p u t s e l e c t i o n b i t C O i 0 : N o o u t p u t O u t p u t N othing is assined. This bit is a write disable bit. When this bit is read out, the value is “0.” Indeterm inate Indeterm inate Indeterm inate Indeterm inate Indeterm inate Indeterm inate

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 116 of 124 REJ03B0136-0100Z Address 00EA16 b 3 b 2 ( S e e n o t e s 3 a n d 4 ) 0 0 S t a n d a r d 0 1 S t a n d a r d TO S C 1 0 S t a n d a r d TO S C 1 1 S t a n d a r d TO S C b 7b 6b 5b 4b 3b 2b 1b 0 O S D c o n t r o l r e g i s t e r ( O C ) [ A d d r e s s 0 0 E A1 BN a m e F u n c t i o n s After resetR W O S D C o n t r o l R e g i s t e r

0 O S D c o n t r o l b i t

O C S e e n o t e 0 : A l l - b l o c k s d i s p l a y O F F A l l b l o c k s d i s p l a y O N b i t O C 0 : A l l b o r d e r e d S h a d o w b o r d e r e d S e e n o t e 2 , 3 0

4 Window control bit

(OC4) W i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t O C O C RW RW RW RW 6R a s t e r c o l o r O U T 1 c o n t r o l b i t O C 0 : Window OFF 1 : Window ON 0R W

5 Scan mode selection

bit (OC5) 0R W0 : Normal scan mode 1 : Bi-scan mode (See note 5) Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC . 2 : Shadow border is output at right and bottom side of the font. 3 : TOSC = OSD oscillation cycle 4 : These bits are vallid for both left border and right border (for detail, refer to “(8) Window Function.”) 5 : When setting to bi-scan mode, connect LC between pins OSC1 and OSC2. 0 : N o o u t p u t O u t p u t 7R a s t e r c o l o r O U T 2 c o n t r o l b i t O C 0R W0 : N o o u t p u t O u t p u t

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 117 of 124 REJ03B0136-0100Z Address 00EB16 b7 b 6 b 5 b 4 b 3 b 2 b 1 b0 OSD I/O polarity register (OPC) [Address 00EB16] B N ame Functions A f t e r r e R W OSD I/O Polarity Register Y N C i n p u t p o l a r i t y s w i t c h b i t O P C 0 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t 1 0 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t b i t O P C 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t 3 0 VS Y N C i n p u t p o l a r i t y s w i t c h b i t O P C R W R W R W R W s w i t c h b i t O P C 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

5 R aster color R control

bit (OPC5) 0 : N o o u t p u t O u t p u t

6 R aster color G control bit

(OPC6)

7 R aster color B control bit

(OPC7) 0 : N o output 1 : Output R W R W R W R W O U T 1 o u t p u t p o l a r i t y s w i t c h b i t O P C 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t 0 : N o output 1 : Output

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 118 of 124 REJ03B0136-0100Z Address 00F416 Address 00F516 b 7b 6 b 5b 4b 3 b 2b 1b 0 T i m e r m o d e r e g i s t e r 1 ( T M 1 ) [ A d d r e s s 0 0 F 41 B A f t e r r e s e t W T i m e r M o d e R e g i s t e r 1 N a m e Functions T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t T M 0 : f ( XI N ) / 1 6 f XI N ) T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t T M 0 : I n t e r r u p t c l o c k s o u r c e E x t e r n a l c l o c k f r o m T I M p i n T i m e r 1 c o u n t s t o p b i t T M 0 : C o u n t s t a r t C o u n t s t o p Timer 2 count stop bit (TM13) 0: Count start 1: Count stop T i m e r 2 i n t e r n a l c o u n t s o u r c e s e l e c t i o n b i t T M R WR WR WR WR WR0: f(XIN)/16 1: Timer 1 overflow 5 < A t e x e c u t i o n o f S T P i n s t r u c t i o n T i m e r s a n d a u t o s e t d i s a b l e b i t T M 0 : A u t o s e t e n a b l e d A u t o s e t d i s a b l e d 0 WR 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R b 7b6 b 5b 4b 3 b 2b 1b 0 Timer mode register 2 (TM2) [Address 00F516] B After reset RW T i m e r M o d e R e g i s t e r 2 N a m e Functions T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t T M 0 RW

1 T i m e r 4 i n t e r n a l

i n t e r r u p t c o u n t s o u r c e s e l e c t i o n b i t T M 0 RW Timer 3 count stop bit (TM22) 0: Count start 1: Count stop T i m e r 4 c o u n t s t o p b i t T M 0: Count start 1: Count stop s e l e c t i o n b i t T M 0 : I n t e r n a l c l o c k s o u r c e f XI N ) s o u r c e s e l e c t i o n b i t T M 0: TIM3 pin input 1: H SYNC pin input RW RW RW RW 0 : f ( XI N ) / 1 6 E x t e r n a l c l o c k s o u r c e 0 : T i m e r 3 o v e r f l o w s i g n a l f XI N ) 6 , 7N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e 0— R

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 119 of 124 REJ03B0136-0100Z Addresses 00F916 and 00FA16 Address 00FB16 b 2b 1b 0 D i s p l a y m o d e ✕ 0 0 D i s p l a y O F F 0 0 1 O S D m o d e n o b o r d e r 0 1 0 B U T T O N m o d e n o b o r d e r 1 0 1 O S D m o d e b o r d e r 1 1 0 B U T T O N m o d e b o r d e r b 7b 6b 5b 4b 3b 2b 1b 0 Block i control register (BiC) (i = 1, 2) [Addresses 00F916, 00FA16] BN a m e Functions A f t e r r e s e t R W B l o c k i C o n t r o l R e g i s t e r t o D i s p l a y m o d e s e l e c t i o n b i t s B i C t o B i C I n d e t e r m i n a t e 3, 4 Dot size selection bit (BiC3, BiC4) RW RW Notes 1 : TOSC = OSD oscillation cycle 2 : H = HSYNC b4b3 Dot size 0 0 1TOSC ✕ 1H 0 1 Do not set 1 0 2TOSC ✕ 2H 1 1 3TOSC ✕ 3H to 0N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e Indeterm inate C P U M o d e R e g i s t e r b7b6 b5b4b3 b2b1b0 B A f t e r r e s e t R W 0 , 1 3 t o 5 N a m e Functions Processor mode bits (CM0, CM1) 0 0: Single-chip mode 0 1: 1 0: Not available 1 1: F i x t h e s e b i t s t o “ 1 . ” 1Stack page selection bit (CM2) (See note) b1 b0 0 : 0 p a g e p a g e 1 00 6, 7 0 C P U m o d e r e g i s t e r ( C M ) [ A d d r e s s 0 0 F B1 R W R W R W R W Note: This bit is set to “1” after the reset release. 100 F i x t h e s e b i t s t o “ 0 . ”

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 120 of 124 REJ03B0136-0100Z Address 00FC16 Address 00FD16 b 7b 6 b 5b 4b 3 b 2b1b0 I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 0 0 F C BN a m e Functions A f t e r r e s e t RW I n t e r r u p t R e q u e s t R e g i s t e r 0 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d T i m e r 1 i n t e r r u p t r e q u e s t b i t T M R

1 Timer 2 interrupt

request bit (TM2R) r e q u e s t b i t T M R 3T i m e r 4 i n t e r r u p t r e q u e s t b i t T M R bit (OSDR) 5 VS Y N C i n t e r r u p t r e q u e s t b i t V S C R 6 M u l t i m a s t e r I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t I I C R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o interrupt request issued 1 : Interrupt request issued 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ ✽: “0” can be set by software, but “1” cannot be set. R R R R R R R RI N T 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t I T R 0 : N o interrupt request issued 1 : Interrupt request issued b 7b 6b 5b 4b 3 b 2b 1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 0 0 F D BNam e Functions A f t e r r e s e t RW I n t e r r u p t R e q u e s t R e g i s t e r 2 request bit (IT1R) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d r e q u e s t b i t S R 4 f ( XI N ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t M S R 7 F i x t h i s b i t t o “ 0 . ” 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t 0 ✽ 0 ✽ 0 ✽ 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 16] R R R R ✽ R R — R W S P R I T E O S D i n t e r r u p t r e q u e s t b i t S P R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d r e q u e s t b i t A D R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” INT2 external interrupt request bit (IT2R)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 121 of 124 REJ03B0136-0100Z Addresses 00FE16 Address 00FF16 b 7b 6 b 5b 4b 3 b 2b 1b0 I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 0 0 F E1 BName F u n c t i o n s RW I n t e r r u p t C o n t r o l R e g i s t e r e n a b l e b i t T M E 0 : Interrupt disabled 1 : Interrupt enabled e n a b l e b i t T M E e n a b l e b i t T M E O S D E 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW RW RW R T i m e r 4 i n t e r r u p t e n a b l e b i t T M E 0 : Interrupt disabled 1 : Interrupt enabled 5 VS Y N C i n t e r r u p t e n a b l e b i t V S C E 0 : Interrupt disabled 1 : Interrupt enabled 0 RW 6 0 : Interrupt disabled 1 : Interrupt enabled 0 RW A f t e r r e s e t I N T 3 e x t e r n a l i n t e r r u p t e n a b l e b i t I T E M ulti-m aster I2C -BU S interface interrupt enable bit (IIC E) 0 : Interrupt disabled 1 : Interrupt enabled W b 7b 6 b 5b 4b 3 b 2b 1b 0 Interrupt control register 2 (ICON2) [Address 00FF16] BName Functions After resetRW I n t e r r u p t C o n t r o l R e g i s t e r e n a b l e b i t I T E 0 : Interrupt disabled 1 : Interrupt enabled e n a b l e b i t I T E e n a b l e b i t S E 4 f ( XI N ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t M S E 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 RW RW RW RW RW S P R I T E O S D i n t e r r u p t e n a b l e b i t S P E 0 : Interrupt disabled 1 : Interrupt enabled 5 F i x t h i s b i t t o “ 0 . ” 0 R e n a b l e b i t A D E 0 : Interrupt disabled 1 : Interrupt enabled 0 RW 7 0 R—N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s W

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 122 of 124 REJ03B0136-0100Z Address 021B16 Address 024116 Address 024016 b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) [ A d d r e s s 0 2 1 B1 B After reset RW R O M C o r r e c t i o n E n a b l e R e g i s t e r 0 : D i s a b l e d E n a b l e d 0 RW

1 V e c t o r 2 e n a b l e b i t ( R C R 1 ) 0

E n a b l e d 0 RW t o F i x t h e s e b i t s t o “ 0 . ” 0 RW 0000 E n a b l e d 0 RW b7 b6 b5 b4 b3 b2 b1 b0 Left border control register (LBR) [Address 024016] B N a m e Functions L e f t B o r d e r C o n t r o l R e g i s t e r C ontrol bits of left border (LBR0 to LBR6) t o Left border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕ W H (n: setting value, Tdef4: 4TOSC , TOSC : OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit) N o t h i n g i s a s s i g n e d . T h i s b i t i s w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s i n d e t e r m i n a t e A f t e r r e s e t R W N ote: Set values fit for LBR ≤ RBR . b7 b6 b5 b4 b3 b2 b1 b0 Right border control register (RBR) [Address 024116] B N a m e F u n c t i o n s R i g h t B o r d e r C o n t r o l R e g i s t e r C ontrol bits of left border (RBR0 to RBR6) to N o t h i n g i s a s s i g n e d . T h i s b i t i s w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s i n d e t e r m i n a t e A f t e r r e s e t R W N o t e : S e t v a l u e s f i t f o r L B R ≤ R B R . Right border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕ W H (n: setting value, Tdef4: 4TOSC , TOSC : OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit)

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 123 of 124 REJ03B0136-0100Z Address 024516 b 7b 6b 5b 4b 3b 2b 1b 0 T o p b o r d e r c o n t r o l r e g i s t e r ( T B R ) [ A d d r e s s 0 2 4 51 BName Functions After resetRW T o p B o r d e r C o n t r o l R e g i s t e r t o C o n t r o l b i t s o f t o p b o r d e r T B R t o T B R T o p b o r d e r p o s i t i o n H d e f H n n s e t t i n g v a l u e H d e H H H S Y N C ) I n d e t e r m i n a t e RW Notes 1: Set values except “0016” to TBR. 2: Set values fit for TBR ≤ BBR. b 7b 6b 5b 4b 3b 2b 1b 0 Bottom border control register (BBR) [Address 024616] BN a m eF u n c t i o n sA f t e r r e s e tR W B o t t o m B o r d e r C o n t r o l R e g i s t e r to C o n t r o l b i t s o f b o t t o m b o r d e r B B R t o B B R I n d e t e r m i n a t e RWBottom border position = Hdef + H ✕ n (n: setting value, Hdef: 17H, H: HSYNC ) N o t e s 1 : S e t v a l u e s e x c e p t “ 0 01 6” t o B B R . : S e t v a l u e s f i t f o r T B R B B R Address 024616

M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 124 of 124 REJ03B0136-0100Z 19. PACKAGE OUTLINE SDIP42-P-600-1.78 Weight(g) JEDEC Code 4.1 Alloy 42/Cu Alloy 42P4B Plastic 42pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° –1 5 ° –– 5 . 5 e 42 22 211 E ce1 A2A1 bb1 b2e L A SEATING PLANE D MMP

REVISION HISTORY

Rev. Date Description Page Summary M37225M6/M8/MA/MC–XXXSP , M37225ECSP

1.00 Nov 01, 2000 – First edition issued

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