M37221EAFP

M37221M4H RENESAS | Alldatasheet

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Technical content

1. DESCRIPTION The M37221M4H/M6H/M8H/MAH-XXXSP/FP are single-chip micro- computers designed with CMOS silicon gate technology. They have a OSD, I2C-BUS interface, and PWM, making them perfect for TV channel selection system. The M37221EASP/FP have a built-in PROM that can be written elec- trically. 2. FEATURES

• Memory size 24K bytes (M37221M6H-XXXSP/FP) 32K bytes (M37221M8H-XXXSP/FP) 40K bytes (M37221MAH-XXXSP/FP, M37221EASP/FP ) 448 bytes (M37221M6H-XXXSP/FP) 576 bytes (M37221M8H-XXXSP/FP) 704 bytes (M37221MAH-XXXSP/FP, M37221EASP/FP ) (ROM correction memory included)
• The minimum instruction execution time
• Subroutine nesting maximum 96 levels (M37221M4H/M6H-XXXSP/FP) maximum 128 levels (M37221M8H/MAH-XXXSP/FP, M37221EASP/FP)
• Programmable I/O ports Note: Only M37221EASP/FP has D-A converter. (at VCC =5.5V, 8 MHz oscillation frequency, and OSD on)
• OSD function (3 lines or more can be displayed by software) Horizontal: 64 levels Vertical: 128 levels 3. APPLICATION TV SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER REJ03B0134-0100Z Rev.1.00 Oct 01, 2002 Rev.1.00 Oct 01, 2002 page 1 of 110 REJ03B0134-0100Z M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 2 of 110 REJ03B0134-0100Z TABLE OF CONTENTS

8.6 MULTI-MASTER I

8.12 SOFTWARE RUNAWAY DETECT FUNCTION ... 74 15. MULTI-MASTER I 2C-BUS BUS LINE CHARACTERISTICS ....81 18.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 3 of 110 REJ03B0134-0100Z P06/INT2/A-D4 XOUT H SYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P30/A-D5 P31/A-D6 RESET OSC1/P3 3 OSC2/P3 4 VCC P17/A-D3 M37221M4H/M6H/M8H/MAH-XXXSP 4. PIN CONFIGURATION Outline 42P4B Fig. 4.1 Pin Configuration (1) (Top View) Outline 42P2R-A/E Fig. 4.2 Pin Configuration (2) (Top View) XOUT P00/PWM0 P 01/ P W M 1 P 02/ P W M 2 P 03/ P W M 3 P 04/ P W M 4 CNV SS XIN VSS P52/R P53/G P54/B P 55/ O U T 1 P 20/ SC L K P 21/ SO U T P 22/ SI N P 10/ O U T 2 P11/SCL1 P26 P27 D-A P32 OSC1/P3 3 OSC2/P3 4 P50/HSYN C P51/VSYN C P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET VC C P15/A-D1/INT3 P14/SDA2 P13/SDA1 P12/SCL2 M37221M4H/M6H/M8H/MAH-XXXFP

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 4 of 110 REJ03B0134-0100Z Outline 42P4B Fig. 4.3 Pin Configuration (3) (Top View) P06/INT2/A-D4 XOUT H SYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P3 3 OSC2/P3 4 VCC P17/A-D3 M37221EASP Outline 42P2R-A/E Fig. 4.4 Pin Configuration (4) (Top View) XO U T P 50/ H S Y N C P51/VSYN C P00/PWM0 P 01/ P W M 1 P 02/ P W M 2 P 03/ P W M 3 P 04/ P W M 4 P 05/ P W M 5 P07/INT1 P 23/ T I M 3 P 24/ T I M 2 P 25 CNV SS XI N VSS P 52/ R P53/G P54/B P 55/ O U T 1 P 20/ SC L K P 21/ SO U T P 22/ SI N P 10/ O U T 2 P 11/ S C L 1 P 12/ S C L 2 P 13/ S D A 1 P 14/ S D A 2 RESET VCC M E A F P P26 P27 D-A P32 OSC1/P3 3 OSC2/P3 4 P06/INT2/A-D4 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 5 of 110 REJ03B0134-0100Z 5. FUNCTIONAL BLOCK DIAGRAM Fig. 5.1 Functional Block Diagram of M37221 OUT1 Clock input Clock output X IN X OUT Reset input V CC V SS CNV SS Clock output for display Input ports P3 OSC1 OSC2 Clock input for display INT2 INT1 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 P5 (4) B G R HSYNC VSYNC A-D comparator 14-bit PWM circuit 8-bit PWM circuit Accumulator A (8) Timer 4T4 (8)Timer 3T3 (8)Timer 2T2 (8)Timer 1T1 (8)Timer count source selection circuit TIM2TIM3 Instruction register (8)Instruction decoder Control signal OSD circuit Stack pointerS (8) Index registerY (8) Index registerX (8) Processor status registerPS (8) 8-bit arithmetic and logical unit Program counterPC L (8) Program counterPC H (8) RAM ROM Data bus Clock generating circuit RESET Address bus SI/O(8) SIN SCLK SOUT INT3 10 9 8 7 65 4 I/O port P0 28 29 3031 32 3334 P1 (8 I/O port P1 15 14 13 1211 3637 P2 (8 I/O port P2 I/O ports P3 0–P3 17 2627 P3 (3 P0 (8 ) Timing output D-A converter (See note) OUT2 Multi-masterI C-BUSinterface2 ROM correction function D-A Notes Only M3722 1EAS P/FP h as D-A converter. Output ports P5 2–P5

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 6 of 110 REJ03B0134-0100Z Parameter Functions Number of basic instructions 71 Number of basic instructions 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre quency) Instruction execution time 8 MHz (maximum) Memory size ROM M37221M4H-XXXSP/FP 16K bytes M37221M6H-XXXSP/FP 24K bytes M37221M8H-XXXSP/FP 32K bytes M37221MAH-XXXSP/FP, 40K bytes M37221EASP/FP RAM M37221M4H-XXXSP/FP 384 bytes (ROM correction memory included) M37221M6H-XXXSP/FP 448 bytes (ROM correction memory included) M37221M8H-XXXSP/FP 576 bytes (ROM correction memory included) M37221MAH-XXXSP/FP, 704 bytes (ROM correction memory included) M37221EASP/FP OSD ROM 8 K bytes OSD RAM 96 bytes tInput/Output ports P0 I/O 8-bit 5 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) P10, P15–P17 I/O 4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin, A-D input pins, INT input pin) P11–P14 I/O 4-bit ✕ 1 (CMOS input/output structure, can be used as multi-master I2C- BUS interface) P20, P21 I/O 2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure, can be used as serial I/O pins) P22–P27 I/O 6-bit ✕ 1 (CMOS input/output structure, can be used as serial input pin, timer external clock input pins) P30, P31 I/O 2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins, D-A conversion output pins <Only M37221EASP/FP>) P32 I/O 1-bit ✕ 1 (N-channel open-drain output structure) P33, P34 Input 2-bit ✕ 1 (can be used as OSD display clock I/O pins) P52–P55 Output 4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins) Serial I/O 8-bit ✕ 1 Multi-master I2C-BUS interface 1 (2 systems) A-D comparator 6 channels (6-bit resolution) D-A converter 2 (6-bit resolution) (Only M37221EASP/FP) PWM output circuit 14-bit ✕ 1, 8-bit ✕ 6 Timers 8-bit timer ✕ 4 ROM correction function 2 vectors Subroutine nesting M37221M4H/M6H-XXXSP/FP 96 levels (maximum) M37221M8H/MAH-XXXSP/FP, 128 levels (maximum) M37221EASP/FP Interrupt <14 sources> INT external interrupt ✕ 3, Internal timer interrupt ✕ 4, Serial I/O interrupt ✕ 1, OSD interrupt ✕ 1, Multi-master I2C-BUS interface interrupt ✕ 1, f(XIN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK interrupt ✕ 1, Reset ✕ 1 Clock generating circuit 2 built-in circuits (externally connected a ceramic resonator or a quartz- crystal oscillator) 6. PERFORMANCE OVERVIEW Table 6.1 Performance Overview

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 7 of 110 REJ03B0134-0100Z Parameter Functions OSD display Number of display characters 24 characters ✕ 2 lines function Dot structure 12 ✕ 16 dots Kinds of characters 256 kinds Kinds of character sizes 3 kinds Character font coloring 1 screen: 8 kinds (per character unit) Display position Horizontal: 64 levels, Vertical: 128 levels Power source voltage 5 V ± 10 % Power dissipation OSD ON 165 mW typ. (at oscillation frequency f(X IN) = 8 MHz, fOSC = 8 MHz) OSD OFF 110 mW typ. (at oscillation frequency f(X IN) = 8 MHz) In stop mode 1.65 mW (maximum) Operating temperature range –10 °C to 70 °C Device structure CMOS silicon gate process Package M37221M4H/M6H/M8H/MAH-XXXSP, 42-pin plastic molded SDIP M37221EASP M37221M4H/M6H/M8H/MAH-XXXFP, 42-pin plastic molded SSOP M37221EAFP Table 6.2 Performance Overview (continued)

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 8 of 110 REJ03B0134-0100Z 7. PIN DESCRIPTION Table 7.1 Pin Description Power source CNV SS Reset input Clock input Clock output I/O port P0 PWM output External interrupt input Analog input I/O port P1 OSD output Multi-master I 2C-BUS interface Analog input External interrupt input I/O port P2 Timer external clock input Serial I/O synchro- nizing clock input/ output Serial I/O data input/output I/O port P3 Analog input D-A conversion output Input port P3 Clock input for OSD Clock output for OSD V CC , VSS. CNV SS RESET XIN XOUT P00/PWM0– P05/PWM5, P06/INT2/ A-D4, P07/INT1 P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/A-D1/ INT3, 6/A-D2, P17/A-D3 P20/SCLK , P21/SOUT , P22/SIN, P23/TIM3, P24/TIM2, P25–P27 P30/A-D5/ DA1, 1/A-D6/ DA2, P33/OSC1, P34/OSC2 Input Input Output I/O Output Input Input I/O Output I/O Input Input I/O Input I/O I/O I/O Input Output Input Input Output Apply voltage of 5 V ± 10 % (typical) to VCC , and 0 V to VSS . This is connected to VSS . To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. This is the input pin for the main clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins X IN and XOUT . If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with a direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output (See note 1.) Output Pins P0 0 to P05 are also used as PWM output pins PWM0 to PWM4, respectively. The output structure is N-channel open-drain output. Pins P06, P07 are also used as external interrupt input pins INT2 and INT1 respectively. P06 pin is also used as analog input pin A-D4. I/O Port P1 is a 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output (See note 1.) Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output. Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P15–P17 are also used as analog input pins A-D1 to A-D3 respectively. P15 pin is also used as external interrupt input pin INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. The output structure is CMOS output (See note 1.) Pins P23, P24 are also used as timer external clock input pins TIM3, TIM2 respectively. P20 pin is also used as serial I/O synchronizing clock input/output pin SCLK . The output structure is N-channel open-drain output. Pins P21, P22 are also used as serial I/O data input/output pins SOUT , SIN respectively. The output structure is N-channel open-drain output. Ports P30–P32 are a 3-bit I/O port and has basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected as the port P30 and P31. The output structure of port P32 is N-channel open-drain output. (See notes 1, 2) Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively. Pins P30, P31 are also used as D-A conversion output pins DA1, DA2 respectively. (See note 3) Ports P33, P34 are a 2-bit input port. P33 pin is also used as OSD clock input pin OSC1. P34 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. Pin Name Name Input/ Output

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 9 of 110 REJ03B0134-0100Z Table 7.2 Pin Description (continued) Output port P5 OSD output H SYNC input VSYNC input DA output P52/R, P53/G, P54/B, P55/OUT1 H SYNC VSYNC D-A Ports P52–P5 5 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output structure is CMOS output. This is a horizontal synchronizing signal input for OSD. This is a vertical synchronizing signal input for OSD. This is a 14-bit PWM output pin. Output Output Input Input Output Note 1 : Port Pi (i = 0 to 3) has a port Pi direction register that can be used to program each bit for input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data is written into the port latch and then output. When data is read from the output pins, the data of the port latch, not the output pin level, is read. This allows a previously output value to be read correctly even if the output LOW voltage has risen due to, for example, a directly-driven light emitting diode. The input pins are in the floating state, so the values of the pins can be read. When data is written to the input pin, it is written only into the port latch, while the pin remains in the floating state. 2 : To swich output structures, set by the following bits. P30 : bit 0 of port P3 output mode control register P31 : bit 1 of port P3 output mode control register When “0,” CMOS output; when “1,” N-channel open-drain output. 3: Only M37221EASP/FP have a built-in D-A converter.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 10 of 110 REJ03B0134-0100Z Fig. 7.1 I/O pin block diagram (1) N-channel open-drain output Ports P06, P07 Note: Each port is also used as follow: P06 : INT2/A-D4 P07 : INT1 N-channel open drain output Ports P00–P05, P32 Note: Each port is also used as follows: P00–P05 : PWM0–PWM5 CMOS output Ports P1, P2, P30, P31 Notes 1: Each port is also used as follows: P10 : OUT2 P2 0 : SCLK P11 : SCL1 P2 1 : SOUT P12 : SCL2 P2 2 : SIN P13 : SDA1 P2 3 : TIM3 P14 : SDA2 P2 4 : TIM2 P15 : A-D1/INT3 P30 : A-D5/DA1 P16 : A-D2 P3 1 : A-D6/DA2 P17 : A-D3 2: The output structure of ports P11–P14 is N-channel open-drain output when using as multi-master I2C-BUS inter face (it is the same with ports P06 and P07 ) 3: The output structure of ports P30 and P31 can be selected either CMOS output or N-channel open-drain output (it is the same with ports P06 and P07 ) Data bus Direction register Port latch Data bus Direction register Port latch Data bus Direction register Port latch Ports P00–P05, P32 Ports P1, P2, P30, P31 Ports P06, P07

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 11 of 110 REJ03B0134-0100Z CMOS output D-A, R, G, B, OUT1, OUT2 Note: Each pin is also used as below: R : P5 G : P53 B : P54 OUT1 : P55 OUT2 : P10 Fig. 7.2 I/O pin block diagram (2) Schmidt input H SYNC , VSYNC Internal circuit D-A, R, G, B, OUT1, OUT2H SYNC , VSYNC Internal circuit

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 12 of 110 REJ03B0134-0100Z 8. FUNCTION BLOCK DESCRIPTION

8.1 CENTRAL PROCESSING UNIT (CPU)

This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Availability of 740 Family instructions is as follows: The FST and SLW instructions cannot be used. The MUL, DIV, WIT and STP instructions can be used.

8.1.1 CPU Mode Register

The CPU mode register includes a stack page selection bit and inter- nal system clock selection bit. The CPU mode register is allocated to address 00FB 16. Fig. 8.1.1 CPU Mode Register B A f t e r r e s e t RW 0 , 1 3 to 7 Indeterminate Indeterminate Name F u n c t i o n s F i x t h e s e b i t s t o “ 1 . ” 1Stack page selection bit (CM2) (See note) 0: 0 page 1: 1 page CPU mode register (CM) [Address 00FB16] R W RW R W N o t e : T h i s b i t i s s e t t o “ 1 ” a f t e r t h e r e s e t r e l e a s e . b 7b 6b 5b4b 3 b 2b 1b 0 C P U M o d e R e g i s t e r 11 00111 F i x t h e s e b i t s t o “ 0 . ”

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 13 of 110 REJ03B0134-0100Z

8.2 MEMORY

8.2.1 Special Function Register (SFR) Area

The special function register (SFR) area in the zero page includes control registers such as I/O ports and timers.

8.2.2 RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

8.2.3 ROM

ROM is used for storing user programs as well as the interrupt vector area.

8.2.4 OSD RAM

RAM used for specifying the character codes and colors for display.

8.2.5 OSD ROM

ROM used for storing character data for display.

8.2.6 Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

8.2.7 Zero Page

The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area is pos- sible with only 2 bytes in the zero page addressing mode.

8.2.8 Special Page

The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area is possible with only 2 bytes in the special page addressing mode.

8.2.9 ROM Correction Memory (RAM)

This is used as the program area for ROM correction. Fig. 8.2.1 Memory Map (M37221M4H/M6H-XXXSP/FP) 0 0 0 01 00C0 16 00FF16 0 1 B F1 06B716 A 0 0 01 SFR area Not used Not used N o t u s e d F F F F1 F F D E1 FF0016 060016 I n t e r r u p t v e c t o r a r e a N o t u s e d 1000016 11FFF 16 1FFFF 16 OSD ROM (8K bytes) S p e c i a l p a g e OSD RAM (96 bytes) (See note) Zero page Note: Refer to Table 8.11.4 OSD RAM. ■ M 3 7 2 2 1 M 4 H/M6H - X X X S P / F P C000 16 0 1 7 F1 M37221 M6H- XXXSP/FP RAM (448 bytes) ROM (16K bytes) ROM (24K bytes) M3 7221M6H- XXXSP/FP M 37221M4H- XXXSP/FP 02FF16 C 016 02E016 RO M correction function Vector 1: address 02C016 Vector 2: address 02E016 M3 7221M4H- XXXSP/FP RAM (384 bytes)

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 14 of 110 REJ03B0134-0100Z Fig. 8.2.2 Memory Map (M37221M8H/MAH-XXXSP/FP, M37221EASP/FP) 0 0 0 01 00C0 16 00FF16 0 1 F F1 06B716 6 0 0 01 SFR area N o t u s e d F F F F1 F F D E1 FF0016 0 6 0 01 Interrupt vector area Not used 1 0 0 0 01 11FFF 16 1FFFF 16 OSD ROM (8K bytes) S p e c i a l p a g e O S D R A M b y t e s S e e n o t e Zero page M 37221M8H- XXXS P/FP RAM (576 bytes) 0 3 B F1 0 3 0 01 02FF16 0 2 C 01 021716 N o t u s e d 2 p a g e r e g i s t e r N o t u s e d 021B16 Note: Refer to Table 8.11.4 OSD RAM. ■ M 3 7 2 2 1 M 8H/MAH-XXXSP/FP , M 3 7 2 2 1 E A S P / F P 02E016 033F16 80 0 01 RO M correction function Vector 1: address 02C016 Vector 2: address 02E016 N o t u s e d M 3 7 2 2 1 M 8 H- X X X S P/FP R A M K b y t e s M37221MAH- XXXSP/FP, M 37221EASP/FP RAM (40K bytes) M37221MAH- XXXSP /FP, M 37221EASP/FP RAM (704 bytes)

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 15 of 110 REJ03B0134-0100Z Fig. 8.2.3 Memory Map of Special Function Register (SFR) (1) P 3 0 SP31S PW0PW1PW2PW3PW4PW5PW6PW7 PN2PN3PN4 SM0SM1SM2SM3SM5SM6 001 0016 0016 000 00 ???? 0016 ? ? DA1SDA2S DA10DA11DA12DA13DA14DA15 D A 2 0DA21DA22DA23DA24DA25 SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RB W LRBAD0AASALPINBBTRXMST BC0BC1BC2ES0ALS10BIT SADBSEL 0BSEL 1 CCR0CCR1CCR2CCR3CCR4FAST MODE ACK BITACK 0016 0016 0016 000 001 ?0 D 01 D 11 D 21 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 C 01 C 11 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C 91 C B1 C C 1 C D 1 C E1 C F1 CA 16 Port P5 (P5) P o r t P 5 d i r e c t i o n r e g i s t e r ( D 5 ) P o r t P 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( P 3 S ) ( N o t e 1 ) D A - H r e g i s t e r ( D A - H ) D A - L r e g i s t e r ( D A - L ) P W M 0 r e g i s t e r ( P W M 0 ) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) R e g i s t e r P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( D 0 ) P W M 1 r e g i s t e r ( P W M 1 ) P W M 2 r e g i s t e r ( P W M 2 ) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Serial I/O mode register (SM) Serial I/O regsiter (SIO) DA1 conversion register (DA1) (Note 2) DA2 conversion register (DA2) (Note 2) I C data shift register (S0)2 I C address register (S0D)2 I C status register (S1)2 I C control register (S1D)2 I C clock control register (S2)2 N o t e 1 : A s f o r , f i x b i t s 2 a n d 3 t o “ 0 . ” d o n o t h a v e t h i s r e g i s t e r F i x t h i s r e g i s t e r t o 0016 0 01 0 01 0016 0016 001 A d d r e s s S F R a r e a a d d r e s s e s C t o D b 7b 0 b 7 b0 Bit allocation S t a t e i m m e d i a t e l y a f t e r r e s e t : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t: F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o F u n c t i o n b i t : N o f u n c t i o n b i t : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “ 0 ” i m m e d i a t e l y a f t e r r e s e t 0 : “ 1 ” i m m e d i a t e l y a f t e r r e s e t < B i t a l l o c a t i o n > S t a t e i m m e d i a t e l y a f t e r r e s e t > M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221M4H/M6H/M8H/MAH-XXXSP/FP

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 16 of 110 REJ03B0134-0100Z Fig. 8.2.4 Memory Map of Special Function Register (SFR) (2) S t a t e i m m e d i a t e l y a f t e r r e s e t b 7 b 0b 7b 0 HR0H R R 2HR3HR4HR5 CV10C V 1 1CV12C V 1 3C V 1 4C V 1 5C V 1 6 CV20C V 2 1CV22C V 2 3C V 2 4C V 2 5C V 2 6 CS10C S 1 1CS20C S 2 1 MD10MD20 CO01C O 0 2CO03C O 0 5 CO11CO12CO13CO15 CO21CO22CO23CO25 CO31C O 3 2CO33C O 3 5 CC0C C C VSYCR /G/BOUT1OP5OP6OP7 HSYC CK0C K ADM0A D M 1ADM2A D M 4 ADC0A D C 1ADC2A D C 4A D C 3A D C 5 T34M 0T 3 4 M 1T34M 2T 3 4 M 3T 3 4 M 4 T12M 0T 1 2 M 1T12M 2T 1 2 M 3T 1 2 M 4 CK0RE5 RE4 RE3 CM2 TM1RTM2RTM3RTM4RCRTRVSCRIT3R C K 0M S R 1 T 1 R1T2RS 1 R T M 1 ETM2ET M 3 ETM4EC R T EV S C EIT3E 1T1E1 T 2 ES 1 EM S E T 3 4 M 5 CK0 0 01 ?0 0 0 0 0 00 FF16 0 71 F F1 0 71 CO04 CO14 CO24 CO34 C O 0 6 CO16 CO26 C O 3 6 CO07 CO17 CO27 CO37 C C OUT2 IICR IICE F016 F 11 F216 F316 F 41 F 51 F 61 F 71 F 81 F916 FA 16 FB 16 FC 16 F D 1 F E1 F F1 E 01 E 11 E 21 E 31 E416 E 51 E616 E716 E 81 E916 E B1 E C 1 ED 16 E E1 E F1 EA 16 A d d r e s s O S D c o n t r o l r e g i s t e r ( C C ) O SD port control register (C R TP) A-D control register 1 (AD1) A-D control register 2 (AD2) T i m e r 1 ( T M 1 ) V e r t i c a l r e g i s t e r 2 ( C V 2 ) C o l o r r e g i s t e r 0 ( C O 0 ) C o l o r r e g i s t e r 1 ( C O 1 ) C h a r a c t e r s i z e r e g i s t e r ( C S ) Border selection register (MD) R e g i s t e r H o r i z o n t a l r e g i s t e r ( H R ) V e r t i c a l r e g i s t e r 1 ( C V 1 ) Timer 2 (TM2) T i m e r 3 ( T M 3 ) T i m e r 4 ( T M 4 ) T i m e r 1 2 m o d e r e g i s t e r ( T 1 2 M ) T i m e r 3 4 m o d e r e g i s t e r ( T 3 4 M ) PWM5 register (PWM5) I n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( R E ) T e s t r e g i s t e r ( T E S T ) Interrupt request register 1 (IR EQ 1) Interrupt request register 2 (IR EQ 2) Interrupt control register 1 (IC O N 1) Interrupt control register 2 (IC O N 2) Color register 2 (CO2) C o l o r r e g i s t e r 3 ( C O 3 ) O S D c l o c k s e l e c t i o n r e g i s t e r ( C K ) CPU mode register (CPUM) B i t a l l o c a t i o n 0 01 0 01 0 01 0 01 0 01 0 01 0 01 0016 0 01 000 0 111 1 10 0 0 00 0016 000 000 0 01 0 ? 0 000???? 0 0000?0? 0000000? 1 1111100 0 01 0 01 0 01 0 01 0 01 S F R a r e a a d d r e s s e s E t o F : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o Function bit : No function bit : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “ 0 ” i m m e d i a t e l y a f t e r r e s e t 0 : “ 1 ” i m m e d i a t e l y a f t e r r e s e t <Bit allocation> <State imm ediately after reset>

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 17 of 110 REJ03B0134-0100Z Fig. 8.2.5 Memory Map of 2 Page Register Area b7 0 b7 0 2 1 71 2 1 81 2 1 91 2 1 B1 2 1 A1 R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) R O M c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) R O M c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) RCR1 RCR0 0016 0016 0016 0016 000 0 16 p a g e r e g i s t e r a r e a a d d r e s s e s t o A d d r e s s R e g i s t e r B i t a l l o c a t i o nS tate immediately after reset : Fix to this bit to “0” (do not write to “1”) F u n c t i o n b i t : N o f u n c t i o n b i t : Fix to this bit to “1” (do not write to “0”) Name : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “ 1 ” i m m e d i a t e l y a f t e r r e s e t N o t e : O n l y M 3 7 2 2 1M4H/M6H/ M 8H / M AH-XXXSP/FP a n d M 3 7 2 2 1 E A S P / F P h a v e 2 p a g e r e g i s t e r. . < B i t a l l o c a t i o n > S t a t e i m m e d i a t e l y a f t e r r e s e t > bb

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 18 of 110 REJ03B0134-0100Z Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset b 7 b0 b 7 b 0 R e g i s t e r P r o c e s s o r s t a t u s r e g i s t e r ( P S ) B i t a l l o c a t i o nS t a t e i m m e d i a t e l y a f t e r r e s e t P r o g r a m c o u n t e r ( P C H ) P r o g r a m c o u n t e r ( P C L) C o n t e n t s o f a d d r e s s F F F F1 C ontents of address FFFE16 : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o Function bit : No function bit : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “1” immediately after reset < B i t a l l o c a t i o n >< S t a t e immediately after reset>

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 19 of 110 REJ03B0134-0100Z Priority

8.3 INTERRUPTS

Interrupts can be caused by 14 different sources comprising 4 exter- nal, 8 internal, 1 software, and 1 reset interrupts. Interrupts are vec- tored interrupts with priorities as shown in Table 8.3.1. Reset is also included in the table as its operation is similar to an interrupt. When an interrupt is accepted, ① The contents of the program counter and processor status regis- ter are automatically stored into the stack. ➁ The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” ➂ The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in Interrupt Request Registers 1 and 2 and the interrupt enable bits the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are ac- cepted when the interrupt enable bit is “1,” interrupt request bit is "1," and the interrupt disable flag is “0.” The interrupt request bit can be set to "0" by a program, but not set to "1." The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt controls.

8.3.1 Interrupt Causes

(1) VSYNC , OSD interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. (2) INT1 to INT3 external interrupts The INT1 to INT3 interrupts are external interrupt inputs, the sys- tem detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The in- put active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00F9 16) : when this bit is “0,” a change from LOW to HIGH is detected; when it is “1,” a change from HIGH to LOW is detected. Note that both bits are cleared to “0” at reset. (3) Timers 1 to 4 interrupts An interrupt is generated by an overflow of timers 1 to 4. Vector Addresses FFFF 16, FFFE16 FFFD 16, FFFC16 FFFB 16, FFFA16 FFF9 16, FFF816 FFF5 16, FFF416 FFF3 16, FFF216 FFF1 16, FFF016 FFEF 16, FFEE16 FFED 16, FFEC16 FFEB 16, FFEA16 FFE9 16, FFE816 FFE7 16, FFE616 FFE5 16, FFE416 FFDF 16, FFDE16 Interrupt Source Reset OSD interrupt INT2 external interrupt INT1 external interrupt Timer 4 interrupt f(X IN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I 2C-BUS interface interrupt INT3 external interrupt BRK instruction interrupt Remarks Non-maskable Active edge selectable Active edge selectable Active edge selectable Non-maskable Table 8.3.1 Interrupt Vector Addresses and Priority

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 20 of 110 REJ03B0134-0100Z (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe- riod. Set bit 0 of PWM output control register 1 to “0.” (6) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (7) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 21 of 110 REJ03B0134-0100Z Fig. 8.3.2 Interrupt Request Register 1 b 7b 6 b 5b 4b 3 b 2b 1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 0 0 F C BN a m e F u n c t i o n s After reset RW I n t e r r u p t R e q u e s t R e g i s t e r 0 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d T i m e r 1 i n t e r r u p t r e q u e s t b i t T M R

1 T i m e r 2 i n t e r r u p t

r e q u e s t b i t T M R

2 Timer 3 interrupt

request bit (TM3R) 3T i m e r 4 interrupt request bit (TM4R)

4 OSD interrupt request

bit (CRTR)

5 VSYNC interrupt

request bit (VSCR) 6 M u l t i m a s t e r I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t I I C R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t R R R R R R R R I N T 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t I T R 0 : N o interrupt request issued 1 : Interrupt request issued Fig. 8.3.3 Interrupt Request Register 2 b 7b 6b 5b 4b 3 b 2b 1b 0 I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 0 0 F D BN a m e Functions A f t e r r e s e t RW I n t e r r u p t R e q u e s t R e g i s t e r

0 INT1 external interrupt

request bit (IT1R) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d

1 INT2 external interrupt

request bit (IT2R)

2 S e r i a l I / O i n t e r r u p t

r e q u e s t b i t S R 4 f ( XI N ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t M S R 5, 6 7 F i x t h i s b i t t o “ 0 . ” 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d ✽: “0” can be set by software, but “1” cannot be set. 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 16] R R R R R — R W0 N othing is assigned. These bits are w rite disable bits. W hen these bits are read out, the values are “0.” 0R —Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.”

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 22 of 110 REJ03B0134-0100Z Fig. 8.3.4 Interrupt Control Register 1 b 7b 6 b 5b 4b 3 b 2b 1b 0 I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 0 0 F E1 BN a m e F u n ctions R W I n t e r r u p t C o n t r o l R e g i s t e r

0 Timer 1 interrupt

enable bit (TM1E) 0 : Interrupt disabled 1 : Interrupt enabled

1 Timer 2 interrupt

enable bit (TM2E) enable bit (TM3E)

4 OSD interrupt enable bit

(CRTE) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW RW RW R Timer 4 interrupt enable bit (TM4E) 0 : Interrupt disabled 1 : Interrupt enabled

5 VSYNC interrupt enable

bit (VSCE) 0 : Interrupt disabled 1 : Interrupt enabled 0 RW 6 0 : Interrupt disabled 1 : Interrupt enabled 0 RW INT3 external interrupt enable bit (IT3E) Multi-master I2C-BU S interface interrupt enable bit (IICE) 0 : Interrupt disabled 1 : Interrupt enabled W After reset Fig. 8.3.5 Interrupt Control Register 2 b 7b 6 b 5b 4b 3 b 2b 1b 0 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 0 0 F F1 BN a m e F u n c t i o n s Interrupt Control Register 2

0 I N T 1 e x t e r n a l i n t e r r u p t

e n a b l e b i t I T E 0 : Interrupt disabled 1 : Interrupt enabled

1 I N T 2 e x t e r n a l i n t e r r u p t

e n a b l e b i t I T E e n a b l e b i t S E 4 f ( XI N ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t M S E 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled F i x t h i s b i t t o “ 0 . ” F i x t h e s e b i t s t o “ 0 . ” 000 After reset RW RW RW RW RW R R W W5 t o 7

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 23 of 110 REJ03B0134-0100Z Fig. 8.3.6 Interrupt Input Polarity Register N a m eF u n c t i o n s I N T 1 p o l a r i t y s w i t c h b i t R E 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y I N T 2 p o l a r i t y s w i t c h b i t R E I N T 3 p o l a r i t y s w i t c h b i t R E N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s Fix These bits to “0.” F i x t h i s b i t t o “ 0 . ” N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s After reset R W R — R W R W R W R W R — R W b 7b 6b 5b 4b 3b 2b 1b 0 I n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( R E ) [ A d d r e s s 0 0 F 9 B I n t e r r u p t I n p u t P o l a r i t y R e g i s t e r 1,2 000

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 24 of 110 REJ03B0134-0100Z

8.4 TIMERS

This microcomputer has 4 timers: timers 1 to 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the correspond- ing timer latch (addresses 00F0 16 to 00F316 : timers 1 to 4), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse, after the count value reaches “00 16.”

8.4.1 Timer 1

Timer 1 can select one of the following count sources:

• f(XIN)/16
• f(XIN)/4096 The count source of timer 1 is selected by setting bit 0 of timer 12 mode register 1 (address 00F416). Timer interrupt request occurs at timer 1 overflow.

8.4.2 Timer 2

Timer 2 can select one of the following count sources:

• f(XIN)/16
• T imer 1 overflow signal
• External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer 12 mode register (address 00F416). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.

8.4.3 Timer 3

Timer 3 can select one of the following count sources:

• f(XIN)/16
• External clock from the HSYNC pin
• External clock from the TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of timer 34 mode register (address 00F516). Timer 3 interrupt request occurs at timer 3 overflow.

8.4.4 Timer 4

Timer 4 can select one of the following count sources:

• f(XIN)/16
• f(XIN)/2
• T imer 3 overflow signal The count source of timer 3 is selected by setting bits 1 and 4 of timer 34 mode register (address 00F516). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set both bit 0 of timer 34 mode register (address 00F516) and bit 6 at address 00C716 to “0” before execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 25 of 110 REJ03B0134-0100Z Fig. 8.4.2 Timer 34 Mode Register b 7b 6 b 5b 4b 3 b 2b 1b 0 Timer 34 mode register (T34M) [Address 00F516] B After reset RW Timer 34 Mode Register N a m e F u n c t i o n s Timer 3 count source selection bit (T34M0) 0 RW

1 Timer 4 internal

selection bit (T34M1) 0R W Timer 3 count stop bit (T34M2) 0: Count start 1: Count stop T i m e r 4 c o u n t s t o p b i t T M 0: Count start 1: Count stop

4 T i m e r 4 c o u n t s o u r c e

s e l e c t i o n b i t T M 0: Internal clock source 1: f(XIN)/2

5 T i m e r 3 e x t e r n a l c o u n t

s o u r c e s e l e c t i o n b i t T M 0 : T I M 3 p i n i n p u t H S Y N C p i n i n p u t RW RW RW RW 0 : f ( XI N ) / 1 6 E x t e r n a l c l o c k s o u r c e 0 : T i m e r 3 o v e r f l o w s i g n a l f XI N ) 6 , 7N othing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R Fig. 8.4.1 Timer 12 Mode Register b 7b 6 b 5b 4b 3 b 2b 1b 0 Timer mode register (T12M) [Address 00F416] B A f t e r r e s e t W T i m e r 1 2 M o d e R e g i s t e r Nam e Functions Timer 1 count source selection bit 1 (T12M0) 0: f(XIN)/16 1: f(XIN)/4096 Timer 2 count source selection bit (T12M1) 0: Interrupt clock source 1: External clock from TIM2 pin Timer 1 count stop bit (T12M2) 0: Count start 1: Count stop Timer 2 count stop bit (T12M3) 0: Count start 1: Count stop Timer 2 internal count source selection bit 2 (T12M4) R WR WR WR WR WR0: f(XIN)/16 1: Timer 1 overflow 5 Fix this bit to “0.” 0 WR 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 26 of 110 REJ03B0134-0100Z Timer 1 (8) 1/2 1/8 Timer 1 latch (8) T12M0 T12M2 T12M4 T12M1 T12M3 Timer 2 (8) Timer 2 latch (8) Timer 3 (8) Timer 3 latch (8) Timer 4 (8) Timer 4 latch (8) Data bus Timer 1 interrupt request Timer 2 interrupt request T34M0 T34M2 T34M5 T34M4 T34M3 T34M1 XIN TIM2 TIM3 Selection gate : Connected to black colored side at reset T12M : Timer 12 mode register T34M : Timer 34 mode register FF16 0716 H SYNC Reset STP instruction Timer 3 interrupt request Timer 4 interrupt request Notes 1: “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 8.4.3 Timer Block Diagram

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8.5 SERIAL I/O

This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchro- nous clock I/O pin (S CLK ), data output pin (SOUT ), and data input pin (SIN) also functions as port P2. Bit 3 of the serial I/O mode register (address 00DC16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 4, 16, 32, or 64. To use SIN pin for serial I/O, set the corresponding bit of the port P2 direction regis- ter (address 00C516) to “0.” Fig. 8.5.1 Serial I/O Block Diagram The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock. Serial I/O shift register (8) Data bus Serial I/O interrupt request Selection gate : Connected to black colored side at reset.Synchronization circuit Frequency divider 1/81/4 1/16 SM1 SM0 Serial I/O counter (8) SM5 : LSB MSB S SM2 SM6 XIN SIN SOUT(/IN) SCLK SM3 P21 latch P20 latch SM3 (Address 00DD16) SM : Serial I/O mode register (See note) Note : When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 28 of 110 REJ03B0134-0100Z Internal clock : The serial I/O counter is set to “7” during the write cycle into the serial I/O register (address 00DD16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S OUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.” Fig. 8.5.2 Serial I/O Timing (for LSB first) Synchronous clock Transfer clock Serial I/O register write signal S e r i a l I / O o u t p u t SO U T D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (See note) S e r i a l I / O i n p u t SI N N o t e : W h e n a n i n t e r n a l c l o c k i s s e l e c t e d , t h e SO U T p i n i s a t h i g h - i m p e d a n c e a f t e r t r a n s f e r i s c o m p l e t e d . Interrupt request bit is set to “1” External clock : The an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an exter- nal clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an inter- nal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2:When an external clock is used as the synchronous clock, write trans- mit data to the serial I/O register when the transfer clock input level is HIGH.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 29 of 110 REJ03B0134-0100Z Fig. 8.5.3 Serial I/O Mode Register b 7b 6 b 5b 4b 3 b 2b 1b0 S e r i a l I / O m o d e r e g i s t e r ( S M ) [ A d d r e s s 0 0 D C 1 BN a m e F u n c t i o n s S e r i a l I / O M o d e R e g i s t e r 0 , 1I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s S M S M b b f XI N ) f XI N ) f XI N ) f XI N )

2 S y n c h r o n o u s c l o c k

s e l e c t i o n b i t S M

3 Serial I/O port

selection bit (SM3)

5 T r a n s f e r d i r e c t i o n

s e l e c t i o n b i t S M 0: P20, P21 1: SCLK, SOUT 0: External clock 1: Internal clock 0: LSB first 1: MSB first 4 Fix this bit to “0.” 7 N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s A f t e r r e s e t RW 0R W RW RW R W RW RW 0R — S e r i a l i n p u t p i n s e l e c t i o n b i t S M 0 : I n p u t s i g n a l f r o m SI N p i n . I n p u t s i g n a l f r o m SO U T p i n

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8.5.1 Serial I/O Common Transmission/Recep-

By writing “1” to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 8.5.4 shows signals on serial I/O common transmission/re- ception mode. Note:When receiving the serial data after writing “FF16” to the serial I/O regis- ter. Fig. 8.5.4 Signals on Serial I/O Common Transmission/Reception Mode S e r i a l I / O s h i f t r e g i s t e r ( 8 ) “ 1 ” “ 0 ” ClockSC L K SOUT SI N S M 6 SM : Serial I/O mode register

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 31 of 110 REJ03B0134-0100Z Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I 2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Format Communication mode SCL clock frequency φ : System clock = f(XIN)/2 Note :We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I 2C control register at address 00DA16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).

8.6 MULTI-MASTER I2C-BUS INTERFACE

The multi-master I2C-BUS interface is a serial communications cir- cuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS in- terface and Table 8.6.1 shows multi-master I2C-BUS interface func- tions. This multi-master I2C-BUS interface consists of the I2C address reg- ister, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface I2C address register (S0D)b7 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Noise elimination circuit Serial data (SDA) Address comparator I C data shift register Data control circuit I2C clock control register (S2) System clock(φ) Interrupt generating circuit Interrupt request signal (IICIRQ) MST TRX BB PIN AL AAS AD0 LRB I C status register (S1) b7 b0 BSEL1 BSEL0 10BIT SAD ALS BC2 BC1 BC0 I2C control register (S1D) Bit counter BB circuit Clock control circuit Noise elimination circuit Serial clock (SCL) b7 b0 ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 Internal data bus Clock division AL circuit ESO

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8.6.1 I2C Data Shift Register

The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I 2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00DA16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00D916) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift regis- ter is always enabled regardless of the ESO bit value. Note:To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Fig. 8.6.2 Data Shift Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 I2C data shift register (S0) [Address 00D716] B F u n c t i o n s A f t e r r e s e t R W I C D ata Shift R egister to This is an 8-bit shift register to store receive data and write transmit data. Indeterminate N ote: 2T o w r i t e d a t a i n t o t h e I C d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e M S T b i t t o s l a v e m o d e k e e p a n i n t e r v a l o f m a c h i n e c y c l e s o r m o r e N ame D 0 to D 7 R W

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8.6.2 I2C Address Register

The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the START condition are detected. (1) Bit 0: read/write bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. (2) Bits 1 to 7: slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. Fig. 8.6.3 I2C Address Register b 7 b 6 b 5 b4 b 3 b 2 b 1 b0

0 R ead/write bit

(RBW) t o Slave address (SAD0 to SAD6) < O n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > T h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r S T A R T c o n d i t i o n r e a d s t a t e W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r R E S T A R T c o n d i t i o n w r i t e s t a t e < I n b o t h m o d e s > T h e a d d r e s s d a t a i s c o m p a r e d I2C A d d r e s s R e g i s t e r I2C address register (S0D) [Address 00D816] B N a m e Functions A f t e r r e s e tR W R W

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8.6.3 I2C Clock Control Register

The I2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL frequency. (1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. (2) Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan- dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. (3) Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). ✽ACK clock: Clock for acknowledgement Fig. 8.6.4 I2C Address Register (4) Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note:Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 I2C c l o c k c o n t r o l r e g i s t e r S A d d r e s s D I2C C l o c k C o n t r o l R e g i s t e r t o S C L f r e q u e n c y c o n t r o l b i t s C C R t o C C R S C L m o d e s p e c i f i c a t i o n b i t F A S T M O D E 0: Standard clock mo de 1: High-speed clock mode 0Standard clock m ode B Nam e F u n c t i o n s A f t e r r e s e t R W A C K b i t A C K B I T A C K c l o c k b i t A C K 0: ACK is returned. 1: ACK is not returned. 0: N o ACK clock 1: ACK clock High speed clock mode S e t u p d i s a b l e d S e t u p d i s a b l e d0 0 t o 0 2 S e t u p d i s a b l e d 33303 S e t u p d i s a b l e d 2 5 00 4 1 0 0 4 0 0 ( S e e n o t e )0 5 83.3 1 6 60 6 C C R v a l u e 1 C C R v a l u e . . . 17.2 34.51 D 16.6 3 3 . 31 E 16.1 3 2 . 31 F ( a t φ = 4 M H z , u n i t : k H z ) N o t e : A t 4 0 0 k H z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . p e r i o d p e r i o d I n t h e o t h e r c a s e s t h e d u t y i s a s b e l o w p e r i o d p e r i o d S e t u p v a l u e o f C C R C C R

0 R W

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8.6.4 I2C Control Register

The I2C control register (address 00DA16) controls the data commu- nication format. (1) Bits 0 to 2: bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “000 2” and the address data is always transmitted and received in 8 bits. (2) Bit 3: I2C-BUS interface use enable bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to “0,” interface is in the disabled status so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ESO = “0,” the following is performed.

• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I status register at address 00D916 ).
• W riting data to the I2C data shift register (address 00D716) is dis- abled. (3) Bit 4: data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that ad- dress data is recognized. When a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to “8.6.5 I 2C Status Register,” bit 1) is received, trans- mission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recog- nized. (4) Bit 5: addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address register (ad- dress 00D816) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected and all the bits of the I2C address register are compared with the address data. (5) Bits 6 and 7: connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) These bits control the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5). Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1 Note: Set the corresponding direction register to “1” to use the port as multi-master I2C-BUS interface. “ 0 ” B S E L SCL1/P11 SCL2/P12 “0” “1” BSEL1 “ 0 ” B S E L SDA1/P1 3 SDA2/P1 4 “ 0 ” B S E L M u l t i - m a s t e r I2C B U S i n t e r f a c e S C L SDA

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 36 of 110 REJ03B0134-0100Z Fig. 8.6.6 I2C Control Register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 to B i t c o u n t e r N u m b e r o f t r a n s m i t r e c i e v e b i t s B C t o B C b 2 b 1 b 0

3 I2C-BU S interface use

enable bit (ESO) 0: Disabled 1: Enabled

4 D a t a f o r m a t s e l e c t i o n

b i t A L S 0 : A d d r e s s i n g f o r m a t F r e e d a t a f o r m a t

5 A d d r e s s i n g f o r m a t s e l e c t i o n

b i t B I T S A D 0 : 7 - b i t a d d r e s s i n g f o r m a t b i t a d d r e s s i n g f o r m a t 6, 7 C onnection control bits between I C-BUS interface and ports (BSEL0, BSEL1) b7 b6 C onnection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2 I2C c o n t r o l r e g i s t e r S D A d d r e s s D I2C Control Register B N a m e F u n c t i o n s A f t e r r e s e t R W R W R W R W R W R W

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8.6.5 I2C Status Register

The I2C status register (address 00D916) controls the I2C-BUS inter- face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) Bit 0: last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00D716). (2) Bit 1: general call detecting flag (AD0) This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. ✽General call: The master transmits the general call address “00 16” to all slaves. (3) Bit 2: slave address comparison flag (AAS) This flag indicates a comparison result of address data. ■ In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in either of the following conditions.

• The address data immediately after occurrence of a START con- dition matches the slave address stored in the high-order 7 bits of the I 2C address register (address 00D816).
• A general call is received. ■ In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” in the following condition.
• When the address data is compared with the I2C address regis- ter (8 bits consisting of slave address and RBW), the first bytes match. ■ The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00D716). (4) Bit 3: arbitration lost✽ detecting flag (AL) In the master transmission mode, when a device other than the mi- crocomputer sets the SDA to “L,”, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ✽Arbitration lost: The status in which communication as a master is disabled. (5) Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the PIN bit. When detecting the STOP condition in slave, the multi-master I 2C-BUS interface interrupt request bit (IR) is set to “1” (interrupt re- quest) regardless of falling of PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in any one of the following conditions.
• W riting “1” to the PIN bit
• Executing a write instruction to the I 2C data shift register (address 00D7 16) (See note)
• When the ESO bit is “0”
• At reset Note: It takes 8 BCLK cycles or more until PIN bit becomes “1” after write instructions are executed to these registers. The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception (6) Bit 5: bus busy flag (BB) This bit indicates the status of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be gen- erated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I 2C control register (address 00DA16) is “0” at reset, the BB flag is kept in the “0” state. (7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I 2C control register (address 00DA16) is “0” in the slave reception mode, the TRX bit is set to “1” (transmit) if the ___ least significant bit (R/W bit) of the address data transmitted by the ___ master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention function (Note).
• When MST = “0” and a START condition is detected.
• When MST = “0” and ACK non-return is detected.
• At reset

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 38 of 110 REJ03B0134-0100Z (8) Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification in data communica- tions. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are gener- ated, and also the clocks required for data communication are gen- erated on the SCL. The MST bit is cleared to “0” in any of the following conditions.

• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention function (Note).
• At reset Fig. 8.6.7 I2C Status Register b 7 b 6 b 5 b 4 b3 b 2 b1 b 0 I2C s t a t u s r e g i s t e r S A d d r e s s D I2C S t a t u s R e g i s t e r 6 , 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode B N a m e F u n c t i o n s After resetR W C o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s T R X M S T 0 : Bus free 1 : Bus busy B u s b u s y f l a g ( B B ) 0 : Interrupt request issued 1 : No interrupt request issued I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t P I N 0 : N ot detected 1 : Detected A r b i t r a t i o n l o s t d e t e c t i n g f l a g A L S e e n o t e 0 : Address mismatch 1 : Address match S l a v e a d d r e s s c o m p a r i s o n f l a g A A S S e e n o t e 0 : N o general call detected 1 : General call detected G e n e r a l c a l l d e t e c t i n g f l a g A D S e e n o t e 0 : Last bit = “0 ” 1 : Last bit = “1 ” L a s t r e c e i v e b i t ( L R B ) S e e n o t e N o t e : T h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . Indeterm inate R— RW R W

( S e e n o t e ) ( S e e n o t e ) (See note) (See note) Fig. 8.6.8 Interrupt Request Signal Generation Timing SC L PIN I I C I R Q Note:The START condition duplication prevention function disables the START condition generation, bit counter reset, and SCL output, when the follow- ing condition is satisfied: a START condition is set by another master device.

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8.6.6 START Condition Generation Method

When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes “0002” and an SCL is output for 1 byte . The START condition generation timing and BB bit set timing are different in the standard clock mode and the high- speed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table. Fig. 8.6.9 START Condition Generation Timing Diagram I2C status registe write signal Set time for BB flag Hold timeSetup time SCL SDA BB flag Setup time

8.6.7 STOP Condition Generation Method

When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP condition generation tim- ing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table. Fig. 8.6.10 STOP Condition Generation Timing Diagram Table 8.6.2 START Condition/STOP Condition Generation Tim- ing Table Item Setup time (START condition) Setup time (STOP condition) Hold time Set/reset time for BB flag Standard Clock Mode 5.0 µs (20 cycles) 4.25 µs (17 cycles) 5.0 µs (20 cycles) 3.0 µs (12 cycles) High-speed Clock Mode 2.5 µs (10 cycles) 1.75 µs (7 cycles) 2.5 µs (10 cycles) 1.5 µs (6 cycles) Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. I2C s t a t u s r e g i s t e r w r i t e s i g n a l H o l d t i m eS e t u p t i m e S C L S D A B B f l a g BB flag Reset time for

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 40 of 110 REJ03B0134-0100Z

8.6.8 START/STOP Condition Detect Conditions

The START/STOP condition detect conditions are shown in 8.6.3 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. Fig. 8.6.11 START Condition/STOP Condition Detect Timing Dia- gram Standard Clock Mode 6.5 µs (26 cycles) < SCL release time 3.25 µs (13 cycles) < Setup time 3.25 µs (13 cycles) < Hold time High-speed Clock Mode 1.0 µs (4 cycles) < SCL release time 0.5 µs (2 cycles) < Setup time 0.5 µs (2 cycles) < Hold time Table 8.6.3 START Condition/STOP Condition Detect Conditions Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the num- ber of φ cycles. H o l d t i m eS e t u p t i m e S C L S D A S T A R T c o n d i t i o n SDA (STOP condition) S C L r e l e a s e t i m e Hold timeS e t u p t i m e

8.6.9 Address Data Communication

There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective ad- dress communication formats are described below. (1) 7-bit addressing format To support the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7- bit slave address stored in the I 2C address register (address 00D816). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00D816) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2). (2) 10-bit addressing format To support the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00D816). At the time of this comparison, an address com- parison is performed between the RBW bit of the I2C address regis- ____ ter (address 00D816) and the R/W bit, which is the last bit of the address data transmitted from the master. In the 10-bit addressing ____ mode, the R/W bit not only specifies the direction of communication for control data but is also processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00D916) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00D716), perform an address comparison between the sec- ond-byte data and the slave address by software. When the address data of the 2nd byte matches the slave address, set the RBW bit of the I 2C address register (address 00D816) to “1” by software. This ____ processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I 2C address register (address 00D816). For the data transmis- sion format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4).

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8.6.10 Example of Master Transmission

An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz with the ACK return mode enable, is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C address register (address 00D816) and “0” in the RBW bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00DB16). ➂ Set “1016” in the I2C status register (address 00D916) and hold the SCL at HIGH. ④ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ➄ Set the address data of the destination of transmission in the high- order 7 bits of the I2C data shift register (address 00D716) and set “0” in the least significant bit. ⑥ Set “F016” in the I2C status register (address 00D916) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ⑦ Set transmit data in the I 2C data shift register (address 00D716). At this time, an SCL and an ACK clock automatically occurs. ➇ When transmitting control data of more than 1 byte, repeat step ➆ . ➈ Set “D016” in the I2C status register (address 00D916). After this, if ACK is not returned or transmission ends, a STOP condition will be generated.

8.6.11 Example of Slave Reception

An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, with the ACK non-return mode enabled while using the addressing format, is shown below. ➀ Set a slave address in the high-order 7 bits of the I 2C address register (address 00D816) and “0” in the RBW bit. ➁ Set the ACK non-return mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00DB16). ➂ Set “1016” in the I2C status register (address 00D916) and hold the SCL at HIGH. ④ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ➄ When a START condition is received, an address comparison is executed. ⑥ •When all transmitted address are“0” (general call): AD0 of the I2C status register (address 00D916) is set to “1” and an interrupt request signal occurs.

• When the transmitted addresses match the address set in ➀ : ASS of the I2C status register (address 00D916) is set to “1” and an interrupt request signal occurs.
• In the cases other than the above: AD0 and AAS of the I2C status register (address 00D916) are set to “0” and no interrupt request signal occurs. ⑦ Set dummy data in the I2C data shift register (address 00D716). ➇ When receiving control data of more than 1 byte, repeat step ➆ . ➈ When a STOP condition is detected, the communication ends.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 42 of 110 REJ03B0134-0100Z Fig. 8.6.12 Address Data Communication Format SS l a v e a d d r e s s A D a t aA D a t aA / A PR / W 7 b i t s“ 0 ”1 t o 8 b i t s1 t o 8 bits SS l a v e a d d r e s s A D a t a AD a t a AP 7 b i t s“ 1 ”1 t o 8 b i t s1 t o 8 bits ( 1 ) A m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r S S l a v e a d d r e s s s t b i t s A A D a t a 7 b i t s“ 0 ”8 b i t s1 t o 8 bits (2) A master-receiver receives data from a slave-transmitter S l a v e a d d r e s s n d b y t e A D a t aA / A P 1 t o 8 b i t s S S l a v e a d d r e s s s t b i t s A A 7 b i t s“ 0 ”8 b i t s7 b i t s (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S l a v e a d d r e s s n d b y t e Data 1 to 8 bits Sr Slave address 1st 7 bits A Data A P 1 t o 8 b i t s“1” (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S: S TART conditionP : STOP condition A: A C K b i t R / W : Read/Write bit Sr : Restart condition From master to slave From slave to master R / W R / W R/W R/W

8.6.12 Precautions when using multi-master

(1) Read-modify-write instruction Precautions for executing the read-modify-write instructions such as SEB, and CLB, is for each register of the multi-master I2C-BUS inter- face are described below.

• I2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become an arbitrary value.
• I2C address register (S0D) When the read-modify-write instruction is executed for this register at detection of the STOP condition, data may become an arbitrary value. It is because hardware changes the read/write bit (RBW) at the timing.
• I2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. 2C control register (S1D) When the read-modify-write instruction is executed for this register at detection of the START condition or at completion the byte trans- fer, data may become an arbitrary value. Because hardware changes the bit counter (BC0–BC2) at the timing. 2C clock control register (S2) The read-modify-write instruction can be executed for this register. (2) START condition generation procedure us- ing multi-master ➀ Procedure example (The necessary conditions for the procedure are described in ➁ to ➄ below). LDA — (Take out slave address value) SEI (Interrupt disabled) BBS 5,S1,BUSBUSY (BB flag confirmation and branch process) BUSFREE: STA S0 (Write slave address value) LDM #$F0, S1 (Trigger START condition generation) CLI (Interrupt enabled) BUSBUSY: CLI (Interrupt enabled) ➁ Use “STA,” “STX” or “STY” of the zero page addressing instruc- tion for writing the slave address value to the I2C data shift register. ➂ Use “LDM” instruction for setting trigger of START condition gen- eration. ④ W rite the slave address value of ➁ and set trigger of START con- dition generation as in ➂ continuously as shown in the procedure example. ➄ Disable interrupts during the following three process steps:
• BB flag confirmation
• Write of slave address value
• Trigger of START condition generation When the condition of the BB flag is bus busy, enable interrupts immediately.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 43 of 110 REJ03B0134-0100Z (3) RESTART condition generation procedure ➀ Procedure example (The necessary conditions for the procedure are described in ➁ to ➅ below.) Execute the following procedure when the PIN bit is “0.” LDM #$00, S1 (Select slave receive mode) LDA —( Take out slave address value) SEI (Interrupt disabled) STAS 0( W rite slave address value) LDM #$F0, S1 (Trigger RESTART condition generation) CLI (Interrupt enabled) ➁ Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. ➂ The SCL pin is released by writing the slave address value to the I 2C data shift register. Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing. ④ Use “LDM” instruction for setting trigger of RESTART condition generation. ➄ W rite the slave address value of ➂ and set trigger of RESTART condition generation of ➃ continuously, as shown in the procedure example. ⑥ Disable interrupts during the following two process steps:

• Write slave address value
• Trigger RESTART condition generation (4) STOP condition generation procedure ➀ Procedure example (The necessary conditions for the procedure are described in ➁ to ➃ below.) SEI (Interrupt disabled) LDM #$C0, S1 (Select master transmit mode) NOP (Set NOP) LDM #$D0, S1 (Trigger STOP condition generation) CLI (Interrupt enabled) ➁ Write “0” to the PIN bit when master transmit mode is selected. ➂ Execute “NOP” instruction after master transmit mode is set. Also, set trigger of STOP condition generation within 10 cycles after se- lecting the master trasmit mode. ④ Disable interrupts during the following two process steps:
• Select master transmit mode
• Trigger STOP condition generation (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously as it may cause the SCL pin the SDA pin to be released after about one machine cycle. Also, do not execute an instruction to set the MST and TRX bits to “0” from “1” when the PIN bit is “1,” as it may cause the same problem. (6) Process after STOP condition generation Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generation the STOP condition in the master mode. Doing so may cause the STOP condition waveform from being generated normally. Reading the registers does not cause the same problem.

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8.7 PWM OUTPUT FUNCTION

This microcomputer is equipped with two 14-bit PWM (DA) and six 8-bit PWMs (PWM0–PWM5). DA1 and DA2 have a 14-bit resolution with the minimum resolution bit width of 0.25 µs and a repeat period of 4096 µs (for f(XIN) = 8 MHz). PWM0–PWM7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of µs and repeat period of 1024 µs (for f(XIN) = 8 MHz). Figure 8.7.1 shows the PWM block diagram. The PWM timing gen- erating circuit applies individual control signals to DA and PWM0– PWM5 using f(X IN) divided by 2 as a reference signal.

8.7.1 Data Setting

When outputting DA, first set the high-order 8 bits to the DA-H regis- ter (address 00CE16), then the low-order 6 bits to the DA-L register (address 00CF16). When outputting PWM0–PWM5, set 8-bit output data to the PWMi register (i means 0 to 5; addresses 00D016 to 00D4 16, 00F616).

8.7.2 Transferring Data from Registers to PWM

Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed when writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. Also, data transfer from the DA register (addresses 00CE 16 and 00CF 16) to the 14-bit PWM circuit is executed at writing data to the DA-L register (address 00CF16). Reading from the DA-H register (address 00CE16) means reading this transferred data. Accordingly, it is possible to confirm the data being output from the DA output pin by reading the DA register.

8.7.3 Operating of 8-bit PWM

The following explains the PWM operation. First, set bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM5 are also used as ports P0 0–P0 5, respectively. Set those of the port P0 direction register to “1.” And select each output polarity by bit 3 of PWM output control register 2 (address 00D6 16). Then, set bits 2 to 7 of PWM output control register 1 to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is com- posed of 256 (2 8) segments. 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 8.7.2 (a). The 8-bit PWM outputs a waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. An en- tirely HIGH selection cannot be output, i.e. 256/256.

8.7.4 Operating of 14-bit PWM

As with 8-bit PWM, set the bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automati- cally), so that the PWM count source is supplied. Next, select the output polarity by bit 2 of PWM output control register 2 (address 00D6 16). Then, the 14-bit PWM outputs from the D-A output pin by setting bit 1 of PWM output control register 1 to “0” (at reset, this bit already set to “0” automatically) to select the DA output. The output example of the 14-bit PWM is shown in Figure 8.7.3. The 14-bit PWM divides the data of the DA latch into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data “D H .” A HIGH area with a length t ✕ DH (HIGH area of funda- mental waveform) is output every short area of “t” = 256τ = 64 µs (τ is the minimum resolution bit width of 250 ns). The HIGH level area increase interval (tm ) is determined with the low-order 6-bit data “DL.” The HIGH are of smaller intervals “tm ” shown in Table 5 is longer by t than that of other smaller intervals in PWM repeat period “T” = 64t. Thus, a rectangular waveform with the different HIGH width is output from the DA pins. Accordingly, the PWM output changes by τ unit pulse width by changing the contents of the DA-H and DA-L registers. A length of entirely HIGH cannot be output, i. e. 256/256.

8.7.5 Output after Reset

At reset, the output of ports P00–P05 are in the high-impedance state, and the contents of the PWM register and the PWM circuit are unde- fined. Note that after reset, the PWM output is undefined until setting the PWM register. LSB Table 8.7.1 Relation Between the Low-order 6-bit Data and High- level Area Increase Interval Area Longer by τ than That of Other tm (m = 0 to 63) Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 Low-order 6 bits of Data 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 45 of 110 REJ03B0134-0100Z Fig. 8.7.1 PWM Block Diagram

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 46 of 110 REJ03B0134-0100Z Fig. 8.7.2 PWM Timing ( a P u l s e s s h o w i n g t h e w e i g h t o f e a c h b i t 2 0 3 6 5 2 6 8 8 4 1 0 1 0 1 1 1 2 1 3 1 4 1 4 1 5 1 6 1 7 1 8 1 9 2 1 2 2 2 3 2 4 2 5 1 6 4 8 8 0 1 1 1 4 1 7 2 0 2 4 2 4 4 0 5 6 7 2 8 8 1 0 1 2 1 3 1 5 1 6 1 8 2 0 2 1 2 3 2 4 3 2 9 6 1 6 2 2 6 4 1 9 B i t 1 0 1 4 1 8 2 2 2 6 3 0 3 4 3 8 4 2 4 6 5 0 5 4 5 8 6 2 6 6 7 0 7 4 7 8 8 2 8 6 9 0 9 4 9 8 1 0 1 0 1 1 1 1 1 1 1 2 1 2 1 3 1 3 1 3 1 4 1 4 1 5 1 5 1 5 1 6 1 6 1 7 1 7 1 7 1 8 1 8 1 9 1 9 1 9 2 0 2 0 2 1 2 1 2 1 2 2 2 2 2 3 2 3 2 3 2 4 2 4 2 5 2 5 B i t B i t B i t B i t B i t B i t 1 2 B i t P W M o u t p u t t µs T µs f X I M H z ( b E x a m p l e o f b i t P W M t 0 01 0 11 1 81 F F T t

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 47 of 110 REJ03B0134-0100Z Fig. 8.7.3 14-bit PWM Timing (f(XIN) = 8 MHz) 0.25 µs b 7b 0b6 b 5b 4b 3b 2b 1 0 0010110 b 1 3b 6 00 010110 b0b5 101000 S e t “ 2 C 1 6” t o D A - H r e g i s t e r . [ D A - H r e g i s t e r D H At writing of DA-L b 0b 6b 5b 4b 3b 2b 1 010100 S e t “ 2 81 6” t o D A - L r e g i s t e r . [ D A - L r e g i s t e r ] D L At writing of DA-L T h e s e b i t s d e c i d e H I G H l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m T h e s e b i t s d e c i d e s m a l l e r i n t e r v a l “ t m ” i n w h i c h H I G H l e v a l a r e a i s H I G H l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m τ Minimum resolution bit width 0.25 µs H i g h - o r d e r 8 - b i t v a l u e o f D A l a t c h✕H I G H l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m FF 00 D3FE FD … D6 D4 02 01D5 14-bit PWM output 8-bit counter 0.25 µs✕ 44 FF 00 D3FE FD D6 D4 02 01D5 14-bit PWM output 8-bit counter 0.25 µs✕ 45 Fundamental waveform Waveform of smaller interval “tm” specified by low-order 6 bits Fundamental waveform of smaller interval “tm” which is not specified by low-order 6 bits is not changed. 14-bit PWM output L o w - o r d e r 6 - b i t o u t p u t o f D A l a t c h 0.25 µs✕ 44 τ = 0 . 2 5 µs T = 4096 µs R epeat period t0 t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 [ D A l a t c h ] …… … b 7 2C 2B 2A 03 02 01 00 2C 2B 2A 03 02 01 00……

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 48 of 110 REJ03B0134-0100Z Fig. 8.7.4 PWM Output Control Register 1 Fig. 8.7.5 PWM Output Control Register 2 b7b 6 b 5b 4b 3 b 2b 1b0 P W M o u t p u t c o n t r o l r e g i s t e r 1 ( P W ) [ A d d r e s s 0 0 D 5 B After reset RW PWM Ou tput Control Register 1 N a m eF unctions DA, PWM count source selection bit (PW0) 0 : C o u n t s o u r c e s u p p l y C o u n t s o u r c e s t o p P 00/ P W M 0 o u t p u t s e l e c t i o n b i t P W 0 : P 00 o u t p u t P W M o u t p u t P 01/ P W M 1 o u t p u t s e l e c t i o n b i t P W 0: P01 output 1: PWM1 output P02/PWM2 output selection bit (PW4) 0 : P 02 o u t p u t P W M o u t p u t

5 P03/PWM3 output

selection bit (PW5) 0 : P 03 o u t p u t P W M o u t p u t

6 P04/PWM4 output

selection bit (PW6) 0 : P 04 o u t p u t P W M o u t p u t D A / P N 4 s e l e c t i o n b i t P W 0 : D A o u t p u t P N 4 o u t p u t

7 P05/PWM5 output

selection bit (PW7) 0 : P 05 o u t p u t P W M o u t p u t RW RW RW RW RW RW RW RW 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R — DA output polarity selection bit (PN2) 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y PWM output polarity selection bit (PN3) DA general-purpose output bit (PN4) 0 : O u t p u t L O W O u t p u t H I G H t o 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y R W R W R W 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R — b 7b 6 b 5b 4b 3 b 2b 1b0 P W M o u t p u t c o n t r o l r e g i s t e r 2 ( P N ) [ A d d r e s s 0 0 D 61 B A f t e r r e s e t R W P W M O u t p u t C o n t r o l R e g i s t e r 2 N a m e F u n c t i o n s 0 , 1

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 49 of 110 REJ03B0134-0100Z

8.8 A-D COMPARATOR

A-D comparator consists of a 6-bit D-A converter and a comparator. The A-D comparator block diagram is shown in Figure 8.8.1. The reference voltage “V ref” for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 00EF16). The comparison result of the analog input voltage and the reference voltage “V ref” is stored in bit 4 of the A-D control register 1 (address 00EE 16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data to select analog input pins for bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to V ref to be compared to bits 0 to 5 of the A-D control register 2. The voltage comparison is started by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ✕ 8). Fig. 8.8.1 A-D Comparator Block Diagram A-D control register 1 Bits 0 to 2 C o m p a r a t o r c o n t r o l D a t a b u s Bit 4 Switch tree A-D control register 2 R e s i s t o r l a d d e r C o m p a - r a t o r A n a l o g s i g n a l s w i t c h B i t 5B i t 4B i t 3B i t 2B i t 1 Bit 0 A - D c o n t r o l r e g i s t e r 1A - D 1 A - D 2 A - D 3 A - D 4 A - D 5 A - D 6

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 50 of 110 REJ03B0134-0100Z Fig. 8.8.2 A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EE16] B After reset RW A - D C o n t r o l R e g i s t e r 1 t o Analog input pin selection bits (ADM0 to ADM2) N a m eF unctions b 2 b 1 b 0 A D A D A D A D A D A D D o n o t s e t D o n o t s e t

4 Storage bit of comparison

result (ADM4) 0 : I n p u t v o l t a g e < r e f e r e n c e v o l t a g e I n p u t v o l t a g e r e f e r e n c e v o l t a g e Indeterm inate 03 This bit is a write disable bit. W hen this bit is read out, the value is “0.” RW R R — to N othing is assigned. This bits are write disable bits. W hen these bits are read out, the values are “0.” R — Fig. 8.8.3 A-D Control Register 2 b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0 A - D c o n t r o l r e g i s t e r 2 ( A D 2 ) [ A d d r e s s 0 0 E F1 B A f t e r r e s e t RW A D C o n t r o l R e g i s t e r to 6 , 7 N a m e F u n c t i o n s D - A c o n v e r t e r s e t b i t s A D C t o A D C b0b1b2 b3 b4 b5 N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e e d o u t t h e v a l u e s a r e 000000 00000 0000 111 11111 111111 : 3/128Vcc : 5/128Vcc : 1 2 3 / 1 2 8 V c c : 1 2 5 / 1 2 8 V c c : 1 2 7 / 1 2 8 V c c : 1/128Vcc RW R —

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 51 of 110 REJ03B0134-0100Z Fig. 8.9.1 D-A converter block diagram

8.9 D-A CONVERTER

This microcomputer has 2 D-A converters with 6-bit resolution. D-A converter block diagram is shown in Figure 8.9.1. D-A conversion is performed by setting the value in the DA conver- sion register. The result of D-A conversion is output from the DA pin by setting “1” to the DA output enable bit of the port P3 output mode control register (bits 2 and 3 at address 00CD 16). The output analog voltage V is determined with the value n (n: deci- mal number) in the DA conversion register. V = VCC ✕ (n = 0 to 63) The DA output does not build in a buffer, so connect an external buffer when driving a low-impedance load. n Data bus DA1 conversion register DA2 conversion register [address 00DE16] 6 [address 00DF16] Resistor ladder DA1 output enable bit Resistor ladder DA2 output enable bit P30/A-D5/DA1 P31/A-D6/DA2 Note: Only M37221EASP/FP have a built-in D-A converter.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 52 of 110 REJ03B0134-0100Z Fig. 8.9.2 P3 output mode control register Fig. 8.9.3 DA conversion register i (i = 1, 2) b 7b 6b 5b4b 3b 2b 1b 0 D A c o n v e r s i o n r e g i s t e r i ( i = 1 , 2 ) ( D A i ) [ A d d r e s s e s 0 0 D E1 6, 0 0 D F1 A f t e r r e s e t D A c o n v e r s i o n r e g i s t e r i to D A c o n v e r s i o n s e l e c t i o n b i t D A i t o D A i b0b1b2 b3 b4 b5 000000 00000 0000 111 11111 111111 : 1 / 6 4 V c c : 2 / 6 4 V c c : 6 1 / 6 4 V c c : 6 2 / 6 4 V c c : 6 3 / 6 4 V c c : 0/64Vcc 7 0N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e R — R W R W R W BN a m e F u n c t i o n s F i x t h i s b i t t o “ 0 . ” N o t e : W h e n u s e M 3 7 2 2 1 M 4H/M6H/M8H/MAH-XXXSP/FP, t h e r e i s n o t t h i s r e g i s t e r F i x t o b7 b 6b 5b 4b 3b 2b 1b 0 P 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( P 3 S ) [ A d d r e s s 0 0 C D 1 P 3 o u t p u t m o d e c o n t r o l r e g i s t e r 4 to 7 P 30 o u t p u t f o r m s e l e c t i o n b i t P S 0: CMOS output 1: N-channel open-drain output

1 P 31 o u t p u t f o r m

s e l e c t i o n b i t P S 0: CMOS output 1: N-channel open-drain output

2 D A 1 o u t p u t e n a b l e b i t

D A S 0: P30 input/output 1: DA1 output

3 D A 2 o u t p u t e n a b l e b i t

D A S 0: P31 input/output 1: DA2 output After reset R WBN a m e F u n c t i o n s R W R W R W R W R—N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 53 of 110 REJ03B0134-0100Z Fig. 8.10.2 ROM Correction Enable Register Fig. 8.10.1 ROM Correction Address Registers

8.10 ROM CORRECTION FUNCTION

This can correct program data in the ROM. Up to 2 addresses can be corrected ; a program for correction is stored in the ROM correction memory in the RAM as the top address. There are 2 vectors for ROM correction : Vector 1 : address 02C0 Vector 2 : address 02E016 Set the address of the ROM data to be corrected into the ROM cor- rection address register. When the value of the counter matches the ROM data address in the top address of the ROM correction vector, the main program branches to the correction program stored in the ROM memory. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable regis- ter. Notes 1:Specify the first address (op code address) of each instruction as the ROM correction address. 2:Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3:Do not set the same ROM correction address to both vectors 1 and b7 b6 b5 b4 b3 b2 b1 b0 R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) [ A d d r e s s 0 2 1 B1 BA f t e r reset R O M C o r r e c t i o n E n a b l e R e g i s t e r

0 Vector 1 enable bit (RCR 0)

0: Disabled 1: Enabled

1 V e c t o r 2 e n a b l e b i t ( R CR 1 ) 0: Disabled

1: Enabled t o N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e 2 , 3 F i x t h e s e b i t s t o “ 0 . ” 0 RW RW RW RW F 0 2 1 71 6R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) 0 2 1 81 6R O M c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) 0 2 1 91 6R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) 0 2 1 A1 6R O M c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r )

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 54 of 110 REJ03B0134-0100Z

8.11 OSD FUNCTIONS

Table 8.11.1 outlines the OSD functions. This microcomputer incor- porates an OSD control circuit of 24 characters ✕ 2 lines. OSD is controlled by the CRT control register. Up to 256 kinds of characters can be displayed. The colors can be specified for each character and up to 4 kinds of colors can be displayed on one screen. A combina- tion of up to 8 colors can be obtained by using each output signal (R, G, and B). Characters are displayed in a 12 ✕ 16 dots configuration to obtain smooth character patterns (refer to Figure 8.11.1). The following shows the procedure how to display characters on the CRT screen. ➀ Write the display character code in OSD RAM. ➁ Specify the display color by using the color register. ➂ W rite the color register in which the display color is set in OSD RAM. ④ Specify the vertical position by using the vertical position register. ➄ Specify the character size by using the character size register. ⑥ Specify the horizontal position by using the horizontal position register. ⑦ W rite the display enable bit to the designated block display flag of the CRT control register. When this is done, the OSD starts ac- cording to the input of the V SYNC signal. Table 8.11.1 Features of Each Display Mode Number of display characters 24 characters ✕ 2 lines Dot structure 12 ✕ 16 dots Kinds of characters 256 kinds Kinds of character sizes 3 kinds Attribute Border (black) Character font coloring 1 screen : 8 kinds (per character unit) Character background coloring 1 screen : 8 kinds (per character unit) OSD output R, G, B Display position Horizontal: 64 levels, Vertical: 128 levels Display expansion (multiline display) Possible Parameter Functions

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 55 of 110 REJ03B0134-0100Z The OSD circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by inter- rupting the display each time one line is displayed and rewriting data in the block for which display has been terminated by software. Figure 8.11.1 shows the configuration of an OSD character. Figure shows OSD control register. Fig. 8.11.1 Configuration of OSD Character Display Area 12 dots 16 dots

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 56 of 110 REJ03B0134-0100Z Fig. 8.11.2 Block Diagram of OSD Circuit D i s p l a y o s c i l l a t i o n c i r c u i t O S C 1 O S C 2 H S Y N C VS Y N C O S D R A M b i t s c h a r a c t e r s l i n e s Data bus OSD ROM 12 dots ✕ 16 dots ✕ 256 characters Shift register 12-bit Clock for OSD O u t p u t c i r c u i t R G B O S D C o n t r o l c i r c u i t OUT1 OUT2 Control registers for OSD (address 00E016) (addresses 00E116, 00E216) (addresses 00E416) (addresses 00E616 to 00E916) (address 00EA16) (address 00EC16) (address 00ED16) H o r i z o n t a l p o s i t i o n r e g i s t e r V e r t i c a l p o s i t i o n r e g i s t e r C h a r a c t e r s i z e r e g i s t e r C o l o r r e g i s t e r O S D c o n t r o l r e g i s t e r O S D p o r t c o n t r o l r e g i s t e r O S D c l o c k s e l e c t i o n r e g i s t e r S h i f t r e g i s t e r b i t

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 57 of 110 REJ03B0134-0100Z Fig. 8.11.3 OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (CC) [Address 00EA16] B Name Functions After reset R W OSD Control Register

0 All-blocks display control

bit (CC0) (See note) 0 : All-blocks display off 1 : All-blocks display on

1 Block 1 display control bit

(CC1) 0 : Block 1 display off 1 : Block 1 display on 2 0 : Block 2 display off 1 : Block 2 display on to Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Block 2 display control bit (CC2) RW RW RW 7 0 : P10 1 : OUT2 0P10/OUT2 pin switch bit (CC7) RW

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 58 of 110 REJ03B0134-0100Z

8.11.1 Display Position

The display positions of characters are specified in units called “blocks.” There are 2 blocks : blocks 1 and 2. Up to 24 characters can be displayed in each block (refer to “8.11.3 Memory for OSD”). The display position of each block can be set in both horizontal and vertical directions by software. The display start position in the horizontal direction can be selected for all blocks from 64-step display positions in units of 4T C (TC = OSD oscillation cycle). The display start position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. Blocks are displayed in conformance with the following rules:

• Block 2 is displayed after the display of block 1 is completed (Figure 8.11.4 (a)).
• When the display position of block 1 is overlapped with that of block 2 (Figure 8.11.4 (b)), block 1 is displayed in front.
• When another block display position appears while one block is displayed (Figure 8.11.4 (c)),only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed. Fig. 8.11.4 Display Position HR C V 2 B l o c k 1 Block 2 ( a ) E x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d Block 1 ( b ) E x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 (Block 2 is not displayed) HR C V 1 C V 2 (c) Examp le when block 2 overlaps in process of block 1 B l o c k 2 N otes 1: CV 1 or CV 2 indicates the vertical display start position of display block 1 or 2. 2: HR indicates the horizontal display start position of display block 1 or 2. C V 1 HR CV 1 = CV 2 CV 1 Block 1 (second) ← N o t d i s p l a y e d ← N ot displayed Block 1

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 59 of 110 REJ03B0134-0100Z The vertical display start position is determined by counting the hori- zontal sync signal (HSYNC ). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), the count starts at the rising edge (falling edge) of HSYNC signal after the fixed cycle of the rising edge (falling edge) of VSYNC signal. So the interval from the rising edge (falling edge) of VSYNC signal to the rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) to avoid jitters. The polarity of HSYNC and VSYNC signals can be select with the OSD port control register (address 00EC16). Fig. 8.11.5 Supplement Explanation for Display Position W h e n b i t s 0 a n d 1 o f t h e O S D p o r t c o n t r o l r e g i s t e r a d d r e s s E C 1 a r e s e t t o n e g a t i v e p o l a r i t y VS Y N C s i g n a l i n p u t VS Y N C c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o [µs a t f XI N ) M H z Period of counting H SYNC signal (See note 2) H SYNC signal input Not count 12345 N o t e s 1 : T h e v e r t i c a l p o s i t i o n i s d e t e r m i n e d b y c o u n t i n g f a l l i n g e d g e o f H S Y N C s i g n a l a f t e r r i s i n g e d g e o f VS Y N C c o n t r o l s i g n a l i n t h e m i c r o c o m p u t e r : D o n o t g e n e r a t e f a l l i n g e d g e o f H S Y N C s i g n a l n e a r r i s i n g e d g e o f VS Y N C c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o a v o i d j i t t e r : T h e p u l s e w i d t h o f VS Y N C a n d H S Y N C n e e d s m a c h i n e c y c l e s o r m o r e 8 m a c h i n e c y c l e s o r m o r e 8 ma chine cycles or more

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 60 of 110 REJ03B0134-0100Z Fig. 8.11.6 Vertical Position Register i The vertical display start position for each block can be set in 512 steps (where each step is 1TH (TH : HSYNC cycle)) as values “0016” to “7F16” in vertical position register i (i = 1 and 2) (addresses 00E116 and 00E216) The vertical position register i is shown in Figure 8.11.6. b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 and 2) [Addresses 00E116, 00E216] B Name Functions After reset R W Vertical Position Register i to Vertical display start positions128 steps (0016 to 7F16) Indeterminate (CVi : CVi0 to CVi6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” RW

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 61 of 110 REJ03B0134-0100Z The horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4TC , TC being the OSD oscillation cycle) as values “0016” to “3F16” in bits 0 to 5 of the horizontal posi- tion register (address 00D116). The horizontal position register is shown in Figure 8.11.7. Fig. 8.11.7 Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E016] B Name Functions After resetRW Horizontal Position Register 0to 6, 7 Horizontal display start positions (HR0 to HR5) 64 steps (0016 to 3F16) 0 0Nothing is assigned. These bits are write disable bits. When thses bits are read out, the values are “0.” RW

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 62 of 110 REJ03B0134-0100Z Fig. 8.11.8 Character Size Register

8.11.2 Character Size

The size of characters to be displayed can be from 3 sizes for each block. Use the character size register (address 00E416) to set a char- acter size. The character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3. Figure 8.11.8 shows the character size register. The character size can be selected from 3 sizes: minimum size, me- dium size and large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (T C ) in the width (horizontal) direction. The minimum size consists of [1 scanning line] ✕ [1TC ]; the medium size consists of [2 scanning lines] ✕ [2TC ]; and the large size con- sists of [3 scanning lines] ✕ [3TC ]. Table 8.11.2 shows the relation between the set values in the character size register and the charac- ter sizes. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 C h a r a c t e r s i z e r e g i s t e r ( C S ) [ A d d r e s s 0 0 E 41 B N am e Functions After reset R W C h a r a c t e r S i z e R e g i s t e r 0, 1Ch aracter size of block 1 selection bits (CS10, CS11) 00 : Minimum s ize 01 : Medium size 10 : Large size 11 : Do not set. Indeterminate 2 , 3 t o C h a r a c t e r s i z e o f b l o c k s e l e c t i o n b i t s C S C S 0 0 : M i n i m u m s i z e M e d i u m s i z e L a r g e s i z e D o n o t s e t N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e I n d e t e r m i n a t e R W R W R —

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 63 of 110 REJ03B0134-0100Z Mini- mum Medium Large Horizontal display start position Fig. 8.11.9 Display Start Position of Each Character Size (Horizontal Direction) Notes 1:The display start position in the horizontal direction is not affected by the character size. In other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to Figure 8.11.9). 2:i indicates 1 or 2. Set values of character size register Width (horizontal) direction TC : oscillating cycle for display 1 TC 2 TC 3 TC Height (vertical) direction scanning lines Character size Minimum Medium Large This is not available CSi1 CSi0 Table. 8.11.2 Relation between Set Values in Character Size Register and Character Sizes

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8.11.3 Clock for OSD

The following 2 types of clocks can be selected for OSD display.

• Main clock supplied from XIN pin
• Main clock supplied from XIN pin divided by I.5
• Clock from the ceramic resonator or the LC or oscillator from the pins OSC1 and OSC2
• Clock from the ceramic resonator or the quartz-crystal oscillator supplied from pins OSC1 and OSC2. The OSD clock for each block can be selected by the OSD clock selection register (address 00ED 16). When selecting the main clock, set the oscillation frequency to 8 MHz. Fig. 8.11.10 OSD clock selection Circuit b7 b6 b5 b4 b3 b2 b1 b0 O S D c l o c k s e l e c t i o n r e g i s t e r ( C K ) [ A d d r e s s 0 0 E D 1 B N a m e F u n c t i o n s A f t e r r e s e t R W OSD Clock Selection R egister 0 , 1 O S D c l o c k s e l e c t i o n b i t s C K C K S i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r d i s p l a y t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d B e c a u s e o f t h i s t h e c h a r a c t e r s i z e i n w i d t h h o r i z o n t a l d i r e c t i o n i s a l s o l i m i t e d I n t h i s c a s e p i n s O S C a n d O S C a r e a l s o u s e d a s i n p u t p o r t s P a n d P r e s p e c t i v e l y T h e c l o c k f o r O S D i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s O S C a n d O S C a c e r a m i c r e s o n a t o r o n l y f o r O S D a q u a r t z c r y s t a l o s c i l l a t o r o n l y f o r O S D a n d a f e e d b a c k r e s i s t o r S e e n o t 2 t o 7 0 000000 T h e c l o c k f o r d i s p l a y i s s u p p l i e d b y c o n n e c t i n g R C o r L C a c r o s s t h e p i n s O S C a n d O S C F u n c t i o n s O S D o s c i l l a t i o n f r e q u e n c y f XI N ) O S D o s c i l l a t i o n f r e q u e n c y f XI N ) N o t e : I t i s n e c e s s a r y t o c o n n e c t o t h e r c e r a m i c r e s o n a t o r o r q u a r t z - c r y s t a l o s c i l l a t o r f o r O S D a c r o s s t h e pI N s XI N a n d XO U 1 1 Fix these bits to “0.” R W R W

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8.11.4 Memory for OSD

There are 2 types of memory for OSD: OSD ROM (addresses 1000016 to 11FFF16) used to store character dot data and OSD RAM (ad- dresses 060016 to 06B716) used to specify the characters and colors to be displayed. Fig. 8.11.11 Character Font Data Storing Address (1) OSD ROM (addresses 1000016 to 11FFF16) The dot pattern data for OSD characters is stored in the OSD ROM. To specify the kinds of character font, it is necessary to write the character code (Table 8.11.3) into the OSD RAM. The OSD ROM has a capacity of 8K bytes. Since 32 bytes are re- quired for 1 character data, the ROM can stores up to 256 kinds of characters. The OSD ROM space is broadly divided into 2 areas. The [vertical 16 dots] ✕ [horizontal (left side) 8 dots] data of display characters are stored in addresses 10000 16 to 107FF16 and 1100016 to 117FF16 ; the [vertical 16 dots] ✕ [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 (refer to Figure 8.11.11). Note however that the high- order 4 bits in the data to be written to addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 must be set to “1” (by writing data “FX16”). Data of the character font is specified shown in Figure 8.11.11. 10XX0 16 +80016 or 11XX0 16 +80016 00 000000 00 000000 00 000010 00 000101 01 001000 01 001000 01 001000 00 010000 1111001 00 100000 00 100000 00 100000 00 000000 00 000101 00 000010 01111 000 0000 0000 0000 0000 0000 0000 0100 0100 0100 0010 0010 0010 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0 b3 00000 10XXF 16 +80016 or 11XXF 16 +80016 10XX0 16 or 11XX0 16 10XXF 16 or 11XXF 16

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 66 of 110 REJ03B0134-0100Z Block Block 1 Block 2 Display Position (from left) 1st character 2nd character 3rd character 22nd character 23rd character 24th character Not used 1st character 2nd character 3rd character 22nd character 23rd character 24th character Character Code Specification 060016 060116 060216 061516 061616 061716 061816 061F16 062016 062116 062216 063516 063616 063716 Color Specification 068016 068116 068216 069516 069616 069716 069816 069F16 06A016 06A116 06A216 06B516 06B616 06B716 Table 8.11.3 Character Code List (Partially Abbreviated) (2) OSD RAM (addresses 060016 to 06B716) The OSD RAM is allocated at addresses 060016 to 06B716, and is divided into a display character code specification part, and color code specification part for each block. Table 8.11.4 shows the con- tents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 0600 16, write the color code at 068016. The structure of the OSD RAM is shown in Figure 8.11.12. Table 8.10.4 Contents of OSD RAM Character code 0016 Character data storage address Left 8 dots lines Right 4 dots lines 1000016 1000F16 1080016 1080F16 0116 1001016 1001F16 1081016 1081F16 0216 1002016 1002F16 1082016 1082F16 0316 1003016 1003F16 1083016 1083F16 ::: 7E16 107E016 107EF 16 10FE0 16 10FEF 16 7F16 107F016 107FF16 10FF016 10FFF 16 8016 1100016 1100F16 1180016 1180F16 8116 1101016 1101F16 1181016 1181F16 ::: FD 16 117D0 16 117DF 16 11FD0 16 11FDF 16 FE 16 117E016 117EF 16 11FE0 16 11FEF 16 FF16 117F016 117FF16 to 11FF016 11FFF 16 to to to to to to to to to to to to to to to to to to to to to

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 67 of 110 REJ03B0134-0100Z Fig. 8.11.12 Bit structure of OSD RAM [Color specification] 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Color register specification Block 1 [Character specification] Specify 256 characters (“0016” to “FF16”) Character code Block 2 [Character specification] 1st character : 062016 24th character : 063716 1st character : 068016 24th character : 069716 1st character : 060016 24th character : 061716 [Color specification] 1st character : 06A016 24th character : 06B716 to to to to Specify 256 characters (“0016” to “FF16”) Character code 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Color register specification

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8.11.5 Color Register

The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E916) and then specifying that color register with the OSD RAM. There are 3 color outputs; R, G and B. By using a combination of these outputs, it is possible to set 8 colors. However, since only 4 color registers are available, up to 4 colors can be disabled at one time. R, G and B outputs are set by using bits 1 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Bits 4, 6 and 7 are used to specify character background color. Figure 8.11.12 shows the color register. Fig. 8.11.13 Color Register i b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 C o l o r r e g i s t e r i ( C O i ) ( i = 0 t o 3 ) [ A d d r e s s e s 0 0 E 61 6 t o 0 0 E 91 B N ame F u n c t i o n s A f t e r r e s e t R W C o l o r R e g i s t e r i 0 0 R — G signal output selection bit (COi2) 0: N o character is output 1: Character is output R s i g n a l o u t p u t s e l e c t i o n b i t C O i 0: N o character is output 1: Character is output R W B s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t C O i S e e n o t e 0 : N o b a c k g r o u n d c o l o r i s o u t p u t B a c k g r o u n d c o l o r i s o u t p u t R W O U T 1 s i g n a l o u t p u t c o n t r o l b i t C O i S e e n o t e s 0 : C h a r a c t e r i s o u t p u t B l a n k i s o u t p u t R W G s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t C O i S e e n o t e 0 : N o b a c k g r o u n d c o l o r i s o u t p u t B a c k g r o u n d c o l o r i s o u t p u t R W R s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t C O i S e e n o t e 0 : N o b a c k g r o u n d c o l o r i s o u t p u t B a c k g r o u n d c o l o r i s o u t p u t R W

7 R W

B s i g n a l o u t p u t s e l e c t i o n b i t C O i 0 : N o c h a r a c t e r i s o u t p u t C h a r a c t e r i s o u t p u t N othing is assigned. This bit is a write disable bit. W hen this bit is read out, the value is “0.” N o t e s 1 : W h e n b i t 5 = “ 0 ” a n d b i t 4 = “ 1 , ” t h e r e i s o u t p u t s a m e a s a c h a r a c t e r o r b o r d e r o u t p u t f r o m p i n O U T D o n o t s e t b i t a n d b i t W h e n o n l y b i t a n d b i t t h e r e i s o u t p u t f r o m p i n O U T

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 69 of 110 REJ03B0134-0100Z Table 8.11.5 Display Example of Character Background Coloring (When Green Is Set for a Character and Blue Is Set for Background Color) B o r d e r s e l e c t i o n r e g i s t e r Color register i C O i 7 C O i 6 C O i 5 C O i 4 C O i 3 C O i 2 C O i 1M D 0 G o u t p u tB output OUT1 output C h a r a c t e r o u t p u tO U T 2 o u t p u t 0 ✕ 00 1 0 N o o u t p u t Same output as character A G r e e n Video signal and character color (green) are not mixed. N o o u t p u t S e e n o t e 0 ✕ 00 1 0 N o output Same output as character A V i d e o s i g n a l a n d c h a r a c t e r c o l o r g r e e n a r e n o t m i x e d . B l a n k o u t p u t G r e e n N o o u t p u t T V i m a g e o f c h a r a c t e r b a c k g r o u n d i s n o t d i s p l a y e d .Blank output Green N o o u t p u t S e e n o t e 1 ✕ 0 1010 N o output Border output (Black) V i d e o s i g n a l a n d c h a r a c t e r c o l o r g r e e n a r e n o t m i x e d G r e e n N o o u t p u t S e e n o t e 01 001000 T V i m a g e o f c h a r a c t e r b a c k g r o u n d i s n o t d i s p l a y e d .Blank output G r e e n 01 0 1 000 N o o u t p u t S e e n o t e Blue T V i m a g e o f c h a r a c t e r b a c k g r o u n d i s n o t d i s p l a y e d G r e e n 10 1 0 Blank output

00 N o o u t p u t

S e e n o t e B l a c kNo output G r e e n No output (See note 2)10 1 0 T V i m a g e o f c h a r a c t e r b a c k g r o u n d i s n o t d i s p l a y e d B l a n k o u t p u t Border output (Black) Background color – border B l u e N o t e s1 :W h e n C O i 5 = “ 0 ” a n d C O i 4 = “ 1 , ” t h e r e i s o u t p u t s a m e a s a c h a r a c t e r o r b o r d e r o u t p u t f r o m t h e O U T 1 p i n . D o n o t s e t C O i a n d C O i W h e n o n l y C O i a n d C O i t h e r e i s o u t p u t f r o m p i n O U T h e p o r t i o n A i n w h i c h c h a r a c t e r d o t s a r e d i s p l a y e d i s n o t m i x e d w i t h a n y T V v i d e o s i g n a l h e w a v y l i n e d a r r o w s i n t h e T a b l e d e n o t e v i d e o s i g n a l s i n d i c a t e s t o i n d i c a t e s o r B o r d e r o u t p u t B l a c k ( N o t e 1 ) Background

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8.11.6 Border

An border of 1 clock (1 dot) equivalent size can be added to a char- acter to be displayed in both horizontal and vertical directions. The border is output from the OUT1 pin. In this case, set bit 5 of a color register to “0” (character is output). Border can be specified in units of block by using the border selec- tion register (address 00E5 16). Figure 8.11.14 shows the border se- lection register. Table 8.11.6 shows the relationship between the val- ues set in the border selection register and the character border func- tion. Fig. 8.11.14 Border Selection Register Table 8.11.6 Relationship between Set Value in Border Selection Register and Character Border Function b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E516] B Name Functions After reset R W Border Selection Register

0 Block 1 OUT1 output

border selection bit (MD10) 0 : Same output as R, G, B is output 1 : Border output Indeterminate

2 Block 2 OUT1 output

border selection bit (MD20) 0 : Same output as R, G, B is output 1 : Border output Indeterminate RW RW 03to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 01 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” R, G, B output OUT1 output R, G, B output OUT1 output Functions Ordinary Border including character Example of output MDi0 Border selection register Note: i indicates 1or 2 Fig. 8.11.15 Example of Border

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8.11.7 Multiline Display

This microcomputer can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which that display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. Note: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to display off by the display control bit of the OSD control register (address 00EA 16), an OSD inter- rupt request does not occur (refer to Figure 8.11.16). Fig. 8.11.16 Note on Occurence of OSD Interrupt B l o c k 1 ( o n d i s p l a y ) Block 2 (on display) B l o c k 1 ’ ( o n d i s p l a y ) B l o c k 2 ’ ( o n d i s p l a y ) B l o c k 1 ( o n d i s p l a y ) Block 2 (on display) B l o c k 1 ’ ( o f f d i s p l a y ) Block 2’ (off display) “ O S D i n t e r r u p t r e q u e s t ” “ O S D i n t e r r u p t r e q u e s t ” “ O S D i n t e r r u p t r e q u e s t ” “OSD interrupt request” “ O S D i n t e r r u p t r e q u e s t ” “ O S D i n t e r r u p t r e q u e s t ” No “OSD interrupt request” On display (OSD interrupt request occurs at the end of block display) Off display (OSD interrupt request does not occur at the end of block display) N o O S D i n t e r r u p t r e q u e s t

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8.11.8 OSD Output Pin Control

The OSD output pins R, G, B and OUT1 can also function as ports P52–P55. Set the corresponding bit of the port P5 direction register (address 00CB16) to “0” to specify these pins as OSD output pins, or to “1” to specify as the general-purpose port P5. The OUT2 can also function as port P10. Set bit 0 of the OSD port control register (address 00EC16) to “1” (output mode). After that, set bit 7 of the OSD control register to “1” to specify the pin as OSD output pin, or set it to “0” to specify as port P10. The input polarity of the HSYNC and VSYNC , and the output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the OSD port control register (address 00EC). Set bits to “0” to specify positive polarity; set it to “1” to specify negative polarity (refer to Figure 8.11.13). The OSD port control register is shown in Figure 8.11.17. Fig. 8.11.17 OSD Port Control Register b 7 b 6 b 5 b 4 b 3 b2 b 1 b 0 O S D p o r t c o n t r o l r e g i s t e r ( C R T P ) [ A d d r e s s 0 0 E C 1 B N a m e F u n c t i o n s After reset R W OSD Port C ontrol R egister

0 H SYNC input polarity

switch bit (HSYC) 0 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t 10 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t

2 R /G /B output polarity switch

bit (R/G/B) 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

4 OUT 1 output polarity

switch bit (OUT1) 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

5 R signal output switch bit

(OP5) 0 : R s i g n a l o u t p u t M U T E s i g n a l o u t p u t

6 G signal output switch

bit(OP6) 0 : G signal output 1 : MUTE signal output

7 B signal output switch

bit(OP7) 0 : B s i g n a l o u t p u t M U T E s i g n a l o u t p u t VSYNC input polarity switch bit (VSYC) R W R W R W R W R W R W R W R W OUT 2 output polarity switch bit (OUT2) 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

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8.11.9 Raster Coloring Function

An entire screen (raster) can be colored by setting CRT port control register. Since each of the R, G and B pins can be switched to raster coloring output, 8 raster colors can be obtained. When the character color/character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2), specified for the character color/character background color, takes priority over the raster color. This ensures that character color/character background color is not mixed with the raster color. An example of raster coloring is shown in Figure 8.11.18. Fig. 8.11.18 Example of Raster Coloring H SYNC A 'A O U T 1 R G B : C h a r a c t e r c o l o r “ R E D ” ( R + O U T 1 + O U T 2 ) : B o r d e r c o l o r “ B L A C K ” ( O U T 1 + O U T 2 ) : B a c k g r o u n d c o l o r “ M A G E N T A ” ( R + B + O U T 1 + O U T 2 ) : Raster color “BLUE” (B + OUT1 + OUT2) S i g n a l s a c r o s s A A O U T 2

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 74 of 110 REJ03B0134-0100Z Fig. 8.12.1 Sequence at Detecting Software Runaway Detection

8.12 SOFTWARE RUNAWAY DETECT FUNCTION

This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. ➀ The CPU generates an undefined instruction decoding signal. ➁ The device is internally reset due to the undefined instruction de- coding signal. ➂ As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be disabled. A D H , A D L01,S–201,S–1 P C H PC L P SA D HA D L P C ? : U n d e f i n e d i n s t r u c t i o n d e c o d e U n d e f i n e d i n s t r u c t i o n d e c o d i n g s i g n a l o c c u r s I n t e r n a l r e s e t s i g n a l o c c u r s φ S Y N C A d d r e s s D a t a Re set sequence 0 1 , S FFFE 16 F F F F1 : Invalid : P r o g r a m c o u n t e r S : Stack pointer PC A D L, A D H : Jump destination address of reset

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 75 of 110 REJ03B0134-0100Z 8.13. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 V ± 10 %, hold the RESET pin at LOW for 2 µs or more, then return to HIGH. Then, as shown in Figure 8.13.2, reset is released and the program starts from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal states of the microcomputer at reset An example of the reset circuit is shown in Figure 8.13.1. The reset input voltage must be kept 0.6 V or less until the power source voltage surpasses 4.5 V. Fig. 8.13.2 Reset Sequence Fig. 8.13.1 Example of Reset Circuit P o w e r s o u r c e v o l t a g e 0 V Reset input voltage 0 V . 5 V 0 . 6 V P o w e r o n V c c R E S E T V s s Microcomputer 3 0 µF M 5 1 9 5 3 A L XI N φ R E S E T I n t e r n a l R E S E T S Y N C A d d r e s s D a t a 3 2 7 6 8 c o u n t o f XI N c l o c k c y c l e S e e n o t e Re set address from the vector table ? ? 0 1 , S 01, S-101, S-2 F F F E F F F F AD H , AD L Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 76 of 110 REJ03B0134-0100Z

8.14 CLOCK GENERATING CIRCUIT

The built-in clock generating circuit is shown in Figure 8.13.3. When the STP instruction is executed, the internal clock φ stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and “FF16” is set in timer 3 and “0716” is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to “0” before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before ex- ecution of the STP instruction). The oscillator restarts when external interrupt is accepted. However, the internal clock φ keeps its HIGH until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock φ stops in the HIGH but the oscillator continues running. This wait state is re- leased when an interrupt is accepted (See note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to “1” before executing the STP or the WIT instructions. Note: In the wait mode, the following interrupts are invalid.

• VSYNC interrupt
• OSD interrupt
• Timer 2 interrupt using external clock input from TIM2 pin as count source
• Timer 3 interrupt using external clock input from TIM3 pin as count source
• Timer 4 interrupt using f(X IN)/2 as count source
• Timer 1 interrupt using f(XIN)/4096 as count source
• f(XIN)/4096 interrupt
• Multi-master I2C-BUS interface interrupt A circuit example using a ceramic resonator (or a quartz-crystal os- cillator) is shown in Figure 8.14.1. Use the circuit constants in accor- dance with the resonator manufacture’s recommended values. A cir- cuit example with external clock input is shown in Figure 8.14.2. In- put the clock to the X IN pin, and open the XOUT pin. Fig. 8.14.1 Ceramic Resonator Circuit Example Fig. 8.14.2 External Clock Input Circuit Example X IN XOUT C IN Microcomputer C OUT X IN Microcomputer Vcc Vss External oscillation circuit Fig. 8.14.3 Clock Generating Circuit Block Diagram I n t e r r u p t r e q u e s t I n t e r r u p t d i s a b l e f l a g I R e s e t S Q RSTP instruction S Q RW I T i n s t r u c t i o n SQ R STP instruction R e s e t I n t e r n a l c l o c k φ 1 / 2 1/8 T i m e r 3 T i m e r 4 XOUTXI N T 3 4 M 0 T34M2 S e l e c t i o n g a t e : C o n n e c t e d t o b l a c k s i d e a t r e s e t T 3 4 M : T i m e r m o d e r e g i s t e r

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 77 of 110 REJ03B0134-0100Z RESET Vss Vcc Circuit example 1 RESET Vss Vcc Circuit example 2 Note :Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage.

8.15 DISPLAY OSCILLATION CIRCUIT

The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, an RC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation cir- cuit is selected by setting bits 0 and 1 of the OSD clock selection register (address 00ED 16).

8.17 ADDRESSING MODE

The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 <Software> User’s Manual for details.

8.18 MACHINE INSTRUCTIONS

There are 71 machine instructions. Refer to SERIES 740 <Soft- ware> User’s Manual for details. 9. TECHNICAL NOTES

• The divide ratio of the timer is 1/(n+1).
• Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions.
• After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed.
• An NOP instruction is needed immediately after the execution of a PLP instruction.
• In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1µF) directly between the V CC pin–VSS pin and the VCC pin– CNV SS pin, using a thick wire.
• [Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCUs] There are differences in electric characteristics, operation mar- gin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manu- facturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Fig. 8.15.1 Display Oscillation Circuit

8.16 AUTO-CLEAR CIRCUIT

When a power source is supplied, the auto-clear function will oper- ate by connecting the following circuit to the RESET pin. Fig. 8.16.1 Auto-clear Circuit Example OSC2OSC1 L C1 C2

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 78 of 110 REJ03B0134-0100Z 10. ABSOLUTE MAXIMUM RATINGS 11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Power source voltage VCC Input voltage CNV SS Input voltage P0 0–P07,P10–P17, P20–P27, P30–P34, OSC1, XIN, HSYNC , VSYNC , RESET Output voltage P0 0–P07, P10–P17, P20–P27, P30–P32, R, G, B, OUT1, D-A, XOUT , OSC2 Circuit current R, G, B, OUT1, P1 0–P17, P20–P27, P30, P31, D-A Circuit current R, G, B, OUT1, P0 0–P07, P10, P15–P17, P20–P23, P30–P32, D-A Circuit current P1 1–P14 Circuit current P2 4–P27 Power dissipation Operating temperature Storage temperature Symbol V CC VI VI VO IOH IOL1 IOL2 IOL3 Pd Topr Tstg Conditions All voltages are based on VSS . Output transistors are cut off. T a = 25 °C Ratings –0.3 to 6 –0.3 to 6 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 6 (Note 2) 0 to 10 (Note 3) 550 –10 to 70 –40 to 125 Unit V V V V mA mA mA mA mW Parameter V V V V V V V mA mA mA mA MHz MHz kHz MHz kHz Max. 5.5 VCC VCC

0.4 VCC

0.3 VCC

0.2 VCC

8.1 8.0 100 400 Power source voltage (Note 4), During CPU, CRT operation Power source voltage “H” input voltage P0 0–P07,P10–P17, P20–P27, P30–P34, SIN, SCLK , HSYNC , VSYNC , RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3 “H” input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) “L” input voltage P0 0–P07,P10–P17, P20–P27, P30–P34 “L” input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) “L” input voltage H SYNC , VSYNC , RESET,TIM2, TIM3, INT1, INT2, INT3, XIN, OSC1, SIN, SCLK “H” average output current (Note 1) R, G, B, OUT1, D-A, P10–P17, P20–P27, P30, P31 “L” average output current (Note 2) R, G, B, OUT1, D-A, P00–P07, P10, P15–P17, P20–P27, P30–P32 “L” average output current (Note 2) P11–P14 “L” average output current (Note 3) P24–P27 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for CRT display) (Note 5) OSC1 Input frequency TIM2, TIM3 Input frequency S CLK Input frequency SCL1, SCL2 VCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 fCPU fCRT fhs1 fhs2 fhs3 Min. 4.5 0.8VCC 0.7VCC 7.9 5.0 Typ. 5.0 8.0 LimitsSymbol Parameter Unit Notes 1:The total current that flows out of the IC must be 20 mA (max.). 2:The total input current to IC (IOL1 + IOL2 ) must be 30 mA or less. 3:The total average input current for ports P24–P2 7 to IC must be 20 mA or less. 4:Connect 0.1 µ F or more capacitor externally across the power source pins VCC –VSS so as to reduce power source noise. Also connect 0.1 µ F or more capacitor externally across the pins VCC –CNV SS . 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 79 of 110 REJ03B0134-0100Z Max. 300 0.4 0.4 0.6 3.0 0.7 1.3 130 I CC VOH VOL VT+ – VT– IIZH IIZL R BS VCC = 5.5 V, f(XIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V VCC = 4.5 V IOL = 10.0 mA VCC = 5.0 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 4.5 V IOL = 3 mA IOL = 6 mA mA µA V V V µA µA Ω Power source current “H” output voltageR, G, B, OUT1, D-A, P10–P17 P20–P27, P30, P31 “L” output voltageR, G, B, OUT1, D-A, P00–P07, P10, P15–P17, P20–P23, P30–P32 “L” output voltage P11–P14 “L” output voltage P11–P14 Hysteresis RESET Hysteresis (Note) HSYNC , VSYNC , TIM2, TIM3, INT1–INT3, SCL1, SCL2, SDA1, SDA2, S IN, SCLK “H” input leak current RESET, P00–P07, P10–P17, P20–P27, P30–P37, HSYNC , VSYNC “L” input leak current RESET, P00–P07, P10–P17, P20–P27, P30–P37, HSYNC , VSYNC I2C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) Limits Min. 2.4 12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Typ. 0.5 0.5 Symbol Parameter T est conditions Unit System operation Stop mode OSD OFF OSD ON Test circuit VCC = 5.5 V, f(XIN) = 8 MHz 1 Notes 1:The total current that flows out of the IC must be 20 mA or less. 2:The total input current to IC (IOL1 + IOL2 ) must be 30 mA or less. 3:The total average input current for ports P24–P27 to IC must be 20 mA or less. 4:Connect 0.1 µF or more capacitor externally between the power source pins VCC –VSS so as to reduce power source noise. Also connect 0.1 µF or more capacitor externally between the pins VCC –CNV SS . 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6:P06, P07, P15, P23, P24 have hysteresis when used as interrupt input pins or timer input pins. P11–P14 have hysteresis when these pins are used as multi- master I2C-BUS interface ports. P20–P22 have the hysteresis when used as serial I/O pins. 7:Pin names in each parameter are described as below. (1) Dedicated pins: dedicated pin names. (2) Double-/triple-function ports

• Same limits: I/O port name.
• Function other than parts vary from I/O port limits: function pin name.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 80 of 110 REJ03B0134-0100Z Fig.12.1 Measurement V s s V c c V VOH or VOL IO H o r IO L 4 . 5 V E a c h o u t p u t p i n A f t e r s e t t i n g e a c h o u t p u t p i n t o H I G H l e v e l w h e n m e a s u r i n g VO H a n d t o L O W l e v e l w h e n m e a s u r i n g VO e a c h p i n i s m e a s u r e d Vss Vcc 5 . 0 V Each input pin V s s V c c VBS 4 . 5 V S C L 1 o r S D A 1 IB S A R B S = VB IB S S C L 2 o r S D A 2 R B S V s s V c c 5 . 5 V Each input pin A IIZH or IIZL A V s s V c cXI N XO U T O S C 1 O S C 2 I c c 8 . 0 0 M H z P i n VC C i s m a d e t h e o p e r a t i o n s t a t e a n d i s m e a s u r e d t h e c u r r e n t w i t h a c e r a m i c r e s o n a t o r + Power source voltage

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 81 of 110 REJ03B0134-0100Z Max. Min. Typ. 2.5 13. A-D COMPARISON CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted) Resolution Absolute accuracy Max. bits LSB Min. Limits UnitTest conditionsParameterSymbol Typ. 15. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Max. 1000 300 Min. 1.3 0.6 1.3 20+0.1C b 0.6 20+0.1Cb 100 0.6 0.6 Max. 300 0.9 300 µs µs µs ns µs µs ns ns µs µs UnitStandard clock mode High-speed clock modeParameterSymbol Note: Cb = total capacitance of 1 bus line Fig.15.1 Definition Diagram of Timing on Multi-master I2C-BUS Min. 4.7 4.0 4.7 4.0 250 4.7 4.0 SDA SCL P tBUF S tHD ;STA tLOW tR tHD ;DAT tHIGH tF tSU ;DAT tSU ;STA Sr P tSU ;STOtHD ;STA S Sr P : Start condition : Restart condition : Stop condition 14. D-A CONVERSION CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted) Resolution Absolute accuracy Setting time Output resistor bits LSB µs kΩ Limits UnitTest conditionsParameterSymbol tsu Ro Note: Only M37221EASP/FP have a built-in D-A converter.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 82 of 110 REJ03B0134-0100Z 16. PROM PROGRAMMING METHOD The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a general- purpose PROM programmer using a special programming adapter. Product M37221EASP M37221EAFP The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 16.1 is recommended to verify programming. Fig. 16.1 Programming and Testing of One Time PROM Version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Name of Programming Adapter PCA7408 PCA7439

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 83 of 110 REJ03B0134-0100Z 17. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM product:

• Mask ROM Order Confirmation Form
• Mark Specification Form
• Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies) or FDK

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 84 of 110 REJ03B0134-0100Z 18. ONE TIME PROM VERSION M37221EASP/FP MARKING M37221EASP XXXXXX XXXXXX is lot number M37221EAFP XXXXXX XXXXXX is lot number

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 85 of 110 REJ03B0134-0100Z P06/INT2/A-D4 XOUT H SYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P30/A-D5 P31/A-D6 RESET OSC1/P3 3 OSC2/P3 4 VCC P17/A-D3 M37221M4H/M6H/M8H/MAH-XXXSP 19. APPENDIX Pin Configuration (TOP VIEW) Outline 42P4B Outline 42P2R-A/E XOUT P00/PWM0 P 01/ P W M 1 P 02/ P W M 2 P 03/ P W M 3 P 04/ P W M 4 CNV SS XIN VSS P52/R P53/G P54/B P 55/ O U T 1 P 20/ SC L K P 21/ SO U T P 22/ SI N P 10/ O U T 2 P11/SCL1 P26 P27 D-A P32 OSC1/P3 3 OSC2/P3 4 P50/HSYN C P51/VSYN C P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET VC C P15/A-D1/INT3 P14/SDA2 P13/SDA1 P12/SCL2 M37221M4H/M6H/M8H/MAH-XXXFP

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 86 of 110 REJ03B0134-0100Z Outline 42P4B Outline 42P2R-A/E XO U T P 50/ H S Y N C P51/VSYN C P00/PWM0 P 01/ P W M 1 P 02/ P W M 2 P 03/ P W M 3 P 04/ P W M 4 P 05/ P W M 5 P07/INT1 P 23/ T I M 3 P 24/ T I M 2 P 25 CNV SS XI N VSS P 52/ R P53/G P54/B P 55/ O U T 1 P 20/ SC L K P 21/ SO U T P 22/ SI N P 10/ O U T 2 P 11/ S C L 1 P 12/ S C L 2 P 13/ S D A 1 P 14/ S D A 2 RESET VCC M E A F P P26 P27 D-A P32 OSC1/P3 3 OSC2/P3 4 P06/INT2/A-D4 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 P06/INT2/A-D4 XOUT H SYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNV SS XIN VSS P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P3 3 OSC2/P3 4 VCC P17/A-D3 M37221EASP

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 87 of 110 REJ03B0134-0100Z Memory Map 0 0 0 01 00C0 16 00FF16 0 1 B F1 06B716 A 0 0 01 SFR area Not used Not used N o t u s e d F F F F1 F F D E1 FF0016 060016 I n t e r r u p t v e c t o r a r e a N o t u s e d 1000016 11FFF 16 1FFFF 16 OSD ROM (8K bytes) S p e c i a l p a g e OSD RAM (96 bytes) (See note) Zero page Note: Refer to Table 8.11.4 OSD RAM. ■ M 3 7 2 2 1 M 4 H/M6H - X X X S P / F P C000 16 0 1 7 F1 M37221 M6H- XXXSP/FP RAM (448 bytes) ROM (16K bytes) ROM (24K bytes) M37221 M6H- XXXSP/FP M37221 M4H- XXXSP/FP 02FF16 C 016 02E016 RO M correction function Vector 1: address 02C016 Vector 2: address 02E016 M 37221M4H- XXXSP/FP RAM (384 bytes)

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 88 of 110 REJ03B0134-0100Z 0 0 0 01 00C0 16 00FF16 0 1 F F1 06B716 6 0 0 01 SFR area N o t u s e d F F F F1 F F D E1 FF0016 0 6 0 01 Interrupt vector area Not used 1 0 0 0 01 11FFF 16 1FFFF 16 OSD ROM (8K bytes) S p e c i a l p a g e O S D R A M b y t e s S e e n o t e Zero page M 37221M8H- XXXSP/FP RAM (576 bytes) 0 3 B F1 0 3 0 01 02FF16 0 2 C 01 021716 N o t u s e d 2 p a g e r e g i s t e r N o t u s e d 021B16 Note: Refer to Table 8.11.4 OSD RAM. ■ M 3 7 2 2 1 M 8H/MAH-XXXSP/FP , M 3 7 2 2 1 E A S P / F P 02E016 033F16 80 0 01 RO M correction function Vector 1: address 02C016 Vector 2: address 02E016 N o t u s e d M 3 7 2 2 1 M 8 H- X X X S P/FP R A M K b y t e s M37221MAH- XXXS P/FP, M 37221EASP/FP RAM (40K bytes) M37221MAH- XXXSP/FP, M 37221EASP/FP RAM (704 bytes)

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 89 of 110 REJ03B0134-0100Z Memory Map of Special Function Register (SFR) P 3 0 SP31S PW0PW1PW2PW3PW4PW5PW6PW7 PN2PN3PN4 SM0SM1SM2SM3SM5SM6 001 0016 0016 000 00 ???? 0016 ? ? DA1SDA2S DA10DA11DA12DA13DA14DA15 D A 2 0DA21DA22DA23DA24DA25 SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RB W LRBAD0AASALPINBBTRXMST BC0BC1BC2ES0ALS10BIT SADBSEL 0BSEL 1 CCR0CCR1CCR2CCR3CCR4FAST MODE ACK BITACK 0016 0016 0016 000 001 ?0 D 01 D 11 D 21 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 C 01 C 11 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C 91 C B1 C C 1 C D 1 C E1 C F1 CA 16 Port P5 (P5) P o r t P 5 d i r e c t i o n r e g i s t e r ( D 5 ) P o r t P 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( P 3 S ) ( N o t e 1 ) D A - H r e g i s t e r ( D A - H ) D A - L r e g i s t e r ( D A - L ) P W M 0 r e g i s t e r ( P W M 0 ) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) R e g i s t e r P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( D 0 ) P W M 1 r e g i s t e r ( P W M 1 ) P W M 2 r e g i s t e r ( P W M 2 ) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Serial I/O mode register (SM) Serial I/O regsiter (SIO) DA1 conversion register (DA1) (Note 2) DA2 conversion register (DA2) (Note 2) I C data shift register (S0)2 I C address register (S0D)2 I C status register (S1)2 I C control register (S1D)2 I C clock control register (S2)2 N o t e 1 : A s f o r , f i x b i t s 2 a n d 3 t o “ 0 . ” d o n o t h a v e t h i s r e g i s t e r F i x t h i s r e g i s t e r t o 0016 0 01 0 01 0016 0016 001 A d d r e s s S F R a r e a a d d r e s s e s C t o D b 7b 0 b 7 b0 Bit allocation S t a t e i m m e d i a t e l y a f t e r r e s e t : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t: F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o F u n c t i o n b i t : N o f u n c t i o n b i t : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “ 0 ” i m m e d i a t e l y a f t e r r e s e t 0 : “ 1 ” i m m e d i a t e l y a f t e r r e s e t < B i t a l l o c a t i o n > S t a t e i m m e d i a t e l y a f t e r r e s e t > M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221M4H/M6H/M8H/MAH-XXXSP/FP

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 90 of 110 REJ03B0134-0100Z State immediately after reset b 7 b0b 7b 0 HR0H R 1H R 2H R 3HR4H R 5 CV10C V 1 1CV12CV13CV14C V 1 5C V 1 6 CV20CV21CV22CV23CV24CV25CV26 CS10C S 1 1CS20CS21 MD10MD20 CO01CO02CO03C O 0 5 CO11CO12CO13C O 1 5 CO21CO22CO23CO25 CO31CO32CO33C O 3 5 CC0C C C V S Y CR/G/BOUT1O P 5O P 6O P 7 HSYC CK0CK1 ADM0ADM1ADM2ADM4 ADC0A D C 1ADC2ADC4 ADC3A D C 5 T34M 0T 3 4 M 1T34M 2T34M 3T34M 4 T12M 0T 1 2 M 1T12M 2T12M 3T12M 4 CK0RE5 RE4 RE3 CM2 TM1RT M 2 RTM3RTM4RCRTRV S C RIT3R CK0MSR 1T1R1T2RS1R T M 1 ETM2ET M 3 ETM4ECRTEV S C EIT3E 1T1E1 T 2 ES 1 EMSE T 3 4 M 5 CK0 0016 ?0 0 0 0 0 00 FF16 0716 FF16 0716 C O 0 4 C O 1 4 CO24 C O 3 4 C O 0 6 C O 1 6 CO26 C O 3 6 C O 0 7 C O 1 7 CO27 C O 3 7 C C OUT2 I I C R I I C E F 01 F 11 F216 F316 F 41 F 51 F 61 F 71 F 81 F916 F A1 F B1 F C 1 F D 1 F E1 F F1 E 01 E 11 E 21 E 31 E 41 E516 E616 E716 E 81 E 91 E B1 E C 1 ED 16 EE 16 E F1 E A1 A d d r e s s O S D c o n t r o l r e g i s t e r ( C C ) O S D p o r t c o n t r o l r e g i s t e r ( C R T P ) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 1 (TM1) V e r t i c a l r e g i s t e r 2 ( C V 2 ) C o l o r r e g i s t e r 0 ( C O 0 ) Color register 1 (CO1) C h a r a c t e r s i z e r e g i s t e r ( C S ) B o r d e r s e l e c t i o n r e g i s t e r ( M D ) R egister H o r i z o n t a l r e g i s t e r ( H R ) Vertical register 1 (CV1) T i m e r 2 ( T M 2 ) T i m e r 3 ( T M 3 ) T i m e r 4 ( T M 4 ) T i m e r 1 2 m o d e r e g i s t e r ( T 1 2 M ) Timer 34 mode register (T34M) P W M 5 r e g i s t e r ( P W M 5 ) I n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( R E ) Test register (TEST) Interrupt request register 1 (IR EQ 1) Interrupt request register 2 (IR EQ 2) Interrupt control register 1 (IC O N 1) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) Color register 2 (CO2) C o l o r r e g i s t e r 3 ( C O 3 ) O S D c l o c k s e l e c t i o n r e g i s t e r ( C K ) CPU mode register (CPUM) Bit allocation 0016 0016 0016 0016 0016 0016 0016 0016 0016 000 0 111 1 10 0 0 00 0016 000 000 0 01 0 ? 0 000???? 0 0000?0? 0000000? 1 1111100 0016 0016 0 01 0 01 0016 S F R a r e a a d d r e s s e s E t o F : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o Function bit : No function bit : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N am e : : “ 0 ” i m m e d i a t e l y a f t e r r e s e t 0 : “ 1 ” i m m e d i a t e l y a f t e r r e s e t < B i t a l l o c a t i o n >< S t a t e i m m e d i a t e l y a f t e r r e s e t >

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 91 of 110 REJ03B0134-0100Z b7 0 b7 0 2 1 71 2 1 81 2 1 91 2 1 B1 2 1 A1 R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) R O M c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) R O M c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) RCR1 RCR0 0016 0016 0016 0016 000 0 16 p a g e r e g i s t e r a r e a a d d r e s s e s t o A d d r e s s R e g i s t e r B i t a l l o c a t i o nS tate immediately after reset : Fix to this bit to “0” (do not write to “1”) F u n c t i o n b i t : N o f u n c t i o n b i t : Fix to this bit to “1” (do not write to “0”) Name : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “ 1 ” i m m e d i a t e l y a f t e r r e s e t N o t e : O n l y M 3 7 2 2 1M4H/M6H/ M 8H / M AH-XXXSP/FP a n d M 3 7 2 2 1 E A S P / F P h a v e 2 p a g e r e g i s t e r. . < B i t a l l o c a t i o n > S t a t e i m m e d i a t e l y a f t e r r e s e t > bb

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 92 of 110 REJ03B0134-0100Z Internal State of Processor Status Register and Program Counter at Reset b 7 b0 b 7 b 0 R e g i s t e r P r o c e s s o r s t a t u s r e g i s t e r ( P S ) B i t a l l o c a t i o nS t a t e i m m e d i a t e l y a f t e r r e s e t P r o g r a m c o u n t e r ( P C H ) P r o g r a m c o u n t e r ( P C L) C o n t e n t s o f a d d r e s s F F F F1 C ontents of address FFFE16 : F i x t o t h i s b i t t o “ 0 ” d o n o t w r i t e t o Function bit : No function bit : F i x t o t h i s b i t t o “ 1 ” d o n o t w r i t e t o N a m e : : “0” immediately after reset : I n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t : “1” immediately after reset < B i t a l l o c a t i o n >< S t a t e immediately after reset>

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 93 of 110 REJ03B0134-0100Z Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: V a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e B i t a t t r i b u t e s ( N o t e 1 ) ( N o t e 2 )B i t p o s i t i o n 2 : B i t a t t r i b u t e s • • • • • • T h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e I n t h e f i g u r e t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : Bit in which nothing is assigned N o t e s 1 : V a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e a f t e r r e s e t r e l e a s e a f t e r r e s e t r e l e a s e I n d e t e r m i n a t e I n d e t e r m i n a t e a f t e r r e s e t r e l e a s e

• • • • • • R e a d e n a b l e d R e a d d i s a b l e d R
• • • • • • W r i t e e n a b l e d W r i t e d i s a b l e d c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t W b 7b6 b 5b 4b 3 b 2b 1b 0 B A f t e r r e s e t RW C P U M o d e R e g i s t e r 0 , 1 3, 4 N a m eF u n c t i o n s Processor mode bits (CM0, CM1) 0 0 : S i n g l e - c h i p m o d e N o t a v a i l a b l e Fix these bits to “1.” 1Stack page selection bit (See note) (CM2) b 1 b 0 0: 0 page 1: 1 page 1 00 5 1N o t h i n g i s a s s i g n e d . T h i s b i t i s w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s 6, 7 0Clock switch bits (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set b7 b6 C P U m o d e r e g i s t e r ( C P U M ) ( C M ) [ A d d r e s s 0 0 F B1 R W RW RW R W RW < E x a m p l e >

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 94 of 110 REJ03B0134-0100Z Address 00C716 b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C 716] B N a m e F u n c t i o n s A f t e r r e s e t R W P o r t P 3 D i r e c t i o n R e g i s t e r 0 0 : Port P30 input mode 1 : Port P30 output mode 1 0 : Port P31 input mode 1 : Port P31 output mode P o r t P 3 d i r e c t i o n r e g i s t e r R W R W i n d e t e r m i n a t eN o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e i n d e t e r m i n a t e R —3 t o 7 20 : Port P32 input mode 1 : Port P32 output mode Addresses 00C116, 00C316, 00C516 b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i=0,1,2) [Addresses 00C116, 00C3 16, 00C516] B Name Functions After reset R W Port Pi Direction Register 00 : Port Pi0 input mode 1 : Port Pi0 output mode 1 0 : Port Pi1 input mode 1 : Port Pi1 output mode 2 0 : Port Pi2 input mode 1 : Port Pi2 output mode 30 : Port Pi3 input mode 1 : Port Pi3 output mode 40 : Port Pi4 input mode 1 : Port Pi4 output mode 50 : Port Pi5 input mode 1 : Port Pi5 output mode 60 : Port Pi6 input mode 1 : Port Pi6 output mode 7 0 : Port Pi7 input mode 1 : Port Pi7 output mode Port Pi direction register RW RW RW RW RW RW RW RW

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 95 of 110 REJ03B0134-0100Z Address 00CB 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 Port P5 direction register (D5) [Address 00CB 16] b N ame Functions After reset R W P o r t P 5 D i r e c t i o n R e g i s t e r 0 , 10 R —N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e 2 0 : R s i g n a l o u t p u t P o r t P o u t p u t

3 P o r t P 53

s e l e c t i o n b i t P S E L 0 : G s i g n a l o u t p u t P o r t P o u t p u t

4 P o r t P 54

s e l e c t i o n b i t P S E L 0 : B s i g n a l o u t p u t P o r t P o u t p u t

5 P o r t P 55

s e l e c t i o n b i t P S E L 0 : OUT 1 signal output 1 : Port P55 output 6 , 7 Port P52 output signal selection bit (P52SEL) Indeterm inate R —N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e Address 00CD 16 b 7b 6b 5b 4b 3b 2b 1b 0 P 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( P 3 S ) [ A d d r e s s 0 0 C D 1 P 3 o u t p u t m o d e c o n t r o l r e g i s t e r 4 to 7 P 30 o u t p u t f o r m s e l e c t i o n b i t P S 0: CMOS output 1: N-channel open-drain output s e l e c t i o n b i t P S 0: CMOS output 1: N-channel open-drain output D A S 0: P30 input/output 1: DA1 output D A S 0: P31 input/output 1: DA2 output After reset R WBN a m e F u n c t i o n s R W R W R W R W R—N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 96 of 110 REJ03B0134-0100Z Address 00D516 b7b 6 b 5b 4b 3 b2b 1b0 P W M o u t p u t c o n t r o l r e g i s t e r 1 ( P W ) [ A d d r e s s 0 0 D 5 B After reset RW PWM Ou tput Control Register 1 N a m eF unctions DA, PWM count source selection bit (PW0) 0 : C o u n t s o u r c e s u p p l y C o u n t s o u r c e s t o p P 00/ P W M 0 o u t p u t s e l e c t i o n b i t P W 0 : P 00 o u t p u t P W M o u t p u t P 01/ P W M 1 o u t p u t s e l e c t i o n b i t P W 0: P01 output 1: PWM1 output P02/PWM2 output selection bit (PW4) 0 : P 02 o u t p u t P W M o u t p u t selection bit (PW5) 0 : P 03 o u t p u t P W M o u t p u t selection bit (PW6) 0 : P 04 o u t p u t P W M o u t p u t D A / P N 4 s e l e c t i o n b i t P W 0 : D A o u t p u t P N 4 o u t p u t selection bit (PW7) 0 : P 05 o u t p u t P W M o u t p u t RW RW RW RW RW RW RW RW Address 00D616 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R — DA output polarity selection bit (PN2) 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y PWM output polarity selection bit (PN3) DA general-purpose output bit (PN4) 0 : O u t p u t L O W O u t p u t H I G H t o 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y R W R W R W 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R — b 7b 6 b5b 4b 3 b 2b 1b0 P W M o u t p u t c o n t r o l r e g i s t e r 2 ( P N ) [ A d d r e s s 0 0 D 61 B After reset R W P W M O u t p u t C o n t r o l R e g i s t e r Nam e F u n c t i o n s 0 , 1

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 97 of 110 REJ03B0134-0100Z Address 00D716 Address 00D816 b 7 b 6 b 5 b4 b 3 b 2 b 1 b0 (RBW) t o Slave address (SAD0 to SAD6) < O n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > T h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r S T A R T c o n d i t i o n r e a d s t a t e W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r R E S T A R T c o n d i t i o n w r i t e s t a t e < I n b o t h m o d e s > T h e a d d r e s s d a t a i s c o m p a r e d I2C A d d r e s s R e g i s t e r I2C address register (S0D) [Address 00D816] B N a m e Functions A f t e r r e s e tR W R W b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 I2C d a t a s h i f t r e g i s t e r S A d d r e s s D B F u n c t i o n s A f t e r r e s e t R W I C D ata Shift R egister t o This is an 8-bit shift register to store receive data and write transmit data. I n d e t e r m i n a t e N ote: 2T o w r i t e d a t a i n t o t h e I C d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e M S T b i t t o s l a v e m o d e k e e p a n i n t e r v a l o f m a c h i n e c y c l e s o r m o r e N ame D 0 to D 7 R W

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 98 of 110 REJ03B0134-0100Z Address 00D916 Address 00DA 16 b 7 b 6 b 5 b 4 b3 b2 b1 b 0 I2C s t a t u s r e g i s t e r S A d d r e s s D I2C S t a t u s R e g i s t e r 6 , 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode B N a m e F u n c t i o n s After resetR W C o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s T R X M S T 0 : Bus free 1 : Bus busy B u s b u s y f l a g ( B B ) 0 : Interrupt request issued 1 : No interrupt request issued I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t P I N 0 : N ot detected 1 : Detected A r b i t r a t i o n l o s t d e t e c t i n g f l a g A L S e e n o t e 0 : Address mismatch 1 : Address match S l a v e a d d r e s s c o m p a r i s o n f l a g A A S S e e n o t e 0 : N o general call detected 1 : General call detected G e n e r a l c a l l d e t e c t i n g f l a g A D S e e n o t e 0 : Last bit = “0 ” 1 : Last bit = “1 ” L a s t r e c e i v e b i t ( L R B ) S e e n o t e N o t e : T h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . Indeterm inate R— RW R W ( S e e n o t e ) ( S e e n o t e ) ( S e e n o t e ) (See note) b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 t o B i t c o u n t e r N u m b e r o f t r a n s m i t r e c i e v e b i t s B C t o B C b 2 b 1 b 0

3 I2C

B U S i n t e r f a c e u s e e n a b l e b i t E S O 0 : D i s a b l e d E n a b l e d b i t A L S 0 : A d d r e s s i n g f o r m a t F r e e d a t a f o r m a t b i t B I T S A D 0 : 7 - b i t a d d r e s s i n g f o r m a t b i t a d d r e s s i n g f o r m a t 6 , 7 C o n n e c t i o n c o n t r o l b i t s b e t w e e n I C B U S i n t e r f a c e a n d p o r t s B S E L B S E L b 7 b 6 C o n n e c t i o n p o r t ( S e e n o t e ) N o n e S C L S D A S C L S D A S C L S D A S C L S D A I2C c o n t r o l r e g i s t e r S D A d d r e s s D I2C Control Register B N a m e F u n c t i o n s After reset R W R W R W R W R W R W

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 99 of 110 REJ03B0134-0100Z Address 00DB 16 Address 00DC 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 I2C c l o c k c o n t r o l r e g i s t e r S A d d r e s s D I2C C l o c k C o n t r o l R e g i s t e r t o S C L f r e q u e n c y c o n t r o l b i t s C C R t o C C R S C L m o d e s p e c i f i c a t i o n b i t F A S T M O D E 0 : S t a n d a r d c l o c k m o d e H i g h s p e e d c l o c k m o d e 0S t a n d a r d c l o c k m o d e B N a m e F u n c t i o n s A f t e r r e s e t R W A C K b i t A C K B I T A C K c l o c k b i t A C K 0 : A C K i s r e t u r n e d . A C K i s n o t r e t u r n e d 0 : N o A C K c l o c k A C K c l o c k H i g h s p e e d c l o c k m o d e S e t u p d i s a b l e d S e t u p d i s a b l e d0 0 t o 0 2 S e t u p d i s a b l e d 3 3 30 3 S e t u p d i s a b l e d 2 5 00 4 1 0 0 4 0 0 ( S e e n o t e )0 5 8 3 . 31 6 60 6 C C R v a l u e 1 C C R v a l u e . . . 1 7 . 2 3 4 . 51 D 1 6 . 63 3 . 31 E 1 6 . 1 3 2 . 31 F ( a t φ = 4 M H z , u n i t : k H z ) N o t e : A t 4 0 0 k H z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . p e r i o d p e r i o d I n t h e o t h e r c a s e s t h e d u t y i s a s b e l o w p e r i o d p e r i o d S e t u p v a l u e o f C C R C C R S e r i a l I / O m o d e r e g i s t e r ( S M ) [ A d d r e s s 0 0 D C 1 BN a m e F u n c t i o n s S e r i a l I / O M o d e R e g i s t e r 0, 1 I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s S M S M b1 b0 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 s e l e c t i o n b i t S M

3 S e r i a l I / O p o r t

s e l e c t i o n b i t S M s e l e c t i o n b i t S M 0: P20, P21 1: SCLK, SOUT 0: External clock 1: Internal clock 0: LSB first 1: MSB first 4 F i x t h i s b i t t o “ 0 . ” 7 N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s A f t e r r e s e t RW 0R W RW RW R W RW RW 0R — S e r i a l i n p u t p i n s e l e c t i o n b i t S M 0: Input signal from SIN pin. 1: Input signal from SOUT pin.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 100 of 110 REJ03B0134-0100Z Address 00E016 Addresses 00DE16 and 00DF16 b 7b 6b 5b4b 3b 2b 1b 0 D A c o n v e r s i o n r e g i s t e r i ( i = 1 , 2 ) ( D A i ) [ A d d r e s s e s 0 0 D E1 6, 0 0 D F1 A f t e r r e s e t D A c o n v e r s i o n r e g i s t e r i to D A c o n v e r s i o n s e l e c t i o n b i t D A i t o D A i b0b1b2 b3 b4 b5 000000 00000 0000 111 11111 111111 : 1 / 6 4 V c c : 2 / 6 4 V c c : 6 1 / 6 4 V c c : 6 2 / 6 4 V c c : 6 3 / 6 4 V c c : 0/64Vcc 7 0N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e R — R W R W R W BN a m e F u n c t i o n s F i x t h i s b i t t o “ 0 . ” N o t e : W h e n u s e M 3 7 2 2 1 M 4H/M6H/M8H/MAH-XXXSP/FP, t h e r e i s n o t t h i s r e g i s t e r F i x t o b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E016] B Name Functions After resetRW Horizontal Position Register 0to 6, 7 Horizontal display start positions (HR0 to HR5) 64 steps (0016 to 3F16) 0 0Nothing is assigned. These bits are write disable bits. When thses bits are read out, the values are “0.” RW

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 101 of 110 REJ03B0134-0100Z Addresses 00E116 and 00E216 Address 00E416 b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 and 2) [Addresses 00E116, 00E216] B Name Functions After reset R W Vertical Position Register i to Vertical display start positions128 steps (0016 to 7F16) Indeterminate (CVi : CVi0 to CVi6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” RW b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 C h a r a c t e r s i z e r e g i s t e r ( C S ) [ A d d r e s s 0 0 E 41 B N am e Functions After reset R W C h a r a c t e r S i z e R e g i s t e r 0, 1Ch aracter size of block 1 selection bits (CS10, CS11) 00 : Minimum s ize 01 : Medium size 10 : Large size 11 : Do not set. Indeterminate 2 , 3 t o C h a r a c t e r s i z e o f b l o c k s e l e c t i o n b i t s C S C S 0 0 : M i n i m u m s i z e M e d i u m s i z e L a r g e s i z e D o n o t s e t N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e I n d e t e r m i n a t e R W R W R —

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 102 of 110 REJ03B0134-0100Z Address 00E516 Addresses 00E616 to 00E916 b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E516] B Name Functions After reset R W Border Selection Register border selection bit (MD10) 0 : Same output as R, G, B is output 1 : Border output Indeterminate border selection bit (MD20) 0 : Same output as R, G, B is output 1 : Border output Indeterminate RW RW 03to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 01 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 C o l o r r e g i s t e r i ( C O i ) ( i = 0 t o 3 ) [ A d d r e s s e s 0 0 E 61 6 t o 0 0 E 91 B N ame F u n c t i o n s A f t e r r e s e t R W C o l o r R e g i s t e r i 0 0 R — G s i g n a l o u t p u t s e l e c t i o n b i t C O i 0 : N o c h a r a c t e r i s o u t p u t C h a r a c t e r i s o u t p u t R s i g n a l o u t p u t s e l e c t i o n b i t C O i 0: N o character is output 1: Character is output R W B s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t C O i S e e n o t e 0 : N o b a c k g r o u n d c o l o r i s o u t p u t B a c k g r o u n d c o l o r i s o u t p u t R W O U T 1 s i g n a l o u t p u t c o n t r o l b i t C O i S e e n o t e s 0 : C h a r a c t e r i s o u t p u t B l a n k i s o u t p u t R W G s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t C O i S e e n o t e 0 : N o b a c k g r o u n d c o l o r i s o u t p u t B a c k g r o u n d c o l o r i s o u t p u t R W R s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t C O i S e e n o t e 0 : N o b a c k g r o u n d c o l o r i s o u t p u t B a c k g r o u n d c o l o r i s o u t p u t R W B s i g n a l o u t p u t s e l e c t i o n b i t C O i 0 : N o c h a r a c t e r i s o u t p u t C h a r a c t e r i s o u t p u t N othing is assigned. This bit is a write disable bit. W hen this bit is read out, the value is “0.” N otes 1: Wh en bit 5 =“0” and bit 4 = “1,” there is output same as a character or border output from pin OUT1. Do not set bit 5 = “0” and bit 4 = “0.” 2: When only bit 7 =“1” and bit 5 “0,” there is output from pin OUT2.

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 103 of 110 REJ03B0134-0100Z Address 00EA16 Addresses 00EC16 b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (CC) [Address 00EA16] B Name Functions After reset R W OSD Control Register bit (CC0) (See note) 0 : All-blocks display off 1 : All-blocks display on (CC1) 0 : Block 1 display off 1 : Block 1 display on 2 0 : Block 2 display off 1 : Block 2 display on to Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Block 2 display control bit (CC2) RW RW RW 7 0 : P10 1 : OUT2 0P10/OUT2 pin switch bit (CC7) RW b 7 b 6 b 5 b 4 b 3 b2 b 1 b 0 OSD port control register (CRTP) [Address 00EC 16] B N a m e F u n c t i o n s After reset R W O S D P o r t C o n t r o l R e g i s t e r

0 H S

Y N C i n p u t p o l a r i t y s w i t c h b i t H S Y C 0 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t 10 : P o s i t i v e p o l a r i t y i n p u t N e g a t i v e p o l a r i t y i n p u t

2 R / G / B o u t p u t p o l a r i t y s w i t c h

b i t R G B 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

4 O U T 1 o u t p u t p o l a r i t y

s w i t c h b i t O U T 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

5 R s i g n a l o u t p u t s w i t c h b i t

O P 0 : R s i g n a l o u t p u t M U T E s i g n a l o u t p u t

6 G s i g n a l o u t p u t s w i t c h

b i t O P 0 : G s i g n a l o u t p u t M U T E s i g n a l o u t p u t

7 B s i g n a l o u t p u t s w i t c h

b i t O P 0 : B s i g n a l o u t p u t M U T E s i g n a l o u t p u t VS Y N C i n p u t p o l a r i t y s w i t c h b i t V S Y C R W R W R W R W R W R W R W R W O U T 2 o u t p u t p o l a r i t y s w i t c h b i t O U T 0 : P o s i t i v e p o l a r i t y o u t p u t N e g a t i v e p o l a r i t y o u t p u t

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 104 of 110 REJ03B0134-0100Z Address 00ED16 Addresses 00EE16 b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 O S D c l o c k s e l e c t i o n r e g i s t e r ( C K ) [ A d d r e s s 0 0 E D 1 B N a m e F u n c t i o n s A f t e r r e s e t R W O S D C l o c k S e l e c t i o n R e g i s t e r 0, 1OSD clock selection bits (CK0,CK1) Since the m ain clock is used as the clock for display, the oscillation frequency is lim ited. Because of this, the character size in w idth (horizontal) direction is also lim ited. In this case, pins O SC 1 and O SC 2 are also used as input ports P33 and P34 respectively. T h e c l o c k f o r O S D i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s O S C a n d O S C a c e r a m i c r e s o n a t o r o n l y f o r O S D a q u a r t z c r y s t a l o s c i l l a t o r o n l y f o r O S D a n d a f e e d b a c k r e s i s t o r S e e n o t 2 to 7 0 000000 T h e c l o c k f o r d i s p l a y i s s u p p l i e d b y c o n n e c t i n g R C o r L C a c r o s s t h e p i n s O S C a n d O S C Functions OSD oscillation frequency = f(XIN) O S D o s c i l l a t i o n f r e q u e n c y f XI N ) N ote: It is necessary to connect other ceramic resonator or quartz-crystal oscillator for OSD across the pINs XIN and XOUT . 1 1 Fix these bits to “0.” R W R W b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 A-D control register 1 (AD1) [Address 00EE16] B A f t e r r e s e t RW A - D C o n t r o l R e g i s t e r 1 t o A n a l o g i n p u t p i n s e l e c t i o n b i t s A D M t o A D M Name F u n c t i o n s b 2 b 1 b 0 A D A D A D A D A D A D D o n o t s e t D o n o t s e t

4 S t o r a g e b i t o f c o m p a r i s o n

r e s u l t A D M 0 : I n p u t v o l t a g e < r e f e r e n c e v o l t a g e I n p u t v o l t a g e r e f e r e n c e v o l t a g e I n d e t e r m i n a t e 03 T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s RW R R — to N o t h i n g i s a s s i g n e d . T h i s b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e R —

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 105 of 110 REJ03B0134-0100Z Address 00EF16 Addresses 00F416 b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0 A - D c o n t r o l r e g i s t e r 2 ( A D 2 ) [ A d d r e s s 0 0 E F1 B A f t e r r e s e t RW A - D C o n t r o l R e g i s t e r 2 to 6 , 7 N a m e F u n c t i o n s D - A c o n v e r t e r s e t b i t s A D C t o A D C b0b1b2 b3 b4 b5 N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e e d o u t t h e v a l u e s a r e 000000 00000 0000 111 11111 111111 : 3/128Vcc : 5/128Vcc : 1 2 3 / 1 2 8 V c c : 1 2 5 / 1 2 8 V c c : 1 2 7 / 1 2 8 V c c : 1/128Vcc RW R — b7b6 b5b4b3 b2b1b0 Timer mode register (T12M) [Address 00F416] B A f t e r r e s e t W Timer 12 Mode Register Nam e Functions Timer 1 count source selection bit 1 (T12M0) 0: f(XIN)/16 1: f(XIN)/4096 Timer 2 count source selection bit (T12M1) 0: Interrupt clock source 1: External clock from TIM2 pin Timer 1 count stop bit (T12M2) 0: Count start 1: Count stop Timer 2 count stop bit (T12M3) 0: Count start 1: Count stop Timer 2 internal count source selection bit 2 (T12M4) R WR WR WR WR WR0: f(XIN)/16 1: Timer 1 overflow 5 Fix this bit to “0.” 0 WR 6 , 7N othing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 106 of 110 REJ03B0134-0100Z Address 00F516 Addresses 00F916 b 7b 6 b 5b 4b 3 b 2b 1b 0 T i m e r 3 4 m o d e r e g i s t e r ( T 3 4 M ) [ A d d r e s s 0 0 F 51 B After reset RW T i m e r M o d e R e g i s t e r N a m e F u n c t i o n s T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t T M 0 RW selection bit (T34M1) 0R W T i m e r 3 c o u n t s t o p b i t T M 0: Count start 1: Count stop Timer 4 count stop bit (T34M3) 0: Count start 1: Count stop s e l e c t i o n b i t T M 0: Internal clock source 1: f(XIN)/2 s o u r c e s e l e c t i o n b i t T M 0 : T I M 3 p i n i n p u t H S Y N C p i n i n p u t RW RW RW RW 0 : f ( XI N ) / 1 6 E x t e r n a l c l o c k s o u r c e 0 : T i m e r 3 o v e r f l o w s i g n a l f XI N ) 6 , 7N othing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R N a m eF u n c t i o n s I N T 1 p o l a r i t y s w i t c h b i t R E 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y 0 : P o s i t i v e p o l a r i t y N e g a t i v e p o l a r i t y I N T 2 p o l a r i t y s w i t c h b i t R E I N T 3 p o l a r i t y s w i t c h b i t R E N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s Fix These bits to “0.” F i x t h i s b i t t o “ 0 . ” N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s After reset R W R — R W R W R W R W R — R W b 7b 6b 5b 4b 3b 2b 1b 0 I n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( R E ) [ A d d r e s s 0 0 F 9 B I n t e r r u p t I n p u t P o l a r i t y R e g i s t e r 1,2 000

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 107 of 110 REJ03B0134-0100Z Address 00FB16 Addresses 00FC16 B A f t e r r e s e t RW 0 , 1 3 to 7 Indeterminate Indeterminate Name F u n c t i o n s F i x t h e s e b i t s t o “ 1 . ” 1S t a c k p a g e s e l e c t i o n b i t C M S e e n o t e 0: 0 page 1: 1 page C P U m o d e r e g i s t e r ( C M ) [ A d d r e s s 0 0 F B1 R W RW R W N o t e : T h i s b i t i s s e t t o “ 1 ” a f t e r t h e r e s e t r e l e a s e . b 7b 6b 5b4b 3 b 2b 1b0 C P U M o d e R e g i s t e r 11 00111 F i x t h e s e b i t s t o “ 0 . ” b 7b 6 b 5b 4b 3 b 2b 1b0 I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 0 0 F C BN a m e Functions A f t e r r e s e t RW I n t e r r u p t R e q u e s t R e g i s t e r 1 0 0 : N o interrupt request issued 1 : Interrupt request issued T i m e r 1 i n t e r r u p t r e q u e s t b i t T M R request bit (TM2R)

2 T i m e r 3 i n t e r r u p t

r e q u e s t b i t T M R 3T i m e r 4 i n t e r r u p t r e q u e s t b i t T M R bit (CRTR) 5 VS Y N C i n t e r r u p t r e q u e s t b i t V S C R 6 M u l t i m a s t e r I2C B U S i n t e r f a c e i n t e r r u p t r e q u e s t b i t I I C R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o interrupt request issued 1 : Interrupt request issued 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 ✽ ✽: “0” can be set by software, but “1” cannot be set. R R R R R R R R I N T 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t I T R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 108 of 110 REJ03B0134-0100Z Address 00FD16 Addresses 00FE16 b 7b 6b 5b 4b 3 b 2b 1b0 I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 0 0 F D BN a m e F u n c t i o n s After reset RW I n t e r r u p t R e q u e s t R e g i s t e r 2 r e q u e s t b i t I T R 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d r e q u e s t b i t I T R r e q u e s t b i t S R 4 f ( XI N ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t M S R 5, 6 7 F i x t h i s b i t t o “ 0 . ” 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d 0 : N o interrupt request issued 1 : Interrupt request issued c a n b e s e t b y s o f t w a r e b u t c a n n o t b e s e t 0 ✽ 0 ✽ 0 ✽ 0 ✽ 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d R R R R R — R W0 N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e 0R —Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” b 7b 6 b 5b 4b 3 b 2b 1b 0 I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 0 0 F E1 BN a m e F u n ctions R W I n t e r r u p t C o n t r o l R e g i s t e r 1 enable bit (TM1E) 0 : Interrupt disabled 1 : Interrupt enabled enable bit (TM2E) enable bit (TM3E) (CRTE) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW RW RW R Timer 4 interrupt enable bit (TM4E) 0 : Interrupt disabled 1 : Interrupt enabled bit (VSCE) 0 : Interrupt disabled 1 : Interrupt enabled 0 RW 6 0 : Interrupt disabled 1 : Interrupt enabled 0 RW INT3 external interrupt enable bit (IT3E) Multi-master I2C-BU S interface interrupt enable bit (IICE) 0 : Interrupt disabled 1 : Interrupt enabled W After reset

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 109 of 110 REJ03B0134-0100Z Address 00FF16 Addresses 021B16 b 7b 6 b 5b 4b 3 b 2b 1b0 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 0 0 F F1 BN a m eF u n c t i o n s I n t e r r u p t C o n t r o l R e g i s t e r 2 enable bit (IT1E) 0 : Interrupt disabled 1 : Interrupt enabled enable bit (IT2E)

2 Serial I/O interrupt

enable bit (S1E) 4 f(XIN)/4096 interrupt enable bit (MSE) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fix this bit to “0.” Fix these bits to “0.” 000 After reset RW RW RW RW RW R R W W5 to 7 b7 b6 b5 b4 b3 b2 b1 b0 R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) [ A d d r e s s 0 2 1 B1 BA f t e r reset R O M C o r r e c t i o n E n a b l e R e g i s t e r 0: Disabled 1: Enabled 1: Enabled t o N o t h i n g i s a s s i g n e d . T h e s e b i t s a r e w r i t e d i s a b l e b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e 2 , 3 F i x t h e s e b i t s t o “ 0 . ” 0 RW RW RW RW F

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP Rev.1.00 Oct 01, 2002 page 110 of 110 REJ03B0134-0100Z 20. PACKAGE OUTLINE SDIP42-P-600-1.78 Weight(g) JEDEC Code 4.1 Alloy 42/Cu Alloy 42P4B Plastic 42pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 –1 . 778 – – 15.24 – 3.0 – – 0° –1 5 ° –– 5 . 5 e 42 22 211 E ce1 A2A1 bb1 b2e L A SEATING PLANE D MMP SSOP42-P-450-0.80 W eight(g) JEDEC Code 0.63 Alloy 42 42P2R-A/E Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .250 .050 .130 .317 .28 .6311 .30 .271 .02 .30 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .40 .20 .717 .68 .2312 .70 .150 b2 –. 5 0– 0° –1 0 ° e 42 22 211 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G –Z1 0.75 0.9 z b G

REVISION HISTORY

Rev. Date Description Page Summary M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP

1.00 Oct 01, 2002 – First edition issued

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