M36W832TE-ZAT

M36W832TE STMICROELECTRONICS | Alldatasheet

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32 Mbit (2Mb x16, Boot Block) Flash Memory

Figure 1. Packages

with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. LFBGA Connections (Top view through package)

M36W832TE, M36W832BE Signal Descriptions See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A18).Addresses A0-A18 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they con- trol the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable ( EF ) and Write Enable (WF) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (WS). Address Inputs (A19-A20).Addresses A19-A20 are inputs for the Flash component only. The Flash memory is accessed through the Chip En- able (EF ) and Write Enable (WF) signals Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF ). The Chip Enable input activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V IL and Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the standby level. Flash Output Enable (GF ). The Output Enable controls the data outputs during the Bus Read op- eration of the Flash memory. Flash Write Enable (WF ). The Write Enable controls the Bus Write operation of the Flash memory’s Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable, EF , or Write Enable, WF, whichever oc- curs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at V IH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 6, Read Protection Register and Protection Register Lock). Flash Reset (RPF ). The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked state. When Reset is at V IH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is re- quired to ensure valid data outputs. SRAM Chip Enable (E1S , E2S). The Chip En- able inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Write Enable (WS). The Write Enable in- put controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM memory. GS is ac- tive low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VDDF Supply Voltage (2.7V to 3.3V). VDDF pro- vides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQF and VDDS Supply Voltage (2.7V to 3.3V). VDDQF provides the power supply for the Flash memory I/O pins and VDDS provides the power supply for the SRAM control pins. This allows all Outputs to be powered independently of the Flash core power supply, V DDF . VDDQF can be tied to VDDS VPPF Program Supply Voltage. VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. The Supply Volt- age V DDF and the Program Supply Voltage VPPF can be applied in any order. If VPPF is kept in a low voltage range (0V to 3.6V) VPPF is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while VPPF > VPP1 en- ables these functions (see Table 15, DC Charac- teristics for the relevant values). V PPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on Program or Erase, however for Double or Quadruple Word Program the results are uncertain. If V PPF is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is com- pleted (see Table 17 and 18).

the Flash and SRAM chips, respectively. PPF program and erase currents. ory and, E1S and E2S for the SRAM. Figure 4. Functional Block Diagram

32 Mbit (x16)

8 Mbit (x16)

Table 2. Main Operation Modes Note: X = VIL or VIH, VPPFH = 12V ± 5%.

programmed in-system on a Word-by-Word basis. maps are shown in Figure 5, Block Addresses. hardware protection against program and erase. program in any other block and then resumed. programmed and erased over 100,000 cycles. Block and Protection Register Memory Map. ings necessary for program and erase operations. consistent with JEDEC standards. Figure 5. Flash Block Addresses Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses.

4 KWords

32 KWords

4 KWord Blocks

32 KWord Blocks

Figure 6. Flash Security Block and Protection Register Memory Map Note: 1. Bit 2 of the Protection Register Lock must not be programmed to 0.

Figure 7. SRAM Block Diagram

M36W832TE, M36W832BE OPERATING MODES Flash Bus Operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby, Automatic Standby and Re- set. See Table 2, Main Operation Modes, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output En- able must be at V IL in order to perform a read op- eration. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read de- pends on the previous command written to the memory (see Command Interface section). See Figure 10, Flash Read Mode AC Waveforms, and Table 16, Flash Read AC Characteristics, for de- tails of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write.Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V IL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figures 11 and 12, Flash Write AC Wave- forms, and Tables 17 and 18, Write AC Character- istics, for details of the timing requirements. Output Disable. The data outputs are high im- pedance when the Output Enable is at V IH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. The memory is in stand-by when Chip Enable is at V IH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V IH during a program or erase operation, the de- vice enters Standby mode when finished. Automatic Standby.Automatic Standby pro- vides a low power consumption state during Read mode. Following a read operation, the device en- ters Automatic Standby after 150ns of bus inactiv- ity even if Chip Enable is Low, V IL, and the supply current is reduced to IDD1 . The data Inputs/Out- puts will still output data if a bus Read operation is in progress. Reset. During Reset mode when Output Enable is Low, V IL, the memory is deselected and the out- puts are high impedance. The memory is in Reset mode when Reset is at V IL. The power consump- tion is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write En- able inputs. If Reset is pulled to VSSF during a Pro- gram or Erase, this operation is aborted and the memory content is no longer valid.

Table 3. Flash Command Codes command returns the memory to its Read mode. command to read the Status Register’s contents. tails on the definitions of the bits. tent of the Status Register. Locking Status, or the Protection Register. ■ The first bus cycle sets up the Erase command.

M36W832TE, M36W832BE ■ The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to V IL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will accept the Read Status Register command and the Pro- gram/Erase Suspend command, all other com- mands will be ignored. Typical Erase times are given in Table 8, Flash Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 30, Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command. Program Command. The memory array can be programmed word-by-word. Two bus write cycles are required to issue the Program Command. ■ The first bus cycle sets up the Program command. ■ The second latches the Address and the Data to be written and starts the Program/Erase Controller. During Program operations the memory will ac- cept the Read Status Register command and the Program/Erase Suspend command. Typical Pro- gram times are given in Table 8, Flash Program, Erase Times and Program/Erase Endurance Cy- cles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. See Appendix C, Figure 26, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command. This feature is offered to improve the programming throughput, writing a page of two adjacent words in paral- lel.The two words must differ only for the address A0. Programming should not be attempted when V PPF is not at VPPH . Three bus write cycles are necessary to issue the Double Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written. ■ The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. Program- ming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 27, Double Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Double Word Program command. Quadruple Word Program Command. This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPPF is not at VPPH . Five bus write cycles are necessary to issue the Quadruple Word Program command. ■ The first bus cycle sets up the Quadruple Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written. ■ The third bus cycle latches the Address and the Data of the second word to be written. ■ The fourth bus cycle latches the Address and the Data of the third word to be written. ■ The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. Program- ming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 28, Quadruple Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Quadruple Word Program command. Clear Status Register Command.The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Sta- tus Register command. The bits in the Status Register do not automatical- ly return to ‘0’ when a new Program or Erase com- mand is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Program/Erase Suspend Command. The Pro- gram/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command In- terface will accept the Program/Erase Resume,

M36W832TE, M36W832BE Read Array, Read Status Register, Read Electron- ic Signature and Read CFI Query commands. Ad- ditionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, Block Lock-Down or Protection Program commands will also be ac- cepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protec- tion Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 29, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 31, Erase Suspend & Resume Flowchart and Pseudo Code for flow- charts for using the Program/Erase Suspend com- mand. Program/Erase Resume Command. The Pro- gram/Erase Resume command can be used to re- start the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the com- mand. Once the command is issued subsequent Bus Read operations read the Status Register. See Appendix C, Figure 29, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 31, Erase Suspend & Resume Flowchart and Pseudo Code for flow- charts for using the Program/Erase Resume com- mand. Protection Register Program Command.The Protection Register Program command is used to Program the 128 bit user One-Time-Programma- ble (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protec- tion Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 6, Flash Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be sus- pended. Block Lock Command. The Block Lock com- mand is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. ■ The first bus cycle sets up the Block Lock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 10 shows the protection status after issuing a Block Lock command. The Block Lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Unlock Command. The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Blocks Unlock command. ■ The first bus cycle sets up the Block Unlock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 10 shows the protection status after issuing a Block Unlock command. Refer to the “Flash Block Locking” section, for a detailed explanation. Block Lock-Down Command. A locked block cannot be Programmed or Erased, or have its pro- tection status changed when WPF is low, VIL. When WPF is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. ■ The first bus cycle sets up the Block Lock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 10 shows the protection sta- tus after issuing a Block Lock-Down command.

Table 4. Flash Commands

1. The signature addresses are listed in Tables 5, 6 and 7.
2. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.
3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

Table 5. Flash Read Electronic Signature Table 6. Flash Read Block Lock Signature Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0"; see Block Locking section. Table 7. Flash Read Protection Register and Lock Register Lock VIL VIL VIH 80h Don't Care Don't Care OTP Prot.

Table 8. Flash Program, Erase Times and Program/Erase Endurance Cycles

M36W832TE, M36W832BE Flash Block Locking The Flash Memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. ■ Lock/Unlock - this first level allows software- only control of block locking. ■ Lock-Down - this second level requires hardware interaction before locking can be changed. ■ VPPF ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 10, de- fines all of the possible protection states (WPF DQ1, DQ0), and Appendix C, Figure 32, shows a flowchart for the locking operations. Reading a Block’s Lock Status.The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protec- tion status of that block. The lock status is repre- sented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock com- mand and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State.The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any pro- gram or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State.Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered- down. The status of an unlocked block can be changed to Locked or Locked-Down using the ap- propriate software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State. Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using soft- ware commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock- Down command. Locked-Down blocks revert to the Locked state when the device is reset or pow- ered-down. The Lock-Down function is dependent on the WPF input pin. When WPF=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from pro- gram, erase and protection status changes. When WPF =1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individu- ally unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while WPF remains high. When WPF is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WPF was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend. Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase opera- tion, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After complet- ing any desired lock, read, or program operations, resume the erase operation with the Erase Re- sume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D, Com- mand Interface and Program/Erase Controller State, for detailed information on which com- mands are valid during erase suspend.

Table 9. Block Lock Status Table 10. Protection Status in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.
2. A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

M36W832TE, M36W832BE Flash Status Register The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, re- fer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V IH. Either Chip En- able or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 11, Status Register Bits. Refer to Table 11 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7).The Pro- gram/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Pro- gram/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High . During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Reg- ister should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, V PPF Status and Block Lock Status bits should be tested for errors. Erase Suspend Status (Bit 6).The Erase Sus- pend Status bit indicates that an Erase operation has been suspended or is going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Pro- gram/Erase Resume command. The Erase Suspend Status should only be consid- ered valid when the Program/Erase Controller Sta- tus bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of the Program/Erase Sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status (Bit 5).The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/ Erase Controller has applied the maximum num- ber of pulses to the block and still failed to verify that the block has erased correctly. The Erase Sta- tus bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4).The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to ‘1’), the Pro- gram/Erase Controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. V PPF Status (Bit 3).The VPPF Status bit can be used to identify an invalid voltage on the VPPF pin during Program and Erase operations. The VPPF pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can oc- cur if VPPF becomes invalid during an operation. When the VPPF Status bit is Low (set to ‘0’), the voltage on the VPPF pin was sampled at a valid voltage; when the VPPF Status bit is High (set to ‘1’), the VPPF pin has a voltage that is below the VPPF Lockout Voltage, VPPLK , the memory is pro- tected and Program and Erase operations cannot be performed. Once set High, the V PPF Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2).The Program Suspend Status bit indicates that a Program oper- ation has been suspended. When the Program Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Re- sume command. The Program Suspend Status should only be considered valid when the Pro-

operation rather than entering the Suspend mode. sued the Program Suspend Status bit returns Low. the new command will appear to fail. reserved. Its value must be masked. Pseudo Codes, for using the Status Register. Table 11. Flash Status Register Bits Note: Logic level '1' is High, '0' is Low.

6 Erase Suspend Status

5 Erase Status

4 Program Status

3 VPPF Status

2 Program Suspend Status

1 Block Protection Status

0 Reserved

M36W832TE, M36W832BE SRAM Operations There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Byte Read mode whenever Write Enable, WS , is at VIH, Output Enable, GS, is at VIL, Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at VIH, and UBS or LBS is at VIL. The SRAM is in Word Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Byte Enable inputs UBS and LBS are both at VIL and the two Chip Enable inputs, E1S, and E2S are Don’t Care. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (t E1LQV , tE2HQV , or tGLQV ) rath- er than the address. Data out may be indetermi- nate at tE1LQX , tE2HQX and tGLQX , but data lines will always be valid at tAVQV (see Table 20, Figures 14 and 15). Write.Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever WS and E1S are at VIL, and E2S is at VIH. Either the Chip Enable inputs, E1S and E2S, or the Write Enable input, WS, must be deasserted during ad- dress transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2S is at VIH and WS is at VIL. The data is latched o the falling edge of E1S, the rising edge of E2S or the falling edge of WS, whichever occurs last. The Write cycle is terminated on the rising edge of E1S , the rising edge of WS or the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S=V IL, E2S=VIH and GS =V IL), then WS will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. The Data input must be valid for tD- VWH before the rising edge of Write Enable, for tDVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX , tE1HAX or tE2LAX (see Table 21, Figure 17, 18, 19 and 20). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which in- vokes an automatic standby mode (see Table 20 and Figure 16). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S at VIH or E2S at VIL. Data Retention.The SRAM data retention per- formance as VDDS goes down to VDR are de- scribed in Table 22, Figures 21 and 22, SRAM Low V DDS Data Retention AC Waveforms, E1S Controlled and SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled, respectively. Output Disable.The data outputs are high im- pedance when the Output Enable, GS, is at VIH with Write Enable, WS, at VIH.

Table 12. Absolute Maximum Ratings

Table 15. DC Characteristics

M36W832TE, M36W832BE IPPE Program Current (Erase) Flash Erase in progress VPPF = 12V ± 5% 31 0 m A Erase in progress VPPF = VDDF 15 µ A VIL Input Low Voltage Flash & SRAM VDDQF = VDDS ≥ 2.7V –0.3 0.8 V VIH Input High Voltage Flash & SRAM VDDQF = VDDS ≥ 2.7V 0.7VDD QF VDDQF +0.4 V VOL Output Low Voltage Flash & SRAM VDDQF = VDDS = VDD min IOL = 100µA 0.1 V VOH Output High Voltage Flash & SRAM VDDQF = VDDS = VDD min IOH = –100µA 2.4 V VPPL Program Voltage (Program or Erase operations) Flash 1.65 3.6 V VPPH Program Voltage (Program or Erase operations) Flash 11.4 12.6 V V PPLK Program Voltage (Program and Erase lock-out) Flash 1 V VLKO VDDF Supply Voltage (Program and Erase lock-out) Flash 2 V Symbol Parameter Device Test Condition Min Typ Max Unit

Figure 10. Flash Read Mode AC Waveforms Table 16. Flash Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. GF may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV .

Figure 11. Flash Write AC Waveforms, Write Enable Controlled

Table 17. Flash Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

1. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).

Figure 12. Flash Write AC Waveforms, Chip Enable Controlled

Table 18. Flash Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.

1. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).

Figure 13. Flash Power-Up and Reset AC Waveforms Table 19. Flash Power-Up and Reset AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.

1. Sampled only, not 100% tested.
2. It is important to assert RPF in order to allow proper CPU initialization during power up or reset.

Table 20. SRAM Read AC Characteristics Note: 1. Sampled only. Not 100% tested. Figure 17. SRAM Write AC Waveforms, E1S or E2S Controlled Note: 1. DQ0-DQ15 are high impedance if GS = VIH.

1. If E1S or E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

Figure 20. SRAM Write Cycle Waveform, UBS and LBS Controlled GS Low, Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied.

Table 21. SRAM Write AC Characteristics

Figure 23. Stacked LFBGA66 12x8mm, 8x8 array, 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 23. Stacked LFBGA66, 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mechanical Data

Figure 24. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)

Figure 25. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)

Table 24. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. Table 25. Daisy Chain Ordering Scheme please contact the STMicroelectronics Sales Office nearest to you.

Table 26. Top Boot Block Addresses,

Table 27. Bottom Boot Block Addresses,

command to return to Read mode. Table 28. Query Structure Overview Note: Query data are always presented on the lowest order data outputs. Table 29. CFI Query Identification String Note:Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 30. CFI Query System Interface Information

Table 31. Device Geometry Definition Number of Erase Block Regions within the device. Erase Blocks of the same size.

Table 32. Primary Algorithm-Specific Extended Query Table Note: 1. See Table 29, offset 15 for P pointer definition. contains less significant byte. (P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space. Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable.

Table 33. Security Code Area

Figure 26. Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Figure 27. Double Word Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

Figure 28. Quadruple Word Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

Figure 29. Program Suspend & Resume Flowchart and Pseudo Code

Figure 30. Erase Flowchart and Pseudo Code Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

Figure 31. Erase Suspend & Resume Flowchart and Pseudo Code

Figure 32. Locking Operations Flowchart and Pseudo Code

Figure 33. Protection Register Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Table 34. Write State Machine Current/Next, sheet 1 of 2 Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

Table 35. Write State Machine Current/Next, sheet 2 of 2 Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection. Read Array Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Read Status Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Lock (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFIQuery Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog.

M36W832TE, M36W832BE

REVISION HISTORY

Table 36. Document Revision History Revision History moved to end of document. Flash and SRAM components updated. Table 2, Main Operation Modes, modified. Characteristicss Table and to CFI Tables 30 and 31. Security block removed. modified for Lock in Table 7, Flash Read Protection Register and Lock Register. 70ns Speed Class added. 100ns Speed Class removed.

M36W832TE, M36W832BE Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States