M36W432T STMICROELECTRONICS | Alldatasheet
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This is preliminary information on a new product now in development. Details are subject to change without notice.
32 Mbit (2Mb x16, Boot Block) Flash Memory
Figure 1. Packages
32 Mbit boot block Flash memory and a 4 Mbit
Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. LFBGA Connections (Top view through package) and the Write Enable signal (WS). eration of the Flash memory.
M36W432T, M36W432B Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL,t h e Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at V IH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 6, Read Protection Register and Protection Register Lock). Flash Reset (RPF ). The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked state. When Reset is at V IH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is re- quired to ensure valid data outputs. SRAM Chip Enable (E1S ,E 2 S ) .T h eC h i pE n - able inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH or E2S at VILdeselects the memory and reduces the power consumption to the standby level. E1Sand E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL.It is not allowed to set EFat VIL,E1S at VILand E2S at VIH at the same time. S R A MW r i t eE n a b l e( W S). The Write Enable in- put controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM memory. GS is ac- tive low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VDDF Supply Voltage (2.7V to 3.3V).VDDF pro- vides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQF and VDDS Supply Voltage (2.7V to 3.3V). VDDQF provides the power supply for the Flash memory I/O pins and VDDS provides the power supply for the SRAM control pins. This allows all Outputs to be powered independently from the Flash core power supply, V DDF .VDDQF c a nb et i e d to VDDS VPPF Program Supply Voltage.VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. The Supply Volt- age V DDF and the Program Supply Voltage VPPF can be applied in any order. If VPPF is kept in a low voltage range (0V to 3.6V) VPPF is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while VPPF >V PPLK en- ables these functions (see Table 14, DC Charac- teristics for the relevant values). V PPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. If V PPF is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is com- pleted (see Table 16 and 17). V SSF and VSSS Ground. VSSF and VSSS are the ground reference for all voltage measurements in the Flash and SRAM chips, respectively. Note: Each device in a system should have V DF,VDDQF and VPPF decoupled with a 0.1µF ca- pacitor close to the pin. See Figure 9, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the re- quired V PPF program and erase currents.
ory and, E1Sand E2S for the SRAM. Figure 4. Functional Block Diagram
32 Mbit (x16)
4 Mbit (x16)
Table 2. Main Operation Modes Note: X = VILor VIH,V PPFH =1 2 V±5 % .
- If UBSand LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBSand LBS separately.
M36W432T, M36W432B Flash Memory Component T h eF l a s hM e m o r yi sa3 2M b i t( 2M b i tx1 6 )d e - vice that can be erased electrically at the block level and programmed in-system on a Word-by- Word basis. These operations can be performed using a single low voltage (2.7 to 3.3V) supply and the V DDQF for device I/0 operation feature the same voltage range. An optional 12V VPPF power supply is provided to speed up customer pro- gramming. The device features an asymmetrical blocked ar- chitecture with an array of 71 blocks: 8 Parameter B l o c k so f4K W o r da n d6 3M a i nB l o c k so f3 2 KWord. The M36W432T device has the Flash Memory Parameter Blocks at the top of the mem- ory address space while the M36W432B device lo- cates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses. The Flash Memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any acciden- tal programming or erasure. There is an additional hardware protection against program and erase. When V PPF ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 128 bit Protection Register and a Security Block to increase the protection of a system design. The Protection Register is divid- ed into two 64 bit segments, the first one contains a unique device number written by ST, while the second one is one-time-programmable by the us- er. The user programmable segment can be per- manently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 6, shows the Flash Security Block Memory Map. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the tim- ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
Figure 5. Flash Block Addresses Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses. Figure 6. Flash Security Block Memory Map
4 KWords
32 KWords
4 KWord Blocks
32 KWord Blocks
M36W432T, M36W432B OPERATING MODES Flash Bus Operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby, Automatic Standby and Re- set. See Table 2, Main Operation Modes, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output En- a b l em u s tb ea tV ILin order to perform a read op- eration. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read de- pends on the previous command written to the memory (see Command Interface section). See Figure 9, Read Mode AC Waveforms, and Table 15, Flash Read AC Characteristics, for details of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write.Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V ILwith Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figures 10 and 11, Write AC Waveforms, and Tables 16 and 17, Flash Write AC Characteristics, for details of the timing requirements. Output Disable.The data outputs are high im- pedance when the Output Enable is at V IH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. The memory is in stand-by when Chip Enable is at V IH a n dt h ed e v i c ei si n read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V IH during a program or erase operation, the de- vice enters Standby mode when finished. Automatic Standby.Automatic Standby pro- vides a low power consumption state during Read mode. Following a read operation, the device en- ters Automatic Standby after 150ns of bus inactiv- ity even if Chip Enable is Low, V IL, and the supply current is reduced to IDD1 . The data Inputs/Out- puts will still output data if a bus Read operation is in progress. Reset. During Reset mode when Output Enable is Low, VIL, the memory is deselected and the out- puts are high impedance. The memory is in Reset mode when Reset is at V IL. The power consump- tion is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write En- able inputs. If Reset is pulled to V SSF during a Pro- gram or Erase, this operation is aborted and the memory content is no longer valid. Flash Command Interface All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. The Pro- gram/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Pro- gram/Erase states. See Appendix 29, Table 34, Write State Machine Current/Next, for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Re- set or whenever V DDF is lower than VLKO .C o m - mand sequences must be followed exactly. Any invalid combination of commands will reset the de- vice to Read mode. Refer to Table 3, Commands, in conjunction with the text descriptions below. Read Memory Array Command. The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command.The Status Register indicates when a program or erase oper- ation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register’s contents. Subsequent Bus Read operations read the Status Register at any address, until another command is issued. See Table 10, Status Register Bits, for de- tails on the definitions of the bits. The Read Status Register command may be is- sued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will automatically output the con- tent of the Status Register.
M36W432T, M36W432B Read Electronic Signature Command.The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or the Protec- tion and Lock Register. See Tables 4, 5 and 6 for the valid address. Read CFI Query Command. The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing pro- gramming equipment or applications to automati- cally match their interface to the characteristics of t h ed e v i c e .O n eB u sW r i t ec y c l ei sr e q u i r e dt oi s - sue the Read Query Command. Once the com- mand is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 28, 29, 30, 31, 32 and 33 for details on the information contained in the Common Flash Inter- face memory area. Block Erase Command. T h eB l o c kE r a s ec o m - m a n dc a nb eu s e dt oe r a s eab l o c k .I ts e t sa l lt h e bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. ■ The first bus cycle sets up the Erase command. ■ The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to V IL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will accept the Read Status Register command and the Pro- gram/Erase Suspend command, all other com- mands will be ignored. Typical Erase times are given in Table 7, Program, Erase Times and Pro- gram/Erase Endurance Cycles. See Appendix C, Figure 28, Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command. Program Command. The memory array can be programmed word-by-word. Two bus write cycles are required to issue the Program Command. ■ The first bus cycle sets up the Program command. ■ The second latches the Address and the Data to be written and starts the Program/Erase Controller. During Program operations the memory will ac- cept the Read Status Register command and the Program/Erase Suspend command. Typical Pro- gram times are given in Table 7, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. See Appendix C, Figure 25, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command. This feature is offered to improve the programming throughput, writing a page of two adjacent words in paral- lel.The two words must differ only for the address A0. Programming should not be attempted when V PPF is not at VPPH . The command can be execut- ed if VPPF is below VPPH but the result is not guar- anteed. Three bus write cycles are necessary to issue the Double Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and t h eD a t ao ft h ef i r s tw o r dt ob ew r i t t e n . ■ The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. Program- ming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 26, Double Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Double Word Program command. Clear Status Register Command.The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Sta- tus Register command. The bits in the Status Register do not automatical- ly return to ‘0’ when a new Program or Erase com- mand is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.
M36W432T, M36W432B Program/Erase Suspend Command. The Pro- gram/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command In- terface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electron- ic Signature and Read CFI Query commands. Ad- ditionally, if the suspend operation was Erase then the Program, Block Lock, Block Lock-Down or Protection Program commands will also be ac- cepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protec- tion Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 27, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 29, Erase Suspend & Resume Flowchart and Pseudo Code for flow- charts for using the Program/Erase Suspend com- mand. Program/Erase Resume Command. The Pro- gram/Erase Resume command can be used to re- start the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the com- mand. Once the command is issued subsequent Bus Read operations read the Status Register. See Appendix C, Figure 27, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 29, Erase Suspend & Resume Flowchart and Pseudo Code for flow- charts for using the Program/Erase Resume com- mand. Protection Register Program Command.The Protection Register Program command is used to Program the 64 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protec- tion Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Pro- tection Lock Register protects bit 2 of the Protec- tion Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block (see Figure 6, Flash Security Block Memory Map). Attempting to program a previously protected Protection Regis- ter will result in a Status Register error. The pro- tection of the Protection Register and/or the Security Block is not reversible. The Protection Register Program cannot be sus- pended. Block Lock Command. The Block Lock com- mand is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. ■ The first bus cycle sets up the Block Lock command. ■ The second Bus Write cycle latches the block address. The Lock Status can be monitored for each block using the Read Block Signature command. Table. 9 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they re- main set until reset or power-down/power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Unlock Command. The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Blocks Unlock command. ■ The first bus cycle sets up the Block Unlock command. ■ The second Bus Write cycle latches the block address. The Lock Status can be monitored for each block using the Read Block Signature command. Table. 9 shows the Lock Status after issuing a Block Un- lock command. Refer to the section, Block Lock- ing, for a detailed explanation.
locked by the Block Unlock command. using the Read Block Signature command. tion, Block Locking, for a detailed explanation. Table 3. Commands
- The signature addresses are listed in Tables 4, 5 and 6.
- Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.
Table 4. Read Electronic Signature Table 5. Read Block Signature Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0"; see Block Locking section. Table 6. Read Protection Register and Lock Register Lock VIL VIL VIH 80h Don't Care 0 OTP Prot.
Table 7. Program, Erase Times and Program/Erase Endurance Cycles scheme has three levels of protection. only control of block locking. 30, shows a flowchart for the locking operations. state when the device is reset or powered-down.
by a device reset or power-down. Locking Operations During Erase Suspend. is resumed, the erase operation will complete. mands are valid during erase suspend. Table 8. Block Lock Status Table 9. Lock Status in the Read Electronic Signature command with A1 = VIH a n dA 0=VIL.
- All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPFstatus.
- A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
M36W432T, M36W432B Flash Status Register The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, re- fer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V IH. Either Chip En- able or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 10, Status Register Bits. Refer to Table 10 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7).The Pro- gram/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Pro- gram/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High. During Program, Erase, operations the Program/ E r a s eC o n t r o l l e rS t a t u sb i tc a nb ep o l l e dt of i n dt h e end of the operation. Other bits in the Status Reg- ister should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, V PPF Status and Block Lock Status bits should be tested for errors. Erase Suspend Status (Bit 6).The Erase Sus- pend Status bit indicates that an Erase operation has been suspended or is going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Pro- gram/Erase Resume command. The Erase Suspend Status should only be consid- ered valid when the Program/Erase Controller Sta- tus bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of the Program/Erase Sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status (Bit 5).The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/ Erase Controller has applied the maximum num- ber of pulses to the block and still failed to verify that the block has erased correctly. The Erase Sta- tus bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4).The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to ‘1’), the Pro- gram/Erase Controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. V PPF Status (Bit 3).The VPPF Status bit can be used to identify an invalid voltage on the VPPF pin during Program and Erase operations. The VPPF pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can oc- cur if V PPF becomes invalid during an operation. When the VPPF Status bit is Low (set to ‘0’), the v o l t a g eo nt h eVPPF pin was sampled at a valid voltage; when the VPPF Status bit is High (set to ‘1’), the VPPF pin has a voltage that is below the VPPF Lockout Voltage, VPPLK , the memory is pro- tected and Program and Erase operations cannot be performed. Once set High, the V PPF Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail.
operation rather than entering the Suspend mode. sued the Program Suspend Status bit returns Low. t e m p t e do nal o c k e db l o c k . the new command will appear to fail. reserved. Its value must be masked. Pseudo Codes, for using the Status Register. Table 10. Status Register Bits Note: Logic level '1' is High, '0' is Low.
6 Erase Suspend Status
5 Erase Status
4 Program Status
3 VPPF Status
2 Program Suspend Status
1 Block Protection Status
0 Reserved
dress transitions for subsequent write cycles. or the falling edge of WS, whichever occurs last. E2S, whichever occurs first. with Write Enable, WS,a tVIH. Table 11. Absolute Maximum Ratings
Table 14. DC Characteristics
Figure 9. Flash Read AC Waveforms Table 15. Flash Read AC Characteristics
M36W432T, M36W432B Note: 1. Sampled only, not 100% tested. 2. GF may be delayed by up to tELQV -tGLQV after the falling edge of EFwithout increasing tELQV . tGLQX (1) tOLZ Output Enable Low to Output Transition Min 0 0 ns Symbol Alt Parameter Flash Unit 70 85
Figure 10. Flash Write AC Waveforms, Write Enable Controlled
Table 16. Flash Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.
- Applicable if VPPF is seen as a logic input (VPPF <3 . 6 V ) .
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled
Table 17. Flash Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.
- Applicable if VPPF is seen as a logic input (VPPF <3 . 6 V ) .
Figure 12. Flash Power-Up and Reset AC Waveforms Table 18. Flash Power-Up and Reset AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.
- Sampled only, not 100% tested.
- It is important to assert RPF
in order to allow proper CPU initialization during power up or reset.
Figure 15. SRAM Standby AC Waveforms Table 19. SRAM Read AC Characteristics Note: 1. Sampled only. Not 100% tested.
Table 20. SRAM Write AC Characteristics Note: 1. tAS is measured from the address valid to the beginning of write.
- tWR is measured from the end or write to the address change. tWR a p p l i e di nc a s eaw r i t ee n d sa sE 1 Sor WS going high.
- tCW is measured from E1Sgoing low end of write.
- A Write occurs during the overlap (tWP )o fl o wE 1 Sand low WS. A write begins when E1Sgoes low and WSgoes low with asserting
liest transition when E1Sgoes high and WSgoes high. The tWP is measured from the beginning of write to the end of write.
Figure 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data
Figure 23. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)
Figure 24. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)
Table 23. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. Table 24. Daisy Chain Ordering Scheme vice, please contact the STMicroelectronics Sales Office nearest to you.
M36W432T, M36W432B
REVISION HISTORY
Table 25. Document Revision History
Table 26. Top Boot Block Addresses,
Table 27. Bottom Boot Block Addresses,
command to return to Read mode. Table 28. Query Structure Overview Note: Query data are always presented on the lowest order data outputs. Table 29. CFI Query Identification String Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Table 30. CFI Query System Interface Information
Table 31. Device Geometry Definition Number of Erase Block Regions within the device. Erase Blocks of the same size.
Table 32. Primary Algorithm-Specific Extended Query Table Note: 1. See Table 29, offset 15 for P pointer definition. contains less significant byte. (P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space. Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable.
Table 33. Security Code Area
Figure 25. Program Flowchart and Pseudo Code
- If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Figure 26. Double Word Program Flowchart and Pseudo Code
- If an error is found, the Status Register must be cleared before further Program/Erase operations.
- Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
Figure 27. Program Suspend & Resume Flowchart and Pseudo Code
Figure 28. Erase Flowchart and Pseudo Code Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code
Figure 30. Locking Operations Flowchart and Pseudo Code
Table 34. Write State Machine Current/Next, sheet 1 of 2 Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
Table 35. Write State Machine Current/Next, sheet 2 of 2 Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection. Read Array Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Read Status Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Lock (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFIQuery Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog.
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