M36W416TGZA

M36W416TG STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 62

Technical content

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

16 Mbit (1Mb x16, Boot Block) Flash Memory

Figure 1. Packages

memory to be active at the same time. and is supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. LFBGA Connections (Top view through package)

M36W416TG, M36W416BG SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17).Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they con- trol the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable ( EF) and Write Enable (WF) signals, while the SRAM is accessed through two Chip Enable (ES) and Write Enable (W S ) signals. Address Inputs (A18-A19).Addresses A18-A19 are inputs for the Flash component only. The Flash memory is accessed through the Chip En- able ( EF) and Write Enable (WF) signals Data Inputs/Outputs (DQ0-DQ15). The Data I/ O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Write Bus operation. Flash Chip Enable ( EF). The Chip Enable input activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V IL and Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the standby level. Flash Output Enable (G F). The Output Enable controls the data outputs during the Bus Read op- eration of the Flash memory. Flash Write Enable (W F). The Write Enable con- trols the Bus Write operation of the Flash memo- ry’s Command Interface. The data and address inputs are latched on the rising edge of Chip En- able, EF, or Write Enable, WF, whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at V IH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 6, Read Protection Register and Protection Register Lock). Flash Reset (RP F). The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked state. When Reset is at V IH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is re- quired to ensure valid data outputs. SRAM Chip Enable (E1 S, E2S). The Chip En- able inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S or E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL and, E1S at VIL or E2S at VIL at the same time. SRAM Write Enable (WS ). The Write Enable in- put controls writing to the SRAM memory array. W S is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM memory. GS is ac- tive low. SRAM Upper Byte Enable (UBS ). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UB S is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LB S is active low. VDDF and VDDS Supply Voltages. VDDF pro- vides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQF and VDDS Supply Voltage (2.7V to 3.3V). VDDQF provides the power supply for the Flash memory I/O pins and VDDS provides the power supply for the SRAM control pins. This allows all Outputs to be powered independently of the Flash core power supply, V DDF . VDDQF can be tied to VDDS. VPPF Program Supply Voltage. VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. The Supply Volt- age V DDF and the Program Supply Voltage VPPF can be applied in any order. If VPPF is kept in a low voltage range (0V to 3.6V) VPPF is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while VPPF > VPP1 en- ables these functions (see Table 6, DC Character- istics for the relevant values). V PPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. If V PPF is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is com- pleted (see Table 19 and 20).

the Flash and SRAM chips, respectively. PPF program and erase currents. ory and E1S and E2S for the SRAM. Figure 4. Functional Block Diagram

16 Mbit (x16)

4 Mbit (x16)

Table 2. Main Operation Modes Note: X = Don’t care = VIL or VIH, VPPFH = 12V ± 5%.

Table 3. Absolute Maximum Ratings

Table 6. DC Characteristics

M36W416TG, M36W416BG IPPE Program Current (Erase) Flash VPPF = 12V ± 0.5V Erase in progress 10 mA VPPF = VDDF Erase in progress 5µ A VIL Input Low Voltage Flash & SRAM VDDQF = VDDS ≥ 2.7V –0.3 0.8 V VIH Input High Voltage Flash & SRAM VDDQF = VDDS ≥ 2.7V 0.7 VDDQF VDDQF +0.3 V VOL Output Low Voltage Flash & SRAM VDDQF = VDDS = VDD min IOL = 100µA 0.1 V VOH Output High Voltage Flash & SRAM VDDQF = VDDS = VDD min IOH = –100µA VDDQ –0.1 V VPP1 Program Voltage (Program or Erase operations) Flash 1.65 3.6 V VPPFH Program Voltage (Program or Erase operations) Flash 11.4 12.6 V VPPLK Program Voltage (Program and Erase lock- out) Flash 1 V V LKO VDDF Supply Voltage (Program and Erase lock- out) Flash 2 V Symbol Parameter Device Test Condition Min Typ Max Unit

Figure 7. Stacked LFBGA66-12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 7. Stacked LFBGA66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, Package Mechanical Data

Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)

Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)

Table 8. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. Table 9. Daisy Chain Ordering Scheme please contact the STMicroelectronics Sales Office nearest to you.

M36W416TG, M36W416BG FLASH DEVICE The M36W416TG contains one 16 Mbit Flash memory. This section describes how to use the Flash device and all signals refer to the Flash de- vice. FLASH SUMMARY DESCRIPTION The Flash Memory is a 16 Mbit (1 Mbit x 16) non- volatile device that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. V DDQF is used to drive the I/O pin down to 1.65V. An optional 12V VPPF power supply is pro- vided to speed up customer programming. The device features an asymmetrical blocked ar- chitecture with an array of 39 blocks: 8 Parameter Blocks of 4 KWords and 31 Main Blocks of 32 KWords. The M36W416TG has the Parameter Blocks at the top of the memory address space while the M36W416BG locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 10, Block Addresses. The Flash Memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any acciden- tal programming or erasure. There is an additional hardware protection against program and erase. When V PPF ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 128 bit Protection Register and a Security Block to increase the protection of a system design. The Protection Register is divid- ed into two 64 bit segments, the first one contains a unique device number written by ST, while the second one is one-time-programmable by the us- er. The user programmable segment can be per- manently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 11, shows the Flash Security Block Memory Map. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the tim- ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Figure 10. Flash Block Addresses Note: Also see Appendix A, Tables 25 and 26 for a full listing of the Flash Block Addresses. Figure 11. Flash Security Block and Protection Register Memory Map

4 KWords

32 KWords

4 KWord Blocks

32 KWord Blocks

M36W416TG, M36W416BG FLASH BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby, Automatic Standby and Re- set. See Table 2, Main Operation Modes, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output En- able must be at V IL in order to perform a read op- eration. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read de- pends on the previous command written to the memory (see Command Interface section). See Figure 12, Flash Read Mode AC Waveforms, and Table 18, Flash Read AC Characteristics, for de- tails of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write.Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V IL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figures 13 and 14, Flash Write AC Wave- forms, and Tables 19 and 20, Flash Write AC Characteristics, for details of the timing require- ments. Output Disable. The data outputs are high im- pedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. The memory is in stand-by when Chip Enable is at V IH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V IH during a program or erase operation, the de- vice enters Standby mode when finished. Automatic Standby.Automatic Standby pro- vides a low power consumption state during Read mode. Following a read operation, the device en- ters Automatic Standby after 150ns of bus inactiv- ity even if Chip Enable is Low, V IL, and the supply current is reduced to IDD1 . The data Inputs/Out- puts will still output data if a bus Read operation is in progress. Reset. During Reset mode when Output Enable is Low, VIL, the memory is deselected and the out- puts are high impedance. The memory is in Reset mode when Reset is at VIL. The power consump- tion is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write En- able inputs. If Reset is pulled to V SS during a Pro- gram or Erase, this operation is aborted and the memory content is no longer valid.

M36W416TG, M36W416BG FLASH COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. The Pro- gram/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Pro- gram/Erase states. See Appendix 29, Table 33, Write State Machine Current/Next, for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Re- set or whenever V DD is lower than VLKO . Com- mand sequences must be followed exactly. Any invalid combination of commands will reset the de- vice to Read mode. Refer to Table 10, Com- mands, in conjunction with the text descriptions below. Read Memory Array Command The Read command returns the memory to its Read mode. One Bus Write cycle is required to is- sue the Read Memory Array command and return the memory to Read mode. Subsequent read op- erations will read the addressed location and out- put the data. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register’s contents. Subsequent Bus Read operations read the Status Register at any address, until another command is issued. See Table 17, Status Register Bits, for details on the definitions of the bits. The Read Status Register command may be is- sued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will automatically output the con- tent of the Status Register. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or the Protec- tion and Lock Register. See Tables 11, 12 and 13 for the valid address. Read CFI Query Command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or appli- cations to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Com- mand. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 27, 28, 29, 30, 31 and 32 for details on the information contained in the Common Flash Interface memory area. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. I The first bus cycle sets up the Erase command. I The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to V IL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will accept the Read Status Register command and the Pro- gram/Erase Suspend command, all other com- mands will be ignored. Typical Erase times are given in Table 14, Program, Erase Times and Pro- gram/Erase Endurance Cycles. See Appendix C, Figure 28, Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command. Program Command The memory array can be programmed word-by- word. Two bus write cycles are required to issue the Program Command. I The first bus cycle sets up the Program command. I The second latches the Address and the Data to be written and starts the Program/Erase Controller. During Program operations the memory will ac- cept the Read Status Register command and the Program/Erase Suspend command. Typical Pro- gram times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program

M36W416TG, M36W416BG operation is aborted, the block containing the memory location must be erased and repro- grammed. See Appendix C, Figure 25, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempt- ed when V PP is not at VPPFH . The command can be executed if VPP is below VPPFH but the result is not guaranteed. Three bus write cycles are necessary to issue the Double Word Program command. I The first bus cycle sets up the Double Word Program Command. I The second bus cycle latches the Address and the Data of the first word to be written. I The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. Program- ming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 26, Double Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Double Word Program command. Clear Status Register Command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatical- ly return to ‘0’ when a new Program or Erase com- mand is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase control- ler. During Program/Erase Suspend the Command In- terface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electron- ic Signature and Read CFI Query commands. Ad- ditionally, if the suspend operation was Erase then the Program, Block Lock, Block Lock-Down or Protection Program commands will also be ac- cepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protec- tion Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 27, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 29, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subse- quent Bus Read operations read the Status Reg- ister. See Appendix C, Figure 27, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 29, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 64 bit user One-Time-Pro- grammable (OTP) segment of the Protection Reg- ister. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protec- tion Register Program command. I The first bus cycle sets up the Protection Register Program command. I The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Pro- tection Lock Register protects bit 2 of the Protec- tion Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block (see Figure 11, Flash Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection

M36W416TG, M36W416BG Register and/or the Security Block is not revers- ible. The Protection Register Program cannot be sus- pended. See Appendix C, Figure 31, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the Protection Register Program command. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. I The first bus cycle sets up the Block Lock command. I The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 16 shows the protection status after issuing a Block Lock command. The Block Lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Unlock Command The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to is- sue the Blocks Unlock command. I The first bus cycle sets up the Block Unlock command. I The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 16 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Lock-Down Command A locked block cannot be Programmed or Erased, or have its protection status changed when WP F is low, VIL. When WP F is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock com- mand. Two Bus Write cycles are required to issue the Block Lock-Down command. I The first bus cycle sets up the Block Lock command. I The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 16 shows the protection sta- tus after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation.

Table 10. Flash Commands

1. The signature addresses are listed in Tables 11, 12 and 13.
2. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 11. Read Electronic Signature

Table 12. Read Block Lock Signature Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section. Table 13. Read Protection Register and Lock Register Table 14. Program, Erase Times and Program/Erase Endurance Cycles Lock VIL VIL VIH 80h Don’t Care 0 OTP Prot.

M36W416TG, M36W416BG FLASH BLOCK LOCKING The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. I Lock/Unlock - this first level allows software- only control of block locking. I Lock-Down - this second level requires hardware interaction before locking can be changed. I VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The lock status of each block can be set to Locked, Unlocked, and Lock-Down. Table 16, de- fines all of the possible protection states (WP DQ1, DQ0), and Appendix C, Figure 30, shows a flowchart for the locking operations. Reading a Block’s Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subse- quent reads at the address specified in Table 12, will output the lock status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indi- cates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when enter- ing Lock-Down. DQ1 indicates the Lock-Down sta- tus and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or af- ter a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase oper- ations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software com- mands. An Unlocked block can be Locked by issu- ing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be un- locked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their lock status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP F input pin. When WPF=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from pro- gram, erase and protection status changes. When WP F=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individu- ally unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while WP F remains high. When WPF is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WPF was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase opera- tion, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the protection status will be changed. After completing any desired lock, read, or program op- erations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D, Com- mand Interface and Program/Erase Controller State, for detailed information on which com- mands are valid during erase suspend.

Table 15. Block Lock Status Table 16. Protection Status as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.
2. A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

M36W416TG, M36W416BG FLASH STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, re- fer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V IH. Either Chip En- able or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 17, Status Register Bits. Refer to Table 17 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7).The Pro- gram/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Pro- gram/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High . During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Reg- ister should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, V PP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status (Bit 6).The Erase Sus- pend Status bit indicates that an Erase operation has been suspended or is going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Pro- gram/Erase Resume command. The Erase Suspend Status should only be consid- ered valid when the Program/Erase Controller Sta- tus bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of the Program/Erase Sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status (Bit 5).The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/ Erase Controller has applied the maximum num- ber of pulses to the block and still failed to verify that the block has erased correctly. The Erase Sta- tus bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4).The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to ‘1’), the Pro- gram/Erase Controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. V PP Status (Bit 3).The V PP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can oc- cur if V PP becomes invalid during an operation. When the VPP Status bit is Low (set to ‘0’), the volt- age on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK , the memory is protected and Pro- gram and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2).The Program Suspend Status bit indicates that a Program oper- ation has been suspended. When the Program Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Re- sume command. The Program Suspend Status should only be considered valid when the Pro-

operation rather than entering the Suspend mode. sued the Program Suspend Status bit returns Low. the new command will appear to fail. reserved. Its value must be masked. Pseudo Codes, for using the Status Register. Table 17. Status Register Bits Note: Logic level ’1’ is High, ’0’ is Low.

6 Erase Suspend Status

5 Erase Status

4 Program Status

3 VPP Status

2 Program Suspend Status

1 Block Protection Status

0 Reserved

Figure 12. Flash Read Mode AC Waveforms Table 18. Flash Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. GF may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV .

Figure 13. Flash Write AC Waveforms, Write Enable Controlled

Table 19. Flash Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

1. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).

Figure 14. Flash Write AC Waveforms, Chip Enable Controlled

Table 20. Flash Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.

1. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).

Figure 15. Flash Power-Up and Reset AC Waveforms Table 21. Flash Power-Up and Reset AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.

1. Sampled only, not 100% tested.
2. It is important to assert RPF in order to allow proper CPU initialization during power up or reset.

same as the Flash component’s voltage supply. Figure 16. SRAM Logic Diagram

M36W416TG, M36W416BG SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable, W S, is at VIH, Out- put Enable, GS, is at VIL, Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at VIH, and one or both of the Byte Enable inputs, UBS and LBS is/are at VIL. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (t E1LQV , tE2HQV , or tGLQV ) rath- er than the address. Data out may be indetermi- nate at t E1LQX , tE2HQX and tGLQX , but data lines will always be valid at tAVQV (see Table 22, Figures 17 and 18). Write.Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever W S and E1S are at VIL, and E2S is at VIH. Either the Chip Enable inputs, E1S and E2S , or the Write Enable input, WS, must be deasserted during ad- dress transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2S is at VIH and WS is at VIL. The data is latched on the falling edge of E1S, the rising edge of E2S or the falling edge of WS, whichever occurs last. The Write cycle is terminated on the rising edge of E1S, the rising edge of WS or the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S =V IL, E2S=V IH and G S=V IL), then WS will return the outputs to high im- pedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of op- eration. The Data input must be valid for t DVWH be- fore the rising edge of Write Enable, for tDVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S , whichever occurs first, and remain valid for tWHDX , tE1HAX or tE2LAX (see Table 23, Figures 20, 21, 22 and 23). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which in- vokes an automatic standby mode (see Table 22, Figure 19). The SRAM is in Standby mode when- ever either Chip Enable is deasserted, E1 S at VIH or E2S at VIL. It is also possible when UBS and LBS are at VIH. Data Retention.The SRAM data retention per- formance as VDDS goes down to VDR are de- scribed in Table 24 and Figure 24. In E1S controlled data retention mode, the minimum standby current mode is entered when E1S ≥ VDDS – 0.2V and E2 S ≤ 0.2V or E2S ≥ VDDS – 0.2V. In E2S controlled data reten- tion mode, minimum standby current mode is en- tered when E2S ≤ 0.2V. Output Disable.The data outputs are high im- pedance when the Output Enable, GS, is at VIH with Write Enable, WS, at VIH.

Table 22. SRAM Read AC Characteristics Note: 1. Sampled only. Not 100% tested.

Figure 20. SRAM Write AC Waveforms, WS Controlled impedance). If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

1. The I/O pins are in output mode and input signals must not be applied.

Figure 21. SRAM Write AC Waveforms, E1S Controlled impedance). If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
2. The I/O pins are in output mode and input signals must not be applied.

Table 23. SRAM Write AC Characteristics

Figure 24. SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled Table 24. SRAM Low VDDS Data Retention Characteristic Note: 1. All other Inputs VIH ≤ VDDS –0.2V or VIL≤ 0.2V.

1. Sampled only. Not 100% tested.

Table 25. Top Boot Block Addresses, Table 26. Bottom Boot Block Addresses,

command to return to Read mode. Table 27. Query Structure Overview Note: Query data are always presented on the lowest order data outputs. Table 28. CFI Query Identification String Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 29. CFI Query System Interface Information

Table 30. Device Geometry Definition Number of Erase Block Regions within the device. Erase Blocks of the same size.

Table 31. Primary Algorithm-Specific Extended Query Table Note: 1. See Table 28, offset 15 for P pointer definition. contains less significant byte. (P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space. Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable.

Table 32. Security Code Area

Figure 25. Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Figure 26. Double Word Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

Figure 27. Program Suspend & Resume Flowchart and Pseudo Code

Figure 28. Erase Flowchart and Pseudo Code Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code

Figure 30. Locking Operations Flowchart and Pseudo Code

Figure 31. Protection Register Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Table 33. Write State Machine Current/Next, sheet 1 of 2. Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

Table 34. Write State Machine Current/Next, sheet 2 of 2. Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection. Read Array Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Read Status Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. Lock (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFIQuery Lock Setup Prot. Prog. (complete) Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog.

M36W416TG, M36W416BG

REVISION HISTORY

Table 35. Document Revision History

M36W416TG, M36W416BG Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.