M36W108T STMICROELECTRONICS | Alldatasheet
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Technical content
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8 Mbit (1Mb x8, Boot Block) Flash Memory and
1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product
Figure 1. Logic Diagram
M36W108T, M36W108B
DESCRIPTION
The M36W108 is multi-chip device containing an
8 Mbit boot block Flash memory and a 1 Mbit of
SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.0 mm ball pitch and LGA48 1.0 mm land pitch. The two components, of the package's overall 9 Mbit of memory, are distinguishable by use of the three chip enable lines: EF for the Flash memory, E1S and E2S for the SRAM. The Flash memory component is identical with the M29W008 device. It is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte ba- sis using only a single 2.7V to 3.6V V CCF supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard program- mers. The array matrix organization allows each block to be erased and reprogrammed without af- fecting other blocks. Instructions for Read/Reset, Auto Select for read- ing the Electronic Signature, Programming, Block Figure 2. LBGA and LGA Connections (Top View) Table 1. Signal Names
and E2S at VIH at the same time. E1S at VIL and E2S at VIH at the same time. chip and Address/Data latches. Table 2. Absolute Maximum Ratings (1)
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
ply for all operations (Read, Program and Erase). all operations (Read, Program). currents and the VCCF erase current required. Table 3. Main Operation Modes (1)
Figure 3. Internal Functional Arrangement
8 Mbit
1 Mbit SRAM
A0-A19 and the Data Input/Outputs DQ0-DQ7. Output Enable (G) and Write Enable (W) inputs. an internal Program/Erase Controller (P/E.C.). sion locates the Boot Block starting at the bottom. tions are managed automatically by the P/E.C. ing erased, and then resumed. Table 4. Top Boot Block, Flash Block Address
16 FC000h-FFFFFh
8 FA000h-FBFFFh
8 F8000h-F9FFFh
32 F0000h-F7FFFh
64 E0000h-EFFFFh
64 D0000h-DFFFFh
64 C0000h-CFFFFh
64 B0000h-BFFFFh
64 A0000h-AFFFFh
Table 5. Bottom Boot Block, Flash Block
64 F0000h-FFFFFh
able (W) is at VIL with Output Enable (G) at VIH. standby value, while outputs still drive the bus. through a Command Interface (C.I.). The C.I. latches commands written to the memory. address 2AAAh during the second cycle. Table 6. Flash User Bus Operations Table 7. Read Flash Electronic Signature
Command sequencing must be followed exactly. with A1 at VIL. Other address inputs are ignored. toggle at the address being programmed. Table 8. Flash Commands
M36W108T, M36W108B Block Erase (BE) Instruction.This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded Cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Cod- ed cycles. The erase will start after the erase tim- eout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for oth- er blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the block(s). If the second command given is not an erase con- firm or if the Coded cycles are wrong, the instruc- tion aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before to erasing to FFh. Read operations after the sixth ris- ing edge of W or EF output the Status Register bits. During the execution of the erase by the P/E.C., the memory only accepts the Erase Suspend (ES) and Read/Reset (RD) instructions. A Read/Reset command will definitively abort erasure and result in invalid data in blocks being erased. A complete state of the block erase operation is given by the Status Register bits (see DQ2, DQ3, DQ5, DQ6 and DQ7 description). Chip Erase (CE) Instruction.This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on the third cycle after the two Coded Cycles. The Chip Erase Con- firm command 10h is similarly written on the sixth cycle after another two Coded Cycles. If the sec- ond command given is not an erase confirm or if the Coded Sequence is wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits. A complete state of the chip erase operation is given by the Status Register bits (see DQ2, DQ3, DQ5, DQ6 and DQ7 description). Erase Suspend (ES) Instruction.The Block Erase operation may be suspended by this in- struction which consists of writing the command B0h without any specific address. No Coded Cy- cles are required. It permits reading of data from another block and programming in another block while an erase operation is in progress. Erase sus- pend is accepted only during the Block Erase in- struction execution. Writing this command during the erase timeout period will, in addition to sus- pending the erase, terminate the timeout. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended. The Toggle bits will stop toggling be- tween 0.1µs and 15µs after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume (ER) and the Program (PG) instructions. A Program opera- tion can be initiated during Erase Suspend in one of the blocks not being erased. It will result in both DQ2 and DQ6 toggling when the data is being pro- grammed. A Read/Reset command will definitively abort erasure and result in invalid data in the blocks being erased. Erase Resume (ER) Instruction.If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles.
Table 9. Flash Instructions (1) Note: 1. Commands not interpreted in this table will default to read array mode.
- A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase, Erase Suspend or Program mode before
starting any new operation (see Table 14 and Figure 7).
- The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
- Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device
- Block Protection Address: A0, at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status.
- For Coded cycles address inputs A15-A19 are don’t care.
- Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be
until Erase is completed or suspended.
- Read Data Polling, Toggle bits or RB until Erase completes.
- During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
Read Memory Array until a new write cycle is initiated.
Table 10. Flash Status Register Bits (1) Note: 1.Logic level ‘1’ is High, ‘0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
7 Data
6 T oggle Bit
5 Error Bit
4 Reserved
3 Erase
can be entered to the P/E.C.
2 T oggle Bit
1 Reserved
0 Reserved
DQ2, or Error on DQ5 and Erase Timer DQ3 bits. plement of the bit being programmed on DQ7. or G toggling will cause DQ6 to toggle. 15 for Toggle Bit waveforms. Error Bit (DQ5).This bit is set to '1' by the P/E.C. of Program or Erase, the error bit will be set to '0'. Table 11. Flash Polling and Toggle Bits Note: 1. Toggle if the address is within a block being erased. ‘1’ if the address is within a block not being erased.
Table 12. Flash Program/Erase Times and Endurance
ray, Output Disable, Power Down (see Table 13). the falling edge of E2S, whichever occurs first. Table 13. SRAM User Bus Operations (1)
Table 17. Flash Read AC Characteristics Note: 1. Sampled only, not 100% tested.
- G may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV .
- To be considered only if the Reset pulse is given while the memory is in Erase, Erase Suspend or Program Mode.
- See Flash-SRAM Switching Waveforms.
Figure 6. Flash Read Mode AC Waveforms Note: Write Enable (W) = High.
Table 18. Flash Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
Figure 7. Flash Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
Table 19. Flash Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
Table 20. Flash Data Polling and Toggle Bits AC Characteristics (1) Note: 1. All other timings are defined in Read AC Characteristics table.
Figure 10. Flash Data Polling DQ7 AC Waveforms
Figure 11. Flash Data Toggle DQ6, DQ2 AC Waveforms Note: All other timings are as a normal Read cycle.
Table 21. SRAM Read AC Characteristics Note: 1. Sampled only. Not 100% tested.
- See Flash-SRAM Switching Waveforms.
Figure 14. SRAM Read Mode AC Waveforms, Address Controlled Note: E1S = Low, E2S = High, G = Low, W = High.
Table 22. SRAM Write AC Characteristics Figure 17. SRAM Write AC Waveforms, W Controlled Note: Output Enable (G) = Low.
Table 23. SRAM Low VCC Data Retention Characteristics (1, 2) Note: 1. All other Inputs VIH ≤ VCC – 0.2V or VIL ≤ 0.2V.
- Sampled only. Not 100% tested.
Figure 20. SRAM Low VCC Data Retention AC Waveforms, E1S Controlled
Table 24. Ordering Information Scheme vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 25. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data Figure 23. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline
Table 26. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data Figure 24. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline
M36W108T, M36W108B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com