M36W0R6040T1 NUMONYX | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 22
Technical content
Datasheet sections
- 1 Description
- 2 Signal descriptions
- 2.1 Address Inputs (A0-A19)
- 2.2 Address Inputs (A20-A21)
- 2.3 Data Input/Output (DQ0-DQ15)
- 2.4 Flash Chip Enable (E
- 2.5 Flash Output Enable (G F)
- 2.6 Flash Write Enable (W F)
- 2.7 Flash Write Protect (WP F)
- 2.8 Flash Reset (RP F)
- 2.9 Flash Latch Enable (L F
- 2.10 Flash Clock (K F)
- 2.11 Flash Wait (WAIT F)
- 2.12 PSRAM Chip Enable (E1 P
- 2.13 PSRAM Chip Enable (E2 P)
- 2.14 PSRAM Output Enable (G P)
- 2.15 PSRAM Write Enable (W P)
- 2.16 PSRAM Upper Byte Enable (UB P)
- 2.17 PSRAM Lower Byte Enable (LB P)
- 2.18 V DDF supply voltage
- 2.19 V DDP supply voltage
- 2.20 V DDQ supply voltage
- 2.21 V PPF program supply voltage
- 2.22 V SS ground
- 3 Functional description
- 4 Maximum rating
- 5 DC and AC parameters
Features
■ Multi-chip package – 1 die of 64 Mbit (4 Mb x 16) Flash memory – 1 die of 16 Mbit (1 Mb x 16) Pseudo SRAM ■ Supply voltage DDF = VDDP = VDDQ = 1.7 V to 1.95 V ■ Low power consumption ■ Electronic signature – Manufacturer Code: 20h – Device Code (top flash configuration), M36W0R6040T1: 8810h – Device Code (bottom flash configuration), M36W0R604BT1: 8811h ■ ECOPACK® packages available Flash memory ■ Programming time – 8 µs by Word typical for Fast Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options ■ Memory blocks – Multiple Bank Memory Array: 4 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 66 MHz – Asynchronous/ Synchronous Page Read mode – Random Access: 70 ns ■ Dual operations – Program Erase in one Bank while Read in others – No delay between Read and Write operations ■ Block locking – All blocks locked at Power-up – Any combination of blocks can be locked –W P F for Block Lock-Down ■ Security – 128-bit user programmable OTP cells – 64-bit unique device number ■ Common Flash Interface (CFI) ■ 100 000 program/erase cycles per block PSRAM ■ Access time: 70 ns ■ Low standby current: 110 µA ■ Deep power down current: 10 µA FBGA Stacked TFBGA88 (ZAQ) 8 × 10 mm www.numonyx.com
M36W0R6040T1, M36W0R604BT1 Contents
Table 6. Stacked TFBGA88 8 × 10 mm - 8 × 10 ball array, 0.8 mm pitch, package
Description M36W0R6040T1, M36W0R604BT1
1 Description
The M36W0R6040T1 and M36W0R604BT1 combine two memory devices in a multi-chip package:
- a 64-Mbit, Multiple Bank Flash memories, the M58WR064HT/B
- a 16-Mbit Pseudo SRAM, the M69AR024B. Recommended operating conditions do not allow more than one memory to be active at the same time. The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58WR064HTB and M69AR024B datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. The memory is offered in a Stacked TFBGA88 (8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch) package. In order to meet environmental requirements, Numonyx offers the M36W0R6040T1 and M36W0R604BT1 in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. The memory is supplied with all the bits erased (set to ‘1’).
Figure 1. Logic diagram
Table 1. Signal names
Figure 2. TFBGA connections (top view through package)
Signal descriptions M36W0R6040T1, M36W0R604BT1
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device.
2.1 Address Inputs (A0-A19)
Addresses A0-A19 are common inputs for the Flash Memory and PSRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller, and they select the cells to access in the PSRAM. The Flash memory is accessed through the Chip Enable signal ( EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP).
2.2 Address Inputs (A20-A21)
Addresses A20-A21 are inputs for the Flash memory component only. The Flash memory is accessed through the Chip Enable signals ( EF) and through the Write Enable (WF) signal.
2.3 Data Input/Output (DQ0-DQ15)
For the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB P) is driven Low. Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low.
2.4 Flash Chip Enable (E F)
The Chip Enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V IL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.5 Flash Output Enable (G F)
The Output Enable pins control data outputs during Flash memory Bus Read operations.
M36W0R6040T1, M36W0R604BT1 Signal descriptions
2.6 Flash Write Enable (W F)
The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.7 Flash Write Protect (WP F)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, V IL, Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR064HT/B datasheet).
2.8 Flash Reset (RP F)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2. Refer to the M58WR064HT/B datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to the M58WR064HT/B datasheet).
2.9 Flash Latch Enable (L F
Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, V IL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.10 Flash Clock (K F)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is don't care during Asynchronous Read and in write operations.
2.11 Flash Wait (WAIT F)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at V IH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable.
Signal descriptions M36W0R6040T1, M36W0R604BT1
2.12 PSRAM Chip Enable (E1 P
When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de- asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode.
2.13 PSRAM Chip Enable (E2 P)
The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode.
2.14 PSRAM Output Enable (G P)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus.
2.15 PSRAM Write Enable (W P)
The Write Enable, WP, controls the Bus Write operation of the memory.
2.16 PSRAM Upper Byte Enable (UB P)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8- DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.17 PSRAM Lower Byte Enable (LB P)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0- DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.18 V DDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supplies for all Flash memory operations (Read, Program and Erase).
2.19 V DDP supply voltage
The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed.
M36W0R6040T1, M36W0R604BT1 Signal descriptions
2.20 V DDQ supply voltage
VDDQ provides the power supply for the Flash Memory and PSRAM I/O pins. This allows all Outputs to be powered independently of the Flash Memory and PSRAM core power supplies: V DDF and VDDP, respectively.
2.21 V PPF program supply voltage
VPPF is both a Flash Memory control input and a Flash Memory power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1F enables these functions (see the M58WR064HT/B datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If V PPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.22 V SS ground
VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. Note: Each Flash memory device in a sys tem should have its supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
3 Functional description
memory and E1P and E2P for the PSRAM. the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram
16 Mbit
64 Mbit
Table 2. Main operating modes (1)
- WAIT signal polarity is configured using the Set Configur ation Register command. Refer to M58WR064HT/B datasheet for
- L F can be tied to VIH if the valid address has been previously latched.
4 Maximum rating
and other relevant quality documents. Table 3. Absolute maximum ratings
5 DC and AC parameters
Figure 4. AC measurement I/O waveform Table 4. Operating and AC measurement conditions
Figure 5. AC measurement load circuit characteristics values and illustrations. Table 5. Device capacitance (1)
- Sampled only, not 100% tested.
6 Package mechanical
Figure 6. Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,
7 Part numbering
device, please contact the Numonyx Sales Office nearest to you. Table 7. Ordering information scheme
8 Revision history
Table 8. Document revision history 08-June-2005 0.1 First Issue. Package is ECOPACK® compliant. and M69AR024B datasheets. Small text changes. 14-Nov-2007 0.3 Applied Numonyx branding.