M36W0R5020T0 STMICROELECTRONICS | Alldatasheet
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Technical content
32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory
Figure 1. Package
7191395 Specification, and the RoHS (Restriction
are compliant with Lead-free soldering processes. Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. TFBGA Connections (Top view through package)
M36W0R5020T0, M36W0R5020B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names , for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A20).Addresses A0-A17 are common inputs for the Flash memory and SRAM components. The other lines (A18-A20) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. Dur- ing Bus Write operations they control the com- mands sent to the Command Interface of the internal state machine. The Flash memory is ac- cessed through the Chip Enable signal ( EF) and through the Write Enable (WF) signal, while the SRAM is accessed through two Chip Enable sig- nals (E1S and E2S) and the Write Enable signal (W S). Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address dur- ing a Bus Read operation or input a command or the data to be programmed during a Write Bus op- eration. Flash Chip Enable (E F). The Chip Enable input activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. Flash Output Enable (GF). The Output Enable pin controls data outputs during Flash memory Bus Read operations. Flash Write Enable (W F). The Write Enable in- put controls the Bus Write operation of the Flash memory’s Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR032FT/B datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2 . Refer to Table 6., Flash Memory DC Characteristics - Cur- rents, for the value of IDD2 . After Reset all blocks are in the Locked state and the Configuration Reg- ister is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is re- quired to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteris- tics - Voltages). Flash Latch Enable (LF).Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF).The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, accord- ing to the configuration settings) when Latch En- able is at V IL. Clock is don't care during Asynchronous Read and in write operations. Flash Wait (WAITF).WAIT is a Flash memory output signal used during Synchronous Read to in- dicate whether the data on the output bus are val- id. This output is high impedance when the Flash memory Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cy- cle or one clock cycle in advance. The WAITF sig- nal is not gated by Output Enable. SRAM Chip Enable inputs (E1S, E2S). The Chip Enable inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH with E2S at VIH deselects the memory, reduc- ing the power consumption to the standby level, whereas E2 S at VIL deselects the memory and re- duces the power consumption to the Power-down level, regardless of the level of E1S. E1S and E2S can also be used to control writing to the SRAM memory array, while W S remains at VIL. It is not al- lowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Write Enable (WS). The Write Enable in- put controls writing to the SRAM memory array. W S is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a Read operation of the SRAM memory. GS is ac- tive low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable input enables the upper byte for SRAM (DQ8-DQ15). UB S is active low.
M36W0R5020T0, M36W0R5020B0 SRAM Lower Byte Enable (LBS). The Lower Byte Enable input enables the lower byte for SRAM (DQ0-DQ7). LBS is active low. VDDF Supply Voltage.VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supply for all Flash memory operations (Read, Program and Erase). VDDS Supply Voltage. VDDS provides the power supply to the internal core of the SRAM device. It is the main power supply for all SRAM operations. VDDQ Supply Voltage. VDDQ provides the power supply for the Flash memory and SRAM I/O pins. This allows all Outputs to be powered indepen- dently of the Flash memory and SRAM core power supplies: VDDF and VDDS , respectively. VPPF Program Supply Voltage. VPPF is a Flash memory power supply pin. The Supply Voltage VDDF and the Program Supply Voltage VPP can be applied in any order. The pin can also be used as a control input for the Flash memory. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ ) VPPF is seen as a con- trol input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while V PPF > VPP1 enables these functions (see Tables 6 and 7, DC Characteristics for the rel- evant values). VPPF is only sampled at the begin- ning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground refer- ence for all voltage measurements in the Flash memory (core and I/O Buffers) and SRAM compo- nents. Note: Each Flash memory device in a system should have its supply voltage (VDDF ) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capaci- tors should be as close as possible to the package). See Figure 7., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
nents which would result in a data bus contention. Figure 4. Functional Block Diagram
32 Mbit
Table 2. Main Operating modes
- LF can be tied to VIH if the valid address has been previously latched.
- WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR032FT/B datasheet for details.
Figure 5. SRAM Block Diagram
M36W0R5020T0, M36W0R5020B0 SRAM OPERATIONS There are five standard operations that control the device. These are Read, Write, Standby/Power- down, Data Retention and Output Disable. Read. Read operations are used to output the contents of the SRAM Array. The device is in Byte Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at VIH, and UBS or LBS is at VIL. The device is in Word Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Byte Enable inputs UBS and LBS are both at VIL and the two Chip Enable inputs, E1S, and E2S are Don’t Care. The Read and Standby AC Waveforms are shown in Figures 9 and 10, respectively and the parame- ters are given in Table 9., SRAM Read AC Char- acteristics. Write.Write operations are used to write data to the SRAM. The device is in Write mode whenever W S, E1S and UBS and/or LBS are at VIL, and E2S is at VIH. All these signals must be asserted to ini- tiate a Write cycle. The data is latched on the fall- ing edge of E1S, the rising edge of E2S, the falling edge of WS, or the falling edge of UBS and/or LBS, whichever occurs last. The Write cycle will termi- nate on the rising edge of E1S, the rising edge of W S, the rising edge of UBS and/or LBS, or the fall- ing edge of E2S, whichever occurs first. The tim- ings are referenced to the signal that terminates the Write cycle. The outputs are disabled during Write cycles (whenever E1S, at VIL, E2S at VIH, and WS at VIL). The Write AC Waveforms are shown in Figures 11, 12, 13 and 14, while Table 10. gives the Write AC Characteristics. Standby/Power-Down. The device automatically enters the Standby/Power-Down mode when DQ0-DQ15 are not toggling, reducing the power consumption to the Standby level, I SB . The device is also in Standby/Power-Down mode whenever E1S is at VIH, E2S is at VIL or both UBS and LBS are at VIH. The outputs then become high impedance. The Standby AC Waveforms are shown in Figure 10. See Table 9., SRAM Read AC Characteristics, for timings. Data Retention.The data retention mode is en- tered tCDR after de-asserting E1S, E2S or UBS and LBS. The data retention performance as VDD goes down to VDR is described in Table 11., Figures 15 and 16, SRAM Low V DDS Data Retention AC Waveforms, E1S or UBS / LBS Controlled and SRAM Low V DDS Data Retention AC Waveforms, E2S Controlled, respectively. Output Disable.The device is in the Output Dis- able mode whenever GS, is at VIH. In this mode, DQ0-DQ15 are high impedance.
Table 3. Absolute Maximum Ratings and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Table 4. Operating and AC Measurement Conditions Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit Table 5. Device Capacitance Note: Sampled only, not 100% tested.
Table 6. Flash Memory DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.
- VDDF Dual Operation current is the sum of read and program or erase currents.
4 Word 7 16 mA
8 Word 10 18 mA
16 Word 12 22 mA
4 Word 8 17 mA
8 Word 11 20 mA
16 Word 14 25 mA
Table 7. Flash Memory DC Characteristics - Voltages Table 8. SRAM DC Characteristics
Table 9. SRAM Read AC Characteristics Note: 1. Sampled only. Not 100% tested.
- Whatever the temperature and voltage, tE1HDZ and tE2LDZ are less than tE1LDX and tE2HDX ; tBHDZ is less than tBLDX and, tGHDZ is
Figure 11. SRAM Write AC Waveforms, E1S or E2S Controlled Note: 1. WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.
- The I/O pins are in output mode and input signals should not be applied.
S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
- UBS, LBS means both UBS and LBS.
Figure 12. SRAM Write AC Waveforms, WS Controlled, GS High during Write Note: 1. WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.
- The I/O pins are in output mode and input signals should not be applied.
S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
- UBS, LBS means both UBS and LBS.
Table 10. SRAM Write AC Characteristics Note: 1. Whatever the temperature and voltage, tWLDZ is less than tWHDX .
Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline Note: Drawing is not to scale. Table 12. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Mechanical Data
Table 13. Ordering Information Scheme Microelectronics Sales Office nearest to you.
M36W0R5020T0, M36W0R5020B0
REVISION HISTORY
Table 14. Document Revision History removed. 0.15µm Flash memory technology replaced by the 0.13µm technology. 13., Ordering Information Scheme. Document status promoted to full Datasheet. Flash memory and PSRAM data updated. TFBGA88 package fully compliant with the ST ECOPACK specification.
M36W0R5020T0, M36W0R5020B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America