M36P0R9060E0 NUMONYX | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Summary description
- 2 Signal descriptions
- 2.1 Address inputs (A0-A24)
- 2.2 Data input/output (DQ0-DQ15)
- 2.3 Latch Enable (L )
- 2.4 Clock (K)
- 2.5 Wait (WAIT)
- 2.6 Flash Chip Enable input (E F)
- 2.7 Flash Output Enable inputs (G F)
- 2.8 Flash Write Enable (W F)
- 2.9 Flash Write Protect (WP F)
- 2.10 Flash Reset (RP F)
- 2.11 PSRAM Chip Enable input (E P)
- 2.12 PSRAM Write Enable (W P)
- 2.13 PSRAM Output Enable (G P)
- 2.14 PSRAM Upper Byte Enable (UB P)
- 2.15 PSRAM Lower Byte Enable (LB P)
- 2.16 PSRAM Configuration Register Enable (CR P)
- 2.17 Deep Power-Down input (DPD F)
- 2.18 V DDF Supply Voltage
- 2.19 V CCP Supply Voltage
- 2.20 V DDQ Supply Voltage
- 2.21 V PPF Program Supply Voltage
- 2.22 V SS Ground
- 3 Functional description
- 4 Maximum rating
- 5 DC and AC parameters
November 2007 Rev. 3 1/23 M36P0R9060E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package Feature summary ■ Multi-Chip Package – 1 die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash memory –1 die of 64 Mbit (4Mb x16) PSRAM ■ Supply voltage –V DDF = VCCP = VDDQ = 1.7 to 1.95V –V PPF = 9V for fast program ■ Electronic signature – Manufacturer Code: 20h – Device Code: 8819 ■ ECOPACK® package Flash memory ■ Synchronous / asynchronous read – Synchronous Burst Read mode: 108MHz, 66MHz – Asynchronous Page Read mode – Random Access: 96ns ■ Programming time – 4.2µs typical Word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple Bank memory array: 64 Mbit banks – Four Extended Flash Array (EFA) Blocks of
64 Kbits
■ Dual operations – program/erase in one Bank while read in others – No delay between read and write operations ■ Security – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ 100,000 Program/erase cycles per block ■ Common Flash Interface (CFI) ■ Block locking – All Blocks locked at power-up – Any combination of Blocks can be locked with zero latency –W P F for Block Lock-Down – Absolute Write Protection with V PPF = VSS PSRAM ■ User-selectable operating modes – Asynchronous modes: Random Read, and Write, Page Read – Synchronous modes: NOR-Flash, Full Synchronous (Burst Read and Write) ■ Asynchronous Random Read – Access time: 70ns ■ Asynchronous Page Read – Page size: 4, 8 or 16 Words – Subsequent Read within Page: 20ns ■ Burst Read – Fixed length (4, 8, 16 or 32 Words) or Continuous ■ Low power consumption – Active current: < 25mA – Standby current: 140µA – Deep Power-Down current: < 10µA ■ Low-power features – Partial Array Self-Refresh (PASR) – Deep Power-Down (DPD) Mode – Automatic Temperature-compensated Self- Refresh TFBGA107 (ZAC) FBGA www.numonyx.com
1 Summary description M36P0R9060E0
1 Summary description
- 512-Mbit Multiple Bank Flash memory (the M58PR512J)
- 64-Mbit PSRAM (the M69KB096AM) The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58PRxxxJ and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the Numonyx website: www.numonyx.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA107 package. It is supplied with all the bits erased (set to ‘1’).
Figure 1. Logic diagram
Table 1. Signal names
- A22-A24 are Address Inputs for the Flash memory component only.
Figure 2. TFBGA connections (top view through package)
M36P0R9060E0 2 Signal descriptions
2 Signal descriptions
See Figure 1., Logic diagram and Table 1., Signal names, for a brief overview of the signals connected to this device.
2.1 Address inputs (A0-A24)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. Addresses A22 and A24 are inputs for the Flash memory component only. The Address Inputs select the cells in the Flash memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory’s Program/Erase Controller. In the PSRAM the Address Inputs select the cells in the memory array to access during Bus read and write operations.
2.2 Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UB P) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LB P) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance.
2.3 Latch Enable (L )
The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58PRxxxJ for the Flash memory.
2.4 Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58PRxxxJ for the Flash memory.
2 Signal descriptions M36P0R9060E0
2.5 Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM and to the M58PRxxxJ datasheet for the Flash memory.
2.6 Flash Chip Enable input (E F)
The Chip Enable input activates the control logic, input buffers, decoders and sense amplifiers of the Flash memory. When Chip Enable is Low, V IL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have EF at VIL and EP at VIL at the same time. Only one memory component can be enabled at a time.
2.7 Flash Output Enable inputs (G F)
The Output Enable input controls the data outputs during Flash memory Bus Read operations.
2.8 Flash Write Enable (W F)
The Write Enable input controls the Bus Write operation of the Flash memory Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.9 Flash Write Protect (WP F)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, V IL, Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M58PRxxxJ datasheet).
2.10 Flash Reset (RP F)
The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2. Refer to the M58PRxxxJ datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to the M58PRxxxJ datasheet).
M36P0R9060E0 2 Signal descriptions
2.11 PSRAM Chip Enable input (E P)
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode, according to the RCR (Refresh Configuration Register) setting.
2.12 PSRAM Write Enable (W P)
Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array.
2.13 PSRAM Output Enable (G P)
When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the PSRAM.
2.14 PSRAM Upper Byte Enable (UB P)
The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8- DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.15 PSRAM Lower Byte Enable (LB P)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0- DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High), the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low.
2.16 PSRAM Configuration Register Enable (CR P)
When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19.
2.17 Deep Power-Down input (DPD F)
The Deep Power-Down input is used to put the device in a Deep Power-Down mode. When the device is in Standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the Deep Power-Down input will cause the memory to enter the Deep Power- Down mode. When the device is in the Deep Power-Down mode, the memory cannot be modified and the data is protected. The polarity of the DPD pin is determined by ECR14. The Deep Power-Down input is active Low by default.
2.18 V DDF Supply Voltage
VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase).
2.19 V CCP Supply Voltage
The VCCP Supply Voltage is the core supply voltage.
2.20 V DDQ Supply Voltage
VDDQ provides the power supply for the Flash memory and PSRAM I/O pins. This allows all Outputs to be powered independently of the Flash memory and PSRAM core power supplies, V DDF and VCCP.
2.21 V PPF Program Supply Voltage
VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPPF > VPP1 enables these functions (see the M58PRxxxJ datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If V PPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
M36P0R9060E0 2 Signal descriptions
2.22 V SS Ground
VSS is the common ground reference for all voltage measurements in the Flashmemory (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5., AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
3 Functional description M36P0R9060E0
3 Functional description
to put the other device in the high impedance state when reading the selected device. Figure 3. Functional block diagram
64 Mbit
512 Mbit
Table 2. Main operating modes (1) Any Flash memory mode is allowed.
- In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in
Standby and Deep Power-Down modes.
- The PSRAM must have been configured to operate in as ynchronous mode by setting BCR15 to ‘1’ (default value).
- The DPD F signal polarity depends on the value of the ECR14 bit.
- WAIT signal polarity is configured using the Set Configuration Register command. See the M58PRxxxJ datasheet for
- L F can be tied to VIH if the valid address has been previously latched
- ECR15 has to be set to ‘1’ for the Flas h memory device to enter Deep Power-Down.
- If ECR15 is set to '0', the Flash memory device cannot enter the Deep Power-Down mode, even if DPDF is asserted.
- Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, VIH, during Deep Power-
4 Maximum rating M36P0R9060E0
4 Maximum rating
and other relevant quality documents. Table 3. Absolute maximum ratings
5 DC and AC parameters
Figure 4. AC measurement I/O waveform Table 4. Operating and AC measurement conditions
5 DC and AC parameters M36P0R9060E0
Figure 5. AC measurement load circuit characteristics values and illustrations. Table 5. Capacitance (1)
- Sampled only, not 100% tested.
6 Package mechanical
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. TFBGA 107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline
6 Package mechanical M36P0R9060E0
Table 6. Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package
7 Part numbering
device, please contact the Numonyx Sales Office nearest to you. Table 7. Ordering information scheme ZAC = stacked TFBGA107 C stacked footprint.
8 Revision history M36P0R9060E0
8 Revision history
Table 8. Document revision history 28-Nov-2005 1 Initial release. Document status promoted to full Datasheet. 30-Nov-2007 3 Applied Numonyx branding.