M36P0R8070E0

M36P0R8070E0 NUMONYX | Alldatasheet

Document overview

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• PDF pages: 22

Technical content

Datasheet sections

• 1 Description
• 2 Signal descriptions
• 2.1 Address inputs (A0-A23)
• 2.2 Data input/output (DQ0-DQ15)
• 2.3 Latch Enable (L )
• 2.4 Clock (K)
• 2.5 Wait (WAIT)
• 2.6 Flash Chip Enable input (E F)
• 2.7 Flash Output Enable inputs (G F)
• 2.8 Flash Write Enable (W F)
• 2.9 Flash Write Protect (WP F)
• 2.10 Flash Reset (RP F)
• 2.11 Flash Deep Power-Down (DPD F)
• 2.12 PSRAM Chip Enable input (E P)
• 2.13 PSRAM Write Enable (W P)
• 2.14 PSRAM Output Enable (G P)
• 2.15 PSRAM Upper Byte Enable (UB P)
• 2.16 PSRAM Lower Byte Enable (LB P)
• 2.17 PSRAM Configuration Register Enable (CR P)
• 2.18 V DDF supply voltage
• 2.19 V CCP supply voltage
• 2.20 V DDQ supply voltage
• 2.21 V PPF program supply voltage
• 2.22 V SS ground
• 3 Functional description
• 4 Maximum ratings
• 5 DC and AC parameters

Features

■ Multichip package – 1 die of 256 Mbit (16 Mb x 16, multiple bank, multilevel, burst) Flash memory – 1 die of 128 Mbit (8 Mb x16) PSRAM ■ Supply voltage DDF = VCCP = VDDQ = 1.7 to 1.95 V –V PPF = 9 V for fast program (12 V tolerant) ■ Electronic signature – Manufacturer code: 20h – Device code: 8818 ■ Package –E C O P A C K ® Flash memory ■ Synchronous/asynchronous read – Synchronous burst read mode:

108 MHz, 66 MHz

– Asynchronous page read mode – Random access: 93 ns ■ Programming time – 4 µs typical Word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple bank memory array: 32 Mbit banks – Four EFA (extended flash array) blocks of

64 Kbits

■ Dual operations – Program/erase in one bank while read in others – No delay between read and write operations ■ Security – 64bit unique device number – 2112 bit user programmable OTP Cells ■ 100 000 program/erase cycles per block ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency –W P F for block lock-down – Absolute write protection with V PPF = VSS ■ CFI (common Flash interface) PSRAM ■ Access time: 70 ns ■ Asynchronous page read – Page size: 4, 8 or 16 words – Subsequent read within page: 20 ns ■ Synchronous burst read/write ■ Low power consumption – Active current: < 25 mA – Standby current: 200 µA – Deep power-down current: 10 µA ■ Low power features – PASR (partial array self refresh) – DPD (deep power-down) mode TFBGA107 (ZAC) FBGA www.numonyx.com

1 Description

• 256-Mbit multiple bank Flash memory (the M58PR256J)
• 128-Mbit PSRAM (the M69KB128AA). This datasheet should be read in conjunction with the M58PR256J and M69KB128AA datasheets, which are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a stacked TFBGA107 package, and it is supplied with all the bits erased (set to ‘1’).

Figure 1. Logic diagram

Table 1. Signal names

1. A23 is an address input for the Flash memory component only.

Figure 2. TFBGA connections (top view through package)

M36P0R8070E0 Signal descriptions

2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals connected to this device.

2.1 Address inputs (A0-A23)

Addresses A0-A22 are common inputs for the Flash memory and PSRAM components. Address A23 is an input for the Flash memory component only. The address inputs select the cells in the Flash memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Flash memory’s Program/Erase Controller. In the PSRAM the address inputs select the cells in the memory array to access during bus read and write operations.

2.2 Data input/output (DQ0-DQ15)

The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. For the PSRAM component, the Upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UB P) is driven Low. The Lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LB P) is driven Low. When both UBP and LBP are disabled, the data inputs/ outputs are high impedance.

2.3 Latch Enable (L )

The Latch Enable pin is common to the Flash memory and PSRAM components. For more details about the Latch Enable signal, please refer to the datasheets of the respective memory components: M69KB128AA for the PSRAM and M58PR256J for the Flash memory.

2.4 Clock (K)

The Clock input pin is common to the Flash memory and PSRAM components. For more details about the Clock signal, please refer to the datasheets of the respective memory components: M69KB128AA for the PSRAM and M58PR256J for the Flash memory.

Signal descriptions M36P0R8070E0

2.5 Wait (WAIT)

WAIT is an output pin common to the Flash memory and PSRAM components. However, the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details on this signal, please refer to the M69KB128AA datasheet for the PSRAM and to the M58PR256J datasheet for the Flash memory.

2.6 Flash Chip Enable input (E F)

The Chip Enable input activates the control logic, input buffers, decoders, and sense amplifiers of the Flash memory. When Chip Enable is Low, V IL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have EF at VIL and EP at VIL at the same time. Only one memory component can be enabled at a time.

2.7 Flash Output Enable inputs (G F)

The Output Enable input controls the data outputs during Flash memory bus read operations.

2.8 Flash Write Enable (W F)

The Write Enable input controls the bus write operation of the Flash memory command interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first.

2.9 Flash Write Protect (WP F)

Write Protect is an input that provides additional hardware protection for each block. When Write Protect is Low, V IL, lock-down is enabled and the protection status of the locked-down blocks cannot be changed. When Write Protect is at High, VIH, lock-down is disabled and the locked-down blocks can be locked or unlocked. (See the lock status table in the M58PR256J datasheet).

2.10 Flash Reset (RP F)

The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset supply current I DD2. After Reset, all blocks are in the locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Upon exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be tied to V RPH .

M36P0R8070E0 Signal descriptions

2.11 Flash Deep Power-Down (DPD F)

The deep power-down input put sthe device in deep power-down mode. When the device is in standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the deep power-down input causes the memory to enter deep power-down mode. When the device is in the deep power-down mode, the memory cannot be modified and the data is protected. The polarity of the DPD F pin is determined by ECR14. The deep power-down input is active Low by default.

2.12 PSRAM Chip Enable input (E P)

The Chip Enable input activates the PSRAM when driven Low (asserted). When de- asserted (V IH), the device is disabled, and goes automatically in low-power standby mode or deep power-down mode, according to the RCR (Refresh Configuration Register) setting.

2.13 PSRAM Write Enable (W P)

Write Enable, WP, controls the bus write operation of the PSRAM. When asserted (VIL), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array.

2.14 PSRAM Output Enable (G P)

When held Low, VIL, the Output Enable, GP, enables the bus read operations of the PSRAM.

2.15 PSRAM Upper Byte Enable (UB P)

The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8- DQ15) to or from the upper part of the selected address during a write or read operation.

2.16 PSRAM Lower Byte Enable (LB P)

The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0- DQ7) to or from the lower part of the selected address during a write or read operation. If both LBP and UBP are disabled (High), the device disables the data bus from receiving or transmitting data. Although the device seems to be deselected, it remains in an active mode as long as E P remains Low.

2.17 PSRAM Configuration Register Enable (CR P)

When this signal is driven High, VIH, bus read or write operations access either the value of the RCR or the BCR (Bus Configuration Register) according to the value of A19.

Signal descriptions M36P0R8070E0

2.18 V DDF supply voltage

VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (read, program and erase).

2.19 V CCP supply voltage

The VCCP supply voltage is the core supply voltage.

2.20 V DDQ supply voltage

VDDQ provides the power supply for the Flash memory and PSRAM I/O pins. This allows all outputs to be powered independently of the Flash memory and PSRAM core power supplies, V DDF and VCCP.

2.21 V PPF program supply voltage

VPPF is both a control input and a power supply pin for the Flash memory. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPPF > VPP1 enables these functions. VPPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the program/erase algorithm is completed.

2.22 V SS ground

VSS is the common ground reference for all voltage measurements in the Flash memory (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a sys tem should have its supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1 µF ceramic capacitor close to the pin (high-frequency, inherently-low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required V PPF program and erase currents.

3 Functional description

the other device in the high impedance state when reading the selected device. Figure 3. Functional block diagram

128 Mbit

256 Mbit

Functional description M36P0R8070E0 Table 2. Main operating modes (1) Flash memories must be disabled.

contents

Register(9) Low-Z V IL VIL VIH XV IH XX 00(RCR) 10(BCR) BCR/ RCR data Hi-Z Standby Any Flash memory mode is allowed. Only one Flash memory can be enabled at a time Hi-Z X V IH VIL XX X X H i - Z Deep Power- Down(10) Hi-Z X V IH XX XXX H i - Z 1. X = Don’t Care. 2. The DPD F signal polarity depends on the value of the ECR14 bit. 3. WAIT signal polarity is configured using the Set Configuration Register command. See the M58PR256J datasheet for details. 4. A18 and A19 are used to select the BCR (Bus Configuration Register), RCR (Refresh Configuration Register) or DIDR (Device ID Register). 5. If ECR15 is set to '0', the Flash memory device cannot enter the Deep Power-Down mode, even if DPDF is asserted. 6. L can be tied to VIH if the valid address has been previously latched. 7. Depends on G F. 8. ECR15 has to be set to ‘1’ for the Flas h memory device to enter Deep Power-Down. 9. BCR and RCR only. 10. Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to ‘0’, and E has to be maintained High, VIH, during Deep Power-Down mode.

4 Maximum ratings

and other relevant quality documents. Table 3. Absolute Maximum Ratings

5 DC and AC parameters

Figure 4. AC measurement I/O waveform Table 4. Operating and AC measurement conditions

Figure 5. AC measurement load circuit Table 5. Capacitance (1)

1. Sampled only, not 100% tested.

6 Package mechanical

The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. TFBGA107 8 x 11 mm 9 x 12 active ball array, 0.8 mm pitch,

Table 6. Stacked TFBGA107 8 x 11 mm 9 x 12 active ball array, 0.8 mm pitch,

7 Part numbering

device, please contact the Numonyx sales office nearest to you. Table 7. Ordering information scheme ZAC = stacked TFBGA107 C stacked footprint.

8 Revision history

Table 8. Document revision history 2-Oct-2007 1 Initial release. 10-Dec-2007 2 Applied Numonyx branding.