M36LLR8760T1 STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
16 Mbit Banks for the 256 Mbit Memory
8 Mbit Banks for the 128 Mbit Memory
Figure 1. Package
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1 SUMMARY DESCRIPTION The M36LLR8760T1, M36LLR8760D1, M36LLR8760M1 and M36LLR8760B1 combine three memory devices in a Multi-Chip Package: ■ a 256-Mbit, Multiple Bank Flash memory, the M30L0R8000(T/B)0 (Flash 1) ■ a 128-Mbit, Multiple Bank Flash memory, the M58LR128GT/B (Flash 2) ■ a 64-Mbit PseudoSRAM, the M69KB096AA. For detailed information on how to use the memo- ry components, refer to the M30L0R8000(T/B)0, M58LR128GT/B and M69KB096AA datasheets which are available from your local STMicroelec- tronics distributor and should be read in conjunc- tion with the M36LLR8760x1 datasheet. What differs between the M36LLR8760T1, M36LLR8760D1 and M36LLR8760B1 is the con- figuration of the two Flash memories: ■ in the M36LLR8760T1, Flash 1 and Flash 2 both have a Top Configuration (Parameter Blocks located at the top of the address space). ■ in the M36LLR8760D1, Flash 1 has a Bottom Configuration (Parameter Blocks at the bottom of the address space) and Flash 2 has a Top Configuration. ■ In the M36LLR8760M1, Flash 1 has a Top Configuration and Flash 2 has a Bottom Configuration. ■ In the M36LLR8760B1, both Flash 1 and Flash 2 have a Bottom Configuration. Recommended operating conditions do not allow more than one memory to be active at the same time. The memories are offered in a Stacked LFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) pack- age. In addition to the standard version, the package is also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram Table 1. Signal Names Note: 1. A22 is an Address Input for the two Flash memories only. A23 is for the 256Mb Flash memory component only.
Figure 3. LFBGA Connections (Top view through package) Note: A22 is an Address Input for the two Flash memories only. A23 is for the 256Mb Flash memory component only.
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names , for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A23).Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. A22 is common to the two Flash memory components whereas A23 is an ad- dress input for the 256 Mbit Flash memory compo- nent only. The Address Inputs select the cells in the memory array to access during Bus Read operations. Dur- ing Bus Write operations they control the com- mands sent to the Command Interface of the internal state machine. The Flash memories are accessed through the Chip Enable signal (E F) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable sig- nal (E P) and the Write Enable signal (WP). It is not allowed to have EF Low, and EP Low at the same time. Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address dur- ing a Bus Read operation or input a command or the data to be programmed during a Bus Write op- eration. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UB P ) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected ad- dress when Lower Byte Enable (LB P) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance. Latch Enable (L).The Latch Enable pin is com- mon to the Flash memory and PSRAM compo- nents. For details of how the Latch Enable signal be- haves, please refer to the datasheets of the re- spective memory components: M69KB096AA for the PSRAM and M30L0R8000(T/B)0 and M58LR128GT/B for Flash 1 and Flash 2, respec- tively. Clock (K).The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for the PSRAM and M30L0R8000(T/B)0 and M58LR128GT/B for Flash 1 and Flash 2, respec- tively. Wait (WAIT).WAIT is an output pin common to the Flash memory and PSRAM components. How- ever the WAIT signal does not behave in the same way for the PSRAM and the Flash memories. For details of how it behaves, please refer to the M69KB096AA datasheet for the PSRAM and to the M30L0R8000T/B0 and M58LR128GT/B datasheets for Flash 1 and Flash 2, respectively. Flash Chip Enable Inputs (E F1, EF2). The Flash Chip Enable inputs activate the control logic, input buffers, decoders and sense amplifiers of the Flash memory component selected (EF1 is used to select Flash 1, EF2 is used to select Flash 2). When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip En- able is at VIH the corresponding Flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have E F1 at VIL, EF2 at VIL and EP at VIL at the same time. Only one memory com- ponent can be enabled at a time. Flash Output Enable Inputs (GF1, GF2).The Output Enable pins control the data outputs during Flash memory Bus Read operations. Flash Write Enable (W F). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WP F). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, V IL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, V IH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R8000(T/B)0 and M58LR128GT/B datasheets). Flash Reset (RP F). The Reset input provides a hardware reset of the Flash memories. When Re- set is at VIL, the memory is in Reset mode: the out- puts are high impedance and the current consumption is reduced to the Reset Supply Cur- rent I DD2 . Refer to Table 6., Flash 1 DC Character- istics - Currents, for the value of IDD2 . After Reset all blocks are in the Locked state and the Configu- ration Register is reset. When Reset is at V IH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1 a negative transition of Chip Enable or Latch En- able is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash 1 and Flash 2 DC Charac- teristics - Voltages). PSRAM Chip Enable input (EP). The Chip En- able input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode. PSRAM Write Enable (W P).Write Enable, WP , controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. PSRAM Output Enable (G P). Output Enable, G P, provides a high speed tri-state control, allow- ing fast read/write cycles to be achieved with the common I/O data bus. PSRAM Upper Byte Enable (UB P).The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. PSRAM Lower Byte Enable (LB P ).The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LB P and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as E P remains Low. PSRAM Configuration Register Enable (CRP). When this signal is driven High, VIH, Write opera- tions load either the value of the Refresh Configu- ration Register (RCR) or the Bus configuration register (BCR). V DDF1 /VDDF2 Supply Voltages.VDDF1 and VDDF2 provide the power supply to the internal cores of Flash 1 and Flash 2, respectively. It is the main power supply for all Flash memory opera- tions (Read, Program and Erase). VCCP Supply Voltage. VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM opera- tions. V DDQF Supply Voltage. VDDQF provides the power supply for the Flash memory. This allows all Outputs to be powered independently of the Flash memory and SRAM core power supplies, V DDF and VCCP . VPPF Program Supply Voltage. VPPF is both a control input and a power supply pin for the Flash memories. The two functions are selected by the voltage range applied to the pin. If V PPF is kept in a low voltage range (0V to VDDQF ) VPPF is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against Program or Erase, while VPPF > VPP1 en- ables these functions (see Tables 6 and 8, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If V PPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground refer- ence for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (V DDF ) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance ca- pacitors should be as close as possible to the package). See Figure 6., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required V PPF program and erase currents.
respectively, and EP for the PSRAM. Figure 4. Functional Block Diagram
64 Mbit
128 Mbit
256 Mbit
Table 2. Main Operating Modes
- LF can be tied to VIH if the valid address has been previously latched.
- WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R8000(T/B)0 and
M30L0R8000(T/B)0 datasheets for details.
- EF is either EF1 or EF2, and GF is either GF1 or GF2 according to the Flash memory enabled. Only one Flash memory can be enabled
Table 3. Absolute Maximum Ratings and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Table 4. Operating and AC Measurement Conditions Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit Table 5. Device Capacitance Note: Sampled only, not 100% tested.
Table 6. Flash 1 DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.
- VDDF1 Dual Operation current is the sum of read and program or erase currents.
4 Word 16 18 mA
8 Word 18 20 mA
16 Word 23 25 mA
Table 7. Flash 2 DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.
- VDDF2 Dual Operation current is the sum of read and program or erase currents.
Table 8. Flash 1 and Flash 2 DC Characteristics - Voltages Table 9. PSRAM DC Characteristics drive the output capacitance expected in the actual system.
- ISB (Max) values are measured with RCR2 to RCR0 bits set to ‘000’ (full array refresh) and RCR6 to RCR5 bits set to ‘11’ (temper-
- The Operating Temperature is +25°C.
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 10. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
Table 11. Ordering Information Scheme Microelectronics Sales Office nearest to you.
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
REVISION HISTORY
Table 12. Document Revision History 01-Feb-2005 0.2 Part Number M69KB096A changed to M69KB096AA throughout document. Table 9. modified.
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America