M36L0T7050T2 NUMONYX | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Summary description
- 2 Signal descriptions
- 2.1 Address Inputs (A0-A22)
- 2.2 Data Input/Output (DQ0-DQ15)
- 2.3 Flash Chip Enable (E F)
- 2.4 Flash Output Enable (G F)
- 2.5 Flash Write Enable (W F)
- 2.6 Flash Write Protect (WP F)
- 2.7 Flash Reset (RP F)
- 2.8 Flash Latch Enable (L F)
- 2.9 Flash Clock (K F)
- 2.10 Flash Wait (WAIT F)
- 2.11 PSRAM Chip Enable Input (E1 P)
- 2.12 PSRAM Chip Enable Input (E2 P)
- 2.13 PSRAM Write Enable (W P)
- 2.14 PSRAM Output Enable (G P)
- 2.15 PSRAM Upper Byte Enable (UB P)
- 2.16 PSRAM Lower Byte Enable (LB P)
- 2.17 V DDF Supply Voltage
- 2.18 V CCP Supply Voltage
- 2.19 V DDQ Supply Voltage
- 2.20 V PPF Program Supply Voltage
- 2.21 V SS Ground
- 3 Functional description
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. November 2007 Rev 0.2 1/22 M36L0T7050T2 M36L0T7050B2
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory
and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package Feature summary ■ Multi-Chip Package – 1 die of 128 Mbit (8Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 32 Mbit (2Mb x16) Pseudo SRAM ■ Supply voltage DDF = 1.7 to 1.95V –V CCP = VDDQ = 2.7 to 3.1V –V PPF = 9V for fast program ■ Electronic signature – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0T7050T2: 88C4h – Device Code (Bottom Flash Configuration) M36L0T7050B2: 88C5h ■ ECOPACK® packages available Flash memory ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 52MHz – Random Access: 85ns ■ Synchronous Burst Read Suspend ■ Programming time – 2.5µs typical Word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple Bank Memory Array: 8 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ Dual operations – program/erase in one Bank while read in others – No delay between read and write operations ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency –W P for Block Lock-Down – Absolute Write Protection with V PP = VSS ■ Security – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ Common Flash Interface (CFI) ■ 100,000 program/erase cycles per block PSRAM ■ Access time: 65ns ■ 8-Word Page Access capability: 18ns ■ Low standby current: 100µA ■ Deep power down current: 10µA ■ Compatible with standard LPSRAM ■ Power-down modes – Deep Power-Down – 4 Mbit Partial Array Refresh – 8 Mbit Partial Array Refresh TFBGA88 (ZAQ) 8 x 10mm FBGA www.numonyx.com
M36L0T7050T2, M36L0T7050B2 Contents
1 Summary description
- a 128-Mbit, Multiple Bank, Multi-Level, Burst, Flash memory, the M58LT128HT or M58LT128HB
- a 32-Mbit PseudoSRAM, the M69KW048BD. The purpose of this document is to describe how the two memory components operate with respect to each other. It should be read in conjunction with the M58LT128HTB and M69KW048BD datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package. The devices are supplied with all the bits erased (set to ‘1’).
Figure 1. Logic diagram
Table 1. Signal names
- A22-A21 are not connected to the PSRAM component.
Figure 2. TFBGA Connections (Top view through package)
M36L0T7050T2, M36L0T7050B2 Signal descriptions
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1 Address Inputs (A0-A22)
Addresses A0-A20 are common inputs for the Flash memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller in the Flash memory, and they select the cells to be accessed in the PSRAM.
2.2 Data Input/Output (DQ0-DQ15)
In the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. In the PSRAM DQ0-DQ7 and/or DQ8-DQ15 carry the data to or from the upper and/or lower part(s) of the selected address during a Write or Read operation, when Upper Byte Enable (UB P) and/or Lower Byte Enable (LBP) is/are driven Low.
2.3 Flash Chip Enable (E F)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V IL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to set EF at VIL, E1P at VIL and E2P at VIH at the same time.
2.4 Flash Output Enable (G F)
The Output Enable input controls data output during Flash memory Bus Read operations.
2.5 Flash Write Enable (W F)
The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
Signal descriptions M36L0T7050T2, M36L0T7050B2
2.6 Flash Write Protect (WP F)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M58LT128HTB datasheet).
2.7 Flash Reset (RP F)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2. Refer to M58LT128HTB datasheet for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to M58LT128HTB datasheet).
2.8 Flash Latch Enable (L F)
Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, V IL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.9 Flash Clock (K F)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is don't care during Asynchronous Read and in write operations.
2.10 Flash Wait (WAIT F)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at V IH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable.
2.11 PSRAM Chip Enable Input (E1 P)
When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de- asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. It is not allowed to set E F at VIL, E1P at VIL and E2P at VIH at the same time.
M36L0T7050T2, M36L0T7050B2 Signal descriptions
2.12 PSRAM Chip Enable Input (E2 P)
The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode.
2.13 PSRAM Write Enable (W P)
The Write Enable, WP, controls the Bus Write operation of the memory.
2.14 PSRAM Output Enable (G P)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus.
2.15 PSRAM Upper Byte Enable (UB P)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8- DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16 PSRAM Lower Byte Enable (LB P)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0- DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17 V DDF Supply Voltage
VDDF provides the power supply to the internal cores of the Flash memory component. It is the main power supply for all Flash operations (Read, Program and Erase).
2.18 V CCP Supply Voltage
The VCCP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed.
2.19 V DDQ Supply Voltage
VDDQ provides the power supply for the Flash memory I/O pins. This allows all Outputs to be powered independently of the Flash Memory core power supply, VDDF.
Signal descriptions M36L0T7050T2, M36L0T7050B2
2.20 V PPF Program Supply Voltage
VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1 enables these functions (see the M58LT128HTB datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If V PPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.21 V SS Ground
VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. Note: The Flash memory device in a system should have their supply voltage (V DDF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
3 Functional description
memory and E1P and E2P for the PSRAM. the other device in the high impedance state when reading the selected device. Figure 3. Functional block diagram
16 Mbit
128 Mbit
Table 2. Operating modes (1)
- WAIT signal polarity is configured us ing the Set Configuration Register command. See the M58LT128HTB datasheet for
- L F can be tied to VIH if the valid address has been previously latched.
- Should not be kept in this logic condition for a period longer than 1µs.
- G P can be VIL during the Write operation if the following conditions are satisfied:
b. GP stays VIL during the entire Write cycle.
- Power-Down mode can be entered from Standby state and all Da ta outputs are in High-Z. The Power-Down current and
data retention depend on the selection of Power-Down programming.
4 Maximum rating
and other relevant quality documents. Table 3. Absolute maximum ratings
5 DC and AC parameters
Figure 4. AC Measurement I/O Waveform Table 4. Operating and AC measurement conditions
Figure 5. AC measurement load circuit characteristic values and illustrations. Table 5. Device Capacitance (1)
- Sampled only, not 100% tested.
6 Package mechanical
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch,
Table 6. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
7 Part numbering
device, please contact the Numonyx Sales Office nearest to you. Table 7. Ordering information scheme
8 Revision history
Table 8. Document revision history 04-May-2006 01 Initial release. 13-Nov-2007 02 Applied Numonyx branding.