M36L0R7060U1 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 22
Technical content
Datasheet sections
- 1 Summary description
- 2 Signal descriptions
- 2.1 Address Inputs (ADQ0-ADQ15 and A16-A22)
- 2.2 Data Input/Output (ADQ0-ADQ15)
- 2.3 Latch Enable (L)
- 2.4 Clock (K)
- 2.5 Wait (WAIT)
- 2.6 Flash memory Chip Enable (EF)
- 2.7 Flash memory Output Enable (GF)
- 2.8 Flash memory Write Enable (WF)
- 2.9 Flash memory Write Protect (WPF)
- 2.10 Flash memory Reset (RPF)
- 2.11 PSRAM Chip Enable (EP)
- 2.12 PSRAM Output Enable (GP)
- 2.13 PSRAM Write Enable (WP)
- 2.14 PSRAM Upper Byte Enable (UBP)
- 2.15 PSRAM Lower Byte Enable (LBP)
- 2.16 PSRAM Configuration Register Enable (CRP)
- 2.17 V DDF Flash memory Supply Voltage
- 2.18 V CCP PSRAM Supply Voltage
- 2.19 V DDQF Supply Voltage
- 2.20 V PPF Flash memory Program Supply Voltage
- 2.21 V SS Ground
- 2.22 V SSQ Ground
- 3 Functional description
- 4 Maximum rating
- 5 DC and AC parameters
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. June 2006 Rev 1 1/22 M36L0R7060U1 M36L0R7060L1 M36L0R7050U1 M36L0R7050L1
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash
memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package Feature summary ■ Multi-Chip Package – 1 die of 128 Mbit (8Mb x16, Mux I/O Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 32 or 64Mbit Mux I/O, Burst Pseudo SRAM ■ Supply voltage –V DDF = VDDP = VDDQF = 1.7 to 1.95V –V PPF = 9V for fast program ■ Electronic signature – Manufacturer Code: 20h – Device Codes (Top Flash Configuration): M36L0R7060U1: 882Eh, M36L0R7050U1: 882Eh – Device Codes (Bottom Flash Configuration) M36L0R7060L1: 882Fh M36L0R7050L1: 882Fh ■ ECOPACK® package Flash memory ■ Multiplexed address/data ■ Synchronous / asynchronous read – Synchronous Burst Read mode: 66MHz – Random Access: 85ns ■ Synchronous burst read suspend programming time – 10µs typical Word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple Bank Memory Array: 8 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ Security – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ 100,000 program/erase cycles per block ■ Dual operations – program/erase in one Bank while read in others – No delay between Read and Write operations ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency –W P F for Block Lock-Down – Absolute Write Protection with VPPF = VSS ■ Common Flash Interface (CFI) PSRAM ■ Access time: 70ns ■ Synchronous modes: – Synchronous Write: continuous burst – Synchronous Read: continuous burst or fixed length: 4, 8 or 16 Words for 32 Mbit devices or 4, 8,16 or 32 Words for 64 Mbit devices – Maximum Clock Frequency: 83MHz ■ Low power consumption ■ Low power features – Partial Array Self-Refresh (PASR) – Deep Power-Down (DPD) Mode – Automatic Temperature-compensated Self- Refresh TFBGA88 (ZAM) 8 x 10mm FBGA
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Contents
Summary description M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
1 Summary description
The M36L0R7060U1, M36L0R7060L1, M36L0R7050U1 and M36L0R7050L1 combine two memory devices in a Multi-Chip Package:
- a 128-Mbit, Multiple Bank Flash memory, the M58LR128G(U/L)
- a 32 or 64 Mbit PseudoSRAM, the M69KM048AA or M69KM096AA, respectively. The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58LRxxxGUL and M69KM048AA or M69KM096AA datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the STMicroelectronics website: www.st.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 ×10mm, 8 × 10 ball array, 0.8mm pitch) package. In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1. Logic diagram
Table 1. Signal names
- A16-A20 (in the case of a 32Mb PSRAM) or A16-A21 (in the case of a 64Mb PSRAM) are common to the
- A21-A22 (if the MCP contains a 32Mb PSRAM) or A22 (if the MCP contains a 64Mb PSRAM) are Address
Input(s) for the Flash memory component only.
Figure 2. TFBGA connections (top view through package)
Signal descriptions M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1 Address Inputs (A DQ0-ADQ15 and A16-A22)
ADQ0-ADQ15 and A16-A20 (for the M36L0R7050U1/L1) or A16-A21 (for the M36L0R7060U1/L1) are common to the Flash memory and PSRAM components. In the Flash memory, the Address Inputs select the cells in the array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. In the PSRAM, the Address Inputs A16-A20 (/A21) are used in conjunction with ADQ0 to ADQ15, to select the cells in the memory array that are accessed during read and write operations.
2.2 Data Input/Output (ADQ0-ADQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation.
2.3 Latch Enable (L )
The Latch Enable input is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL for the Flash memory.
2.4 Clock (K)
The Clock input is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL for the Flash memory.
2.5 Wait (WAIT)
The Wait output is common to the Flash memory and PSRAM components. For details of how the WAIT signal behaves, please refer to the datasheets of the respective memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL for the Flash memory
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Signal descriptions
2.6 Flash memory Chip Enable (E F)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. It is not allowed to set both EF and EP to VIL at the same time.
2.7 Flash memory Output Enable (G F)
The Output Enable input controls data outputs during the Bus Read operation of the Flash memory.
2.8 Flash memory Write Enable (W F)
The Write Enable input controls the Bus Write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.9 Flash memory Write Protect (WP F)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to M58LRxxxGUL datasheet).
2.10 Flash memory Reset (RP F)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2 . Refer to the M58LRxxxGUL datasheet for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to the M58LRxxxGUL datasheet).
2.11 PSRAM Chip Enable (E P)
Chip Enable, EP, activates the device when driven Low (asserted). When de-asserted (VIH), the device is disabled and goes automatically in low-power Standby mode or Deep Power- Down mode, according to the RCR settings. It is not allowed to set both E F and EP to VIL at the same time.
Signal descriptions M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2.12 PSRAM Output Enable (G P)
When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the memory.
2.13 PSRAM Write Enable (W P)
Write Enable, WP, controls the Bus Write operation of the memory. When asserted (VIL), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array.
2.14 PSRAM Upper Byte Enable (UB P)
The Upper Byte Enable, UBP, gates the data on the Upper Byte of the Address Inputs/ Data Inputs/Outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a write or read operation.
2.15 PSRAM Lower Byte Enable (LB P)
The Lower Byte Enable, LBP, gates the data on the Lower Byte of the Address Inputs/Data Input/Outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write or read operation. If both LB P and UBP are disabled (High), the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low.
2.16 PSRAM Configuration Register Enable (CRP)
When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19.
2.17 V DDF Flash memory Supply Voltage
VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase).
2.18 V CCP PSRAM Supply Voltage
The VCCP Supply Voltage is the core supply voltage.
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Signal descriptions
2.19 V DDQF Supply Voltage
VDDQF provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDDF . VDDQF can be tied to VDDF or can use a separate supply.
2.20 V PPF Flash memory Program Supply Voltage
VPPF is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF ) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPPF in the VPP1 range enables these functions (see the M58LRxxxGUL datasheet for the relevant values). VPPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.21 V SS Ground
VSS ground is the common Flash memory and PSRAM ground. It is the reference for the core supplies. It must be connected to the system ground.
2.22 V SSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQF . VSSQ must be connected to VSS Note: Each device in a system should have VDDF , VDDQF and VPP decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
3 Functional description
memory and the PSRAM components which would result in a data bus contention. reading the selected device. Figure 3. Functional block diagram
- Address Inputs corresponding to the M36L0R7050U1 and M36L0R7050L1 devices.
- Address Inputs corresponding to the M36L0R7060U1 and M36L0R7060L1 devices.
32 Mbit
64 Mbit
128 Mbit
Table 2. Operating modes - Standard Asynchronous operation
- The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode.
- In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
- Operating mode available in the M36L0R7060U1 and M36L0R7060L1 only (see M69KM096AA datasheet).
- In the PSRAM of the M36L0R7050U1 and M36L0R7050L1, A19 is used to select between the BCR and the RCR whereas
- The device enters Deep Power-Down mode by driving the Chip Enable signal, E
set to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP) .
4 Maximum rating
Program and other relevant quality documents. Table 3. Absolute maximum ratings
5 DC and AC parameters
Figure 4. AC measurement I/O waveform Table 4. Operating and AC measurement conditions
Figure 5. AC measurement load circuit further DC and AC characteristics values and illustrations. Table 5. Device capacitance
- Sampled only, not 100% tested.
6 Package mechanical
Figure 6. TFBGA88 8 × 10mm, 8 × 10 ball array - 0.8mm pitch, bottom view package Table 6. Stacked TFBGA88 8 × 10mm - 8 × 10 active ball array, 0.8mm pitch,
7 Part numbering
Table 7. Part numbering scheme
8 Revision history
Table 8. Document revision history 08-Jun-2006 1 Initial release.