M36L0R7060T1 NUMONYX | Alldatasheet
Document overview
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- PDF pages: 22
Technical content
Datasheet sections
- 1 Description
- 2 Signal descriptions
- 2.1 Address inputs (A0-A22)
- 2.2 Data input/output (DQ0-DQ15)
- 2.3 Latch Enable (L )
- 2.4 Clock (K)
- 2.5 Wait (WAIT)
- 2.6 Flash Chip Enable (E F)
- 2.7 Flash Output Enable (G F)
- 2.8 Flash Write Enable (W F)
- 2.9 Flash Write Protect (WP F)
- 2.10 Flash Reset (RP F)
- 2.11 PSRAM Chip Enable input (E P)
- 2.12 PSRAM Write Enable (W P)
- 2.13 PSRAM Output Enable (G P)
- 2.14 PSRAM Upper Byte Enable (UB P)
- 2.15 PSRAM Lower Byte Enable (LB P)
- 2.16 PSRAM Configuration Register Enable (CR P)
- 2.17 V DDF supply voltage
- 2.18 V CCP supply voltage
- 2.19 V DDQF supply voltage
- 2.20 V PPF Program supply voltage
- 2.21 V SS ground
- 3 Functional description
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical
Features
■ Multichip package – 1 die of 128 Mbit (8 Mb x16, Multiple Bank, Multilevel, Burst) Flash memory – 1 die of 64 Mbit (4 Mb x16) Pseudo SRAM ■ Supply voltage DDF = VCCP = VDDQF = 1.7 to 1.95 V –V PPF = 9 V for fast program ■ Electronic signature – Manufacturer Code: 20h – Top Device Code M36L0R7060T1: 88C4h – Bottom Device Code M36L0R7060B1: 88C5h ■ Package –E C O P A C K ® Flash memory ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 54 MHz,
66 MHz
– Random Access: 70 ns, 85 ns ■ Synchronous Burst Read Suspend ■ Programming time – 2.5 µs typical word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple Bank memory array: 8 Mbit banks – Parameter Blocks (top or bottom location) ■ Common Flash Interface (CFI) ■ 100 000 program/erase cycles per block ■ Dual operations – program/erase in one Bank while read in others – No delay between read and write operations ■ Security – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency –W P F for Block Lock-Down – Absolute Write Protection with V PPF = VSS PSRAM ■ Access time: 70 ns ■ Asynchronous Page Read – Page Size: 4, 8 or 16 words – Subsequent read within page: 20 ns ■ Low power features – Automatic Temperature-compensated Self- Refresh (TCR) – Partial Array Self-Refresh (PASR) – Deep Power-Down (DPD) mode ■ Synchronous Burst Read/Write TFBGA88 (ZAQ) 8 x 10 mm FBGA www.numonyx.com
M36L0R7060T1, M36L0R7060B1 Contents
Table 6. Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,
1 Description
- a 128-Mbit, Multiple Bank Flash memory, the M58LR128HT or M58LR128HB
- a 64-Mbit PseudoSRAM, the M69KB096AM The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58LR128HTB and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch) package. The memory is supplied with all the bits erased (set to ‘1’).
Figure 1. Logic diagram
Table 1. Signal names
Figure 2. TFBGA connections (top view through package)
M36L0R7060T1, M36L0R7060B1 Signal descriptions
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device.
2.1 Address inputs (A0-A22)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The other lines (A22) is an input for the Flash memory component only. The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable signal ( EF) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP).
2.2 Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data inputs/outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UB P) is driven Low. The lower Byte Data inputs/outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LB P) is driven Low. When both UBP and LBP are disabled, the Data inputs/outputs are high impedance.
2.3 Latch Enable (L )
The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory.
2.4 Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory.
Signal descriptions M36L0R7060T1, M36L0R7060B1
2.5 Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM and to the M58LR128HTB datasheet for the Flash memory.
2.6 Flash Chip Enable (E F)
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense amplifiers of the Flash memory component. When Chip Enable is Low, V IL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.7 Flash Output Enable (G F)
The Output Enable pin controls the data outputs during Flash memory Bus Read operations.
2.8 Flash Write Enable (W F)
The Write Enable controls the Bus Write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.9 Flash Write Protect (WP F)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, V IL, Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R7000T1/B1 datasheet).
2.10 Flash Reset (RP F)
The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2. Refer to the M58LR128HTB datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied to V RPH (refer to the M58LR128HTB datasheet).
M36L0R7060T1, M36L0R7060B1 Signal descriptions
2.11 PSRAM Chip Enable input (E P)
The Chip Enable input activates the PSRAM when driven Low (asserted). When de- asserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode, according to the RCR settings.
2.12 PSRAM Write Enable (W P)
Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array.
2.13 PSRAM Output Enable (G P)
When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the memory.
2.14 PSRAM Upper Byte Enable (UB P)
The Upper Byte En-able, UBP, gates the data on the Upper Byte Data inputs/outputs (DQ8- DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.15 PSRAM Lower Byte Enable (LB P)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data inputs/outputs (DQ0- DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low.
2.16 PSRAM Configuration Register Enable (CR P)
When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19.
2.17 V DDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase).
2.18 V CCP supply voltage
VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations.
Signal descriptions M36L0R7060T1, M36L0R7060B1
2.19 V DDQF supply voltage
VDDQF provides the power supply for the Flash I/O pins. This allows all outputs to be powered independently of the Flash core power supplies, VDDF and VCCP.
2.20 V PPF Program supply voltage
VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPP in the VPP1 range enables these functions (see the M58LR128HTB datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If V PPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.21 V SS ground
VSS is the common ground reference for all voltage measurements in the Flash (core and I/O buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (V DDF) and the program supply voltage VPPF decoupled with a 0.1 µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
3 Functional description
memory and the PSRAM components which would result in a data bus contention. reading the selected device. Figure 3. Functional block diagram
64 Mbit
128 Mbit
Table 2. Main operating modes (1)
- In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in
Standby and Deep Power-Down modes.
- The PSRAM must have been configured to operate in as ynchronous mode by setting BCR15 to ‘1’ (default value).
- WAIT signal polarity is configured using the Set Configuration Register command. See the M58LR128HTB datasheet for
- L F can be tied to VIH if the valid address has been previously latched.
- A18 and A19 are used to select the BCR, RCR or DIDR registers.
- Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E
4 Maximum rating
and other relevant quality documents. Table 3. Absolute maximum ratings
5 DC and AC parameters
Figure 4. AC measurement I/O waveform Table 4. Operating and AC measurement conditions
Figure 5. AC measurement load circuit characteristics values and illustrations. Table 5. Device capacitance
- Sampled only, not 100% tested.
6 Package mechanical
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline
7 Part numbering
device, please contact the Numonyx Sales Office nearest to you. Table 7. Ordering information scheme
8 Revision history
Table 8. Document revision history 23-May-2006 0.1 First release. Option in Table 7: Ordering information scheme. 07-May-2007 1 Document status promoted from Target Specification to full Datasheet. 70 ns speed class and 66 MHz frequency added. 13-Nov-2007 2 Applied Numonyx branding.