M36L0R7040T0 STMICROELECTRONICS | Alldatasheet
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Technical content
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
Figure 1. Package
than one memory to be active at the same time. (8x10mm, 8x10 ball array, 0.8mm pitch) package. (Restriction of Hazardous Substances) directive. Figure 2. Logic Diagram Table 1. Signal Names Note: 1. A22-A20 are not connected to the PSRAM component.
Figure 3. TFBGA Connections (Top view through package)
M36L0R7040T0, M36L0R7040B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names , for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A22).Addresses A0-A19 are common inputs for the Flash memory and the PSRAM components. The other lines (A20-A22) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. Dur- ing Bus Write operations they control the com- mands sent to the Command Interface of the Flash memory Program/Erase Controller or they select the cells to access in the PSRAM. The Flash memory component is accessed through the Chip Enable signal ( EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP). Data Input/Output (DQ0-DQ15). In the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be pro- grammed during a Write Bus operation. In the PSRAM the Upper Byte Data Inputs/Out- puts, DQ8-DQ15, carry the data to or from the up- per part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. The Lower Byte Data Inputs/Outputs, DQ0-DQ7, carry the data to or from the lower part of the se- lected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip En- able is Low, V IL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable input controls data output during Flash memory Bus Read operations. Flash Write Enable (W F). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, V IL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R7000T0 datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at V IL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2 . Refer to Table 6., Flash Memory DC Characteristics - Cur- rents, for the value of IDD2 . After Reset all blocks are in the Locked state and the Configuration Reg- ister is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is re- quired to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteris- tics - Voltages). Flash Latch Enable (LF).Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF).The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, accord- ing to the configuration settings) when Latch En- able is at V IL. Clock is don't care during Asynchronous Read and in write operations. Flash Wait (WAITF).WAIT F is a Flash output sig- nal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be config- ured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. PSRAM Chip Enable (E1P).When asserted (Low), the Chip Enable, E1P, activates the memo- ry state machine, address buffers and decoders, allowing Read and Write operations to be per- formed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. It is not allowed to set E F at VIL, E1P at VIL and E2P at VIH at the same time. PSRAM Chip Enable (E2P).The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode.
M36L0R7040T0, M36L0R7040B0 It is not allowed to set EF at VIL, E1P at VIL and E2P at VIH at the same time. PSRAM Write Enable (WP). The Write Enable input controls writing to the PSRAM memory array. W P is active low. PSRAM Output Enable (GP). The Output En- able gates the outputs through the data buffers during a Read operation of the PSRAM memory. G P is active low. PSRAM Upper Byte Enable (UBP). The Upper Byte Enable input enables the upper byte for PSRAM (DQ8-DQ15). UB P is active low. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable input enables the lower byte for PSRAM (DQ0-DQ7). LB P is active low. VDDF Supply Voltage.VDDF provides the power supply to the internal cores of the Flash memory component. It is the main power supply for all Flash operations (Read, Program and Erase). VDDP Supply Voltage. VDDP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM opera- tions. VDDQ Supply Voltage. VDDQ provides the power supply for the Flash Memory I/O pins. This allows all Outputs to be powered independently of the Flash Memory core power supply, VDDF . VPPF Program Supply Voltage. VPPF i s b o t h a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If V PPF is kept in a low voltage range (0V to VDDQ ) VPPF is seen as a control input. In this case a volt- age lower than VPPLKF gives an absolute protec- tion against Program or Erase, while VPPF > VPP1F enables these functions (see Tables 6 and 7, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If V PPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground refer- ence for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. Note: Each Flash memory device in a system should have their supply voltage (VDDF ) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance ca- pacitors should be as close as possible to the package). See Figure 6., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required V PPF program and erase currents.
Figure 4. Functional Block Diagram
16 Mbit
128 Mbit
Table 2. Main Operating modes
- LF can be tied to VIH if the valid address has been previously latched.
- WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R7000T0 datasheet for details.
M36L0R7040T0, M36L0R7040B0 FLASH MEMORY COMPONENT The M36L0R7040T0 and M36L0R7040B0 contain a 128 Mbit Flash memory. For detailed information on how to use the devices, see the M30L0R7000(T/B)0 datasheet which is available from the internet site http://www.st.com or from your local STMicroelectronics distributor. PSRAM COMPONENT The M36L0R7040T0 and M36L0R7040B0 contain a 16 Mbit PSRAM. For detailed information on how to use the device, see the M69AR024B datasheet which is available from the internet site http:// www.st.com or from your local STMicroelectronics distributor.
Table 3. Absolute Maximum Ratings and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Table 4. Operating and AC Measurement Conditions Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit Table 5. Device Capacitance Note: Sampled only, not 100% tested.
Table 6. Flash Memory DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.
- VDDF Dual Operation current is the sum of read and program or erase currents.
4 Word 7 16 mA
8 Word 10 18 mA
16 Word 13 20 mA
4 Word 16 18 mA
8 Word 18 20 mA
16 Word 21 25 mA
Table 7. Flash Memory DC Characteristics - Voltages Table 8. PSRAM DC Characteristics Note: 1. Average AC current, cycling at tAVAV minimum.
- E1P = VIL, E2P = VIH, UBP OR/AND LB P = VIL, VIN = VIH OR VIL.
Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline Note: Drawing is not to scale. Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
Table 10. Ordering Information Scheme Microelectronics Sales Office nearest to you.
M36L0R7040T0, M36L0R7040B0
REVISION HISTORY
Table 11. Document Revision History the ST ECOPACK specification. and revision 6.0 of M69AR024B datasheet. Document status promoted from Target Specification to full Datasheet.
M36L0R7040T0, M36L0R7040B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America