M36DR432A120ZA6C

M36DR432A STMICROELECTRONICS | Alldatasheet

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Technical content

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory

Figure 1. Packages

M36DR432A, M36DR432B

DESCRIPTION

The M36DR432 is a multichip memory device con- taining a 32 Mbit boot block Flash memory and a 4M b i to fS R A M .T h ed e v i c ei so f f e r e di naS t a c k e d LFBGA66 (0.8 mm pitch) package. The two components are distinguished by use with three chip enable inputs: EF for the Flash memory and, E1Sand E2S for the SRAM. The two compo- nents are also separately power supplied and grounded. Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. LFBGA Connections (Top view through package)

Table 2. Absolute Maximum Ratings(1)

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns.

Figure 4. Functional Block Diagram

32 Mbit (x16)

4 Mbit (x16)

M36DR432A, M36DR432B SIGNAL DESCRIPTIONS See Figure 2 and Table 1. Address Inputs (A0-A17).Addresses A0 to A17 are common inputs for the Flash chip and the SRAM chip. The address inputs for the Flash memory are latched during a write operation on the falling edge of the Flash Chip Enable (EF )o r Write Enable (WF), while address inputs for the SRAM array are latched during a write operation on the falling edge of the SRAM Chip Enable lines (E1S or E2S) or Write Enable (WS). Address Inputs (A18-A20).Address A18 to A20 are address inputs for the Flash chip. They are latched during a write operation on the falling edge of Flash Chip Enable (EF ) or Write Enable (WF). Data Input/Outputs (DQ0-DQ15).The input is data to be programmed in the Flash or SRAM memory array or a command to be written to the C.I. of the Flash chip. Both are latched on the ris- ing edge of Flash Chip Enable (EF )o rW r i t eE n - able (WF) and, SRAM Chip Enable lines (E1Sor E2S) or Write Enable (WS). The output is data from the Flash memory or SRAM array, the Elec- tronic Signature Manufacturer or Device codes or the Status register Data Polling bit DQ7, the Tog- gle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Flash Chip Enable (EF ) and Output Enable (GF)o r SRAM Chip Enable lines (E1Sor E2S) and Output Enable (GS) are active. The output is high imped- ance when the both the Flash chip and the SRAM chip are deselected or the outputs are disabled and when Reset (RPF )i sa taVIL. Flash Chip Enable (EF).The Chip Enable input for Flash activates the memory control logic, input buffers, decoders and sense amplifiers. EFat VIH deselects the memory and reduces the power con- sumption to the standby level and output do Hi-Z. EF c a na l s ob eu s e dt oc o n t r o lw r i t i n gt ot h ec o m - mand register and to the Flash memory array, while WF remains at VIL.I ti sn o ta l l o w e dt os e tE F at VIL,E 1 Sat VILand E2S at VIH at the same time. Flash Write Enable (WF). The Write Enable in- put controls writing to the Command Register of the Flash chip and Address/Data latches. Data are latched on the rising edge of WF Flash Output Enable (GF). The Output Enable gates the outputs through the data buffers during a read operation of the Flash chip. When GFand WF are High the outputs are High impedance. Flash Reset/Power Down Input (RPF).The RPF input provides hardware reset of the memory (without affecting the Configuration Register sta- tus), and/or Power Down functions, depending on the Configuration Register status. Reset/Power Down of the memory is achieved by pulling RPF to VILfor at least tPLPH . When the reset pulse is giv- en, if the memory is in Read, Erase Suspend Read or Standby, it will output new valid data in tPHQ7V1 after the rising edge of RPF.I ft h em e m o r yi si n Erase or Program modes, the operation will be aborted and the reset recovery will take a maxi- mum of t PLQ7V . The memory will recover from Power Down (when enabled) in tPHQ7V2 after the rising edge of RPF. See Tables 1, 26 and Figure 11. Flash Write Protect (WPF).Write Protect is an input to protect or unprotect the two lockable pa- rameter blocks of the Flash memory. When WPF is at VIL, the lockable blocks are protected. Pro- gram or erase operations are not achievable. When WPF is at VIH, the lockable blocks are un- protected and they can be programmed or erased (refer to Table 17). SRAM Chip Enable (E1S ,E 2 S ) .The Chip En- able inputs for SRAM activate the memory control logic, input buffers and decoders. E1S at VIH or E2S at VILdeselects the memory and reduces the power consumption to the standby level. E1Sand E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL.I t is not allowed to set EFat VIL,E 1 Sat VILand E2S at VIH at the same time. S R A MW r i t eE n a b l e( W S).The Write Enable in- put controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS).The Output Enable gates the outputs through the data buffers during a read operation of the SRAM chip. GSis active low. SRAM Upper Byte Enable (UBS).Enable the upper bytes for SRAM (DQ8-DQ15). UBSis active low. SRAM Lower Byte Enable (LBS). Enable the lower bytes for SRAM (DQ0-DQ7). LBSis active low. VDDF Supply Voltage (1.65V to 2.2V).Flash memo- ry power supply for all operations (Read, Program and Erase). V PPF Programming Voltage (11.4V to 12.6V). Used to provide high voltage for fast factory pro- gramming. High voltage on VPPF pin is required to use the Double Word Program instruction. It is also possible to perform word program or erase in- structions with V PPF pin grounded. VDDS Supply Voltage (1.65V to 2.2V).SRAM power supply for all operations (Read, Program). VSSF and VSSS Ground. VSSF and VSSS are the reference for all voltage measurements respec- tively in the Flash and SRAM chips.

Table 3. Main Operation Modes Note: X = VILor VIH,V PPFH =1 2 V±5 % .

1. If UBSand LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBSand LBS separately.

M36DR432A, M36DR432B FLASH MEMORY COMPONENT Organization The Flash Chip is organized as 2Mb x16 bits. A0- A20 are the address lines, DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable EF, Output Enable GFand Write En- able WF inputs. Reset RPFis used to reset all the memory circuitry and to set the chip in power down mode if this function is enabled by a proper setting of the Con- figuration Register. Erase and Program operations are controlled by an internal Program/Erase Con- troller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, DQ6 and DQ2 provide Toggle signals and DQ5 provides error bit to indicate the state of the P/E.C operations. Memory Blocks The device features asymmetrically blocked archi- tecture. The Flash Chip has an array of 71 blocks and is divided into two banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. The memory also fea- tures an erase suspend allowing to read or pro- gram in another block within the same bank. Once suspended the erase can be resumed. The Bank Size and Sectorization are summarized in Table 4. Parameter Blocks are located at the top of the memory address space for the Top version, and at the bottom for the Bottom version. The memory maps are shown in Tables 5, 6, 7 and 8. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. All blocks are protected at Power Up. In- structions are provided to protect or unprotect any block in the application. A second register locks the protection status while WPF is low (see Block Locking description). The Reset command does not affect the configuration of unprotected blocks and the Configuration Register status. Device Operations The following operations can be performed using the appropriate bus cycles: Read Array (Random, and Page Modes), Write command, Output Dis- able, Standby, Reset/Power Down and Block Locking. See Table 9. Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature, the Status Register, the CFI, the Block Protection Status or the Configuration Register status. Read operation of the memory array is per- formed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code are performed as single asynchronous read cycles (Random Read). Both Chip Enable EF and Output Enable GFmust be at VILin order to read the output of the memory. Write.Write operations are used to give Instruc- tion Commands to the memory or to latch Input Data to be programmed. A write operation is initi- ated when Chip Enable EFand Write Enable WF are at VILwith Output Enable GFat VIH.A d d r e s s - es are latched on the falling edge of WFor EF whichever occurs last. Commands and Input Data are latched on the rising edge of WF or EFwhich- ever occurs first. Noise pulses of less than 5ns typ- ical on EF,W F and GF signals do not start a write cycle. Dual Bank Operations.The Dual Bank allows to read data from one bank of memory while a pro- gram or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any delay. Status Register during Program or Erase must be monitored using an ad- dress within the bank being modified. Output Disable.The data outputs are high im- pedance when the Output Enable GF is at VIH with Write Enable WFat VIH. Standby. The memory is in standby when Chip Enable EF is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable GF or Write Enable WFin- puts. Automatic Standby.When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically en- ters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while out- puts still drive the bus. Power Down. The memory is in Power Down when the Configuration Register is set for Power Down and RPF is at VIL. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independent of the Chip Enable EF, Output Enable GFor Write Enable WF inputs. Block Locking.Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WPF to VIL(see Block Lock instruction).

Table 5. Bank A, Top Boot Block Addresses Table 6. Bank B, Top Boot Block Addresses

Table 7. Bank B, Bottom Boot Block Addresses Table 8. Bank A, Bottom Boot Block Addresses

Table 9. User Bus Operations(1) Table 10. Read Electronic Signature (AS and Read CFI instructions) Table 11. Read Block Protection (AS and Read CFI instructions) Table 12. Read Configuration Register (AS and Read CFI instructions)

55h at the address 2AAh during the second cycle. blocks of the same memory bank can be erased. gram data in another block, and then resumed. Command sequencing must be followed exactly. Table 13. Commands command set and some electrical specifications. changing the code after it has been written by ST. IL, while other address input are ignored.

M36DR432A, M36DR432B The bank address is don’t care for this instruction. The Electronic Signature can be read from the memory allowing programming equipment or ap- plications to automatically match their interface to the characteristics of Flash Chip. The Manufactur- er Code is output when the address lines A0 and A1 are at V IL, the Device Code is output when A0 is at VIH with A1 at VIL. The codes are output on DQ0-DQ7 with DQ8- DQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS instruction, A0 is set to VILwith A1 at VIH, while A12-A20 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. The AS Instruction finally allows the access to the Configuration Register status if both A0 and A1 are set to V IH. If DQ10 is '0' only the Reset function is active as RPFis set to VIL(default at power-up). If DQ10 is '1' both the Reset and the Power Down functions will be achieved by pulling RPFto VIL. The other bits of the Configuration Register are re- served and must be ignored. A reset command puts the device in read array mode. Write Configuration Register (CR) Instruc- tion.This instruction uses two Coded Cycles fol- lowed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the contents of address bits A0-A15 to the 16 bits configuration register. Bits written by inputs A0-A9 and A11-A15 are reserved for future use. Address input A10 defines the sta- tus of the Reset/Power Down functions. It must be set to V ILto enable only the Reset function and to VIH to enable also the Power Down function. At Power Up all the Configuration Register bits are reset to '0'. Enter Bypass Mode (EBY) Instruction.This in- struction uses the two Coded cycles followed by one write cycle giving the command 20h to ad- dress 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass (XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall pro- gramming time when large memory arrays need to be programmed. Exit Bypass Mode (XBY) Instruction.This in- struction uses two write cycles. The first inputs to the memory the command 90h and the second in- puts the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memo- ry Array mode. Program in Bypass Mode (PGBY) Instruc- tion.This instruction uses two write cycles. The Program command A0h is written to any Address on the first cycle and the second write cycle latch- es the Address on the falling edge of WF or EFand the Data to be written on the rising edge and starts the P/E.C. Read operations within the same bank output the Status Register bits after the program- ming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Program (PG) Instruction.This instruction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations within the same bank out- put the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Pro- gramming at an address not in blocks being erased is also possible during erase suspend. Double Word Program (DPG) Instruction.This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. High voltage (11.4V to 12.6V) on V PP pin is required. This instruction uses five write cy- cles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the ad- dress and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPG- BY) to skip the two coded cycles at the beginning of each command. Block Protect (BP), Block Unprotect (BU), Block Lock (BL) Instructions.All blocks are protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be pro- grammed or erased until a Block Unprotect in- struction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WPF pin, according to the following scheme: – when WPF is at VIH, the Lock status is overrid- den and all blocks can be protected or unpro- tected; – when WPF is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status, and pro- gram or erase accordingly;

M36DR432A, M36DR432B – the lock status is cleared for all blocks at power up; once a block has been locked state can be cleared only with a reset command. The protec- tion and lock status can be monitored for each block using the Autoselect (AS) instruction. Pro- tected blocks will output a ‘1’ on DQ0 and locked blocks will output a ‘1’ on DQ1. Refer to Table 14 for a list of the protection states. Block Erase (BE) Instruction.This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Cod- ed cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100µs. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the inter- nal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automati- cally before erasing to FFh. Read operations with- in the same bank, after the sixth rising edge of WF or EF, output the status register bits. During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is ac- cepted during the 100µs time-out period. Data Polling bit DQ7 returns '0' while the erasure is in progress and '1' when it has completed. The Tog- gle bit DQ6 toggles during the erase operation, and stops when erase is completed. After completion the Status Register bit DQ5 re- turns '1' if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to de- termine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. Bank Erase (BKE) Instruction.This instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command given is not an erase con- firm or if the Coded cycles are wrong, the instruc- tion aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of WF or EFoutput the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 re- turns '0', then '1' on completion. The Toggle bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an Erase Failure. Erase Suspend (ES) Instruction.In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in progress. It is also possible to program data in blocks not being erased. The Erase Suspend instruction consists of writing the command B0h without any specific address. No Coded Cycles are required. Erase suspend is accepted only during the Block Erase instruction execution. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended within 15µs after the Erase Suspend (ES) command has been writ- ten. The device will then automatically be set to Read Memory Array mode. When erase is sus- pended, a Read from blocks being erased will out- put DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instruc- tions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in DQ6 toggling when the data is being programmed. Erase Resume (ER) Instruction.If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank be- ing erased and without any Coded Cycle.

Table 14. Protection States(1) Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WPFstatus.

1. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by

D Q 1( =1f o ral o c k e db l o c k )a n dD Q 0( =1f o rap r o t e c t e db l o c k )a sr e a di nt h eA u t o s e l e c ti n s t r u c t i o nw i t hA 1=VIH a n dA 0=VIL.

1. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WPFhas
2. A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Table 15. Instructions(1,2) Read Memory Array until a new write cycle is initiated. Read CFI data until a new write cycle is initiated.

M36DR432A, M36DR432B Note: 1. Commands not interpreted in this table will default to read array mode. 2. For Coded cycles address inputs A11-A20 are don't care. 3. X = Don't Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com- mand cycles. 5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. 7. High voltage on VPPF (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction. XBY Exit Bypass Mode 2 Addr. XX Data 90h 00h PGBY Program in Bypass Mode 2 Addr. X Program Address Read Data Polling or Toggle Bit until Program completes. Data A0h Program Data DPGBY Double Word Program in Bypass Mode Addr. X Program Address 1 Program Address 2 Note 6, 7 Data 40h Program Data 1 Program Data 2 BP Block Protect 4 Addr. 555h 2AAh 555h Block Address Data AAh 55h 60h 01h BU Block Unprotect 1 Addr. 555h 2AAh 555h Block Address Data AAh 55h 60h D0h BL Block Lock 4 Addr. 555h 2AAh 555h Block Address Data AAh 55h 60h 2Fh BE Block Erase 6+ Addr. 555h 2AAh 555h 555h 2AAh Block Address Data AAh 55h 80h AAh 55h 30h BKE Bank Erase 6 Addr. 555h 2AAh 555h 555h 2AAh Bank Address Data AAh 55h 80h AAh 55h 10h ES Erase Suspend 1 Addr.(3) X Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase.Data B0h ER Erase Resume 1 Addr. Bank Address Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time Data 30h

tomatically sets bits DQ2, DQ5, DQ6 and DQ7. modified will output array data. program operation and to ‘0’ in Erase operation. Error Bit (DQ5).This bit is set to '1' by the P/E.C. Table 16. Polling and Toggle Bits

Table 17. Status Register Bits(1) Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

1. In case of double word program DQ7refers to the last word input.

7 Data

for Program or Erase Success.

6 Toggle Bit

5 Error Bit

4 Reserved

3 Erase Time

P/E.C. Erase operation has started.

2 Toggle Bit

to identify the erased block.

1 Program on-going or Erase

1 Reserved

0 Reserved

M36DR432A, M36DR432B POWER CONSUMPTION Power Down The memory provides Reset/Power Down control input RPF. The Power Down function can be acti- vated only if the relevant Configuration Register bit is set to '1'. In this case, when the RPFsignal is pulled at VSS the supply current drops to typically ICC2 (see Table 24), the memory is deselected and the outputs are in high impedance.If RPFis pulled to VSS during a Program or Erase operation, this operation is aborted in tPLQ7V and the memory content is no longer valid (see Reset/Power Down input description). Power Up The memory Command Interface is reset on Pow- er Up to Read Array. Either EFor WF must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of WF Supply Rails Normal precautions must be taken for supply volt- age decoupling; each device in a system should have the VCCF rails decoupled with a 0.1µF capac- i t o rc l o s et ot h eVCCF and VSS pins. The PCB trace widths should be sufficient to carry the required VCCF program and erase currents.

that can be read from the Flash memory device. software to configure itself when necessary. security number is written, starting at address 81h. Table 18. Query Structure Overview detailed in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs. Table 19. CFI Query Identification String Note: 1. Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 20. CFI Query System Interface Information

Table 21. Device Geometry Definition

1. x specifies the number of regions within the device containing one or more con-
2. By definition, symmetrically block devices have only one blocking region.

size. The value z = 0 is used for 128 byte block size.

M36DR432A, M36DR432B SRAM COMPONENT Device Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write Ar- ray, Output Disable, Power Down (see Table 3). Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable (WS )i sa tVIH with Output Enable (GS)a tVIL, and both Chip Enables (E1S and E2S) and UBS,L B Scombinations are asserted. Valid data will be available at the output pins within tAVQV after the last stable address, providing GSis Low, E1S is Low and E2S is High. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parame- ter (t E1LQV ,tE2HQV ,o rtGLQV ) rather than the ad- dress. Data out may be indeterminate at tE1LQX , tE2HQX and tGLQX , but data lines will always be val- id at tAVQV (see Table 31, Figures 16 and 17). Write.Write operations are used to write data in the SRAM. The SRAM is in Write mode whenever the WS and E1S pins are at VIL, with E2S at VIH. Either the Chip Enable inputs (E1Sand E2S) or the Write Enable input (WS) must be de-asserted during address transitions for subsequent write cy- cles. Write begins with the concurrence of both Chip Enables being active with WS at VIL.AW r i t e begins at the latest transition among E1Sgoing to VIL,E 2 Sg o i n gt oVIH and WS going to VIL. There- fore, address setup time is referenced to Write En- able and both Chip Enables as tAVWL ,tAVE1L and tAVE2H respectively, and is determined by the latter occurring edge. The Write cycle can be terminated b yt h er i s i n ge d g eo fE 1 S, the rising edge of WSor the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S=V IL,E 2 S = VIH and GS =V IL), then WSwill return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVE1H before the rising edge of E1Sor for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for t WHDX ,tE1HAX or tE2LAX (see Table 32, Figure 19, 21, 23). Standby/Power-Down. The SRAM chip has a Chip Enable power-down feature which invokes an automatic standby mode (see Table 31, Figure 18) whenever either Chip Enable is de-asserted (E1S =V IH or E2S=VIL). Data Retention The SRAM data retention performances as VCCS go down to VDR are described in Table 33 and Fig- ure 23, 24. In E1Scontrolled data retention mode, minimum standby current mode is entered when E1S ≥ VCCS – 0.2V and E2S ≤ 0.2V or E2S ≥ VCCS – 0.2V. In E2S controlled data reten- tion mode, minimum standby current mode is en- tered when E2S≤ 0.2V. Output Disable.The data outputs are high im- pedance when the Output Enable (GS )i sa tVIH with Write Enable (WS)a tVIH.

Table 24. DC Characteristics

and IDDR. If the device is read while in program suspend, current draw is the sum ofIDDWS and IDDR . Table 25. Flash Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. GF may be delayed by up to tELQV -tGLQV after the falling edge of EFwithout increasing tELQV

Figure 7. Flash Read AC Waveforms Note: Write Enable (WF) = High.

Figure 8. Flash Page Read AC Waveforms

Table 26. Flash Write AC Characteristics, Write Enable Controlled Figure 9. Flash Write AC Waveforms, WFControlled Note: 1. Address are latched on the falling edge of WF, Data is latched on the rising edge of WF.

Table 27. Flash Write AC Characteristics, Chip Enable Controlled Figure 10. Flash Write AC Waveforms, EFControlled Note: Address are latched on the falling edge of EF,D a t ai sl a t c h e do nt h er i s i n ge d g eo fE F.

Table 28. Flash Read and Write AC Characteristics, RPFRelated Figure 11. Flash Read and Write AC Waveforms, RPFRelated

Table 29. Flash Program, Erase Times and Program, Erase Endurance Cycles erase should perform significantly better.

1. Excludes the time needed to execute the sequence for program instruction.

Table 30. Flash Data Polling and Toggle Bits AC Characteristics(1) Note: 1. All other timings are defined in Read AC Characteristics table.

Figure 12. Flash Data Polling DQ7 AC Waveforms

Figure 13. Flash Data Toggle DQ6, DQ2 AC Waveforms Note: All other timings are as a normal Read cycle.

Figure 14. Flash Data Polling Flowchart Figure 15. Flash Data Toggle Flowchart

Table 31. SRAM Read AC Characteristics Note: 1. Sampled only. Not 100% tested. Figure 16. SRAM Read Mode AC Waveforms, Address Controlled with UBS=L B S=V IL Note: E1S= Low, E2S = High, GS=L o w ,W S= High.

Table 32. SRAM Write AC Characteristics Note: 1. tAS is measured from the address valid to the beginning of write.

1. tWR is measured from the end or write to the address change. tWR a p p l i e di nc a s eaw r i t ee n d sa sE 1 Sor WS going high.
2. tCW is measured from E1Sgoing low end of write.
3. A Write occurs during the overlap (tWP )o fl o wE 1 Sand low WS. A write begins when E1Sgoes low and WSgoes low with asserting

liest transition when E1Sgoes high and WSgoes high. The tWP is measured from the beginning of write to the end of write.

Table 34. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. Table 35. Daisy Chain Ordering Scheme vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 36. Revision History

Table 37. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data Figure 25. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline Note: Drawing is not to scale.

Figure 26. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)

Figure 27. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through

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