M36D0R6040T0 STMICROELECTRONICS | Alldatasheet
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Technical content
64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory
Figure 1. Package
Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . 15
(12 x 8mm, 8x8 ball array, 0.8mm pitch) package. (Restriction of Hazardous Substances) directive. Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. TFBGA Connections (Top view through package)
M36D0R6040T0, M36D0R6040B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names , for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A19).Addresses A0-A19 are common inputs for the Flash Memory and PSRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory internal state ma- chine and they select the cells to access in the PSRAM. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable (W F) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP). Address Inputs (A20-A21).Addresses A20-A21 are inputs for the Flash Memory component only. The Flash Memory is accessed through the Chip Enable signals ( EF) and through the Write Enable (W F) signal. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF). The Chip Enable in- puts activate the memory control logics, input buff- ers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the de- vice is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is re- duced to the standby level. Flash Output Enable (G F). The Output Enable pins control data outputs during Flash memory Bus Read operations. Flash Write Enable (W F). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR064F(T/B) datasheet). Flash Reset (RP F). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2 . Refer to Table 7., Flash Memory DC Characteristics - Cur- rents, for the value of IDD2 . After Reset all blocks are in the Locked state and the Configuration Reg- ister is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is re- quired to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to V RPH (refer to Table 8., Flash Memory DC Characteris- tics - Voltages). PSRAM Chip Enable (E1P).When asserted (Low), the Chip Enable, E1P, activates the memo- ry state machine, address buffers and decoders, allowing Read and Write operations to be per- formed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. PSRAM Chip Enable (E2P).The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode. PSRAM Output Enable (GP).The Output En- able, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. PSRAM Write Enable (WP).The Write Enable, W P, controls the Bus Write operation of the mem- ory’s Command Interface. PSRAM Upper Byte Enable (UB P).The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. PSRAM Lower Byte Enable (LB P).The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VDDF Supply Voltage.VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supplies for all Flash memory operations (Read, Program and Erase). VDDP Supply Voltage. The V DDP Supply Volt- age supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed. V PPF Program Supply Voltage. VPPF i s b o t h a Flash Memory control input and a Flash Memory power supply pin. The two functions are selected by the voltage range applied to the pin.
M36D0R6040T0, M36D0R6040B0 If VPPF is kept in a low voltage range (0V to VDDF ) VPPF is seen as a control input. In this case a volt- age lower than VPPLKF gives an absolute protec- tion against Program or Erase, while VPPF > VPP1F enables these functions (see Tables 7 and 8, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground refer- ence for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. Note: Each Flash memory device in a system should have its supply voltage (VDDF ) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capaci- tors should be as close as possible to the package). See Table 5., AC Measurement Load Circuit. The PCB track widths should be suffi- cient to carry the required VPPF program and erase currents.
which would result in a data bus contention. Figure 4. Functional Block Diagram
16 Mbit
64 Mbit
Table 2. Main Operating modes
- LF can be tied to VIH if the valid address has been previously latched.
- WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064F(T/B) datasheet for details.
M36D0R6040T0, M36D0R6040B0 FLASH MEMORY COMPONENT The M36D0R6040T0 and M36D0R6040B0 con- tain a 64Mbit Flash memory, the M58WR064F(T/ B). The burst mode of this device is not available in the M36D0R6040(T/B). For detailed information on how to use the Flash memory, see the M58WR064F(T/B) datasheet which is available from your local STMicroelec- tronics distributor. PSRAM COMPONENT The M36D0R6040T0 and M36D0R6040B0 con- tain a 16Mbit PSRAM. For detailed information on how to use it, see the M69AR024B datasheet which is available from the internet site http:// www.st.com or from your local STMicroelectronics distributor.
Table 3. Absolute Maximum Ratings Note: 1. VDDF = VDDP = VDD .
- Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Table 4. Operating and AC Measurement Conditions Note: 1. VDDF = VDDP = VDD . Figure 5. AC Measurement I/O Waveform Table 5. AC Measurement Load Circuit Table 6. Device Capacitance Note: Sampled only, not 100% tested.
Table 7. Flash Memory DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.
- VDDF Dual Operation current is the sum of read and program or erase currents.
Table 8. Flash Memory DC Characteristics - Voltages
Table 9. PSRAM DC Characteristics
- The minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, inputs may undershoot VSS by 1.0V for periods
Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline Note: Drawing is not to scale. Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data
Table 11. Ordering Information Scheme Microelectronics Sales Office nearest to you.
M36D0R6040T0, M36D0R6040B0
REVISION HISTORY
Table 12. Document Revision History Document status promoted from Target Specification to full Datasheet. TFBGA67 package fully compliant with the ST ECOPACK specification. datasheet and to the revision 6.0 of the M69AR024B datasheet.
M36D0R6040T0, M36D0R6040B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America