M35B32-WMC3TG

M35B32 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 44

Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Data output (Q)
• 2.2 Serial Data input (D)
• 2.3 Serial Clock (C)
• 2.4 Chip Select (S
• 2.5 Reset (RESET )
• 2.6 Write Protect (W )
• 2.7 V CC supply voltage
• 2.8 V SS ground
• 3 SPI modes
• 4 Operating features
• 4.1 An easy way to modify data
• 4.2 A fast way to store data
• 4.3 Polling during a write, program or erase cycle
• 4.4 Protection modes
• 5 Memory organization
• 6 Instructions
• 6.1 Write Enable (WREN)
• 6.2 Write Disable (WRDI)
• 6.3 Read Identification (RDID)
• 6.4 Read Status Register (RDSR)
• 6.4.1 WIP bit
• 6.4.2 WEL bit
• 6.4.3 BPi bits
• 6.5 Write Status Register (WRSR)
• 6.6 Read Data Bytes (READ)
• 6.7 Page Write (PW)

Features

• SPI bus compatible serial interface
• 32 Kbit of EEPROM divided into two sectors: – Data sector – Event sector
• Large page size: 256 bytes
• Fast programming: – Event sector: 256 bytes programmed in less than 1 ms – Data sector: 256 bytes written in less than 5 ms
• Low energy EEPROM in either Read, Write, Program or Erase modes
• 2.5 V to 5.5 V single supply voltage
• Operating temperature range:
• – 40°C to +85°C
• – 40°C to +125°C
• Operating frequency, fC = 20 MHz
• Electronic signature: 20 10 0Ch
• Data cycling: – Data sector: more than 1 Million write cycles – Event sector: more than 10 000 write cycles
• Data retention: – Data sector: more than 40 years’ data retention – Event sector: 1 year Packages
• SO8 ECOPACK®2
• TSSOP8 ECOPACK®2
• UFDFPN8 ECOPACK®2 SO8 (MN) 150 mil width UFDFPN8 (MC) 2 x 3 mm TSSOP8 (DW) 169 mil width

Table 4. Value of the WEL bit after decoding a Page Write, Page Program, Page Table 12. SO8N – 8-lead plastic small outline, 150 mils body width, Table 13. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch, Table 14. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitc h ultra thin profile fine pitch dual flat

1 Description

2.5 V associated with a low Programming current (the M35B32 is based on EEPROM cells,

energy-saving technology when compared to the Flash technology).

• the Data sector: standard EEPROM which can be written(a) by page (1 to 256 bytes at a time) with a standard write time and a standard retention time,
• the Event sector: data bytes which can be programmed(b) by page (1 to 256 bytes at a time) with a fast programming time and a limited retention time. The time required to update data is significantly reduced by the Page size (256 bytes) as a page is updated in a single shot. Both Data sector and Event sector can be erased either a page at a time (using the Page Erase instruction) or a sector at a time (using the Sector Erase instruction). The size of each sector is defined by the user.

Figure 1. Logic diagram

Figure 2. 8-pin package connections

1. See Package mechanical data section for package dimensions, and how to identify pin-1.

Table 1. Signal names

2 Signal description

During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 10). These signals are described below.

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S )

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

2.5 Reset (RESET )

The Reset (RESET) input provides a hardware reset for the memory. In this mode, the device is in Standby mode, the WEL and WIP bits are reset (to 0) and the outputs are high impedance. When Reset (RESET ) is driven high, the memory is in the normal operating mode. When Reset (RESET) is driven low, the memory will enter the Reset mode(c). c. If the M35A32 is executing a Write (pr program) cycle), the RESET pin driven active (low) does not stop an on going Program or Write cycle.

2.6 Write Protect (W )

This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is driven low (VIL), causing the Event sector to become read-only (by protecting them from write, program and erase operations). When Write Protect (W) is driven high (VIH), the 4 Kbytes of EEPROM memory can be accessed in Read and Write mode.

2.7 V CC supply voltage

VCC is the supply voltage. (See also Section 7 for more)

2.8 V SS ground

VSS is the reference for the VCC supply voltage.

3 SPI modes

• CPOL=0, CPHA=0
• CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 3, is the clock polarity when the bus master is in Standby mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. SPI modes supported

4 Operating features

4.1 An easy way to modify data

The Page Write (PW) instruction provides a convenient way of modifying data (1 up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence.

4.2 A fast way to store data

The Page Program (PP) instruction provides a fast way of modifying the data (1 up to 256 contiguous bytes at a time) in the Event sector, provided that these data bytes were erased (by the completion of an earlier Page Erase instruction). When addressing the Event sector (Sector 0, see Figure 5), the Page Program instruction is executed in a very short time (tFP, see Table 11), that is about 5 times faster than when executing a Page Program (or Page Write) instruction in the Data sector. To be correctly used, the Event sector has to be first erased. When an event occurs, data are programmed in the Event sector within a fast time. Later on, when the device receives less requests from the application, the contents of the Event sector can be copied/written into the Data sector (to benefit from the standard data retention time of 40 years), after what the Event sector content can be erased (using only one instruction: the Sector Erase instruction).

4.3 Polling during a write, program or erase cycle

A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (tPW, tPP, tPE, or tSE). The write in progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous cycle is complete.

4.4 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M35B32 features the following data protection mechanisms:

• Power on reset can provide protection against inadvertent changes while the power supply is outside the operating specification.
• Program, Erase and Write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
• All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the WEL bit (in the status register). This bit is returned to its reset state by the following events: –P o w e r - u p – Reset (RESET ) driven low – Write Disable (WRDI) instruction completion – Page Write (PW) instruction completion – Page Program (PP) instruction completion – Page Erase (PE) instruction completion – Sector Erase (SE) instruction completion
• The Hardware Protected mode is entered when Write Protect (W ) is driven low, causing the Event sector to become read-only. When Write Protect (W) is driven high, the 4 Kbytes of EEPROM memory can be accessed in Read and Write mode.
• The Reset (RESET) signal can be driven low to protect the contents of the memory during any critical time, not just during Power-up and Power-down. When driven active (low), the RESET pin does not stop an on going Program or Write cycle.

5 Memory organization

• The Data sector (standard EEPROM) is at the top,
• The Event sector (offering a fast programming time tFP) is at the bottom. The Event sector can be also write-protected with pin W. Both sectors can be erased in a single cycle, with the help of the Sector Erase instruction; however, each page can be erased using the Page Erase instructions (recommended for the Data sector).

Figure 5. Memory organization

1. N is defined by the BPi bits (see Section 6.4.3).

• programmed (bits are programmed from 1 to 0),
• erased (bits are erased from 0 to 1),
• written (bits are changed to either 0 or 1). When the Page Program instruction addresses bytes in the Data sector, the instruction is executed with the programming time tPP, when the Page Program instruction addresses bytes in the Event sector, the instruction is executed with the fast programming time tFP. !DDRESS &&&H %VENTSECTOR .PAGES CANBE WRITE PROTECTED $ATASECTOR n.PAGES THE%VENTSECTORISWRITE PROTECTED THE%VENTSECTORCANBEWRITTEN !DDRESS H .4W

Figure 6. Block diagram

6 Instructions

The instruction set is listed in Table 2. instruction, this might be followed by address bytes, or by data bytes, or by both or none. driven high after any bit of the data-out sequence is being shifted out. high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. (S) being driven low is an exact multiple of eight. Table 2. Instruction set

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. instruction code, and then driving Chip Select (S) high. Figure 7. Write Enable (WREN) instruction sequence

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit. instruction code, and then driving Chip Select (S) high.

• Power-up
• Write Disable (WRDI) instruction completion
• Page Write (PW) instruction completion
• Page Program (PP) instruction completion
• Page Erase (PE) instruction completion
• Sector Erase (SE) instruction completion

Figure 8. Write Disable (WRDI) instruction sequence

6.3 Read Identification (RDID)

first byte (58h), and the memory capacity of the device in the second byte (0Ch). not decoded, and has no effect on the cycle that is in progress. falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. any time during data output. Figure 9. Read Identification (RDID) instruction sequence and data-out sequence Table 3. Read Identification (RDID) data-out sequence

6.4 Read Status Register (RDSR)

the Status Register continuously, as shown in Figure 10.

• if W=0: Status Register = [0, 0, 0, 0, 0, 0, WEL, WIP]
• if W=1: Status Register = [0, 0, BP3, BP2, BP1, BP0, WEL, WIP] The status bits of the Status Register are as follows:

6.4.1 WIP bit

6.4.2 WEL bit

instruction is not executed. unless when /W is driven low when addressing the Event sector (see table4).

1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is

automatically set and reset by the internal logic of the device).

1. N is defined with BPi bits and (0 < N < 15): Page = 256 bytes.

6.4.3 BPi bits

the binary value of (BP3,BP2,BP1,BP0) (0 < N < 15). BPi bits also define the size of the write-protected area.

2 When W =0, the BPi bits cannot be read and the Status Register is read as [0, 0, 0, 0, 0, 0,

Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence

6.5 Write Status Register (WRSR)

executed, the device sets the Write Enable Latch (WEL). followed by the instruction code and the data byte on Serial Data input (D). The instruction sequence is shown in Figure 11. Chip Select (S) must be driven high after the eighth bit of the data byte has been latched in. some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset.

• If the Write Protect pin (W) is driven high, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction
• If the Write Protect pin (W) is driven low, attempts to write the Status Register are not executed (even if the Write Enable Latch (WEL) bit was previously set with a previous Write Enable instruction). As a consequence, the size and the write protection status of the Event sector (which size is defined by the (BP3, BP2, BP1, BP0) bits of the Status Register) cannot be modified.

Figure 11. Write Status Register (WRSR) instruction sequence

6.6 Read Data Bytes (READ)

R, during the falling edge of Serial Clock (C). sequence to be continued indefinitely. any effects on the cycle that is in progress. Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence

1. Address bits A15 to A12 are Don’t Care.

6.7 Page Write (PW)

As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. In the case of Figure 13, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts from the rising edge of Chip Select (S and continues for a period tPW (as specified in Table 11), at the end of which the Write in Progress (WIP) bit is reset to 0. However, if Chip Select (S) continues to be driven low, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 256 bytes). The instruction is not accepted, and is not executed, under the following conditions:

• If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
• If a write cycle is already in progress
• If the device has not been deselected, by Chip Select (S ) being driven high, at a byte boundary (after the eighth bit b0, of the last data byte that has been latched in)
• If the addressed page is in the region protected by the Block Protect (BP3, BP2, BP1, BP0) bits. Note: The self-timed write cycle t PW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “1” and a programmed bit is read as “0”. A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed. Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 13. Page Write (PW) instruction sequence

1. Address bits A15 to A12 are Don’t Care

6.8 Page Program (PP)

The Page Program instruction has be used when addressing erased bytes (see Note: below). The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must have been previously executed. (This sets the Write Enable Latch (WEL) bit). The Page Program (PP) instruction is entered by driving Chip Select (S ) low, followed by the instruction code, two address bytes and at least one data byte on Serial Data Input (D). The transmitted data must NOT exceed the addressed page boundary as a wrap round would corrupt the data from the start address of the same page. Chip Select (S ) must be driven low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. Chip Select (S) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven high, the self-timed Page Program cycle is initiated. The Page Program cycle lasts tPP when the Data sector is addressed, or tFP when the Event sector is addressed. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is at 1 during the self-timed Page Program cycle, and it is at 0 when the cycle is completed. The Write Enable Latch (WEL) bit is also reset (or not) once the self-timed Page Program cycle is complete, depending on the logical level applied on the W input pin and the value of the decoded address, as shown in Table 4. A Page Program (PP) instruction applied to a page that is Hardware Protected is not executed. Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Note: The Program instruction does not include an Erase cycle (unlike the Page Write instruction, which includes two cycles: Erase+ Program). As a consequence, the Page Program instruction has to be used only when pointing to locations which were previously erased. In addition, as the M35B32 offers the ECC feature (see Section 6.9), it is important to check, before programming data with the Page Program instruction, that the addressed bytes are inside an erased area defined as a multiple of four bytes. Example: to program data inside locations [003h-011h], the minimum erased area has to be [000h-013h], because location 003h belongs to the four bytes [000h-003h] and location 011h belongs to the four bytes [010h-013h].

Figure 14. Page Program (PP) instruction sequence

1. Address bits A15 to A12 are Don’t Care.

6.9 ECC (error correction code) and write cycling

4*N (where N is an integer) in order to benefit from the larger amount of Write cycles. writes to the device by multiples of 4-byte packets.

6.10 Page Erase (PE)

be erased before executing a Page Program instruction (fast programming time). low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Select (S) is driven high, the self-timed Page Erase cycle (whose duration is tPE) is initiated. address, as shown in Table 4). rejected without having any effects on the cycle that is in progress. Figure 15. Page Erase (PE) instruction sequence

1. Address bits A15 to A12 are Don’t Care.

6.11 Sector Erase (SE)

The M35B32 offers two sectors: the Data sector and the Event sector.

• when the transmitted address is inside the Event sector, the data in the Event sector are erased if the W pin is driven high
• when the transmitted address is inside the Data sector, the data in the top pages are erased (whatever the state of the W pin)
• when the transmitted address is above 1000h: no action Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable, the Sector Erase (SE) instruction is entered by driving Chip Select (S) low, followed by the instruction code, and two address bytes on Serial Data Input (D). Any address inside the Sector is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is at 1 during the self-timed Sector Erase cycle, and it is at 0 when the cycle is complete. The Write Enable Latch (WEL) bit is also reset (or not) once the self-timed Sector Erase cycle is complete, depending on the logical level applied on the W input pin and the value of the decoded address, as shown in Table 4. A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware Protected is not executed. Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 16. Sector Erase (SE) instruction sequence

1. Address bits A15 to A12 are Don’t Care.

M35B32 Power-up and power-down

7 Power-up and power-down

7.1 Supply voltage (V CC)

7.1.1 Operating supply voltage V CC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 6). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for write, program and erase instructions, until the completion of the internal write, program or erase cycle, respectively.

7.1.2 Power-up conditions

When the power supply is turned on, VCC continuously rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the S line to VCC via a suitable pull-up resistor. In addition, the Chip Select (S) input offers a built-in safety feature, as this input is edge- sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC rise time must not vary faster than 1 V/µs.

7.1.3 Internal r eset during power up

In order to prevent inadvertent write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At power-up, the device does not respond to any instruction until the V CC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 6). Until VCC has passed over the POR threshold, the device is reset, then the device is in the following state:

• Standby Power mode
• deselected (at next power-up, a falling edge is required on Chip Select (S) before any instruction can be started)
• Status register: – the Write Enable Latch (WEL) is reset to 0 – the Write In Progress (WIP) is reset to 0 The BP3, BP2, BP1 and BP0 bits of the Status Register are unchanged from the previous power down (they are non-volatile bits).

Power-up and power-down M35B32

7.1.4 Power-down

At power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device is reset and stops responding to any instruction sent to it. During power-down, the device must be deselected (the Chip Select (S ) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is, there should be no internal Write cycle in progress). As an extra protection, the Reset (RESET) signal can be driven low for the whole duration of the power-up and power-down phases.

8 Initial delivery state

Status Register are programmed with (BP3,BP2,BP1,BP0) = (0, 0, 0, 0).

9 Maximum rating

Table 5. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ®

10 DC and AC parameters

match the measurement conditions when relying on the quoted parameters.

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 17. AC measurement I/O waveform Table 6. Operating conditions (range 6) Table 7. Operating conditions (range 3) Table 8. AC measurement conditions

1. Sampled only, not 100% tested, at T A=25°C.

Table 9. Capacitance Table 10. DC characteristics(1)

1. Characterized only, not tested in production.

Table 11. AC characteristics

1. t CH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterizati on, not 100% tested in production.
3. t CLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be

equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

11.1 SO8N package information

Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width,

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted fr om mm and rounded to four decimal digits.

11.2 TSSOP8 package information

1. Values in inches are converted fr om mm and rounded to four decimal digits.

11.3 UFDFN8 package information

Figure 25. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch

1. Max. package warpage is 0.05 mm.
2. Exposed copper is not systematic and can appear parti ally or totally according to the cross section.

Table 14. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension b applies to plated terminal and is meas ured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Ex clude embedding part of exposed die paddle from mea-

12 Part numbering

prior to any decision to use these Engineering samples to run qualification activity. Table 15. Ordering information scheme

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

nearest ST sales office for a copy.

1. Used only for device grade 3.

Table 16. Document revision history 15-Mar-2011 1 Initial release. 24-May-2011 3 Status of document changed from Internal to Public. package recommended footprint.