M35080FP

M35080FP RENESAS | Alldatasheet

Document overview

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The M35080FP is a bitmap pattern display control IC can display on the screen. Display frequency can operate in 3.3MHz to 20MHz, and is equipped with the analog RGB output (512 colors / 260k colors) and the digital RGB output (512 colors) function. Moreover, 2 pages (horizontal 128 dot ✕ vertical 96 dots/page) display can be simultaneously performed on 1 screen.It uses a silicon gate CMOS process and it housed in a 24-pin shrink SOP package.

FEATURES

double-screen display (3 bits each of RGB) : 512 colors one-screen display (6 bits each of RGB) : 260 K colors one and double-screen display (3 bits each of RGB) : 512 colors

• Horizontal synchronous input frequency APPLICATION Liquid crystal display, Plasma display, Multi-scan monitor Outline 24P2Q-A PIN CONFIGURATION (TOP VIEW) MITSUBISHI MICROCOMPUTERS M35080FP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Rev.1.0 LP NC VDD2 ROUT/G2 GOUT/G1 BOUT/G0 IREF/B2 VG2/B1 VG1/B0 BIN V SS1 VSS2 AC CS SCK SIN TCK V DD1 P0/BLNK P1/R2 M35080FP P2/R1 P3/R0 VERT HOR

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Symbol LP VSS2 AC CS SCK SIN TCK V DD1 P0/BLNK P1/R2 P2/R1 P3/R0 HOR VERT V SS1 BIN VG1/B0 VG2/B1 IREF/B2 BOUT/G0 GOUT/G1 ROUT/G2 VDD2 NC Input/ Output Output Input Input Input Input Input Output Output Output Output Input Input Output Output Output Output Output Output Pin name Test output Earthing pin Auto-clear input Chip select input Serial clock input Serial data input External clock Power pin Port P0 output BLNK Port P1 output Port P2 output Port P3 output Horizontal synchro- nous signal input Vertical synchro- nous signal input Earthing pin Test pin Reference voltage output 1 Reference voltage output 1 Reference voltage output 2 Analog B signal output Analog G signal output Analog R signal output Power pin NC PIN DESCRIPTION Function Test pin. Open this pin. Connect to GND. When “L”, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor. This is the pin for chip select input. Set “L” level at serial data transmission. Hysteresis input. At CS pin is “L” level, SDA pin serial data is taken in when SCL rises. Hysteresis input. Built-in pull-up resistor. This is the pin for serial input of display control register and display RAM data. Also, this pin output acknowledge signal. Hysteresis input. Nch open-drain output. This is the pin for external clock input. Digital power supply. Connect to +3V with the power pin. This is a general purpose port output at analog RGB output. Outputs port output or BLNK signal. Outputs BLNK signal at digital RGB output. This is the output port output at analog RGB output. Outputs R2 signal at digital RGB output. This is the output port output at analog RGB output. Outputs R1 signal at digital RGB output. This is the output port output at analog RGB output. Outputs R0 signal at digital RGB output. Input horizontal synchronous signal. (Hysteresis input.) Input vertical synchronous signal. (Hysteresis input.) Connect to GND. Test pin. Connect to GND. Use reference voltage output 1 of DAC for analog RGB output at analog RGB output. Connect to capacitor. Output B0 signal at digital RGB output. Use reference voltage output 2 of DAC for analog RGB output at analog RGB output. Connect to capacitor. Output B1 signal at digital RGB output. The pin connects resistors which convert voltage current at analog RGB output. Output B2 signal at digital RGB output. Output analog B signal at analog RGB output(Current output). Connect to load resistance. Output G0 signal at digital RGB output. Output analog G signal at analog RGB output(Current output). Connect to load resistance. Output G1 signal at digital RGB output. Output analog R signal at analog RGB output(Current output). Connect to load resistance. Output G2 signal at digital RGB output. Digital power supply. Connect to +3V with the power pin. NC pin. Open.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS BLOCK DIAGRAM 6 8 234 SCK SIN V DD1 V DD2 Inputcontrolcircuit Datacontrolcircuit Displa y controlregister Read-outcontrolcircuit Displa y controlcircuit Shift register Displa y position detection circuit Synchronous signal switching circuitH counterPolality s witching circuit Output control circuit Port output control circuit Addresscontrolcircuit Timinggener ator AC V SS1 V SS2CS Bit map RAM (page A) Bit map RAM (page B) TCK 13HOR VER T P0/BLNK P1/R2 P2/R1 P3/R0 ROUT/G2 GOUT/G1 BOUT/G0 5 16 BIN 1LP 18(D AC) IREF/B2 VG /B1 VG /B0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS MEMORY CONSTITUTION Address 000016 to 000716 are assigned to the display RAM, ad- dress 100016 to 3AFF16 are assigned to bitmap RAM. The internal circuit is reset and all display control registers (address 000016 to 000716) are set to "0" when the AC pin level is "L". And then, bit map RAM is not erased and be undefinited. This memory has 2- page composition (an address is Page A and page B community) Fig.1 Memory constitution (Display Control register) DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 ––––– YM2 YM1 YM0 BLANK1 BLANK0 ALLON DSPON – WIDTH2 WIDTH1 WIDTH0 – VSIZE1VSIZE0 ––– VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 –––––– HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 – ANADIG2 ANADIG1 ANADIG0 SYNCCK TEST ––––– POLV POLH MODE2 MODE1 MODE0 –––––––– SBLANK3 SBLANK2 SBLANK1 SBLANK0 PTD3 PTD2 PTD1 PTD0 000016 000116 000216 000316 000416 000516 000616 000716 Address of the memory for page A, and the memory for page B. Registers PAGEONA and PAGEONB perform page control at the time of writing in data. For detail, refer to "DATA INPUT EXAMPLE". Memory constitution is shown in Figure 1 to 10. Note : Address 000016 and 000416 to 000716 are Page A and B common registers. The writing of data is made regardless of registers PAGEONA and PAGEONB. As for addresses 000116 to 000316, register of Page A and Page B exists for every page (common to an address.) When write data in the memory for page A, and write data in the memory for page B, set it as register PAGEONA = “1” at register PAGEONB = “1.” When both of PAGEONA and PAGEONB are set to “1”, data can be simultaneously written in both the memory for page A, and the memory for page B. Address 0XXX16 other than addresses 000016 to 000716 are write-protected.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 100016 100116 100216 100316 100416 100516 100616 100716 100816 100916 100A16 120616 120716 120816 12F916 12FA 16 12FB 16 12FC 16 12FD 16 12FE 16 12FF16 130016 13FF16 Address Fig.2 Memory constitution (Bit map RAM (R0)) Dot composition (DAF to DA0) at 128 dots ✕ 96 dots ……… ……… Bit map RAM (R0) data unused area Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 33 to 48 of line 1 Dot 49 to 64 of line 1 Dot 65 to 80 of line 1 Dot 81 to 96 of line 1 Dot 97 to 112 of line 1 Dot 113 to 128 of line 1 Dot 1 to 16 of line 2 Dot 17 to 32 of line 2 Dot 33 to 48 of line 2 Dot 81 to 96 of line 95 Dot 97 to 112 of line 95 Dot 113 to 128 of line 95 Dot 1 to 16 of line 96 Dot 17 to 32 of line 96 Dot 33 to 48 of line 96 Dot 49 to 64 of line 96 Dot 65 to 80 of line 96 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96 ……… Notes : Bit map RAM (Addresses 100016 to 3AFF16) has 2-page composition of the memory for page A, and the memory for page B. When write data in the memory for page A, and write data in the memory for page B, set it as register PAGEONA = “1” at register PAGEONB = “1.” When both of PAGEONA and PAGEONB are set to “1”, data can be simultaneously written in both the memory for page A, and the memory for page B.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 140016 140116 16FE 16 16FF16 170016 17FF16 Address ……… DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 180016 180116 1AFE 16 1AFF 16 1B0016 1FFF 16 Address ……… Bit map RAM (R1) data unused area unused area Bit map RAM (R2) data Fig.3 Memory constitution (Bit map RAM (R1)) Fig.4 Memory constitution (Bit map RAM (R2)) Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96 Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 200016 200116 22FE 16 22FF16 230016 23FF16 Address Fig.5 Memory constitution (Bit map RAM (G0)) ……… Bit map RAM (G0) data unused area DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 240016 240116 26FE 16 26FF16 270016 27FF16 Address Fig.6 Memory constitution (Bit map RAM (G1)) ……… Bit map RAM (G1) data unused area DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 280016 280116 2AFE 16 2AFF 16 2B0016 2FFF 16 Address Fig.7 Memory constitution (Bit map RAM (G2)) ……… Bit map RAM (G2) data unused area Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96 Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96 Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 300016 300116 32FE 16 32FF16 330016 33FF16 Fig.8 Memory constitution (Bit map RAM (B0)) ……… Bit map RAM (B0) data unused area DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 340016 340116 36FE 16 36FF16 370016 37FF16 Address Fig.9 Memory constitution (Bit map RAM (B1)) ……… Bit map RAM (B1) data unused area DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 380016 380116 3AFE 16 3AFF 16 3B0016 3FFF 16 Address Fig.10 Memory constitution (Bit map RAM (B2)) ……… Bit map RAM (B2) data unused area Address Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96 Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96 Dot composition (DAF to DA0) at 128 dots ✕ 96 dots Dot 1 to 16 of line 1 Dot 17 to 32 of line 1 Dot 81 to 96 of line 96 Dot 97 to 112 of line 96

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 00016 00116 00216 00316 00416 00516 00616 00716 00816 00916 00A16 00B16 00C16 00D16 00E16 00F16 01016 01116 01216 01316 01416 01516 01616 01716 01816 01916 01A16 01B16 01C16 01D16 01E16 01F16 02016 02116 02216 02316 02416 02516 02616 02716 02816 02916 02A16 02B16 02C16 02D16 02E16 02F16 2D016 2D1 16 2D2 16 2D316 2D416 2D516 2D616 2D7 16 2D816 2D9 16 2DA 16 2DB16 2DC16 2DD16 2DE16 2DF 16 2E016 2E2E6 2E216 2E316 2E416 2E516 2E616 2E716 2E816 2E916 2EA 16 2EB16 2EC16 2ED16 2EE16 2EF 16 2F016 2F116 2F216 2F316 2F416 2F516 2F616 2F716 2F816 2F916 2FA 16 2FB16 2FC16 2FD16 2FE16 2FF16 * The numerical value in a thick frame corresponds to lower 10-bits of bit map RAM (R0 to R2, G0 to G2, B0 to B2) address. (n RAM character number : 0 to 7) 1 to 16 17 to 32 33 to 48 49 to 64 65 to 80 81 to 96 97 to 112113 to 128Lines Dots 00016 00116 00216 00316 00416 00516 00616 00716 00816 00916 00A16 00B16 00C16 00D 16 00E16 00F16 01016 01116 01216 01316 01416 01516 01616 01716 2E816 2E916 2EA 16 2EB16 2EC16 2ED 16 2EE 16 2EF16 2F016 2F116 2F216 2F316 2F416 2F516 2F616 2F716 2F816 2F916 2FA 16 2FB16 2FC16 2FD 16 2FE 16 2FF16 187 188 189 190 191 192 1 to 16 17 to 32 33 to 48 49 to 64Lines Dots Pixel composition Each bit of a bit map display consists of nine bit map RAM (R0 to R2, G0 to G2, and B0 to B2.) Color setup can be specified out of 512 kinds per dot. The bit map RAM address corresponding to dot composition in case pixel composition is 128 dot x 96 dot is shown in Fig. 11. And, the bit map RAM address corresponding to dot composition in case pixel composition is 64 dot x192 dot is shown in Fig. 12. In other pixel composition, the bit map RAM is similarly assigned in an order from the dots 1 to 16 of line 1. Fig.11 Pixel composition (at 128 dots ✕ 96 dots) * The numerical value in a thick frame corresponds to lower 10-bits of bit map RAM (R0 to R2, G0 to G2, B0 to B2) address. (n RAM character number : 0 to 7) Fig.12 Pixel composition (at 64 dots ✕ 192 dots)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Writing to the memory(display control registers and Bit map RAM) for page A is disapproval. Writing to the memory(display control registers and Bit map RAM) for page A is permission. Writing to the memory(display control registers and Bit map RAM) for page B is disapproval. Writing to the memory(display control registers and Bit map RAM) for page B is permission. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Register Address 0000 A B C D E F RegisterDA Function

Contents

Memory writing control for page A. Memory writing control for page B. PAGEONA PAGEONB

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Address 000116 A B C D E F RegisterDA Function Set "0" to this bit. Can not be used. Display OFF Display ON Set "0" to this bit. Can not be used. when set to R < 0, R = 0. Same as G output and B output. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set the pixel composition. The BLNK signal of the range set up by this register is outputted at the time of BLANK1, 0 = 0, and 0 (normal) setup. The measure against a character bend (test bit) Control of blank signal. (a blank setup in a bit unit is possible). Note 2 Control of R, G and B output luminosity WIDTH0 WIDTH1 WIDTH2 DSPON BLANK0 BLANK1 YM0 YM1 YM2 WIDTH2 WIDTH1 WIDTH0 Pixel (Horizontal ✕ Vertical) 0 0 0 128 ✕ 96 dots 0 0 1 192 ✕ 64 dots 0 1 0 256 ✕ 48 dots 0 1 1 384 ✕ 32 dots 100 3 2 ✕ 384 dots 101 4 8 ✕ 256 dots 110 6 4 ✕ 192 dots 111 9 6 ✕ 128 dots BLANK1 BLANK0 Blank signal

00 Normal(Control by register WIDTH 0 to 2)

0 1 Control by Bit map RAM(R0) 1 0 Control by Bit map RAM(G0) 1 1 Control by Bit map RAM(B0) R = Σ 2nR n – Σ 2nYM n n = 0 n = 0 Notes 1 : This register is consisted of 2 pages (address community) of the register for page A, and the register for page B. Writing control to each page is performed by registers PAGEONA and PAGEONB (address 000016). 2 : The bit map RAM used for blank signal control is not applicable to color setup.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Address 000216 RegisterDA Status If VS is the vertical display start location, VS = H ✕ 2nVP n H: Cycle with the horizonal synchronizing pulse Setting vertical start location .It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. Σ n = 0 A B C D E F Notes 1 : This register is consisted of 2 pages (address community) of the register for page A, and the register for page B. Writing control to each page is performed by registers PAGEONA and PAGEONB (address 000016). 2 : Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "1FF16" (blank without background) for the display RAM of the part which the display range exceeds. Setting vertical direction dot size It should be fixed to "0". Can not be used. VSIZE1 VSIZE0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H : Synchronous of horizontal direction pulse Display area Note 2 Note 2 HS VS HOR VERT Note 2 Note 2 Monitor display

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Address 000316 A B C D E F RegisterDA Function It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. If HS is the horizontal display start location, HS = T ✕ 2nHP n T: Display clock Setting horizontal start location Σ n = 0 Display area Note 2 Note 2 HS VS HOR VERT Note 2 Note 2 Monitor display Notes 1 : This register is consisted of 2 pages (address community) of the register for page A, and the register for page B. Writing control to each page is performed by registers PAGEONA and PAGEONB (address 000016). 2 : Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "1FF16" (blank without background) for the display RAM of the part which the display range exceeds.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Address 000416 A B C D E F RegisterDA Function Set "0" to this bit. Can not be used. HOR pin is negative polarity HOR pin is positive polarity VERT pin is negative polarity VERT pin is positive polarity Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. It synchronizes with a display CK rising and is port output (at the time of digital output setup). It synchronizes with a display CK falling and is port output (at the time of analog output setup). Port P1 to P3 output (at the time of analog RGB output setup "L" fixation) R0 to R2 output (at the time of digital RGB output setup "H" fixation) Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. MODE0 MODE1 POLH POLV TEST SBLANK0 SBLANK1 PTC13 Polarity of HOR pin Polarity of VERT pin Test bit BLNK signal output timing control (BLNK signal). Effective at the time of SBLANK1, 2 = 1, and 1 (BLNK output) setup. P0/BLNK pin output control. SBLANK2 : address 000716 P1 to P3 output control MODE1 Display mode Priority is given to Page A Priority is given to Page B

260 K colors display

The average of Page A and Page B MODE0 SBLANK1 P0/BLNK pin output Port P0 output Can not be used Can not be used BLNK output SBLANK2

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Address 000516 A B C D E F RegisterDA Function Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Address 000616 A B C D E F RegisterDA Function Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. DAC OFF (at the time of digital RGB output setup "L" fixation) Digital RGB output mode (G0 to G2, B0 to B2 signal output) DAC ON (at the time of analog RGB output setup "H" fixation). Analog RGB output mode (VG1, VG2, IREF, ROUT, GOUT, and BOUT signal output) Set "0" to this bit. Can not be used. DACON DAC ON/OFF, and digital RGB/analog RGB output change

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Address 000716 A B C D E F RegisterDA Function "L" fixation at port output, negative polarity at BLNK output. "H" fixation at port output, positive polarity at BLNK output. "L" fixation at port output. "H" fixation at port output. "L" fixation at port output. "H" fixation at port output. "L" fixation at port output. "H" fixation at port output. Refer to SBLANK1(0004 16). Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. Set "0" to this bit. Can not be used. PTD0 PTD1 PTD2 PTD3 SBLANK2 Data control of P0 pin Data control of P1 pin Data control of P2 pin Data control of P3 pin Output control of P0/BLNK pin

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 13 The example of a display at the time of a 2-page display DISPLAY FORM M35080FP can display two pages, Page A and Page B, simulta- neously, as shown in Figure 13. And,1 page of 260K color display can be displayed by piling up two pages completely. Page A: register PAGEONA (address 000016) Set up by = "1." Page B: register PAGEONB (address 000016) Set up by = "1." Example 1 Example 2 Page A (128 dots ✕ 96 dots) Page A (128 dots ✕ 96 dots) Page B (128 dots ✕ 96 dots) Monitor display Monitor display Page B (128 dots ✕ 96 dots) Notes 1: Setup of display position, display size, etc. can be freely performed for every page. Two pages can be displayed side by side vertically and horizon tally. 2: when the display area of two pages overlaps on the monitoring screen, registers MODE0 and MODE1 (address 000416) can perform four displays as follows. RGB output is 6-bit(Note 2)each setup. (4) The average of Page A and Page B ... The overlaped part averages and outputs the RGB output of two pages. Notes 1. It becomes 512 color displays at the time of digital RGB output setup. 2. Assignment of 6 bits each of RGB is as follows. MODE1 Display mode Priority is given to Page A Priority is given to Page B

260 K colors display(Note 1)

The average of Page A and Page B MODE0 Display number of pages 2 pages 2 pages 1 page 2 pages MSB LSB R R2 Page A R1 R0 R2 Page B R1 R0 G G2 Page A G1 G0 G2 Page B G1 G0 B B2 Page A B1 B0 B2 Page B B1 B0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DATA INPUT EXAMPLE Data of Bit map RAM and display control registers can be set by the 16-bit serial input function. Example of data setting is shown in Figure 14. Fig. 14 Example of data setting DA0 DA1DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2Address/Data Remarks 000 000000000000 0 000000000000001 1 000000000000000 0 000000000000000 0 000000000000000 1

0 VSIZE1 VSIZE0 0 0 0 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0

000000 H P 9 H P 8 H P 7 H P 6 H P 5 H P 4 H P 3 H P 2 H P 1 H P 0

0000000000 0 POLV POLH MODE2 MODE1 MODE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 SBLANK 3 SBLANK 2 SBLANK 1 SBLANK 0 PTD3 000100000000000 0 Bit map RAM (Page A) (R0,R1,R2,G0,G1,G2,B0,B1,B2) Bit map RAM (PageB) (R0,R1,R2,G0,G1,G2,B0,B1,B2) 000000000000000 0 000000000000001 0 Page A and B writing setting (Note 1) Page A and B writing setting Page A writing setting Page B writing setting Display form setting DAC setting Port output setting Address setting Address setting Address setting Address setting Display ON Bit map setting Vertical display location setting Horizontal display location setting Page A Vertical display location setting Horizontal display location setting Page BPage B Bit map setting Page A Address 000016 Data 000016 Data 000116 Address 000016 Data 000716 Data 000616 Data 000516 Data 000416 Data 000316 Data 000216 Data 000016 Address 100016 Data 100116 Data 100016 Data 3AFF16 Data 3AFE16 Address 000016 Address 100016 Address 000016 Data 000116 Data 000016 Data 3AFF16 Data 3AFF16 Data 100116 Data 100016 Data 000316 Data 000216 Data 000016 Notes 1. Registers PAGEONA and PAGEONB perform writing control of data. 2. Input the clock with which the cycle was fixed and continued from the TCK pin. Moreover, input horizontal synchronized signal into HOR pin,

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig.15 Example of the M35080FP peripheral circuit (at analog RGB output setting) Fig.16 Example of the M35080FP peripheral circuit (at digital RGB output setting) LP V SS2 AC CS SCK SIN TCK V DD1 P0/BLNK P1/R2 NC VDD2 ROUT/G2 GOUT/G1 BOUT/G0 IREF/B2 VG2/B1 VG1/B0 BIN VSS1 +3V +3V R G B + — — + M35080FP P2/R1 P3/R0 VERT HOR BLANK 100 F 0.01 F 100 F 0.01 F 1 F Synchronous signal generator Microcomputer External clock Horizontal synchronors signal (3V) Vertical synchronors signal (3V) Mixing video pre-amp 0.1 F 0.1 F 1.2K‰ 300‰ Output buffer 100µF 1µF 0.01µF 100µF 1µF 0.01µF 1µF Synchronous signal generator Microcomputer External clock Horizontal synchronors signal (3V) Vertical synchronors signal (3V) Mixing video pre-amp LP V SS2 AC CS SCK SIN TCK V DD1 P0/BLNK P1/R2 NC VDD2 ROUT/G2 GOUT/G1 BOUT/G0 IREF/B2 VG2/B1 VG1/B0 BIN VSS1 +3V +3V + – – + M35080FP P2/R1 P3/R0 VERT HOR BLANK

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DATA INPUT SERIAL DATA INPUT TIMING (1) Serial data should be input with the LSB first. (2) The address consists of 16 bits. (3) The data consists of 16 bits. (4) The 16 bits in the SCK after the CS signal has fallen are the address, and for succeeding input data, the address is incremented every 16 bits. Therefore, it is not necessary to input the address from the second data. Fig.17 Serial input timing Address(16 bits) Data(16 bits) N Data(16 bits) N + 1 CS N = 1,2,3……… SCK SIN LSB MSB LSB MSB LSB MSB

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS TIMING REQUIREMENTS (VDD = 3 ± 0.30 V, Ta = –20 to +85°C, unless otherwise noted) Serial data input Fig.18 Serial input timing ns ns µs ns ns µs Parameter Limits Max. 200 200 200 200 Typ. Max. Unit Remarks Refer to fig 18 Symbol tw(SCK) ___ tsu(CS) ___ th(CS) tsu(SIN) th(SIN) tword SCK width ____ CS setup time ____ CS hold time SIN setup time SIN hold time 1 word write time tsu(CS) tw(SCK) tw(SCK) tsu(SIN) th(SIN) th(CS) tw(CS) 1µs (min.) tword more than 2 µs 1 2 12 13 14 15 16… 1 1 21 31 41 51 6… CS SCK SIN SCK CS

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Parameter Supply voltage Supply current (at analog output) “H” level output voltage “L” level output voltage Pull-up resistance AC External clock input width Full scale width Nonlinear nature error Symbol VDD VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to V SS . Ta = +25 °C Ratings –0.3 to +4.2 VSS –0.3 ≤ VI ≤ VDD +0.3 VSS ≤ VO ≤ VDD +70 –20 to +85 –40 to +125 Unit V V V mW Min. 2.7 0.8 ✕ VDD 10.0 10.0 Typ. 3.00 VDD Max. 3.3 VDD 0.2 ✕ VDD 20.0 20.0 Unit V V V MHz kHz Supply voltage "H" level input voltage "L" level input voltage Oscillating frequency for display Horizontal synchronous signal input frequeney VDD VIH VIL FOSC H.sync __ __ SIN, SCK, CS, AC, HOR, VERT __ __ SIN, SCK, CS, AC, HOR, VERT Min. 2.70 2.2 0.7 ✕ VDD Typ. 3.00 1.0 Max. 3.30 0.5 100 VDD ±2.0 Unit V mA V V kΩ V Vp-p LSB Test conditions Ta = –20 to +70°C VDD = 3.00V VDD = 2.70V, IOH = –1mA VDD = 2.70V, IOL = 1mA VDD = 3.00V R IREF=1.2KΩ , R L=300Ω R IREF=1.2KΩ , R L=300Ω VDD IDD VOH VOL R I VTCK VDAO N L P0 to P7,R0 to R2 G0 to G2,B0 to B2 P0 to P7,R0 to R2 G0 to G2,B0 to B2 ROUT,GOUT,BOUT ROUT,GOUT,BOUT ABSOLUTE MAXIMUM RATINGS (VDD = 3.00V, Ta = –20 to +85°C, unless otherwise noted) RECOMMENDED OPERATING CONDITIONS (VDD = 3.00V, Ta = –20 to +85°C, unless otherwise noted) ELECTRICAL CHARACTERISTICS (VDD = 3.00V, Ta = 25°C, unless otherwise noted) Symbol LimitsParameter LimitsSymbol

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig.19 Timing of power supplying to AC pin NOTE FOR SUPPLYING POWER (1) Timing of power supplying to AC pin The internal circuit of M35080FP is reset when the level of the auto clear input pin AC is “L”. This pin in hysteresis input with the pull-up resistor. The timing about power supplying of AC pin is shown in Figure be- low. After supplying the power (V DD and VSS ) to M35080FP and the supply voltage becomes more than 0.8 ✕ VDD , it needs to keep VIL time; tw of the AC pin for more than 1ms. Start inputting from microcomputer after AC pin supply voltage becomes more than 0.8 ✕ VDD and keeping 200ms wait time. PRECAUTION FOR USE Notes on noise and latch-up In order to avoid noise and latch-up, connect a bypass capacitor (≈0.1µF) directly between the V DD1 pin and VSS1 pin, and the VDD2 pin and VSS2 pin using a heavy wire. Notes on the time of external clock input to TCK pin Input the continuous external clock which cycle is fixed and syn- chronized with horizontal synchronized signal from TCK pin. And, input continuous horizontal synchronized signal which cycle is fixed from HOR pin. Do not stop clock input absolutely during dis- play. (2) Timing of power supplying to VDD1 and VDD2 . Supply power to VDD1 and VDD2 at the same time. VDD 0.8 ✕ VDD 0.2 ✕ VDD tW tS Voltage [V] Supply voltage Time t [s] Data input disable VAC (AC pin input voltage)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS SSOP24-P-300-0.80 Weight(g) JEDEC Code 0.2 Cu Alloy 24P2Q-A Plastic 24pin 300mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .30 .180 .010 .25 .57 .40 .271 .10 .81 .350 .20 .110 .35 .80 .87 .60 .251 .627 .20 .12 .450 .250 .210 .45 .18 .80 .10 b2 –. 5 0– 0° –8 ° e 24 13 121 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F –Z1 0.65 0.8 z Detail G z b G MMP PACKAGE OUTLINE

© 2002 MITSUBISHI ELECTRIC CORP. New publication, effective MAR. 2002. Specifications subject to change without notice. Notes regarding these materials  These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.  Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.  All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).  When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.  Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.  The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.  If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.  Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!  Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

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