M35080 STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M35080
8 Kbit Serial SPI Bus EEPROM
With Incremental Registers ■ Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) ■ Single Supply Voltage: 4.5 V to 5.5 V ■ 5 MHz Clock Rate (maximum) ■ Sixteen 16-bit Incremental Registers ■ BYTE and PAGE WRITE (up to 32 Bytes) (except for the Incremental Registers) ■ Self-Timed Programming Cycle ■ Hardware Protection of the Status Register ■ Resizeable Read-Only EEPROM Area ■ Enhanced ESD Protection ■ 1 Million Erase/Write Cycles (minimum) ■ 40 Year Data Retention (minimum)
DESCRIPTION
The M35080 device consists of 1024x8 bits of low power EEPROM, fabricated with STMicroelectronics’ proprietary High Endurance Double Polysilicon CMOS technology. The device is accessed by a simple SPI-compati- ble serial interface. The bus signals consist of a serial clock input (C), a serial data input (D) and a serial data output (Q), as shown in Table 1. The device is selected when the chip select input ) is held low. Data is clocked in during the low to high transition of the clock, C. Data is clocked out during the high to low transition of the clock. Figure 1. Logic Diagram Table 1. Signal Names
Figure 2. DIP and SO Connections Note: 1. NC = Not Connected. Table 2. Absolute Maximum Ratings 1 other relevant quality documents.
- EIAJ IC-121 (Condition C) (200pF, 0W).
The memory is organized in pages of 32 bytes. accepted if it is greater than the current value. an electricity meter, or a tally for remaining credit). latched on the rising edge of the serial clock. quired prior to the start of any operation.
Figure 3. Data and Clock Timing set or reset by the device’s internal logic). the Status Register Write Disable bit (SRWD). the WREN instruction (Write Enable Latch). Hardware Protected Mode (HPM). Mode, once entered, is to pull high the W pin. the application, W is read as a logical '0'. Table 3. Write Protection Control Table 4. Status Register Format
- UV, INC, WEL, WIP: Read only bits.
- SRWD: Read and Write bit.
must have been previously selected (S held low). Figure 4. EEPROM and SPI Bus Table 5. Instruction Set
– WRITE instruction completion. and a ’0’ that no write is in progress. status of the write enable latch. It, too, is read-only. ing Write instructions will be ignored). Figure 5. Read EEPROM Array Operation Sequence Note: 1. The most significant address bits, A15-A10, are treated as Don't Care. Table 6. Memory Mapping
writes any previously written data. byte has been received, as shown in Figure 12. – The WEL bit is reset at power-up. programming cycle continues unaffected. Figure 10. Write Data to Incremental Registers (WRINC) Note: 1. The most significant address bits, A15-A10, are treated as Don't Care.
Figure 11. Block Diagram Note: 1. An is the top address of the memory.
32 Bytes
down (they are non-volatile bits). ‘0’s, and hence the first 16 words at 0000h. for bit b4, which is set to ‘1’, as shown in Table 8. Figure 12. Page Write Operation Sequence Note: 1. The most significant address bits, A15-A10, are treated as Don't Care.
- The number of clock pulses must be a multiple of 8. Otherwise, the write is aborted.
Table 8. Initial Status Register Format
Table 9. DC Characteristics Note: 1. The device meets output requirements for both TTL and CMOS standards.
- Test performed at –40 to 125°C temperature range, Grade 3.
Table 10. Input Parameters 1 Note: 1. Sampled only, not 100% tested. Table 11. AC Measurement Conditions Figure 13. AC Testing Input Output
Table 12. AC Characteristics
- Value guaranteed by characterization, not 100% tested in production.
Table 13. Ordering Information Scheme
ORDERING INFORMATION
The notation used for the device number is as shown in Table 13. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Figure 16. PSDIP8 (BN) Note: 1. Drawing is not to scale. Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width Figure 17. SO8 narrow (MN) Note: 1. Drawing is not to scale.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com