M35076 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The M35076-XXXSP is a character pattern display control IC can display on the digital camera, the digital video, the digital televi- sion, the CRT display, the liquid crystal display and the plasma display. It can display 2 pages ( 24 characters × 12 lines per 1 page) at the same time. It uses a silicon gate CMOS process and it housed in a 20-pin shrink DIP package (M35076-XXXSP). For M35076-001SP that is a standard ROM version of M35076- XXXSP respectively, the character pattern is also mentioned.

FEATURES

1 page:256 characters

  • Display locations available Cycle : division of vertical synchronization signal into 32 or 64 Duty : 25%, 50%, or 75%
  • Coloring for ROM character Specified by register Specified by register
  • Blanking Character size blanking Border size blanking Matrix-outline blanking All blanking (all raster area)
  • Output ports 8 shared output ports (toggled between RGB output)
  • Display RAM erase function
  • Display oscillation stop function <VDD=5V>
  • Display input frequency range OSC = 6.3 MHz to 80.0 MHz
  • Horizontal synchronous input frequency <VDD=3V>
  • Display input frequency range OSC = 6.3 MHz to 40 MHz
  • Horizontal synchronous input frequency APPLICATION Digital camera, Digital video, Digital television, CRT display, Liquid crystal display, Plasma display PIN CONFIGURATION (TOP VIEW) Outline 20P4B Rev.1.0 MITSUBISHI MICROCOMPUTERS M35076-XXXSP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS CPOUT ← VDD2 ← VERT ← HOR → P5/B0 → P4/G1 → P3/G0 → P2/R1 → P1/R0 → P0/BLNK0 VSS1 VSS2 AC → CS → SCK/SCL → SIN/SDA ↔ TCK → VDD1 P6/B1 ← P7/BLNK1 ← M35076 - XXXSP

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Symbol CPOUT VSS2 AC CS SCK/SCL SIN/SDA TCK VDD1 P6/B1 P7/BLNK1 VSS1 P0/BLNK0 P1/R0 P2/R1 P3/G0 P4/G1 P5/B0 HOR VERT V DD2 Input/ Output Output Input Input Input Input I/O Input Output Output Output Output Output Output Output Output Input Input Function Filter output. Connect loop filter to this pin. Connect to GND. When “L”, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor. <at the 16-bit serial communication> Chip select pin. Set this pin to "L" level at serial data transfer. Hysteresis input. Built-in pull-up resistor. <at the I 2C-BUS serial communication> Set this pin to “H ” level. <at the 16-bit serial communication> _____ SIN pin serial data is taken in when SCK rises at CS pin "L" level. Hysteresis input. <at the I 2C-BUS serial communication> SDA pin serial data is taken in synchronized with SCL. <at the 16-bit serial communication> This is the pin for serial input of display control register and display RAM data. Hysteresis input. <at the I 2C-BUS serial communication> Hysteresis input. This is the pin for serial input of display control register and display RAM data. Also this pin output acknowledge signal. This is the pin for external clock input. Please connect to +5V with the power pin. This pin can be toggled between port pin output and B1 signal output. This pin can be toggled between port pin output and BLNK1 signal output. Please connect to GND using circuit earthing pin. This pin can be toggled between port pin output and BLNK0 signal output. This pin can be toggled between port pin output and R0 signal output. This pin can be toggled between port pin output and R1 signal output. This pin can be toggled between port pin output and G0 signal output. This pin can be toggled between port pin output and G1 signal output. This pin can be toggled between port pin output and B0 signal output. This pin inputs the horizontal synchronous signal. Hysteresis input. This pin inputs the vertical synchronous signal. Hysteresis input. Please connect to +5V with the power pin. Pin name Filter output Earthing pin Auto-clear input Chip select input Clock input Data input Data I/O External clock Power pin Port P6 output Port P7 output Earthing pin Port P0 output Port P1 output Port P2 output Port P3 output Port P4 output Port P5 output Horizontal synchro- nous signal input Vertical synchro- nous signal input Power pin Pin Number PIN DESCRIPTION

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS BLOCK DIAGRAM 6 8 204 SCK/SCLSIN/SD A V DD1 V DD2 AC V SS1 V SS2CS Cloc k oscillation circuit displa y Timing gener ator Polar ity s witching circuit Address control circuit Data control circuit Displa y control register Displa y RAM 0 (page 0) Displa y RAM 1 (page 1) Shift register Blinking circuit Reading address control circuit Displa y location detection circuit H counter TCK CPOUT 18HOR 19VER T Synchronous signal switching circuit Displa y control circuit Input control circuit Displa y char acter ROM 0 (page 0) Displa y char acter ROM 1 (page 1) Port output control circuit Polarity switching circuit P0/BLNK0 P1/R0 P3/G0 P5/B0 P2/R1 P4/G1 P6/B1 P7/BLNK1

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS MEMORY CONSTITUTION Address 00016 to 11F16 are assigned to the display RAM, address 12016 to 12816 are assigned to the display control registers. The in- ternal circuit is reset and all display control registers (address 12016 to 12816) are set to “0” when the AC pin level is “L”. And then, RAM is not erased and be undefinited. This memory is consisted of 2 Fig. 1 Memory constitution (page 0 memory) pages : page 0 memory and page 1 memory (their addresses are common), page controlled by DAF bit of each address when writing data. For detail, see “Data input”. Memory constitution is shown in Figure 1 and 2. DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

0 BB BG BR BLINK B G R C7 C6 C5 C4 C3 C2 C1 C0

0 EXCK0 DISV2 DIVS1 DIVS0 DIV10 DIV9 DIV8 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0

0 RSEL0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0

0 RSEL1

SPACE2 SPACE1 SPACE0 HP10 HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0

0 EXCK1 TEST3 TEST2 TEST1 TEST0 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0

0 TEST9 PTC67 TEST4 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0

TEST10 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 LIN9 LIN8 LIN7 LIN6 LIN5 LIN4 LIN3 LIN2

0 POPUP VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10

0 MODE0 TEST12 HSZ20 TEST11 HSZ10 BETA14 TEST8 TEST7 TEST6 FB FG FR RB RG RR

0 MODE1 BLINK2 BLINK1 BLINK0 DSPON STOP RAMERS SYAD BLK1 BLK0 POLH POLV VMASK

___ B/F BCOL 00016 00116 11E16 11F16 12016 12116 12216 12316 12416 12516 12616 12716 12816 Addresses Background coloring Blink- ing Character color Character code

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

1 BB BG BR BLINK B G R C7 C6 C5 C4 C3 C2 C1 C0

1 – SPACE2 SPACE1 SPACE0 HP10 HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 1 – TEST3 VJT TEST1 TEST0 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 1 –– TEST4 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0 1 – VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 LIN9 LIN8 LIN7 LIN6 LIN5 LIN4 LIN3 LIN2 1 – VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10 1 – TEST12 HSZ20 TEST11 HSZ10 BETA14 TEST8 TEST7 TEST6 FB FG FR RB RG RR 1 – BLINK2 BLINK1 BLINK0 DSPON TEST13 RAMERS SYAD BLK1 BLK0 –––– BCOL 00016 00116 11E16 11F16 12016 12116 12216 12316 12416 12516 12616 12716 12816 ……… Addresses Fig. 2 Memory constitution (page 1 memory) Background coloring Blink- ing Character color Character code ……… Note: Page 0 and page 1 registers are found in their respective pages. For example, HP10 to HP0 of the page 0 memory sets the horizontal display start position of page 0, whereas HP10 to HP0 (same register name) of the page 1 memory sets the horizontal display start position of page 1. Also, registers common to both page 0 and page 1 are found only in the page 0 memory. For example, PTC0 is the control register of the P0 pin and is found only in the page 0 memory.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 00016 00116 00216 00316 00416 00516 00616 00716 00816 00916 00A16 00B16 00C 16 00D 16 00E16 00F16 01016 01116 01216 01316 01416 01516 01616 01716 01816 01916 01A16 01B16 01C 16 01D 16 01E16 01F16 02016 02116 02216 02316 02416 02516 02616 02716 02816 02916 02A16 02B16 02C 16 02D 16 02E16 02F16 03016 03116 03216 03316 03416 03516 03616 03716 03816 03916 03A16 03B16 03C 16 03D 16 03E16 03F16 04016 04116 04216 04316 04416 04516 04616 04716 04816 04916 04A16 04B16 04C 16 04D 16 04E16 04F16 05016 05116 05216 05316 05416 05516 05616 05716 05816 05916 05A16 05B16 05C 16 05D 16 05E16 05F16 06016 06116 06216 06316 06416 06516 06616 06716 06816 06916 06A16 06B16 06C 16 06D 16 06E16 06F16 07016 07116 07216 07316 07416 07516 07616 07716 07816 07916 07A16 07B16 07C 16 07D 16 07E16 07F16 08016 08116 08216 08316 08416 08516 08616 08716 08816 08916 08A16 08B16 08C 16 08D 16 08E16 08F16 09016 09116 09216 09316 09416 09516 09616 09716 09816 09916 09A16 09B16 09C 16 09D 16 09E16 09F16 0A016 0A116 0A216 0A316 0A416 0A516 0A616 0A716 0A816 0A916 0AA 16 0AB 16 0AC 16 0AD 16 0AE 16 0AF 16 0B016 0B116 0B216 0B316 0B416 0B516 0B616 0B716 0B816 0B916 0BA 16 0BB 16 0BC 16 0BD 16 0BE 16 0BF 16 0C0 16 0C1 16 0C2 16 0C3 16 0C4 16 0C5 16 0C6 16 0C7 16 0C8 16 0C9 16 0CA 16 0CB 16 0CC 16 0CD 16 0CE 16 0CF 16 0D0 16 0D1 16 0D2 16 0D3 16 0D4 16 0D5 16 0D6 16 0D7 16 0D8 16 0D9 16 0DA 16 0DB 16 0DC 16 0DD 16 0DE 16 0DF 16 0E016 0E116 0E216 0E316 0E416 0E516 0E616 0E716 0E816 0E916 0EA 16 0EB 16 0EC 16 0ED 16 0EE 16 0EF 16 0F016 0F116 0F216 0F316 0F416 0F516 0F616 0F716 0F816 0F916 0FA 16 0FB 16 0FC 16 0FD 16 0FE 16 0FF16 10016 10116 10216 10316 10416 10516 10616 10716 10816 10916 10A16 10B16 10C 16 10D 16 10E16 10F16 11016 11116 11216 11316 11416 11516 11616 11716 11816 11916 11A16 11B16 11C 16 11D 16 11E16 11F16 Row Line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 * The hexadecimal numbers in the boxes show the display RAM address. SCREEN CONSTITUTION The screen lines and rows are determined from each address of the display RAM (page 0 and page 1 are common). The screen constitution is shown in Figure 3. Fig. 3 Screen constitution

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DISPLAY RAM Address 00016 to 11F16 Register Status

Contents

Set the displayed ROM character code. To write data into page 0 (Note 2), select the data from the ROM characters (256 types) for page 0 and set the character code. To write data into page 1, do the same from the ROM characters (256 types) for page 1. DA Set display character0 A B C D E Set blinking See register BLINK2 to BLINK0 (ad- dress128 16) Set character background (character unit) Do not blink. Blinking BB R G B BLINK BR BG BB Set character color (character unit) BR BG B R G ____ Notes 1. The display RAM is undefined state at the AC pin. 2. The display RAM consists of 2 pages, page 0 and page 1 (common address). The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. Color Black Red Green Yellow Blue Magenta Cyan White Color Black Red Green Yellow Blue Magenta Cyan White

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Set division value (multiply value) of horizontal oscillation frequency. N1 = N1 : division value (multiply value) DA Set display frequency range. Display clock setting See REGISTER SUPPLEMENTARY DESCRIPTION (1) EXCK1 : address123 EXCK1 EXCK0 DIV0 DIV1 DIV2 DIV3 DIV4 DIV5 DIV6 DIV7 DIV8 DIV9 DIV10 DIVS0 DIVS1 DISV2 Σ n = 0 A B C D E REGISTERS DESCRIPTION (1) Address 12016 Register Status (DIVn × 2n) ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". Display clock input External clock mode 1 Internal clock mode Do not set External clock mode 2 For setting, see REGISTER SUPPLEMENTARY DESCRIPTION (2). Set display frequency by division value (multiply value) setting. For details, see REGISTER SUPPLE- MENTARY DESCRIPTION (1). Also, set the display frequency range by registers DIVS0, DIVS1(address 120 16), RSEL0(address 12116) and RSEL1(address 12216) in accordance with the display frequency. Any of this settings above is required only when EXCK1 = 0, EXCK0 = 1 and EXCK1 = 1, EXCK0 = 1. EXCK0 (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 RSEL0 P0 output (port P0). BLNK0 output. P1 output (port P1). R0 signal output. P2 output (port P2). R1 signal output. P3 output (port P3). G0 signal output. P4 output (port P4). G1 signal output. P5 output (port P5). B0 signal output. “L” output or negative polarity output (BLNK0 output). “H ” output or positive polarity output (BLNK0 output). “L” output or negative polarity output (R0 signal output). “H ” output or positive polarity output (R0 signal output). “L” output or negative polarity output (R1 signal output). “H ” output or positive polarity output (R1 signal output). “L” output or negative polarity output (G0 signal output). “H ” output or positive polarity output (G0 signal output). “L” output or negative polarity output (G1 signal output). “H ” output or positive polarity output (G1 signal output). “L” output or negative polarity output (B0 signal output). “H ” output or positive polarity output (B0 signal output). “L” output or negative polarity output (B1 signal output). “H ” output or positive polarity output (B1 signal output). “L” output or negative polarity output (BLNK1 signal output). “H ” output or positive polarity output (BLNK1 signal output). For setting, see REGISTER SUPPLYMENTARY DESCRIPTION (2). P0 pin output control. P1 pin output control. P2 pin output control. P3 pin output control. P4 pin output control. P5 pin output control. P0 pin data control. P1 pin data control. P2 pin data control. P3 pin data control. P4 pin data control. P5 pin data control. P6 pin data control. P7 pin data control. Set display frequency range. (2) Address 121 A B C D E RegisterDA Status (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) Remarks ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1".

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (3) Address 12216 Horizontal display start location is specified using the 11 bits from HP10 to HP0. HP10 to HP0 = (00000000000 2) and (000001001112) setting is forbidden. HS* (shown left) shows horizontal__ display start location that is register B/F (address 128 16) = 0 is set. A B C D E Leave one line worth of space in the ver- tical direction. For example, 6 (S) 6 indicates two sets of 6 lines with a line of spaces between lines 6 and 7. A line is 18 × N horizontal scan lines. N is determined by the character size in the vertical direction Set display frequency range. HP0 HP1 HP2 HP3 HP4 HP5 HP6 HP7 HP8 HP9 HP10 SPACE0 SPACE1 SPACE2 RSEL1 SPACE Number of Lines and Space <(S) represents space> 1 (S) 10 (S) 1 2 (S) 8 (S) 2 3 (S) 6 (S) 3 4 (S) 4 (S) 4 5 (S) 2 (S) 5 6 (S) 6 6 (S)(S) 6 (S) represents one line worth of spac For setting, see REGISTER SUPPLEMENTARY DESCRIPTION (2). n = 0 RegisterDA Function ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". 4. Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds. OSD Display area Note 4 HS VS HOR VERT Monitor Screen Note 4 Note 4 Note 4 (Note 3) If HS is the horizontal display start location, HS = T × 2nHP n + 6) T : Period of display frequency 2007 settings are possible.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (4) Address 12316 The vertical start location is specified using the 10 bits from VP9 to VP0. VP9 to VP0 = (0000000000 2) setting is forbidden. HS* (shown left) shows horizontal__ display start location that is register B/F (address 12816) = 0 is set. A B C D E VP0 VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 VP9 TEST0 TEST1 VJT TEST3 EXCK1 If VS is the vertical display start location, VS = H × 2nVP n H: Cycle with the horizontal synchronizing pulse 1023 settings are possible. Σ n = 0 It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. For setting, see Register EXCK0 (address 120 16). Display clock setting RegisterDA Function (Note 3) ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". 4. Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds. OSD Display area Note 4 HS VS HOR VERT Monitor Screen Note 4 Note 4 Note 4

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (5) Address 12416 Sets the display mode of line 1. Sets the display mode of line 2. Sets the display mode of line 3. Sets the display mode of line 4. Sets the display mode of line 5. Sets the display mode of line 6. Sets the display mode of line 7. Sets the display mode of line 8. Sets the display mode of line 9. Sets the display mode of line 10. Sets the display mode of line 11. Sets the display mode of line 12. P6 pin and P7 pin output control. A B C D E RegisterDA Status (Note 3) (Note 3) Remarks ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". DSP0 DSP1 DSP2 DSP3 DSP4 DSP5 DSP6 DSP7 DSP8 DSP9 DSP10 DSP11 TEST4 PTC67 TEST9 It should be fixed to “0”. Can not be used. P6 output (port P6) and P7 output (port P7). B1 output and BLNK output. Set to “0” in internal clock mode. Set to “1” in external clock mode. BLK1 BLK0 DSPn= “0” Matrix-outline border Character Border Matrix-outline DSPn= “1” Matrix-outline Border Matrix-outline Character (At register BCOL = “0”) For detail, see DISPLAY FORM1(1). The display mode (blanking mode) for line n on the display screen is set line-by-line, using DSPn (n = 0 to 11). The display mode is determined by the combination of registers BLK1 and BLK0 (address 12816). Settings are given below.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (6) Address 12516 LIN2 LIN3 LIN4 LIN5 LIN6 LIN7 LIN8 LIN9 V1SZ0 V1SZ1 VSZ1L0 VSZ1L1 VSZ1H0 VSZ1H1 TEST10 A B C D E RegisterDA Status (Note 3) Remarks ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". Character size setting in the vertical direction for the 2nd line. Character size setting in the vertical direction for the 3rd line. Character size setting in the vertical direction for the 4th line. Character size setting in the vertical direction for the 5th line. Character size setting in the vertical direction for the 6th line. Character size setting in the vertical direction for the 7th line. Character size setting in the vertical direction for the 8th line. Character size setting in the vertical direction for the 9th line. Character size setting in the vertical direction for the 1st line. (display monitor 1 to 12 line) Character size setting in the vertical direction (display monitor 1 line) at “0” state in register LIN2 to LIN17 (address 125 16, 12616). Character size setting in the vertical direction (display monitor 1 line) at “1” state in register LIN2 to LIN17 (address 125 16, 12616). H: Cycle with the horizontal synchronizing pulse V1SZ1 V1SZ0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse VSZ1L1 VSZ1L0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse It should be fixed to “0”. Can not be used. VSZ1H1 VSZ1H0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot 1st line 2nd to 12th line LINn = “0” LINn = “1” Refer to VSZ1L0 and VSZ1L1 Refer to VSZ2L0 and VSZ2L1 Refer to VSZ1H0 and VSZ1H1 Refer to VSZ2H0 and VSZ2H1 The vertical dot size for line n in the character dot lines (18 vertical lines) is set using LINn (n = 2 to 17). Dot size can be selected between 2 types for each dot line. For dot size, see the below registers. Line 1 and lines 2 to 12 can be set independent of one another.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (7) Address 12616 LIN10 LIN11 LIN12 LIN13 LIN14 LIN15 LIN16 LIN17 V18SZ0 V18SZ1 VSZ2L0 VSZ2L1 VSZ2H0 VSZ2H1 POPUP A B C D E RegisterDA Status (Note 3) Remarks ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". H: Cycle with the horizontal synchronizing pulse Page 1 priority display Page 0 priority display Sets the priority page for when 2 pages are displayed at the same time. The setting is effective only when the standard display mode is set as MODE0 = "0" , MODE1 = "0". See "DISPLAY FORM 2" . Character size setting in the vertical direction for the 10th line. Character size setting in the vertical direction for the 11th line. Character size setting in the vertical direction for the 12th line. Character size setting in the vertical direction for the 13th line. Character size setting in the vertical direction for the 14th line. Character size setting in the vertical direction for the 15th line. Character size setting in the vertical direction for the 16th line. Character size setting in the vertical direction for the 17th line. Character size setting in the vertical direction for the 18th line. (display monitor 1 to 12 line) Character size setting in the vertical direction (display monitor for 2 to 12 line) at “0” state in register LIN2 to LIN17 (address 125 16, 12616). Character size setting in the vertical direction (display monitor for 2 to 12 line) at “0” state in register LIN2 to LIN17 (address 125 16, 12616). H: Cycle with the horizontal synchronizing pulse V18SZ1 V18SZ0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse VSZ2L1 VSZ2L0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot VSZ2H1 VSZ2H0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot 1st line 2nd to 12th line LINn = “0” LINn = “1” Refer to VSZ1L0 and VSZ1L1 Refer to VSZ2L0 and VSZ2L1 Refer to VSZ1H0 and VSZ1H1 Refer to VSZ2H0 and VSZ2H1 The vertical dot size for line n in the character dot lines (18 vertical lines) is set using LINn (n = 2 to 17). Dot size can be selected between 2 types for each dot line. For dot size, see the below registers. Line 1 and lines 2 to 12 can be set independent of one another.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (8) Address 12716 RR RG RB FR FG FB TEST6 TEST7 TEST8 BETA14 HSZ10 TEST11 HSZ20 TEST12 MODE0 A B C D E RegisterDA Status (Note 3) Remarks ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". 4. 2 way settings are available by POPUP (address 12616). Sets the raster color of all blankings. Sets the blanking color of the Border size, or the shadow size. Character size setting in the horizontal direction for the first line. T : Display frequency cycle Character size setting in the horizontal direction for the 2nd line to 12th line. T : Display frequency cycle Color Black Red Green Yellow Blue Magenta Cyan White It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Matrix-outline display (12 × 18 dot) Matrix-outline display (14 × 18 dot) RB RG RR Color Black Red Green Yellow Blue Magenta Cyan White FB FG FR HSZ10 Horizontal direction size 1T/dot 2T/dotHSZ20 Horizontal direction size 1T/dot 2T/dot It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. MODE1 MODE0 Output system 1 system 1 system 2 system 1 system Display mode Standard.(Note4) AND OR Sets the RGB signal output system and the display mode for when 2 pages are displayed at the same time. See “DISPLAY FORM 2”. MODE1(address128 16) .

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (9) Address 12816 BCOL B/F VMASK POLV POLH BLK0 BLK1 SYAD RAMERS STOP DSPON BLINK0 BLINK1 BLINK2 MODE1 A B C D E RegisterDA Status (Note 3) Remarks ____ Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. The page in which data is written is controlled by the DAF bit. When set to "0", data is written into page 0, whereas when set to "1", data is written into page 1. 3. Registers marked with (Note 3) are found only in page 0, therefore the register value does not change when the DAF bit is set to "1". (Note 3) (Note 3) (Note 3) (Note 3) Blanking of BLK0, BLK1 All raster blanking Synchronize with the leading edge of horizontal synchronization. Synchronize with the trailing edge of horizontal synchronization. Do not mask by VERT input signal Mask by VERT input signal VERT pin is negative polarity VERT pin is positive polarity HOR pin is negative polarity HOR pin is positive polarity Border display of character Shadow display of character RAM not erased RAM erased Oscillation of clock for display Stop the oscillation of clock for display Display OFF Display ON Divided into 64 of vertical synchronous signal Divided into 32 of vertical synchronous signal For setting, see MODE0 (address 127 16). Sets all raster blanking Synchronize with the front porch or back porch of the horizontal synchronazation signal. Set mask at phase comparison operating. Set VERT pin polarity. Set HOR pin polarity. Set blanking mode. See “DISPLAY SHAPE 2”. See “DISPLAY FORM1 (2)”. When register RAMERS is set to “1”,do not stop the display clock. There is no need to reset because there is no register for this bit. It is a test bit (TEST13) in the page 1 register, therefore fix it to “0”. Set blinking duty ratio. Set blinking frequency. Sets the RGB signal output system and the display mode for when 2 pages are displayed at the same time. BLINK Duty Blinking OFF 25% 50% 75% (When DSPn (address 12416) = “0”) Blanking mode Matrix-outline size Character size Border size Matrix-outline size BLK1 BLK0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS REGISTER SUPPLEMENTARY DESCRIPTION (1) Setting external clock input and display frequency mode Setting external clock input and display frequency mode (by use of EXCK0 (12016), EXCK1 (12316) and DIV10 to DIV0 (12016), as explained here following. Fosc = 6.3 to 80 MHz (VDD = 4.75 to 5.25 V) Fosc = 6.3 to 40 MHz (VDD = 2.50 to 3.50 V) Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronous signal. And input from HOR pin a constant period continuous horizontal synchronous signal. Never stop inputting the clock while displaying. Do not have to set a display frequency because the clock just as it is entered from outside is used as the display clock. Fosc = 20 to 110 MHz (V DD = 4.75 to 5.25 V) Clock input from the TCK pin is unnecessary. The multiply clock of the internally generated horizontal synchronous signal is used as the display clock. The display frequency is set by setting the multiply value of the horizontal synchronous frequency (of the display frequency) in DIV10 to DIV0 (address 120 16). Also, set the display frequency range. (See the next page.) Display frequency is calculated using the below expression. Display frequency = Horizontal synchronous frequency x Multiply value Fosc = 20 to 110 MHz (V DD = 4.75 to 5.25 V) Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronous signal. And input from HOR pin a constant-period continuous horizontal synchronous signal. Never stop inputting the clock while displaying. An internal clock which is in sync with the external input clock is used as the display clock. Because the display frequency equals the external clock frequency, set N1 (division value) that satisfies the below expressions to DIV10 to DIV0 (address 120 16) for make the display frequency is equal to the external clock frequency. N1 = external clock frequency / horizontal synchronous frequency N1 = Also, set the display frequency range. (See the next page.) Fig. 4 Example of external clock input Horizontal synchronous signal External clock Number of clock (N1) Σ n = 0 2nDIVn

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (2) To set display frequency range Whenever setting display frequency (when EXCK1 = "0", EXCK0 = "1", or EXCK1 = "1", EXCK0 = "1"), always set the display frequency range in accordance with the display frequency. This range is set from DIVS0, DIVS1, DIVS2 (address 120 16), RSEL0 address 12116) and RSEL1 (address 12216). Frequency ranges are given here below. (3) Notes on setting display frequency To change external clock (display) frequency or horizontal synchronization frequency, always use the following procedures. To set EXCK1 = "0", EXCK0 = "1" (a) Turn the display OFF. … DSPON (address 128 16) = "0" (b) Set the display frequency. … Set from DIV10 to DIV0, DIVS0, DIVS1, DIVS2 (address 12016), RSEL0 (address 12116) and RSEL1 (address 12216). (c) Wait 20 ms while the horizontal synchronization signal is being input. (d) Turn the display ON. … DSPON (address 12816) = "1" To set EXCK1 = "1", EXCK0 = "1" (a) Turn the display OFF. … DSPON (address 12816) = "0" (b) Set the display frequency. … Set from DIV10 to DIV0, DIVS0, DIVS1, DIVS2 (address 12016), RSEL0 (address 12116) and RSEL1 (address 12216). (c) Wait 20 ms while the horizontal synchronization signal and external clock are being input. (d) Turn the display ON. … DSPON (address 12816) = "1" RSEL1 RSEL0 DIVS1 DIVS0 DIVS2 Display frequency range(MHz) 100.0 to 110.0 92.0 to 100.0 73.0 to 92.0 66.5 to 73.0 61.0 to 66.5 49.0 to 61.0 45.5 to 49.0 36.5 to 45.5 33.5 to 36.5 30.5 to 33.5 24.5 to 30.5 23.0 to 24.5 20.0 to 23.0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 5 Example of R0,G0,B0,BLNK0,R1,G1,B1 and BLNK1 signal output DISPLAY FORM 1 M35076-XXXSP has the following four display forms. (1) Blanking mode Character size : Blanking same as the character size. Border size : Blanking the background as a size from character. Matrix-outline size : Blanking the background 12 × 18 dot. All blanking size : When set register BCOL to “1”, all raster area is blanking. The display mode and blanking mode can be set line-by-line, as fol- lows, from registers BCOL, BLK1, BLK0 (address 128 16), DSP0 to DSP11 (address 12416). BCOL BLK1 BLK0 Line of DSPn = “1”Line of DSPn = “0” Display mode All matrix-outline border display Character display Border display All matrix-outline display All matrix-outline border display Character display Border display All matrix-outline display Blanking mode All matrix-outline size Character size Border size All matrix-outline size All blanking size Display mode All matrix-outline display Border display All matrix-outline display Character display All matrix-outline display Border display All matrix-outline display Character display Blanking mode All matrix-outline size Border size All matrix-outlinesize Character size All blanking size 12 dots (Note 2) 18 dots 12 dots 12 dots 12 dots (Note 2) Scanning <Register BCOL=“0”> (Note 1) R1,G1 or B1 output BLNK0 output color setting Character color: R,G,B of display RAM (Character unit) Border color :Register FR,FG,FB (Display unit) Matrix-outline color :BR,BG,BB of display RAM (Character unit) (a) Matrix-outline and border display (Matrix-outline size) Character color : R,G,B of display RAM (Character unit) Matrix-outline color :BR,BG,BB of display RAM (Character unit) (d) Matrix-outline display (Matrix-outline size) Character color : R,G,B of display RAM (Character unit) Matrix-outline color :BR,BG,BB of displayRAM (Character unit) (c) Border display (Border size) Character color : R,G,B of display RAM (Character unit) (b) Character display (Character size) Note 1. When register BCOL is set to “1”, the raster range of the display modes set respectively by BLK1 and BLK0 are colored by registers RR, RG, and RB (address 127 16). And the blanking mode is set all blanking size (all raster size) regardless of the BLK1 and BLK0 settings. Note 2. When register MODE1,0=1,0 setting, RGB signal of page 0 is output from R0,G0,B0 and BLNK0 pin, and RGB signal of page 1 is output from R1, G1,B1 and BLNK1 pin. Note 3. The horizontal size of the full matrix-outline size can be set to 14 dots by register BETA14 (address 127 16). BLNK0 and BLNK1 can also be output at 14 dots. R0,G0 or B0 output BLNK1 output (Note 2) ( ) is blankin mode.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (2) Shadow display When border display mode, if set SYAD (address 12816) = “0” to “1”, it change to shadow display mode. Border and shadow display are shown below. Set shadow display color by BR, BG or BB of display RAM or by register FR, FG and FB (address 12716). Fig. 6 Border and shadow display Register SYAD(12816 address) = “0” Border display Register SYAD(12816 address) = “1” Shadow display

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS MODE0 POPUP DISPLAY FORM 2 This IC can display both page 0 and page 1 at the same time. Page 0: Set the DAF bit in each addresses to "0". Page 1: Set the DAF bit in each addresses to "1". MODE1 Fig. 7 Example of 2 pages display Example 1: Display position, display size, color, etc., can be freely set for each page, and the 2 pages can be displayed on top of each other or side-by-side. Example 2: RGB output of two pages can be outputted by one line or two lines by registers MODE0 (address 127 16) and MODE1 (address 12816) and POPUP (address 12616). And, when the display range of the 2 pages overlap on the monitor screen at the time of an one-line output, they can perform the following displays. (The POPUP register is effective only when MODE0 = "0" and MODE1 = "0".) Menu Setting Help End Page 1 (24 columns ✕ 12 line) Monitor display Monitor display Example 1 Example 2 Screen size Tone Menu Setting Help End Screen size Tone Page 1 (24 columns ✕ 12 line) Page 0 (24 columns ✕ 12 line)Page 0 (24 columns ✕ 12 line) Output system 1 system 1 system 1 system 2 systems 1 system Display mode Standard (Page 1 priority) Standard (Page 0 priority) AND OR (1) Output system (a) 1 system : Output RBG signal of both of page 0 and 1 from R0,G0,B0 and BLNK0 pin (For overlapping areas, refer to below.) (b) 2 systems : RBG signal of page 0 is output from R0,G0,B0 and BLNK0 pin, RBG signal of page 1 is output from R1,G1,B1 and BLNK1 pin. (2) Display mode (Overlapping areas of Page 0 and 1) (a) Standard (page 1 priority).. Page 1 has priority in overlapping areas. Page 0 is not displayed in those areas. (b) Standard (page 0 priority).. Page 0 has priority in overlapping areas. Page 1 is not displayed in those areas. Note : Set 0 (port output) to control register PTC2, PTC4 and PT67 except at 2 systems output setting (MODE1=1,MODE0=0.)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS CHARACTER FONT Images are composed on a 12 ✕ 18 dot matrix, and characters can be linked vertically and horizontally with other characters to allow the display the continuous symbols. Character code FF 16 is fixed as a blank without background. Therefore, cannot register a character font in this code. Fig. 8 Example of border display When the character extends to the top line of the matrix, no border is left at the top. Note: Hatching represents border. When the character extends to the bottom (18th) line of the matrix, no border is left at the bottom. 12 dots 18 dots

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Character color DATA INPUT EXAMPLE Data of display RAM and display control registers can be set by the 16-bit serial input function or the I2C-BUS serial input function. Ex- ample of data setting is shown in Figure 9 (at EXCK0 = “1”, EXCK1 = “0” setting). Data input example (M35076-XXXSP) Notes 1 : The page in which data is written is controlled by the address. To write data into page 0, set "0". To write data into page 1, set "1". 2 : Input a continuous clock of constant period from the TCK pin. Also, input a horizontal synchronous signal into the HOR pin and a vertical synchronous signal into the VERT pin. 3 : Matrix-outline display in this data. 4 : Secure the waiting time of 200ms after releasing AC, and set data from setting the display frequency (setting of the register). 5 : Set data to display RAM at internal clock (display clock) is stabilized. DAF (Note1)DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Remarks 0 page Address/data Address 12016 Data 120 16 Data 121 16 Data 122 16 Data 123 16 Data 124 16 Data 125 16 Data 126 16 Data 127 16 Data 128 16 Address 12216 Data 122 16 Data 123 16 Data 124 16 Data 125 16 Data 126 16 Data 127 16 Data 128 16 Data 000 16 Data 11F 16 Address 00016 Data 000 16 Data 11F 16 Address 12816 Data 128 16 Address 12816 Data 128 16 DIV0 HP0 VP0 HP0 VP0 RSEL0 RSEL1 BB BB BB BB DIVS1 PTD6 BR BR BR BR DIV10 PTD4 HP10 HP10 B B B B DIV9 HP9 VP9 HP9 VP9 G G G DIV8 PTD2 HP8 VP8 HP8 VP8 R R R R DIV7 HP7 VP7 HP7 VP7 DIV6 HP6 VP6 HP6 VP6 DIV5 HP5 VP5 HP5 VP5 DIV4 HP4 VP4 POLH HP4 VP4 DIV3 HP3 VP3 POLV HP3 VP3 DIV2 HP2 VP2 HP2 VP2 DIV1 HP1 VP1 HP1 VP1 DIVS2 PTD7 BG BG BG BG System set up (Note 4) Address setting 200m sec hold Address setting 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 POLH POLV 0 0 0 Fig 9. Example of data setting Horizontal display location setting Vertical display location setting Display form setting Character size setting Character size setting Color, character size setting Output setting Frequency value setting (Note2) 1 page Horizontal display location setting Vertical display location setting Display form setting Character size setting Character size setting Color, character size setting Page 0 display OFF Address setting Page 1 display OFF Be stable / Waiting time Character setting Character setting Character code Character code Page 1 display ON Display form setting (Note 3) Address setting Page 0 display ON Display form setting (Note 3) 200m sec hold Character color Blink -ing DIVS0 BLINK BLINK BLINK BLINK Blink -ing Background coloring Background coloring 0 page 1 page

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig 11. Example of the M35076-XXXSP peripheral circuit ( Internal clock mode. At EXCK1 = “0”, EXCK0 = “1”) 1µF 100µF 1µF 0.01µF CPOUT V SS2 AC CS SCK/SCL SIN/SDA TCK V DD2 VERT HOR +5V +5V + – 100µF 1µF 0.01µF – + M35076-XXXSP Synchronous signal generator Microcomputer 470PF (Note 2) Horizontal synchronors signal (5V) Vertical synchronors signal (5V) Note 1: Use this 1% precision element Note 2: Use this 10% precision element Note3. Connect to VDD with CS pin at the I C-Bus serial communication. 1.0kΩ (Note 1) 0.1µF(Note 2) VDD1 P6/B1 P7/BLNK1 P5/B0 P4/G1 P3/G0 P2/R1 P1/R0 P0/BLNK0 V SS1 BLNK1 BLNK0 Fig 10. Example of the M35076-XXXSP peripheral circuit ( External clock mode 1. At EXCK1 = “0”, EXCK0 = “0”) 1µF 100µF 1µF 0.01µF CPOUT V SS2 AC CS SCK/SCL SIN/SDA TCK BLNK1 V DD1 P6/B1 P7/BLNK1 VDD2 VERT HOR P5/B0 P4/G1 P3/G0 P2/R1 P1/R0 P0/BLNK0 V SS1 +5V or +3V +5V or +3V BLNK0 + – 100µF 1µF 0.01µF – + Note1. CPOUT pin can be opened when use only EXCK1 = "0" and EXCK0 = "0". Note2. Connect to VDD with CS pin at the I C-Bus serial communication. M35076-XXXSP Synchronous signal generator Microcomputer External clock Horizontal synchronors signal (5V or 3V) Vertical synchronors signal (5V or 3V)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig 12. Example of the M35076-XXXSP circuit (External clock mode 2. At EXCK1 = “1”, EXCK0 = “1”) External clock 1µF 100µF 1µF 0.01µF CPOUT V SS2 AC CS SCK/SCL SIN/SDA TCK V DD1 P6/B1 P7/BLNK1 VDD2 VERT HOR P5/B0 P4/G4 P3/G0 P2/R1 P1/R0 P0/BLNK0 VSS1 +5V +5V + – 100µF 1µF 0.01µF – + M35076-XXXSP Synchronous signal generator Microcomputer 470PF (Note 2) Horizontal synchronors signal (5V) Vertical synchronors signal (5V) Note 1: Use this 1% precision element Note 2: Use this 10% precision element Note3. Connect to VDD with CS pin at the I C-Bus serial communication. 1.0kΩ (Note 1) 0.1µF(Note 2) BLNK1 BLNK0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DATA INPUT 1 (1) The16-bit communication function (a)Serial data should be input with the LSB first. (b)The address consists of 16 bits. (c)The data consists of 16 bits. Fig.13 Serial input timing CS N = 1,2,3……… SCK SIN LSB MSB LSB MSB LSB MSB Address(16 bits) Data(16 bits) N Data(16 bits) N + 1 (d)The 16 bits in the SCK after the CS signal has fallen are the address, and for succeeding input data, the address is incremented every 16 bits. Therefore, it is not necessary to in put the address from the second data. Note. Stop the input to SCK pin and fix it to “H ” at CS pin “H ” level.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (2)Timing requirements Data input Fig. 14 Serial input timing requirements Symbol tw (SCK) tsu(CS) th(CS) tsu(SIN) th(SIN) tword Parameter SCK width CS setup time CS hold time SIN setup time SIN hold time 1 word writing time Min. 200 200 200 200 Typ. Limits Unit ns ns µs ns ns µs Max. Remarks See Figure 14 tsu(CS) tw(SCK) tw(SCK) tsu(SIN) th(SIN) th(CS) tw(CS) 1µs(min.) tword more than 2 µs 1 2 12 13 14 15 16… 1 1 21 31 41 51 6… CS SCK SIN SCK CS

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 15 Start state / Stop state Fig. 16 Control byte configuration DATA INPUT 2 (1) The I2C-Bus communication function (at VDD=5V only) This IC has a built-in data transmission interface which utilizes 2 unidirectional buses. In communications, this IC functions as a slave reception device. Set CS pin to “H ” level at the I2C-Bus serial input communication. The IC is synchronized with the serial clock (SCL) sent from the master device and receives the data (SDA). Communica- tions are controlled from the start/stop states. Also, always in- put the control byte after attaining the start state. The below chart shows the start/stop state and control byte configuration. SCL SDA Start state Stop stateData receive Data modify enable Note1. Connect to VDD with CS pin. Control byte: 7C16(Fixed) Slave address R/W 01111100 (0: Written)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (2) Data input (Sequence) (a) Addresses are consists of 16 bits. (b) Data is consists of 16 bits. (c) Addresses and data are communicated in 8-bit units. Input the lower 8 bits before the upper 8 bits. Make input from the MSB side. (d) After the start state has been attained and the control byte (7CH) received, the next 16 bits (2 bytes) are for inputting the address. Addresses are increased in increments for every 16 bits (2 bytes) of data input thereafter. As a result, it is not necessary to input the address from the second data. Note: During external synchronous, stop the external clock input from the TCK pin while inputting data. Fig. 17 Data input sequence ACK* (Acknowledge) : Output the acknowledge signal whenever one byte input after the start state. Output the acknowledge signal and recieve the data thereafter when mach the slave address (7CH). S T A R T S P M S B A C K A C K A C K A C K A C K A C K L S B M S B L S B M S B L S B M S B L S B M S B L S B S T O P Control byte (7 CH) Lower address (N ) Upper address (N ) Lower data (N ) Upper data (N ) lower data (N + 1) SDA

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS ParameterSymbol fCLK tHIGH tLOW tR tF tHD : STA tSU : STA tHD : DAT tSU : DAT tSU : STO tBUF tSP Clock frequency HIGH period of Clock LOW period of Clock SDA & SCL rise time SDA & SCL fall time Hold time at START status Set up time at START status Data input hold time Data input setup time Set up time at STOP state Bus release time Input filter / spike suppress (SDA & SCL pin) Min. 4000 4700 4000 4700 250 4000 4700 N/A Max. 100 1000 300 N/A Min. 600 1300 20+(Note) 0.1CB 20+(Note) 0.1CB 600 600 100 600 1300 Max. 400 300 300 Unit Limits Typ. mode High-speed mode KHz ns ns ns ns ns ns ns ns ns ns ns Remarks Note. CB = total capacitance of 1 bus line. (3) Timing requirement Data input Time must be re- leased bus before next transmission Only at START state repeating generation Fig. 18 Data input timing SCL SDA t SP tsu : STA tHD : STA tHD : DAT tSU : DAT tF tHIGH tLOW tR tSU : STO tBUF

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Max. 5.25 3.50 VDD VDD 0.2VDD 0.3VDD 80.0 40.0 110.0 110.0 130.0 60.0 Parameter Supply voltage “L” level input voltage Oscillating frequency for display Horizontal synchronous signal input frequeney Unit V mA V V kΩ V Min. 4.75 3.5 0.6VDD Parameter Supply voltage Supply current “H ” level output voltage “L” level output voltage __ __ Pull-up resistance AC, CS External clock input width Test conditions Ta = –20 to +85°C VDD = 5.00V VDD = 4.75V, IOH = -0.4mA VDD = 4.75V, IOH = -0.05mA VDD = 4.75V, IOL = 0.4mA VDD = 4.75V, IOL = 0.05mA VDD = 4.75V, IOL = 3.0mA VDD = 5.00V 4.75V ≤ VDD ≤ 5.25V Unit V V V V V V MHz MHz MHz MHz kHz kHz Symbol V DD VIH VIL FOSC H.sync Symbol VDD VI VO Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS (VDD = 5.00V, Ta = –20 to +85°C, unless otherwise noted) Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to V SS . Ta = +25°C Ratings –0.3 to +6.0 VSS –0.3 ≤ VI ≤ VDD +0.3 VSS ≤ VO ≤ VDD +300 –20 to +85 –40 to +125 Unit V V V mW Typ. 5.0 3.0 VDD VDD Min. 4.75 2.50 0.8V DD 0.7VDD 6.3 6.3 20.0 20.0 15.0 15.0 Limits RECOMMENDED OPERATING CONDITIONS (VDD = 5.00V, Ta = –20 to +85°C, unless otherwise noted) ELECTRICAL CHARACTERISTICS 1 V DD =5V (VDD = 5.00V, Ta = 25°C, unless otherwise noted) Symbol VDD IDD VOH VOL R I VTCK Limits Max. 5.25 0.4 100 0.9VDD P0 to P7 (Note1) CPOUT P0 to P7 (Note2) CPOUT SIN/SDA Typ. 5.0 SCK/SCL, SIN/SDA “H ” level input voltage __ __ AC, CS, HOR, VERT SCK/SCL, SIN/SDA __ __ AC, CS, HOR, VERT Notes 1. The current from the IC must not exceed – 0.4 mA/port at any of the port pins (P0 to P7). 2. The current flowing into the IC must not exceed 0.4 mA/port at any of port pins (P0 to P7). Internal clock mode External clock mode 1 External clock mode 2 VDD = 4.75 to 5.25 V VDD = 2.50 to 3.50 V VDD = 4.75 to 5.25 V VDD = 4.75 to 5.25 V VDD = 4.75 to 5.25 V VDD = 2.50 to 3.50 V

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Unit V mA V V kΩ V Min. 2.50 2.30 0.7VDD Parameter Supply voltage Supply current “H ” level output voltage “L” level output voltage __ __ Pull-up resistance AC, CS External clock input width Test conditions Ta = –20 to +85°C VDD = 3.00V VDD = 2.70V, IOH = -0.1mA VDD = 2.70V, IOH = 0.1mA VDD = 3.00V 2.20V ≤ VDD ≤ 3.50V ELECTRICAL CHARACTERISTICS 2 V DD =3V (VDD = 3.00V, Ta = 25°C, unless otherwise noted) Symbol VDD IDD VOH VOL R I VTCK Limits Max. 3.50 0.4 150 VDD P0 to P7 (Note1) P0 to P7 (Note2) Typ. 3.00 Notes 1. The current from the IC must not exceed – 0.1 mA/port at any of the port pins (P0 to P7). 2. The current flowing into the IC must not exceed 0.1 mA/port at any of port pins (P0 to P7).

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS NOTE FOR SUPPLYING POWER (1)Timing of power supplying to AC pin The internal circuit of M35076-XXXSP is reset when the level of the auto clear input pin AC is “L”. This pin in hysteresis input with the pull-up resistor. The timing about power supplying of AC pin is shown in Figure 19. PRECAUTION FOR USE Notes on noise and latch-up In order to avoid noise and latch-up, connect a bypass capacitor (≈0.1µF) directly between the VDD1 pin and VSS1 pin, and the VDD2 pin and VSS2 pin using a heavy wire. Fig. 19 Timing of power supplying to AC pin After supplying the power (VDD and VSS ) to M35076-XXXSP and the supply voltage becomes more than 0.8 × VDD , it needs to keep VIL time; tw of the AC pin for more than 1ms. Start inputting from microcomputer after AC pin supply voltage becomes more than 0.8 × V DD and keeping 200ms wait time. (2)Timing of power supplying to VDD1 and VDD2 . Supply power to VDD1 and VDD2 at the same time. Note for waveform timing of the horizontal signals to the HOR pin Set horizontal synchronous signal edge∗ waveform timing to under 5ns and input to HOR pin. Set only the side which set by B/F register waveform timing under 5ns and input to HOR pin. ∗: Set front porch edge or back porch edge by B/F register. Voltage [V] VDD 0.8 x VDD 0.2 x VDD Supply voltage more than 1ms tW tS Time t [s] Data input disable VAC (AC pin input voltage) 90% 10% tf tr Horizontal synchronous signal DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders. (1) M35076-XXXSP mask ROM order confirmation form (2) 20P4B mark specification form (3) ROM data : EPROMs or floppy disks *In the case of EPROMs, thres sets of EPROMs are required per pattern. *In the case of floppy disks, 3.5-inch 2HD disk (1BM format) is required per pattern.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS STANDARD ROM TYPE : M35076-001SP M35076-001SP is a standard ROM type of M35076-XXXSP. The character patterns for 0 page are fixed to the contents of Figure 20 to 23, the character patterns for page 1 are fixed to the contents of Figure 24 to 27.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 20 M35076-001SP character pattern for page 0 (1) 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C 16 0D 16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C 16 2D 16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 3F16

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 21 M35076-001SP character pattern for page 0 (2) 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C 16 4D 16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C 16 6D 16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 22 M35076-001SP character pattern for page 0 (3) 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C 16 8D 16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C 16 9D 16 9E16 9F16 A016 A116 A216 A316 A416 A516 A616 A716 A816 A916 AA 16 AB 16 AC 16 AD 16 AE 16 AF 16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA 16 BB 16 BC 16 BD 16 BE 16 BF 16

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 23 M35076-001SP character pattern for page 0 (4) C0 16 C116 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CA 16 CB 16 CC 16 CD 16 CE 16 CF 16 D0 16 D116 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA 16 EB 16 EC 16 ED 16 EE 16 EF 16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB 16 FC 16 FD 16 FE 16 FF16 blank

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C 16 0D 16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C 16 2D 16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 3F16 Fig. 24 M35076-001SP character pattern for page 1 (1)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C 16 4D 16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C 16 6D 16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 Fig. 25 M35076-001SP character pattern for page 1 (2)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C 16 8D 16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C 16 9D 16 9E16 9F16 A016 A116 A216 A316 A416 A516 A616 A716 A816 A916 AA 16 AB 16 AC 16 AD 16 AE 16 AF 16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA 16 BB 16 BC 16 BD 16 BE 16 BF 16 Fig. 26 M35076-001SP character pattern for page 1 (3)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS C0 16 C116 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CA 16 CB 16 CC 16 CD 16 CE 16 CF 16 D0 16 D116 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA 16 EB 16 EC 16 ED 16 EE 16 EF 16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB 16 FC 16 FD 16 FE 16 FF16 blank Fig. 27 M35076-001SP character pattern for page 1 (4)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS PACKAGE OUTLINE

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS © 2002 MITSUBISHI ELECTRIC CORP. New publication, effective MAR. 2002. Specifications subject to change without notice. Notes regarding these materials

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