M35075-XXXFP

M35075-XXXFP RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 45

Technical content

Rev.1.10 Feb 13, 2006 page 1 of 44 REJ03B0180-0110 M35075-XXXFP REJ03B0180-0110 Rev.1.10 Feb 13, 2006SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS

DESCRIPTION

The M35075-XXXFP is a character pattern display control IC can display on the CRT display the liquid crystal display and the plasma display. It uses a silicon gate CMOS process and it housed in a 24-pin shrink SOP package (M35075-XXXFP). For M35075-001FP that is a standard ROM version of M35075- XXXFP respectively, the character pattern is also mentioned.

FEATURES

RAM character:8 characters

• Display locations available Cycle : division of vertical synchronization signal into 32 or 64 Duty : 25%, 50%, or 75%
• Coloring for ROM character character unit)
• Blanking for ROM character Character size blanking Border size blanking Matrix-outline blanking All blanking (all raster area)
• Blanking for RAM character Character size blanking Matrix-outline blanking All blanking (all raster area)
• Output ports 4 shared output ports (toggled between RGB output) 4 dedicated output ports
• Display RAM erase function
• Horizontal synchronous input frequency
• Display oscillation stop function <VDD=5V>
• Display input frequency range OSC = 6.3 MHz to 80.0 MHz
• Horizontal synchronous input frequency PIN CONFIGURATION (TOP VIEW) <VDD=3V>
• Display input frequency range OSC = 6.3 MHz to 40 MHz
• Horizontal synchronous input frequency APPLICATION CRT display, Liquid crystal display, Plasma display Outline 24P2Q CPOUT ← → P3/G → P2 → P1/R → P0/BLNK0 ← BIN VSS1 ← VERT ← HOR → P5/B → P4 VSS2 AC → CS → SCK/SCL → SIN/SDA ↔ TCK → VDD1 P6 ← P7 ← M35075 - XXXFP NC NC NC VDD2

Rev.1.10 Feb 13, 2006 page 2 of 44 REJ03B0180-0110 M35075-XXXFP Symbol CPOUT VSS2 AC CS SCK/SCL SIN/SDA TCK V DD1 NC NC HOR VERT V SS1 BIN P0/BLNK0 P1/R P3/G P5/B V DD2 NC Input/ Output Output Input Input Input Input I/O Input Output Output Input Input Input Output Output Output Output Output Output Function Filter output. Connect loop filter to this pin. Please connect to GND using circuit earthing pin. When “L”, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor. <at the 16-bit serial communication> Chip select pin. Set this pin to "L" level at serial data transfer. Hysteresis input. Built-in pull-up resistor. <at the I 2C-BUS serial communication> Set this pin to “H” level. <at the 16-bit serial communication> _____ SIN pin serial data is taken in when SCK rises at CS pin "L" level. Hysteresis input. <at the I 2C-BUS serial communication> SDA pin serial data is taken in synchronized with SCL. <at the 16-bit serial communication> This is the pin for serial input of display control register and display RAM data. Hysteresis input. <at the I 2C-BUS serial communication> Hysteresis input. This is the pin for serial input of display control register and display RAM data. Also this pin output acknowledge signal. This is the pin for external clock input. This is the output port. This is the output port. Please connect to +5V with the power pin. This is NC pin. Please open this pin. This is NC pin. Please open this pin. This pin inputs the horizontal synchronous signal. Hysteresis input. This pin inputs the vertical synchronous signal. Hysteresis input. Please connect to GND using circuit earthing pin. Test pin. Connect to 0V. This pin can be toggled between port pin output and BLNK0 signal output. This pin can be toggled between port pin output and R signal output. This is the output port. This pin can be toggled between port pin output and G signal output. This is the output port. This pin can be toggled between port pin output and B signal output. Please connect to +5V with the power pin. This is NC pin. Please open this pin. Pin name Filter output Earthing pin Auto-clear input Chip select input Clock input Data input Data I/O External clock Port P6 output Port P7 output Power pin Horizontal synchro- nous signal input Vertical synchro- nous signal input Earthing pin Test pin Port P0 output Port P1 output Port P2 output Port P3 output Port P4 output Port P5 output Power pin Pin Number PIN DESCRIPTION

Rev.1.10 Feb 13, 2006 page 3 of 44 REJ03B0180-0110 M35075-XXXFP BLOCK DIAGRAM 4 5 6 10 23 16 CS SIN/SDASCK/SCL V DD1 V DD2 AC V SS1 V SS2 TEST Clock oscillationcircuit display Timing generator Polarity switching circuit Address control circuit Data control circuit Display control register Display RAM Shift register Blinking circuit Reading address control circuit Display locationdetection circuit H counter TCK CPOUT 13HOR VERT Synchronous signal switching circuit Display control circuit Po rt output control circuit P0/BLNK0

18 P1/R 20 P3/G22 P5/B 19 P2 21 P4 8P 6 9

Polarity switching circuit Display character RAM Display character ROM

Rev.1.10 Feb 13, 2006 page 4 of 44 REJ03B0180-0110 M35075-XXXFP DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B BB GB R BLINK B G R C7 C6 C5 C4 C3 C2 C1 C0 0B BB GB R BLINK B G R C7 C6 C5 C4 C3 C2 C1 C0 0B BB GB R BLINK B G R C7 C6 C5 C4 C3 C2 C1 C0 0B BB GB R BLINK B G R C7 C6 C5 C4 C3 C2 C1 C0

0 SPACE2 SPACE1 SPACE0 TEST10 DIV10 DIV9 DIV8 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0

0 EXCK1 EXCK0 RSEL1 RSEL0 DIVS2 DIVS1 DIVS0 PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0

0 TEST17 TEST16 TEST15 TEST14 TEST13 TEST12 TEST11 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

0 TEST3 TEST2 TEST1 TEST0 HP10 HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0

0 TEST20 RBLK0 TEST19 TEST18 VP10 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0

0 TEST23 TEST22 TEST21 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0

0 TEST24 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 LIN9 LIN8 LIN7 LIN6 LIN5 LIN4 LIN3 LIN2

0 TEST25 VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10

0 TEST29 TEST32 HSZ20 TEST31 HSZ10 BETA14 TEST28 TEST27 TEST26 FB FG FR RB RG RR

0 TEST30 BLINK2 BLINK1 BLINK0 DSPON STOP RAMERS SYAD BLK1 BLK0 POLH POLV VMASK B/F BCOL

Address 00016 to 11F16 are assigned to the display RAM, address 12016 to 12916 are assigned to the display control registers and address 20016 to 2F116 are assigned to the RAM characters. The internal circuit is reset and all display control registers (address 12016 to 12916) are set to "0" when the AC pin level is "L". And then, RAM is not erased and be undefinited. For detail, see "DATA INPUT EXAMPLE". Memory constitution is shown in Figure 1 to 9. Fig.1 Memory constitution (Display RAM, Display Control register) Addresses Background coloring Blink- ing Character color Character code 00016 00116 11E16 11F16 12016 12116 12216 12316 12416 12516 12616 12716 12816 12916

Rev.1.10 Feb 13, 2006 page 5 of 44 REJ03B0180-0110 M35075-XXXFP DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B S G S R S FR000B FR000A FR0009 FR0008 FR0007 FR0009 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000 0B S G S R S FR001B FR001A FR0019 FR0018 FR0017 FR0019 FR0015 FR0014 FR0013 FR0012 FR0011 FR0010 0B S G S R S FR002B FR002A FR0029 FR0028 FR0027 FR0026 FR0025 FR0024 FR0023 FR0022 FR0021 FR0020 0B S G S R S FR003B FR003A FR0039 FR0038 FR0037 FR0036 FR0035 FR0034 FR0033 FR0032 FR0031 FR0030 0B S G S R S FR004B FR004A FR0049 FR0048 FR0047 FR0046 FR0045 FR0044 FR0043 FR0042 FR0041 FR0040 0B S G S R S FR005B FR005A FR0059 FR0058 FR0057 FR0056 FR0055 FR0054 FR0053 FR0052 FR0051 FR0050 0B S G S R S FR006B FR006A FR0069 FR0068 FR0067 FR0066 FR0065 FR0064 FR0063 FR0062 FR0061 FR0060 0B S G S R S FR007B FR007A FR0079 FR0078 FR0077 FR0076 FR0075 FR0074 FR0073 FR0072 FR0071 FR0070 0B S G S R S FR008B FR008A FR0089 FR0088 FR0087 FR0086 FR0085 FR0084 FR0083 FR0082 FR0081 FR0080 0B S G S R S FR009B FR009A FR0099 FR0098 FR0097 FR0096 FR0095 FR0094 FR0093 FR0092 FR0091 FR0090 0B S G S R S FR00AB FR00AA FR00A9 FR00A8 FR00A7 FR00A6 FR00A5 FR00A4 FR00A3 FR00A2 FR00A1 FR00A0 0B S G S R S FR00BB FR00BA FR00B9 FR00B8 FR00B7 FR00B6 FR00B5 FR00B4 FR00B3 FR00B2 FR00B1 FR00B0 0B S G S R S FR00CB FR00CA FR00C9 FR00C8 FR00C7 FR00C6 FR00C5 FR00C4 FR00C3 FR00C2 FR00C1 FR00C0 0B S G S R S FR00DB FR00DA FR00D9 FR00D8 FR00D7 FR00D6 FR00D5 FR00D4 FR00D3 FR00D2 FR00D1 FR00D0 0B S G S R S FR00EB FR00EA FR00E9 FR00E8 FR00E7 FR00E6 FR00E5 FR00E4 FR00E3 FR00E2 FR00E1 FR00E0 0B S G S R S FR00FB FR00FA FR00F9 FR00F8 FR00F7 FR00F6 FR00F5 FR00F4 FR00F3 FR00F2 FR00F1 FR00F0 0B S G S R S FR010B FR010A FR0109 FR0108 FR0107 FR0106 FR0105 FR0104 FR0103 FR0102 FR0101 FR0100 0B S G S R S FR011B FR011A FR0119 FR0118 FR0117 FR0116 FR0115 FR0114 FR0113 FR0112 FR0111 FR0110 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C 16 20D 16 20E16 20F16 21016 21116 21216 21F16 Address DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B S G S R S FR100B FR100A FR1009 FR1008 FR1007 FR1006 FR1005 FR1004 FR1003 FR1002 FR1001 FR1000 0B S G S R S FR111B FR111A FR1119 FR1118 FR1117 FR1116 FR1115 FR1114 FR1113 FR1112 FR1111 FR1110 22016 22116 23016 23116 23216 23F16 RAM character 1 data Fig.2 Memory constitution (RAM character 0) Fig.3 Memory constitution (RAM character 1) Can not be used Address Can not be used

Rev.1.10 Feb 13, 2006 page 6 of 44 REJ03B0180-0110 M35075-XXXFP DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B S G S R S FR300B FR300A FR3009 FR3008 FR3007 FR3006 FR3005 FR3004 FR3003 FR3002 FR3001 FR3000 0B S G S R S FR311B FR311A FR3119 FR3118 FR3117 FR3116 FR3115 FR3114 FR3113 FR3112 FR3111 FR3110 26016 26116 27016 27116 27216 27F16 28016 28116 29016 29116 29216 29F16 DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B S G S R S FR200B FR200A FR2009 FR2008 FR2007 FR2006 FR2005 FR2004 FR2003 FR2002 FR2001 FR2000 0B S G S R S FR211B FR211A FR2119 FR2118 FR2117 FR2116 FR2115 FR2114 FR2113 FR2112 FR2111 FR2110 24016 24116 25016 25116 25216 25F16 Fig.6 Memory constitution (RAM character 4) Fig.5 Memory constitution (RAM character 3) Fig.4 Memory constitution (RAM character 2) DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B S G S R S FR400B FR400A FR4009 FR4008 FR4007 FR4006 FR4005 FR4004 FR4003 FR4002 FR4001 FR4000 0B S G S R S FR411B FR411A FR4119 FR4118 FR4117 FR4116 FR4115 FR4114 FR4113 FR4112 FR4111 FR4510 Address Address Address RAM character 2 data Can not be used RAM character 3 data Can not be used RAM character 4 data Can not be used

Rev.1.10 Feb 13, 2006 page 7 of 44 REJ03B0180-0110 M35075-XXXFP 2C0 16 2C1 16 2D0 16 2D1 16 2D2 16 2DF 16 2E016 2E116 2F016 2F116 2A016 2A116 2B016 2B116 2B216 2BF 16 DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B S G S R S FR700B FR700A FR7009 FR7008 FR7007 FR7006 FR7005 FR7004 FR7003 FR7002 FR7001 FR7000 0B S G S R S FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 Fig.9 Memory constitution (RAM character 7) Fig.8 Memory constitution (RAM character 6) Fig.7 Memory constitution (RAM character 5) Address Address Address RAM character 5 data Can not be used RAM character 6 data Can not be used RAM character 7 data DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0B S G S R S FR600B FR600A FR6009 FR6008 FR6007 FR6006 FR6005 FR6004 FR6003 FR6002 FR6001 FR6000 0B S G S R S FR611B FR611A FR6119 FR6118 FR6117 FR6116 FR6115 FR6114 FR6113 FR6112 FR6111 FR6110 DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 D00 0B S G S R S FR500B FR500A FR5009 FR5008 FR5007 FR5006 FR5005 FR5004 FR5003 FR5002 FR5001 FR5000 0B S G S R S FR511B FR511A FR5119 FR5118 FR5117 FR5116 FR5115 FR5114 FR5113 FR5112 FR5111 FR5110

Rev.1.10 Feb 13, 2006 page 8 of 44 REJ03B0180-0110 M35075-XXXFP SCREEN CONSTITUTION The screen lines and rows are determined from each address of the display RAM . The screen constitution is shown in Figure 10. Fig.11 RAM charcter consititution Note. When the RAM character is used, it is necessary to clear all areas of the RAM character first. FR n00B FR n00A FR n009 FR n008 FR n007 FR n006 FR n005 FR n004 FR n003 FR n002 FR n001 FR n000 FR n01B FR n01A FR n019 FR n018 FR n017 FR n016 FR n015 FR n014 FR n013 FR n012 FR n011 FR n010 FR n02B FR n02A FR n029 FR n028 FR n027 FR n026 FR n025 FR n024 FR n023 FR n022 FR n021 FR n020 FR n03B FR n03A FR n039 FR n038 FR n037 FR n036 FR n035 FR n034 FR n033 FR n032 FR n031 FR n030 FR n04B FR n04A FR n049 FR n048 FR n047 FR n046 FR n045 FR n044 FR n043 FR n042 FR n041 FR n040 FR n05B FR n05A FR n059 FR n058 FR n057 FR n056 FR n055 FR n054 FR n053 FR n052 FR n051 FR n050 FR n06B FR n06A FR n069 FR n068 FR n067 FR n066 FR n065 FR n064 FR n063 FR n062 FR n061 FR n060 FR n07B FR n07A FR n079 FR n078 FR n077 FR n076 FR n075 FR n074 FR n073 FR n072 FR n071 FR n070 FR n08B FR n08A FR n089 FR n088 FR n087 FR n086 FR n085 FR n084 FR n083 FR n082 FR n081 FR n080 FR n09B FR n09A FR n099 FR n098 FR n097 FR n096 FR n095 FR n094 FR n093 FR n092 FR n091 FR n090 FR n0AB FR n0AA FR n0A9 FR n0A8 FR n0A7 FR n0A6 FR n0A5 FR n0A4 FR n0A3 FR n0A2 FR n0A1 FR n0A0 FR n0BB FR n0BA FR n0B9 FR n0B8 FR n0B7 FR n0B6 FR n0B5 FR n0B4 FR n0B3 FR n0B2 FR n0B1 FR n0B0 FR n0CB FR n0CA FR n0C9 FR n0C8 FR n0C7 FR n0C6 FR n0C5 FR n0C4 FR n0C3 FR n0C2 FR n0C1 FR n0C0 FR n0DB FR n0DA FR n0D9 FR n0D8 FR n0D7 FR n0D6 FR n0D5 FR n0D4 FR n0D3 FR n0D2 FR n0D1 FR n0D0 FR n0EB FR n0EA FR n0E9 FR n0E8 FR n0E7 FR n0E6 FR n0E5 FR n0E4 FR n0E3 FR n0E2 FR n0E1 FR n0E0 FR n0FB FR n0FA FR n0F9 FR n0F8 FR n0F7 FR n0F6 FR n0F5 FR n0F4 FR n0F3 FR n0F2 FR n0F1 FR n0F0 FR n10B FR n10A FR n109 FR n108 FR n107 FR n106 FR n105 FR n104 FR n103 FR n102 FR n101 FR n100 FR n11B FR n11A FR n119 FR n118 FR n117 FR n116 FR n115 FR n114 FR n113 FR n112 FR n111 FR n110 12 3 4 567891 0 1 1 1 2 ✽ The number in the boxes show the bit address of the RAM character :n. ("n" is RAM number : 0 to 7) Dot Dot RAM Character CONSTITUTION The dot lines and dot rows of the character RAM are determined from each address and bit of the character RAM . The RAM char- acter constitution is shown in Figure 11. Fig.10 Screen constitution 00016 00116 00216 00316 00416 00516 00616 00716 00816 00916 00A16 00B16 00C 16 00D 16 00E16 00F16 01016 01116 01216 01316 01416 01516 01616 01716 01816 01916 01A16 01B16 01C 16 01D 16 01E16 01F16 02016 02116 02216 02316 02416 02516 02616 02716 02816 02916 02A16 02B16 02C 16 02D 16 02E16 02F16 03016 03116 03216 03316 03416 03516 03616 03716 03816 03916 03A16 03B16 03C 16 03D 16 03E16 03F16 04016 04116 04216 04316 04416 04516 04616 04716 04816 04916 04A16 04B16 04C 16 04D 16 04E16 04F16 05016 05116 05216 05316 05416 05516 05616 05716 05816 05916 05A16 05B16 05C 16 05D 16 05E16 05F16 06016 06116 06216 06316 06416 06516 06616 06716 06816 06916 06A16 06B16 06C 16 06D 16 06E16 06F16 07016 07116 07216 07316 07416 07516 07616 07716 07816 07916 07A16 07B16 07C 16 07D 16 07E16 07F16 08016 08116 08216 08316 08416 08516 08616 08716 08816 08916 08A16 08B16 08C 16 08D 16 08E16 08F16 09016 09116 09216 09316 09416 09516 09616 09716 09816 09916 09A16 09B16 09C 16 09D 16 09E16 09F16 0A016 0A116 0A216 0A316 0A416 0A516 0A616 0A716 0A816 0A916 0AA 16 0AB 16 0AC 16 0AD 16 0AE 16 0AF 16 0B016 0B116 0B216 0B316 0B416 0B516 0B616 0B716 0B816 0B916 0BA 16 0BB 16 0BC 16 0BD 16 0BE 16 0BF 16 0C0 16 0C1 16 0C2 16 0C3 16 0C4 16 0C5 16 0C6 16 0C7 16 0C8 16 0C9 16 0CA 16 0CB 16 0CC 16 0CD 16 0CE 16 0CF 16 0D0 16 0D1 16 0D2 16 0D3 16 0D4 16 0D5 16 0D6 16 0D7 16 0D8 16 0D9 16 0DA 16 0DB 16 0DC 16 0DD 16 0DE 16 0DF 16 0E016 0E116 0E216 0E316 0E416 0E516 0E616 0E716 0E816 0E916 0EA 16 0EB 16 0EC 16 0ED 16 0EE 16 0EF 16 0F016 0F116 0F216 0F316 0F416 0F516 0F616 0F716 0F816 0F916 0FA 16 0FB 16 0FC 16 0FD 16 0FE 16 0FF16 10016 10116 10216 10316 10416 10516 10616 10716 10816 10916 10A16 10B16 10C 16 10D 16 10E16 10F16 11016 11116 11216 11316 11416 11516 11616 11716 11816 11916 11A16 11B16 11C 16 11D 16 11E16 11F16 Row Line 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 61 71 81 92 02 12 22 32 4 ✽ The hexadecimal numbers in the boxes show the display RAM address.

Rev.1.10 Feb 13, 2006 page 9 of 44 REJ03B0180-0110 M35075-XXXFP DISPLAY RAM Address 00016 to 11F16 Register Status

Contents

Set the displayed ROM character code. *RAM character is selected using the 8 bits from C7 to C0. When C7 to C0=(111111102) is set. And, RAM character code is set to R, G and B. DA Set display character0 A B C D E Set blinking See register BLINK2 to BLINK0 (ad- dress129 16) Do not blink. Blinking BB R G B BLINK BR BG BB Set character color (character unit) * When set C7 to C0= (11111110 2), can be set RAM character code. BR BG B R G Color Black Red Green Yellow Blue Magenta Cyan White Color Black Red Green Yellow Blue Magenta Cyan White B R G RAM character code RAM character 0 RAM character 1 RAM character 2 RAM character 3 RAM character 4 RAM character 5 RAM character 6 RAM character 7 ____ Note. The display RAM is undefined state at the AC pin. Set character background color. (character unit) *When set C7 to C0=(111111102) and register RBLK0 (address 124 16)= “1”, set coloring prohibition color. Moreover, when the blink is set, the parts other than the color set by this register are blinks. See DISPLAY FORM 2.

Rev.1.10 Feb 13, 2006 page 10 of 44 REJ03B0180-0110 M35075-XXXFP DA A B C D E REGISTERS DESCRIPTION Register Status <(S) represents space> 1 (S) 10 (S) 1 2 (S) 8 (S) 2 3 (S) 6 (S) 3 4 (S) 4 (S) 4 5 (S) 2 (S) 5 6 (S) 6 6 (S)(S) 6 (S) represents one line worth of space Leave one line worth of space in the ver- tical direction. For example, 6 (S) 6 indicates two sets of 6 lines with a line of spaces between lines 6 and 7. A line is 18 ✕ N horizontal scan lines. N is determined by the character size in the vertical direction It should be fixed to "0". Can not be used. SPACE2 Set division value (multiply value) of horizontal oscillation frequency. N1 = N1 : division value (multiply value) Σ n = 0 (DIVn ✕ 2n) Set display frequency by division value (multiply value) setting. For details, see REGISTER SUPPLEMENTARY DESCRIPTION (1). Also, set the display frequency range by registers DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1(address 121 16) in accor- dance with the display frequency. Any of this settings above is required only when EXCK1 = 0, EXCK0 = 1 and EXCK1 = 1, EXCK0 = 1. Note. The mark around the status value means the reset status by the "L" level is input to AC pin. (1) Address 12016

Rev.1.10 Feb 13, 2006 page 11 of 44 REJ03B0180-0110 M35075-XXXFP (2) Address 121 RegisterDA Status P0 output (port P0). BLNK0 output. P1 output (port P1). R signal output. P2 output (port P2). Can not be used. P3 output (port P3). G signal output. P4 output (port P4). Can not be used. P5 output (port P5). B signal output. P6 output (port P6). Can not be used. P7 output (port P7). Can not be used. For setting, see REGISTER SUPPLEMENTARY DESCRIPTION (2). Set display frequency range. EXCK0 Display clock input External synchronous (external clock) Internal synchronous Do not set External synchronous (internal clock) EXCK1 Display clock setting See REGISTER SUPPLEMENTARY DESCRIPTION (1) P0 pin output control. P1 pin output control. P2 pin output control. P3 pin output control. P4 pin output control. P5 pin output control. P6 pin output control. P7 pin output control. A B C D E Note. The mark around the status value means the reset status by the "L" level is input to AC pin.

Rev.1.10 Feb 13, 2006 page 12 of 44 REJ03B0180-0110 M35075-XXXFP (3) Address 12216 A B C D E RegisterDA Function "L" output or negative polarity output (BLNK0 output). "H" output or positive polarity output (BLNK0 output). "L" output or negative polarity output (R signal output). "H" output or positive polarity output (R signal output). "L" output. "H" output. "L" output or negative polarity output (G signal output). "H" output or positive polarity output (G signal output). "L" output. "H" output. "L" output or negative polarity output (B signal output). "H" output or positive polarity output (B signal output). "L" output. "H" output. "L" output. "H" output. Can not be used. It should be fixed to "1". It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. P0 pin data control. P1 pin data control. P2 pin data control. P3 pin data control. P4 pin data control. P5 pin data control. P6 pin data control. P7 pin data control. Note. The mark around the status value means the reset status by the "L" level is input to AC pin.

Rev.1.10 Feb 13, 2006 page 13 of 44 REJ03B0180-0110 M35075-XXXFP (4) Address 12316 A B C D E If HS is the horizontal display start location, HS = T ✕ ( 2nNP n+m) T: Period of display frequency 2007 settings are possible. m : offset value differ for the setting of the register EXCK0 and EXCK1. It shown below. Σ n = 0 RegisterDA Function Horizontal display start location is speci- fied using the 11 bits from HP10 to HP0. HP10 to HP0 = (00000000000 2) and (000001001112) setting is forbidden. HS*(shown left) shows horizontal dis- play start location this is register B/F (address 12916) = "0" is set. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. EXCK1 EXCK0 m 00 1 1 01 0 1 13 13 Do not set 19 OSD Display area Note 2 HS VS HOR VERT Monitor Screen Note 2 Note 2 Note 2 Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds.

Rev.1.10 Feb 13, 2006 page 14 of 44 REJ03B0180-0110 M35075-XXXFP (5) Address 12416 A B C D E RegisterDA Status If VS is the vertical display start location, VS = H ✕ 2nVP n T: Cycle with the horizonal synchronizing pulse 2047 settings are possible. The vertical start location is specified using the 11 bits from VP10 to VP0. VP10 to VP0 = (00000000000 2) setting is forbidden. HS*(shown left) shows horizontal dis- play start location this is register B/F (address 12916) = "0" is set. Sets the blanking mode of RAM charac- ter. See DISPLAY FORM 2. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. Matrix-outline size. Charcter size. (Note 3) It should be fixed to "0". Can not be used. Σ n = 0 Notes 1. The mark around the status value means the reset status by the "L" level is input to AC pin. 2. Set up the horizontal and vertical display start location so that display range may not exceed it. Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds. 3. The part of the appointed color by BR, BG and BB of the display RAM changes that the blanking is "OFF". OSD Display area Note 2 HS VS HOR VERT Monitor Screen Note 2 Note 2 Note 2

Rev.1.10 Feb 13, 2006 page 15 of 44 REJ03B0180-0110 M35075-XXXFP (6) Address 12516 DSP0 DSP1 DSP2 DSP3 DSP4 DSP5 DSP6 DSP7 DSP8 DSP9 DSP10 DSP11 TEST21 TEST22 TEST23 A B C D E RegisterDA Status Sets the display mode of line 1. Sets the display mode of line 2. Sets the display mode of line 3. Sets the display mode of line 4. Sets the display mode of line 5. Sets the display mode of line 6. Sets the display mode of line 7. Sets the display mode of line 8. Sets the display mode of line 9. Sets the display mode of line 10. Sets the display mode of line 11. Sets the display mode of line 12. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. It should be fixed to "0". Can not be used. The display modes of display screen inside n+1 line by DSPn (n=0 to 11) The display mode decided by the combination with registers BLK1 and BLK0 (address 12916). Settings are given below. For detail, see DISPLAY FORM 1 (1). BLK1 BLK0 DSPn="0" Matrix-outline border Character Border Matrix-outline DSPn="1" Matrix-outline Border Matrix-outline Charcter (At register BCOL="0") Note. The mark around the status value means the reset status by the "L" level is input to AC pin.

Rev.1.10 Feb 13, 2006 page 16 of 44 REJ03B0180-0110 M35075-XXXFP (7) Address 12616 LIN2 LIN3 LIN4 LIN5 LIN6 LIN7 LIN8 LIN9 V1SZ0 V1SZ1 VSZ1L0 VSZ1L1 VSZ1H0 VSZ1H1 TEST24 A B C D E RegisterDA Status H: Cycle with the horizontal synchronizing pulse V1SZ1 H: Cycle with the horizontal synchronizing pulse VSZ1L1 VSZ1L0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot VSZ1H1 VSZ1H0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse It should be fixed to "0". Can not be used. V1SZ0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot Character size setting in the vertical direction for the 2nd line. Character size setting in the vertical direction for the 3rd line. Character size setting in the vertical direction for the 4th line. Character size setting in the vertical direction for the 5th line. Character size setting in the vertical direction for the 6th line. Character size setting in the vertical direction for the 7th line. Character size setting in the vertical direction for the 8th line. Character size setting in the vertical direction for the 9th line. Character size setting in the vertical direction for the 1st line. (display monitor 1 to 12 line) Character size setting in the vertical direction (display monitor 1 line) at "0" state in register LIN2 to LIN17 (address 12616, 12716). Character size setting in the vertical direction (display monitor 1 line) at "1" state in register LIN2 to LIN17 (address 126 16, 12716). The vertical dot size for line n in the character dot lines (18 vertical lines) is set using LINn (n = 2 to 17). Dot size can be selected between 2 types for each dot line. For dot size, see the below registers. Line 1 and lines 2 to 12 can be set independent of one another. 1st line 2nd to 12th line LINn = "0" LINn = "1" Refer to VSZ1L0 and VSZ1L1 Refer to VSZ2L0 and VSZ2L1 Refer to VSZ1H0 and VSZ1H1 Refer to VSZ2H0 and VSZ2H1 Note. The mark around the status value means the reset status by the "L" level is input to AC pin.

Rev.1.10 Feb 13, 2006 page 17 of 44 REJ03B0180-0110 M35075-XXXFP (8) Address 12716 LIN10 LIN11 LIN12 LIN13 LIN14 LIN15 LIN16 LIN17 V18SZ0 V18SZ1 VSZ2L0 VSZ2L1 VSZ2H0 VSZ2H1 TEST25 A B C D E RegisterDA Status H: Cycle with the horizontal synchronizing pulse VSZ2L1 H: Cycle with the horizontal synchronizing pulse H: Cycle with the horizontal synchronizing pulse VSZ2H1 VSZ2H0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot It should be fixed to "0". Can not be used. VSZ2L0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot Character size setting in the vertical direction for the 10th line. Character size setting in the vertical direction for the 11th line. Character size setting in the vertical direction for the 12th line. Character size setting in the vertical direction for the 13th line. Character size setting in the vertical direction for the 14th line. Character size setting in the vertical direction for the 15th line. Character size setting in the vertical direction for the 16th line. Character size setting in the vertical direction for the 17th line. Character size setting in the vertical direction for the 18th line. (display monitor 1 to 12 line) Character size setting in the vertical direction (display monitor for 2 to 12 line) at "0" state in register LIN2 to LIN17 (address 126 16, 12716). The vertical dot size for line n in the character dot lines (18 vertical lines) is set using LINn (n = 2 to 17). Dot size can be selected between 2 types for each dot line. For dot size, see the below registers. Line 1 and lines 2 to 12 can be set independent of one another. 1st line 2nd to 12th line LINn = "0" LINn = "1" Refer to VSZ1L0 and VSZ1L1 Refer to VSZ2L0 and VSZ2L1 Refer to VSZ1H0 and VSZ1H1 Refer to VSZ2H0 and VSZ2H1 Character size setting in the vertical direction (display monitor for 2 to12 line) at "1" state in register LIN2 to LIN17(address 126 16, 12716). Note. The mark around the status value means the reset status by the "L" level is input to AC pin.

Rev.1.10 Feb 13, 2006 page 18 of 44 REJ03B0180-0110 M35075-XXXFP (9) Address 12816 RR RG RB FR FG FB TEST26 TEST27 TEST28 BETA14 HSZ10 TEST31 HSZ20 TEST32 TEST29 A B C D E RegisterDA Status Sets the raster color of all blankings. Set the blanking color of the Border size, or the shadow size. Charcter size setting in the horizontal direction for the first line. T: Display frequency cycle Charcter size setting in the horizontal direction for the 2nd line to 12th line. T: Display frequency cycle Color Black Red Green Yellow Blue Magenta Cyan White RB RG RR Color Black Red Green Yellow Blue Magenta Cyan White FB FG FR Matrix-outline display (12 ✕ 18 dot) Matrix-outline display (14 ✕ 18 dot) It should be fixed to "0". Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Note. The mark around the status value means the reset status by the "L" level is input to AC pin. It should be fixed to “0”. Can not be used. It should be fixed to "0". Can not be used. HSZ10 Horizontal direction size 1T/dot 2T/dot HSZ20 Horizontal direction size 1T/dot 2T/dot

Rev.1.10 Feb 13, 2006 page 19 of 44 REJ03B0180-0110 M35075-XXXFP (10) Address 12916 BCOL B/F VMASK POLV POLH BLK0 BLK1 SYAD RAMERS STOP DSPON BLINK0 BLINK1 BLINK2 TEST30 A B C D E RegisterDA Status Blanking of BLK0, BLK1 All raster blanking Synchronize with the leading edge of horizontal synchronization. Synchronize with the trailing edge of horizontal synchronization. Do not mask by VERT input signal Mask by VERT input signal VERT pin is negative polarity VERT pin is positive polarity HOR pin is negative polarity HOR pin is positive polarity ( When DSPn (address 125 16) = "0" ) Border display of character Shadow display of character RAM not erased RAM erased Oscillation of clock for display Stop the oscillation of clock for display Display OFF Display ON Divided into 64 of vertical synchronous signal Divided into 32 of vertical synchronous signal It should be fixed to "0". Can not be used. Sets all raster blanking Synchronize with the front porch or back porch of the horizontal synchronization signal. Set mask at phase comparison operating. Set VERT pin polarity. Set HOR pin polarity. Set blanking mode. See DISPLAY FORM 1 (1). See DISPLAY FORM 1 (2). Set blinking duty ratio. Set blinking frequency. BLINK1 BLINK0 Duty Blinking OFF 25% 50% 75% Blanking mode Matrix-outline size Character size Border size Matrix-outline size BLK1 BLK0 When register RAMERS is set to "1", do not stop the display clock. There is no need to reset because there is no register for this bit. Note. The mark around the status value means the reset status by the "L" level is input to AC pin.

Rev.1.10 Feb 13, 2006 page 20 of 44 REJ03B0180-0110 M35075-XXXFP Fig. 12 Example of external clock input Horizontal synchronous signal External clock Number of clock (N1) REGISTER SUPPLEMENTARY DESCRIPTION (1) Setting external clock input and display frequency mode Setting external clock input and display frequency mode (by use of EXCK0, EXCK1 (121 16), and DIV10 to DIV0 (12016) as explained here following. Fosc = 6.3 to 80 MHz (VDD = 4.75 to 5.25 V) Fosc = 6.3 to 40 MHz (VDD = 2.50 to 3.50 V) Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronous signal. And input from HOR pin a constant period continuous horizontal synchronous signal. Never stop inputting the clock while displaying. Do not have to set a display frequency because the clock just as it is entered from outside is used as the display clock. Fosc = 20 to 110 MHz (V DD = 4.75 to 5.25 V) Clock input from the TCK pin is unnecessary. The multiply clock of the internally generated horizontal synchronous signal is used as the display clock. The display frequency is set by setting the multiply value of the horizontal synchronous frequency (of the display frequency) in DIV10 to DIV0 (address 120 16). Also, set the display frequency range. (See the next page.) Display frequency is calculated using the below expression. Display frequency = Horizontal synchronous frequency x Multiply value Σ n = 0 2nDIVn Fosc = 20 to 110 MHz (VDD = 4.75 to 5.25 V) Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronous signal. And input from HOR pin a constant-period continuous horizontal synchronous signal. Never stop inputting the clock while displaying. An internal clock which is in sync with the external input clock is used as the display clock. Because the display frequency equals the external clock frequency, set N1 (division value) that satisfies the below expressions to DIV10 to DIV0 (address 120 16) for make the display frequency is equal to the external clock frequency. N1 = external clock frequency / horizontal synchronous frequency N1 = Also, set the display frequency range. (See the next page.)

Rev.1.10 Feb 13, 2006 page 21 of 44 REJ03B0180-0110 M35075-XXXFP (2) To set display frequency range Whenever setting display frequency (when EXCK1 = "0", EXCK0 = "1", or EXCK1 = "1", EXCK0 = "1"), always set the display frequency range in accordance with the display frequency. This range is set from DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1 (address 121 16). Frequency ranges are given here below. (3) Notes on setting display frequency To change external clock (display) frequency or horizontal syn- chronization frequency, always use the following procedures. To set EXCK1 = "0", EXCK0 = "1" (a) Turn the display OFF. … DSPON (address 12916) = "0" (b) Set the display frequency. … Set from DIV10 to DIV0(address 12016) , DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1 (address 12116). (c) Wait 20 ms while the horizontal synchronization signal is being input. (d) Turn the display ON. … DSPON (address 12916) = "1" To set EXCK1 = "1", EXCK0 = "1" (a) Turn the display OFF. … DSPON (address 12916) = "0" (b) Set the display frequency. … Set from DIV10 to DIV0(address 12016) , DIVS0, DIVS1, DIVS2, RSEL0 and RSEL1 (address 12116). (c) Wait 20 ms while the horizontal synchronization signal and external clock are being input. (d) Turn the display ON. … DSPON (address 12916) = "1" RSEL1 RSEL0 DIVS1 DIVS0 DIVS2 Display frequency range MHz 100.0 to 110.0 92.0 to 100.0 73.0 to 92.0 66.5 to 73.0 61.0 to 66.5 49.0 to 61.0 45.5 to 49.0 36.5 to 45.5 33.5 to 36.5 30.5 to 33.5 24.5 to 30.5 23.0 to 24.5 20.0 to 23.0

Rev.1.10 Feb 13, 2006 page 22 of 44 REJ03B0180-0110 M35075-XXXFP Fig. 13 Display form DISPLAY FORM 1 M35075-XXXFP has the following four display forms. (1) ROM character blanking mode Character size : Blanking same as the character size. Border size : Blanking the background as a size from character. Matrix-outline size : Blanking the background 12 ✕ 18 dot. All blanking size : When set register BCOL to "1", all raster area is blanking. The display mode and blanking mode can be set line-by-line, as follows, from registers BCOL, BLK1, BLK0 (address 12916), DSP0 to DSP11 (address 12516). BCOL BLK1 BLK0 Display mode Matrix-outline border display Character display Border display Matrix-outline display Matrix-outline border display Character display Border display Matrix-outline display Blanking mode Matrix-outline size Character size Border size Matrix-outline size All blanking size Display mode Matrix-outline display Border display Matrix-outline display Character display Matrix-outline display Border display Matrix-outline display Character display Blanking mode Matrix-outline size Border size Matrix-outlinesize Character size All blanking size 12 dots (Note 2) 18 dots 12 dots 12 dots 12 dots (Note 2) Scanning <Register BCOL=“0”> (Note 1) R,GorB output BLNK0 output color setting Character color : R,G,B of display RAM (Character unit) Border color :Register FR,FG,FB (Display unit) Matrix-outline color :BR,BG,BB of display RAM (Character unit) (a) Matrix-outline and border display (Matrix-outline size) Character color : R,G,B of display RAM (Character unit) Matrix-outline color :BR,BG,BB of display RAM (Character unit) (d) Matrix-outline display (Matrix-outline size) ( ) is blanking mode. Character color : R,G,B of display RAM (Character unit) Border color :BR,BG,BB of display RAM (Character unit) (c) Border display (Border size) Character color : R,G,B of display RAM (Character unit) (b) Character display (Character size) Note 1. When register BCOL is set to "1", the raster range of the display modes set respectively by BLK1 and BLK0 are colored by registers RR, RG, and RB (address 12816). And the blanking mode is set all blanking size (all raster size) regardless of the BLK1 and BLK0 settings. Note 2. The horizontal size of the full matrix-outline size can be set to 14 dots by register BETA14 (address 12816). BLNK0 can also be output at 14 dots. Line of DSPn = "0" Line of DSPn = "1"

Rev.1.10 Feb 13, 2006 page 23 of 44 REJ03B0180-0110 M35075-XXXFP (2) Shadow display When border display mode, if set SYAD (address 12916) = "0" to "1", it change to shadow display mode. Border and shadow display are shown below. Set shadow display color by BR, BG and BB of display RAM or by register FR, FG and FB. Fig.14 Border and shadow display Register SYAD(12916 address) = “0” Border display Register SYAD(12916 address) = “1” Shadow display Note : Border display is invalid in RAM characters.

Rev.1.10 Feb 13, 2006 page 24 of 44 REJ03B0180-0110 M35075-XXXFP DISPLAY FORM 2 This IC can display both ROM character and RAM character at the same time. The display form is shown in Figure 15 and 16. Fig.15 Display form1 Continue to Next Display mode Matrix-outline display Character display (Note1) Matrix-outline display Character display (Note1) Blanking mode Matrix-outline size Character size (Note2) All blanking size All blanking size RBLK0 BCOL (1) RAM character blanking mode R,GorB output BLNK0 output Scanning 12dots (Note 2) RAM Character ROM Character R,GorB output BLNK0 output Scanning ScanningScanning 12dots (Note 2) RAM Character ROM Character 12dots (Note 2) RAM Character ROM Character 12dots (Note 2) RAM Character ROM Character Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) BR, BG, BB of display RAM : (Character unit) Display mode : Matrix-outline display (b) (Matrix- outline size) Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) BR, BG, BB of display RAM : Border color (Character unit) Display mode : Matrix-outline display (c) (Matrix- outline size) Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) BR, BG, BB of display RAM : Matrix-outline color (Character unit) Display mode : Matrix-outline display (d) (Matrix- outline size) Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) BR, BG, BB of display RAM : Matrix-outline color (Character unit) FR, FG, FB of register : Border color (Display unit) Display mode : Matrix-outline display (a) (Matrix- outline size)( ) is blanking mode. Refer to DISPLAY FORM 1 about (a)-(d). Note1: The part of the appointed color by BR, BG and BB of the display RAM changes that is not coloring. Note2: The part of the appointed color by BR, BG and BB of the display RAM changes that the blanking is "OFF" < Regiser BCOL = “0”, RBLK0 = “0”> (Note 1)

Rev.1.10 Feb 13, 2006 page 25 of 44 REJ03B0180-0110 M35075-XXXFP Fig. 16 Display form2 < Register BCOL = “0”, RBLK0 = “1”> (Note 1) Note 1 : When register BCOL = "1", the raster range of the display modes set respectively by RBLK0 is colored by register RR, RG and RB (address 12816) . And the blanking mode is set all blanking size (all raster size) independent of the RBLK0 settings. Note 2 : The horizontal size of the full matrix-outline size can be set to 14 dots by register BETA14 (address 12816). BLNK0 can also be out- put at 14 dots. Note 3 : When display mode (setting by register BLK1, BLK0, DSPn) is Matrix-outline display or Matrix-outline border display, register RBLK0= "1" setting (coloring prohibition color setting) is invalid. 12dots (Note 2) RAM Character ROM Character 12dots (Note 2) RAM Character ROM Character 12dots (Note 2) RAM Character ROM Character 12dots (Note 2) RAM Character ROM Character R,GorB output BLNK0 output Scanning R,GorB output BLNK0 output Scanning Scanning Scanning Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) . BR, BG, BB of display RAM : Coloring prohibition (Character unit) color Display mode : Character display (b) (Character size) Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) BR, BG, BB of display RAM : Coloring prohibition Border color (Character unit) color Display mode : Character display (c) (Character size) Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) BR, BG, BB of display RAM : (Note 3) Matrix-outline color (Character unit) Display mode : Matrix-outline display (d) (Matrix-outline size) (Note 3) Color setting ( RAM character setting) (ROM character setting) R, G, B of display RAM : RAM character code No. Character color (Character unit) BR, BG, BB of display RAM : (Note 3) Matrix-outline color (Character unit) FR, FG, FB of register : Border color (Display unit) Display mode : Matrix-outline display (a) (Matrix-outline size) (Note 3) ( ) is blanking mode. Refer to DISPLAY FORM 1 about (a)-(d).

Rev.1.10 Feb 13, 2006 page 26 of 44 REJ03B0180-0110 M35075-XXXFP 000 1 00000 0000000 000 1 00000 0000000 000 1 00000 0000000 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00111 1111100 000 1 00000 0000000 000 1 00000 0000000 000 1 00000 0000000 0 010 00000 00 00 0 00 0 010 00000 00 00 0 00 0 010 01111 11 11 1 10 0 010 01000 00 00 0 10 0 010 01001 11 10 0 10 0 010 01010 00 01 0 10 0 010 01010 00 01 0 10 0 010 01010 00 00 0 10 0 010 01010 01 11 0 10 0 010 01010 00 01 0 10 0 010 01010 00 01 0 10 0 010 01010 00 11 0 10 0 010 01001 11 01 0 10 0 010 01000 00 00 0 10 0 010 01000 00 00 0 10 0 010 01111 11 11 1 10 0 010 00000 00 00 0 00 0 010 00000 00 00 0 00 (1)200 (2)20116 (3)20216 (4)20316 (5)20416 (6)20516 (7)20616 (8)20716 (9)20816 (10)20916 (11)20A16 (12)20B16 (13)20C16 (14)20D16 (15)20E16 (16)20F16 (17)21016 (18)21116 21216 21F16 0 100 1 11 1 11 1 11 11 1 0 100 1 11 1 11 1 11 11 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 00 0 00 0 00 00 1 0 100 1 11 1 11 1 11 11 1 0 100 1 11 1 11 1 11 11 1 DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 (1)20016 (2)20116 (3)20216 (4)20316 (5)20416 (6)20516 (7)20616 (8)20716 (9)20816 (10)20916 (11)20A16 (12)20B16 (13)20C16 (14)20D16 (15)20E16 (16)20F16 (17)21016 (18)21116 21216 21F16 Address For example : RAM character 0 BLUE GREEN RED Note 1 : After clearing or setting all character RAM areas, and use the RAM characters. Note 2 : The RAM character's dots are set RED, GREEN and BLUE data, which are controlled by BS, GS and RS bit. (Can be set at same time) Example of setting RAM character data (R+G+B display image) DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Example of setting the RED bit code data Example of setting the GREEN bit code data Example of setting the GREEN bit code data Address (1)20016 (2)20116 (3)20216 (4)20316 (5)20416 (6)20516 (7)20616 (8)20716 (9)20816 (10)20916 (11)20A16 (12)20B16 (13)20C16 (14)20D16 (15)20E16 (16)20F16 (17)21016 (18)21116 21216 21F16 Address Can not used Can not used Fig.17 Setting of the data of RAM character 123 4 5 6 789 1 011 12 (Dot) (Dot) (Dot) 123 4 5 6 789 1 01112 (Dot) 123 4 5 6 789 1 01112 (Dot) (Dot) 123 4 5 6 789 1 011 12 (Dot) (Dot)

Rev.1.10 Feb 13, 2006 page 27 of 44 REJ03B0180-0110 M35075-XXXFP CHARACTER FONT Images are composed on a 12 ✕ 18 dot matrix, and characters can be linked vertically and horizontally with other characters to al- low the display the continuous symbols. Character code FF 16 is fixed as a blank without background. Therefore, cannot register a character font in this code. Fig.18 Example of border display When the character extends to the top line of the matrix, no border is left at the top. Note: Hatching represents border. When the character extends to the bottom (18th) line of the matrix, no border is left at the bottom. 12 dots 18 dots Note: Border

Rev.1.10 Feb 13, 2006 page 28 of 44 REJ03B0180-0110 M35075-XXXFP DATA INPUT EXAMPLE Data of display RAM and display control registers can be set by the I2C-BUS serial input function. Example of data setting is shown in Figure 19 (at EXCK0 = "1", EXCK1 = "0" setting). Fig. 19 Example of data setting DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 RemarksAddress/data Address 12016 Data 120 16 Data 121 16 Data 122 16 Data 123 16 Data 124 16 Data 125 16 Data 126 16 Data 127 16 Data 128 16 Data 129 16 Address 20016 Data 200 16 Data 2F1 16 Address 20016 Data 200 16 Data 2F1 16 Address 20016 Data 200 16 Data 2F116 Address00016 Data 000 16 Data 11F 16 Address 12916 Data 129 16 System set up (Note 3) Address setting Frequency value setting Frequency range setting Output setting Horizontal display location setting Vertical display location setting Display form setting Character size setting Character size setting Color, character size setting Display OFF Be stable/Waiting time Background coloring Character color Character code 200 m sec hold Blink -ing Bit color Bit code/RED Bit code/GREEN Bit code/BLUE RED•bit code setting GREEN•bit code setting BLUE•bit code setting DAF Address setting 20 m sec hold Bit color Bit color Notes 1 : Input a continuous clock of constant period from the TCK pin. Also, input a horizontal synchronous signal into the HOR pin and a vertical synchronous signal into the VERT pin. 2: Matrix-outline display in this data. ____ Secure the waiting time of 200ms after releasing AC, and set data from setting the display frequency (setting of the register). 4: Set data to Display RAM and Display character RAM at internal clock (display clock) is stabilized. Address setting Address setting Address setting Address setting Character setting Display ON (Note 2) 00 00000100100000 00 000 DIV10 DIV9 DIV8 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 00 1 RSEL1RSEL0 DIVS2 DIVS1 DIVS0 11 1 01011 00 00000111101011 00 000 HP10 HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 00 000 VP10 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 00 00000000000000 00 00000000000000 00 00000000000000 00 00000000000000 00 000000000 POLH POLV 000 00 00001000000000 00 01 FR000B FR000A FR0009 FR0008 FR0007 FR0006FR0005 FR0004FR0003 FR0002 FR0001 FR0000 00 01 FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 00 00001000000000 00 10 FR000B FR000A FR0009 FR0008 FR0007 FR0006FR0005 FR0004FR0003 FR0002 FR0001 FR0000 00 1 0 FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 00 00001000000000 01 0 0 FR000B FR000A FR0009 FR0008 FR0007 FR0006FR0005 FR0004FR0003 FR0002 FR0001 FR0000 01 0 0 FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110 00 00000000000000 0B B B G B R BLINK BGR C 7 C 6 C 5 C 4C 3C 2C 1 C 0 0B B B G B R BLINK BGR C 7 C 6 C 5 C 4C 3C 2C 1 C 0 00 00000100101001 00 000100011 POLH POLV 000

Rev.1.10 Feb 13, 2006 page 29 of 44 REJ03B0180-0110 M35075-XXXFP Fig.20 Example of the M35075-XXXFP peripheral circuit (Internal synchronous. At EXCK1 = "0", EXCK0 = "0") Fig.21 Example of the M35075-XXXFP peripheral circuit (External synchronous. At EXCK1 = "0", EXCK0 = "1") 1µF (note 1) (note 2) CPOUT V SS2 AC TCK VDD1 VDD2 VERT HOR P5/B P3/G P1/R P0/BLNK0 VSS1 +5V +5V BLNK0 R G B + – – + M35075-XXXFP NC NC NC BIN 1.0kΩ 0.1µF 470PF CS SCK/SCL SIN/SDA Note : Connect CS pin to VDD at the time of I2C-Bus communication use. Note 1: Use this 1% precision element Note 2: Use this 10% precision element (note 2) 100µF 1µF 0.01µF 100µF 1µF 0.01µF Synchronous signal generator Microcomputer Horizontal synchronors signal (5V) Vertical synchronors signal (5V) 1µF 100µF 1µF 0.01µF 100µF 1µF 0.01µF CPOUT V SS2 AC CS SCK/SCL SIN/SDA TCK V DD1 VDD2 VERT HOR P5/B P3/G P1/R P0/BLNK0 VSS1 +3V or +5V +3V or +5V BLNK0 R G B + – – + M35075-XXXFP NC NC NC BIN Synchronous signal generator Microcomputer External clock Horizontal synchronors signal (3V or 5V) Vertical synchronors signal (3V or 5V) Notes 1: CPOUT pin can be opened when use only EXCK1= “0” and EXCK= “0.” 2: Connect CS pin to VDD at the time of I2C-Bus communication use.

Rev.1.10 Feb 13, 2006 page 30 of 44 REJ03B0180-0110 M35075-XXXFP Fig.22 Example of the M35075-XXXFP peripheral circuit (External clock mode 2. At EXCK1 = "1", EXCK0 = "1") 1.0kΩ 0.01µF 47PF 1µF CPOUT V SS2 AC TCK VDD1 VDD2 VERT HOR P5/B P3/G P1/R P0/BLNK0 VSS1 +5V +5V BLNK0 R G B + – – + M35075-XXXFP NC NC NC BIN CS SCK/SCL SIN/SDA Note : Connect CS pin to VDD at the time of I2C-Bus communication use. Note 1: Use this 1% precision element Note 2: Use this 10% precision element 100µF 1µF 0.01µF 100µF 1µF 0.01µF Synchronous signal generator Microcomputer External clock Horizontal synchronors signal (5V) Vertical synchronors signal (5V) (note 1) (note 2) (note 2)

Rev.1.10 Feb 13, 2006 page 31 of 44 REJ03B0180-0110 M35075-XXXFP DATA INPUT 1 (1) The16-bit communication function (a)Serial data should be input with the LSB first. (b)The address consists of 16 bits. (c)The data consists of 16 bits. Fig.23 Serial input timing (d)The 16 bits in the SCK after the CS signal has fallen are the address, and for succeeding input data, the address is incremented every 16 bits. Therefore, it is not necessary to in put the address from the second data. Note. Stop the input to SCK pin and fix it to “H” at CS pin “H” level. CS N = 1,2,3……… SCK SIN LSB MSB LSB MSB LSB MSB Address(16 bits) Data(16 bits) N Data(16 bits) N + 1

Rev.1.10 Feb 13, 2006 page 32 of 44 REJ03B0180-0110 M35075-XXXFP (2)Timing requirements Data input Fig. 24 Serial input timing requirements Symbol tw (SCK) tsu(CS) th(CS) tsu(SIN) th(SIN) tword Parameter SCK width CS setup time CS hold time SIN setup time SIN hold time 1 word writing time Min. 200 200 200 200 Typ. Limits Unit ns ns µs ns ns µs Max. Remarks See Figure 24 tsu(CS) tw(SCK) tw(SCK) tsu(SIN) th(SIN) th(CS) tw(CS) 1µs(min.) tword more than 2 µs 12 1 2 13 14 15 16… 11 2 1 31 41 51 6… CS SCK SIN SCK CS

Rev.1.10 Feb 13, 2006 page 33 of 44 REJ03B0180-0110 M35075-XXXFP Fig.25 Start state / Stop state Fig.26 Control byte configuration DATA INPUT 2 (1) I2C-Bus communication function This IC has a built-in data transmission interface which utilizes 2 unidirectional buses. In communications, this IC functions as a slave reception device. Must connect CS pin to “H” at the time of I2C-Bus communi- cation use. The IC is synchronized with the serial clock (SCL) sent from the master device and receives the data (SDA). Communications are controlled from the start/stop states. Also, always in put the control byte after attaining the start state. The below chart shows the start/stop state and control byte configuration. SCL SDA Start state Stop stateData receive Data modify enable Control byte: 7C16(Fixed) Slave address R/W 01111100 (0: Written)

Rev.1.10 Feb 13, 2006 page 34 of 44 REJ03B0180-0110 M35075-XXXFP (2) Data input (Sequence) (a) Addresses are consists of 16 bits. (b) Data is consists of 16 bits. (c) Addresses and data are communicated in 8-bit units. Input the lower 8 bits before the upper 8 bits. Make input from the MSB side. (d) After the start state has been attained and the control byte (7CH) received, the next 16 bits (2 bytes) are for inputting the address. Addresses are increased in increments for every 16 bits (2 bytes) of data input thereafter. As a result, it is not necessary to input the address from the second data. Note:During external synchronous , do not stop the external clock input from the TCK pin while inputting data. Fig.27 Data input sequence ACK* (Acknowledge) : Output the acknowledge signal whenever one byte input after the start state. Output the acknowledge signal and recieve the data thereafter when match the slave address (7CH). S T A R T S P M S B A C K A C K A C K A C K A C K A C K L S B M S B L S B M S B L S B M S B L S B M S B L S B S T O P Control byte (7 CH) Lower address (N ) Upper address (N ) Lower data (N ) Upper data (N ) lower data (N + 1) SDA

Rev.1.10 Feb 13, 2006 page 35 of 44 REJ03B0180-0110 M35075-XXXFP ParameterSymbol fCLK tHIGH tLOW tR tF tHD : STA tSU : STA tHD : DAT tSU : DAT tSU : STO tBUF tSP Clock frequency HIGH period of Clock LOW period of Clock SDA & SCL rise time SDA & SCL fall time Hold time at START status Set up time at START status Data input hold time Data input setup time Set up time at STOP state Bus release time Input filter / spike suppress (SDA & SCL pin) Min. 4000 4700 4000 4700 250 4000 4700 N/A Max. 100 1000 300 N/A Min. 600 1300 20+ (Note) 0.1CB 20+(Note) 0.1CB 600 600 100 600 1300 Max. 400 300 300 Unit Limits Typ. mode High-speed mode KHz ns ns ns ns ns ns ns ns ns ns ns Remarks Note. CB = total capacitance of 1 bus line. (2) Timing requirements Data input Time must be re- leased bus before next transmission Only at START state repeating generation Fig.28 Data input timing SCL SDA t SP tsu : STA tHD : STA tHD : DAT tSU : DAT tF tHIGH tLOW tR tSU : STO tBUF

Rev.1.10 Feb 13, 2006 page 36 of 44 REJ03B0180-0110 M35075-XXXFP Parameter Supply voltage Unit V mA V V kΩ V Min. 4.75 3.5 0.6VDD Parameter Supply voltage Supply current "H" level output voltage "L" level output voltage __ __ Pull-up resistance AC, CS External clock input width Ta = –20 to +85°C VDD = 5.00V VDD = 4.75V, IOH = -0.4mA VDD = 4.75V, IOH = -0.05mA VDD = 4.75V, IOL = 0.4mA VDD = 4.75V, IOL = 0.05mA VDD = 4.75V, IOL = 3.0mA VDD = 5.00V 4.75V ≤ VDD ≤ 5.25V Unit V V V V V V MHz MHz MHz MHz kHz kHz Symbol V DD VIH VIL FOSC H.sync Symbol VDD VI VO Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to V SS . Ta = +25 °C Ratings –0.3 to +6.0 VSS –0.3 ≤ VI ≤ VDD +0.3 VSS ≤ VO ≤ VDD +300 –20 to +85 –40 to +125 Unit V V V mW Typ. 5.0 3.0 VDD VDD Min. 4.75 2.50 0.8V DD 0.7VDD 6.3 6.3 20.0 20.0 15.0 15.0 Max. 5.25 3.50 VDD VDD 0.2VDD 0.3VDD 80.0 40.0 110.0 110.0 130.0 60.0 Limits RECOMMENDED OPERATING CONDITIONS (VDD = 5.00V, Ta = 25°C, unless otherwise noted) Symbol VDD IDD VOH VOL R I VTCK Limits Max. 5.25 0.4 100 0.9VDD P0 to P7 (Note1) CPOUT P0 to P7 (Note2) CPOUT SIN/SDA Typ. 5.0 SCK/SCL, SIN/SDA "H" level input voltage __ __ AC, CS, HOR, VERT SCK/SCL, SIN/SDA __ __ AC, CS, HOR, VERT Oscillating frequency for display Horizontal synchronous signal input frequeney Notes 1. The current from the IC must not exceed – 0.4 mA/port at any of the port pins (P0 to P7). 2. The current flowing into the IC must not exceed 0.4 mA/port at any of port pins (P0 to P7). Test conditions ELECTRICAL CHARACTERISTICS 1 (VDD = 5.00V, Ta = –20 to +85°C, unless otherwise noted) (VDD = 5.00V, Ta = –20 to +85°C, unless otherwise noted) "L" level input voltage Internal clock mode External clock mode 1 External clock mode 2 VDD = 4.75 to 5.25 V VDD = 2.50 to 3.50 V VDD = 4.75 to 5.25 V VDD = 4.75 to 5.25 V VDD = 4.75 to 5.25 V VDD = 2.50 to 3.50 V

Rev.1.10 Feb 13, 2006 page 37 of 44 REJ03B0180-0110 M35075-XXXFP Unit V mA V V kΩ V Min. 2.50 2.30 0.9VDD Parameter Supply voltage Supply current “H” level output voltage “L” level output voltage __ __ Pull-up resistance AC, CS External clock input width Test conditions Ta = –20 to +85°C V DD = 3.00V VDD = 2.70V, IOH = -0.1mA VDD = 2.70V, IOH = 0.1mA VDD = 3.00V 2.50V ≤ VDD ≤ 3.50V ELECTRICAL CHARACTERISTICS 2 V DD =3V (VDD = 3.00V, Ta = 25°C, unless otherwise noted) Symbol VDD IDD VOH VOL R I VTCK Limits Max. 3.50 0.4 150 VDD P0 to P7 (Note1) P0 to P7 (Note2) Typ. 3.00 Notes 1. The current from the IC must not exceed – 0.1 mA/port at any of the port pins (P0 to P7). 2. The current flowing into the IC must not exceed 0.1 mA/port at any of port pins (P0 to P7).

Rev.1.10 Feb 13, 2006 page 38 of 44 REJ03B0180-0110 M35075-XXXFP NOTE FOR SUPPLYING POWER (1)Timing of power supplying to AC pin The internal circuit of M35075-XXXFP is reset when the level of the auto clear input pin AC is "L". This pin in hysteresis input with the pull-up resistor. The timing about power supplying of AC pin is shown in Figure 29. DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders. (1) M35075-XXXFP mask ROM order confirmation form (2) 24P2Q mark specification form (3) ROM data : EPROMs or floppy disks *In the case of EPROMs, thres sets of EPROMs are required per pattern. *In the case of floppy disks, 3.5-inch 2HD disk (1BM format) is required per pattern. PRECAUTION FOR USE Notes on noise and latch-up In order to avoid noise and latch-up, connect a bypass capacitor (≈0.1µF) directly between the V DD1 pin and VSS1 pin, and the VDD2 pin and VSS2 pin using a heavy wire. Fig.29 Timing of power supplying to AC pin After supplying the power (VDD and VSS ) to M35075-XXXFP and the supply voltage becomes more than 0.8 ✕ VDD , it needs to keep VIL time; tw of the AC pin for more than 1ms. Start inputting from microcomputer after AC pin supply voltage becomes more than 0.8 ✕ VDD and keeping 200ms wait time. (2)Timing of power supplying to VDD1 and VDD2 . Supply power to VDD1 and VDD2 at the same time. Note for waveform timing of the horizontal signals to the HOR pin Set horizontal synchronous signal edge* waveform timing to under 5ns and input to HOR pin. Set only the side which set by B/F register waveform timing under 5ns and input to HOR pin. *: Set front porch edge or back porch edge by B/F register. Voltage [V] VDD 0.8 x VDD 0.2 x VDD Supply voltage more than 1ms tW tS Time t [s] Data input disable VAC (AC pin input voltage) 90% 10% tf tr Horizontal synchronous signal

Rev.1.10 Feb 13, 2006 page 39 of 44 REJ03B0180-0110 M35075-XXXFP STANDARD ROM TYPE : M35075-001FP M35075-001FP is a standard ROM type of M35075-XXXFP. The character patterns are fixed to the contents of Figure 30 to 33.

Rev.1.10 Feb 13, 2006 page 40 of 44 REJ03B0180-0110 M35075-XXXFP Fig.30 M35075-001FP character patterns (1) 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C 16 0D 16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C 16 2D 16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 3F16

Rev.1.10 Feb 13, 2006 page 41 of 44 REJ03B0180-0110 M35075-XXXFP Fig.31 M35075-001FP character patterns (2) 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C 16 4D 16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C 16 6D 16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16

Rev.1.10 Feb 13, 2006 page 42 of 44 REJ03B0180-0110 M35075-XXXFP Fig.32 M35075-001FP character patterns (3) 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C 16 8D 16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C 16 9D 16 9E16 9F16 A016 A116 A216 A316 A416 A516 A616 A716 A816 A916 AA 16 AB 16 AC 16 AD 16 AE 16 AF 16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA 16 BB 16 BC 16 BD 16 BE 16 BF 16

Rev.1.10 Feb 13, 2006 page 43 of 44 REJ03B0180-0110 M35075-XXXFP Fig.33 M35075-001FP character patterns (4) C0 16 C116 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CA 16 CB 16 CC 16 CD 16 CE 16 CF 16 D0 16 D116 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA 16 EB 16 EC 16 ED 16 EE 16 EF 16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB 16 FC 16 FD 16 FE 16 FF16blank

Rev.1.10 Feb 13, 2006 page 44 of 44 REJ03B0180-0110 M35075-XXXFP PACKAGE OUTLINE SSOP24-P-300-0.80 Weight(g) JEDEC Code 0.2 Cu Alloy 24P2Q-A Plastic 24pin 300mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .30 .180 .010 .25 .57 .40 .271 .10 .81 .350 .20 .110 .35 .80 .87 .60 .251 .627 .20 .12 .450 .250 .210 .45 .18 .80 .10 b2 –. 5 0– 0° – e 24 13 121 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F –Z1 0.65 0.8 z Detail G z b G MMP

REVISION HISTORY M35075-XXXFP Rev. Date Description Page Summary

1.00 Mar 01, 2002 - First edition issued

1.10 Feb 13, 2006 P36 "RECOMMENDED OPERATING CONDITIONS" and

"ELECTRICAL CHARACTERISTICS 1" are changed. P37 "ELECTRICAL CHARACTERISTICS 2" is changed.