M32C83T

Renesas Technology Corp

16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

Manufacturer: Renesas Technology Corp

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RENE SAS 16/32-BIT SING LE-C HIP MIC R OCO MP U TE R M1 6C FAMILY / M32C/80 SERIES M32C/83 Group (M32C/83, M32C/83T)16/32 Rev. 1.31 Revision Date: Jan. 31, 2006 Hardware Manual www.renesas.com Before using this material, please visit our website to verify that this is the most current document available. REJ09B0034-0131

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis- tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari- ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Introduction This hardware manual provides detailed information on the M32C/83 Group (M32C/83, M32C/83T) microcom- puters. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. Function XXX Register Bit NameBit Symbol Symbol Address After Reset XXX XXX 00 16 RW RW RW WO RO XXX0 XXX1 (b2) (b4 - b3) XXX bit Reserved bit XXX7 Set to "0" 0: XXX 1: XXX Nothing is assigned. When write, set to "0". When read, its content is indeterminate. XXX bit 0 0: XXX 0 1: XXX 1 0: Do not set a value 1 1: XXX b1b0 XXX bit Function varies depending on mode of operation XXX5 XXX6 RW RW b7 b6 b5 b4 b3 b2 b1 b0 Blank:Set to "0" or "1" according to the application 0: Set to "0" 1: Set to "1" X: Nothing is assigned RW: Read and write RO: Read only WO: Write only –: Nothing is assigned

Reserved bit Reserved bit. Set to specified value.
Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to "0" when writing to this bit.
Do not set a value The operation is not guaranteed when a value is set.
Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode.

M16C Family Documents The following documents were prepared for the M16C family. (1) Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer perfor- mance of each instruction Application Note • Application examples of peripheral functions

Sample programs
Introduction to the basic functions in the M16C family
Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to confirm that this is the most current document available.

8.3.1 f

Three-Phase Motor Control Timer Functions ____ 161

16.3 Special Mode 1 (I

21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode (Group 0 to 3) ....280

22.1.15 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask 22.1.16 CAN0 Message Slot i Control Register (C0MCTLi Register) (i=0 to 15) ...346

27.14.1 Differences Between Flash Memory Version and Masked ROM Version...481

Quick Reference by Address Address Register Page 000016 000116 000216 000316

000416 Processor Mode Register 0 (PM0) 49

000516 Processor Mode Register 1 (PM1) 50

000616 System Clock Control Register 0 (CM0) 67

000716 System Clock Control Register 1 (CM1) 68

000816 Wait Control Register 1 (WCR) 58

000916 Address Match Interrupt Enable Register (AIER) 107

000A 16 Protect Register (PRCR) 88 000B 16 External Data Bus Width Control Register (DS) 52 000C 16 Main Clock Division Register (MCD) 69 000D 16 Oscillation Stop Detect Register (CM2) 70 000E 16 Watchdog Timer Start Register (WDTS) 112000F16 Watchdog Timer Control Register (WDC) 001016

001116 Address Match Interrupt Register 0 (RMAD0) 107

001516 Address Match Interrupt Register 1 (RMAD1) 107

001716 VDC Control Register for PLL (PLV) 72

001916 Address Match Interrupt Register 2 (RMAD2) 107

001B 16 VDC Control Register 0 (VDC0) - 001C 16 001D 16 Address Match Interrupt Register 3 (RMAD3) 107 001E 16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A 16 002B 16 002C 16 002D 16 002E 16 002F16 Address Register Page 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A 16 003B 16 003C 16 003D 16 003E 16 003F16

004016 DRAM Control Register (DRAMCONT) 360

004116 DRAM Refresh Interval Set Register (REFCNT)

005716 Flash Memory Control Register 0 (FMR0) 395

Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 006016 006116 006216 006316 006416 006516 006616 006716

006816 DMA0 Interrupt Control Register (DM0IC)

006916 Timer B5 Interrupt Control Register (TB5IC)

006A 16 DMA2 Interrupt Control Register (DM2IC) 006B 16 UART2 Receive /ACK Interrupt Control Register (S2RIC) 006C 16 Timer A0 Interrupt Control Register (TA0IC) 006D 16 UART3 Receive /ACK Interrupt Control Register (S3RIC) 006E 16 Timer A2 Interrupt Control Register (TA2IC) 006F16 UART4 Receive /ACK Interrupt Control Register (S4RIC)

007016 Timer A4 Interrupt Control Register (TA4IC)

UART0 Bus Conflict Detect Interrupt Control Register (BCN0IC)/ 007116 96UART3 Bus Conflict Detect Interrupt Control Register (BCN3IC)

007216 UART0 Receive/ACK Interrupt Control Register (S0RIC)

007316 A/D0 Conversion Interrupt Control Register (AD0IC)

007416 UART1 Receive/ACK Interrupt Control Register (S1RIC)

007516 Intelligent I/O Interrupt Control Register 0 (IIO0IC)

007616 Timer B1 Interrupt Control Register (TB1IC)

007716 Intelligent I/O Interrupt Control Register 2 (IIO2IC)

007816 Timer B3 Interrupt Control Register (TB3IC)

007916 Intelligent I/O Interrupt Control Register 4 (IIO4IC)

007A 16 INT5 Interrupt Control Register (INT5IC) 97 007B 16 Intelligent I/O Interrupt Control Register 6 (IIO6IC) 96 007C 16 INT3 Interrupt Control Register (INT3IC) 97 007D 16 Intelligent I/O Interrupt Control Register 8 (IIO8IC) 96 007E 16 INT1 Interrupt Control Register (INT1IC) 97 Intelligent I/O Interrupt Control Register 10 (IIO10IC)/ 007F16 96CAN Interrupt 1 Control Register (CAN1IC) 008016 Intelligent I/O Interrupt Control Register 11 (IIO11IC)/ 008116 96CAN Interrupt 2 Control Register (CAN2IC) 008216 008316 008416 008516

008616 A/D1 Conversion Interrupt Control Register (AD1IC)96

008816 DMA1 Interrupt Control Register (DM1IC)

008916 UART2 Transmit /NACK Interrupt Control Register (S2TIC)

008A 16 DMA3 Interrupt Control Register (DM3IC) 008B 16 UART3 Transmit /NACK Interrupt Control Register (S3TIC) 96008C 16 Timer A1 Interrupt Control Register (TA1IC) 008D 16 UART4 Transmit /NACK Interrupt Control Register (S4TIC) 008E 16 Timer A3 Interrupt Control Register (TA3IC) 008F16 UART2 Bus Conflict Detect Interrupt Control Register (BCN2IC) Address Register Page

009016 UART0 Transmit /NACK Interrupt Control Register (S0TIC)

UART1 Bus Conflict Detect Interrupt Control Register (BCN1IC)/

009116 UART4 Bus Conflict Detect Interrupt Control Register (BCN4IC)

009216 UART1 Transmit/NACK Interrupt Control Register (S1TIC)

009316 Key Input Interrupt Control Register (KUPIC)

009416 Timer B0 Interrupt Control Register (TB0IC)

96009516 Intelligent I/O Interrupt Control Register 1 (IIO1IC)

009616 Timer B2 Interrupt Control Register (TB2IC)

009716 Intelligent I/O Interrupt Control Register 3 (IIO3IC)

009816 Timer B4 Interrupt Control Register (TB4IC)

009916 Intelligent I/O Interrupt Control Register 5 (IIO5IC)

009A 16 INT4 Interrupt Control Register (INT4IC) 97 009B 16 Intelligent I/O Interrupt Control Register 7 (IIO7IC) 96 009C 16 INT2 Interrupt Control Register (INT2IC) 97 Intelligent I/O Interrupt Control Register 9 (IIO9IC)/ 009D 16 96CAN Interrupt 0 Control Register (CAN0IC) 009E 16 INT0 Interrupt Control Register (INT0IC) 97 009F16 Exit Priority Control Register (RLVL) 98 00A0 16 Interrupt Request Register 0 (IIO0IR) 00A1 16 Interrupt Request Register 1 (IIO1IR) 00A2 16 Interrupt Request Register 2 (IIO2IR) 00A3 16 Interrupt Request Register 3 (IIO3IR) 00A4 16 Interrupt Request Register 4 (IIO4IR) 00A5 16 Interrupt Request Register 5 (IIO5IR) 109 00A6 16 Interrupt Request Register 6 (IIO6IR) 00A7 16 Interrupt Request Register 7 (IIO7IR) 00A8 16 Interrupt Request Register 8 (IIO8IR) 00A9 16 Interrupt Request Register 9 (IIO9IR) 00AA 16 Interrupt Request Register 10 (IIO10IR) 00AB 16 Interrupt Request Register 11 (IIO11IR) 00AC 16 00AD 16 00AE 16 00AF 16 00B0 16 Interrupt Enable Register 0 (IIO0IE) 00B1 16 Interrupt Enable Register 1 (IIO1IE) 00B2 16 Interrupt Enable Register 2 (IIO2IE) 00B3 16 Interrupt Enable Register 3 (IIO3IE) 00B4 16 Interrupt Enable Register 4 (IIO4IE) 00B5 16 Interrupt Enable Register 5 (IIO5IE) 110 00B6 16 Interrupt Enable Register 6 (IIO6IE) 00B7 16 Interrupt Enable Register 7 (IIO7IE) 00B8 16 Interrupt Enable Register 8 (IIO8IE) 00B9 16 Interrupt Enable Register 9 (IIO9IE) 00BA 16 Interrupt Enable Register 10 (IIO10IE) 00BB 16 Interrupt Enable Register 11 (IIO11IE) 00BC 16 00BD 16 00BE 16 00BF 16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 00C0 16 Group 0 Time Measurement Register 0 (G0TM0)/ 00C1 16 Group 0 Waveform Generation Register 0 (G0PO0) 00C2 16 Group 0 Time Measurement Register 1 (G0TM1)/ 00C3 16 Group 0 Waveform Generation Register 1 (G0PO1) 00C4 16 Group 0 Time Measurement Register 2 (G0TM2)/ 00C5 16 Group 0 Waveform Generation Register 2 (G0PO2) 00C6 16 Group 0 Time Measurement Register 3 (G0TM3)/ 00C7 16 Group 0 Waveform Generation Register 3 (G0PO3)259/ 00C8 16 Group 0 Time Measurement Register 4 (G0TM4)/261 00C9 16 Group 0 Waveform Generation Register 4 (G0PO4) 00CA 16 Group 0 Time Measurement Register 5 (G0TM5)/ 00CB 16 Group 0 Waveform Generation Register 5 (G0PO5) 00CC 16 Group 0 Time Measurement Register 6 (G0TM6)/ 00CD 16 Group 0 Waveform Generation Register 6 (G0PO6) 00CE 16 Group 0 Time Measurement Register 7 (G0TM7)/ 00CF 16 Group 0 Waveform Generation Register 7 (G0PO7) 00D0 16 Group 0 Waveform Generation Control Register 0 (G0POCR0) 00D1 16 Group 0 Waveform Generation Control Register 1 (G0POCR1) 00D2 16 Group 0 Waveform Generation Control Register 2 (G0POCR2) 00D3 16 G roup 0 Waveform Generation Control Register 3 (G0POCR3)259 00D4 16 Group 0 Waveform Generation Control Register 4 (G0POCR4) 00D5 16 Group 0 Waveform Generation Control Register 5 (G0POCR5) 00D6 16 Group 0 Waveform Generation Control Register 6 (G0POCR6) 00D7 16 Group 0 Waveform Generation Control Register 7 (G0POCR7) 00D8 16 Group 0 Time Measurement Control Register 0 (G0TMCR0) 00D9 16 Group 0 Time Measurement Control Register 1 (G0TMCR1) 00DA 16 Group 0 Time Measurement Control Register 2 (G0TMCR2) 00DB 16 Group 0 Time Measurement Control Register 3 (G0TMCR3)258 00DC 16 Group 0 Time Measurement Control Register 4 (G0TMCR4) 00DD 16 Group 0 Time Measurement Control Register 5 (G0TMCR5) 00DE 16 Group 0 Time Measurement Control Register 6 (G0TMCR6) 00DF 16 Group 0 Time Measurement Control Register 7 (G0TMCR7) 00E0 16 Group 0 Base Timer Register (G0BT)00E1 16 253 00E2 16 Group 0 Base Timer Control Register 0 (G0BCR0) 00E3 16 Group 0 Base Timer Control Register 1 (G0BCR1)254 00E4 16 Group 0 Time Measurement Prescaler Register 6 (G0TPR6)258 00E5 16 Group 0 Time Measurement Prescaler Register 7 (G0TPR7) 00E6 16 Group 0 Function Enable Register (G0FE) 262 00E7 16 Group 0 Function Select Register (G0FS) 00E8 16 Group 0 SI/O Receive Buffer Register (G0RB) 291 00E9 16 00EA 16 Group 0 Transmit Buffer/Receive Data Register (G0TB/G0DR)294 00EB 16 00EC 16 Group 0 Receive Input Register (G0RI) 289 00ED 16 Group 0 SI/O Communication Mode Register (G0MR)291 00EE 16 Group 0 Transmit Output Register (G0TO) 289 00EF 16 Group 0 SI/O Communication Control Register (G0CR)290 Address Register Page 00F016 Group 0 Data Compare Register 0 (G0CMP0) 00F116 Group 0 Data Compare Register 1 (G0CMP1) 00F216 Group 0 Data Compare Register 2 (G0CMP2) 29500F316 Group 0 Data Compare Register 3 (G0CMP3) 00F416 Group 0 Data Mask Register 0 (G0MSK0) 00F516 Group 0 Data Mask Register 1 (G0MSK1) 00F616 00F716 00F816 Group 0 Receive CRC Code Register (G0RCRC)00F916 29500FA 16 Group 0 Transmit CRC Code Register (G0TCRC)00FB 16 00FC 16 Group 0 SI/O Extended Mode Register (G0EMR) 292 00FD 16 Group 0 SI/O Extended Receive Control Register (G0ERC)293 00FE 16 Group 0 SI/O Special Communication Interrupt Detect Register (G0IRF)294 00FF 16 Group 0 SI/O Extended Transmit Control Register (G0ETC)292

010016 Group 1 Time Measurement Register 0 (G1TM0)/

010116 Group 1 Waveform Generation Register 0 (G1PO0)

010216 Group 1 Time Measurement Register 1 (G1TM1)/

010316 Group 1 Waveform Generation Register 1 (G1PO1)

010416 Group 1 Time Measurement Register 2 (G1TM2)/

010516 Group 1 Waveform Generation Register 2 (G1PO2)

010616 Group 1 Time Measurement Register 3 (G1TM3)/

010716 Group 1 Waveform Generation Register 3 (G1PO3)259/

010816 Group 1 Time Measurement Register 4 (G1TM4)/ 261

010916 Group 1 Waveform Generation Register 4 (G1PO4)

010A 16 Group 1 Time Measurement Register 5 (G1TM5)/ 010B 16 Group 1 Waveform Generation Register 5 (G1PO5) 010C 16 Group 1 Time Measurement Register 6 (G1TM6)/ 010D 16 Group 1 Waveform Generation Register 6 (G1PO6) 010E 16 Group 1 Time Measurement Register 7 (G1TM7)/ 010F16 Group 1 Waveform Generation Register 7 (G1PO7)

011016 Group 1 Waveform Generation Control Register 0 (G1POCR0)

011116 Group 1 Waveform Generation Control Register 1 (G1POCR1)

011216 Group 1 Waveform Generation Control Register 2 (G1POCR2)

011316 Group 1 Waveform Generation Control Register 3 (G1POCR3)

259011416 Group 1 Waveform Generation Control Register 4 (G1POCR4)

011516 Group 1 Waveform Generation Control Register 5 (G1POCR5)

011616 Group 1 Waveform Generation Control Register 6 (G1POCR6)

011716 Group 1 Waveform Generation Control Register 7 (G1POCR7)

011816 Group 1 Time Measurement Control Register 0 (G1TMCR0)

011916 Group 1 Time Measurement Control Register 1 (G1TMCR1)

011A 16 Group 1 Time Measurement Control Register 2 (G1TMCR2) 011B 16 Group 1 Time Measurement Control Register 3 (G1TMCR3) 258011C 16 Group 1 Time Measurement Control Register 4 (G1TMCR4) 011D 16 Group 1 Time Measurement Control Register 5 (G1TMCR5) 011E 16 Group 1 Time Measurement Control Register 6 (G1TMCR6) 011F16 Group 1 Time Measurement Control Register 7 (G1TMCR7) Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 012016 Group 1 Base Timer Register (G1BT)012116 253

012216 Group 1 Base Timer Control Register 0 (G1BCR0)

012316 Group 1 Base Timer Control Register 1 (G1BCR1)254

012416 Group 1 Time Measurement Prescaler Register 6 (G1TPR6)

258012516 Group 1 Time Measurement Prescaler Register 7 (G1TPR7)

012616 Group 1 Function Enable Register (G1FE) 262

012716 Group 1 Function Select Register (G1FS)

012816 Group 1 SI/O Receive Buffer Register (G1RB) 291

012A 16 Group 1 Transmit Buffer/Receive Data Register (G1TB/G1DR)294 012B 16 012C 16 Group 1 Receive Input Register (G1RI) 289 012D 16 Group 1 SI/O Communication Mode Register (G1MR)291 012E 16 Group 1 Transmit Output Register (G1TO) 289 012F16 Group 1 SI/O Communication Control Register (G1CR)290

013016 Group 1 Data Compare Register 0 (G1CMP0)

013116 Group 1 Data Compare Register 1 (G1CMP1)

013216 Group 1 Data Compare Register 2 (G1CMP2) 295

013316 Group 1 Data Compare Register 3 (G1CMP3)

013416 Group 1 Data Mask Register 0 (G1MSK0)

013516 Group 1 Data Mask Register 1 (G1MSK1)

Group 1 Receive CRC Code Register (G1RCRC)013916 295013A 16 Group 1 Transmit CRC Code Register (G1TCRC)013B 16 013C 16 Group 1 SI/O Extended Mode Register (G1EMR) 292 013D 16 Group 1 SI/O Extended Receive Control Register (G1ERC)293 013E 16 Group 1 SI/O Special Communication Interrupt Detect Register (G1IRF)294 013F16 Group 1 SI/O Extended Transmit Control Register (G1ETC)292 014016 Group 2 Waveform Generation Register 0 (G2PO0)014116 014216 Group 2 Waveform Generation Register 1 (G2PO1)014316 014416 Group 2 Waveform Generation Register 2 (G2PO2)014516 014616 Group 2 Waveform Generation Register 3 (G2PO3)014716 261 014816 Group 2 Waveform Generation Register 4 (G2PO4)014916 014A 16 Group 2 Waveform Generation Register 5 (G2PO5)014B 16 014C 16 Group 2 Waveform Generation Register 6 (G2PO6)014D 16 014E 16 Group 2 Waveform Generation Register 7 (G2PO7)014F16 Address Register Page

015016 Group 2 Waveform Generation Control Register 0 (G2POCR0)

015116 Group 2 Waveform Generation Control Register 1 (G2POCR1)

015216 Group 2 Waveform Generation Control Register 2 (G2POCR2)

015316 Group 2 Waveform Generation Control Register 3 (G2POCR3)260

015416 Group 2 Waveform Generation Control Register 4 (G2POCR4)

015516 Group 2 Waveform Generation Control Register 5 (G2POCR5)

015616 Group 2 Waveform Generation Control Register 6 (G2POCR6)

015716 Group 2 Waveform Generation Control Register 7 (G2POCR7)

Group 2 Base Timer Register (G2BT)016116 253

016216 Group 2 Base Timer Control Register 0 (G2BCR0)

016316 Group 2 Base Timer Control Register 1 (G2BCR1)255

016416 Base Timer Start Register (BTSR) 257

016616 Group 2 Function Enable Register (G2FE) 262

016716 Group 2 RTP Output Buffer Register (G2RTP) 263

016A 16 Group 2 SI/O Communication Mode Register (G2MR) 307016B 16 Group 2 SI/O Communication Control Register (G2CR) 016C 16 Group 2 SI/O Transmit Buffer Register (G2TB)016D 16 306 016E 16 Group 2 SI/O Receive Buffer Register (G2RB)016F16 017016 Group 2 IEBus Address Register (IEAR)017116 308

017216 Group 2 IEBus Control Register (IECR)

017316 Group 2 IEBus Transmit Interrupt Cause Detect Register (IETIF)309

017416 Group 2 IEBus Receive Interrupt Cause Detect Register (IERIF)

017816 Input Function Select Register (IPS) 383

017A 16 Group 3 SI/O Communication Mode Register (G3MR)318 017B 16 Group 3 SI/O Communication Control Register (G3CR) 017C 16 Group 3 SI/O Transmit Buffer Register (G3TB)017D 16 317 017E 16 Group 3 SI/O Receive Buffer Register (G3RB)017F16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 018016 Group 3 Waveform Generation Register 0 (G3PO0)018116 018216 Group 3 Waveform Generation Register 1 (G3PO1)018316 018416 Group 3 Waveform Generation Register 2 (G3PO2)018516 018616 Group 3 Waveform Generation Register 3 (G3PO3)018716 261 018816 Group 3 Waveform Generation Register 4 (G3PO4)018916 018A 16 Group 3 Waveform Generation Register 5 (G3PO5)018B 16 018C 16 Group 3 Waveform Generation Register 6 (G3PO6)018D 16 018E 16 Group 3 Waveform Generation Register 7 (G3PO7)018F16

019016 Group 3 Waveform Generation Control Register 0 (G3POCR0)

019116 Group 3 Waveform Generation Control Register 1 (G3POCR1)

019216 Group 3 Waveform Generation Control Register 2 (G3POCR2)

019316 Group 3 Waveform Generation Control Register 3 (G3POCR3)260

019416 Group 3 Waveform Generation Control Register 4 (G3POCR4)

019516 Group 3 Waveform Generation Control Register 5 (G3POCR5)

019616 Group 3 Waveform Generation Control Register 6 (G3POCR6)

019716 Group 3 Waveform Generation Control Register 7 (G3POCR7)

Group 3 Waveform Generation Mask Register 4 (G3MK4)019916 019A 16 Group 3 Waveform Generation Mask Register 5 (G3MK5)019B 16 261 019C 16 Group 3 Waveform Generation Mask Register 6 (G3MK6)019D 16 019E 16 Group 3 Waveform Generation Mask Register 7 (G3MK7)019F16 01A0 16 Group 3 Base Timer Register (G3BT)01A1 16 253 01A2 16 Group 3 Base Timer Control Register 0 (G3BCR0) 01A3 16 Group 3 Base Timer Control Register 1 (G3BCR1)256 01A4 16 01A5 16 01A6 16 Group 3 Function Enable Register 1 (G3FE) 262 01A7 16 Group 3 RTP Output Buffer Register 1 (G3RTP) 263 01A8 16 01A9 16 01AA 16 01AB 16 01AC 16 01AD 16 Group 3 SI/O Communication Flag Register (G3FLG)319 01AE 16 01AF 16 Address Register Page 01B0 16 01B1 16 01B2 16 01B3 16 01B4 16 01B5 16 01B6 16 01B7 16 01B8 16 01B9 16 01BA 16 01BB 16 01BC 16 01BD 16 01BE 16 01BF 16 01C0 16 A/D1 Register 0 (AD10)01C1 16 01C2 16 A/D1 Register 1 (AD11)01C3 16 01C4 16 A/D1 Register 2 (AD12)01C5 16 01C6 16 A/D1 Register 3 (AD13)01C7 16 233 01C8 16 A/D1 Register 4 (AD14)01C9 16 01CA 16 A/D1 Register 5 (AD15)01CB 16 01CC 16 A/D1 Register 6 (AD16)01CD 16 01CE 16 A/D1 Register 7 (AD17)01CF 16 01D0 16 01D1 16 01D2 16 01D3 16 01D4 16 A/D1 Control Register 2 (AD1CON2) 233 01D5 16 01D6 16 A/D1 Control Register 0 (AD1CON0) 231 01D7 16 A/D1 Control Register 1 (AD1CON1) 232 01D8 16 01D9 16 01DA 16 01DB 16 01DC 16 01DD 16 01DE 16 01DF 16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 01E0 16 CAN0 Message Slot Buffer 0 Standard ID0 (C0SLOT0_0) 35001E1 16 CAN0 Message Slot Buffer 0 Standard ID1 (C0SLOT0_1) 01E2 16 CAN0 Message Slot Buffer 0 Extended ID0 (C0SLOT0_2) 35101E3 16 CAN0 Message Slot Buffer 0 Extended ID1 (C0SLOT0_3) 01E4 16 CAN0 Message Slot Buffer 0 Extended ID2 (C0SLOT0_4) 35201E5 16 CAN0 Message Slot Buffer 0 Data Length Code (C0SLOT0_5) 01E6 16 CAN0 Message Slot Buffer 0 Data 0 (C0SLOT0_6) 01E7 16 CAN0 Message Slot Buffer 0 Data 1 (C0SLOT0_7) 01E8 16 CAN0 Message Slot Buffer 0 Data 2 (C0SLOT0_8) 01E9 16 CAN0 Message Slot Buffer 0 Data 3 (C0SLOT0_9) 01EA 16 CAN0 Message Slot Buffer 0 Data 4 (C0SLOT0_10) 35301EB 16 CAN0 Message Slot Buffer 0 Data 5 (C0SLOT0_11) 01EC 16 CAN0 Message Slot Buffer 0 Data 6 (C0SLOT0_12) 01ED 16 CAN0 Message Slot Buffer 0 Data 7 (C0SLOT0_13) 01EE 16 CAN0 Message Slot Buffer 0 Time Stamp High-Order (C0SLOT0_14) 01EF 16 CAN0 Message Slot Buffer 0 Time Stamp Low-Order (C0SLOT0_15) 01F016 CAN0 Message Slot Buffer 1 Standard ID0 (C0SLOT1_0) 35001F116 CAN0 Message Slot Buffer 1 Standard ID1 (C0SLOT1_1) 01F216 CAN0 Message Slot Buffer 1 Extended ID0 (C0SLOT1_2) 35101F316 CAN0 Message Slot Buffer 1 Extended ID1 (C0SLOT1_3) 01F416 CAN0 Message Slot Buffer 1 Extended ID2 (C0SLOT1_4) 35201F516 CAN0 Message Slot Buffer 1 Data Length Code (C0SLOT1_5) 01F616 CAN0 Message Slot Buffer 1 Data 0 (C0SLOT1_6) 01F716 CAN0 Message Slot Buffer 1 Data 1 (C0SLOT1_7) 01F816 CAN0 Message Slot Buffer 1 Data 2 (C0SLOT1_8) 01F916 CAN0 Message Slot Buffer 1 Data 3 (C0SLOT1_9) 01FA 16 CAN0 Message Slot Buffer 1 Data 4 (C0SLOT1_10) 35301FB 16 CAN0 Message Slot Buffer 1 Data 5 (C0SLOT1_11) 01FC 16 CAN0 Message Slot Buffer 1 Data 6 (C0SLOT1_12) 01FD 16 CAN0 Message Slot Buffer 1 Data 7 (C0SLOT1_13) 01FE 16 CAN0 Message Slot Buffer 1 Time Stamp High-Order (C0SLOT1_14) 01FF 16 CAN0 Message Slot Buffer 1 Time Stamp Low-Order (C0SLOT1_15) 020016 CAN0 Control Register0 (C0CTLR0) 326020116 020216 CAN0 Status Register (C0STR) 331020316 020416 CAN0 Extended ID Register (C0IDR) 333020516 020616 CAN0 Configuration Register (C0CONR) 334020716 020816 CAN0 Time Stamp Register (C0TSR)020916 336 020A 16 CAN0 Transmit Error Count Register (C0TEC) 020B 16 CAN0 Receive Error Count Register (C0REC) 337 020C 16 CAN0 Slot Interrupt Status Register (C0SISTR) 338020D 16 020E 16 020F16 Address Register Page 021016 CAN0 Slot Interrupt Mask Register (C0SIMKR) 340021116 021216 021316

021416 CAN0 Error Interrupt Mask Register (C0EIMKR) 341

021516 CAN0 Error Interrupt Status Register (C0EISTR)342

021716 CAN0 Baud Rate Prescaler (C0BPR) 337

022816 CAN0 Global Mask Register Standard ID0 (C0GMR0)343

022916 CAN0 Global Mask Register Standard ID1 (C0GMR1)

344022A 16 CAN0 Global Mask Register Extended ID0 (C0GMR2) 022B 16 CAN0 Global Mask Register Extended ID1 (C0GMR3) 345022C 16 CAN0 Global Mask Register Extended ID2 (C0GMR4) 022D 16 022E 16 022F16 CAN0 Message Slot 0 Control Register (C0MCTL0)/346/

023016 CAN0 Local Mask Register A Standard ID0 (C0LMAR0)343

CAN0 Message Slot 1 Control Register (C0MCTL1)/

023116 CAN0 Local Mask Register A Standard ID1 (C0LMAR1)344/

CAN0 Message Slot 2 Control Register (C0MCTL2)/346/

023216 CAN0 Local Mask Register A Extended ID0 (C0LMAR2)

CAN0 Message Slot 3 Control Register (C0MCTL3)/

023316 CAN0 Local Mask Register A Extended ID1 (C0LMAR3)345

CAN0 Message Slot 4 Control Register (C0MCTL4)/346/

023416 CAN0 Local Mask Register A Extended ID2 (C0LMAR4)

023516 CAN0 Message Slot 5 Control Register (C0MCTL5)

023616 CAN0 Message Slot 6 Control Register (C0MCTL6)346

023716 CAN0 Message Slot 7 Control Register (C0MCTL7)

CAN0 Message Slot 8 Control Register (C0MCTL8)/346/

023816 CAN0 Local Mask Register B Standard ID0 (C0LMBR0)343

Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page CAN0 Message Slot 9 Control Register (C0MCTL9)/

023916 CAN0 Local Mask Register B Standard ID1 (C0LMBR1)344

CAN0 Message Slot 10 Control Register (C0MCTL10)/346/ 023A 16 CAN0 Local Mask Register B Extended ID0 (C0LMBR2) CAN0 Message Slot 11 Control Register (C0MCTL11)/ 023B 16 CAN0 Local Mask Register B Extended ID1 (C0LMBR3)345 CAN0 Message Slot 12 Control Register (C0MCTL12)/346/ 023C 16 CAN0 Local Mask Register B Extended ID2 (C0LMBR4) 023D 16 CAN0 Message Slot 13 Control Register (C0MCTL13) 023E 16 CAN0 Message Slot 14 Control Register (C0MCTL14)346 023F16 CAN0 Message Slot 15 Control Register(C0MCTL15)

024016 CAN0 Slot Buffer Select Register (C0SBS) 349

024116 CAN0 Control Register 1 (C0CTLR1) 329

024216 CAN0 Sleep Control Register (C0SLPR) 330

CAN0 Acceptance Filter Support Register (C0AFS)354024516 Address Register Page 02C0 16 X0 Register Y0 Register (X0R,Y0R)02C1 16 02C2 16 X1 Register Y1 Register (X1R,Y1R)02C3 16 02C4 16 X2 Register Y2 Register (X2R,Y2R)02C5 16 02C6 16 X3 Register Y3 Register (X3R,Y3R)02C7 16 02C8 16 X4 Register Y4 Register (X4R,Y4R)02C9 16 02CA 16 X5 Register Y5 Register (X5R,Y5R)02CB 16 02CC 16 X6 Register Y6 Register (X6R,Y6R)02CD 16 02CE 16 X7 Register Y7 Register (X7R,Y7R)02CF 16 24602D0 16 X8 Register Y8 Register (X8R,Y8R)02D1 16 02D2 16 X9 Register Y9 Register (X9R,Y9R)02D3 16 02D4 16 X10 Register Y10 Register (X10R,Y10R)02D5 16 02D6 16 X11 Register Y11 Register (X11R,Y11R)02D7 16 02D8 16 X12 Register Y12 Register (X12R,Y12R)02D9 16 02DA 16 X13 Register Y13 Register (X13R,Y13R)02DB 16 02DC 16 X14 Register Y14 Register (X14R,Y14R)02DD 16 02DE 16 X15 Register Y15 Register (X15R,Y15R)02DF 16 02E0 16 XY Control Register (XYC) 245 02E1 16 02E2 16 02E3 16 02E4 16 UART1 Special Mode Register 4 (U1SMR4) 180 02E5 16 UART1 Special Mode Register 3 (U1SMR3) 179 02E6 16 UART1 Special Mode Register 2 (U1SMR2) 178 02E7 16 UART1 Special Mode Register (U1SMR) 177 02E8 16 UART1 Transmit/Receive Mode Register (U1MR) 17502E9 16 UART1 Baud Rate Register (U1BRG) 02EA 16 UART1 Transmit Buffer Register (U1TB) 17402EB 16 02EC 16 UART1 Transmit/Receive Control Register 0 (U1C0)176 02ED 16 UART1 Transmit/Receive Control Register 1 (U1C1)177 02EE 16 UART1 Receive Buffer Register (U1RB) 17402EF 16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 02F016 02F116 02F216 02F316 02F416 UART4 Special Mode Register 4 (U4SMR4) 180 02F516 UART4 Special Mode Register 3 (U4SMR3) 179 02F616 UART4 Special Mode Register 2 (U4SMR2) 178 02F716 UART4 Special Mode Register (U4SMR) 177 02F816 UART4 Transmit/Receive Mode Register (U4MR) 17502F916 UART4 Baud Rate Register (U4BRG) 02FA 16 UART4 Transmit Buffer Register (U4TB) 17402FB 16 02FC 16 UART4 Transmit/Receive Control Register 0 (U4C0)176 02FD 16 UART4 Transmit/Receive Control Register 1 (U4C1)177 02FE 16 UART4 Receive Buffer Register (U4RB) 17402FF 16

030016 Timer B3,B4,B5 Count Start Flag (TBSR) 154

Timer A1-1 Register (TA11)030316 030416 Timer A2-1 Register (TA21) 167030516 030616 Timer A4-1 Register (TA41)030716

030816 Three-Phase PWM Control Register 0 (INVC0) 164

030916 Three-Phase PWM Control Register 1 (INVC1) 165

030A 16 Three-Phase Output Buffer Register 0 (IDB0) 030B 16 Three-Phase Output Buffer Register 1 (IDB1) 166 030C 16 Dead Time Timer (DTT) 030D 16 Timer B2 Interrupt Generation Frequency Set Counter (ICTB2)167 030E 16 030F16 031016 Timer B3 Register (TB3)031116 031216 Timer B4 Register (TB4) 152031316 031416 Timer B5 Register (TB5)031516 031616 031716 031816 031916 031A 16 031B 16 Timer B3 Mode Register (TB3MR) 031C 16 Timer B4 Mode Register (TB4MR) 153 031D 16 Timer B5 Mode Register (TB5MR) 031E 16 031F16 External Interrupt Cause Select Register (IFSR) 105 Address Register Page 032016 032116 032216 032316

032416 UART3 Special Mode Register 4 (U3SMR4) 180

032516 UART3 Special Mode Register 3 (U3SMR3) 179

032616 UART3 Special Mode Register 2 (U3SMR2) 178

032716 UART3 Special Mode Register (U3SMR) 177

032816 UART3 Transmit/Receive Mode Register (U3MR)

175032916 UART3 Baud Rate Register (U3BRG)

UART3 Transmit Buffer Register (U3TB) 174032B 16 032C 16 UART3 Transmit/Receive Control Register 0 (U3C0)176 032D 16 UART3 Transmit/Receive Control Register 1 (U3C1)177 032E 16 UART3 Receive Buffer Register (U3RB) 174032F16 033016 033116 033216 033316

033416 UART2 Special Mode Register 4 (U2SMR4) 180

033516 UART2 Special Mode Register 3 (U2SMR3) 179

033616 UART2 Special Mode Register 2 (U2SMR2) 178

033716 UART2 Special Mode Register (U2SMR) 177

033816 UART2 Transmit/Receive Mode Register (U2MR)

175033916 UART2 Baud Rate Register (U2BRG)

UART2 Transmit Buffer Register (U2TB) 174033B 16 033C 16 UART2 Transmit/Receive Control Register 0 (U2C0)176 033D 16 UART2 Transmit/Receive Control Register 1 (U2C1)177 033E 16 UART2 Receive Buffer Register (U2RB) 174033F16

034016 Count Start Flag (TABSR) 137

034116 Clock Prescaler Reset Flag (CPSRF) 71

034216 One-Shot Start Flag (ONSF) 138

034316 Trigger Select Register (TRGSR) 139

034416 Up-Down Flag (UDF) 138

Timer A0 Register (TA0)034716 034816 Timer A1 Register (TA1)034916 034A 16 Timer A2 Register (TA2) 136034B 16 034C 16 Timer A3 Register (TA3)034D 16 034E 16 Timer A4 Register (TA4)034F16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 035016 Timer B0 Register (TB0)035116 035216 Timer B1 Register (TB1) 152035316 035416 Timer B2 Register (TB2)035516

035616 Timer A0 Mode Register (TA0MR)

035716 Timer A1 Mode Register (TA1MR)

035816 Timer A2 Mode Register (TA2MR) 137

035916 Timer A3 Mode Register (TA3MR)

035A 16 Timer A4 Mode Register (TA4MR) 035B 16 Timer B0 Mode Register (TB0MR) 035C 16 Timer B1 Mode Register (TB1MR) 153 035D 16 Timer B2 Mode Register (TB2MR) 035E 16 Timer B2 Special Mode Register (TB2SC) 167 035F16 Count Source Prescaler Register (TCSPR) 71 036016 036116 036216 036316

036416 UART0 Special Mode Register 4 (U0SMR4) 180

036516 UART0 Special Mode Register 3 (U0SMR3) 179

036616 UART0 Special Mode Register 2 (U0SMR2) 178

036716 UART0 Special Mode Register (U0SMR) 177

036816 UART0 Transmit/Receive Mode Register (U0MR)

175036916 UART0 Baud Rate Register (U0BRG)

UART0 Transmit Buffer Register (U0TB) 174036B 16 036C 16 UART0 Transmit/Receive Control Register 0 (U0C0)176 036D 16 UART0 Transmit/Receive Control Register 1 (U0C1)177 036E 16 UART0 Receive Buffer Register (U0RB) 174036F16 037016 037116 037216 037316 037416 037516

037616 PLL Control Register 0 (PLC0) 72

037716 PLL Control Register 1 (PLC1) 73

037816 DMA0 Cause Select Register (DM0SL)

037916 DMA1 Cause Select Register (DM1SL)

116037A 16 DMA2 Cause Select Register (DM2SL) 037B 16 DMA3 Cause Select Register (DM3SL) 037C 16 CRC Data Register (CRCD)037D 16 243 037E 16 CRC Input Register (CRCIN) 037F16 Address Register Page 038016 A/D0 Register0 (AD00)038116 038216 A/D0 Register1 (AD01)038316 038416 A/D0 Register2 (AD02)038516 038616 A/D0 Register3 (AD03)038716 230038816 A/D0 Register4 (AD04)038916 038A 16 A/D0 Register5 (AD05)038B 16 038C 16 A/D0 Register6 (AD06)038D 16 038E 16 A/D0 Register7 (AD07)038F16 039016 039116 039216 039316

039416 A/D0 Control Register 2 (AD0CON2) 230

039616 A/D0 Control Register 0 (AD0CON0) 228

039716 A/D0 Control Register 1 (AD0CON1) 229

039816 D/A Register 0 (DA0) 242

039A 16 D/A Register 1 (DA1) 242 039B 16 039C 16 D/A Control Register (DACON) 242 039D 16 039E 16 039F16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address Address Register Page 03A0 16 Function Select Register A8 (PS8) 376 03A1 16 Function Select Register A9 (PS9) 377 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 Function Select Register C (PSC) 380 03B0 16 Function Select Register A0 (PS0) 37303B1 16 Function Select Register A1 (PS1) 03B2 16 Function Select Register B0 (PSL0) 37803B3 16 Function Select Register B1 (PSL1) 03B4 16 Function Select Register A2 (PS2) 37403B5 16 Function Select Register A3 (PS3) 03B6 16 Function Select Register B2 (PSL2) 37903B7 16 Function Select Register B3 (PSL3) 03B8 16 03B9 16 Function Select Register A5 (PS5) 375 03BA 16 03BB 16 03BC 16 Function Select Register A6 (PS6) 375 03BD 16 Function Select Register A7 (PS7) 376 03BE 16 03BF 16 03C0 16 Port P6 Register (P6) 37203C1 16 Port P7 Register (P7) 03C2 16 Port P6 Direction Register (PD6) 37103C3 16 Port P7 Direction Register (PD7) 03C4 16 Port P8 Register (P8) 37203C5 16 Port P9 Register (P9) 03C6 16 Port P8 Direction Register (PD8) 37103C7 16 Port P9 Direction Register (PD9) 03C8 16 Port P10 Register (P10) 37203C9 16 Port P11 Register (P11) 03CA 16 Port P10 Direction Register (PD10) 37103CB 16 Port P11 Direction Register(PD11) 03CC 16 Port P12 Register (P12) 37203CD 16 Port P13 rRegister (P13) 03CE 16 Port P12 Direction Register (PD12) 37103CF 16 Port P13 Direction Register (PD13) Address Register Page 03D0 16 Port P14 Register (P14) 37203D1 16 Port P15 Register (P15) 03D2 16 Port P14 Direction Register (PD14) 37103D3 16 Port P15 Direction Register (PD15) 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-Up Control Register 2 (PUR2) 381 03DB 16 Pull-Up Control Register 3 (PUR3) 38203DC 16 Pull-Up Control Register 4 (PUR4) 03DD 16 03DE 16 03DF 16 03E0 16 Port P14 Register (P0) 37203E1 16 Port P14 Register (P1) 03E2 16 Port P14 Direction Register (PD0) 37103E3 16 Port P14 Direction Register (PD1) 03E4 16 Port P14 Register (P2) 37203E5 16 Port P14 Register (P3) 03E6 16 Port P14 Direction Register (PD2) 37103E7 16 Port P14 Direction Register (PD3) 03E8 16 Port P14 Register (P4) 37203E9 16 Port P14 Register (P5) 03EA 16 Port P14 Direction Register (PD4) 37103EB 16 Port P14 Direction Register (PD5) 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-Up Control Register 0 (PUR0) 38103F116 Pull-Up Control Register 1 (PUR1) 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register (PCR) 383 Blank spaces are reserved. No access is allowed.

M32C/83 Group (M32C/83, M32C/83T) SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 884fo6002,13.naJ13.1.veR 1310-4300B90JER 1. Overview The M32C/83 Group (M32C/83, M32C/83T) microcomputer is a single-chip control unit that utilizes high- performance silicon gate CMOS technology with the M32C/80 Series CPU core. The M32C/83 Group (M32C/83, M32C/83T) is available in 144-pin and 100-pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili- ties to process complex instructions by less bytes and execute instructions at higher speed. It includes a multiplier and DMAC adequate for office automation, communication devices and industrial equipments, and other high-speed processing applications.

1.1 Applications

Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc.

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M

1.2 Performance Overview

Tables 1.1 and 1.2 list performance overview of the M32C/83 Group (M32C/83, M32C/83T). Table 1.1 M32C/83 Group (M32C/83, M32C/83T) Performance (144-Pin Package) Characteristic Performance M32C/83 M32C/83T CPU Basic Instructions 108 instructions 50 ns (f(BCLK)=20 MHz, VCC =3.0 to 5.5 V) Operating Mode Single-chip mode, Memory expansion Single-chip mode mode and Microprocessor mode Address Space 16 Mbytes Memory Capacity See Table 1.3 PeripheralI/O Port 123 I/O pins and 1 input pin Function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function: 16 bits x 12 channels Waveform generating function: 16 bits x 28 channels Communication function (Clock synchronous serial I/O, Clock asynchronous se- rial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1), 8-bit or 16-bit Clock synchronous serial I/O) Serial I/O 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) CAN Module 1 channel Supporting CAN 2.0B specification A/D Converter 10-bit A/D converter: 2 circuit, 34 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions DRAM CAS before RAS refresh, Self-reflesh, EDO, EP CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 42 internal and 8 external sources, 5 software sources, Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscilla- tor must be connected externally Oscillation Stop Detect Function Main clock oscillation stop detect function Electrical Supply Voltage 4.2 to 5.5 V (f(BCLK)=32 MHz) 4.2 to 5.5 V (f(BCLK)=32 MHz) Charact- 3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC) eristics 3.0 to 3.6 V (f(BCLK)=20 MHz, not through VDC) Power Consumption 41 mA (V CC =5 V, f(BCLK)=32 MHz) 41 mA (V CC =5 V, f(BCLK)=32 MHz) 38 mA (VCC =5 V, f(BCLK)=30 MHz) 38 mA (V CC =5 V, Vf(BCLK)=30 MHz) 26 mA (VCC =3.3 V, f(BCLK)=20 MHz) 470 µA (VCC =5 V, f(XCIN)=32 kHz, 470 µA (VCC =5 V, f(XCIN)=32 kHz, in wait mode) in wait mode) 0.4 µA (VCC =5 V, stop mode) 340 µA (VCC =3.3 V, f(XCIN)=32 kHz, through VDC, in wait mode) 5.0 µA (VCC =3.3 V, f(XCIN)=32 kHz, not through VDC, in wait mode) 0.4 µA (VCC =5 V, stop mode) 0.4 µA (VCC =3.3 V, stop mode) Memory Program and Erase Endurance 100 times Operating Ambient Temperature –20 to 85 oC, –40 to 85oC (optional) –40 to 85oC (T version) Package 144-pin plastic molded LQFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. Contact our sales office if 30-MHz or higher frequency is required. All options are on a request basis.

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M Table 1.2 M32C/83 Group (M32C/83, M32C/83T) Performance (100-Pin Package) Characteristic Performance M32C/83 M32C/83T CPU Basic Instructions 108 instructions 50 ns (f(BCLK) = 20 MHz, VCC = 3.0 to 5.5 V) Operating Mode Single-chip mode, Memory expansion Single-chip mode mode and Microprocessor mode Address Space 16 Mbytes Memory Capacity See Table 1.3 Peripheral I/O Port 87 I/O pins and 1 input pin Function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function: 16 bits x 5 channels Waveform generating function: 16 bits x 10 channels Communication function (Clock synchronous serial I/O, Clock asynchronous se- rial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1)) Serial I/O 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) CAN Module 1 channel Supporting CAN 2.0B specification A/D Converter 10-bit A/D converter: 2 circuits, 26 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 42 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation Stop Detect Function Main clock oscillation stop detect function Electrical Supply Voltage 4.2 to 5.5 V (f(BCLK)=32 MHz) 4.2 to 5.5 V (f(BCLK)=32 MHz) Charact- 3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC) eristics 3.0 to 3.6 V (f(BCLK)=20 MHz, not through VDC) Power Consumption 41 mA (V CC =5 V, f(BCLK)=32 MHz) 41 mA (V CC =5 V, f(BCLK)=32 MHz) 38 mA (VCC =5 V, f(BCLK)=30 MHz) 38 mA (V CC =5 V, Vf(BCLK)=30 MHz) 26 mA (VCC =3.3 V, f(BCLK)=20 MHz) 470 µA (VCC =5 V, f(XCIN)=32 kHz, 470 µA (VCC =5 V, f(XCIN)=32 kHz, in wait mode) in wait mode) 0.4 µA (VCC =5 V, stop mode) 340 µA (VCC =3.3 V, f(XCIN)=32 kHz, through VDC, in wait mode) 5.0 µA (VCC =3.3 V, f(XCIN)=32 kHz, not through VDC, in wait mode) 0.4 µA (VCC =5 V, stop mode) 0.4 µA (VCC =3.3 V, stop mode) Memory Program and Erase Endurance 100 times Operating Ambient Temperature –20 to 85 oC, –40 to 85oC (optional) –40 to 85 oC (T version) Package 100-pin plastic molded LQFP/QFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. Contact our sales office if 30-MHz or higher frequency is required. All options are on a request basis.

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M

1.3 Block Diagram

Figure 1.1 shows a block diagram of the M32C/83 Group (M32C/83, M32C/83T) microcomputer. Figure 1.1 M32C/83 Group (M32C/83, M32C/83T) Block Diagram Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Port P15 Port P14 Port P13 Port P12 Port P10 Port P9 Port P8P85Port P11 R0H R0L R1H R1L FB SB NOTES: 1. Ports P11 to P15 are provided only in the 144-pin package. 2. Included only in the 144-pin package. 3. Can be used only in the 144-pin package. FLG INTB ISP USP PC SVF SVP VCT Multiplier M32C/80 Series CPU Core Clock Generation Circuit XIN - XOUT XCIN - XCOUT On-chip Oscillator PLL Frequency Synthesizer A/D Converter: 2 circuits Standard: 18 inputs(2) Maximum: 34 inputs(2) UART/Clock Synchronous Serial I/O: 5 channels X/Y Converter: 16 bits x 16 bits CRC Calculation Circuit (CCITT): X16+X12+X5+1 Timer (16 bits) Timer A: 5 channels Timer B: 6 channels Three-phase Motor Control Circuit Watchdog Timer (15 bits) D/A Converter (8 bits x 2 channels) Intelligent I/O ( 4 Groups ) Peripheral Functions ROM RAM Memory 87 88 5 (Note1) 88 7 8888888 8 DMAC DMACII DRAMC CAN Module Time Measurement: 12 channels(2) Wave Generating: 28 channels(2) Communication Functions: Clock Synchronous Serial I/O, UART, IEBus, HDLC Data Processing, 8-bit or 16-bit Clock Synchronous Serial I/O (3)

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M

1.4 Product Information

Table 1.3 lists the product information. Figure 1.2 shows the product numbering system. Table 1.3 M32C/83 Group (1) (M32C/83) As of January, 2006 Table 1.3 M32C/83 Group (2) (T Version, M32C/83T) As of January, 2006 rebmuNepyTe pyTegakcaP MOR yticapaC MAR yticapaC skrameR PGJF53803M) A-Q6P441(A-AK4410PQLP K215K 13y romeMhsalFPGJF33803M) A-Q6P001(A-BK0010PQLP PFJF33803M) A-S6P001(A-BJ0010PQRP rebmuNepyTe pyTegakcaP MOR yticapaC MAR yticapaC skrameR JF33803MT P G) A-Q6P001(A-BK0010PQLPK 215K 13 yromeMhsalF noisreVT ytilibailer-hgiH( 58 o )noisreVC Package Type: FP = Package PRQP0100JB-A (100P6S-A) GP = Package PLQP0100KB-A (100P6Q-A) ROM Capacity: J = 512 Kbytes Memory Type: F = Flash Memory Version M30 83 3 F J GP M32C/83 Group M16C Family RAM Capacity, Pin Count, etc. (Value itself has no specific meaning) Classification: Blank = General Industrial Use T = T Version Please contact our sales office for V version information. Figure 1.2 Product Numbering System

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 P146 P145 P144 OUTC1 7 / INPC17 / P143 OUTC1 6 / INPC16 / P142 OUTC1 5 / P141 OUTC1 4 / P140 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 CAN IN / INT1 / P83 ISRxD3 / OUTC32 / CANOUT / INT0 / P82 ISTxD3 / OUTC30 / U / TA4IN / P81 BE0 IN / ISRxD0 / INPC02 / U / TA4OUT / P80 CAN IN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 CAN OUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (3) IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 108 107 106 105 104 103 102 101 100 131 132 133 134 135 136 137 138 139 140 141 142 143 144 125 126 127 128 129 130 119 120 121 122 123 124 113 114 115 116 117 118 109 110 111 112 M32C/83 GROUP (M32C/83, M32C/83T) PLQP0144KA-A (144P6Q-A) P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss Vcc P12 0 / OUTC30 / ISTxD3 P121 / OUTC31 / ISCLK3 P122 / OUTC32 / ISRxD3 P123 / OUTC33 P124 / OUTC34 P31 / A9 ( MA1 ) ( / D9 ) P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) Vss 2 / A18 ( MA10 ) Vcc 3 / A19 ( MA11 ) D 8 / P10 AN07 / D7 / P07 AN06 / D6 / P06 AN05 / D5 / P05 AN04 / D4 / P04 P114 OUTC1 3 / P113 BE1 IN / ISRxD1 / OUTC12 / INPC12 / P112 ISCLK1 / OUTC11 / INPC11 / P111 BE1 OUT / ISTxD1 / OUTC10 / P110 AN03 / D3 / P03 AN02 / D2 / P02 AN01 / D1 / P01 AN00 / D0 / P00 INPC0 7 / AN157 / P157 INPC0 6 / AN156 / P156 OUTC0 5 / INPC05 / AN155 / P155 OUTC0 4 / INPC04 / AN154 / P154 INPC0 3 / AN153 / P153 BE0 IN / ISRxD0 / INPC02 / AN152 / P152 ISCLK0 / OUTC01 / INPC01 / AN151 / P151 Vss BE0 OUT / ISTxD0 / OUTC00 / INPC00 / AN150 / P150 Vcc KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P125 / OUTC35 P126 / OUTC36 P127 / OUTC37 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P130 / OUTC24 P131 / OUTC25 Vcc P13 2 / OUTC26 Vss P13 3 / OUTC23 P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P134 / OUTC20 / ISTxD2 / IEOUT P135 / OUTC22 / ISRxD2 / IEIN P136 / OUTC21 / ISCLK2 P137 / OUTC27 P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 Vss 6 / RxD1 / SCL1 / STxD1 Vcc 7 / TxD1 / SDA1 / SRxD1 P70(2, 3) NOTES: 1. P6 4 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P7 0 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P7 0 and P71 are ports for the N-channel open drain output.

1.5 Pin Assignment

Figures 1.3 to 1.5 show pin assignments (top view). Figure 1.3 Pin Assignment for 144-Pin Package

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M BYTE CNV SS XCIN/VCONT XCOUT RESET X OUT VSS XIN VCC VCC VSS P96 P95 P94 P93 P92 P91 P90 P146 P145 P144 P143 P142 P141 P140 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P137 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CAN IN CAN OUT CAN IN CAN OUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 OUTC2 0/IEOUT /ISTxD2 IEIN/ISRxD2 INPC1 7/OUTC1 7 INPC1 6/OUTC1 6 OUTC1 5 OUTC1 4 OUTC3 2/ISRxD3 OUTC3 0/ISTxD3 INPC0 2/ISRxD0/BE0IN INPC0 1/OUTC0 1/ISCLK0 INPC0 0/OUTC0 0/ISTxD0/BE0OUT INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 OUTC1 0/ISTxD1/BE1OUT OUTC2 2/ISRxD2/IEIN OUTC2 0/ISTxD2/IEOUT OUTC2 1/ISCLK2 OUTC2 7 ANEX1 ANEX0 DA1 DA0 Intelligent I/O Pin Bus Control Pin (1)Analog Pin Interrupt Pin Pin No Control Pin Port Timer Pin UART/CAN Pin NOTES: 1. Bus control pins in M32C/83T cannot be used. Table 1.4 Pin Characteristics for 144-Pin Package

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M VSS VCC VCC VSS VCC VSS P136 P135 P134 P57 P56 P55 P54 P133 P132 P131 P130 P53 P52 P51 P50 P127 P126 P125 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P124 P123 P122 P121 P120 P30 P27 P26 P25 Timer Pin UART/CAN Pin OUTC2 1/ISCLK2 OUTC2 2/ISRxD2/IEIN OUTC2 0/ISTxD2/IEOUT OUTC2 3 OUTC2 6 OUTC2 5 OUTC2 4 OUTC3 7 OUTC3 6 OUTC3 5 OUTC3 4 OUTC3 3 OUTC3 2/ISRxD3 OUTC3 1/ISCLK3 OUTC3 0/ISTxD3 AN2 7 AN2 6 AN2 5 RDY ALE/RAS HOLD HLDA/ALE CLK OUT /BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL CS0/A CS1/A22 CS2/A21 CS3/A20(MA 12) A19(MA 11) A18(MA 10) A17(MA 9) A16(MA 8) A15(MA 7)(/D15) A14(MA 6)(/D14) A13(MA 5)(/D13) A12(MA 4)(/D12) A11(MA 3)(/D11) A10(MA 2)(/D10) A9(MA 1)(/D9) A8(MA 0)(/D8) A7(/D7) A6(/D6) A5(/D5) Intelligent I/O Pin Bus Control Pin (1)Analog Pin Interrupt Pin Pin No Control Pin Port NOTES: 1. Bus control pins in M32C/83T cannot be used. Table 1.4 Pin Characteristics for 144-Pin Package (Continued)

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS VCC AV SS VREF AV CC P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P114 P113 P112 P111 P110 P03 P02 P01 P00 P157 P156 P155 P154 P153 P152 P151 P150 P107 P106 P105 P104 P103 P102 P101 P100 P97 INT5 INT4 INT3 KI KI2 KI1 KI0 Timer Pin RxD4/SCL4/STxD4 AN2 4 AN2 3 AN2 2 AN2 1 AN2 0 AN0 7 AN0 6 AN0 5 AN0 4 AN0 3 AN0 2 AN0 1 AN0 0 AN15 7 AN15 6 AN15 5 AN15 4 AN15 3 AN15 2 AN15 1 AN15 0 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 AD TRG A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Bus Control Pin(1)Analog Pin Interrupt Pin Pin No OUTC1 3 INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 OUTC1 0/ISTxD1/BE1OUT INPC0 7 INPC0 6 INPC0 5/OUTC0 5 INPC0 4/OUTC0 4 INPC0 3 INPC0 2/ISRxD0/BE0IN INPC0 1/OUTC0 1/ISCLK0 INPC0 0/OUTC0 0/ISTxD0/BE0OUT Control Pin Port UART/CAN Pin Intelligent I/O Pin NOTES: 1. Bus control pins in M32C/83T cannot be used. Table 1.4 Pin Characteristics for 144-Pin Package (Continued)

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M 100 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 CANIN / INT1 / P83 ISRxD3 / OUTC32 / CANOUT / INT0 / P82 ISTxD3 / OUTC30 / U / TA4IN / P81 BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 CAN IN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 CAN OUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (3)IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 (3)IEOUT / ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70 P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P10 / D8 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss Vcc P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) P42 / A18 ( MA10 ) P43 / A19 ( MA11 ) D 7 / AN07 / P07 D 6 / AN06 / P06 D 5 / AN05 / P05 D 4 / AN04 / P04 D 3 / AN03 / P03 D 2 / AN02 / P02 D 1 / AN01 / P01 D 0 / AN00 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc (2)P97 M32C/83 GROUP (M32C/83, M32C/83T) PRQP0100JB-A (100P6S-A) NOTES: 1. P6 4 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P9 7 / ADTRG / RxD4 / STxD4 / SCL4 3. P7 0 and P71 are ports for the N-channel open drain output. Figure 1.4 Pin Assignment for 100-Pin Package

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M 100 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN/ ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 CAN IN / INT1 / P83 ISRxD3 / OUTC32 / CAN OUT / INT0 / P82 ISTxD3 / OUTC30 / U / TA4IN / P81 BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 CAN IN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 CAN OUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 P42 / A18 ( MA10 ) P43 / A19 ( MA11 ) P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70(2, 4) P71(3, 4) P72 / TA1OUT / V / CLK2 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss Vcc P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) D 10 / P12 D 9 / P11 D 8 / P10 D 7 / AN07 / P07 D 6 / AN06 / P06 D 5 / AN05 / P05 D 4 / AN04 / P04 D 3 / AN03 / P03 D 2 / AN02 / P02 D 1 / AN01 / P01 D 0 / AN00 / P00 KI3 / AN37 / P107 KI2 / AN36 / P106 KI1 / AN35 / P105 KI0 / AN34 / P104 AN3 3 / P103 AN3 2 / P102 AN3 1 / P101 AVss AN3 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 M32C/83 GROUP (M32C/83, M32C/83T) PLQP0100KB-A (100P6Q-A) NOTES: 1. P6 4 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P7 0 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P7 1 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22 / ISRxD2 / IEIN 4. P7 0 and P71 are ports for the N-channel open drain output. Figure 1.5 Pin Assignment for 100-Pin Package

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M BYTE CNV SS XCIN/VCONT XCOUT RESET X OUT VSS XIN VCC P96 P95 P94 P93 P92 P91 P90 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CAN IN CAN OUT CAN IN CAN OUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 OUTC2 0/IEOUT /ISTxD2 IEIN/ISRxD2 OUTC3 2/ISRxD3 OUTC3 0/ISTxD3 INPC0 2/ISRxD0/BE0IN INPC0 1/OUTC0 1/ISCLK0 INPC0 0/OUTC0 0/ISTxD0/BE0OUT INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 OUTC1 0/ISTxD1/BE1OUT OUTC2 2/ISRxD2/IEIN OUTC2 0/ISTxD2/IEOUT OUTC2 1/ISCLK2 ANEX1 ANEX0 DA1 DA0 100 RDY ALE/RAS HOLD HLDA/ALE CLK OUT /BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL CS0/A CS1/A22 CS2/A21 CS3/A20(MA 12) Package Pin No FP GP Control Pin Port Timer Pin UART/CAN Pin Intelligent I/O Pin Bus Control Pin(1)Analog Pin Interrupt Pin NOTES: 1. Bus control pins in M32C/83T cannot be used. Table 1.5 Pin Characteristics for 100-Pin Package

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M 100 VCC VSS AV SS VREF AV CC P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 P100 P97 Timer Pin UART/CAN Pin AN2 7 AN2 6 AN2 5 AN2 4 AN2 3 AN2 2 AN2 1 AN2 0 AN0 7 AN0 6 AN0 5 AN0 4 AN0 3 AN0 2 AN0 1 AN0 0 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 AD TRG A19(MA 11) A18(MA 10) A17(MA 9) A16(MA 8) A15(MA 7)(/D15) A14(MA 6)(/D14) A13(MA 5)(/D13) A12(MA 4)(/D12) A11(MA 3)(/D11) A10(MA 2)(/D10) A9(MA 1)(/D9) A8(MA 0)(/D8) A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Intelligent I/O Pin Bus Control Pin (1)Analog Pin Interrupt Pin INT5 INT4 INT3 KI KI2 KI1 KI0 RxD4/SCL4/STxD4 FP GP Package Pin No Control Pin Port NOTES: 1. Bus control pins in M32C/83T cannot be used. Table 1.5 Pin Characteristics for 100-Pin Package (Continued)

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M Apply 3.0 to 5.5V to both VCC pin. Apply 0V to the VSS pin. (1) Supplies power to the A/D converter. Connect the AVCC pin to VCC and the AV SS pin to VSS The microcomputer is in a reset state when "L" is applied to the RESET pin Switches processor mode. Connect the CNVSS pin to VSS to start up in single- chip mode or to VCC to start up in microprocessor mode Switches data bus width in external memory space 3. The data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Set to either. Connect the BYTE pin to VSS to use the microcomputer in single-chip mode Inputs and outputs data (D 0 to D7) while accessing an external memory space with separate bus Inputs and outputs data (D 8 to D15) while accessing an external memory space with 16-bit separate bus Outputs address bits A0 to A22 Outputs inversed address bit A23 Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing while accessing an external memory space with multiplexed bus Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing while accessing an external memory space with 16-bit multiplexed bus Outputs CS0 to CS3 that are chip-select signals specifying an external space Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH can be switched with WR and BHE by program WRL, WRH and RD selected: If external data bus is 16 bits wide, data is written to an even address in external memory space when WRL is held "L". Data is written to an odd address when WRH is held "L". Data is read when RD is held "L". WR, BHE and RD selected: Data is written to external memory space when WR is held "L". Data in an external memory space is read when RD is held "L". An odd address is accessed when BHE is held "L". Select WR, BHE and RD for external 8-bit data bus. ALE is a signal latching the address The microcomputer is placed in a hold state while the HOLD pin is held "L" Outputs an "L" signal while the microcomputer is placed in a hold state Bus is placed in a wait state while the RDY pin is held "L" When DRAM area is accessed, outputs column and row addresses by time-sharing. The DW signal becomes "L" when data is written to the DRAM area. CASL and CASH are signals indicating the timing to latch column addresses. The CASL signal becomes "L" when an even address is accessed. The CASH signal becomes "L" when an odd address is accessed. RAS is a signal latching row addresses. VCC VSS AV CC AV SS RESET CNV SS BYTE D 0 to D7 D 8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL / WR WRH / BHE RD ALE HOLD HLDA RDY MA 0 to MA12 DW CASL CASH RAS Power Supply Analog Power Supply Reset Input CNV SS Input to Switch External Data Bus Width(2) Bus Control Pins(2) DRAM Bus Control Pin(2) I I I I I I/O I/O O O I/O I/O O O O I O I O O I : Input O : Output I/O : Input and output NOTES: 1. Apply 4.2 to 5.5V to the VCC pin when using M32C/83T. 2. Bus control pins in M32C/83T cannot be used. Classsfication Symbol I/O Type Function

1.6 Pin Description

Table 1.6 Pin Description (100-Pin and 144-Pin Packages)

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M XIN XOUT XCIN XCOUT VCONT BCLK CLK OUT INT0 to INT5 NMI KI0 to KI3 TA0 OUT to TA4 OUT TA0 IN to TA4 IN TB0 IN to TB5 IN U, U, V, V, ___ W, W CTS0 to CTS4 RTS0 to RTS4 CLK0 to CLK4 RxD0 to RxD4 TxD0 to TxD4 SDA0 to SDA4 SCL0 to SCL4 Main Clock Input Main Clock Output Sub Clock Input Sub Clock Output Low-Pass Filter Connect Pin for PLL Frequency Synthesizer Pin BCLK Output(1) Clock Output INT Interrupt Input NMI Interrupt Input Key Input Interrupt Timer A Timer B Three-phase Motor Control Timer Output Serial I/O I2C Mode I O I O O O I I I I/O I I O I O I/O I O I/O I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT . To apply external clock, apply it to XIN and leave XOUT open I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT . To apply external clock, apply it to XCIN and leave XCOUT open Connects the low-pass filter to the VCONT pin when using the PLL fre- quency synthesizer. Connect P86 to VSS to stabilize the PLL frequency. Outputs BCLK signal Outputs the clock having the same frequency as fC , f8 or f32 Input pins for the INT interrupt Input pin for the NMI interrupt Input pins for the key input interrupt I/O pins for the timer A0 to A4 (TA0OUT is a pin for the N-channel open drain output.) Input pins for the timer A0 to A4 Input pins for the timer B0 to B5 Output pins for the three-phase motor control timer Input pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Outputs serial data (TxD2 is a pin for the N-channel open drain output.) Inputs and outputs serial data (SDA2 is a pin for the N-channel open drain output.) Inputs and outputs the transfer clock (SCL2 is a pin for the N-channel open drain output.) I : Input O : Output I/O : Input and output NOTE: 1. Bus control pins in M32C/83T cannot be used. Classsfication Symbol I/O Type Function Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M STxD0 to STxD4 SRxD0 to SRxD4 SS0 to SS4 VREF AN 0 to AN7 AN0 0 to AN07 AN2 0 to AN27 AN15 0 to AN157 AD TRG ANEX0 ANEX1 DA0, DA1 INPC0 0 to INPC02 INPC0 3 to INPC0 7(1) INPC1 1 to INPC12 INPC1 6 to INPC1 7(1) OUTC0 0 to OUTC02 OUTC0 4 to OUTC0 5(1) OUTC1 0 to OUTC12 OUTC1 3 to OUTC1 7(1) OUTC2 0 to OUTC22 OUTC2 3 to OUTC2 7(1) OUTC3 0 to OUTC32 OUTC3 1, OUTC3 3 to OUTC3 7(1) ISCLK0 to ISCLK2 ISCLK3 (1) ISRXD0 to ISRXD3 ISTXD0 to ISTXD3 BE0 IN, BE1 IN BE0 OUT, BE1 OUT IEIN IEOUT CAN IN CAN OUT Serial I/O Special Function Reference Voltage Input A/D ConverterD/A Converter Intelligent I/O CAN Outputs serial data when slave mode is selected Inputs serial data when slave mode is selected Input pins to control serial I/O special function Applies reference voltage to the A/D converter and D/A converter Analog input pins for the A/D converter Input pin for an external A/D trigger Extended analog input pin for the A/D converter and output pin in external op-amp connection mode Extended analog input pin for the A/D converter Output pin for the D/A converter Input pins for the time measurement function Output pins for the waveform generating function (OUTC2 0 and OUTC2 2 assigned to P70 and P71 are pins for the N-channel open drain output.) Inputs and outputs the clock for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Input pin for the CAN communication function Output pin for the CAN communication function O I I I I I I/O I O I O I/O I O I O I O I O I : Input O : Output I/O : Input and output NOTE: 1. Available in the 144-pin package only. Classsfication Symbol I/O Type Function Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)

Overview 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P90 to P97 P10 0 to P107 P11 0 to P114 P12 0 to P127 P13 0 to P137 P14 0 to P146 P15 0 to P157 (1) P80 to P84 P86, P87 P85 I/O I/O I/O I 8-bit I/O ports for CMOS. Each port can be programmed for input or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units (P70 and P71 are ports for the N-channel open drain output.) I/O ports having equivalent functions to P0 I/O ports having equivalent functions to P0 Shares a pin with NMI. NMI input state can be got by reading P85 I : Input O : Output I/O : Input and output NOTE: 1. Available in the 144-pin package only. Classsfication Symbol I/O Type Function I/O Ports Input Port Table 1.6 Pin Description (144-Pin Package only) (Continued)

Page 19 884fo6002,13.naJ13.1.veR 1310-4300B90JER 2. Central Processing Unit (CPU))T38/C23M,38/C23M(puorG38/C23M

2.1 General Registers

2.1.1 Data Registers (R0, R1, R2 and R3)

R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3.

2.1.2 Address Registers (A0 and A1)

A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith- metic and logic operations.

2.1.3 Static Base Register (SB)

SB is a 24-bit register for SB-relative addressing.

2.1.4 Frame Base Register (FB)

FB is a 24-bit register for FB-relative addressing.

2.1.5 Program Counter (PC)

PC, 24 bits wide, indicates the address of an instruction to be executed.

2.1.6 Interrupt Table Register (INTB)

INTB is a 24-bit register indicating the starting address of an interrupt vector table.

2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to "2.1.8 Flag Register (FLG)" for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.

2.1.8 Flag Register (FLG)

FLG is a 16-bit register indicating a CPU state.

2.1.8.1 Carry Flag (C)

The C flag indicates whether carry or borrow has occurred after executing an instruction.

2.1.8.2 Debug Flag (D)

The D flag is for debug only. Set to "0".

2.1.8.3 Zero Flag (Z)

The Z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0".

2.1.8.4 Sign Flag (S)

The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0".

Page 20 884fo6002,13.naJ13.1.veR 1310-4300B90JER 2. Central Processing Unit (CPU))T38/C23M,38/C23M(puorG38/C23M

2.1.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1".

2.1.8.6 Overflow Flag (O)

The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".

2.1.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged.

2.1.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.1.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.1.8.10 Reserved Space

When writing to a reserved space, set to "0". When read, its content is indeterminate.

2.2 High-Speed Interrupt Registers

Registers associated with the high-speed interrupt are as follows. Refer to 10.4 High-Speed Interrupt for details. - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT)

2.3 DMAC-Associated Registers

Registers associated with DMAC are as follows. Refer to 12. DMAC for details. - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1)

Page 22 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 000016 000116 000216 000316 1000 00002 (CNVss pin ="L")

000416 Processor Mode Register 0(1) PM0 0000 00112 (CNVss pin ="H")

000516 Processor Mode Register 1 PM1 0X00 0000 2

000616 System Clock Control Register 0 CM0 0000 X000 2

000716 System Clock Control Register 1 CM1 0010 0000 2

000816 Wait Control Register(2) WCR 1111 1111 2

000916 Address Match Interrupt Enable Register AIER XXXX 0000 2

000A 16 Protect Register PRCR XXXX 0000 2 XXXX 1000 2 (BYTE pin ="L") 000B 16 External Data Bus Width Control Register(2) DS XXXX 0000 2 (BYTE pin ="H") 000C 16 Main Clock Division Register MCD XXX0 1000 2 000D 16 Oscillation Stop Detection Register CM2 00 16 000E 16 Watchdog Timer Start Register WDTS XX 16 000F16 Watchdog Timer Control Register WDC 000X XXXX 2 001016

001116 Address Match Interrupt Register 0 RMAD0 00 00 00 16

001516 Address Match Interrupt Register 1 RMAD1 00 00 00 16

001716 VDC Control Register for PLL PLV XXXX XX01 2

001916 Address Match Interrupt Register 2 RMAD2 00 00 00 16

001B 16 VDC Control Register 0 VDC0 00 16 001C 16 001D 16 Address Match Interrupt Register 3 RMAD3 00 00 00 16 001E 16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A 16 002B 16 002C 16 002D 16 002E 16 002F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The PM00 and PM01 bits in the PM1 register maintain values set before reset even if software reset or watchdog timer reset is performed. 2. These registers in M32C/83T cannot be used. 4. Special Function Registers (SFR)

Page 23 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A 16 003B 16 003C 16 003D 16 003E 16 003F16

004016 DRAM Control Register (1) DRAMCONT XX 16

004116 DRAM Refresh Interval Set Register (1) REFCNT XX 16

005716 Flash Memory Control Register 0 FMR0 XX00 0001 2

X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. These registers in M32C/83T cannot be used.

Page 24 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 006016 006116 006216 006316 006416 006516 006616 006716

006816 DMA0 Interrupt Control Register DM0IC XXXX X000 2

006916 Timer B5 Interrupt Control Register TB5IC XXXX X000 2

006A 16 DMA2 Interrupt Control Register DM2IC XXXX X000 2 006B 16 UART2 Receive /ACK Interrupt Control Register S2RIC XXXX X000 2 006C 16 Timer A0 Interrupt Control Register TA0IC XXXX X000 2 006D 16 UART3 Receive /ACK Interrupt Control Register S3RIC XXXX X000 2 006E 16 Timer A2 Interrupt Control Register TA2IC XXXX X000 2 006F16 UART4 Receive /ACK Interrupt Control Register S4RIC XXXX X000 2

007016 Timer A4 Interrupt Control Register TA4IC XXXX X000 2

007116 UART0/UART3 Bus Conflict Detect Interrupt Control Register BCN0IC/BCN3IC XXXX X000 2

007216 UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X000 2

007316 A/D0 Conversion Interrupt Control Register AD0IC XXXX X000 2

007416 UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X000 2

007516 Intelligent I/O Interrupt Control Register 0 IIO0IC XXXX X000 2

007616 Timer B1 Interrupt Control Register TB1IC XXXX X000 2

007716 Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X000 2

007816 Timer B3 Interrupt Control Register TB3IC XXXX X000 2

007916 Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X000 2

007A 16 INT5 Interrupt Control Register INT5IC XX00 X000 2 007B 16 Intelligent I/O Interrupt Control Register 6 IIO6IC XXXX X000 2 007C 16 INT3 Interrupt Control Register INT3IC XX00 X000 2 007D 16 Intelligent I/O Interrupt Control Register 8 IIO8IC XXXX X000 2 007E 16 INT1 Interrupt Control Register INT1IC XX00 X000 2 Intelligent I/O Interrupt Control Register 10/ IIO10IC 007F16 XXXX X000 2CAN Interrupt 1 Control Register CAN1IC 008016 Intelligent I/O Interrupt Control Register 11/ IIO11IC

008116 XXXX X000 2CAN Interrupt 2 Control Register CAN2IC

008616 A/D1 Conversion Interrupt Control Register AD1IC XXXX X000 2

008816 DMA1 Interrupt Control Register DM1IC XXXX X000 2

008916 UART2 Transmit /NACK Interrupt Control Register S2TIC XXXX X000 2

008A 16 DMA3 Interrupt Control Register DM3IC XXXX X000 2 008B 16 UART3 Transmit /NACK Interrupt Control Register S3TIC XXXX X000 2 008C 16 Timer A1 Interrupt Control Register TA1IC XXXX X000 2 008D 16 UART4 Transmit /NACK Interrupt Control Register S4TIC XXXX X000 2 008E 16 Timer A3 Interrupt Control Register TA3IC XXXX X000 2 008F16 UART2 Bus Conflict Detect Interrupt Control Register BCN2IC XXXX X000 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 25 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET

009016 UART0 Transmit /NACK Interrupt Control Register S0TIC XXXX X000 2

009116 UART1/UART4 Bus Conflict Detect Interrupt Control Register BCN1IC/BCN4IC XXXX X000 2

009216 UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X000 2

009316 Key Input Interrupt Control Register KUPIC XXXX X000 2

009416 Timer B0 Interrupt Control Register TB0IC XXXX X000 2

009516 Intelligent I/O Interrupt Control Register 1 IIO1IC XXXX X000 2

009616 Timer B2 Interrupt Control Register TB2IC XXXX X000 2

009716 Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X000 2

009816 Timer B4 Interrupt Control Register TB4IC XXXX X000 2

009916 Intelligent I/O Interrupt Control Register 5 IIO5IC XXXX X000 2

009A 16 INT4 Interrupt Control Register INT4IC XX00 X000 2 009B 16 Intelligent I/O Interrupt Control Register 7 IIO7IC XXXX X000 2 009C 16 INT2 Interrupt Control Register INT2IC XX00 X000 2 Intelligent I/O Interrupt Control Register 9/ IIO9IC 009D 16 XXXX X000 2CAN Interrupt 0 Control Register CAN0IC 009E 16 INT0 Interrupt Control Register INT0IC XX00 X000 2 009F16 Exit Priority Control Register RLVL XXXX 0000 2 00A0 16 Interrupt Request Register 0 IIO0IR 0000 000X 2 00A1 16 Interrupt Request Register 1 IIO1IR 0000 000X 2 00A2 16 Interrupt Request Register 2 IIO2IR 0000 000X 2 00A3 16 Interrupt Request Register 3 IIO3IR 0000 000X 2 00A4 16 Interrupt Request Register 4 IIO4IR 0000 000X 2 00A5 16 Interrupt Request Register 5 IIO5IR 0000 000X 2 00A6 16 Interrupt Request Register 6 IIO6IR 0000 000X 2 00A7 16 Interrupt Request Register 7 IIO7IR 0000 000X 2 00A8 16 Interrupt Request Register 8 IIO8IR 0000 000X 2 00A9 16 Interrupt Request Register 9 IIO9IR 0000 000X 2 00AA 16 Interrupt Request Register 10 IIO10IR 0000 000X 2 00AB 16 Interrupt Request Register 11 IIO11IR 0000 000X 2 00AC 16 00AD 16 00AE 16 00AF 16 00B0 16 Interrupt Enable Register 0 IIO0IE 00 16 00B1 16 Interrupt Enable Register 1 IIO1IE 00 16 00B2 16 Interrupt Enable Register 2 IIO2IE 00 16 00B3 16 Interrupt Enable Register 3 IIO3IE 00 16 00B4 16 Interrupt Enable Register 4 IIO4IE 00 16 00B5 16 Interrupt Enable Register 5 IIO5IE 00 16 00B6 16 Interrupt Enable Register 6 IIO6IE 00 16 00B7 16 Interrupt Enable Register 7 IIO7IE 00 16 00B8 16 Interrupt Enable Register 8 IIO8IE 00 16 00B9 16 Interrupt Enable Register 9 IIO9IE 00 16 00BA 16 Interrupt Enable Register 10 IIO10IE 00 16 00BB 16 Interrupt Enable Register 11 IIO11IE 00 16 00BC 16 00BD 16 00BE 16 00BF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 26 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 00C0 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 0 G0TM0/G0PO000C1 16 XX 16 00C2 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 1 G0TM1/G0PO100C3 16 XX 16 00C4 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 2 G0TM2/G0PO200C5 16 XX 16 00C6 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 3 G0TM3/G0PO300C7 16 XX 16 00C8 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 4 G0TM4/G0PO400C9 16 XX 16 00CA 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 5 G0TM5/G0PO500CB 16 XX 16 00CC 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 6 G0TM6/G0PO600CD 16 XX 16 00CE 16 XX 16 Group 0 Time Measurement/Waveform Generating Register 7 G0TM7/G0PO700CF 16 XX 16 00D0 16 Group 0 Waveform Generating Control Register 0 G0POCR0 0X00 X000 2 00D1 16 Group 0 Waveform Generating Control Register 1 G0POCR1 0X00 X000 2 00D2 16 Group 0 Waveform Generating Control Register 2 G0POCR2 0X00 X000 2 00D3 16 Group 0 Waveform Generating Control Register 3 G0POCR3 0X00 X000 2 00D4 16 Group 0 Waveform Generating Control Register 4 G0POCR4 0X00 X000 2 00D5 16 Group 0 Waveform Generating Control Register 5 G0POCR5 0X00 X000 2 00D6 16 Group 0 Waveform Generating Control Register 6 G0POCR6 0X00 X000 2 00D7 16 Group 0 Waveform Generating Control Register 7 G0POCR7 0X00 X000 2 00D8 16 Group 0 Time Measurement Control Register 0 G0TMCR0 00 16 00D9 16 Group 0 Time Measurement Control Register 1 G0TMCR1 00 16 00DA 16 Group 0 Time Measurement Control Register 2 G0TMCR2 00 16 00DB 16 Group 0 Time Measurement Control Register 3 G0TMCR3 00 16 00DC 16 Group 0 Time Measurement Control Register 4 G0TMCR4 00 16 00DD 16 Group 0 Time Measurement Control Register 5 G0TMCR5 00 16 00DE 16 Group 0 Time Measurement Control Register 6 G0TMCR6 00 16 00DF 16 Group 0 Time Measurement Control Register 7 G0TMCR7 00 16 00E0 16 XX 16 Group 0 Base Timer Register G0BT00E1 16 XX 16 00E2 16 Group 0 Base Timer Control Register 0 G0BCR0 00 16 00E3 16 Group 0 Base Timer Control Register 1 G0BCR1 00 16 00E4 16 Group 0 Time Measurement Prescaler Register 6 G0TPR6 00 16 00E5 16 Group 0 Time Measurement Prescaler Register 7 G0TPR7 00 16 00E6 16 Group 0 Function Enable Register G0FE 00 16 00E7 16 Group 0 Function Select Register G0FS 00 16 00E8 16 XXXX XXXX 2 Group 0 SI/O Receive Buffer Register G0RB00E9 16 XX00 XXXX 2 00EA 16 Group 0 Transmit Buffer/Receive Data Register G0TB/G0DR XX 16 00EB 16 00EC 16 Group 0 Receive Input Register G0RI XX 16 00ED 16 Group 0 SI/O Communication Mode Register G0MR 00 16 00EE 16 Group 0 Transmit Output Register G0TO XX 16 00EF 16 Group 0 SI/O Communication Control Register G0CR 0000 X000 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 27 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 00F016 Group 0 Data Compare Register 0 G0CMP0 XX 16 00F116 Group 0 Data Compare Register 1 G0CMP1 XX 16 00F216 Group 0 Data Compare Register 2 G0CMP2 XX 16 00F316 Group 0 Data Compare Register 3 G0CMP3 XX 16 00F416 Group 0 Data Mask Register 0 G0MSK0 XX 16 00F516 Group 0 Data Mask Register 1 G0MSK1 XX 16 00F616 00F716 00F816 XX 16 Group 0 Receive CRC Code Register G0RCRC00F916 XX 16 00FA 16 0016 Group 0 Transmit CRC Code Register G0TCRC00FB 16 0016 00FC 16 Group 0 SI/O Extended Mode Register G0EMR 00 16 00FD 16 Group 0 SI/O Extended Receive Control Register G0ERC 00 16 00FE 16 Group 0 SI/O Special Communication Interrupt Detect Register G0IRF 0000 00XX 2 00FF 16 Group 0 SI/O Extended Transmit Control Register G0ETC 0000 0XXX 2

010016 XX 16

Group 1 Time Measurement/Waveform Generating Register 0 G1TM0/G1PO0010116 XX 16

010216 XX 16

Group 1 Time Measurement/Waveform Generating Register 1 G1TM1/G1PO1010316 XX 16

010416 XX 16

Group 1 Time Measurement/Waveform Generating Register 2 G1TM2/G1PO2010516 XX 16

010616 XX 16

Group 1 Time Measurement/Waveform Generating Register 3 G1TM3/G1PO3010716 XX 16

010816 XX 16

Group 1 Time Measurement/Waveform Generating Register 4 G1TM4/G1PO4010916 XX 16 010A 16 XX 16 Group 1 Time Measurement/Waveform Generating Register 5 G1TM5/G1PO5010B 16 XX 16 010C 16 XX 16 Group 1 Time Measurement/Waveform Generating Register 6 G1TM6/G1PO6010D 16 XX 16 010E 16 XX 16 Group 1 Time Measurement/Waveform Generating Register 7 G1TM7/G1PO7010F16 XX 16

011016 Group 1 Waveform Generating Control Register 0 G1POCR0 0X00 X000 2

011116 Group 1 Waveform Generating Control Register 1 G1POCR1 0X00 X000 2

011216 Group 1 Waveform Generating Control Register 2 G1POCR2 0X00 X000 2

011316 Group 1 Waveform Generating Control Register 3 G1POCR3 0X00 X000 2

011416 Group 1 Waveform Generating Control Register 4 G1POCR4 0X00 X000 2

011516 Group 1 Waveform Generating Control Register 5 G1POCR5 0X00 X000 2

011616 Group 1 Waveform Generating Control Register 6 G1POCR6 0X00 X000 2

011716 Group 1 Waveform Generating Control Register 7 G1POCR7 0X00 X000 2

011816 Group 1 Time Measurement Control Register 0 G1TMCR0 00 16

011916 Group 1 Time Measurement Control Register 1 G1TMCR1 00 16

011A 16 Group 1 Time Measurement Control Register 2 G1TMCR2 00 16 011B 16 Group 1 Time Measurement Control Register 3 G1TMCR3 00 16 011C 16 Group 1 Time Measurement Control Register 4 G1TMCR4 00 16 011D 16 Group 1 Time Measurement Control Register 5 G1TMCR5 00 16 011E 16 Group 1 Time Measurement Control Register 6 G1TMCR6 00 16 011F16 Group 1 Time Measurement Control Register 7 G1TMCR7 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 28 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET

012016 XX 16

Group 1 Base Timer Register G1BT012116 XX 16

012216 Group 1 Base Timer Control Register 0 G1BCR0 00 16

012316 Group 1 Base Timer Control Register 1 G1BCR1 00 16

012416 Group 1 Time Measurement Prescaler Register 6 G1TPR6 00 16

012516 Group 1 Time Measurement Prescaler Register 7 G1TPR7 00 16

012616 Group 1 Function Enable Register G1FE 00 16

012716 Group 1 Function Select Register G1FS 00 16

012816 XXXX XXXX 2

Group 1 SI/O Receive Buffer Register G1RB012916 XX00 XXXX 2 012A 16 Group 1 Transmit Buffer/Receive Data Register G1TB/G1DR XX 16 012B 16 012C 16 Group 1 Receive Input Register G1RI XX 16 012D 16 Group 1 SI/O Communication Mode Register G1MR 00 16 012E 16 Group 1 Transmit Output Register G1TO XX 16 012F16 Group 1 SI/O Communication Control Register G1CR 0000 X000 2

013016 Group 1 Data Compare Register 0 G1CMP0 XX 16

013116 Group 1 Data Compare Register 1 G1CMP1 XX 16

013216 Group 1 Data Compare Register 2 G1CMP2 XX 16

013316 Group 1 Data Compare Register 3 G1CMP3 XX 16

013416 Group 1 Data Mask Register 0 G1MSK0 XX 16

013516 Group 1 Data Mask Register 1 G1MSK1 XX 16

013816 XX 16

Group 1 Receive CRC Code Register G1RCRC013916 XX 16 013A 16 0016 Group 1 Transmit CRC Code Register G1TCRC013B 16 0016 013C 16 Group 1 SI/O Extended Mode Register G1EMR 00 16 013D 16 Group 1 SI/O Extended Receive Control Register G1ERC 00 16 013E 16 Group 1 SI/O Special Communication Interrupt Detect Register G1IRF 0000 00XX 2 013F16 Group 1 SI/O Extended Transmit Control Register G1ETC 0000 0XXX 2

014016 XX 16

Group 2 Waveform Generating Register 0 G2PO0014116 XX 16

014216 XX 16

Group 2 Waveform Generating Register 1 G2PO1014316 XX 16

014416 XX 16

Group 2 Waveform Generating Register 2 G2PO2014516 XX 16

014616 XX 16

Group 2 Waveform Generating Register 3 G2PO3014716 XX 16

014816 XX 16

Group 2 Waveform Generating Register 4 G2PO4014916 XX 16 014A 16 XX 16 Group 2 Waveform Generating Register 5 G2PO5014B 16 XX 16 014C 16 XX 16 Group 2 Waveform Generating Register 6 G2PO6014D 16 XX 16 014E 16 XX 16 Group 2 Waveform Generating Register 7 G2PO7014F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 29 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET

015016 Group 2 Waveform Generating Control Register 0 G2POCR0 00 16

015116 Group 2 Waveform Generating Control Register 1 G2POCR1 00 16

015216 Group 2 Waveform Generating Control Register 2 G2POCR2 00 16

015316 Group 2 Waveform Generating Control Register 3 G2POCR3 00 16

015416 Group 2 Waveform Generating Control Register 4 G2POCR4 00 16

015516 Group 2 Waveform Generating Control Register 5 G2POCR5 00 16

015616 Group 2 Waveform Generating Control Register 6 G2POCR6 00 16

015716 Group 2 Waveform Generating Control Register 7 G2POCR7 00 16

016016 XX 16

Group 2 Base Timer Register G2BT016116 XX 16

016216 Group 2 Base Timer Control Register 0 G2BCR0 00 16

016316 Group 2 Base Timer Control Register 1 G2BCR1 00 16

016416 Base Timer Start Register BTSR XXXX 0000 2

016616 Group 2 Function Enable Register G2FE 00 16

016716 Group 2 RTP Output Buffer Register G2RTP 00 16

016A 16 Group 2 SI/O Communication Mode Register G2MR 00XX X000 2 016B 16 Group 2 SI/O Communication Control Register G2CR 0000 X000 2 016C 16 XX 16 Group 2 SI/O Transmit Buffer Register G2TB016D 16 XX 16 016E 16 XX 16 Group 2 SI/O Receive Buffer Register G2RB016F16 XX 16

017016 XX 16

Group 2 IEBus Address Register IEAR017116 XX 16

017216 Group 2 IEBus Control Register IECR 00XX X000 2

017316 Group 2 IEBus Transmit Interrupt Cause Detect Register IETIF XXX0 0000 2

017416 Group 2 IEBus Receive Interrupt Cause Detect Register IERIF XXX0 0000 2

017816 Input Function Select Register IPS 00 16

017A 16 Group 3 SI/O Communication Mode Register G3MR 00XX 0000 2 017B 16 Group 3 SI/O Communication Control Register G3CR 0000 X000 2 017C 16 XX 16 Group 3 SI/O Transmit Buffer Register G3TB017D 16 XX 16 017E 16 XX 16 Group 3 SI/O Receive Buffer Register G3RB017F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 30 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET

018016 XX 16

Group 3 Waveform Generating Register 0 G3PO0018116 XX 16

018216 XX 16

Group 3 Waveform Generating Register 1 G3PO1018316 XX 16

018416 XX 16

Group 3 Waveform Generating Register 2 G3PO2018516 XX 16

018616 XX 16

Group 3 Waveform Generating Register 3 G3PO3018716 XX 16

018816 XX 16

Group 3 Waveform Generating Register 4 G3PO4018916 XX 16 018A 16 XX 16 Group 3 Waveform Generating Register 5 G3PO5018B 16 XX 16 018C 16 XX 16 Group 3 Waveform Generating Register 6 G3PO6018D 16 XX 16 018E 16 XX 16 Group 3 Waveform Generating Register 7 G3PO7018F16 XX 16

019016 Group 3 Waveform Generating Control Register 0 G3POCR0 00 16

019116 Group 3 Waveform Generating Control Register 1 G3POCR1 00 16

019216 Group 3 Waveform Generating Control Register 2 G3POCR2 00 16

019316 Group 3 Waveform Generating Control Register 3 G3POCR3 00 16

019416 Group 3 Waveform Generating Control Register 4 G3POCR4 00 16

019516 Group 3 Waveform Generating Control Register 5 G3POCR5 00 16

019616 Group 3 Waveform Generating Control Register 6 G3POCR6 00 16

019716 Group 3 Waveform Generating Control Register 7 G3POCR7 00 16

019816 XX 16

Group 3 Waveform Generating Mask Register 4 G3MK4019916 XX 16 019A 16 XX 16 Group 3 Waveform Generating Mask Register 5 G3MK5019B 16 XX 16 019C 16 XX 16 Group 3 Waveform Generating Mask Register 6 G3MK6019D 16 XX 16 019E 16 XX 16 Group 3 Waveform Generating Mask Register 7 G3MK7019F16 XX 16 01A0 16 XX 16 Group 3 Base Timer Register G3BT01A1 16 XX 16 01A2 16 Group 3 Base Timer Control Register 0 G3BCR0 00 16 01A3 16 Group 3 Base Timer Control Register 1 G3BCR1 00 16 01A4 16 01A5 16 01A6 16 Group 3 Function Enable Register G3FE 00 16 01A7 16 Group 3 RTP Output Buffer Register G3RTP 00 16 01A8 16 01A9 16 01AA 16 01AB 16 01AC 16 01AD 16 Group 3 SI/O Communication Flag Register G3FLG XXXX XXX0 2 01AE 16 01AF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 31 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 01B0 16 01B1 16 01B2 16 01B3 16 01B4 16 01B5 16 01B6 16 01B7 16 01B8 16 01B9 16 01BA 16 01BB 16 01BC 16 01BD 16 01BE 16 01BF 16 01C0 16 XX 16 A/D1 Register 0 AD1001C1 16 XX 16 01C2 16 XX 16 A/D1 Register 1 AD1101C3 16 XX 16 01C4 16 XX 16 A/D1 Register 2 AD1201C5 16 XX 16 01C6 16 XX 16 A/D1 Register 3 AD1301C7 16 XX 16 01C8 16 XX 16 A/D1 Register 4 AD1401C9 16 XX 16 01CA 16 XX 16 A/D1 Register 5 AD1501CB 16 XX 16 01CC 16 XX 16 A/D1 Register 6 AD1601CD 16 XX 16 01CE 16 XX 16 A/D1 Register 7 AD1701CF 16 XX 16 01D0 16 01D1 16 01D2 16 01D3 16 01D4 16 A/D1 Control Register 2 AD1CON2 X00X X000 2 01D5 16 01D6 16 A/D1 Control Register 0 AD1CON0 00 16 01D7 16 A/D1 Control Register 1 AD1CON1 XX00 0000 2 01D8 16 01D9 16 01DA 16 01DB 16 01DC 16 01DD 16 01DE 16 01DF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 32 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 01E0 16 CAN0 Message Slot Buffer 0 Standard ID0 C0SLOT0_0 XX 16 01E1 16 CAN0 Message Slot Buffer 0 Standard ID1 C0SLOT0_1 XX 16 01E2 16 CAN0 Message Slot Buffer 0 Extended ID0 C0SLOT0_2 XX 16 01E3 16 CAN0 Message Slot Buffer 0 Extended ID1 C0SLOT0_3 XX 16 01E4 16 CAN0 Message Slot Buffer 0 Extended ID2 C0SLOT0_4 XX 16 01E5 16 CAN0 Message Slot Buffer 0 Data Length Code C0SLOT0_5 XX 16 01E6 16 CAN0 Message Slot Buffer 0 Data 0 C0SLOT0_6 XX 16 01E7 16 CAN0 Message Slot Buffer 0 Data 1 C0SLOT0_7 XX 16 01E8 16 CAN0 Message Slot Buffer 0 Data 2 C0SLOT0_8 XX 16 01E9 16 CAN0 Message Slot Buffer 0 Data 3 C0SLOT0_9 XX 16 01EA 16 CAN0 Message Slot Buffer 0 Data 4 C0SLOT0_10 XX 16 01EB 16 CAN0 Message Slot Buffer 0 Data 5 C0SLOT0_11 XX 16 01EC 16 CAN0 Message Slot Buffer 0 Data 6 C0SLOT0_12 XX 16 01ED 16 CAN0 Message Slot Buffer 0 Data 7 C0SLOT0_13 XX 16 01EE 16 CAN0 Message Slot Buffer 0 Time Stamp High-Order C0SLOT0_14 XX 16 01EF 16 CAN0 Message Slot Buffer 0 Time Stamp Low-Order C0SLOT0_15 XX 16 01F016 CAN0 Message Slot Buffer 1 Standard ID0 C0SLOT1_0 XX 16 01F116 CAN0 Message Slot Buffer 1 Standard ID1 C0SLOT1_1 XX 16 01F216 CAN0 Message Slot Buffer 1 Extended ID0 C0SLOT1_2 XX 16 01F316 CAN0 Message Slot Buffer 1 Extended ID1 C0SLOT1_3 XX 16 01F416 CAN0 Message Slot Buffer 1 Extended ID2 C0SLOT1_4 XX 16 01F516 CAN0 Message Slot Buffer 1 Data Length Code C0SLOT1_5 XX 16 01F616 CAN0 Message Slot Buffer 1 Data 0 C0SLOT1_6 XX 16 01F716 CAN0 Message Slot Buffer 1 Data 1 C0SLOT1_7 XX 16 01F816 CAN0 Message Slot Buffer 1 Data 2 C0SLOT1_8 XX 16 01F916 CAN0 Message Slot Buffer 1 Data 3 C0SLOT1_9 XX 16 01FA 16 CAN0 Message Slot Buffer 1 Data 4 C0SLOT1_10 XX 16 01FB 16 CAN0 Message Slot Buffer 1 Data 5 C0SLOT1_11 XX 16 01FC 16 CAN0 Message Slot Buffer 1 Data 6 C0SLOT1_12 XX 16 01FD 16 CAN0 Message Slot Buffer 1 Data 7 C0SLOT1_13 XX 16 01FE 16 CAN0 Message Slot Buffer 1 Time Stamp High-Order C0SLOT1_14 XX 16 01FF 16 CAN0 Message Slot Buffer 1 Time Stamp Low-Order C0SLOT1_15 XX 16

020016 XX01 0X01 2(1)

CAN0 Control Register 0 C0CTLR0020116 XXXX 0000 2(1) 020216 0000 00002(1) CAN0 Status Register C0STR020316 X000 0X012(1) 020416 0016(1) CAN0 Extended ID Register C0IDR020516 0016(1) 020616 0000 XXXX 2(1) CAN0 Configuration Register C0CONR020716 0000 00002(1) 020816 00161) CAN0 Time Stamp Register C0TSR020916 0016(1) 020A 16 CAN0 Transmit Error Count Register C0TEC 00 16(1) 020B 16 CAN0 Receive Error Count Register C0REC 00 16(1) 020C 16 0016(1) CAN0 Slot Interrupt Status Register C0SISTR020D 16 0016(1) 020E 16 020F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset.

Page 33 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 021016 0016(2) CAN0 Slot Interrupt Mask Register C0SIMKR021116 0016(2) 021216 021316

021416 CAN0 Error Interrupt Mask Register C0EIMKR XXXX X000 2(2)

021516 CAN0 Error Interrupt Status Register C0EISTR XXXX X000 2(2)

021716 CAN0 Baud Rate Prescaler C0BRP 0000 0001 2(2)

022816 CAN0 Global Mask Register Standard ID0 C0GMR0 XXX0 0000 2(2)

022916 CAN0 Global Mask Register Standard ID1 C0GMR1 XX00 0000 2(2)

022A 16 CAN0 Global Mask Register Extended ID0 C0GMR2 XXXX 0000 2(2) 022B 16 CAN0 Global Mask Register Extended ID1 C0GMR3 00 16(2) 022C 16 CAN0 Global Mask Register Extended ID2 C0GMR4 XX00 0000 2(2) 022D 16 022E 16 022F16 CAN0 Message Slot 0 Control Register / C0MCTL0/ 0000 0000 2(2)

023016 CAN0 Local Mask Register A Standard ID0 C0LMAR0 XXX0 0000 2(2)

CAN0 Message Slot 1 Control Register / C0MCTL1/ 0000 0000 2(2)

023116 CAN0 Local Mask Register A Standard ID1 C0LMAR1 XX00 0000 2(2)

CAN0 Message Slot 2 Control Register / C0MCTL2/ 0000 0000 2(2)

023216 CAN0 Local Mask Register A Extended ID0 C0LMAR2 XXXX 0000 2(2)

CAN0 Message Slot 3 Control Register / C0MCTL3/ 00 16(2)

023316 CAN0 Local Mask Register A Extended ID1 C0LMAR3 00 16(2)

CAN0 Message Slot 4 Control Register / C0MCTL4/ 0000 0000 2(2)

023416 CAN0 Local Mask Register A Extended ID2 C0LMAR4 XX00 0000 2(2)

023516 CAN0 Message Slot 5 Control Register C0MCTL5 00 16(2)

023616 CAN0 Message Slot 6 Control Register C0MCTL6 00 16(2)

023716 CAN0 Message Slot 7 Control Register C0MCTL7 00 16(2)

CAN0 Message Slot 8 Control Register / C0MCTL8/ 0000 0000 2(2)

023816 CAN0 Local Mask Register B Standard ID0 C0LMBR0 XXX0 0000 2(2)

X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. (Note 1)

Page 34 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET CAN0 Message Slot 9 Control Register / C0MCTL9/ 0000 0000 2(2)

023916 CAN0 Local Mask Register B Standard ID1 C0LMBR1 XX00 0000 2(2)

CAN0 Message Slot 10 Control Register / C0MCTL10/ 0000 0000 2(2) 023A 16 CAN0 Local Mask Register B Extended ID0 C0LMBR2 XXXX 0000 2(2) CAN0 Message Slot 11 Control Register / C0MCTL11/ 00 16(2) 023B 16 CAN0 Local Mask Register B Extended ID1 C0LMBR3 00 16(2) CAN0 Message Slot 12 Control Register / C0MCTL12/ 0000 0000 2(2) 023C 16 CAN0 Local Mask Register B Extended ID2 C0LMBR4 XX00 0000 2(2) 023D 16 CAN0 Message Slot 13 Control Register C0MCTL13 00 16(2) 023E 16 CAN0 Message Slot 14 Control Register C0MCTL14 00 16(2) 023F16 CAN0 Message Slot 15 Control Register C0MCTL15 00 16(2)

024016 CAN0 Slot Buffer Select Register C0SBS 00 16(2)

024116 CAN0 Control Register 1 C0CTLR1 XX00 00XX 2(2)

024216 CAN0 Sleep Control Register C0SLPR XXXX XXX0 2

024416 0016(2) CAN0 Acceptance Filter Support Register C0AFS024516 0116(2) 024616 024716 024816 024916 024A 16 024B 16 024C 16 024D 16 024E 16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A 16 025B 16 025C 16 025D 16 025E 16 025F16 026016 026116 to 02BF 16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. (Note 1)

Page 35 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 02C0 16 XX 16 X0 Register Y0 Register X0R,Y0R02C1 16 XX 16 02C2 16 XX 16 X1 Register Y1 Register X1R,Y1R02C3 16 XX 16 02C4 16 XX 16 X2 Register Y2 Register X2R,Y2R02C5 16 XX 16 02C6 16 XX 16 X3 Register Y3 Register X3R,Y3R02C7 16 XX 16 02C8 16 XX 16 X4 Register Y4 Register X4R,Y4R02C9 16 XX 16 02CA 16 XX 16 X5 Register Y5 Register X5R,Y5R02CB 16 XX 16 02CC 16 XX 16 X6 Register Y6 Register X6R,Y6R02CD 16 XX 16 02CE 16 XX 16 X7 Register Y7 Register X7R,Y7R02CF 16 XX 16 02D0 16 XX 16 X8 Register Y8 Register X8R,Y8R02D1 16 XX 16 02D2 16 XX 16 X9 Register Y9 Register X9R,Y9R02D3 16 XX 16 02D4 16 XX 16 X10 Register Y10 Register X10R,Y10R02D5 16 XX 16 02D6 16 XX 16 X11 Register Y11 Register X11R,Y11R02D7 16 XX 16 02D8 16 XX 16 X12 Register Y12 Register X12R,Y12R02D9 16 XX 16 02DA 16 XX 16 X13 Register Y13 Register X13R,Y13R02DB 16 XX 16 02DC 16 XX 16 X14 Register Y14 Register X14R,Y14R02DD 16 XX 16 02DE 16 XX 16 X15 Register Y15 Register X15R,Y15R02DF 16 XX 16 02E0 16 XY Control Register XYC XXXX XX00 2 02E1 16 02E2 16 02E3 16 02E4 16 UART1 Special Mode Register 4 U1SMR4 00 16 02E5 16 UART1 Special Mode Register 3 U1SMR3 00 16 02E6 16 UART1 Special Mode Register 2 U1SMR2 00 16 02E7 16 UART1 Special Mode Register U1SMR 00 16 02E8 16 UART1 Transmit/Receive Mode Register U1MR 00 16 02E9 16 UART1 Baud Rate Register U1BRG XX 16 02EA 16 XX 16 UART1 Transmit Buffer Register U1TB02EB 16 XX 16 02EC 16 UART1 Transmit/Receive Control Register 0 U1C0 0000 1000 2 02ED 16 UART1 Transmit/Receive Control Register 1 U1C1 0000 0010 2 02EE 16 XX 16 UART1 Receive Buffer Register U1RB02EF 16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 36 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 02F016 02F116 02F216 02F316 02F416 UART4 Special Mode Register 4 U4SMR4 00 16 02F516 UART4 Special Mode Register 3 U4SMR3 00 16 02F616 UART4 Special Mode Register 2 U4SMR2 00 16 02F716 UART4 Special Mode Register U4SMR 00 16 02F816 UART4 Transmit/Receive Mode Register U4MR 00 16 02F916 UART4 Baud Rate Register U4BRG XX 16 02FA 16 XX 16 UART4 Transmit Buffer Register U4TB02FB 16 XX 16 02FC 16 UART4 Transmit/Receive Control Register 0 U4C0 0000 1000 2 02FD 16 UART4 Transmit/Receive Control Register 1 U4C1 0000 0010 2 02FE 16 XX 16 UART4 Receive Buffer Register U4RB02FF 16 XX 16

030016 Timer B3, B4, B5 Count Start Flag TBSR 000X XXXX 2

030216 XX 16

Timer A1-1 Register TA11030316 XX 16

030416 XX 16

Timer A2-1 Register TA21030516 XX 16

030616 XX 16

Timer A4-1 Register TA41030716 XX 16

030816 Three-Phase PWM Control Register 0 INVC0 00 16

030916 Three-Phase PWM Control Register 1 INVC1 00 16

030A 16 Three-Phase output Buffer Register 0 IDB0 XX11 1111 2 030B 16 Three-Phase output Buffer Register 1 IDB1 XX11 1111 2 030C 16 Dead Time Timer DTT XX 16 030D 16 Timer B2 Interrupt Generating Frequency Set Counter ICTB2 XX 16 030E 16 030F16

031016 XX 16

Timer B3 Register TB3031116 XX 16

031216 XX 16

Timer B4 Register TB4031316 XX 16

031416 XX 16

Timer B5 Register TB5031516 XX 16 031616 031716 031816 031916 031A 16 031B 16 Timer B3 Mode Register TB3MR 00XX 0000 2 031C 16 Timer B4 Mode Register TB4MR 00XX 0000 2 031D 16 Timer B5 Mode Register TB5MR 00XX 0000 2 031E 16 031F16 External Interrupt Cause Select Register IFSR 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 37 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET 032016 032116 032216 032316

032416 UART3 Special Mode Register 4 U3SMR4 00 16

032516 UART3 Special Mode Register 3 U3SMR3 00 16

032616 UART3 Special Mode Register 2 U3SMR2 00 16

032716 UART3 Special Mode Register U3SMR 00 16

032816 UART3 Transmit/Receive Mode Register U3MR 00 16

032916 UART3 Baud Rate Register U3BRG XX 16

UART3 Transmit Buffer Register U3TB032B 16 XX 16 032C 16 UART3 Transmit/Receive Control Register 0 U3C0 0000 1000 2 032D 16 UART3 Transmit/Receive Control Register 1 U3C1 0000 0010 2 032E 16 XX 16 UART3 Receive Buffer Register U3RB032F16 XX 16 033016 033116 033216 033316

033416 UART2 Special Mode Register 4 U2SMR4 00 16

033516 UART2 Special Mode Register 3 U2SMR3 00 16

033616 UART2 Special Mode Register 2 U2SMR2 00 16

033716 UART2 Special Mode Register U2SMR 00 16

033816 UART2 Transmit/Receive Mode Register U2MR 00 16

033916 UART2 Baud Rate Register U2BRG XX 16

UART2 Transmit Buffer Register U2TB033B 16 XX 16 033C 16 UART2 Transmit/Receive Control Register 0 U2C0 0000 1000 2 033D 16 UART2 Transmit/Receive Control Register 1 U2C1 0000 0010 2 033E 16 XX 16 UART2 Receive Buffer Register U2RB033F16 XX 16

034016 Count Start Flag TABSR 00 16

034116 Clock Prescaler Reset Flag CPSRF 0XXX XXXX 2

034216 One-Shot Start Flag ONSF 00 16

034316 Trigger Select Register TRGSR 00 16

034416 Up-Down Flag UDF 00 16

034616 XX 16

Timer A0 Register TA0034716 XX 16

034816 XX 16

Timer A1 Register TA1034916 XX 16 034A 16 XX 16 Timer A2 Register TA2034B 16 XX 16 034C 16 XX 16 Timer A3 Register TA3034D 16 XX 16 034E 16 XX 16 Timer A4 Register TA4034F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 38 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET

035016 XX 16

Timer B0 Register TB0035116 XX 16

035216 XX 16

Timer B1 Register TB1035316 XX 16

035416 XX 16

Timer B2 Register TB2035516 XX 16

035616 Timer A0 Mode Register TA0MR 0000 0X00 2

035716 Timer A1 Mode Register TA1MR 0000 0X00 2

035816 Timer A2 Mode Register TA2MR 0000 0X00 2

035916 Timer A3 Mode Register TA3MR 0000 0X00 2

035A 16 Timer A4 Mode Register TA4MR 0000 0X00 2 035B 16 Timer B0 Mode Register TB0MR 00XX 0000 2 035C 16 Timer B1 Mode register TB1MR 00XX 0000 2 035D 16 Timer B2 Mode Register TB2MR 00XX 0000 2 035E 16 Timer B2 Special Mode Register TB2SC XXXX XXX0 2 035F16 Count Source Prescaler Register(1) TCSPR 0XXX 0000 2 036016 036116 036216 036316

036416 UART0 Special Mode Register 4 U0SMR4 00 16

036516 UART0 Special Mode Register 3 U0SMR3 00 16

036616 UART0 Special Mode Register 2 U0SMR2 00 16

036716 UART0 Special Mode Register U0SMR 00 16

036816 UART0 Transmit/Receive Mode Register U0MR 00 16

036916 UART0 Baud Rate Register U0BRG XX 16

UART0 Transmit Buffer Register U0TB036B 16 XX 16 036C 16 UART0 Transmit/Receive Control Register 0 U0C0 0000 1000 2 036D 16 UART0 Transmit/Receive Control Register 1 U0C1 0000 0010 2 036E 16 XX 16 UART0 Receive Buffer Register U0RB036F16 XX 16 037016 037116 037216 037316 037416 037516

037616 PLL Control Register 0 PLC0 0011 X100 2

037716 PLL Control Register 1 PLC1 XXXX 0000 2

037816 DMA0 Cause Select Register DM0SL 0X00 0000 2

037916 DMA1 Cause Select Register DM1SL 0X00 0000 2

037A 16 DMA2 Cause Select Register DM2SL 0X00 0000 2 037B 16 DMA3 Cause Select Register DM3SL 0X00 0000 2 037C 16 XX 16 CRC Data Register CRCD037D 16 XX 16 037E 16 CRC Input Register CRCIN XX 16 037F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The TCSPR register maintains the values set before reset even if software reset or watchdog timer reset is performed.

Page 39 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M Address Register Symbol Value after RESET

038016 XX 16

A/D0 Register 0 AD00038116 XX 16

038216 XX 16

A/D0 Register 1 AD01038316 XX 16

038416 XX 16

A/D0 Register 2 AD02038516 XX 16

038616 XX 16

A/D0 Register 3 AD03038716 XX 16

038816 XX 16

A/D0 Register 4 AD04038916 XX 16 038A 16 XX 16 A/D0 Register 5 AD05038B 16 XX 16 038C 16 XX 16 A/D0 Register 6 AD06038D 16 XX 16 038E 16 XX 16 A/D0 Register 7 AD07038F16 XX 16 039016 039116 039216 039316

039416 A/D0 Control Register 2 AD0CON2 X000 0000 2

039616 A/D0 Control Register 0 AD0CON0 00 16

039716 A/D0 Control Register 1 AD0CON1 00 16

039816 D/A Register 0 DA0 XX 16

039A 16 D/A Register 1 DA1 XX 16 039B 16 039C 16 D/A Control Register DACON XXXX XX00 2 039D 16 039E 16 039F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 40 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M <144-pin package> Address Register Symbol Value after RESET 03A0 16 Function Select Register A8 PS8 X000 0000 2 03A1 16 Function Select Register A9 PS9 00 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 Function Select Register C PSC 00X0 0000 2 03B0 16 Function Select Register A0 PS0 00 16 03B1 16 Function Select Register A1 PS1 00 16 03B2 16 Function Select Register B0 PSL0 00 16 03B3 16 Function Select Register B1 PSL1 00 16 03B4 16 Function Select Register A2 PS2 00X0 0000 2 03B5 16 Function Select Register A3 PS3 00 16 03B6 16 Function Select Register B2 PSL2 00X0 0000 2 03B7 16 Function Select Register B3 PSL3 00 16 03B8 16 03B9 16 Function Select Register A5 PS5 XXX0 0000 2 03BA 16 03BB 16 03BC 16 Function Select Register A6 PS6 00 16 03BD 16 Function Select Register A7 PS7 00 16 03BE 16 03BF 16 03C0 16 Port P6 Register P6 XX 16 03C1 16 Port P7 Register P7 XX 16 03C2 16 Port P6 Direction Register PD6 00 16 03C3 16 Port P7 Direction Register PD7 00 16 03C4 16 Port P8 Register P8 XX 16 03C5 16 Port P9 Register P9 XX 16 03C6 16 Port P8 Direction Register PD8 00X0 0000 2 03C7 16 Port P9 Direction Register PD9 00 16 03C8 16 Port P10 Register P10 XX 16 03C9 16 Port P11 Register P11 XX 16 03CA 16 Port P10 Direction Register PD10 00 16 03CB 16 Port P11 Direction Register PD11 XXX0 0000 2 03CC 16 Port P12 Register P12 XX 16 03CD 16 Port P13 Register P13 XX 16 03CE 16 Port P12 Direction Register PD12 00 16 03CF 16 Port P13 Direction Register PD13 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 41 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M <144-pin package> Address Register Symbol Value after RESET 03D0 16 Port P14 Register P14 XX 16 03D1 16 Port P15 Register P15 XX 16 03D2 16 Port P14 Direction Register PD14 X000 0000 2 03D3 16 Port P15 Direction Register PD15 00 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-Up Control Register 2 PUR2 00 16 03DB 16 Pull-Up Control Register 3 PUR3 00 16 03DC 16 Pull-Up Control Register 4 PUR4 XXXX 0000 2 03DD 16 03DE 16 03DF 16 03E0 16 Port P0 Register P0 XX 16 03E1 16 Port P1 Register P1 XX 16 03E2 16 Port P0 Direction Register PD0 00 16 03E3 16 Port P1 Direction Register PD1 00 16 03E4 16 Port P2 Register P2 XX 16 03E5 16 Port P3 Register P3 XX 16 03E6 16 Port P2 Direction Register PD2 00 16 03E7 16 Port P3 Direction Register PD3 00 16 03E8 16 Port P4 Register P4 XX 16 03E9 16 Port P5 Register P5 XX 16 03EA 16 Port P4 Direction Register PD4 00 16 03EB 16 Port P5 Direction Register PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-Up Control Register 0 PUR0 00 16 03F116 Pull-Up Control Register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register PCR XXXX XXX0 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 42 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 <100-pin package> Address Register Symbol Value after RESET 03A0 16 03A1 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 Function Select Register C PSC 0X00 0000 2 03B0 16 Function Select Register A0 PS0 00 16 03B1 16 Function Select Register A1 PS1 00 16 03B2 16 Function Select Register B0 PSL0 00 16 03B3 16 Function Select Register B1 PSL1 00 16 03B4 16 Function Select Register A2 PS2 00X0 0000 2 03B5 16 Function Select Register A3 PS3 00 16 03B6 16 Function Select Register B2 PSL2 00X0 0000 2 03B7 16 Function Select Register B3 PSL3 00 16 03B8 16 03B9 16 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 03C0 16 Port P6 Register P6 XX 16 03C1 16 Port P7 Register P7 XX 16 03C2 16 Port P6 Direction Register PD6 00 16 03C3 16 Port P7 Direction Register PD7 00 16 03C4 16 Port P8 Register P8 XX 16 03C5 16 Port P9 Register P9 XX 16 03C6 16 Port P8 Direction Register PD8 00X0 0000 2 03C7 16 Port P9 Direction Register PD9 00 16 03C8 16 Port P10 Register P10 XX 16 03C9 16 03CA 16 Port P10 Direction Register PD10 00 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Set address spaces 03CB16, 03CE16 and 03CF16 to "FF16" in the 100-pin package. 2. Address spaces 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16 and 03CD16 are not provided in the 100-pin package. 123456 1 2345 6 123456 1234 1234 (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 1) (Note 1)

Page 43 884fo6002,13.naJ13.1.veR 1310-4300B90JER 4. Special Function Registers (SFR))T38/C23M,38/C23M(puorG38/C23M 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456 7 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 <100-pin package> Address Register Symbol Value after RESET 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-up Control Register 2 PUR2 00 16 03DB 16 Pull-up Control Register 3 PUR3 00 16 03DC 16 03DD 16 03DE 16 03DF 16 03E0 16 Port P0 Register P0 XX 16 03E1 16 Port P1 Register P1 XX 16 03E2 16 Port P0 Direction Register PD0 00 16 03E3 16 Port P1 Direction Register PD1 00 16 03E4 16 Port P2 Register P2 XX 16 03E5 16 Port P3 Register P3 XX 16 03E6 16 Port P2 Direction Register PD2 00 16 03E7 16 Port P3 Direction Register PD3 00 16 03E8 16 Port P4 Register P4 XX 16 03E9 16 Port P5 Register P5 XX 16 03EA 16 Port P4 Direction Register PD4 00 16 03EB 16 Port P5 Direction Register PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-Up Control Register 0 PUR0 00 16 03F116 Pull-Up Control Register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register PCR XXXX XXX0 2 X: Indeterminate 123456 1 2345 6 123456 1234 1234 12345 12345 Blank spaces are reserved. No access is allowed. NOTES: 1. Set address spaces 03D216 and 03D316 to "FF16" in the 100-pin package. 2. Set address spaces 03DC16 to "0016" in the 100-pin package. 3. Address spaces 03D016 and 03D116 are not provided in the 100-pin package. (Note 3) (Note 1) (Note 2)

Page 44 884fo6002,13.naJ13.1.veR 1310-4300B90JER 5. Reset)T38/C23M,38/C23M(puorG38/C23M RESET VCC 0.2VCC or below RESET VCC Recommended Operation Voltage The above applies to VCC = 5V Supply a clock with 20 or more cycles to the XIN pin 5. Reset Hardware reset, software reset, and watchdog timer reset are available to reset the microcomputer.

5.1 Hardware Reset

5.1.1 Reset on a Stable Supply Voltage

The microcomputer resets pins, the CPU and SFR when the supply voltage meets the recommended performance conditions while an "L" signal is applied to the RESET pin (see Table 5.1). Apply an "H" signal to the RESET pin again after 20 or more clock cycles are input to the XIN pin while applying an "L" to the RESET pin. The CPU and SFR are reset and programs run from the address indicated by the reset vector. The internal RAM is not reset. When the RESET pin becomes "L" while writing data to the internal RAM, the internal RAM is in an indeterminate state.

5.1.2 Power-on Reset

The microcomputer resets pins, the CPU and SFR when the supply voltage applied to the VCC pin meets the recommended performance conditions while an "L" signal is applied to the RESET pin. (See Table 5.1.) The CPU and SFR are reset when the signal applied to the RESET pin changes low ("L") to high ("H") after the main clock oscillation stabilizes and 20 or more clock cycles are applied to the XIN pin. Programs run from the address indicated by the reset vector. The internal RAM is in a indeterminate state tions after reset. Table 5.1 lists pin states while the RESET pin is held "L". Refer to 4. SFR for SFR states after reset. Figure 5.1 Reset Circuit

Page 45 884fo6002,13.naJ13.1.veR 1310-4300B90JER 5. Reset)T38/C23M,38/C23M(puorG38/C23M BCLK XIN RESET RD WR CS0 RD WR CS0 Address Address Address(1) Microprocessor mode BYTE = “H ” Microprocessor mode BYTE = “L” Content of reset vectorSingle-chip mode 40 to 45 BCLK cycles FFFFFC16 FFFFFE 16 Content of reset vector FFFFFE 16 Content of reset vector FFFFFE 16 FFFFFC 16 20 or more XIN cycles required FFFFFC 16 FFFFFD16 NOTES: 1. Addresses cannot be output from pins, in single-chip mode. 2. M32C/83T cannot be used in memory expansion mode and microprocessor mode. (2) (2) Figure 5.2 Reset Sequence

Page 46 884fo6002,13.naJ13.1.veR 1310-4300B90JER 5. Reset)T38/C23M,38/C23M(puorG38/C23M Pin States CNV SS = VCC CNV SS = VSS BYTE = VSS BYTE = VCC Pin Name P2, P3, P4 P50 P51 P52 P53 P54 P55 P56 P57 Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Data input (high-impedance) Data input (high-impedance) Address output (indeterminate) BCLK output RAS output WR output (output "H") RD output (output "H") RDY input (high-impedance) Input port (high-impedance) BHE output (indeterminate) HLDA output (output value depends on an input to HOLD pin) HOLD input (high-impedance) Input port (high-impedance) NOTES: 1. Ports P11 to P15 are provided in the 144-pin package. P6 to P15 (1) Table 5.1 Pin States while RESET Pin is Held "L"

5.2 Software Reset

When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), pins, the CPU and SFR are reset. Then the microcomputer executes the program from an address determined by the reset vector. When software reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for details. Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is stable.

5.3 Watchdog Timer Reset

The microcomputer resets pins, the CPU and the SFR when the watchdog timer underflows while the CM06 bit in the CM0 register is set to "1" (reset). Then the microcomputer executes the program from an address indicated by the reset vector. When watchdog timer reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for details. Because the PM01 to PM00 bits in the PM0 register are not reset, the processor mode remains unchanged.

Page 47 884fo6002,13.naJ13.1.veR 1310-4300B90JER 5. Reset)T38/C23M,38/C23M(puorG38/C23M b15 b0 b23 0016 000016 000016 00000016 00000016 00000016 00000016 00000016 00000016 00000016 Contents of addresses FFFFFE 16 to FFFFFC16 Data Register (R0H/R0L) Address Register (A0) Static Base Register (SB) Frame Base Register (FB) User Stack Pointer (USP) Interrupt Stack Pointer (ISP) Interrupt Table Register (INTB) Program Counter (PC) General Register b15 b0

000016 Flag Register (FLG)

X 0 0 0 X X X X 0 0 0 0 0 0 0 0 0016 0016 0016 Data Register (R2) Data Register (R3) Address Register (A1) Data Register (R1H/R1L) High-Speed Interrupt Register b15 b0 b23 XXXX 16 XXXXXX 16 XXXXXX 16 DMAC-Associated Register b7 b0 b23 0016 b15 Save Flag Register (SVF) Save PC Register (SVP) Vector Register (VCT) DMA Mode Register (DMD0) DMA Transfer Count Register (DCT0) DMA Transfer Count Reload Register (DRC0) DMA Memory Address Register (DMA0) DMA SFR Address Register (DSA0) DMA Memory Address Reload Register (DRA0) DMA Mode Register (DMD1) DMA Transfer Count Register (DCT1) DMA Transfer Count Reload Register (DRC1) DMA Memory Address Register (DMA1) DMA SFR Address Register (DSA1) DMA Memory Address Reload Register (DRA1) XXXX 16 XXXX 16 XXXX 16 XXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 0 : "0" after reset X : Indeterminate after reset

5.4 Internal Space

Figure 5.3 shows CPU register states after reset. Refer to 4. SFR for SFR states after reset. Figure 5.3 CPU Register after Reset

Page 48 884fo6002,13.naJ13.1.veR 1310-4300B90JER 6. Processor Mode)T38/C23M,38/C23M(puorG38/C23M 6. Processor Mode NOTE M32C/83T can be used in single-chip mode. M32C/83T cannot be used in memory expansion mode and microprocessor mode.

6.1 Types of Processor Mode

Single-chip mode, memory expansion mode, or microprocessor mode can be selected as processor mode. Pin functions, memory map and accessible space vary depending on the selected processor mode.

6.1.1 Single-chip Mode

In single-chip mode, internal memory space (the SFR, internal RAM and internal ROM) can be accessed. All I/O ports can be used.

6.1.2 Memory Expansion Mode

In memory expansion mode, both external memory space and internal memory space can be accessed . Some pins function as pins for bus control signals. The BYTE pin and register settings determine how many pins are assigned for these pin functions. Refer to 7. Bus for details.

6.1.3 Microprocessor Mode

In microprocessor mode, SFR, internal RAM and external memory space can be accessed. Internal ROM cannot be accessed. Some pins function as pins for bus control signals. The BYTE pin and register settings determine how many pins are assigned for these pin functions. (Refer to 7. Bus for details.)

6.2 Setting Processor Mode

The processor mode is set by the combination of CNVSS pin and the PM01 to PM00 bit settings in the PM0 register. Do not set the PM01 to PM00 bits to "102". If the PM01 to PM00 bits are rewritten, the mode corresponding to the PM01 to PM00 bits is selected regardless of CNV SS pin level. Do not change the PM01 to PM00 bits when the PM02 to PM07 bits in the PM0 register are being rewritten. Do not enter microprocessor mode while the CPU is executing a program in the internal ROM . Do not enter single-chip mode while the CPU is executing a program in an external memory space. Figures 6.1 and 6.2 show the PM0 register and PM1 register. Figure 6.3 shows a memory map in each processor mode.

6.2.1 Applying VSS to CNVSS Pin

The microcomputer enters single-chip mode after reset. Set the PM01 to PM00 bits to "012" (memory expansion mode) to switch to memory expansion mode after the microcomputer starts operating.

6.2.2 Applying VCC to CNVSS Pin

The microcomputer enters microprocessor mode after reset. When using the flash memory version, apply V CC to P55 (HOLD) as well as to the CNVSS .

Page 49 884fo6002,13.naJ13.1.veR 1310-4300B90JER 6. Processor Mode)T38/C23M,38/C23M(puorG38/C23M Figure 6.1 PM0 Register NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. Processor mode is not changed even if the PM03 bit is set to "1" (software reset). 3. Set the PM01 to PM00 bits to "01 2" or "112" separately. Rewrite other bits before rewriting the PM01 to PM00 bits. 4. When using the 16-bit data bus in the DRAMC, set the PM02 bit to "1". 5. The PM05 to PM04 bits are available in memory expansion mode or microprocessor mode.

Set the PM05 to PM04 bits to "00 2" in mode 0.
Do not set the PM05 to PM04 bits to "012" in mode 2. 6. The PM05 to PM04 bits cannot be set to "112" in microprocessor mode because the microcomputer starts operation using the separate bus after reset. When the PM05 to PM04 bits are set to "112" in memory expansion mode, the microcomputer can access each 64-Kbyte chip-select-assigned address space. The multiplexed bus is not available in mode 0. The microcomputer accesses CS0 to CS2 in mode 1, CS0 and CS1 in mode 2 and CS0 to CS3 in mode 3. 7. No BCLK is output in single-chip mode even if the PM07 bit is set to "0". When a clock output is terminated in microprocessor mode or memory expansion mode, set the PM07 bit to "1" and the CM01 to CM00 bits in the CM0 register to "00 2" (I/O port P53). P53 outputs "L" . 8. When the PM07 bit is set to "0" (BCLK output), set the CM01 and CM00 bits to "002". 9. M32C/83T cannot be used in memory expansion mode and microprocessor mode. Symbol Address After Reset PM0 0004 16 1000 0000 2 (CNVss = "L") 0000 0011 2 (CNVss = "H") RW RW RW RW RW RW RW RW RW b1 b0 b5 b4 0: RD / BHE / WR 1: RD / WRH / WRL PM00 PM01 PM02 PM03 Software Reset Bit R/W Mode Select Bit(4) PM04 PM05 (b6) 0 0: Single-chip mode 0 1: Memory expansion mode(9) 1 0: Do not set to this value 1 1: Microprocessor mode (9) Set to "0" PM07 BCLK Output Disable Bit(7) Reserved Bit 0 : BCLK is output(8) 1 : BCLK is not output The CM01 and CM00 bits in the CM0 register determine pin functions. The microcomputer is reset when this bit is set to "1". When read, its content is "0". Bit Name FunctionBit Symbol Processor Mode Bit(2, 3) Multiplexed Bus Space Select Bit(5) 0 0 : Multiplexed bus is not used 0 1 : Access the CS2 area with the bus 0 1 : Access the CS1 area with the bus 1 1 : Access all CS areas with the bus(6) b7 b6 b5 b4 b3 b2 b1 b0 Processor Mode Register 0(1)

Page 50 884fo6002,13.naJ13.1.veR 1310-4300B90JER 6. Processor Mode)T38/C23M,38/C23M(puorG38/C23M Figure 6.2 PM1 Register Processor Mode Register 1(1) After Reset 0X00 00002 Address 0005 Symbol PM1 RW RW RW RW RW RW RW RW PM10 PM11 PM12 External Memory Space Mode Bit(2, 6) PM13 Internal Memory Wait Bit0 : No wait state 1 : Wait state SFR Area Wait Bit 0 Reserved Bit Set to "0" 0 : 1 wait state 1 : 2 wait states(4) PM14 PM15 (b6) (b7) ALE Pin Select Bit(2, 6) 0 0 : No ALE 0 1 : P53/BCLK(5) 1 0 : P56/RAS 1 1 : P54/HLDA Nothing is assigned. When read, its content is indeterminate. 0 0 : Mode 0 (A20 to A23 for P44 to P47) 0 1 : Mode 1 (A20 for P44, CS2 to CS0 for P45 to P47) 1 0 : Mode 2 (A20, A21 for P44, P45, CS1, CS0 for P46, P47) 1 1 : Mode 3(3) (CS3 to CS0 for P44 to P47) b1 b0 b5 b4 Bit Name FunctionBit Symbol NOTES: 1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. The PM10 and PM11 bits are available in memory expansion mode or microprocessor mode. 3. The DRAMC is not available when the PM11 and PM10 bits are set to "11 2" (mode 3). 4. Set the PM13 bit to "1" (2 wait states) to access CAN-associated registers (addresses 01E016 to 024516). 5. Set the CM01 and CM00 bits in the CM0 register to "002" (I/O port P53) when the PM15 and PM14 bits are set to "012" (P53/BCLK select). 6. M32C/83T cannot be used in memory expansion mode and microprocessor mode. b7 b6 b5 b4 b3 b2 b1 b0

Page 51 884fo6002,13.naJ13.1.veR 1310-4300B90JER 6. Processor Mode)T38/C23M,38/C23M(puorG38/C23M Figure 6.3 Memory Map in Each Processor Mode Single-Chip Mode Memory Expansion Mode Microprocessor Mode SFR Internal RAM Reserved Space Internal ROM Not Used External Space 0 CS2 2M bytes External Space 1 CS0 2M bytes External Space 3 Not Used Internal ROMReserved Space Internal ROMReserved Space Internal ROMReserved Space CS0 3M bytes External Space 3 CS1 4M bytes External Space 0 External Space 3 Not Used CS0 2M bytes External Space 3 CS0 4M bytes External Space 3 000000 000400 000800 200000 400000 C00000 E00000 F00000 FFFFFF Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Mode 3 Reserved Space SFR Internal RAM Internal ROMReserved SpaceCS1, 1M byte External Space 0 Mode 3 Reserved Space SFR Internal RAM Not Used CS2, 1M byteExternal Space 1 Not Used DRAM- Connectable Space 0, 0.5 to 8M byte(Available as external space when DRAM is not used) DRAM- Connectable Space 0, 0.5 to 8M bytes (Remaining space cannot be used if empty space is less than 8M bytes) DRAM- Connectable Space 0, 0.5 to 8M bytes(Remaining space cannot be used if empty space is less than 8M bytes) DRAM- Connectable Space 0, 0.5 to 8M bytes(Remaining space cannot be used if empty space is less than 8M bytes) Not Used (Cannot be used as DRAM-connectable space or external space) DRAM- Connectable Space 0, 0.5 to 8M bytes( Available as external space when DRAM is not used) DRAM- Connectable Space 0, 0.5 to 8M bytes(Remaining space cannot be used if empty space is less than 8M bytes) Not Used (Cannot be used as DRAM-connectable space or external space)Not Used Not Used CS1 2M bytes External Space 0 Not Used NOTES: 1. 200000 –008000 =2016K bytes. 32K bytes less than 2M bytes. 2. 400000 –008000 =4064K bytes. 32K bytes less than 4M bytes. External Space 1 External Space 0 CS2 2M bytes External Space 1 CS1 4M bytes External Space 0 CS1, 1M byteExternal Space 0 CS2, 1M byteExternal Space 1 CS1 2M bytes External Space 0 External Space 1 (External Space 2) (External Space 2) (External Space 2) (External Space 2) (External Space 2) (External Space 2)External Space 3 CS3, 1M byteExternal Space 2 CS0, 1M byteExternal Space 3 CS3, 1M byte External Space 2 CS0, 1M byteExternal Space 3 (1) (2) (1) (2) 100000 The WCR register determines how many wait states are inserted for each space CS0 to CS3. Not Used 300000 E00000

Page 52 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M 7. Bus In memory expansion mode or microprocessor mode, some pins function as bus control pins to input and output data from external devices. A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE, HLDA/ALE, HOLD, ALE/RAS, and RDY are used as bus control pins. Bus control pins in M32C/83T cannot be used. Figure 7.1 DS Register NOTES: 1. After reset, the DS3 bit is set to "1" when the BYTE pin is held "L". It is set to "0" when the BYTE pin is held "H". 2. The DS register in the M32C/83T cannot be used. Symbol Address After Reset DS 000B 16 XXXX 1000 2 (BYTE pin = "L") XXXX 0000 2 (BYTE pin = "H") External Data Bus Width Control Register(2) RW RW RW RW RW DS0 DS1 DS2 DS3 (b7 - b4) 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. External Space 0 Data Bus Width Select Bit External Space 1 Data Bus Width Select Bit External Space 2 Data Bus Width Select Bit External Space 3 Data Bus Width Select Bit(1) b7 b6 b5 b4 b3 b2 b1 b0

7.1 Bus Settings

The BYTE pin, the DS register, the PM05 to PM04 bits in the PM0 register and the PM11 to PM10 bits in the PM1 register determine bus settings. Table 7.1 lists how to change a bus setting. Figure 7.1 shows the DS register. Table 7.1 Bus Settings Bus Setting Changed By Selecting external address bus width DS register Setting bus width after reset BYTE pin (external space 3 only) Switching between separate bus or multiplexed bus PM05 to PM04 bits in PM0 register Number of chip-select PM11 to PM10 bits in PM1 register NOTE

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7.1.1 Selecting External Address Bus

The number of externally-output address bus, chip-select signals and chip-select-assigned address space (CS area) varies depending on each external space mode. The PM11 to PM10 bits in the PM1 register determine the external space mode. When using the DRAMC, row addresses and column addresses are multiplexed to output in the DRAM area.

7.1.2 Selecting External Data Bus

The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the external space 3, after reset, becomes 16 bits wide when an "L" signal is applied to the BYTE pin and 8 bits wide when an "H" signal is applied. Do not change the BYTE pin level while the microcomputer is operating. The internal bus is always 16 bits wide.

7.1.3 Selecting Separate/Multiplexed Bus

The PM05 to PM04 bits in the PM0 register determine either a separate or multiplexed bus as bus format .

7.1.3.1 Separate Bus

The separate bus is a bus format which allows the microcomputer to input and output data and ad- dress using separate buses. The DS register selects 8-bit or 16-bit data bus as the external data bus per external space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P becomes the data bus and port P1 becomes the programmable I/O port. If one of the DSi bits is set to "1" (16-bit data bus), ports P0 and P1 become the data bus. When the microcomputer accesses a space while the DSi bit set to "0", port P1 is indeterminate. If the microcomputer accesses a space with the separate bus, the WCR register determines the num- ber of software wait states inserted.

7.1.3.2 Multiplexed Bus

The multiplexed bus is a bus format which allows the microcomputer to input and output data and address via bus by timesharing. D 0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit data bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. If the microcomputer accesses a space with the multiplexed bus, the WCR register can be set to either two wait states or three wait states. Two-wait-state access is automatically selected if the WCR register is set to no wait state or one wait state. Refer to 7.2.4 Bus Timing for details. The microcomputer starts operation using the separate bus after reset. Therefore, the multiplexed bus can be assigned to access the CS1 area, the CS2 area, or all CS areas. However, the multiplexed bus cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits in the PM0 register are set to "112" (access all CS areas with the bus), only 16 low-order bits, from A0 to A15, of an address are output. See Table 7.2 for details.

Page 54 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M Table 7.2 Processor Mode and Port Function Access all CS Areas using the Separate Bus Single- Chip Mode Memory Expansion Mode/ Microprocessor Mode Memory Expansion Mode Data Bus Width Access all external space with 8-bit data bus NOTES: 1. The PM05 to PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in microprocessor mode because the microcomputer starts operation using the separate bus after reset. When the PM05 to PM04 bits are set to "11 2" in memory expansion mode, the microcomputer accesses 64K-byte memory space per chip select using the address bus . 2. These ports become address buses when accessing space using the separate bus. 3. The PM15 to PM14 bits in the PM1 register determine which pin outputs the ALE signal. The PM02 bit in the PM0 register selects either "WRL,WRH" or "BHE,WR" combination. P5 6 provides an indeterminate output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port. 4. When DRAMC is selected to access DRAM area, CASL, CASH, DW, BCLK become output pins. 5. The PM11 to PM10 bits in the PM1 register determine the CS signal and address bus. PM05 to PM04 Bits in PM0 Register CS (Chip-select signal) or Address bus (A23) (Refer to 7.2 Bus Control for details)(4) Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK (Refer to 7.2 Bus Control for details)(3) P00 to P07 P10 to P17 Data bus D 0 to D 7 I/O port I/O port I/O port I/O port P20 to P27 I/O port I/O port I/O port I/O port I/O port P30 to P37 I/O port Address bus/ Data bus(2) A8/D8 to A15/D15 P40 to P43 I/O port I/O port I/O port P44 to P46 I/O port P47 I/O port P50 to P53 I/O port P54 I/O port P55 I/O port P56 I/O port P57 I/O port HOLD HOLD HOLD HOLD HOLD HOLD RAS (3) RDY RDY RDY RDY RDY RDY Access CS1 or CS2 using the Multiplexed Bus Access All Other CS Areas using the Separate Bus Data bus D 0 to D 7 Data bus D 0 to D 7 Data bus D 0 to D 7 Address bus/ Data bus (2) A0/D0 to A7/D7 Address bus A0 to A7 Address bus A0 to A7 Address bus/ Data bus A0/D0 to A7/D7 Address bus/ Data bus A 0/D0 to A7/D7 Address bus A8 to A15 Address bus A8 to A15 Address bus A8 to A15 Address bus A8 to A15 Address bus A16 to A19 Address bus A16 to A19 Address bus A16 to A19 Address bus A16 to A19 Data bus D 8 to D 15 Data bus D 8 to D 15 Address bus/ Data bus A8/D8 to A15/D15 Access all CS Areas using the Multiplexed Bus Access one or more external space with 16-bit data bus Access all external space with 8-bit data bus Access one or more external space with 16-bit data bus Access all external space with 8-bit data bus Access one or more external space with 16-bit data bus CS (Chip-select signal) or Address bus (A20 to A22) (Refer to 7.2 Bus Control for details)(4) HLDA (3) HLDA (3) HLDA (3) HLDA (3) HLDA (3) HLDA (3) RAS (3) RAS (3) RAS (3) RAS (3) RAS (3) Processor Mode Address bus/ Data bus(2) A0/D0 to A7/D7

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7.2 Bus Control

Signals required to access external devices are provided and software wait states are inserted as follows. The signals are available in memory expansion mode and microprocessor mode only.

7.2.1 Address Bus and Data Bus

The address bus is a signal accessing 16M-byte space and uses 24 control pins; A0 to A22 and A23. A23 is the inversed output signal of the highest-order address bit. The data bus is a signal which inputs and outputs data. The DS register selects the 8-bit data bus from D to D7 or the 16-bit data bus from D0 to D15 for each external space. When applying an "H" signal to the BYTE pin, the data bus accessing the external memory space 3 becomes the 8-bit data bus after reset. When applying an "L" signal to the BYTE pin, the data bus accessing the external memory space 3 becomes the 16-bit data bus. When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate state until the microcomputer accesses an external memory space. When using the DRAMC to access DRAM area, row addresses and column addresses are multiplexed and output via A 8 to A20.

7.2.2 Chip-Select Signal

The chip-select signal shares ports with A0 to A22 and A23. The PM11 to PM10 bits in the PM1 register determine which CS area is accessed and how many chip-select signals are output. A maximum of four chip-select signals can be output. In microprocessor mode, the chip-select signal is not output after reset. A23, however, can perform as the chip-signal signal. The chip-select signal becomes "L" while the microcomputer accesses the external CSi area (i=0 to 3). It becomes high ("H") when the microcomputer accesses another external memory space or an internal memory space. Figure 7.2 shows an example of the address bus and chip-select signal output.

Page 56 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M Figure 7.2 Address Bus and Chip-Select Signal Outputs (Separate bus) Example 1: When the microcomputer accesses the external space j specified by another chip-select signal in the next cycle after having accessed the external space i, both address bus and chip-select signal change. NOTES: 1. The above applies to the address bus and chip-select signal in two consecutive cycles. By combining these examples, a chip-select signal extended by two or more cycles may be output. Data Bus Address Bus Chip-Select Signal CSk Access External Space i Chip-Select Signal CSp Access External Space jAddress DataData Example 2: When the microcomputer accesses the SFR or the internal ROM/RAM area in the next cycle after having accessed an external space, the chip-select signal changes but the address bus does not. Example 3: When the microcomputer accesses the space i specified by the same chip-select signal in the next cycle after having accessed the external space i, the address bus changes but the chip-select signal does not. Data Bus Address Bus Chip-Select Signal CSk Data Address Data Bus Address Bus Chip-Select Signal CSk Data Address Access External Space No Access Access External Space i Access External Space i Data Bus Address Bus Chip-Select Signal CSk Data Address Example 4: When the microcomputer does not access any space in the next cycle after having accessed an external space (no pre-fetch of an instruction is generated), neither address bus nor chip-select signal changes. Data Access External Space Access SFR, Internal ROM/RAM Area i = 0 to 3 k = 0 to 3 j = 0 to 3, excluding i p= 0 to 3, excluding k (See Figure 6.3 for i, j and p, k) k = 0 to 3 i = 0 to 3 k = 0 to 3 (See Figure 6.3 for i and k) k = 0 to 3

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7.2.3 Read and Write Signals

When set to the 16-bit data bus, the PM02 bit in the PM0 register selects a combination of the RD, WR and BHE signals or the RD, WRL and WRH signals to determine the read or write signal. When the DS3 to DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). If any of the DS3 to DS0 bits are set to "1" (16-bit data bus) when accessing an 8-bit space, the combination of RD, WR and BHE is automatically selected regardless of the PM02 bit setting. Tables 7.3 and 7.4 list each signal operations. The RD, WR and BHE signals are combined for the read or write signal after reset. When changing the combination to RD, WRL and WRH, set the PM02 bit before writing data to an external memory. When using the DRAMC to access the DRAM with the 16-bit bus, set the PM02 bit to "1" (RD/ WRL/ WRH). Table 7.3 RD, WRL and WRH Signals Status of External Data BusRD WR HLL LHL HLH LHH Write 1-byte data to odd address Read 1-byte data from odd address Write 1-byte data to even address Read 1-byte data from even address Data Bus H H L L HLL L LHL L HL H / L LH H / L8 Bits Write data to both even and odd addresses Read data from both even and odd addresses Write 1-byte data Read 1-byte data

16 Bits

Status of External Data Bus Read data Write 1-byte data to even address Write 1-byte data to odd address Write data to both even and odd addresses WRHWRLRDData Bus

16 Bits H

H H H L H L H H L L L H H (1) L(1) L Not used Write 1-byte data Read 1-byte dataNot used8 Bits NOTES: 1. The WR signal is used instead of the WRL signal. Table 7.4 RD, WR and BHE Signals

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7.2.4 Bus Timing

Bus cycle for the internal ROM and internal RAM are basically one BCLK cycle. When the PM12 bit in the PM1 register is set to "1" (wait state), the bus cycles are two BCLK cycles. Bus cycles for the SFR are basically two BCLK cycles. When the PM13 bit in the PM1 register is set to "1" (2 wait states), the bus cycles are three BCLK cycles. To access CAN-associated registers (addresses 01E0 16 to 024516), set the PM13 bit to "1". Bus cycle for an external space is basically one BCLK cycle for a read operation and two BCLK cycles for a write operation. The WCR register inserts wait states equivalent to one to three BCLK cycles into an external space. Bus cycles are two BCLK cycles if selecting one wait state. Bus cycles are four BCLK cycles if selecting three wait states. If applicable to the followings, bus cycles vary from those selected by the WCR register. Figure 7.5 shows each bit status and bus cycle.

Write cycle with the separate bus and no wait state
Read cycle and write cycle with the multiplexed bus and no wait state.
Read cycle and write cycle with the multiplexed bus and one wait state. Figure 7.3 WCR Register NOTES: 1. When using the multiplexed bus, "2 waits" is selected even if the WCR register is set to "002" (no wait state) or "012" (1 wait state). "102" (2 wait states) and "112" (3 wait states) can be selected. 2. When using the separate bus, the read bus runs one BCLK cycle and the write bus runs two BCLK cycles (1 wait state) if the WCR register is set to "002". 3.The WCR register cannot be used in M32C/83T. Symbol Address After Reset WCR 0008 16 1111 1111 2 Wait Control Register(1, 2, 3) RW RW RW RW RW RW RW RW RW WCR0 WCR1 WCR2 WCR3 WCR4 WCR5 WCR6 WCR7 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states Bit Name FunctionBit Symbol External Space 0 Wait Bit External Space 1 Wait Bit External Space 2 Wait Bit External Space 3 Wait Bit b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 b3 b2 b5 b4 b7 b6

Page 59 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M Table 7.5 Software Wait State and Bus Cycle i = 0, 2, 4, 6 j = i + 1 Space External Bus Status PM13 Bit WCR Register Bus Cycle 1 2 BCLK cycles External Memory 002 Read :1 BCLK cycle Separate Bus Write : 2 BCLK cycles

2 BCLK cycles

3 BCLK cycles

4 BCLK cycles

3 BCLK cycle

PM12 Bit WCRj to WCRi Bits

Page 60 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M Figure 7.4 External Bus Operation with Software Wait State (1) Output Input Address Address Bus cycle(1)(2) Separate Bus with 1 Wait State BCLK Read Signal Write Signal Data Bus Address Bus(2) Chip-Select Signal(2, 3) BCLK Read Signal Data Bus Chip-Select Signal(2, 3) Data Output AddressAddress Bus(2) Address Input (3) Separate Bus with 2 Wait States Write Signal BCLK Read Signal Write Signal Address Bus(2) Address Bus cycle(1) (1) Separate Bus with No Wait State OutputData Bus Chip-Select Signal(2, 3) Input Bus cycle(1) Bus cycle(1) Bus cycle(1) Bus cycle(1) Address NOTES: 1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively. 2. The address bus and chip-select signal may be extended depending on CPU state such as an instruction queue buffer. 3. When the microcomputer continuously accesses the same external space (same CS area), the chip- select signal may be output continuously.

Page 61 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M Figure 7.5 External Bus Operation with Software Wait State (2) BCLK Read Signal Write Signal Address Bus/Data Bus(2) Chip-Select Signal(2, 3) Address AddressAddress Bus Data output Address Address Input ALE Bus cycle(1) (2) Multiplexed Bus with 2 Wait States Bus cycle(1) BCLK Read Signal Write Signal Chip-Select Signal(2, 3) Bus cycle(1) (1) Separate Bus with 3 Wait States AddressAddress Bus(2) Address Bus cycle(1) Data Bus Data output Input BCLK Read Signal Write Signal Address Bus/ Data Bus(2) Chip-Select Signal (2, 3) AddressAddress Bus Data output Address Input Bus cycle(1) (3) Multiplexed Bus with 3 Wait States Address Address ALE Bus cycle(1) NOTES: 1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively. 2. The address bus and chip-select signal may be extended depending on CPU state such as an instruction queue buffer. 3. When the microcomputer continuously accesses the same external space (same CS area), the chip- select signal may be output continuously.

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7.2.5 ALE Signal

The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the ALE signal. The PM15 to PM14 bits in the PM1 register determine the output pin for the ALE signal. The ALE signal is output to an internal space and external space. Figure 7.6 ALE Signal and Address/Data Bus

7.2.6 RDY Signal

The RDY signal facilitates access to external devices which need longer access time. When an "L" signal is applied to the RDY pin on the falling edge of last BCLK of the bus cycle, wait states are inserted into the bus cycle. When an "H" signal is applied to the RDY pin on the falling edge of the BCLK, the bus cycle starts running again. Table 7.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure 7.7 shows an example of the RD signal extended by the RDY signal. Table 7.6 Microcomputer States in a Wait State(1) Item State Oscillation On RD Signal, WR Signal, Address Bus, CSi (i=0 to 3), Maintains the same state as when RDY signal Data Bus, ALE Signal, HLDA, Programmable I/O Ports was received Internal Peripheral Circuits On NOTES: 1. The RDY signal cannot be accepted immediately before software wait states are inserted. (1) 8-Bit Data Bus (2) 16-Bit Data Bus ALE Address Data Address D 0/A0 to D7/A7 A8 to A15 ALE Address Data Address D 0/A0 to D15/A15 A16 to A19 NOTES: 1. D0/A0 to D7/A7 are placed in high-impedance state when read. 2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port. Address Address or CSAddress or CS A16 to A19 (1) (1) (2)(2) A20/CS3 A21/CS2 A22/CS1 A23/CS0 A20/CS3 A21/CS2 A22/CS1 A23/CS0

Page 63 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M Figure 7.7 RD Signal Output Extended by RDY Signal

7.2.7 HOLD Signal

The HOLD signal transfers bus privileges from the CPU to external circuits. When an "L" signal is applied to the HOLD pin , the microcomputer enters a hold state after bus access is completed. While the HOLD pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal. Table 7.7 shows the microcomputer status in a hold state. Bus is used in the following order of priority: HOLD, DMAC, CPU. /LiteDiagLines/LiteDiagLines (1) Separate Bus with 2 Wait States (2) Multiplexed Bus with 2 Wait States BCLK RD CS i (i=0 to 3) RDY /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines BCLK RD CS i (i=0 to 3) RDY tsu(RDY - BCLK) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 1st cycle 2nd cycle 3rd cycle 4th cycle tsu(RDY - BCLK) Timing to receive RDY tsu(RDY-BCLK) : Setup time for RDY input Timing to receive RDY for j wait(s): j+1 cycles (j = 1 to 3) 1st cycle 2nd cycle 3rd cycle 4th cycle : Wait states inserted by RDY : Wait states inserted by program (1) (1) NOTES: 1. The chip-select signal (CSi) may be extended depending on CPU state such as the instruction queue buffer. Timing to receive RDY Figure 7.8 Order of Bus Priority HOLD > DMAC > CPU

Page 64 884fo6002,13.naJ13.1.veR 1310-4300B90JER 7. Bus)T38/C23M,38/C23M(puorG38/C23M Table 7.7 Microcomputer Status in a Hold State Item Status Oscillation On RD Signal, WR Signal, Address Bus, Data Bus, BHE, High-impedance CS0 to CS3 Programmable I/O Ports: P0 to P15 Maintains the same state as when HOLD signal is received HLDA Output "L" Internal Peripheral Circuits On (excluding the watchdog timer) ALE Signal Output "L"

7.2.8 External Bus State when Accessing Internal Space

Table 7.8 shows external bus states when an internal space is accessed. Table 7.8 External Bus State when Accessing Internal Space Item State when accessing SFR, internal ROM and internal RAM Address bus Holds an address of an external space accessed just before Data Bus When Read High-impedance When Write High-impedance RD, WR, WRL, WRH Output "H" BHE Holds state of external space last accessed CS0 to CS3 Output "H" ALE Output ALE

7.2.9 BCLK Output

The CPU clock operates the CPU. When combining the PM07 bit in the PM0 register set to "0" (BCLK output) and the CM01 to CM00 bits in the CM0 register set to "00 2", the CPU clock signal is output from P53 as BCLK. No BCLK is output in single-chip mode. Refer to 8. Clock Generating Circuit for details.

7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW)

The DRAM control signals control the DRAM. The DRAM control signals are output when the DRAM area, determined by the AR0 to AR2 bits in the DRAMCONT register, is output. Table 7.9 lists each signal operation. Table 7.9 RAS, CASL, CASH and DW Signals Data Bus StateRAS CASHCASL LLL LLH LL LLL Read data from both even and odd addresses Read 1-byte data from even address Read 1-byte data from odd address Write data to both even and odd addresses Data Bus Width DW H H H L LLHL LHL L LL H LL L8 bits Write 1-byte data to even address Write 1-byte data to odd address Read 1-byte data Write 1-byte data 16 bits Not used Not used H

Page 65 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M 8. Clock Generation Circuit

8.1 Types of Clock Generation Circuits

Four circuits are incorporated to generate the system clock signal :

Main clock oscillation circuit
Sub clock oscillation circuit
On-chip oscillator
PLL frequency synthesizer Table 8.1 lists specifications of the clock generation circuit. Figure 8.1 shows a block diagram of the clock generation circuit. Figures 8.2 to 8.8 show registers controlling the clock.
CPU clock source
Peripheral function clock source Use Main Clock Oscillation Circuit On-chip Oscillator PLL Frequency Synthesizer Sub Clock Oscillation CircuitItem
CPU clock source
Timer A and B clock source
CPU clock source
Peripheral function clock source
CPU clock source
Peripheral function clock source Clock Frequency Up to 32 MHz 32.768 kHz 20 MHz to 32 MHz ( See Table 8.2) Approximatly 1 MHz
Ceramic resonator
Crystal oscillator Connectable Oscillator or Additional Circuit
Crystal oscillator • Low pass filter XIN, XOUTPins for Oscillator or for Additional Circuit X CIN, XCOUT VCOUT (connect to low pass filter) P86 (connect to Vss) AvailableOscillation Stop/ Restart Function OscillatingOscillator State After Reset StoppedStopped Stopped External clock can be input Other The sub clock cannot be used when using the PLL frequency synthesizer External clock can be input. The PLL frequency synthesizer cannot be used when using the sub clock oscillation circuit. When the main clock stops oscillating, the on-chip oscillator starts oscillating automatically and becomes the clock source for the CPU and peripheral functions Available Available Available Table 8.1 Clock Generation Circuit Specifications

Page 66 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M CPU ClockBCLK CM07 CM21 cab e fC CM04 X CIN X COUT Sub Clock Oscillation Circuit S QR NMI RESET Output to determine an interrupt request levelSoftware Reset WAIT Instruction (wait mode) CM02 S QR CM10 = 1 (stop mode) NOTES: 1. The CNT3 to CNT0 bits in the TCSRR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. The MCD4 to MCD0 bits in the MCD register select divide-by-m (m=1,2,3,4,6,8,10,12,14,16 ). CST fAD f1 f32f8 1/2n 1/m f2n (1) CM0i : Bit in CM0 register CST : Bit in TCSPR registerCM1i : Bit in CM1 register CPSR : Bit in CPSRF register CM2i : Bit in CM2 register fC32 CM05 X IN X OUT Main Clock Oscillation Circuit On-chip Oscillator CM171 00 01 10 11 1 0 PLL FrequencySynthesizer (Note 2) Main Clock Peripheral Function Clock Sub Clock fC CLK OUT Port P5 f8 f32 CM01 to CM00 CPSR=1 DividerReset Figure 8.1 Clock Generation Circuit InterruptRequest Signal a On-chip Oscillator Clock On-chip Oscillator Charge and Discharge Circuit Circuit to Generate Oscillation Stop Detect Interrupt Request Clock Edge Detect /Charge and Discharge Circuit Control Watchdog Timer Interrupt Request CM21 SwitchSignal b On-chip Oscillator Reference Frequency Counter Phase Comparator ChargePump Programmable Counter Voltage Controlled Oscillator(VCO) 1/2 1/3 V CONT PLC07 PLC12 PLC11 PLL Clock c e PLC07 : Bit in PLC0 registerPLC11, PLC12 : Bits in PLC1 register PLL Frequency Synthesizer

Page 67 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Figure 8.2 CM0 Register Symbol Address After Reset CM0 0006 16 0000 X000 2 System Clock Control Register 0(1) CM00 CM01 CM02 (b3) Clock Output Function Select Bit(2) In Wait Mode, Peripheral Function Clock Stop Bit Port X C Switch Bit Main Clock (XIN-XOUT ) Stop Bit(5) CM04 CM05 CM06 CM07 RWFunctionBit NameBit Symbol RW RW RW RW RW RW RW RW 0 : Main clock oscillates 1 : Main clock stops(6) 0 0 : I/O port P53 0 1 : Outputs fC 1 0 : Outputs f8 1 1 : Outputs f32 0 : I/O port function 1 : XCIN-XCOUT oscillation function(4) Watchdog Timer Function Select Bit System C lock Select Bit(8) 0: Clock selected by the CM21 bit divided by MCD register setting 1: Sub clock 0 : Watchdog timer interrupt 1 : Reset(7) NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to "002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), set the CM01 to CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 to CM00 bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "002", an "L" signal is output from port P53 (port P53 does not function as an I/O port). 3. fc32 does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode. 4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), set the PD8_7 to PD8_6 bits to "002" (with port P87 and P86 input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up). 5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode, the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the CM05 bit is set to "1", X OUT becomes "H". The built-in feedback resistor remains on. XIN is pulled up to XOUT ("H" level) via the feedback resistor. 6. When the CM05 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). In on-chip oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates XIN-XOUT . 7. Once the CM06 bit is set to "1", it cannot be set "0" by program. 8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0". After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1". Do not set the CM07 bit and CM04 or CM05 bits simultaneously. b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 0 : Peripheral clock does not stop in wait mode 1 : Peripheral clock stops in wait mode (3) Reserved Bit Set to "1"

Page 68 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Figure 8.3 CM1 Register CM10 (b4 - b1) (b5) (b6) CM17 System Clock Control Register 1(1) Reserved Bit All Clock Stop Control Bit(2) Reserved Bit Reserved Bit CPU Clock Select Bit 2(4) Set to "0" Set to "0" Set to "1" 0 : Clock oscillates 1 : All clocks stop (stop mode)(3) 0 : Main clock 1 : PLL clock Symbol Address After Reset CM1 0007 16 0010 0000 2 FunctionBit NameBit Symbol RW RW RW RW RW RW NOTES: 1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the CM10 bit is set to "1", XOUT becomes "H" and the internal feedback resistance is disabled. X IN, XCIN and XCOUT are placed in high-impedance states. 3. When the CM10 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1". 4. CM17 bit is enabled only when the CM21 bit in the CM2 register is set to "0". Use the procedure shown in Figure 8.13 to set the CM17 bit to "1". b7 b6 b5 b4 b3 b2 b1 b0 00 00 01

Page 69 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Figure 8.4 MCD Register MCD0 MCD1 MCD2 MCD3 MCD4 (b7 - b5) Main Clock Division Register(1) Main Clock Division Select Bit(2, 4) 1 0 0 1 0 : Divide-by-1(no division) mode 0 0 0 1 0 : Divide-by-2 mode 0 0 0 1 1 : Divide-by-3 mode 0 0 1 0 0 : Divide-by-4 mode 0 0 1 1 0 : Divide-by-6 mode 0 1 0 0 0 : Divide-by-8 mode 0 1 0 1 0 : Divide-by-10 mode 0 1 1 0 0 : Divide-by-12 mode 0 1 1 1 0 : Divide-by-14 mode 0 0 0 0 0 : Divide-by-16 mode Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Symbol Address After Reset MCD 000C 16 XXX01000 2 FunctionBit NameBit Symbol RW RW RW RW RW RW NOTES: 1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. While the microcomputer is in stop mode or low-power consumption mode, the MCD register is set to "0816" (divide-by-8 mode). In on-chip oscillator mode, divide-by-8 mode cannot be entered even if the CM05 bit in the CM0 register is set to "1"(XIN-XOUT stopped). 3. Do not set to bit combinations not listed above. 4. Access CAN-associated register addresses (addresses 01E0 16 to 024516) after setting the MCD register to "1216" (no division mode). (Note 3) b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

Page 70 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Figure 8.5 CM2 Register CM20 CM21 CM22 CM23 (b7 - b4) Oscillation Stop Detect Register(1) CPU Clock Select Bit(2, 3) Oscillation Stop Detect Enable Bit XIN Clock Monitor Flag(5) Oscillation Stop Detect Flag(4) Reserved Bit 0: Main clock oscillates 1: Main clock stops 0: Clock selected by the CM17 bit 1: On-chip oscillator clock 0: Main clock does not stop 1: Detects main clock stop 0: Disables oscillation stop detect function 1: Enables oscillation stop detect function Set to "0" Symbol Address After Reset CM2 000D 16 00 16 FunctionBit NameBit Symbol RW RW RW RW RO RW NOTES: 1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the main clock oscillation stop is detected while the CM20 bit is set to "1" (oscillation stop detect function enabled), the CM21 bit is set to "1". Although the main clock starts oscillating, the CM21 bit is not set to "0". When the main clock is used as a CPU clock source after the main clock resumes oscillation, set the CM21 bit to "0" by program. 3. When the CM20 bit is set to "1" ( oscillation stop detect function enabled) and the CM22 bit is set to "1", do not set the CM21 bit to "0". 4. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0", not "1", by program. If the CM22 bit is set to "0" by program while the main clock is stopped, the CM22 bit cannot be set to "1" until the next main clock stop is detected. 5. Determine the main clock state by reading the CM23 bit several times after the oscillation stop interrupt is generated. b7 b6 b5 b4 b3 b2 b1 b0 000 0

Page 71 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Figure 8.6 TCSPR and CPSRF Registers CNT0 CNT1 CNT2 CNT3 (b6 - b4) CST NOTES: 1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "1". 2. Value of the TCSPR register is not reset by software reset or watchdog timer reset. Count Source Prescaler Register Division Rate Select Bit (1) Operation Enable Bit 0: Divider stops 1: Divider starts If setting value is n, f2n is divided the main clock, on-chip oscillator clock or PLL clock by 2n. When n is set to "0", no division is selected. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Symbol Address After Reset (2) TCSPR 035F 16 0XXX 0000 2 FunctionBit NameBit Symbol RW RW RW RW RW RW CPSR (b6 - b0) Clock Prescaler Reset Flag Clock Prescaler Reset Flag Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Symbol Address After Reset CPSRF 0341 16 0XXX XXXX 2 FunctionBit NameBit Symbol RW RWRW When the CPSR bit is set to "1", fC divided by 32 is reset. When read, its content is "0". b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

Page 72 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Figure 8.7 PLC0 and PLV Registers PLC00 PLC01 PLC02 (b3) (b4) (b5) (b6) PLC07 Function PLL Control Register 0(1) Programmable Counter Select Bit(2) Reserved Bit Operation Enable Bit(3, 4) See Table 8.2 0: PLL is Off 1: PLL is On Set to "0" Reserved Bit(2) Set to "0" Reserved Bit(2) Set to "1" Bit NameBit Symbol Symbol Address After Reset PLC0 0376 16 0011 X100 2 RW RW RW RW RW RW RW RW Reserved Bit Set to "0" NOTES: 1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. Set these bits when the PLC07 bit is set to "0". Once these bits are set, they cannot be changed. 3. To use the PLL function, the PD8_7 bit in the PD8 register is set to "0" (input) and the CM04 bit in the CM0 register is set to "0" (I/O port). Set the PD8_6 bit in the PD8 register to "0" (input) before connecting P8 6 to Vss. 4. Before the microcomputer enters wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), the PLC07 bit to "0" and PLV00 bit to "0" (cut off power to PLL) in this order. NOTES: 1. Rewrite the PLV register after the PRC3 bit in the PRCR register is set to "1" (write enable). 2. Before the microcomputer enters wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), the PLC07 bit to "0" (PLL off) and PLV00 bit to "0" (cut off power to PLL) in this order. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 00 1 PLV00 (b1) (b7 - b2) Function VDC Control Register for PLL(1) PLL VDC Enable Bit(2) 0 : Cut off power to PLL 1 : Power to PLL Bit NameBit Symbol Symbol Address After Reset PLV 0017 16 XXXX XX01 2 RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate.

Page 73 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M PLC11 (b0) (b3) (b7 - b4) PLC12 Function PLL Control Register 1(1, 2) PLL Clock Division Enable Bit(3) Reserved Bit 0 : Disables the PLL clock to be divided 1 : Enables the PLL clock to be divided 0 : Divide-by-2 1 : Divide-by-3 Set to "0" PLL Clock Division Switch Bit(4) Bit NameBit Symbol Symbol Address After Reset PLC1 0377 16 XXXX 0000 2 RW RW RW RW Reserved Bit Set to "0" RW NOTES: 1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. Rewrite the PLC1 register after the CM17 bit in the CM1 register is set to "0" (main clock) . 3. When the CM21 bit in the CM2 register is set to "0" (clock selected by the CM17 bit), if the PLC11 bit is set to "1" before the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock divided- by-2 or divided-by-3 becomes the clock source of the CPU clock and peripheral function clock. 4. Do not rewrite the PLC12 bit if the PLL clock is the CPU clock source. b7 b6 b5 b4 b3 b2 b1 b0 0 0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Figure 8.8 PLC1 Register

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8.1.1 Main Clock

Main clock oscillation circuit generates the main clock. The main clock becomes a clock source for the CPU clock and peripheral function clock. The main clock oscillation circuit is configured by connecting an oscillator or resonator between the X IN and XOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the oscillation circuit in stop mode to reduce power consumption. The externally generated clock can be input to the X IN pin in the main clock oscillation circuit. Figure 8.9 shows an example of a main clock circuit connection. Circuit constants vary with each oscillator. Use the circuit constant recommended by each oscillator manufacturer. The main clock divided-by-eight becomes the CPU clock after reset. To reduce power consumption, set the CM05 bit in the CM0 register to "1" (main clock stopped) after switching the CPU clock source to the sub clock or on-chip oscillator clock. In this case, X OUT becomes "H". XIN is pulled up by XOUT via the feedback resistor which remains on. When an externally generated clock is input to the XIN pin, the main clock does not stop even if the CM05 bit is set to "1". Terminate main clock operation externally if necessary. All clocks, including the main clock, stop in stop mode. Refer to 8.5 Power Consumption Control for details. Figure 8.9 Main Clock Circuit Connection External ClockXIN XOUT Open VCC VSS NOTE: 1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting. Use values recommended by each oscillator manufacturer. Place a feedback resistor between X IN and XOUT if the oscillator manufacturer recommends placing the resistor externally. Oscillator Rd (1) C IN C OUT XIN XOUT Microcomputer (Built-in Feedback Resistor) Microcomputer (Built-in Feedback Resistor) VSS

Page 75 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M

8.1.2 Sub Clock

Sub clock oscillation circuit generates the sub clock. The sub clock becomes a clock source for the CPU clock and a count source for the timers A and B. The same frequency, fc, as the sub clock can be output from the CLK OUT pin. The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and XCOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the oscillation circuit in stop mode to reduce power consumption. The externally generated clock can be applied to the X CIN pin. Figure 8.10 shows an example of a sub clock circuit connection. Circuit constants vary with each oscillator. Use the circuit constant recommended by each oscillation manufacturer. The sub clock stops after reset. The feedback resistor is separated from the oscillation circuit. When the PD8_6 and PD8_7 bits in the PD8 register are set to "0" (input mode) and the PU25 bit in the PUR2 register is set to "0" (no pull-up), set the CM04 bit in the CM0 register to "1" (X CIN-XCOUT oscillation function). The sub clock oscillation circuit starts oscillating. To apply the external clock to the XCIN pin, set the CM04 bit to "1" when the PD8_6 bit is set to "0" and the PU25 bit to "0". The clock applied to the XCIN pin becomes the clock source for the sub clock. When the CM07 bit in the CM0 register is set to "1" (sub clock) after the sub clock oscillation has stabi- lized, the sub clock becomes the CPU clock. All clocks, including the sub clock, stop in stop mode. Refer to 8.5 Power Consumption Control for details. X CIN shares pins with VCONT and XCOUT shares pins with P86. The sub clock and PLL frequency synthe- sizer cannot be used simultaneously. Figure 8.10 Sub Clock Connection Circuit External ClockXC IN XC OUT Open VCC VSS NOTE: 1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting. Use values recommended by each oscillator manufacturer. Place a feedback resistor between X CIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally. Oscillator R C d(1) C CIN C COUT XCIN XCOUT Microcomputer (Built-in Feedback Resistor) Microcomputer (Built-in Feedback Resistor) VSS

Page 76 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M

8.1.3 On-chip Oscillator Clock

On-chip oscillator generates the on-chip oscillator clock. The 1MHz on-chip oscillator clock becomes a clock source for the CPU clock and peripheral function clock. The on-chip oscillator clock stops after reset. When the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock), the on-chip oscillator starts oscillating. Instead of the main clock, the on-chip oscillator clock becomes the clock source for the CPU clock and peripheral function clock.

8.1.3.1 Oscillation Stop Detect Function

When the main clock is terminated by external factors, the on-chip oscillator automatically starts oscil- lating to generate another clock. When the CM 20 bit is set to "1" (oscillation stop detect function enabled), the oscillation stop detect interrupt request is generated as soon as the main clock stops. Simultaneously, the on-chip oscillator starts oscillating. The on-chip oscillator clock takes place of the main clock as the clock source for the CPU clock and peripheral function clock. Associated bits are set as follows:

CM21 bit = 1 (on-chip oscillator clock becomes the clock source of the CPU clock.)
CM22 bit = 1 (main clock stop is detected.)
CM23 bit = 1 (main clock stops) (See Figure 8.15)

8.1.3.2 How to Use Oscillation Stop Detect Function

The oscillation stop detect interrupt shares vectors with the watchdog timer interrupt. When both oscillation stop detect interrupt and watchdog timer interrupt are used, read the CM22 bit with an interrupt service routine to determine which interrupt request has been generated.
When the main clock resumes running after an oscillation stop is detected, set the main clock as the clock source for the CPU clock and peripheral function clock. Figure 8.11 shows the procedure to switch the on-chip oscillator clock to the main clock.
In low-speed mode, when the main clock is stopped by setting the CM20 bit to "1", the oscillation stop detect interrupt request is generated. Simultaneously, the on-chip oscillator starts oscillating. The sub clock remains the CPU clock. The on-chip oscillator clock becomes the clock source for the peripheral function clock.
To enter wait mode while the oscillation stop detect interrupt function is in use, set the CM02 bit to "0" (peripheral function clock does not stop in wait mode).
When the oscillation stop detect interrupt request is generated in wait mode, wait mode cannot be exited by the oscillation stop detect interrupt. After the microcomputer exits wait mode, the oscilla- tion stop detect interrupt is acknowledged first, followed by the interrupt used to exit wait mode.
The oscillation stop detect function is provided to handle main clock stop caused by external fac- tors. Set the CM20 bit to "0" (oscillation stop detect function disabled) when the main clock is terminated by program, i.e., entering stop mode or setting the CM05 bit is set to "1" (main clock oscillation stop).
When the main clock frequency is 2MHz or less, the oscillation stop detect function is not available. Set the CM20 bit to "0".

Page 77 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock

8.1.4 PLL Clock

The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be used as a clock source for the CPU clock or peripheral function clock. Connect a resistor and capacitor to the V CONT pin when using the PLL frequency synthesizer. Set the PD8_6 and PD8_7 bits in the PD8 register to "0" (input mode) and the CM04 bit to "0" (the XCIN and XCOUT pins as ports). After that, connect the VCONT pin, the P86 pin, and the VSS pin to the circuit as is shown in Figure 8.12. Set the PLV00 bit in the PLV register to "1" (power to PLL). The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL frequency synthesizer starts operating. Wait 20 ms (5 V operation) to 50 ms (3.3 V operation) for the PLL clock to stabilize. The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function clock, set each bit as is shown in Table 8.2. Figure 8.13 shows the procedure for using the PLL clock as the CPU clock source. To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source). Set the PLC07 bit in the PLC0 register to "0" (PLL off) and the PLV00 bit to "0" (no power to PLL) before the microcomputer enters wait or stop mode. The V CONT and P86 pins share pins with XCIN and XCOUT pins. When the PLL frequency synthesizer is being used, the sub clock cannot be used. Switch to the main clock Determine several times whether the CM23 bit is set to "0" (main clock oscillates) Set the CM22 bit to "0" (main clock does not stop) Set the MCD register to "0816" (divide-by-8) Set the CM21 bit to "0" (main clock as CPU clock source) End CM21 to CM23 bits : Bits in CM2 register Yes No

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8.2 CPU Clock and BCLK

The CPU operation clock is referred to as the CPU clock. The CPU clock is also the count source for the watchdog timer. After reset, the CPU clock is the main clock divided-by-8. In memory expansion or micro- processor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Refer to 8.4 Clock Output Function for details. The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the CPU clock. Table 8.3 shows CPU clock source and bit settings. When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock, the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock. The MCD register selects the clock division. When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip oscillator clock is the CPU clock), the MCD register is set to "08 16" (divide-by-8 mode). Therefore, when the main clock starts running, the CPU clock enters middle-speed mode (divide-by-8). Table 8.3 CPU Clock Source and Bit Settings CM0 Register CM2 Register CM1 Register CPU Clock Source CM07 CM21 CM17 Main Clock 0 0 0 Sub Clock 1 0 0 On-chip Oscillator Clock 0 1 0 PLL Clock 0 0 1

8.3 Peripheral Function Clock

The peripheral function clock becomes the operation clock or count source for peripheral functions exclud- ing the watchdog timer. 8.3.1 f1, f8, f32 and f2n f1, f8, f32 and f2n are the main clock(1) or on-chip oscillator clock divided-by-1, -8, -32 ,or -2n (n=1 to 15. No division when n=0). The CM21 bit determines which clock is selected. When the CM02 bit is set to "1" (peripheral function stops in wait mode) when entering wait mode, f 1, f8, f32 and f2n stop running. These clocks also stop in low-power consumption mode. f1, f8 and f2n are used as the operation clock for the serial I/O and the count source for timers A and B. The CNT3 to CNT0 bits in the TCSPR register selects a f2n division. f1 is also used as the operation clock for the intelligent I/O. The CLK OUT pin outputs f8 and f32 . Refer to 8.4 Clock Output Function for details. 8.3.2 fAD fAD is the operation clock for the A/D convertor and has the same frequency as the main clock(1) and on- chip oscillator clock. The CM21 bit determines which clock is selected. When the CM02 bit is set to "1" (peripheral function stop in wait mode) when entering wait mode, f AD stops. fAD also stops in low-power consumption mode. NOTES: 1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock.

Page 80 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M 8.3.3 fC32 fC32 is the sub clock divided by 32. fC32 is used for as a count source for the timers A and B. fC32 is available when the sub clock is running.

8.4 Clock Output Function

The CLKOUT pin outputs fC , f8 or f32. In memory expansion and microprocessor modes, a clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Table 8.4 lists CLK OUT pin function in single-chip mode. Table 8.5 lists CLKOUT pin functions in memory expansion and microprocessor modes. Table 8.4 CLKOUT Pin in Single-Chip Mode - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable) 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable) Table 8.5 BLCK/CLKOUT Pin in Memory Expansion Mode and Microprocessor Mode(4) PM07 CM01 CM00 CLK OUT Pin Function P53 I/O port Outputs fc Outputs f8 Outputs f32 PM0 Register (1) CM0 Register (2) - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM0 and PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable) 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable) 3. When the PM07 bit is set to "0" (selected in the CM01 to CM00 bits) or the PM15 to PM14 bits are set to "012" (P53/BCLK), set the CM01 to CM00 bits to "002" (I/O port P53) 4. M32C/83T cannot be used in memory expansion mode and microprocessor mode.

8.5 Power Consumption Control

Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operation mode in this document. Figure 8.14 shows a block diagram of status transition in wait mode and stop mode. Figure 8.15 shows a block diagram of status transition in all modes. (3) 002, 102, 112, Outputs BCLK Outputs "L" (not P53) Outputs fc Outputs f8 0 (3) 0 (3)0 1 Outputs f32 Outputs ALE 0 (3) PM07 CM01 CM00PM14 CLK OUT Pin Function PM15 PM0 Register(1) CM0 Register(2)PM1 Register(1)

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8.5.1 Normal Operation Mode

The normal operation mode is further separated into six modes. In normal operation mode, the CPU clock and peripheral function clock are supplied to operate the CPU and peripheral function. The power consumption control is enabled by controlling the CPU clock fre- quency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. When unnecessary oscillation circuits stop, power consumption is further reduced.

8.5.1.1 High-Speed Mode

(1) becomes the CPU clock and the clock source for the peripheral function clock. When the sub clock runs, fC32 can be used as a count source for the timers A and B.

8.5.1.2 Medium-Speed Mode

The main clock divided-by-2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The main clock is the clock source for the peripheral function clock. When the sub clock runs, f C32 can be used as the count source for the timers A and B.

8.5.1.3 Low-Speed Mode

The sub clock becomes the CPU clock. The main clock is the count source for the peripheral function clock. f C32 can be used as the count source for the timers A and B.

8.5.1.4 Low-Power Consumption Mode

The microcomputer enters low-power consumption mode when the main clock stops in low-speed mode. The sub clock becomes the CPU clock. f C32 can be used as the count source for timers A and B. Only fC32 can be used as the peripheral function clock. In low-power consumption mode, the MCD register is set to "0816" (divide-by-8 mode). Therefore, when the main clock resumes running, the microcomputer is in middle-speed mode (divide-by-8 mode).

8.5.1.5 On-chip Oscillator Mode

The on-chip oscillator clock divided-by-1(no division), -2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is the clock source for the peripheral function clock. When the sub clock runs, f C32 can be used as the count source for the timers A and B.

8.5.1.6 On-chip Oscillator Low-Power Consumption Mode

The microcomputer enters on-chip oscillator low-power consumption mode when the main clock stops in on-chip oscillator mode. The on-chip oscillator clock divided-by-1(no division), -2, -3, -4, -6, -8, -10, - 12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is the clock source for the peripheral function clock. When the sub clock runs, f C32 can be used as the count source for the timers A and B. Switch the CPU clock after the clock to be switched to stabilizes. Sub clock oscillation will take longer(2) to stabilize. Wait, by program, until the clock stabilizes directly after running the microcomputer on or exiting stop mode. To switch the on-chip oscillator to the main clock, enter medium-speed mode (divide-by-8) after the main clock is divided by eight in on-chip oscillator mode (MCD register=08 16). Do not enter on-chip oscillator mode or on-chip oscillator low-power consumption mode from low-speed mode or low-power consumption mode and vice versa. NOTES: 1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock . 2. Contact your oscillator manufacturer for oscillation stabilization time.

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8.5.2 Wait Mode

In wait mode, the CPU clock stops running. The CPU and watchdog timer, operated by the CPU clock, also stop. Because the main clock, sub clock and on-chip oscillator clock continue running, peripheral functions using these clocks also continue operating.

8.5.2.1 Peripheral Function Clock Stop Function

If the CM02 bit is set to "1" (peripheral function clock stops in wait mode), f 1, f8, f32, f2n and fAD stop in wait mode. Power consumption can be reduced because the peripheral function that has f1, f8, f32, f2n, or fAD as a count source stops. fC32 does not stop running.

8.5.2.2 Entering Wait Mode

Follow the procedure below to enter wait mode.

Initial Setting Set each interrupt priority level after setting the exit priority level required to exit wait mode, con- trolled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
Before Entering Wait Mode (1) Set the I flag to "0" (2) Set the interrupt priority level of the interrupt being used to exit wait mode (3) Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0" (4) Set the IPL in the FLG register. Then set the exit priority level to the same level as IPL (Interrupt priority level of the interrupt used to exit wait mode > exit priority level ≥ interrupt priority level of the interrupts not used to exit wait mode) (5) Set the PRC0 bit in the PRCR register to "1" (write enable) (6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock), the PLC07 bit in the PLC0 register to "0" (PLL off), and the PLV00 bit in the PLV register to "0"(cut off power to PLL) (7) Set the I flag to "1" (8) Execute the WAIT instruction
After Exiting Wait Mode Set the interrupt priority level required to exit wait mode to "7" immediately after exiting wait mode.

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8.5.2.3 Pin Status in Wait Mode

Table 8.6 lists pin states in wait mode. Table 8.6 Pin Status in Wait Mode Pin Memory Expansion Mode Single-Chip Mode Microprocessor Mode Address Bus, Data Bus, CS0 to CS3, Maintains state immediately BHE before entering wait mode RD, WR, WRL, WRH, DW, CASL, CASH "H" (1) RAS "H" (1) HLDA, BCLK "H" ALE "L" Port Maintains state immediately before entering wait mode CLK OUT When fC is selected Outputs clock When f8, f32 are selectedThe clock is output when the CM02 bit in the CM0 register is set to "0" (peripheral function clock not stop in wait mode). Maintains state immediately before entering wait mode when the CM02 bit is set to "1" (peripheral function clock stopped in wait mode). NOTES: 1. When performing a self-refresh operation using the DRAMC, CAS and RAS become low ("L"). 2. M32C/83T cannot be used in memory expansion mode and microprocessor mode.

8.5.2.4 Exiting Wait Mode

Wait mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts. When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupt disabled) before executing the WAIT instruction. The CM02 bit affects the peripheral function interrupts. When the CM02 bit is set to "0" (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to "1" (peripheral function clock stops in wait mode), peripheral functions using the peripheral function clock stop. Therefore, the peripheral function interrupts cannot be used to exit wait mode. However, peripheral function interrupts caused by an external signal can be used to exit wait mode. The CPU clock used when exiting wait mode by the peripheral function interrupts or NMI interrupt is the same CPU clock used when WAIT instructions are executed. Table 8.7 shows interrupts to be used to exit wait mode and usage conditions.

Page 84 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Table 8.7 Interrupts to Exit Wait Mode Interrupt When CM02=0 When CM02=1 NMI Interrupt Available Available Serial I/O Interrupt Available when the internal and externalAvailable only when the external clock is used clocks are used Key Input Interrupt Available Available A/D Conversion InterruptAvailable in single or single-sweep mode Do not use Timer A Interrupt Available in all modes Available in event counter mode or when Timer B Interrupt the count source is f C32 INT Interrupt Available Available CAN Interrupt Available Do not use Intelligent I/O Interrupt Available Do not use

8.5.3 Stop Mode

In stop mode, all oscillators and resonators stop. The CPU clock and peripheral function clock, as well as the CPU and peripheral functions operated by these clocks, also stop. The least power required to operate the microcomputer is in stop mode. The internal RAM holds its data if the voltage applied to the Vcc pin is 2.5V or more. Interrupts used to exit stop mode are NMI interrupt, key input interrupt, and INT interrupt.

8.5.3.1 Entering Stop Mode

Stop mode is entered when setting the CM10 bit in the CM1 register to "1" (all clocks stops). The MCD4 to MCD0 bits in the MCD register become set to "010002" (divide-by-8 mode). Enter stop mode after setting the followings.

Initial Setting Set each interrupt priority level after setting the minimum interrupt priority level required to exit stop or wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
Before Entering Stop Mode (1) Set the I flag to "0" (2) Set the interrupt priority level of the interrupt being used to exit stop mode (3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0" (4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL (Interrupt priority level of the interrupt used to exit stop mode > interrupt priority level to exit stop mode ≥ interrupt priority level of the interrupts not used to exit stop mode) (5) Set the PRC0 bit in the PRCR register to "1" (write enabled) (6) Select the main clock as the CPU clock
When the CPU clock source is the sub clock, Set the CM05 bit in the CM0 register to "0" (main clock oscillates) and CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by MCD register setting)
When the CPU clock source is the PLL clock, Set the CM17 bit in the CM1 register to "0" (main clock) and the PLC07 bit in the PLC0 register to "0" (PLL off)
When the CPU clock source is the on-chip oscillator clock, Set the MCD4 to MCD0 bits to "010002" (divide-by-8 mode), the CM05 bit to "0" (main clock oscillates), and the CM21 it in the CM2 register to "0" (clock selected by the CM17 bit)

Page 85 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M (7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscilla tion stop detect function disabled) (8) Set the I flag to "1" (9) Set the CM10 bit to "1" (all clocks stops)

After Exiting Stop Mode Set the interrupt priority level required to exit stop mode to "7" immediately after exiting stop mode.

8.5.3.2 Exiting Stop Mode

Stop mode is exited by the hardware reset, NMI interrupt, or peripheral function interrupts (key input interrupt and INT interrupt). When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to "000 2" (interrupt disabled) before setting the CM10 bit to "1" (all clocks stops).

8.5.3.3 Pin Status in Stop Mode

Table 8.8 lists pin status in stop mode. Table 8.8 Pin Status in Stop Mode Pin Memory Expansion Mode Single-Chip Mode Microprocessor Mode(2) Address Bus, Data Bus, CS0 to CS3, BHE Maintains state immediately before entering stop mode RD, WR, WRL, WRH, DW, CASL, CASH "H" (1) RAS "H" (1) HLDA, BCLK "H" ALE "H" Port Maintains state immediately before entering stop mode CLK OUT When fC selected "H" When f8, f32 selected Maintains state immediately before entering stop mode XIN High-impedance XOUT "H" XCIN, XCOUT High-impedance NOTES: 1. When performing a self-refresh operation using DRAMC, CAS and RAS become low ("L"). 2. M32C/83T cannot be used in memory expansion mode and microprocessor mode.

Page 86 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Wait mode Normal operation mode CPU operation is stopped CM10=1 CM10=1 All oscillation is stopped Interrupt Wait mode Wait mode Stop mode Stop mode Wait mode WAIT instruction WAIT instruction WAIT instruction WAIT instruction Interrupt Interrupt Interrupt Interrupt Interrupt Reset Middle-speed mode (divide-by-8 mode) High-speed / middle-speed mode Low-speed/ low-power consumption mode (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) (Note 3) On-chip oscillator / On-chip oscillator low- power consumption NOTES: 1. See Figure 8.15. 2. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source) before the PLC07 bit is set to "0" (PLL off). Set the PLV00 bit to "0" (no power to PLL) before the microcomputer enters wait mode or stop mode. 3. When the PLL frequency synthesizer is used, the microcomputer cannot enter low-speed and low-power consumption mode. (Note 2) Figure 8.14 Status Transition in Wait Mode and Stop Mode

Page 87 884fo6002,13.naJ13.1.veR 1310-4300B90JER 8. Clock Generation Circuit)T38/C23M,38/C23M(puorG38/C23M Main clock oscillationSub clock stopOn-chip oscillator clock stopPLL clock stopCPU clock: f(X IN )/8 CM07=0 MCD=08 CM21=0 CM05=0 CM04=0 PLC07=0PLC11=0 CM17=0 MCD=XX (Note 1) Main clock oscillationSub clock oscillationOn-chip oscillator clock stopPLL clock stop CPU clock: f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=1 PLC07=0PLC11=0 CM17=0CPU clock: f(X IN )/n CM21=0 CM05=0 CM04=1 PLC07=0PLC11=0 CM17=0 CM04=1 (Note 1) Main clock oscillation Sub clock stop On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/ n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX CM21=1 CM05=0 CM04=0 PLC07=0 PLC11=0 CM17=0 : Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown. MCD=XX : Desired division must be set in the MCD register. NOTES: 1. Switch clock after main clock oscillation is full y stabilized. 2. Switch clock after sub clock oscillation is full y stabilized. 3. The MCD register is set to "08 " (divide-by-8 mode) automatically. 4. When the CM20 bit is set to "1" ( oscillation stop detect function enabled ), the microcomputer detects a main clock oscillation stop. If the microcomputer then enters on-chip oscillator lo w power consumption mode, the CM05 bit is set to "1" (main clock stopped). See Figure 1.8.10 about the follow-up handling. CM21=1 (Note 1) CM21=0 CM05=1 CM05=0 High-speed mode CM04=0 CM04=1 On-chip oscillator mode CM21=1 (Note 1) CM21=0 CM04=0 CM04=1 CM04=0 CM04=1 Main clock stopis detected whenCM20=1 (Note 4, 5) Low-speed mode CM07=0 (Note 1)CM07=1 (Note 2) PLC07=0PLC07=1 Low-speed mode CM21=1(Note 1) CM21=0 Low power consumption mode Low power consumption mode CM05=1 CM05=0 CM05=1 CM05=0 CM07=0 CM07=1(Note 2) (Note 3) (Note 3) After reset,middle-speed mode ( divide-by-8) (Note 5) Main clock stopis detected whenCM20=1 Middle-speed mode Main clock oscillationSub clock stopOn-chip oscillator clock stopPLL clock stopCPU clock: f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=0 PLC07=0PLC11=0 CM17=0CPU clock: f(X IN )/n CM21=0 CM05=0 CM04=0 PLC07=0PLC11=0 CM17=0High-speed modeMiddle-speed mode Main clock stop Sub clock stop On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX CM21=1 CM05=1 CM04=0 PLC07=0 PLC11=0 CM17=0On-chip oscillator lo w power consumption mode CM05=1 CM05=0 Main clock oscillation Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX CM21=1 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0On-chip oscillator mode Main clock stop Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX CM21=1 CM05=1 CM04=1 PLC07=0 PLC11=0 CM17=0 Main clock oscillation Sub clock oscillation On-chip oscillator clock stop PLL clock stop CPU clock: f(X CIN CM07=1 CM21=0 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0 Main clock oscillation Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: f(X CIN CM07=1 CM21=1 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0 Main clock stop Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: f(X CIN CM07=1 MCD=08 CM21=1 CM05=1 CM04=1 PLC07=0 PLC11=0 CM17=0 Main clock stop Sub clock oscillation On-chip oscillator clock stop PLL clock stop CPU clock: f(X CIN CM07=1 MCD=08 CM21=0 CM05=1 CM04=1 PLC07=0 PLC11=0 CM17=0 Main clock oscillationSub clock oscillationOn-chip oscillator clock stopPLL clock oscillation CPU clock: f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=1 PLC07=1PLC11=0 CM17=0CPU clock: f(X IN )/n CM21=0 CM05=0 CM04=1 PLC07=1PLC11=0 CM17=0High-speed modeMiddle-speed mode Main clock oscillationSub clock oscillationOn-chip oscillator clock stopPLL clock oscillation CPU clock: f(X PLL CM07=0 MCD=12 CM21=0 CM05=0 CM04=1 PLC07=1PLC11=1 CM17=1CPU clock: f(X PLL )/n CM21=0 CM05=0 CM04=1 PLC07=1PLC11=1 CM17=1High-speed modeMiddle-speed mode PLC11=0CM17=0 PLC11=1CM17=1 (Note 6) PLC07=0PLC07=1 Main clock oscillationSub clock stopOn-chip oscillator clock stopPLL clock oscillation CPU clock: f(X PLL CM07=0 MCD=12 CM21=0 CM05=0 CM04=0 PLC07=1PLC11=1 CM17=1CPU clock: f(X PLL )/n CM21=0 CM05=0 CM04=0 PLC07=1PLC11=1 CM17=1High-speed modeMiddle-speed mode Main clock oscillationSub clock stopOn-chip oscillator clock stopPLL clock oscillation CPU clock: f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=0 PLC07=1PLC11=0 CM17=0CPU clock: f(X IN )/n CM21=0 CM05=0 CM04=0 PLC07=1PLC11=0 CM17=0High-speed modeMiddle-speed mode PLC11=0CM17=0 (Note 6)PLC11=1 CM17=1 On-chip oscillator lo w power consumption mode 5. The CM05 bit is not s et to "1" when the microcomputer detects a main clock oscillation stop throu gh the oscillation stop detect circuit 6. To select the PLL clock, set the PLC07 bit to "1" (PLL on) after the PLC11 bit is set to "1" (division enabled). To select the main clock, set the PLC11 bit to "0" (division disabled) after the PLC07 bit is set to "0" (PLL off). Switch the PLL clock after a PLL clock oscillation is full y stabilized. Figure 8.15 Status Transition

Page 89 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Undefined Instruction (UND Instruction) Overflow (INTO Instruction) BRK Instruction BRK2 Instruction (2) INT Instruction Software (Non-Maskable Interrupt) Hardware Interrupt NMI Watchdog Timer Oscillation Stop Detect Single-Step (2) Address Match DMACII Special (Non-Maskable Interrupt) Peripheral Function (1) (Maskable Interrupt) NOTES: 1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt. 2. Do not use this interrupt. For development support tools only. 10. Interrupts

10.1 Types of Interrupts

Figure 10.1 shows types of interrupts. Figure 10.1 Interrupts

Maskable Interrupt The I flag enables or disables an interrupt. The interrupt priority order based on interrupt priority level can be changed.
Non-maskable Interrupt The I flag does not enable nor disable an interrupt . The interrupt priority order based on interrupt priority level cannot be changed.

10.2 Software Interrupts

Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable inter- rupts.

10.2.1 Undefined Instruction Interrupt

The undefined instruction interrupt occurs when the UND instruction is executed.

10.2.2 Overflow Interrupt

The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic operation) and the INTO instruction is executed. Instructions to set the O flag are : ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX

10.2.3 BRK Interrupt

The BRK interrupt occurs when the BRK instruction is executed.

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10.2.4 BRK2 Interrupt

The BRK2 interrupt occurs when the BRK2 instruction is executed. Do not use this interrupt. For development support tools only.

10.2.5 INT Instruction Interrupt

The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 7 to 54, and 57 are assigned to the vector table used for the peripheral function interrupt. Therefore, the microcomputer executes the same service routine when the INT instruction is executed as when a peripheral function interrupt occurs. When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the relocatable vector of the specified software interrupt number. Where the stack is saved varies, depend- ing on the software interrupt number. ISP is selected as the stack for the software interrupt numbers 0 to 31 (the U flag is set to "0"). SP, which is set before the INT instruction is executed, is selected as the stack for the software interrupt numbers 32 to 63 (the U flag is not changed). With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select) when an interrupt request is acknowledged. With software interrupt numbers 32 to 54 and 57, the SP to be used varies, depending on whether the interrupt is generated by the peripheral function interrupt request or by the INT instruction.

10.3 Hardware Interrupts

Special interrupts and peripheral function interrupts are available as hardware interrupts.

10.3.1 Special Interrupts

Special interrupts are non-maskable interrupts.

10.3.1.1 NMI Interrupt

The NMI interrupt occurs when a signal applied to the NMI pin changes from an "H" signal to an "L" signal. Refer to 10.8 NMI Interrupt for details.

10.3.1.2 Watchdog Timer Interrupt

The watchdog timer interrupt occurs when the count source of the watchdog timer underflows. Refer to 11. Watchdog Timer for details.

10.3.1.3 Oscillation Stop Detection Interrupt

The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscilla- tion stop. Refer to 8. Clock Generating Circuit for details.

10.3.1.4 Single-Step Interrupt

Do not use the single-step interrupt. For development support tool only.

10.3.1.5 Address Match Interrupt

The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 3) when the AIERi bit in the AIER register is set to "1" (address match interrupt enabled). Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur when a table data or addresses of the instruction other than the starting address, if the instruction has multiple addresses, is set. Refer to 10.10 Address Match Interrupt for details.

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10.3.2 Peripheral Function Interrupt

The peripheral function interrupt occurs when a request from the peripheral functions in the microcom- puter is acknowledged. The peripheral function interrupts and software interrupt numbers 7 to 54 and 57 for the INT instruction use the same interrupt vector table. The peripheral function interrupt is a maskable interrupt. See Table 10.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details.

10.4 High-Speed Interrupt

The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in 3 cycles. When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "111 2" (level 7) to use the high-speed interrupt. Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority level 7 available for interrupts). Set the starting address of the high-speed interrupt service routine in the VCT register. When the high-speed interrupt is acknowledged, the FLG register is saved to the SVF register and PC is saved to the SVP registers. The program is executed from an address indicated by the VCT register. Execute the FREIT instruction to return from the high-speed interrupt service routine. The values saved to the SVF and SVP registers are restored to the FLG register and PC by executing the FREIT instruction. The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used.

10.5 Interrupts and Interrupt Vectors

There are four bytes in one vector. Set the starting address of interrupt service routine in each vector table. When an interrupt request is acknowledged, the interrupt service routine is executed from the address set in the interrupt vectors. Figure 10.2 shows the interrupt vector. Figure 10.2 Interrupt Vector /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Middle-order bits of an address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low-order bits of an address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines High-order bits of an address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 16 Vector Address + 0 Vector Address + 1 Vector Address + 2 Vector Address + 3 LSBMSB

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10.5.1 Fixed Vector Tables

The fixed vector tables are allocated addresses FFFFDC16 to FFFFFF16. Table 10.1 lists the fixed vector tables. Refer to 25.2 Functions to Prevent Flash Memory from Rewriting for fixed vectors of the flash memory. Table 10.1 Fixed Vector Table

10.5.2 Relocatable Vector Tables

The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 10.2 lists the relocatable vector tables. Set an even address as the starting address of the vector table set in the INTB register to increase interrupt sequence execution rate. tpurretnI ybdetareneG sesserddArotceV )H(sserddAot)L(sserddA skrameRe cnerefeR denifednU noitcurtsnI CDFFFF 61 FDFFFFot 61 seires08/C23M launamerawtfos wolfrevO0 EFFFF 61 3EFFFFot 61 noitcurtsnIKRB4 EFFFF 61 7EFFFFot 61 7EFFFFsserddafotnetnocehtfI 61 si FF 61 ehtmorfdetucexesimargorpeht, tpurretnierawtfosotniderotssserdda elbatrotcevelbatacolerehtni0rebmun hctaMsserddA8 EFFFF 61 BEFFFFot 61 -C EFFFF 61 FEFFFFot 61 ecapsdevreseR remiTgodhctaW0 FFFFF 61 3FFFFFot 61 ehtrofdesuerasesserddaesehT ehtdnatpurretniremitgodhctaw tpurretnitcetedpotsnoitallicso ,tiucricnoitallicsokcolC remitgodhctaW -4 FFFFF 61 7FFFFFot 61 ecapsdevreseR IMN8 FFFFF 61 BFFFFFot 61 teseRC FFFFF 61 FFFFFFot 61 teseR

Page 93 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Table 10.2 Relocatable Vector Tables Interrupt Generated by Vector Table Address Software Reference Address(L) to Address(H)(1) Interrupt Number BRK Instruction(2) +0 to +3 (000016 to 000316) 0 M32C/80 Series Reserved Space +4 to +27 (0004 16 to 001B16) 1 to 6 Software Manual A/D1 +28 to +31 (001C 16 to 001F16) 7 A/D Converter DMA0 +32 to +35 (0020 16 to 002316) 8 DMAC DMA1 +36 to +39 (0024 16 to 002716)9 DMA2 +40 to +43 (0028 16 to 002B16)1 0 DMA3 +44 to +47 (002C 16 to 002F16)1 1 Timer A0 +48 to +51 (0030 16 to 003316) 12 Timer A Timer A1 +52 to +55 (0034 16 to 003716)1 3 Timer A2 +56 to +59 (0038 16 to 003B16)1 4 Timer A3 +60 to +63 (003C 16 to 003F16)1 5 Timer A4 +64 to +67 (0040 16 to 004316)1 6 UART0 Transmission, NACK(3) +68 to +71 (004416 to 004716) 17 Serial I/O UART0 Reception, ACK(3) +72 to +75 (004816 to 004B16)1 8 UART1 Transmission, NACK(3) +76 to +79 (004C16 to 004F16)1 9 UART1 Reception, ACK(3) +80 to +83 (005016 to 005316)2 0 Timer B0 +84 to +87 (0054 16 to 005716) 21 Timer B Timer B1 +88 to +91 (0058 16 to 005B16)2 2 Timer B2 +92 to +95 (005C 16 to 005F16)2 3 Timer B3 +96 to +99 (0060 16 to 006316)2 4 Timer B4 +100 to +103 (0064 16 to 006716)2 5 INT5 +104 to +107 (0068 16 to 006B16) 26 Interrupt INT4 +108 to +111 (006C 16 to 006F16)2 7 INT3 +112 to +115 (0070 16 to 007316)2 8 INT2 +116 to +119 (0074 16 to 007716)2 9 INT1 +120 to +123 (0078 16 to 007B16)3 0 INT0 +124 to +127 (007C 16 to 007F16)3 1 Timer B5 +128 to +131 (0080 16 to 008316) 32 Timer B UART2 Transmission, NACK(3) +132 to +135 (008416 to 008716) 33 Serial I/O UART2 Reception, ACK(3) +136 to +139 (008816 to 008B16)3 4 UART3 Transmission, NACK(3) +140 to +143 (008C16 to 008F16)3 5 UART3 Reception, ACK(3) +144 to +147 (009016 to 009316)3 6 UART4 Transmission, NACK(3) +148 to +151 (009416 to 009716)3 7 UART4 Reception, ACK(3) +152 to +155 (009816 to 009B16)3 8

Page 94 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Table 10.2 Relocatable Vector Tables (Continued) Interrupt Generated by Vector Table Address Software Reference Address(L)to Address(H)(1) Interrupt Number Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39 Serial I/O Stop Condition Detect, (UART2)(3), Fault Error(4) Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316)4 0 Stop Condition Detect, (UART3/UART0) (5), Fault Error(4) Bus Conflict Detect, Start Condition Select, +164 to +167 (00A416 to 00A716)4 1 Stop Condition Detect, (UART4/UART1) (5), Fault Error(4) A/D0 +168 to +171 (00A8 16 to 00AB16) 42 A/D Converter Key Input +172 to +175 (00AC 16 to 00AF16) 43 Interrupts Intelligent I/O Interrupt 0 +176 to +179 (00B0 16 to 00B316) 44 Intelligent I/O Intelligent I/O Interrupt 1 +180 to +183 (00B4 16 to 00B716) 45 CAN Intelligent I/O Interrupt 2 +184 to +187 (00B8 16 to 00BB16)4 6 Intelligent I/O Interrupt 3 +188 to +191 (00BC 16 to 00BF16)4 7 Intelligent I/O Interrupt 4 +192 to +195 (00C0 16 to 00C316)4 8 Intelligent I/O Interrupt 5 +196 to +199 (00C4 16 to 00C716)4 9 Intelligent I/O Interrupt 6 +200 to +203(00C8 16 to 00CB16)5 0 Intelligent I/O Interrupt 7 +204 to +207(00CC 16 to 00CF16)5 1 Intelligent I/O Interrupt 8 +208 to +211(00D0 16 to 00D316)5 2 Intelligent I/O Interrupt 9, CAN 0 +212 to +215 (00D416 to 00D716)5 3 Intelligent I/O Interrupt 10, CAN 1 +216 to +219 (00D816 to 00DB16)5 4 Reserved Space +220 to +227 (00DC 16 to 00E316) 55 to 56 Intelligent I/O Interrupt 11, CAN 2 +228 to +231 (00E416 to 00E716) 57 Intelligent I/O CAN Reserved Space +232 to +255 (00E8 16 to 00FF16) 58 to 62 INT Instruction(2) +0 to +3 (000016 to 000316) to 0 to 63 Interrupts +252 to +255 (00FC16 to 00FF16) NOTES: 1. These addresses are relative to those in the INTB register. 2. The I flag does not disable interrupts. 3. In I2C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated. 4. When the SS pin is selected, fault error causes an interrupt to be generated. 5. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in UART3. The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in UART4.

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10.6 Interrupt Request Reception

Software interrupts and special interrupts occur when conditions to generate an interrupt are met. The peripheral function interrupts are acknowledged when all conditions below are met.

I flag = "1"
IR bit = "1"
ILVL2 to ILVL0 bits > IPL The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.

10.6.1 I Flag and IPL

The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically set to "0" after reset. IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7. If a requested interrupt has higher priority than that indicated by IPL, the interrupt is acknowledged. Table 10.3 lists interrupt priority levels associated with IPL. Table 10.3 Interrupt Priority Levels IPL2 IPL1 IPL0 Interrupt Priority Levels 0 0 0 Level 1 and above 0 0 1 Level 2 and above 0 1 0 Level 3 and above 0 1 1 Level 4 and above 1 0 0 Level 5 and above 1 0 1 Level 6 and above 1 1 0 Level 7 and above 1 1 1 All maskable interrupts are disabled

10.6.2 Interrupt Control Register and RLVL Register

The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 10.3 and 10.4 show the interrupt control register. Figure 10.5 shows the RLVL register.

Page 96 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Interrupt Control Register After Reset XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 Address 006C 16, 008C16, 006E16, 008E16, 007016 009416, 007616, 009616, 007816, 009816, 006916 009016, 009216, 008916, 008B16, 008D16 007216, 007416, 006B16, 006D16, 006F16 007116, 009116, 008F16, 007116(1), 009116(2) 006816, 008816, 006A16, 008A16 007316, 008616 009316 007516, 009516, 007716, 009716, 007916, 009916 007B16, 009B16, 007D16, 009D16, 007F16, 008116 009D 16, 007F16, 008116(3) Symbol TA0IC to TA4IC TB0IC to TB5IC S0TIC to S4TIC S0RIC to S4RIC BCN0IC to BCN4IC DM0IC to DM3IC AD0IC, AD1IC KUPIC IIO0IC to IIO5IC IIO6IC to IIO11IC CAN0IC0 to CAN2IC RW RW RW RW RW ILVL0 ILVL1 ILVL2 Interrupt Priority Level Select Bit IR (b7 - b4) NOTES: 1. The BCN0IC register shares an address with the BCN3IC register. 2. The BCN1IC register shares an address with the BCN4IC register. 3. The IIO9IC register shares an address with the CAN0IC register. The IIO10IC register shares an address with the CAN1IC register. The IIO11IC register shares an address with the CAN2IC register. 4. The IR bit can be set to "0" only (do not set to "1"). Interrupt Request Bit0 : No interrupt requested 1 : Interrupt requested (4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 Figure 10.3 Interrupt Control Register (1)

Page 97 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Figure 10.4 Interrupt Control Register (2)

10.6.2.1 ILVL2 to ILVL0 Bits

The ILVL2 to ILVL0 bits determines the interrupt priority level. The higher the interrupt priority level, the higher interrupt priority is. When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits are set to "000 2" (level 0), this interrupt is ignored.

10.6.2.2 IR Bit

The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and the program in the corresponding interrupt vector is executed. The IR bit can be set to "0" by program. Do not set to "1". Interrupt Control Register After Reset XX00 X000 XX00 X0002 Address 009E 16, 007E16, 009C16 007C 16, 009A16, 007A16 Symbol INT0IC to INT2IC INT3IC to INT5IC (1) RW RW RW RW RW RW RW ILVL0 ILVL1 ILVL2 Interrupt Priority Level Select Bit IR POL LVS (b7 - b6) Interrupt Request Bit Polarity Switch Bit Level Sensitive/Edge Sensitive Switch Bit 0 : Requests no interrupt 1 : Requests an interrupt (2) 0 : Selects falling edge or "L"(3) 1 : Selects rising edge or "H" 0 : Edge sensitive 1 : Level sensitive(4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol NOTES: 1. When the 16-bit data bus is used in microprocessor or memory expansion mode, each pin for the INT3 to INT5 bits is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers to "000 2". 2. The IR bit can be set to "0" only (do not set to "1"). 3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges). 4. When setting the LVS bit to "1", set a bit corresponding to the IFSR register to "0" (one edge). b7 b6 b5 b4 b3 b2 b1 b0

Page 98 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Exit Priority Register After Reset XXXX 0000 2 Address 009F Symbol RLVL RW RW RW RW RW RW RLVL0 RLVL1 RLVL2 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit(1) FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt DMA II (b4) (b7 - b6) DMAC II Select Bit (4) 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMAC II transfer (3) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. 2. When the FSIT bit is set to "1", interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to interrupt priority level 7 and the DMA II bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. After reset, the DMA II bit is indeterminate. When using an interrupt, set the interrupt control register after setting the DMA II bit to "0". Figure 10.5 RLVL Register

10.6.2.3 RLVL2 to RLVL0 Bits

When using an interrupt to exit stop or wait mode, refer to 8.5.2 Wait Mode and 8.5.3 Stop Mode for details.

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10.6.3 Interrupt Sequence

The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA instruction, if an interrupt request is generated while executing the instruction, the microcomputer sus- pends the instruction to start the interrupt sequence. The interrupt sequence is performed as follows: (1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address 000000 16 (address 00000216 for the high-speed interrupt). Then, the IR bit applicable to the interrupt information is set to "0" (interrupt requested). (2) The FLG register, prior to an interrupt sequence, is saved to a temporary register(1) within the CPU. (3) Each bit in the FLG register is set as follows:

The I flag is set to "0" (interrupt disabled)
The D flag is set to "0" (single-step disabled)
The U flag is set to "0" (ISP selected) (4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed interrupt. (5) PC is saved to the stack; or to the SVP register for the high-speed interrupt. (6) The interrupt priority level of the acknowledged interrupt is set in IPL . (7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC. After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt service routine. NOTES: 1. Temporary register cannot be modified by users.

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10.6.4 Interrupt Response Time

Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt generation and the execution of the first instruction in an interrupt service routine. An interrupt response time includes the period between an interrupt request generation and the completed execution of an in- struction ((a) in Figure 10.6) and the period required to perform an interrupt sequence ((b) in Figure 10.6) Figure 10.6 Interrupt Response Time Time (a) varies depending on the instruction being executed. The DIV instruction requires the longest time (a); 40 cycles when an immediate value or register is set as the divisor . When the divisor is a value in the memory, the following value is added.

Normal addressing : 2 + X
Index addressing : 3 + X
Indirect addressing : 5 + X + 2Y
Indirect index addressing : 6 + X + 2Y X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be doubled. Table 10.4 lists time (b). (a) Period between an interrupt request generation and the completed execution of an instruction. (b) Period required to perform an interrupt sequence. (a) (b) Time Instruction Interrupt response time Instruction in an interrupt routineInterrupt sequence Interrupt request is acknowledgedInterrupt request is generated

Page 101 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Table 10.4 Interrupt Sequence Execution Time 8-Bit Bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles 16 cycles 19 cycles 19 cycles 21 cycles 16-Bit Bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 14 cycles 17 cycles 19 cycles 19 cycles Interrupt Vector Address Even address Odd address (1) Even address Odd address (1) Even address(2) Even address(2) Even address Odd address (1) Even address(2) Vector table is internal register Interrupt Peripheral Function INT Instruction NMI Watchdog Timer Undefined Instruction Address Match Overflow BRK Instruction (relocatable vector table) BRK Instruction (fixed vector table) High-Speed Interrupt 5 cycles NOTES: 1. Allocate interrupt vectors to even addresses. 2. Vectors are fixed to even addresses.

10.6.5 IPL Change when Interrupt Request is Acknowledged

When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowl- edged interrupt. Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has no interrupt priority level is acknowledged, the value shown in Table 10.5 is set in IPL as the interrupt priority level. Table 10.5 Interrupts without Interrupt Priority Levels and IPL Interrupt Sources Level that is Set to IPL Watchdog Timer, NMI, Oscillation Stop Detect 7 Reset 0 Software, Address Match Not changed

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10.6.6 Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack. After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32 bits, are saved to the stack. Figure 10.7 shows the stack state before and after an interrupt request is acknowledged. Other important registers are saved by program at the beginning of an interrupt service routine. The PUSHM instruction can save all registers except SP. Refer to 10.4 High-Speed Interrupt for the high-speed interrupt. [SP] SP value before interrupt is generated Stack state before an interrupt request is acknowledged Address Stack state after an interrupt request is acknowledged m-6 m-5 m –4 m –3 m –2 m –1 m m+1 LSBMSBLSBMSBAddress The Stack The Stack FLG L PC H FLG H Content of previous stack Content of previous stack Content of previous stack Content of previous stack PC L PC M [SP] New SP value m-6 m-5 m –4 m –3 m –2 m –1 m m+1 0016 Figure 10.7 Stack States

10.6.7 Restoration from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt service routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, executed before an interrupt request has been acknowledged, starts running again. Refer to 10.4 High-Speed Interrupt for the high- speed interrupt. Restore registers saved by program in an interrupt service routine by the POPM instruction or others before the REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt sequence by the REIT or FREIT instruction.

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10.6.8 Interrupt Priority

If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an interrupt request is generated or not), the interrupt with the highest priority is acknowledged. Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral function interrupt). Priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are set by hardware. Figure 10.8 shows priority levels of hardware interrupts. The interrupt priority does not affect software interrupts. The microcomputer jumps to the interrupt rou- tine when the instruction is executed. Reset > NMI > > Peripheral Function > Address Match Watchdog Figure 10.8 Interrupt Priority

10.6.9 Interrupt Priority Level Select Circuit

The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are sampled at the same sampling point. Figure 10.9 shows the interrupt priority level select circuit.

Page 104 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Timer B2 Timer B0 Timer A0 Timer A1 Timer B1 UART1 Reception/ACK UART0 Reception/ACK Intelligent I/O Interrupt 1 A/D0 Converter UART1 Transmission/NACK UART0 Transmission/NACK Intelligent I/O Interrupt 0 Key Input Interrupt IPL I Flag Watchdog Timer, Oscillation Stop Detect Reset DMAC II NMI Interrupt request is acknowledged. To CPU Level 0 (initial value) Each Interrupt Priority LevelHigh Low Peripheral Function Interrupt Priority (if priority levels are the same) UART2 Reception/ACK Address Match Timer B4 Timer B3 DMA0 DMA1 DMA2 DMA3 Timer A2 Timer A3 Timer A4 UART2 Transmission/NACK UART3 Reception/ACK UART3 Transmission/NACK UART4 Reception/ACK UART4 Transmission/ NACK Bus Conflict/Start, Stop Condition( UART0,3) Bus Conflict/Start, Stop Condition(UART1,4) RLVL2 to RLVL0 Bits Interrupt request is acknowledged. To CLK A/D1 Converter Bus Conflict/Start, Stop Condition(UART2) Intelligent I/O Interrupt 2 Intelligent I/O Interrupt 3 Intelligent I/O Interrupt 4 Intelligent I/O Interrupt 5 Intelligent I/O Interrupt 6 Intelligent I/O Interrupt 7 Intelligent I/O Interrupt 8 Intelligent I/O Interrupt 9 /CAN Interrupt 0 Intelligent I/O Interrupt 10 /CAN Interrupt 1 Intelligent I/O Interrupt 11 /CAN Interrupt 2 INT3 INT5 INT4 INT1 INT2 INT0 Timer B5 Each Interrupt Priority Level Figure 10.9 Interrupt Priority Level Select Circuit

Page 105 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M External Interrupt Request Cause Select Register Symbol Address After Reset IFSR 031F 16 0016 RW INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit (1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity Select Bit(1) INT5 Interrupt Polarity Select Bit (1) 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges Bit Name Bit Symbol Function NOTES: 1.Set this bit to "0" to select level sensitive. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). UART1, UART4 Interrupt Cause Select Bit UART0, UART3 Interrupt Cause Select Bit 0 : One edge 1 : Both edges IFSR3 IFSR4 IFSR5 IFSR6 IFSR0 IFSR2 IFSR1 IFSR7 RW RW RW RW RW RW RW RW 0 : UART3 bus conflict, start condition detect, stop condition detect, fault error detect 1 : UART0 bus conflict, start condition detect, stop condition detect, fault error detect 0 : UART4 bus conflict, start condition detect, stop condition detect, fault error detect 1 : UART1 bus conflict, start condition detect, stop condition detect, fault error detect b7 b6 b5 b4 b3 b2 b1 b0

10.7 INT Interrupt

External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an inter- rupt at an applied signal level. The POL bit in the INTiIC register determines the polarity. With an edge sensitive triggering, when the IFSRi bit in the IFSR register is set to "1" (both edges), an interrupt occurs on both rising and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding register to "0" (falling edge). With a level sensitive triggering, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains set to "1" even if the INTi pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when "0" is written by program. Figure 10.10 shows the IFSR register. Figure 10.10 IFSR Register

Page 106 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M

10.8 NMI Interrupt

The NMI interrupt occurs when the signal applied to the P85/NMI pin changes from an "H" signal to an "L" signal. The NMI interrupt is a non-maskable interrupt. Although the P85/NMI pin is used as the NMI inter- rupt input pin, the P8_5 bit in the P85 register indicates input level for this pin. NOTES: When the NMI interrupt is not used, connect (pull-up) the NMI pin to Vcc via a resistor. Because the NMI interrupt cannot be ignored, the pin must be connected.

10.9 Key Input Interrupt

Key input interrupt request is generated when one of the signals applied to the P104 to P107 pins in input mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait or stop mode. To use the key input interrupt, do not use P10 4 to P107 as A/D input ports. Figure 10.11 shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode, signals applied to other pins are not detected as a request signal for an interrupt. When the PSC_7 bit in the PSC register (1) is set to "1" (key input interrupt disabled), no key input interrupt occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a port pin is available even when in input mode. NOTES: 1. Refer to 24. Programmable I/O Ports for details on the PSC register. Figure 10.11 Key Input Interrupt Interrupt Control Circuit KUPIC Register Key Input Interrupt Request P107/KI3 P106/KI2 P105/KI1 P104/KI0 PU31 bit in PUR3 register PD10_7 bit Pull-up transistor PD10_7 bit PD10_6 bit PD10_5 bit PD10_4 bit Pull-up transistor Pull-up transistorPull-up transistor PSC_7 bit

Page 107 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M AIER0 AIER1 AIER2 Address Match Interrupt 0 Enable Bit Address Match Interrupt 1 Enable Bit Address Match Interrupt 2 Enable Bit Address Match Interrupt 3 Enable Bit AIER3 (b7 - b4) Function Address Match Interrupt Enable Register 0 : Disables the interrupt 1 : Enables the interrupt Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit Name Bit Symbol Symbol Address After Reset AIER 0009 16 XXXX 0000 2 RW RW RW RW RW 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt b7 b6 b5 b4 b3 b2 b1 b0

10.10 Address Match Interrupt

The address match interrupt occurs immediately before executing an instruction that is stored into an ad- dress indicated by the RMADi register (i=0 to 3). The address match interrupt can be set in four addresses. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I flag and IPL do not affect the address match interrupt. Figure 10.12 shows registers associated with the address match interrupt. Set the starting address of an instruction in the RMADi register. The address match interrupt does not occur when a table data or addresses other than the starting address of the instruction is set. Figure 10.12 AIER Register and RMAD0 to RMAD3 Registers Address Match Interrupt Register i Function RW RW Setting Range Symbol Address After Reset RMAD0 0012 16 - 001016 000000 16 RMAD1 0016 16 - 001416 000000 16 RMAD2 001A 16 - 001816 000000 16 RMAD3 001E 16 - 001C16 000000 16 00000016 to FFFFFF16Addressing Register for the Address Match Interrupt b23 b16 b15 b8 b7 b0

Page 108 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Bit 1 IIOiIR Register(2) Intelligent I/O Interrupt i Request IIOiIE Register(3) IRLT Bit in IIOiIE Register Interrupt Request(1) Interrupt Request(1) Interrupt Request(1) Bit 2 Bit 7 Bit 1 Bit 2 Bit 7 i= 0 to 11 NOTES: 1. See Figures 10.14 and 10.15 for details on bits 1 to 7 in the IIOiIR register and bits 1 to 7 in the IIOiIE register. 2. Bits 1 to 7 in the IIOiIR register are not set to "0" automatically even if an interrupt request is generated. Set to "0" by program. 3. Do not change the IRLT bit and the interrupt enable bit in the IIOiIE register simultaneously.

10.11 Intelligent I/O Interrupt and CAN Interrupt

The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 54, and 57. Figure 10.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 10.14 shows the IIOiIR register (i = 0 to 11). Figure 10.15 shows the IIOiIE register. When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register to "1" (inter- rupt request for interrupt used). Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is gener- ated with intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1" (interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested). After the IR bit setting changes from "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1". Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit to "0" by program. If these bits remain set to "1", all generated interrupt requests are ignored. CAN interrupt uses bit 7 in the IIO9IR to IIO11IR registers and bit 7 in the IIO9IE to IIO11IE registers. IIO9IR to IIO11IR registers share addresses with the CAN0IC to CAN2IC registers. Refer to 22.3 CAN Interrupt for details. Figure 10.13 Intelligent I/O Interrupt and CAN Interrupt When using the intelligent I/O interrupt or CAN interrupt to activate DMAC II, set the IRLT bit in the IIOiIE register to "0" (an interrupt used for DMAC, DMAC II) to enable the interrupt request that the IIOiIE register requires.

Page 109 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Function Interrupt Request Register Bit Symbol Address See below After Reset 0000 000X2 Symbol IIO0IR to IIO11IR RW ( Note 2) 0 : Requests no interrupt 1 : Requests an interrupt NOTES: 1. See table below for bit symbols. 2. Only "0" can be set (nothing is changed even if "1" is set). (Note 1) (b0) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Symbol IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Address 00A0 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA 16 00AB 16 Bit 7 SRT0R IE0R IE1R CAN0R CAN1R CAN2R Bit 6 SRT1R IE2R Bit 5 SIO0RR SIO0TR SIO1RR SIO1TR Bit 0 Bit 4 G0RIR G0TOR G1RIR G1TOR BT1R SIO2RR SIO2TR BT0R BT2R SIO3RR SIO3TR BT3R Bit 3 PO27R PO32R PO33R PO34R PO35R PO36R PO31R PO30R PO37R Bit 2 PO13R PO14R TM12R/PO12R PO10R TM17R/PO17R PO21R PO20R PO22R PO23R PO24R PO25R PO26R Bit 1 TM02R TM00R/PO00R TM03R TM04R/PO04R TM05R/PO05R TM06R TM07R TM11R/PO11R PO15R TM16R/PO16R TM01R/PO01R Bit Symbols for the Interrupt Request Register BTiR TMmjR POijR SIOiRR/SIOiTR GmRIR/GmTOR SRTmR IEkR CANkR : Intelligent I/O Group i Base Timer Interrupt Request Bit (i=0 to 3) : Intelligent I/O Group m Time Measurement j Interrupt Request Bit (j=0 to 7)(m=0,1) : Intelligent I/O Group i Waveform Generation Function j Interrupt Request Bit : Intelligent I/O Group i Communication Function Interrupt Request Bit (RR:receive, TR:transmit) : Intelligent I/O Group m HDLC Data Processing Function Interrupt Request Bit (RIR:input to receive, TOR:input to transmit) : Intelligent I/O Group m Special Communication Function Interrupt Request Bit : Intelligent I/O Group 2 IEBus Communication Function Interrupt Request Bit (k = 0 to 2) : CAN Communication Function Interrupt Request Bit : Reserved bit. Set to "0". RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 10.14 IIO0IR to IIO11IR Registers

Page 110 884fo6002,13.naJ13.1.veR 1310-4300B90JER 10. Interrupts)T38/C23M,38/C23M(puorG38/C23M Function Interrupt Enable Register Bit NameBit Symbol Symbol Address IIO0IE to IIO11IE See below RW 0 : Disables an interrupt by bit 1 in IIOiIR register 1 : Enables an interrupt by bit 1 in IIOiIR register 0 : Disables an interrupt by bit 7 in IIOiIR register 1 : Enables an interrupt by bit 7 in IIOiIR register 0 : Disables an interrupt by bit 6 in IIOiIR register 1 : Enables an interrupt by bit 6 in IIOiIR register 0 : Disables an interrupt by bit 5 in IIOiIR register 1 : Enables an interrupt by bit 5 in IIOiIR register 0 : Disables an interrupt by bit 4 in IIOiIR register 1 : Enables an interrupt by bit 4 in IIOiIR register 0 : Disables an interrupt by bit 3 in IIOiIR register 1 : Enables an interrupt by bit 3 in IIOiIR register 0 : Disables an interrupt by bit 2 in IIOiIR register 1 : Enables an interrupt by bit 2 in IIOiIR register 0 : Interrupt request is used for DMAC, DMAC II 1 : Interrupt request is used for interruptIRLT Interrupt Request Select Bit (2) Address 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA 16 00BB 16 Bit 7 SRT 0E IE0E IE1E CAN0E CAN1E CAN2E Bit Symbols for the Interrupt Enable Register BTiE TMmjE POijE SIOiRE/SIOiTE GmRIE/GmTOE SRTm E IEkE CANkE Bit 6 SRT 1E IE2E Bit 5 SIO0RE SIO0TE SIO1RE SIO1TE Bit 4 G0RIE G0TOE G1RIE G1TOE BT1E SIO2RE SIO2TE BT0E BT2E SIO3RE SIO3TE BT3E Bit 3 PO27E PO32E PO33E PO34E PO35E PO36E PO31E PO30E PO37E Bit 2 PO13E PO14E TM12E/PO12E PO10E TM17E/PO17E PO21E PO20E PO22E PO23E PO24E PO25E PO26E Bit 1 TM02E TM00E/PO00E TM03E TM04E/PO04E TM05E/PO05E TM06E TM07E TM11E/PO11E PO15E TM16E/PO16E TM01E/PO01E Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE Bit 0 IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT RW RW RW RW RW RW RW RW NOTES: 1. See table below for bit symbols. 2. If an interrupt request is used for interrupt, set bit 1 to 7 to "1" after the IRLT bit is set to "1". (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) After Reset 0016 : Intelligent I/O Group i Base Timer Interrupt Enable Bit (i=0 to 3) : Intelligent I/O Group m Time Measurement j Interrupt Enable Bit (j=0 to 7)(m=0,1) : Intelligent I/O Group i Waveform Generation Function j Interrupt Enable Bit : Intelligent I/O Group i Communication Function Interrupt Enable Bit (RE:receive, TE:transmit) : Intelligent I/O Group m HDLC Data Processing Function Interrupt Enable Bit (RIE:input to receive, TOE:input to transmit) : Intelligent I/O Group m Special Communication Function Interrupt Enable Bit : Intelligent I/O Group 2 IEBus Communication Function Interrupt Enable Bit (k=0 to 2) : CAN Communication Function Interrupt Enable Bit : Reserved bit. Set to "0". b7 b6 b5 b4 b3 b2 b1 b0 Figure 10.15 IIO0IE to IIO11IE Registers

Page 112 884fo6002,13.naJ13.1.veR 1310-4300B90JER 11. Watchdog Timer)T38/C23M,38/C23M(puorG38/C23M WDC7 (b4 - b0) (b6 - b5) Reserved Bit Prescaler Select Bit Watchdog Timer Control Register High-Order Bit of Watchdog Timer 0 : Divide-by-16 1 : Divide-by-128 Set to "0" Symbol Address After Reset WDC 000F 16 000X XXXX 2 RW RO RW RW Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 Watchdog Timer Start Register Symbol Address After Reset WDTS 000E 16 Indeterminate RW WO Function The watchdog timer is reset to start counting by a write instruction to the WDTS register. Default value of the watchdog timer is always set to "7FFF 16" regardless of the value written. b7 b0 Figure 11.2 WDC Register and WDTS Register

Page 113 884fo6002,13.naJ13.1.veR 1310-4300B90JER 11. Watchdog Timer)T38/C23M,38/C23M(puorG38/C23M Symbol Address After Reset CM0 0006 16 0000 X000 2 System Clock Control Register 0(1) CM00 CM01 CM02 (b3) Clock Output Function Select Bit(2) In Wait Mode, Peripheral Function Clock Stop Bit Port X C Switch Bit Main Clock (XIN-XOUT ) Stop Bit(5) CM04 CM05 CM06 CM07 RWFunctionBit NameBit Symbol RW RW RW RW RW RW RW RW 0 : Main clock oscillates 1 : Main clock stops(6) 0 0 : I/O port P53 0 1 : Outputs fC 1 0 : Outputs f8 1 1 : Outputs f32 0 : I/O port function 1 : XCIN-XCOUT oscillation function(4) Watchdog Timer Function Select Bit System C lock Select Bit(8) 0: Clock selected by the CM21 bit divided by MCD register setting 1: Sub clock 0 : Watchdog timer interrupt 1 : Reset(7) NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to "002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), set the CM01 to CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 to CM00 bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "002", an "L" signal is output from port P53 (port P53 does not function as an I/O port). 3. fc32 does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode. 4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), set the PD8_7 to PD8_6 bits to "002" (with port P87 and P86 input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up). 5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode, the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the CM05 bit is set to "1", X OUT becomes "H". The built-in feedback resistor remains on. XIN is pulled up to XOUT ("H" level) via the feedback resistor. 6. When the CM05 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). In on-chip oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates XIN-XOUT . 7. Once the CM06 bit is set to "1", it cannot be set "0" by program. 8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0". After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1". Do not set the CM07 bit and CM04 or CM05 bits simultaneously. b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 0 : Peripheral clock does not stop in wait mode 1 : Peripheral clock stops in wait mode (3) Reserved Bit Set to "1" Figure 11.3 CM0 Register

Page 114 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M 12. DMAC This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized when using DMAC. DMAC2 and DMAC3 share registers required for high-speed interrupts. High-speed interrupts cannot be used when using three or more DMAC channels. The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. The cycle-steal method employed by DMAC enables high-speed operation between a transfer request and the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 12.1 shows a mapping of registers to ated with DMAC. Because the registers shown in Figure 12.1 are allocated to the CPU, use the LDC instruction to write to the registers. To set DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register bank 1) and set R0 to R3, A0, A1 registers with the MOV instruction. To set DSA2 and DSA3 registers, set the B flag to "1" and set the SB, FB, SVP, VCT registers with the LDC instruction. To set the DRA2 and DRA3 registers, set the SVP, VCT registers with the LDC instruction. DMA Mode Register 0 DMA 0 Transfer Count Register DMA 0 Transfer Count Reload Register(1) DMA 0 Memory Address Register DMA 0 SFR Address Register DMA 0 Memory Address Reload Register(1) DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMAC-Associated Registers When Three or More DMAC Channels are Used, the High-Speed Interrupt Register is Used as DMAC Registers DMA2 Transfer Count Register DMA2 Transfer Count Reload Register(1) DMA2 Memory Address Register DMA2 SFR Address Register DCT2 (R0) DCT3 (R1) DRC2 (R2) DRC3 (R3) DMA2 (A0) DMA3 (A1) DSA2 (SB) DSA3 (FB) When using DMA2 and DMA3, use the CPU registers shown in parentheses (). When Three or More DMAC Channels are Used, the Register Bank 1 is Used as DMAC Registers DMA3 Transfer Count Register DMA3 Transfer Count Reload Register(1) DMA3 Memory Address Register DMA3 SFR Address Register SVF DMA2 Memory Address Reload Register(1)DRA2 (SVP) DRA3 (VCT) Flag Save Register DMA3 Memory Address Reload Register(1) DMA Mode Register 1 DMA 1 Transfer Count Register DMA 1 Transfer Count Reload Register(1) DMA 1 Memory Address Register DMA 1 SFR Address Register DMA 1 Memory Address Reload Register(1) NOTES: 1. Registers are used for repeat transter, not for single transfer. Figure 12.1 Register Mapping for DMAC

Page 115 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. There- fore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged. Table 12.1 DMAC Specifications Item Specification Channels 4 channels (cycle-steal method) Transfer Memory Space • From a desired address in a 16M-byte space to a fixed address in a 16M-byte space

From a fixed address in a 16M-byte space to a desired address in a 16M-byte space Maximum Bytes Transferred 128K bytes (when a 16-bit data is transferred) or 64K bytes (when an 8- bit data is transferred) DMA Request Factors(1) Falling edge or both edges of input signals to the INT0 to INT3 pins Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 to UART4 transmit and receive interrupt requests A/D conversion interrupt request Intelligent I/O interrupt request CAN interrupt request Software trigger Channel Priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority) Transfer Unit 8 bits, 16 bits Destination Address Forward/fixed (forward and fixed directions cannot be specified when specifying source and destination addresses simultaneously) Transfer Mode Single TransferTransfer is completed when the DCTi register (i = 0 to 3) is set to "000016" Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register is reloaded into the DCTi register and the DMA transfer is continued DMA Interrupt Request Generation TimingWhen the DCTi register changes "000116" to "000016" DMA Startup Single Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 to MD0 bits in the DMDj register (j = 0 to 1) are set to "012" (single transfer) Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 to MDi0 bits are set to "112" (re- peat transfer) DMA Stop Single Transfer DMA stops when the MDi1 to MDi0 bits are set to "002" (DMA disabled) or when the DCTi register is set to "000016" (0 DMA transfer) by DMA transfer or write Repeat TransferDMA stops when the MDi1 to MDi0 bits are set to "002" or when the DCTi register is set to "000016" and the DRCi register set to "000016" Reload Timing to the DCTi When the DCTi register is set to "000016" from "000116" in repeat trans- or DMAi Register fer mode DMA Transfer Cycles Minimum 3 cycles between SFR and internal RAM NOTES: 1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.

Page 116 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M DMAi Request Factor Select Register (i=0 to 3) RW RW RW RW RW RW RW RW DSEL0 DSEL1 DSEL2 DMA Request Cause Select Bit(1) DSEL3 DSEL4 Software DMA Request Bit(2)DSR (b6) Nothing is assigned. When write, set "0". When read, its content is indeterminate. See Table 12.2 about DMiSL register (i = 0 to 3) function DRQ DMA Request Bit (2, 3) 0 : Not requested 1 : Requested NOTES: 1. Change the DSEL4 to DSEL0 bit settings while the MDi1 to MDi0 bits in the DMA0 or DMD1 register are set to "002" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the DSEL4 to DSEL0 bit settings are changed. e.g., MOV.B #083h, DMiSL ; Set timer A0 2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously. e.g., OR.B #0A0h, DMiSL 3. Do not set the DRQ bit to "0". Symbol Address After Reset DM0SL to DM3SL 0378 16, 037916, 037A16, 037B16 0X00 0000 2 FunctionBit NameBit Symbol When a software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, its content is always "0") b7 b6 b5 b4 b3 b2 b1 b0 Figure 12.2 DM0SL to DM3SL Registers

Page 117 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M Setting Value DMA Request Cause b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 DMA0 Falling edge of INT0 Both edges of INT0 DMA1 DMA2 Falling edge of INT2 Both edges of INT2 DMA3 Falling edge of INT3(1) Both edges of INT3(1) Software Trigger Timer A0 Interrupt Request Timer A1 Interrupt Request Timer A2 Interrupt Request Timer A3 Interrupt Request Timer A4 Interrupt Request Timer B0 Interrupt Request Timer B1 Interrupt Request Timer B2 Interrupt Request Timer B3 Interrupt Request Timer B4 Interrupt Request Timer B5 Interrupt Request UART0 Transmit Interrupt Request UART0 Receive or ACK Interrupt Request (3) UART1 Transmit Interrupt Request UART1 Receive or ACK Interrupt Request(3) UART2 Transmit Interrupt Request UART2 Receive or ACK Interrupt Request(3) UART3 Transmit Interrupt Request UART3 Receive or ACK Interrupt Request(3) UART4 Transmit Interrupt Request UART4 Receive or ACK Interrupt Request(3) Falling edge of INT1 Both edges of INT1 A/D0 Interrupt Request Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request Intelligent I/O Interrupt 5 Request Intelligent I/O Interrupt 6 Request A/D1 Interrupt Request Intelligent I/O Interrupt 7 Request Intelligent I/O Interrupt 8 Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request(5) Intelligent I/O Interrupt 11 Request(6) Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request A/D0 Interrupt request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request Intelligent I/O Interrupt 5 Request Intelligent I/O Interrupt 6 Request Intelligent I/O Interrupt 7 Request Intelligent I/O Interrupt 8 Request A/D1 Interrupt Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request(5) Intelligent I/O Interrupt 11 Request(6) Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request (Note 2) (Note 2) NOTES: 1. If the INT3 pin is used as data bus in the memory expansion mode or microprocessor mode, a DMA3 interrupt request cannot be generated by an input signal to the INT3 pin. 2. The falling edge and both edges of input signal into the INTj pin (j = 0 to 3) cause a DMA request. The INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa. 3. The UkSMR register and UkSMR2 register (k = 0 to 4) switch the UARTj receive to ACK or ACK to UARTk receive. 4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request. 5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request. 6. The same setting is used to generate an intelligent I/O interrupt 11 request and a CAN interrupt 2 request. Table 12.2 DMiSL Register (i = 0 to 3) Function

Page 118 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M DMA Mode Register 0(1) RW RW RW RW RW RW RW RW RW MD00 MD01 BW0 Channel 0 Transfer Unit Select Bit Channel 0 Transfer Mode Select Bit RW0 MD10 Channel 0 Transfer Direction Select Bit Channel 1 Transfer Mode Select Bit Channel 1 Transfer Unit Select Bit 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : 8 bits 1 : 16 bits 0 : 8 bits 1 : 16 bits MD11 BW1 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer RW1 Channel 1 Transfer Direction Select Bit NOTES: 1. Use the LDC instruction to set the DMD0 register. Symbol Address After Reset DMD0 CPU Internal Register 00 16 FunctionBit NameBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b1 b0 Figure 12.3 DMD0 Register, DMD1 Register DMA Mode Register 1(1) RW RW RW RW RW RW RW RW RW MD20 MD21 BW2 Channel 2 Transfer Unit Select Bit Channel 2 Transfer Mode Select Bit RW2 MD30 Channel 2 Transfer Direction Select Bit Channel 3 Transfer Mode Select Bit Channel 3 Transfer Unit Select Bit 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : 8 bits 1 : 16 bits 0 : 8 bits 1 : 16 bits MD31 BW3 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer RW3 Channel 3 Transfer Direction Select Bit NOTES: 1. Use the LDC instruction to set the DMD1 register. Symbol Address After Reset DMD1 CPU Internal Register 00 16 FunctionBit NameBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b1 b0

Page 119 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M Figure 12.4 DCT0 to DCT3 Registers and DRC0 to DRC3 Registers Function DMAi Transfer Count Register (i=0 to 3) Setting Range Symbol Address After Reset DCT0 (2) (CPU Internal Register) XXXX 16 DCT1 (2) (CPU Internal Register) XXXX 16 DCT2(bank1;R0)(3) (CPU Internal Register) 0000 16 DCT3(bank1;R1)(4) (CPU Internal Register) 0000 16 RW 000016 to FFFF16(1)Set the number of transfers RW NOTES: 1. When the DCTi register to "000016", no data transfer occurs regardless of a DMA request. 2. Use the LDC instruction to set the DCT0 and DCT1 registers. 3. To set the DCT2 register, set the B flag in the FLG register to "1" (register bank 1) and set R0 register. Use the MOV instruction to set the R0 register. 4. To set the DCT3 register, set the B flag to "1" and set R1 register. Use the MOV instruction to set the R1 register. b15 b8 b7 b0 Function DMAi Transfer Count Reload Register (i=0 to 3) Setting Range Symbol Address After Reset DRC0 (1) (CPU Internal Register) XXXX 16 DRC1 (1) (CPU Internal Register) XXXX 16 DRC2(bank1;R2)(2) (CPU Internal Register) 0000 16 DRC3(bank1;R3)(3) (CPU Internal Register) 0000 16 RW 000016 to FFFF16Set the number of transfers RW NOTES: 1. Use the LDC instruction to set the DRC0 and DRC1 registers. 2. To set the DRC2 register, set the B flag in the FLG register to "1" (register bank 1) and set R2 register. Use the MOV instruction to set the R2 register. 3. To set the DRC3 register, set the B flag to "1" and set R3 register. Use the MOV instruction to set the R3 register. b15 b8 b7 b0

Page 120 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M Figure 12.5 DMA0 to DMA3 Registers, DSA0 to DSA3 Registers and DRA0 to DRA3 Registers Function DMAi Memory Address Register (i=0 to 3) Setting Range Symbol Address After Reset DMA0 (2) (CPU Internal Register) XXXXXX 16 DMA1 (2) (CPU Internal Register) XXXXXX 16 DMA2(bank1;A0)(3) (CPU Internal Register) 000000 16 DMA3(bank1;A1)(4) (CPU Internal Register) 000000 16 RW 00000016 to FFFFFF16 (16-Mbyte space) Set a source memory address or destination memory address(1) RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a destination address is selected. When the RWk bit is set to "1" (memory to fixed address), a source address is selected. 2. Use the LDC instruction to set the DMA0 and DMA1 registers. 3. To set the DMA2 register, set the B flag in the FLG register to "1" (register bank 1) and set A0 register. Use the MOV instruction to set the A0 register. 4. To set the DMA3 register, set the B flag to "1" and set A1 register. Use the MOV instruction to set the 1 register. b23 b16 b8 b7 b0b15 Function DMAi SFR Address Register (i=0 to 3) Setting Range Symbol Address After Reset DSA0 (2) (CPU Internal Register) XXXXXX 16 DSA1 (2) (CPU Internal Register) XXXXXX 16 DSA2(bank1;SB)(3) (CPU Internal Register) 000000 16 DSA3(bank1;FB)(4) (CPU Internal Register) 000000 16 RW 00000016 to FFFFFF16 (16-Mbyte space) Set a source fixed address or destination fixed address(1) RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1) is set to "0" (fixed address to memory), a source address is selected. When the RWk bit is set to "1" (memory to fixed address), a destination address is selected. 2. Use the LDC instruction to set the DSA0 and DSA1 registers. 3. To set the DSA2 register, set the B flag in the FLG register to "1" (register bank 1) and the set the SB register. Use the LDC instruction to set the SB register. 4. To set the DSA3 register, set the B flag to "1" and set the FB register. Use the LDC instruction to set the FB register. b23 b16 b8 b7 b0b15 Function DMAi Memory Address Reload Register(1) (i=0 to 3) Setting Range Symbol Address After Reset DRA0 (CPU Internal Register) XXXXXX 16 DRA1 (CPU Internal Register) XXXXXX 16 DRA2(SVP) (2) (CPU Internal Register) XXXXXX 16 DRA3(VCT) (3) (CPU Internal Register) XXXXXX 16 RW 00000016 to FFFFFF16 (16-Mbyte space) Set a source memory address or destination memory address RW NOTES: 1. Use the LDC instruction to set the these registers. 2. To set the DRA2 register, set the SVP register. 3. To set the DRA3 register, set the VCT register. b23 b16 b8 b7 b0b15

Page 121 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M

12.1 Transfer Cycles

Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus cycle to write data to a memory space or the SFR area (destination write). The number of read and write bus cycles depends on source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the DS register. Software wait state insertion and the RDY signal make a bus cycle longer.

12.1.1 Effect of Source and Destination Addresses

When a 16-bit data is transferred with a 16-bit data bus, and the source address starts with an odd address, source read cycle has one more bus cycle compared to a source address starting with an even address. When a 16-bit data is transferred with a 16-bit data bus and the destination address starts with an odd address, destination write cycle has one more bus cycle compared to a destination address starting with an even address.

12.1.2 Effect of the DS Register

In an external space in memory expansion or microprocessor mode, transfer cycle varies depending on the data bus used at the source and destination addresses. See Figure 7.1 for details about the DS register. (1) When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing both source address and destination address, is used to transfer a 16-bit data, 8-bit data is transferred twice. Therefore, two bus cycles are required to read the data and another two bus cycles to write the data. (2) When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing source address, and a 16-bit data bus, accessing destination address, are used to transfer a 16-bit data, 8- bit data is read twice but is written once as 16-bit data. Therefore, two bus cycles are required for reading and one bus cycle is for writing. (3) When a 16-bit data bus, accessing source address, and an 8-bit data bus, accessing destination address, are used to transfer a 16-bit data, 16-bit data is read once and 8-bit data is written twice. Therefore, one bus cycle is required for reading and two bus cycles is for writing.

12.1.3 Effect of Software Wait State

When the SFR area or memory space with software wait states is accessed, the number of cycles is incremented by software wait states. Figure 12.6 shows an example of a transfer cycle for the source-read bus cycle. In Figure 12.6, the number of source-read bus cycles is illustrated under different conditions, provided that the destination address is an address of an external space with the destination write bus cycle as two BCLK cycles (=one bus cycle). In effect, the destination-write bus cycle is also affected by each condition and the transfer cycles change accordingly. To calculate a transfer cycle, apply respective conditions to both destination- write bus cycle and source-read bus cycle. As shown in example (2) of Figure 12.6, when an 8-bit data bus, accessing both source and destination addresses, is used to transfer a 16-bit data, two bus cycles each are required for the source-read bus cycle and destination-write bus cycle.

12.1.4 Effect of RDY Signal

In memory expansion or microprocessor mode, the RDY signal affects a bus cycle of source address or destination address is allocated address in an external space. Refer to 7.2.6 RDY Signal for details.

Page 122 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M (1) When 8-bit data is transferred or when 16-bit data is transferred from an even source address by a 16-bit data bus BCLK Address Bus RD Signal WR Signal Data Bus (3) When one wait state is inserted into the source-read bus cycle under the conditions in (1) (2) When 16-bit data is transferred from an odd source address or when 16-bit data is transferred from source by an 8-bit data bus BCLK Address Bus RD Signal WR Signal Data Bus CPU Use CPU Use CPU Use CPU UseSource Source Source + 1 Source + 1 (4) When one wait state is inserted into the source-read bus cycle under the conditions in (2) NOTES: 1. The above applies when the destination-write bus cycle is 2 BCLK cycles (1 bus cycle). However, if the destination-write bus cycle is placed under these conditions, it will change to the same timing as the source-read bus cycle illustrated above. Destination Destination BCLK Address Bus RD Signal WR Signal Data bus CPU Use CPU Use CPU Use CPU UseSource Source Destination Destination CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use CPU Use CPU Use CPU UseSource Source Source + 1 Source + 1 Destination Destination CPU Use CPU UseSource Destination CPU Use CPU UseSource Destination BCLK Figure 12.6 Transfer Cycle Examples with the Source-Read Bus Cycle

Page 123 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M

12.2 DMAC Transfer Cycles

The number of DMAC transfer cycle can be calculated as follows. Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number of DMAC transfer cycles. Table 12.4 lists coefficient j, k. Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k Table 12.3 DMAC Transfer Cycles Single-Chip Mode Memory Expansion Mode Microprocessor ModeTransfer Unit Bus Width Access Address Read Write Read Write Cycle Cycle Cycle Cycle 16-bit Even 1 1 1 1 8-bit transfers Odd 1 1 1 1 (BWi bit in the DMDp 8-bit Even —— 11 register = 0) Odd —— 11 16-bit Even 1 1 1 1 16-bit transfers Odd 2 2 2 2 (BWi bit = 1) 8-bit Even —— 22 Odd —— 22 i= 0 to 3, p = 0 to 1 Table 12.4 Coefficient j, k

12.3 Channel Priority and DMA Transfer Timing

When multiple DMA requests are generated in the same sampling period, between the falling edge of the CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested) simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3. Figure 12.7 shows an example of the DMA transfer by external factors. In Figure 12.7, the DMA0 request having the highest priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts. After one DMA1 transfer is completed, the privilege is again returned to the CPU. In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is completed. ecapSlanretnIe capSlanretxE roMORlanretnI MARlanretnI etatstiawonhtiw roMORlanretnI htiwMARlanretnI etatstiawa RFS aerA etarapeS onhtiwsuB etatstiaw etarapeS 1htiwsuB etatstiaw etarapeS 2htiwsuB setatstiaw etarapeS 3htiwsuB setatstiaw dexelpitluM 2htiwsuB setatstiaw dexelpitluM 3htiwsuB setatstiaw 1=j 1=k 2=j 2=k 2=j 2=k 1=j 2=k 2=j 2=k 3=j 3=k 4=j 4=k 3=j 3=k 4=j 4=k

Page 124 884fo6002,13.naJ13.1.veR 1310-4300B90JER 12. DMAC)T38/C23M,38/C23M(puorG38/C23M BCLK /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLinesDMA0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLinesDMA1 DRQ Bit in DMA0 Register DRQ Bit in DMA1 Register /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines CPU INT0 INT1 When DMA transfer request signals are applied to INT0 and INT1 simultaneously and a DMA transfer with minimum cycle occurs. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bus priviledge acquired /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Figure 12.7 DMA Transfer by External Factors

Page 125 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M 13. DMAC II The DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which transfers the sum of two data added by an interrupt request from any peripheral functions. Table 13.1 lists specifications of the DMAC II. Table 13.1 DMAC II Specifications Item Specification DMAC II Request Factor Interrupt requests generated by all peripheral functions when the ILVL2 to ILVL0 bits are set to "1112" Transfer Data • Data in memory is transferred to memory (memory-to-memory transfer)

Immediate data is transferred to memory (immediate data transfer)
Data in memory (or immediate data) + data in memory are transferred to memory (calculation transfer) Transfer Block 8 bits or 16 bits Transfer Space 64-Kbyte space in addresses 00000 16 to 0FFFF16(1, 2) Transfer Direction Fixed or forward address Selected separately for each source address and destination address Transfer Mode Single transfer, burst transfer Chained Transfer FunctionParameters (transfer count, transfer address and other information) are switched when transfer counter reaches zero End-of-Transfer Interrupt Interrupt occurs when a transfer counter reaches zero Multiple Transfer FunctionMultiple data can be transferred by a generated request for one DMA II transfer NOTES: 1. When transferring a 16-bit data to destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16. 2. The actual space where transfer can occur is limited due to internal RAM capacity.

13.1 DMAC II Settings

DMAC II can be made available by setting up the following registers and tables.

RLVL register
DMAC II Index
Interrupt control register of the peripheral function causing a DMAC II request
The relocatable vector table of the peripheral function causing a DMAC II request
IRLT bit in the IIOiIE register (i = 0 to 11) if using the intelligent I/O or CAN interrupt Refer to 10. Interrupts for details on the IIOiIE register

13.1.1 RLVL Register

When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), the DMAC II is activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the inter- rupt control register set to "111 2" (level 7). Figure 13.1 shows the RLVL register.

Page 126 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M Exit Priority Register After Reset XXXX 0000 2 Address 009F Symbol RLVL RW RW RW RW RW RW RLVL0 RLVL1 RLVL2 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit(1) FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt DMA II (b4) (b7 - b6) DMAC II Select Bit (4) 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMAC II transfer (3) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. 2. When the FSIT bit is set to "1", interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to interrupt priority level 7 and the DMA II bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. After reset, the DMA II bit is indeterminate. When using an interrupt, set the interrupt control register after setting the DMA II bit to "0". Figure 13.1 RLVL Register

Page 127 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M Transfer Mode (MOD) Transfer Counter (COUNT) Transfer Source Address (or immediate data) (SADR) Operation Address(1) (OADR) Transfer Destination Address (DADR) Chained Transfer Address (2) (CADR0) Chained Transfer Address(2) (CADR1) End-of-Transfer Interrupt Address(3) (IADR0) End-of-Transfer Interrupt Address(3) (IADR1) 16 bits DMAC II Index Starting Address (BASE) BASE + 2 BASE + 4 BASE + 6 BASE + 8 BASE + 10 BASE + 14 BASE + 16 BASE + 12 Transfer Mode (MOD) Transfer Counter (COUNT) Transfer Source Address (SADR1) Transfer Destination Address (DADR1) Transfer Source Address (SADR2) Transfer Destination Address (DADR2) Transfer Source Address (SADR7) Transfer Destination Address (DADR7) 16 bits BASE BASE + 2 BASE + 4 BASE + 6 BASE + 8 BASE + 10 BASE + 28 BASE + 30 Memory-to-Memory Transfer, Immediate Transfer, Calculation Transfer Multiple Transfer NOTES: 1. This data is not required when not using the calculation transfer function. 2. This data is not required when not using the chained transfer function. 3. This data is not required when not using the end-of-transfer interrupt. The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation transfer function, set destination address to BASE+6. (See Table 13.2) Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request.

13.1.2 DMAC II Index

The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination ad- dress, chained transfer address, and end-of-transfer interrupt address. This DMAC II index must be located on the RAM area. Figure 13.2 shows a configuration of the DMAC II index. Table 13.2 lists a configuration of the DMAC II index in transfer mode. Figure 13.2 DMAC II Index The followings are details of the DMAC II index. Set these parameters in the specified order listed in Table 13.2, according to DMAC II transfer mode.

Transfer mode (MOD) Two-byte data is required to set transfer mode. Figure 13.3 shows a configuration for transfer mode.
Transfer counter (COUNT) Two-byte data is required to set the number of transfer.
Transfer source address (SADR) Two-byte data is required to set the source memory address or immediate data.
Operation address (OADR) Two-byte data is required to set a memory address to be calculated. Set this data only when using the calculation transfer function.
Transfer destination address (DADR) Two-byte data is required to set the destination memory address.
Chained transfer address (CADR) Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set this data only when using the chained transfer function.
End-of-transfer interrupt address (IADR) Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this data only when using the end-of-transfer interrupt.

Page 128 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M Memory-to-Memory Transfer /Immediate Data Transfer Calculation Transfer Multiple Transfer Chained Transfer End-of-Transfer Interrupt Not Used Not Used Not Used Not UsedUsed Not Used Not Used Not Used Used Used Not Used Used Used Used Not Available Not Available Used Used DMAC II Index COUNT MOD SADR DADR COUNT MOD SADR DADR CADR0 CADR1 COUNT MOD SADR OADROADR OADR DADR IADR0 IADR1 COUNT MOD SADR DADR IADR0 IADR1 COUNT MOD SADR DADR CADR0 CADR1 IADR0 IADR1 OADR 8 bytes 12 bytes COUNT MOD SADR DADR COUNT MOD SADR DADR CADR0 CADR1 10 bytes 14 bytes 12 bytes 14 bytes 18 bytes COUNT MOD SADR DADR CADR0 CADR1 IADR0 IADR1 16 bytes COUNT MOD SADR1 DADR1 SADRi DADRi i=1 to 7 Max 32 bytes (when i=7) Function (MULT=0) Function (MULT=1) Transfer Mode (MOD)(1) RW RW RW RW RW RW RW RW RW RW SIZE IMM UPDS Transfer Unit Select Bit UPDD INTE/ CNT2 (2) Transfer Destination Direction Select Bit 0: Fixed address 1: Forward address 0: Single transfer 1: Burst transfer Calculation Transfer Function Select Bit 0: Not used 1: Used 0: 8 bits 1: 16 bits BRST/ CNT1 (2) OPER/ CNT0 (2) CHAIN Transfer Data Select Bit Transfer Source D irection Select Bit Burst Transfer Select Bit End-of-Transfer Interrupt Select Bit Chained Transfer Select Bit 0: Immediate data 1: Memory Set to "1" Set to "0" MULT (b14 - b8) Multiple Transfer Select Bit 0: Multiple transfer not used 1: Use multiple transfer 0: Fixed address 1: Forward address 0: Interrupt not used 1: Use interrupt 0: Chained transfer not used 1: Use chained transfer b6 b5 b4 0 0 0: Do not set to this value 0 0 1: Once 0 1 0: Twice 1 1 0: 6 times 1 1 1: 7 times Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit NameBit Symbol NOTES: 1. MOD must be located on the RAM. 2. When the MULT bit is set to "0" (no multiple transfer), bits 4 to 6 becomes the OPER, BRST, INTE bits. When the MULT bit is set to "1" (multiple transfer), bits 4 to 6 becomes the CNT0 to CNT2 bits. b7 b0b15 b8 Table 13.2 DMAC II Index Configuration in Transfer Mode Figure 13.3 MOD

Page 129 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M

13.1.3 Interrupt Control Register for the Peripheral Function

For the peripheral function interrupt activating a DMAC II request, set the ILVL2 to ILVL0 bits to "1112" (level 7).

13.1.4 Relocatable Vector Table for the Peripheral Function

Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt activating a DMAC II request. When using the chained transfer, the relocatable vector table must be located in the RAM.

13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 11)

When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE register of the interrupt to "0".

13.2 DMAC II Performance

The DMAC II function is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II request is activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "1112" (level 7). These peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral function interrupt cannot be used. When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "111 2" (level 7), the DMAC II is activated regardless of what state the I flag and IPL is in.

13.3 Transfer Data

The DMAC II transfers 8-bit or 16-bit data.

Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space (Addresses 0000016 to 0FFFF16) to another desired memory location in the same space.
Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space.
Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired memory location in a 64K-byte space. When a 16-bit data is transferred to the destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16 .

13.3.1 Memory-to-Memory Transfer

Data transfer between any two memory locations can be:

a transfer from a fixed address to another fixed address
a transfer from a fixed address to a relocatable address
a transfer from a relocatable address to a fixed address
a transfer from a relocatable address to another relocatable address When a relocatable address is selected, the DMAC II increments address, after a transfer, for the next transfer. In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer address is incremented by two. When a source or destination address exceeds address 0FFFF 16 as a result of address incrementation, the source or destination address returns to address 00000016 and continues incrementation. Maintain source and destination address at address 0FFFF16 or below.

Page 130 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M

13.3.2 Immediate Data Transfer

The DMAC II transfers immediate data to a desired memory location. A fixed or relocatable address can be selected as the destination address. Store the immediate data into SADR. To transfer an 8-bit imme- diate data, write the data in the low-order byte of SADR (high-order byte is ignored).

13.3.3 Calculation Transfer

After two memory data, or an immediate data and memory data are added together, the calculated result is transferred to a desired memory location. SADR must have one memory location address to be calcu- lated or immediate data. OADR must have the other memory location address to be calculated. Fixed or relocatable address can be selected as source and destination addresses when using a memory + memory calculation transfer. If the transfer source address is relocatable, the operation address also becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address when using an immediate data + memory calculation transfer.

13.4 Transfer Modes

In DMAC II, single and burst transfers are available. The BRST bit in MOD selects transfer method, either the single transfer or burst transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set to "0000 16". All interrupts are ignored while transfer is in progress.

13.4.1 Single Transfer

For every transfer request factor, the DMAC II transfers one transfer unit of 8-bit or 16-bit data once. When the source or destination address is relocatable, the DMAC II increments the address, after a transfer, for the next transfer. COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the inter- rupt is acknowledged when COUNT reaches "0".

13.4.2 Burst Transfer

For every transfer request factor, the DMAC II continuously transfers data the number of times deter- mined by COUNT. The DMAC II decrements COUNT every time a transfer occurs. The burst transfer ends when COUNT reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer ends if using the end-of-transfer interrupt. All interrupts are ignored while the burst transfer is in progress.

13.4.3 Multiple Transfer

The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memory- to-memory transfer. One transfer request factor initiates multiple transfers. The CNT2 to CNT0 bits in MOD selects the number of transfers from "001 2" (once) to "1112" (7 times). Do not set the CNT2 to CNT0 bits to "0002". The transfer source and destination addresses for each transfer must be allocated alternately to ad- dresses following MOD and COUNT. When the multiple transfer is selected, the calculation transfer, burst transfer, end-of-transfer interrupt and chained transfer cannot be used.

Page 131 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M

13.4.4 Chained Transfer

The CHAIN bit in MOD selects the chained transfer. The following process initiates the chained transfer. (1) Transfer, caused by a transfer request factor, occurs according to the content of the DMAC II index. The vectors of the request factor indicates the address where the DMAC II index is allocated. For each request, the BRST bit in MOD selects either single or burst transfer. (2) When COUNT reaches "0", the contents of CADR1 to CADR0 are written to the vector of the request factor. When the INTE bit in the MOD is set to "1," the end-of-transfer interrupt is generated simulta- neously. (3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the DMAC II index indicated by the vector rewritten in (2). Figure 13.4 shows the relocatable vector and DMACII index of when the chained transfer is in progress. For the chained transfer, the relocatable vector table must be located in the RAM. RAM Relocatable vector INTB DMAC II Index(1) DMAC II Index(2) BASE(1) BASE(2) BASE(2) BASE(3) (CADR1 to CADR0) (CADR1 to CADR0) Peripheral I/O interrupt vector causing DMAC II request Default value of DMAC II is BASE(1). The above vector is rewritten to BASE(2) when a transfer is completed. The above vector is rewritten to BASE(3) when a transfer is completed. Starts at BASE(2) when next request conditions are met. Transferred according to the DMAC II Index.Figure 13.4 Relocatable Vector and DMAC II Index

13.4.5 End-of-Transfer Interrupt

The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer interrupt service routine in the IADR1 to IADR0 bits. The end-of-transfer interrupt is generated when COUNT reaches "0."

Page 132 884fo6002,13.naJ13.1.veR 1310-4300B90JER 13. DMACII)T38/C23M,38/C23M(puorG38/C23M a=-1 b=0 c=1 d=0 e=0 m=1 First DMAC II transfer t=6+26x1+4x1=36 cycles Second DMAC II transfer t=6+26x1+4x0=32 cycles Transfer counter = 2 Decrement a transfer counter Transfer counter = 1 Transfer counter = 1 Program ProgramDMAC II transfer (First time) DMAC II transfer (Second time) 7 cycles Processing the end-of-transfer interrupt DMAC II transfer request Decrement a transfer counter Transfer counter = 0 32 cycles36 cycles DMAC II transfer request If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address, single transfer and double transfer:

13.5 Execution Time

DMAC II execution cycle is calculated by the following equations: Multiple transfers: t = 21 + (11 + b + c) x k cycles Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles a: If IMM = 0 (source of transfer is immediate data), a = 0; if IMM = 1 (source of transfer is memory), a = –1 b: If UPDS = 1 (source transfer address is a relocatable address), b = 0; if UPDS = 0 (source transfer address is a fixed address), b = 1 c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0; if UPDD = 0 (destination transfer address is a fixed address), c = 1 d: If OPER = 0 (calculation function is not selected), d = 0; if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed address memory), d = 7; if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address memory), d = 8 e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4 m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in COUNT n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1 k: Number of transfers set in the CNT2 to CNT0 bits The equations above are approximations. The number of cycles may change with CPU state, bus wait state, and DMAC II index allocation. The first instruction from the end-of-transfer interrupt service routine is executed in the 8th cycle after the DMAC II transfer is completed. Figure 13.5 Transfer Cycle When an interrupt request which acts as a DMAC II transfer request factor and another interrupt request with higher priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher priority takes precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt sequence has been completed.

Page 133 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer)T38/C23M,38/C23M(puorG38/C23M 14. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each timer operates independently. The count source for each timer is the clock for timer operations including counting and reloading, etc. Figures 14.1 and 14.2 show block diagrams of timer A and timer B configuration. CST 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter mode TA0 IN TA1 IN TA2 IN TA3 IN TA4 IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 f1 f8 f2n fC32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter Main clock, PLL clock or On-chip oscillator clock 1/2n (Note 1) TCK1 to TCK0 00: Timer mode 10: One-shot tiemr mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter mode 01: Event counter mode 01: Event counter mode 01: Event counter mode TCK1 to TCK0 TCK1 to TCK0 TCK1 to TCK0 TCK1 to TCK0 TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 TA0TGH to TA0TGL Timer B2 overflow or underflow CST: Bit in TCSPR register TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register TAiGH to TAiGL: Bits in ONSF register or TRGSR register (i=1 to 4) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). f TA1TGH to TA1TGL TA2TGH to TA2TGL TA3TGH to TA3TGL TA4TGH to TA4TGL TMOD1 to TMOD0 TMOD1 to TMOD0 1/32 fC32XCIN Set the CPSR bit in the CPSRF register to "1" Reset Clock prescaler Figure 14.1 Timer A Configuration

Page 134 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer)T38/C23M,38/C23M(puorG38/C23M TB0 IN TB1 IN TB2 IN Timer B0 f1 f8 f2n fC32 Timer B0 interrupt Noise filter Timer B2 overflow or underflow (to a count source of the timer A) TB3 IN TB4 IN TB5 IN Timer B3 interrupt Timer B1 interrupt Timer B2 interrupt Timer B4 interrupt Timer B5 interrupt 1/2n Main clock, PLL clock or On-chip clock CST (Note 1) TCK1 to TCK0 Timer B1 TCK1 to TCK0 Noise filter Timer B2 TCK1 to TCK0 Noise filter Timer B3 TCK1 to TCK0 Noise filter TCK1 to TCK0 Timer B4Noise filter TCK1 to TCK0 Timer B5Noise filter 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 TMOD1 to TMOD0 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 CST : Bit in TCSPR register TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TBiMR register (i=0 to 5) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). f2n TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 1/32 fC32XCIN Reset Clock prescaler Set the CPSR bit in the CPSRF register to "1" Figure 14.2 Timer B Configuration

Page 135 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M

14.1 Timer A

Figure 14.3 shows a block diagram of the timer A. Figures 14.4 to 14.7 show registers associated with the timer A. The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the same function. The TMOD1 to TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is used.

Timer mode: The timer counts an internal count source.
Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers.
One-shot timer mode: The timer outputs one valid pulse until the counter reaches "0000 16".
Pulse width modulation mode: The timer continuously outputs desired pulse widths. Table 14.1 lists TAiOUT pin settings when used as an output. Table 14.2 lists TAiIN and TAiOUT pin settings when used as an input. TAiS Increment / decrement TAi Addresses TAj TAk Timer A0 034716 034616 Timer A4 Timer A1 Timer A1 034916 034816 Timer A0 Timer A2 Timer A2 034B16 034A16 Timer A1 Timer A3 Timer A3 034D16 034C 16 Timer A2 Timer A4 Timer A4 034F16 034E16 Timer A3 Timer A0 Select Count Source
Timer(gate function):TMOD1 to TMOD0=00, MR2=1
Timer :TMOD1 to TMOD0=00, MR2=0
One-Shot Timer :TMOD1 to TMOD0=10
Pulse Width Modulation:TMOD1 to TMOD0=11 f2n(1) TAiIN
Event counter:TMOD1 to TMOD0=01 fC32 Select clock TAj Overflow(2) Pulse Output Toggle Flip Flop TAiOUT Always decrement except in event counter mode 8 low- order bits High-Order Bits of Data Bus Reload Register Counter Low-Order Bits of Data Bus /LiteDiagLines /LiteDiagLines TAiUD Decrement TAk Overflow(2) Polarity Selector TCK1 to TCK0 TB2 Overflow(2) TAiTGH to TAiTGL MR2 TMOD1 to TMOD0 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. Overflow or underflow TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR1 : Bits in TAiMR register TAiTGH to TAiTGL: Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4 TAiS: Bits in the TABSR register TAiUD: Bits in the UDF register TMOD1 to TMOD0, MR2 i=0 to 4 j=i-1, except j=4 if i=0 k=i+1, except k=0 if i=4 8 high- order bits Figure 14.3 Timer A Block Diagram

Page 136 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Timer Ai Register (i=0 to 4)(1) Symbol Address After Reset TA0 to TA2 034716-034616, 034916-034816, 034B16-034A16 Indeterminate TA3, TA4 034D 16-034C16, 034F16-034E16 Indeterminate RW RW RW WO WO WO Timer Mode 0000 16 to FFFF16 000016 to FFFF16 000016 to FFFF16(3) 000016 to FFFE16(3) 0016 to FE16(3) (High-order address bits) 0016 to FF16(3) (Low-order address bits) Event Counter Mode (2) One-Shot Timer Mode (4) Pulse Width Modulation Mode(5) (16-Bit PWM) Pulse Width Modulation Mode (5) (8-Bit PWM) Function Setting RangeMode If setting value is n, count source is divided by n+1. If setting value is n, count source is divided by FFFF 16 - n+1 when the counter is incremented and by n+1 when the counter is decremented. If count source frequency is fj and setting value of the TAi register is n, PWM cycle: (2 16-1) / fj "H" width of PWM pulse: n / fj If count source frequency is fj, setting value of high-order bits in the TAi register is n and setting value of low-order bits in the TAi register is m , PWM cycle: (2 8-1)x(m+1) / fj "H" width of PWM pulse: (m+1)n / fj If setting value is n, count source is divided by n, then stops. b15 b8 b7 b0 fj : f1, f8, f2n, fC32 NOTES: 1. Use 16-bit data for reading and writing. 2. The TAi register counts how many pulses are input externally or how many times another timer counter overflows and underflows. 3. Use the MOV instruction to set the TAi register. 4. When the TAi register is set to "0000 16", the counter does not start and the timer Ai interrupt request is not generated. 5. When the TAi register is set to "000016", the pulse width modulator does not operate and the TAiOUT pin is held "L". The TAi interrupt request is also not generated. The same situation occurs in 8-bit pulse width modulator mode if the 8 high-order bits in the TAi register are set to "00 16". Figure 14.4 TA0 to TA4 Registers

Page 137 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Figure 14.5 TA0MR to TA4MR Registers and TABSR Register Timer Ai Mode Register (i=0 to 4) Symbol Address After Reset TA0MR0 to TA4MR 0356 16, 035716, 035816, 035916, 035A16 0000 0X002 RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operation Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit Function varies depending on operation mode Function varies depending on operation mode 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode b1b0 Bit Name FunctionBit Symbol (b2) Nothing is assigned. When write, set to "0". b7 b6 b5 b4 b3 b2 b1 b0 Count Start Flag Symbol Address After Reset TABSR 0340 16 00 16 RW RW RW RW RW RW RW RW RW TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag 0 : Stops counting 1 : Starts counting TA2S Timer A2 Count Start Flag 0 : Stops counting 1 : Starts counting TA3S Timer A3 Count Start Flag 0 : Stops counting 1 : Starts counting TA4S Timer A4 Count Start Flag 0 : Stops counting 1 : Starts counting TB0S Timer B0 Count Start Flag 0 : Stops counting 1 : Starts counting TB1S Timer B1 Count Start Flag 0 : Stops counting 1 : Starts counting TB2S Timer B2 Count Start Flag 0 : Stops counting 1 : Starts counting Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0

Page 138 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Figure 14.6 UDF Register and ONSF Register Up/Down Flag(1) Symbol Address After Reset UDF 0344 16 00 16 RW RW WO WO WO TA0UD Timer A0 Up/Down Flag TA2P 0 : Decrement 1 : Increment (Note 2) RWTA1UD Timer A1 Up/Down Flag 0 : Decrement 1 : Increment (Note 2) RWTA2UD Timer A2 Up/Down Flag 0 : Decrement 1 : Increment (Note 2) RWTA3UD Timer A3 Up/Down Flag 0 : Decrement 1 : Increment (Note 2) RWTA4UD Timer A4 Up/Down Flag 0 : Decrement 1 : Increment (Note 2) (Note 3) (Note 3) (Note 3) Bit Name FunctionBit Symbol Timer A2 Two-Phase Pulse Signal Processing Function Select Bit 0 : Disables two-phase pulse signal processing function 1 : Enables two-phase pulse signal processing function TA3P Timer A3 Two-Phase Pulse Signal Processing Function Select Bit 0 : Disables two-phase pulse signal processing function 1 : Enables two-phase pulse signal processing function TA4P Timer A4 Two-Phase Pulse Signal Processing Function Select Bit 0 : Disables two-phase pulse signal processing function 1 : Enables two-phase pulse signal processing function NOTES: 1. Use the MOV instruction to set the UDF register. 2. This bit is enabled when the MR2 bit in the TAiMR register (i=0 to 4) is set to "0" (the UDF register causes increment/decrement switching) in event counter mode. 3. Set this bit to "0" when not using the two-phase pulse signal processing function. b7 b6 b5 b4 b3 b2 b1 b0 One-Shot Start Flag Symbol Address After Reset ONSF 0342 16 00 16 RW RWTA0OS Timer A0 One-Shot Start Flag RWTA1OS Timer A1 One-Shot Start Flag RWTA2OS Timer A2 One-Shot Start Flag RWTA3OS Timer A3 One-Shot Start Flag RWTA4OS Timer A4 One-Shot Start Flag 0 : In an idle state 1 : Starts the timer (Note 1) RWTAZIE Z-Phase Input Enable Bit0 : Disables Z-phase input 1 : Enables Z-phase input Bit Name FunctionBit Symbol RW RW TA0TGL TA0TGH Timer A0 Event/Trigger Select Bit 0 0 : Selects an input to the TA0IN pin 0 1 : Selects the TB2 overflows(2) 1 0 : Selects the TA4 overflows(2) 1 1 : Selects the TA1 overflows(2) b7 b6 NOTES: 1. When read, the bit is set to "0". 2. Overflow or underflow. 0 : In an idle state 1 : Starts the timer (Note 1) 0 : In an idle state 1 : Starts the timer (Note 1) 0 : In an idle state 1 : Starts the timer (Note 1) 0 : In an idle state 1 : Starts the timer (Note 1) b7 b6 b5 b4 b3 b2 b1 b0

Page 139 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Figure 14.7 TRGSR Register and TCSPR Register Trigger Select Register Symbol Address After Reset TRGSR 0343 16 00 16 RW RW RW RW RW RW RW Bit Name FunctionBit Symbol RW RW TA4TGL TA4TGH Timer A4 Event/Trigger Select Bit TA1TGL TA1TGH Timer A1 Event/Trigger Select Bit b1b0 TA2TGL TA2TGH Timer A2 Event/Trigger Select Bit TA3TGL TA3TGH Timer A3 Event/Trigger Select Bit NOTES: 1. Overflow or underflow. 0 0 : Selects an input to the TA1IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA0 overflows(1) 1 1 : Selects the TA2 overflows(1) b3 b2 0 0 : Selects an input to the TA2IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA1 overflows(1) 1 1 : Selects the TA3 overflows(1) b5 b4 0 0 : Selects an input to the TA3IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA2 overflows(1) 1 1 : Selects the TA4 overflows(1) b7 b6 0 0 : Selects an input to the TA4IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA3 overflows(1) 1 1 : Selects the TA0 overflows(1) b7 b6 b5 b4 b3 b2 b1 b0 Count Source Prescaler Register Symbol Address After Reset (2) TCSPR 035F 16 0XXX 0000 2 RW RW RW RW RW Bit Name FunctionBit Symbol RWCST Operation Enable Bit 0 : Stops divider 1 : Starts divider CNT0 CNT1 CNT2 CNT3 (b6 - b4) Divide Ratio Select Bit If setting value is n, f2n is the main clock, PLL clock or on-chip oscillator clock divided by 2n. Not divided if n=0. (1) NOTES: 1. Set the CST bit to "0" before the CNT3 to CNT0 bits are rewritten. 2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has performed. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0

Page 140 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Table 14.1 Pin Settings for Output from TAiOUT Pin (i=0 to 4) Pin Setting PS1, PS2 Registers PSL1, PSL2 Registers PSC Register P70/TA0OUT (1) PS1_0= 1 PSL1_0=1 PSC_0= 0 P72/TA1OUT PS1_2= 1 PSL1_2=1 PSC_2= 0 P74/TA2OUT PS1_4= 1 PSL1_4=0 PSC_4= 0 P76/TA3OUT PS1_6= 1 PSL1_6=1 PSC_6= 0 P80/TA4OUT PS2_0= 1 PSL2_0=0 – NOTES: 1. P70/TA0OUT is a port for the N-channel open drain output. PS1_0=0 Pin P70/TA0OUT P71/TA0IN P72/TA1OUT P73/TA1IN P74TA2 OUT PS1_1=0 PS1, PS2 Registers PS1_2=0 PS1_3=0 PS1_4=0 PD7, PD8 Registers PD7_0=0 PD7_1=0 PD7_2=0 PD7_3=0 PD7_4=0 Setting P75/TA2IN P76TA3 OUT P77/TA3IN P80/TA4OUT P81/TA4IN PS1_5=0 PS1_6=0 PS1_7=0 PS2_0=0 PS2_1=0 PD7_5=0 PD7_6=0 PD7_7=0 PD8_0=0 PD8_1=0 Table 14.2 Pin Settings for Input to TAiIN and TAiOUT Pins (i=0 to 4)

Page 141 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M

14.1.1 Timer Mode

In timer mode, the timer counts an internally generated count source (see Table 14.3). Figure 14.8 shows the TAiMR register (i=0 to 4) in timer mode. Table 14.3 Specifications in Timer Mode Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio 1/(n+1) n: setting value of the TAi register (i=0 to 4) 000016 to FFFF16 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition The TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter underflows TAiIN Pin Function Programmable I/O port or gate input TAiOUT Pin Function Programmable I/O port or pulse output Read from Timer The TAi register indicates counter value Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter

While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function • Gate function Input signal to the TAiIN pin determines whether the timer counter starts or stops counting
Pulse output function The polarity of the TAiOUT pin is inversed whenever the timer counter underflows NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 142 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M b7 b6 b5 b4 b3 b2 b1 b0 0 0 (b2) Timer Ai Mode Register (i=0 to 4) (Timer Mode) Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 0000 0X00 2 RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operation Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit Gate Function Select Bit Set to "0" in timer mode 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 0 0 : Timer mode b1 b0 Bit Name FunctionBit Symbol b7 b6 b4 b3 NOTES: 1. X can be set to either "0" or "1". 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

0 X : Gate function disabled

(1) (TAiIN pin is a programmable I/O pin) 1 0 : Timer counts only while the TAiIN pin is held "L" 1 1 : Timer counts only while the TAiIN pin is held "H" Nothing is assigned. When write, set to "0". Figure 14.8 TA0MR to TA4MR Registers

Page 143 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M

14.1.2 Event Counter Mode

In event counter mode, the timer counts how many external signals are applied or how many times another timer overflows and underflows. The timers A2, A3 and A4 can count externally generated two- phase signals. Table 14.4 lists specifications in event counter mode (when not handling a two-phase pulse signal). Table 14.5 lists specifications in event counter mode (when handling a two-phase pulse signal with the timer A2, A3 and A4). Figure 14.9 shows the TAiMR (i=0 to 4) register in event counter mode. Table 14.4 Specifications in Event Counter Mode (when not processing two-phase pulse signal) Item Specification Count Source • External signal applied to the TAiIN pin (i = 0 to 4) (valid edge can be selected by program)

Timer B2 overflow or underflow signal, timer Aj overflow or underflow signal (j=i-1, except j=4 if i=0) and timer Ak overflow or underflow signal (k=i+1, except k=0 if i=4) Counting Operation • External signal and program can determine whether the timer increments or decre- ments the counter
When the timer counter underflows or overflows, the content of the reload register is reloaded into the count register and counting resumes. When the free-running count function is selected, the timer counter continues running without reloading. Divide Ratio • 1/(FFFF16 - n + 1) for counter increment
1/(n + 1) for counter decrement n : setting value of the TAi register 000016 to FFFF16 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition The TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter overflows or underflows TAiIN Pin Function Programmable I/O port or count source input TAiOUT Pin Function Programmable I/O port, pulse output or input selecting a counter increment or decrement Read from Timer The TAi register indicates counter value Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function • Free-running count function Content of the reload register is not reloaded even if the timer counter overflows or underflows
Pulse output function The polarity of the TAi OUT pin is inversed whenever the timer counter overflows or underflows

Page 144 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Table 14.5 Specifications in Event Counter Mode (when processing two-phase pulse signal on timer A2, A3 and A4) Item Specification Count Source Two-phase pulse signal applied to the TAi IN pin, or TAiIN and TAiOUT pin (i = 2 to 4) Counting Operation • Two-phase pulse signal determines whether the timer increments or decrements a counter value

When the timer counter overflows or underflows, content of the reload register is reloaded into the count register and counting resumes. With the free-running count function, the timer counter continues running without reloading. Divide Ratio • 1/ (FFFF16 - n + 1) for counter increment
1/ (n + 1) for counter decrement n : setting value of the TAi register 000016 to FFFF16 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition The TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter overflows or underflows TAiIN Pin Function Two-phase pulse signal is applied TAiOUT Pin Function Two-phase pulse signal is applied Read from Timer The TAi register indicates counter value Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function(1) • Normal processing operation (the timer A2 and timer A3) While a high-level ("H") signal is applied to the TAjOUT pin (j = 2 or 3), the timer incre- ments a counter value on the rising edge of the TAjIN pin or decrements a counter value on the falling edge. TAjOUT Increment Decrement TAjIN Increment Increment Decrement Decremen t TAkOUT TAkIN Increment on all edgesDecrement on all edges NOTES: 1. Only timer A3 operation can be selected. The timer A2 is for the normal processing operation. The timer A4 is for the multiply-by-4 operation.
Multiply-by-4 processing operation (the timer A3 and timer A4) While an "H" signal is applied to the TAkOUT pin (k = 3 or 4) with the rising edge of the TAkIN pin, the timer counter increments a counter value on the rising and falling edges of the TAkOUT and TAkIN pins. While "H" is applied to the TAkOUT pin on the falling edge of the TAkIN pin, the timer decrements a counter value on the rising and falling edges of the TAkOUT and TAkIN pins.

Page 145 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Function (When not using two-phase pulse signal processing) Function (When using two-phase pulse signal processing) Timer Ai Mode Register (i=0 to 4) (Event Counter Mode) Bit NameBit Symbol Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 0000 0X00 16 RW 0 1 : Event counter mode(1) b1 b0 Operation Mode Select Bit Count Polarity Select Bit(2) Increment/Decrement Switching Cause Select Bit Count Operation Type Select Bit 0 : Normal processing operation 1 : Multiplied-by-4 processing operation 0 : Reloading 1 : Free running Set to "0" in event counter mode 0 : Counts falling edges of an external signal 1 : Counts rising edges of an external signal 0 : Setting of the UDF register 1 : Input signal to TAi OUT pin(3) Set to "0" Set to "1" Set to "0" TMOD0 TMOD1 (b2) MR1 MR2 MR3 TCK1 TCK0 RW RW RW RW RW RW RW RW Two-Phase Pulse Signal Processing Operation Select Bit (4,5) Nothing is assigned. When write, set to "0". b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The TAiTGH to TAiTGL bits in the ONSF or TRGSR register determine the count source in the event counter mode. 2. The MR1 bit is enabled only when counting how many times external signals are applied. 3. The timer decrements a counter value when "L" is applied to the TA iOUT pin and the timer increments a counter value when "H" is applied to the TAiOUT pin. 4. The TCK1 bit is enabled only in the TA3MR register. 5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (two- phase pulse signal processing function enabled) and the TAiTGH and TAiTGL bits to "00 2" (input to the TAjIN pin). 010 Figure 14.9 TA0MR to TA4MR Registers

Page 146 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Pulse width of one count source cycle or more is required NOTES: 1. When the rising edge of INT2 is selected. TA3 OUT (A-phase) Count source TA3 IN (B-phase) INT2 (1) (Z-phase) TA3 OUT (A-phase) Count source TA3 IN (B-phase) Timer counter is reset at this timing Counter value mm + 11 2 3 4 5 INT2 (1) (Z-phase) NOTES: 1. When the rising edge of INT2 is selected.

14.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing

The timer counter is reset to "0" by a Z-phase input when processing a two-phase pulse signal. This function can be used in timer A3 event counter mode, two-phase pulse signal processing, free- run type or multiply-by-4 processing. The Z-phase signal is applied to the INT2 pin. When the TAZIE bit in the ONSF register is set to "1" (Z-phase input enabled), the timer counter can be reset by a Z-phase input. To reset the timer counter by a Z-phase input, set the TA3 register to "0000 16" beforehand. Z-phase input is enabled when the edge of the signal applied to the INT2 pin is detected. The POL bit in the INT2IC register can determine edge polarity. The Z-phase must have a pulse width of one timer A3 count source cycle or more. Figure 14.10 shows two-phase pulses (A-phase and B-phase) and the Z-phase. Z-phase input resets the counter in the next count source following Z-phase input. Figure 14.11 shows the counter reset timing. Timer A3 interrupt request is generated twice when a timer A3 overflow or underflow, and a counter reset by INT2 input occur at the same time. Do not use the timer A3 interrupt request when this function is used. Figure 14.10 Two-phase Pulse (A-phase and B-phase) and Z-phase Figure 14.11 Counter Reset Timing

Page 147 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M

14.1.3 One-shot Timer Mode

In one-shot timer mode, the timer operates only once for each trigger (see Table 14.6). Once a trigger occurs, the timer starts and continues operating for a desired period. Figure 14.12 shows the TAiMR register (i=0 to 4) in one-shot timer mode. Table 14.6 Specifications in One-shot Timer Mode Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation The timer decrements a counter value

When the timer counter reaches "000016", it stops counting after reloading.
If a trigger occurs while counting, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio 1/n n : setting value of the TAi register (i=0 to 4) 000016 to FFFF16 but the timer counter does not run if n=000016 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) and following triggers occur:
External trigger input
The timer overflow or underflow signal
The TAiOS bit in the ONSF register is set to "1" (timer started) Counter Stop Condition • After the timer counter has reached "000016" and is reloaded
When the TAiS bit is set to "0" (timer stopped) Interrupt Request Generation TimingThe timer counter reaches "000016" TAiIN Pin Function Programmable I/O port or trigger input TAiOUT Pin Function Programmable I/O port or pulse output Read from Timer The value in the TAi register is indeterminate when read Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 148 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Figure 14.12 TA0MR to TA4MR Registers b7 b6 b5 b4 b3 b2 b1 b0 00 1 Timer Ai Mode Register (i=0 to 4) (One-Shot Timer Mode) Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 0000 0X00 2 RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operation Mode Select Bit Trigger Select Bit Set to "0" in the one-shot timer mode MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit External Trigger Select Bit(1) 0 : Falling edge of input signal to TAiIN pin 1 : Rising edge of input signal to TAiIN pin 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 1 0 : One-shot timer mode b1b0 Bit Name FunctionBit Symbol b7b6 NOTES: 1. The MR1 bit setting is enabled only when the TAiTGH to TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 0 : The TAiOS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits (b2) Nothing is assigned. When write, set to "0".

Page 149 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M

14.1.4 Pulse Width Modulation Mode

In pulse width modulation mode, the timer outputs pulse of desired width continuously (see Table 14.7). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 14.13 shows the TAiMR register (i=0 to 4) in pulse width modulation mode. Figures 14.14 and 14.15 show examples of how a 16-bit pulse width modulator operates and of how an 8-bit pulse width modulator operates. Table 14.7 Specifications in Pulse Width Modulation Mode Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation The timer decrements the counter (The counter functions as an 8-bit or a 16-bit pulse width modulator)

The timer reloads on the rising edge of PWM pulse and continues counting.
The timer is not affected by the trigger that is generated during counting. 16-Bit PWM • "H" width = n / fj n : setting value of the TAi register 000016 to FFFE16 fj : Count source frequency
Cycle = (216-1) / fj fixed 8-Bit PWM • "H" width = n x (m+1) / fj n : setting value of high-order bit address of the TAi register 0016 to FE16
Cycles = (28-1) x (m+1) / fj m : setting value of low-order bit address of the TAi register 0016 to FF16 Counter Start Condition • External trigger is input
The timer overflows and underflows
The TAiS bit in the TABSR register is set to "1" (start counting) Counter Stop Condition The TAiS bit is set to "0" (stop counting) Interrupt Request Generation TimingOn the falling edge of the PWM pulse TAiIN Pin Function Programmable I/O port or trigger input TAiOUT Pin Function Pulse output Read from Timer The value in the TAi register is indeterminate when read Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 150 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer A))T38/C23M,38/C23M(puorG38/C23M Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode) Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 0000 0X00 2 RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operation Mode Select Bit Trigger Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit External Trigger Select Bit(1) 16/8-Bit PWM Mode Select Bit 0 : Falling edge of input signal to TAiIN pin 1 : Rising edge of input signal to TAiIN pin 0 : The TAiS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 1 1 : Pulse width modulation (PWM) mode b1b0 Bit Name FunctionBit Symbol b7 b6 NOTES: 1. The MR1 bit setting is enabled only when the TAiTGH to TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (b2) Nothing is assigned. When write, set to "0". b7 b6 b5 b4 b3 b2 b1 b0 1 1 Figure 14.13 TA0MR to TA4MR Registers

Page 152 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M

14.2 Timer B

Figure 14.16 shows a block diagram of the timer B. Figures 14.17 to 14.19 show registers associated with the timer B. The timer B supports the following three modes. The TMOD1 to TMOD0 bits in the TBiMR register (i=0 to 5) determine which mode is used.

Timer mode : The timer counts an internal count source.
Event counter mode : The timer counts pulses from an external source or overflow and underflow of another timer.
Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an external signal. Table 14.18 lists TBi IN pin settings. Figure 14.16 Timer B Block Diagram Figure 14.17 TB0 to TB5 Registers Select Clock Source 01: Event Counter 00: Timer 01: Pulse Period and Pulse Width Measurement Reload Register 8 low-order bits 8 high- order bits Low-order Bits of Data Bus High-order Bits of Data Bus f2n(1) TBj Overflow TBiS fc32 Polarity Switching and Edge PulseTBiIN Counter Reset Circuit Counter TBi Address TBj Timer B0 035116 035016 Timer B2 Timer B1 035316 035216 Timer B0 Timer B2 035516 035416 Timer B1 Timer B3 031116 031016 Timer B5 Timer B4 031316 031216 Timer B3 Timer B5 031516 031416 Timer B4 TCK1 to TCK000 TMOD1 to TMOD0 TCK1 (Note 2, 3) i=0 to 5 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. The timer counter overflows or underflows. 3. j=i-1, except j=2 when i=0 j=5 when i=3 TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register TBiS : Bits in the TABSR and the TBSR register Timer Bi Register(1) (i=0 to 5) Symbol Address After Reset TB0 to TB2 035116 - 035016, 035316 - 035216, 035516 - 035416 Indeterminate TB3 to TB5 031116 - 031016, 031316 - 031216, 031516 - 031416 Indeterminate RW RW RW RO Timer Mode 0000 16 to FFFF16 000016 to FFFF16Event Counter Mode Pulse Period/Pulse Width Measurement Mode Function Setting RangeMode If setting value is n, a count source is divided by n+1 If setting value is n, a count source is divided by n+1(2) A count source is incremented between one valid edge and another valid edge of TBi IN pulse b15 b8 b7 b0 NOTES: 1. Use 16-bit data for read and write operations. 2. The TBi register counts the number of external input pulses or the number of times another timer counter overflows and underflows.

Page 153 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M Figure 14.18 TB0MR to TB5MR Registers, TABSR Register Timer Bi Mode Register (i=0 to 5) Symbol Address After Reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 0000 2 RW RW RW RW RW RW RW RW RW TMOD0 TMOD1 MR0 Operation Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit Function varies depending on operation mode (1, 2) Function varies depending on operation mode 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse width measurement mode 1 1 : Do not set to this value b1b0 Bit Name FunctionBit Symbol NOTES: 1. Only MR2 bits in the TB0MR and TB3MR registers are enabled. 2. Nothing is assigned in the MR2 bit in the TB1MR, TB2MR, TB4MR and TB5MR registers. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Count Start Flag Symbol Address After Reset TABSR 0340 16 00 16 RW RW RW RW RW RW RW RW RW TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag 0 : Stops counting 1 : Starts counting TA2S Timer A2 Count Start Flag 0 : Stops counting 1 : Starts counting TA3S Timer A3 Count Start Flag 0 : Stops counting 1 : Starts counting TA4S Timer A4 Count Start Flag 0 : Stops counting 1 : Starts counting TB0S Timer B0 Count Start Flag 0 : Stops counting 1 : Starts counting TB1S Timer B1 Count Start Flag 0 : Stops counting 1 : Starts counting TB2S Timer B2 Count Start Flag 0 : Stops counting 1 : Starts counting Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0

Page 154 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M Timer B3, B4,B5 Count Start Flag Symbol Address After Reset TBSR 0300 16 000X XXXX 2 RW RW RW RW TB3S (b4 - b0) Timer B3 Count Start Flag 0 : Stops counting 1 : Starts counting TB4S Timer B4 Count Start Flag 0 : Stops counting 1 : Starts counting TB5S Timer B5 Count Start Flag 0 : Stops counting 1 : Starts counting Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Figure 14.19 TBSR Register Table 14.8 Settings for the TBiIN Pins (i=0 to 5) PS1_1=0 Port Name P90 PS1, PS3(1) Registers PD7, PD9(1) Registers PD9_0=0 Setting NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" ( write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Function P91 P92 P93 P94 P71 TB0 IN TB1 IN TB2 IN TB3 IN TB4 IN TB5 IN PS3_4=0 PS3_3=0 PS3_2=0 PS3_1=0 PS3_0=0 PD9_1=0 PD9_2=0 PD9_3=0 PD9_4=0 PD7_1=0

Page 155 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M

14.2.1 Timer Mode

In timer mode, the timer counts an internally generated count source (see Table 14.9). Figure 14.20 shows the TBiMR register (i=0 to 5) in timer mode. Table 14.9 Specifications in Timer Mode Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation The timer decrements a counter value

When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes Divide Ratio 1/(n+1) n: setting value of the TBi register (i=0 to 5) 000016 to FFFF16 Counter Start Condition The TBiS bits in the TABSR or TBSR registers are set to "1" (starts counting) Counter Stop Condition The TBiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter underflows TBiIN Pin Function Programmable I/O port Read from Timer The TBi register indicates counter value Write to Timer • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter
While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.20 TB0MR to TB5MR Registers Timer Bi Mode Register (i=0 to 5) (Timer Mode) Symbol Address After reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 RW RW RW RW RW RW RW RW RW TMOD0 TMOD1 MR0 Operation Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit TB0MR, TB3MR registers: Set to "0" in timer mode Set to "0" in timer mode Disabled in timer mode. Can be set to "0" or "1". 0 0 : f1 0 1 : f8 1 0 : f2n(1) 1 1 : fC32 0 0 : Timer mode b1b0 Bit Name FunctionBit Symbol b7 b6 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 00 0

Page 156 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M

14.2.2 Event Counter Mode

In event counter mode, the timer counts how many external signals are applied or how many times another timer overflows and underflows. (See Table 14.10) Figure 14.21 shows the TBiMR register (i=0 to 5) in event counter mode. Table 14.10 Specifications in Event Counter Mode Item Specification Count Source • External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by program)

TBj overflows or underflows (j=i-1, except j=2 when i=0, j=5 when i=3) Counting Operation • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register to continue counting Divide Ratio 1/(n+1) n : setting value of the TBi register 0000 16 to FFFF16 Counter Start Condition The TBiS bit in the TABSR or TBSR register is set to "1" (starts counting) Counter Stop Condition The TBiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter underflows TBiIN Pin Function Programmable I/O port or count source input Read from Timer The TBi register indicates the value of the counter Write to Timer • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter
While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing)

Page 157 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M Timer Bi Mode Register (i=0 to 5) (Event Counter Mode) Symbol Address After reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 RW RW RW RW RW RW RW RW TMOD0 TMOD1 MR0 Operation Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit 0 : Input signal from the TBiIN pin 1 : TBj overflows or underflows(2) TB0MR and TB3MR registers: Set to "0" in event counter mode Disabled in event counter mode. When write, set to "0". When read, its content is indeterminate. Disabled in event counter mode. Can be set to "0" or "1". Count Polarity Select Bit (1) 0 1 : Event counter mode b1 b0 Bit Name FunctionBit Symbol 0 0 : Counts falling edges of external signal 0 1 : Counts rising edges of external signal 1 0 : Counts falling and rising edges of external signal 1 1 : Do not set to this value b3 b2 NOTES: 1. The MR0 and MR1 bits are enabled when the TCK1 bit is set to "0" (input signal from the TBiIN pin). The MR1 bit can be set to either "0" or "1", when the TCK1 bit is set to "1" (timer overflow or underflow). 2. j=i – 1, except j=2 when i=0 and j=5 when i=3. TB1MR, TB2MR, TB4MR and TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 00 1 Figure 14.21 TB0MR to TB5MR Registers

Page 158 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M

14.2.3 Pulse Period/Pulse Width Measurement Mode

In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. (See Table 14.11) Figure 14.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse width measurement mode. Figure 14.23 shows an example of an operation timing when measuring a pulse period. Figure 14.24 shows an example of the pulse width measurement. Table 14.11 Specifications in Pulse Period/Pulse Width Measurement Mode Item Specification Count Source f 1, f8, f2n(3), fC32 Counting Operation • The timer increments a counter value Counter value is transferred to the reload register on the valid edge of a pulse to be measured. It is set to "000016" and the timer continues counting Counter Start Condition The TBiS bit (i=0 to 5) in the TABSR or TBSR register is set to "1" (starts counting) Counter Stop Condition The TBiS bit is set to "0" (stops counting) Interrupt Request Generation Timing• On the valid edge of a pulse to be measured(1)

The timer counter overflows The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the TBiS bit is set to "1" (start counting) and the next count source is counted after setting the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to the TBiMR register. TBiIN Pin Function Input for a pulse to be measured Read from Timer The TBi register indicates reload register values (measurement results)(2) Write to Timer Value written to the TBi register can be written to neither reload register nor counter NOTES: 1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the timer has started counting. 2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid edge after the timer has started counting. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 159 884fo6002,13.naJ13.1.veR 1310-4300B90JER 14. Timer (Timer B))T38/C23M,38/C23M(puorG38/C23M Timer Bi Mode Register (i=0 to 5) (Pulse Period / Pulse Width Measurement Mode) Symbol Address After reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 RW RW RW RW RW (Note 1) RW RW RO RW TMOD0 TMOD1 MR0 Operation Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit 0 0 : f1 0 1 : f8 1 0 : f2n(3) 1 1 : fC32 TB0MR, TB3MR registers: Set to "0" in pulse period/pulse width measurement mode Timer Bi Overflow Flag(2) 0 : No overflow 1 : Overflow Measurement Mode Select Bit 1 0 : Pulse period measurement mode, pulse width measurement mode b1 b0 Bit Name FunctionBit Symbol 0 0 : Pulse period measurement 1 0 1 : Pulse period measurement 2 1 0 : Pulse width measurement 1 1 : Do not set to this value b3 b2 b7 b6 NOTES: 1. The MR1 to MR0 bits selects the following measurements. Pulse period measurement 1 (MR1 to MR0 bits = 00 2) : Measures between the falling edge and the next falling edge of a pulse to be measured Pulse period measurement 2 (MR1 to MR0 bits = 01 2) : Measures between the rising edge and the next rising edge of a pulse to be measured Pulse width measurement (MR1 to MR0 bits = 10 2) : Measures between a falling edge and the next rising edge of a pulse to be measured and between the rising edge and the next falling edge of a pulse to be measured 2. The MR3 bit is indeterminate when reset. When the timer overflows, the MR3 bit is set to "1" (overflow) simultaneously. When the TBiS bit is set to "1" (start counting) and the next count source is counted after the MR3 bit is set to "1", the MR3 bit is set to "0" (no overflow) by writing again. The MR3 bit cannot be set to "1" by program. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Figure 14.22 TB0MR to TB5MR Registers

Page 161 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M 15. Three-Phase Motor Control Timer Functions Three-phase motor driving waveform can be output by using the timers A1, A2, A4 and B2. Table 15.1 lists specifications of the three-phase motor control timer functions. Table 15.2 lists pin settings. Figure 15.1 shows a block diagram. Figures 15.2 to 15.7 show registers associated with the three-phase control timer functions. Table 15.1 Three-Phase Motor Control Timer Functions Specification Item Specification Three-Phase Waveform Output Pin Six pins (U, U, V, V, W, W) Forced Cutoff(1) Apply a low-level signal ("L") to the NMI pin Timers to be Used Timer A4, A1, A2 (used in one-shot timer mode) ___ Timer A4: U- and U-phase waveform control ___ Timer A1: V- and V-phase waveform control ___ Timer A2: W- and W-phase waveform control Timer B2 (used in timer mode) Carrier wave cycle control Dead time timer (three 8-bit timers share reload register) Dead time control Output Waveform Triangular wave modulation, Sawtooth wave modification Can output a high-level waveform or a low-level waveform for one cycle Can set positive-phase level and negative-phase level separately Carrier Wave Cycle Triangular wave modulation: count source x (m+1) x 2 Sawtooth wave modulation: count source x (m+1) m: setting value of the TB2 register, 000016 to FFFF16 Count source: f1, f8, f2n(2), fc32 Three-Phase PWM Output Width Triangular wave modulation: count source x n x 2 Sawtooth wave modulation: count source x n n : setting value of the TA4, TA1 and TA2 register (of the TA4, TA41, TA1, TA11, TA2 and TA21 registers when setting the INV11 bit to "1"), 0001 16 to FFFF16 Count source: f1, f8, f2n(2), fc32 Dead Time Count source x p, or no dead time p: setting value of the DTT register, 0116 to FF16 Count source: f1, or f1 divided by 2 Active Level Selected from a high level ("H") or low level ("L") Positive and Negative-Phase Con- Positive and negative-phases concurrent active disable function current Active Disable Function Positive and negative-phases concurrent active detect function Interrupt Frequency For the timer B2 interrupt, one carrier wave cycle-to-cycle basis through 15 time- carrier wave cycle-to-cycle basis can be selected NOTES: 1. Forced cutoff by the signal applied to the NMI pin is available when the INV02 bit is set to "1" (three- phase motor control timer functions) and the INV03 bit is set to "1" (three-phase motor control timer output enabled). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 162 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M PS1_2 =1 Pin P72/V PS1_3 =1 PS1, PS2 Registers(1) PS1_4 =1 PS1_5 =1 PS2_0 =1 PSL1, PSL2 Registers PSL1_2 =0 PSL1_3 =1 PSL1_4 =1 PSL1_5 =0 PSL2_0 =1 Setting PSC Register PSC_2 =1 NOTES: 1. Set the PS1_2 to PS1_5 and PS2_0 to PS2_1 bits in the PS1 and PS2 registers to "1" after the INV02 bit is set to "1". P73/V P74/W P75/W P80/U P81/U PS2_1 =1 PSL2_1 =0 PSC_3 =0 PSC_4 =0 Table 15.2 Pin Settings

Page 163 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M DUB1bit Timer B2(Timer Mode) Timer B2 Underflow ICTB2 Counter Interrupt Request Bit U U V V W W NMI RESET RD D T Q D T Q D T Q D T Q D T Q D T Q Q INV03 INV05 INV04 Timer A4 Counter (One-Shot Timer Mode) (One-Shot Timer Mode) (One-Shot Timer Mode) Trigger TA4 Register Reload TA41 Register Timer A1 Counter TriggerTA1 Register Reload TA11 Register Timer A2 Counter TriggerTA2 Register Reload TA21 RegisterINV07 T Q INV11 Dead Time Timer INV00 1 0 INV01INV11 DU0 bit DU1 bitT DQ T DQ DUB0bit T DQ T DQ U-phase Output Control Circuit U-Phase Output SignalU-Phase Output Signal V-Phase Output Control Circuit When setting the TA4S bit to "0", signal is set to "0" T Q INV11 T Q INV11 W-Phase Output Control Circuit V-Phase Output Signal W-Phase Output Signal V-Phase Output Signal W-Phase Output Signal Write Signal to Timer B2 Start Trigger Signal for Timers A1, A2, A4 Transfer Trigger (1) INV10 Circuit to set Interrupt Generation Frequency Three-Phase Output Shift Register (U Phase) /LiteDiagLines 0 1 n=1 to 15 Reload Register Dead Time Timer n = 1 to 255 Dead Time Timer n = 1 to 255 n = 1 to 255 Trigger INV06 Trigger TriggerTrigger TriggerTrigger INV06 INV06 INV14 INV13 ICTB2 Register n=1 to 15 Timer B2 n = 1 to 255 INV12 Reload Control Signal for Timer A4 When setting the TA1S bit to "0", signal is set to "0" When setting the TA2S bit to "0", signal is set to "0" INV00 to INV07: Bits in INVC0 RegisterINV10 to INV15: Bits in INVC1 RegisterDUi, DUBi: Bits in IDBi Register (i=0,1)TA1S to TA4S: Bits in TABSR Register Switching to P8 0, P8 1 and P7 2 to P7 5 is not shown in this diagram. NOTES: 1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows, if the INV06 bit is set to "0" (triangular wave modulation). InverseControl InverseControl InverseControlInverseControl InverseControl InverseControl Timer A4One-Shot Pulse Value to be written to INV03 bit Write signal to INV03 bit T INV02 Figure 15.1 Three-Phase Motor Control Timer Functions Block Diagram

Page 164 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M Figure 15.2 INVC0 Register INV00 INV01 INV02 INV03 INV05 INV06 INV07 INV04 Function Three-Phase PWM Control Register 0(1) Bit NameBit Symbol Symbol Address After Reset INVC0 0308 16 00 16 RW RW RW RW RW RW RW RW RW Item INV06 = 0 INV06 = 1 Transfer trigger is generated when the INV07 bit is set to "1". Trigger to the dead time timer is also generated when setting the INV06 bit to "1". Its value is "0" when read. NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). Rewrite the INV00 to INV02 and INV06 bits when the timers A1,A2, A4 and B2 stop. 2. Set the INV01 bit to "1" after setting the ICTB2 register . 3. The INV00 and INV01 bits are enabled only when the INV11 bit is set to "1" (three-phase mode 1). The ICTB2 counter is incremented by one every time the timer B2 counter underflows, regardless of INV00 and INV01 bit settings, when the INV11 bit is set to "0" (three-phase mode). When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflow. When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. 4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and the ICTB2 counter. 5. Set pins after the INV02 bit is set to "1". See Table 15.2 for pin settings. 6. When the INV02 bit is set to "1" and the INV03 bit to "0", U, U, V, V, W and W pins, including pins shared with other output functions, are placed in high-impedance states. 7. The INV03 bit is set to "0" when the followings occurs : - Reset - A concurrent active state occurs while INV04 bit is set to "1" - The INV03 bit is set to "0" by program - A signal applied to the NMI pin changes "H" to "L" The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit to "0". 9. The following table describes how the INV06 bit works. Transfer trigger : Timer B2 underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1 0: The ICTB2 counter is incremented by one on the rising edge of the timer A1 reload control signal 1: The ICTB2 counter is incremented by one on the falling edge of the timer A1 reload control signal 0: ICTB2 counter is incremented by one whenever the timer B2 counter underflows 1: Selected by the INV00 bit 10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the TB2SC register to "0" (timer B2 counter underflows). Transferred once by generating a transfer trigger after setting the IDB0 and IDB1 registers Interrupt Enable Output Polarity Select Bit (3) Interrupt Enable Output Specification Bit(2, 3) Mode Select Bit(4, 5, 6) 0: No three-phase control timer functions 1: Three-phase control timer function 0: Disables three-phase control timer output 1: Enables three-phase control timer outputOutput Control Bit(6, 7) 0: Enables concurrent active output 1: Disables concurrent active output Positive and Negative- Phases Concurrent Active Disable Function Enable Bit Positive and Negative- Phases Concurrent Active Output Detect Flag (8) 0: Not detected 1: Detected Modulation Mode Select(9, 10) 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode Software Trigger Select Transferred every time a transfer trigger is generated By a transfer trigger, or the falling edge of a one-shot pulse of the timer A1, A2 or A4 On the falling edge of a one-shot pulse of the timer A1, A2 or A4 Timing to Trigger the Dead Time Timer when the INV16 Bit=0 INV13 Bit Enabled when the INV11 bit=1 and the INV06 bit=0 Disabled Timing to Transfer from the IDB0 and IDB1 Registers to Three-Phase Output Shift Register Mode Triangular wave modulation mode Sawtooth wave modulation mode b7 b6 b5 b4 b3 b2 b1 b0

Page 165 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M INV10 INV11 INV12 INV13 INV15 TA11, TA21 and TA41 Registers INV00 and INV01 Bits in the INVC0 Register Not used Used INV14 Function Three-Phase PWM Control Register 1(1) Timer A1, A2 and A4 Start Trigger Select Bit Carrier Wave Detect Flag(4) Dead Time Timer Trigger Select Bit INV13 Bit Disabled Enabled Output Polarity Control Bit 0: Timer A1 reload control signal is "0" 1: Timer A1 reload control signal is "1" Timer A1-1, A2-1, A4-1 Control Bit(2, 3) 0: Three-phase mode 0 1: Three-phase mode 1 Dead Time Timer Count Source Select Bit 0 : f 1 : f1 divided-by-2 0: Timer B2 counter underflows 1: Timer B2 counter underflows and write to the TB2 register 0 : Active "L" of an output waveform 1 : Active "H" of an output waveform Dead Time Disable Bit0: Enables dead time 1: Disables dead time Bit NameBit Symbol Symbol Address After Reset INVC1 0309 16 00 16 RW RW RW RW RO RW RW RW Reserved Bit Set to "0" RW Item Mode INV11 = 0 INV11 = 1 Three-phase mode 0 Three-phase mode 1 NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). The timers A1, A2, A4, and B2 must be stopped during rewrite. 2. The following table lists how the INV11 bit works. 3. When the INV06 bit is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0" (three- phase mode 0). Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0" (timer B2 counter underflows). 4. The INV13 bit is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and the INV11 bit to "1" (three-phase mode 1). 5. If the following conditions are all met, set the INV16 bit to "1".

The INV15 bit is set to "0" (dead time timer enabled)
The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit is set to "1". (The positive-phase and negative-phase always output opposite level signals.) If above conditions are not met, set the INV16 bit to "0". Disabled. The ICTB2 counter is incremented whenever the timer B2 counter underflows 0: Falling edge of a one-shot pulse of the timer A1, A2, A4 (5) 1: Rising edge of the three-phase output shift register (U-, V-, W-phase) INV16 (b7) Enabled when INV11=1 and INV06=0 b7 b6 b5 b4 b3 b2 b1 b0 Figure 15.3 INVC1 Register

Page 166 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M Three-Phase Output Buffer Register i(1) (i=0, 1) Symbol Address After Reset IDB0, IDB1 030A16, 030B16 XX11 1111 2 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RO Bit NameBit Symbol DUi DUBi DVi U-Phase Output Buffer i DVBi DWi DWBi (b7 - b6) Function Write output level 0: Active level 1: Inactive level When read, the value of the three- phase shift register is read. U-Phase Output Buffer i V-Phase Output Buffer i V-Phase Output Buffer i W-Phase Output Buffer i W-Phase Output Buffer i NOTES: 1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger. After the transfer trigger occurs, the values written in the IDB0 register determine each phase output signal first. Then the value written in the IDB1 register on the falling edge of timers A1, A2 and A4 one- shot pulse determines each phase output signal. Nothing is assigned. When write, set to "0". When read, its content is "0." Dead Time Timer(1, 2) Symbol Address After Reset DTT 030C 16 Indeterminate RW WO Function Setting Range 1 to 255 If setting value is n, the timer stops when counting n times a count source selected by the INV12 bit after start trigger occurs. Positive or negative phase, which changes from inactive level to active level, shifts when the dead time timer stops. NOTES: 1. Use the MOV instruction to set the DTT register. 2. The DTT register is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06 bit in the INVC0 register determines start trigger of the DTT register. Figure 15.4 IDB0, IDB1 and DTT Registers

Page 167 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M Timer B2 Interrupt Generation Frequency Set Counter(1, 2, 3) Symbol Address After Reset ICTB2 030D 16 Indeterminate b7 b0 RW WO Function Setting Range 1 to 15 Nothing is assigned. When write, set to "0". When the INV01 bit is set to "0" (the ICTB2 counter increments whenever the timer B2 counter underflows) and the setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow occurs. When the INV01 bit is set to "1" (selected by the INV00 bit) and setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow meeting the condition selected in the INV00 bit occurs. NOTES: 1. Use the MOV instruction to set the ICTB2 register. 2. If the INV01 bit in the INVC0 register is set to "1", set the ICTB2 register when the TB2S bit is set to "0" (timer B2 counter stopped). If the INV01 bit is set to "0" and the TB2S bit to "1" (timer B2 counter start), do not set the ICTB2 register when the timer B2 counter underflows. If the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, n being the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. Timer Ai, Ai-1 Register (i=1, 2, 4)(1, 2, 3, 4, 5, 6, 7) Symbol Address After Reset TA1, TA2, TA4 0349 16 - 034816, 034B16 - 034A16, 034F16 - 034E16 Indeterminate TA11, TA21, TA41 030316 - 030216, 030516 - 030416, 030716 - 030616 Indeterminate RW WO Function b0b8 Setting Range 000016 to FFFF16 b15 b7 If setting value is n, the timer stops when the nth count source is counted after a start trigger is generated. Positive phase changes to negative phase, and vice versa, when the timers A1, A2 and A4 stop. NOTES: 1. Use a 16-bit data for read and write.. 2. If the TAi or TAi1 register is set to "0000 16", no counters start and no timer Ai interrupt is generated. 3. Use the MOV instruction to set the TAi and TAi1 registers. 4. When the INV15 bit in the INVC1 register is set to "0" (dead timer enabled), phase switches from an inactive level to an active level when the dead time timer stops. 5. When the INV11 bit is set to "0" (three-phase mode 0), the value of the TAi register is transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to "1" (three-phase mode 1), the value of the TAi1 register is first transferred to the reload register by a timer Ai start trigger. Then, the value of the TAi register is transferred by the next trigger. The values of the TAi1 and TAi registers are transferred alternately to the reload register with every timer Ai start trigger. 6. Do not write to these registers when the timer B2 counter underflows. 7. Follow the procedure below to set the TAi1 register. (1) Write value to the TAi1 register. (2) Wait one timer Ai count source cycle. (3) Write the same value as (1) to the TAi1 register. Timer B2 Special Mode Register Symbol Address After Reset TB2SC 035E 16 XXXX XXX0 2 RW RW Bit Name FunctionBit Symbol PWCON Timer B2 Reload Timing Switching Bit(1) 0 : Timer B2 underflow 1 : Timer A output in odd-number times Nothing is assigned. When write, set to "0". When read, its content is "0." b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. When setting the INV11 bit to "0" (three-phase mode 0) or the INV06 bit to "1" (sawtooth wave modulation mode), set the PWCON bit to "0". Figure 15.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers and TB2SC Register

Page 168 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M Timer B2 Register(1) Symbol Address After Reset TB2 0355 16 - 035416 Indeterminate RW RW Function b0b8 Setting Range If setting value is n, count source is divided by n+1. The timers A1, A2 and A4 start every time an underflow occurs.000016 to FFFF16 NOTES: 1. Use a 16-bit data for read and write. b15 b7 Trigger Select Register Symbol Address After Reset TRGSR 0343 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Bit NameBit Symbol TA1TGL TA1TGH TA2TGL Timer A1 Event/Trigger Select Bit TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH Function Set to "012" (TB2 underflow) before using a V-phase output control circuit Timer A2 Event/Trigger Select Bit Set to "012" (TB2 underflow) before using a W-phase output control circuit : Selects an input to the TA3IN pin : Selects TB2 overflow(1) : Selects TA2 overflow(1) : Selects TA4 overflow(1) Timer A3 Event/Trigger Select Bit Timer A4 Event/Trigger Select Bit Set to "012" (TB2 underflow) before using a U-phase output control circuit NOTES: 1. Overflow or underflow Count Start Flag Symbol Address After Reset TABSR 0340 16 00 16 RW RW RW RW RW Bit Name FunctionBit Symbol TA0S TA1S TA2S Timer A0 Count Start Flag TA3S RW RW RW RW TA4S TB0S TB1S TB2S 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag b6 b5 b3 b2 b1b4b7 b0 Figure 15.6 TB2, TRGSR and TABSR Registers

Page 169 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M Timer Ai Mode Register (i=1, 2, 4) Symbol Address After Reset TA1MR, TA2MR, TA4MR 035716, 035816, 035A16 0000 0X002 RW RW RW Bit Name FunctionBit Symbol TMOD0 TMOD1 Operation Mode Select Bit MR1 RW RW RW RW MR2 MR3 TCK0 TCK1 Set to "102" (one-shot timer mode) with the three-phase motor control timer function Set to "0" with the three-phase motor control timer function Set to "1"(selected by the TRGSR register) with the three- phase motor control timer function : f : f8 : f2n(1) : fC32 External Trigger Select Bit Trigger Select Bit Set to "0" with the three-phase motor control timer function Count Source Select Bit NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). b6 b5 b3 b2 b1b4b7 b0 110 0 (b2) Nothing is assigned. When write, set to "0". Timer B2 Mode Register Symbol Address After Reset TB2MR 035D 16 00XX 00002 RW RW RW Bit Name FunctionBit Symbol TMOD0 TMOD1 MR0 Operation Mode Select Bit MR1 RW RW RW MR2 MR3 TCK0 TCK1 Set to "002" (timer mode) when using the three-phase motor control timer function : f : f8 : f2n(1) : fC32 Disabled when using the three-phase motor control timer function. When write, set to "0". When read, its content is indeterminate. Set to "0" when using three-phase motor control timer function Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Count Source Select Bit NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). b6 b5 b3 b2 b1b4b7 b0 000 Figure 15.7 TA1MR, TA2MR, TA4MR Registers and TB2MR Register

Page 170 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M TA4 Register(2) TA41 Register(2) Reload Register(2) m m m nn p p p m m q q q Timer A1 Reload Control Signal(1) m n n n n n p p q qp q r r Triangular Wave Signal Wave Triangular waveform as a Carrier Wave Timer B2 TB2S Bit in TABSR Register Timer A4 Start Trigger Signal(1) Timer A4 One-Shot Pulse (1) Rewrite the IDB0 and IDB1 registers Transfer a counter value to the three-phase shift register U-Phase Output Signal(1) U-Phase Output Signal (1) U-Phase INV14 = 0 ("L" active) U-Phase Dead time Dead timeINV14 = 1 ("H" active) U-Phase U-Phase NOTES: 1. Internal signals. See Figure 15.1. 2. Applies only when the INV11 bit is set to "1" (three-phase mode). Examples of PWM output change are (a) When INV11=1 (three-phase mode 1) - INV01=0 and ICTB2=2 16 (The timer B2 interrupt is generated with every second timer B2 underflow) or INV01=1, INV00=1and ICTB2=1 16 (The timer B2 interrupt is generated on the falling edge of the timer A1 reload control signal) - Default value of the timer: TA41=m, TA4=m The TA4 and TA41 registers are changed whenever the timer B2 interrupt is generated. First time: TA41=n, TA4:=n. Second time: TA41=p, TA4=p. - Default value of the IDB0 and IDB1 registers DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the third timer B2 interrupt. (b) When INV11=0 (three-phase mode 0) - INV01=0, ICTB2=1 16 (The timer B2 interrupt is generated whenever the timer B2 underflows) - Default value of the timer: TA4=m The TA4 register is changed whenever the timer B2 interrupt is generated. First time: TA4=m. Second time: TA4=n. Third time: TA4=n. Fourth time: TA=p. Fifth time: TA4=p. - Default value of the IDB0 and IDB1 registers: DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the sixth timer B2 interrupt. The above applies to INVC0 = 00XX11XX2 and INVC1 = 010XXXX02 (X varies depending on each system.) INV00, INV01: Bits in the INVC0 register INV11, INV14: Bits in the INVC1 register r The three-phase control timer function is available by setting the INV02 bit in the INVC0 register to "1". The timer B2 is used for carrier wave control and timers A4, A1, A2 for three-phase PWM output (U, U, V, V, W, W) control. An exclusive dead time timer controls dead time. Figure 15.8 shows an example of the triangular modulation waveform. Figure 15.9 shows an example of the sawtooth modulation waveform. Figure 15.8 Triangular Wave Modulation Operation

Page 171 884fo6002,13.naJ13.1.veR 1310-4300B90JER 15. Three-Phase Motor Control Timer Functions)T38/C23M,38/C23M(puorG38/C23M Timer B2 U-Phase Sawtooth Wave Signal Wave U-Phase Output Signal(1) U-Phase Output Signal (1) INV14 = 0 ("L" active) Sawtooth Waveform as a Carrier Wave Transfer the counter to the three-phase shift register Rewrite the IDB0 and IDB1 registers NOTES: 1. Internal signals. See Figure 15.1. The examples of PWM output change are - Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt. The above applies to INVC0 = 01XX110X 2 and INVC1 = 010XXX002 (X varies depending on each system.) INV14 = 1 ("H" active) U-Phase U-Phase U-Phase Dead time Dead time Timer A4 One-Shot Pulse(1) Timer A4 Start Trigger Signal(1) INV14: Bits in the INVC1 register Figure 15.9 Sawtooth Wave Modulation Operation

Page 172 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M 16. Serial I/O Serial I/O consists of five channels (UART0 to UART4). Each UARTi (i=0 to 4) has an exclusive timer to generate the transfer clock and operates independently. Figure 16.1 shows a UARTi block diagram. UARTi supports the following modes : - Clock synchronous serial I/O mode - Clock asynchronous serial I/O mode (UART mode) - Special mode 1 (I 2C mode) - Special mode 2 - Special mode 3 (Clock-divided synchronous function, GCI mode) - Special mode 4 (Bus conflict detect function, IE mode) - Special mode 5 (SIM mode) Figures 16.2 to 16.9 show registers associated with UARTi. Refer to the tables listing each mode for register and pin settings.

Page 173 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M m : setting value of UiBRG register RxDi Receive Control Circuit Transmit Control Circuit 1 / (m+1) UiBRG Register Clock Synchronous Type (when internal clock is selected) Clock Asynchronous Receive Clock Synchronous Type Clock Synchronous Type Clock Synchronous Type (when internal clock is selected) Clock Synchronous Type (when external clock is selected) Receive Clock Transmit Clock CLKi CTSi / RTSi f2n(2) Vss CTSi TxDiRxD Polarity Switching Circuit TxD Polarity Switching Circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK Polarity Switching Circuit CKDIR Inside Outside Selecting Clock Source Transmit/ Receive Unit (Note 1) NOTES: 1. P70 and P71 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). CKPOL CLK1 to CLK0 010, 100, 101, 110 010, 100, 101, 110 001 001 Clock Asynchronous Transmit SMD2 to SMD0 CKDIR CRD CRD RTSi CRS 0 Clock Asynchronous Type (8 bits) Clock Synchronous Type Clock Asynchronous Type (7 bits) SP SP PAR Clock Synchronous Type Clock Synchronous Type Low-order bits of data bus TxDi UARTi Transmit RegisterPAR disabled PAR enabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 UiTB Register Clock Synchronous Type UiRB Register UARTi Receive Register 2SP 1SP RxDi D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 8000 0000 SP SP PAR Inverse No inverse Error Signal Output Circuit RxD Data Inverse Circuit Error Signal Output enable Error Signal Output disable Inverse No inverse Logic Inverse Circuit + MSB/LSB Conversion Circuit Logic Inverse Circuit + MSB/LSB Conversion Circuit PAR enabled PAR disabled Clock Synchronous Type TxD Data Inverse CircuitSP: Stop bit PAR: Parity bit i=0 to 4 SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register UiERE: Bit in UiC1 register IOPOL PRYE Clock Asynchronous Type (9 bits) Clock Synchronous Type Clock Asynchronous Type (8 bits) Clock Asynchronous Type Clock Asynchronous Type (9 bits) Clock Asynchronous Type (7 bits) 1 11 SMD2 to SMD0 STPS Clock Asynchronous Type (7 bits) Clock Asynchronous Type (8 bits) Clock Asynchronous Type (8 bits) Clock Asynchronous Type (9 bits) Clock Asynchronous Type (7 bits) 1SP 2SP STPS PRYE Clock Asynchronous Type Clock Asynchronous Type (9 bits) 1 1 IOPOL UiERE High-order bits of data bus SMD2 to SMD0 Figure 16.1 UARTi Block Diagram

Page 174 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M UARTi Transmit Buffer Register (i=0 to 4)(1) Symbol Address After Reset U0TB to U2TB 036B 16-036A16, 02EB16-02EA 16, 033B16-033A16 Indeterminate U3TB, U4TB 032B 16-032A16, 02FB16-02FA16 Indeterminate RW Transmit data (D7 to D0) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Transmit data (D8) NOTES: 1. Use the MOV instruction to set the UiTB register. WO WO (b15 - b9) (b7 - b0) (b8) Function b7 b0b15 b8 Bit Symbol UARTi Receive Buffer Register (i=0 to 4) Bit NameBit Symbol Symbol Address After Reset U0RB to U2RB 036F 16 - 036E16, 02EF 16 - 02EE 16, 033F16 - 033E16 Indeterminate U3RB, U4RB 032F 16 - 032E16, 02FF16 - 02FE 16 Indeterminate RW Received data (D7 to D0) ABT (b10 - b9) (b7 - b0) (b8) OER FER SUM PER Function Overrun Error Flag(2) Arbitration Lost Detect Flag(1) Framing Error Flag(2, 3) Parity Error Flag(2, 3) Error Sum Flag(2, 3) Received data (D8) 0: Not detected (win) 1: Detected (lose) 0: No overrun error occurs 1: Overrun error occurs 0: No framing error occurs 1: Framing error occurs 0: No parity error occurs 1: Parity error occurs 0: No error occurs 1: Error occurs RW RO RO RO RO RO RO NOTES: 1. The ABT bit can be set to "0" only. 2. When the SMD2 to SMD0 bits in the UiMR register is set to "000 2" (serial I/O disable) or the RE bit in the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0" (no error occurs). When all OER, FER and PER bits are set to "0" (no error), the SUM bit is set to "0" (no error). Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register. 3. These error flags are disabled when the SMD2 to SMD0 bits in the UiMR register are set to "001 (clock synchronous serial I/O mode, special mode 2, or special mode 3) or to "0102" (I2C mode). When read, the contents are indeterminate. b7 b0b15 b8 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Figure 16.2 U0TB to U4TB Registers and U0RB to U4RB Registers

Page 175 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M Function UARTi Baud Rate Register (i=0 to 4)(1, 2, 3) Setting Range Symbol Address After Reset U0BRG to U4BRG 0369 16, 02E916, 033916, 032916, 02F916 Indeterminate If the setting value is m , the UiBRG register divides a count source by m+1 RW 0016 to FF16 NOTES: 1. Use the MOV instruction to set the UiBRG register. 2. Set the UiBRG register data transmit and receive is stopped. 3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 register. WO b7 b0 UARTi Transmit/Receive Mode Register (i=0 to 4) Symbol Address After Reset U0MR to U4MR 036816, 02E816, 033816, 032816, 02F816 0016 RW CKDIR STPS PRY IOPOL PRYE SMD0 SMD2 SMD1 Serial I/O Mode Select Bit Internal/External Clock Select Bit Stop Bit Length Select Bit Odd/Even Parity Select Bit Parity Enable Bit TxD,RxD Input/Output Polarity Switch Bit 0 0 0: Serial I/O disabled 0 0 1: Clock synchronous serial I/O mode 0 1 0: I 2C mode 1 0 0: UART mode, 7-bit transfer data 1 0 1: UART mode, 8-bit transfer data 1 1 0: UART mode, 9-bit transfer data b2 b1 b0 0: Not inversed 1: Inverse 0 : 1 stop bit 1 : 2 stop bits Enables when PRYE = 1 0 : Odd parity 1 : Even parity 0 : Disables a parity 1 : Enables a parity 0 : Internal clock 1 : External clock Bit Name Bit Symbol Do not set value other than the above RW RW RW RW RW RW RW RW Function b7 b6 b5 b4 b3 b2 b1 b0 Figure 16.3 U0BRG to U4BRG Registers and U0MR to U4MR Registers

Page 176 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M UARTi Transmit/Receive Control Register 0 (i=0 to 4) Symbol Address After Reset U0C0 to U4C0 036C 16, 02EC 16, 033C 16, 032C 16, 02FC 16 0000 1000 2 RO RW TXEPT CRD NCH UFORM CKPOL b1b0 CLK0 CRS CLK1 UiBRG Count Source Select Bit(4) CST/RTS Function Select Bit Transmit Register Empty Flag CTS/RTS Disable Bit Data Output Select Bit(1) CLK Polarity Select Bit Transfer Format Select Bit (3) Enabled when CRD=0 0 : Selects CTS function 1 : Selects RTS function 0 0: Selects f 0 1: Selects f8 1 0: Selects f2n(2) 1 1: Do not set to this value 0 : Data in the transmit register (during transmission) 1 : No data in the transmit register (transmission is completed) 0 : Enables CTS/RTS function 1 : Disables CTS/RTS function 0 : TxDi/SDAi and SCLi are ports for the CMOS output 1 : TxDi/SDAi and SCLi are ports for the N-channel open drain output 0 : LSB first 1 : MSB first Bit NameBit Symbol Function RW RW RW RW RW RW RW NOTES: 1. P7 0/TxD2 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 3. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001 (clock synchronous serial I/O mode), or "1012" (UART mode, 8-bit transfer data). Set this bit to "1" when the SMD2 to SMD0 bits are set to "0102" (I2C mode), and to "0" when the SMD2 to SMD0 bits are set to "1002"(UART mode, 7-bit transfer data) or "1102"(UART mode, 9-bit transfer data). 4. If the CLK1 and CLK0 bits are changed, set the UiBRG register. 0 : Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge 1 : Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge b7 b6 b5 b4 b3 b2 b1 b0 Figure 16.4 U0C0 to U4C0 Registers

Page 177 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M UARTi Transmit/Receive Control Register 1 (i=0 to 4) Symbol Address After Reset U0C1 to U4C1 036D 16, 02ED 16, 033D 16, 032D 16, 02FD 16 0000 00102 RW RW RI UiIRS UiRRM UiLCH TE RE TI Transmit Enable Bit Transmit Buffer Empty Flag Receive Enable Bit Receive Complete Flag Clock-Divided Synchronous Stop Bit / Error Signal Output Enable Bit (1) SCLKSTPB /UiERE UARTi Transmit Interrupt Cause Select Bit UARTi Continuous Receive Mode Enable Bit Data Logic Select Bit 0: Transmit disable 1: Transmit enable 0: Data in the UiTB register 1: No data in the UiTB register 0: Receive disable 1: Receive enable 0: No data in the UiRB register 1: Data in the UiRB register 0: No data in the UiTB register (TI = 1) 1: Transmission is completed (TXEPT = 1) Disables continuous receive mode to be entered 1: Enables continuous receive mode to be entered 0: Not inversed 1: Inverse Clock-divided synchronous stop bit (special mode 3) 0: Stops synchronizing 1: Starts synchronizing Error signal output enable bit (special mode 5) 0: Not output 1: Output Bit Name Bit Symbol RO RW RO RW RW RW RW Function NOTES: 1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register. 2. The UiLCH bit is enabled when the SMD2 to SMD0 bits are set to "001 2" (clock synchronous serial I/O mode), "1002"(UART mode, 7-bit transfer data), or "1012" (UART mode, 8-bit transfer data). Set this bit to "0" when the SMD2 to SMD0 bits are set to "0102" (I2C mode) or "1102"(UART mode, 9-bit transfer data) b7 b6 b5 b4 b3 b2 b1 b0 UARTi Special Mode Register (i=0 to 4) Symbol Address After Reset U0SMR to U4SMR 036716, 02E716, 033716, 032716, 02F716 0016 RW RW LSYN ABSCS ACSE SSS IICM BBS ABC 0: Except I2C mode 1: I2C mode 0: Update per bit 1: Update per byte 0: Stop condition detected 1: Start condition detected (Busy) 0: Disabled 1: Enabled 0: Not related to RxDi 1: Synchronized with RxDi 0: Rising edge of transfer clock 1: Timer Aj underflow(2) Bit Name Bit Symbol I2C Mode Select Bit Bus Busy Flag NOTES: 1. The BBS bit is set to "0" by program. It is unchanged if set to "1". 2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal, UART3: timer A3 underflow signal, UART4: timer A4 underflow signal. 3. Refer to notes for the SU1HIM bit in the UiSMR2 register. Auto Clear Function Select Bit for Transmit Enable Bit SCLL Sync Output Enable Bit Arbitration Lost Detect Flag Control Bit Bus Conflict Detect Sampling Clock Select Bit Transmit Start Condition Select Bit 0: No auto clear function 1: Auto clear at bus conflict SCLKDIV Clock Divide Synchronous Bit (Note 3) RW RW (1) RW RW RW RW RW Function b7 b6 b5 b4 b3 b2 b1 b0 Figure 16.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers

Page 178 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M UARTi Special Mode Register 2 (i=0 to 4) Symbol Address After Reset U0SMR2 to U4SMR2 036616, 02E616, 033616, 032616, 02F616 0000 00002 RW IICM2 CSC Clock Synchronous Bit I2C Mode Select Bit 2 0: Output 1: No output (high-impedance) Bit NameBit Symbol Function ALS STC SWC2 SDHI SWC SCL Wait Output Bit SDA Output Stop Bit UARTi Initialize Bit SCL Wait Output Bit 2 SDA Output Inhibit Bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Output 1: No output 0: Disabled 1: Enabled 0: Transfer clock 1: 0 output SU1HIM External Clock Synchronous Enable Bit RW RW RW RW RW RW RW RW NOTES: 1. Refer to 16.3 Special mode 1 (I2C Mode). 2. The external clock synchronous function can be selected by combining the SU1HIM bit and the SCLKDIV bit in the UiSMR register. SCLKDIV bit in the UiSMR Register SU1HIM bit in the UiSMR2 Register External Clock Synchronous Function Selection 0 or 1 No synchronization Same division as the external clock External clock divided by 2 b7 b6 b5 b4 b3 b2 b1 b0 (Note 1) (Note 2) Figure 16.6 U0SMR2 to U4SMR2 Registers

Page 179 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M UARTi Special Mode Register 3 (i=0 to 4) Symbol Address After Reset U0SMR3 to U4SMR3 036516, 02E516, 033516, 032516, 02F516 0016 RW NODC ERR DL0 DL1 SSE DINC CKPH DL2 SS Pin Function Enable Bit(1) Clock-Phase Set Bit Serial Input Port Set Bit Clock Output Select Bit Fault Error Flag (2) SDAi Digital Delay Time Set Bit(3, 4) 0: Disables SS pin function 1: Enables SS pin function 0: No clock delay 1: Clock delay 0: Selects the TxDi and RxDi pins (master mode) 1: Selects the STxDi and SRxDi pins (slave mode) 0: CMOS output 1: N-channel open drain output 0: No error 1: Error 000 : No delay 001 : 1-to-2 cycles of BRG count source 010 : 2-to-3 cycles of BRG count source 011 : 3-to-4 cycles of BRG count source 100 : 4-to-5 cycles of BRG count source 101 : 5-to-6 cycles of BRG count source 110 : 6-to-7 cycles of BRG count source 111 : 7-to-8 cycles of BRG count source b7 b6 b5 Bit NameBit Symbol Function NOTES: 1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled). 2. The ERR bit is set to "0" by program. It is unchanged if set to "1". 3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I 2C mode. Set these bits to "000 2" (no delay) except in the I2C mode. 4. When the external clock is selected, approximately 100ns delay is added. RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 16.7 U0SMR3 to U4SMR3 Registers

Page 180 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M UARTi Special Mode Register 4 (i=0 to 4) Symbol Address After Reset U0SMR4 to U4SMR4 0364 16, 02E416, 033416, 032416, 02F416 0016 RW Start Condition Generate Bit(1) Restart Condition Generate Bit (1) Stop Condition Generate Bit (1) SCL, SDA Output Select Bit ACK Data Bit ACK Data Output Enable Bit 0: Clear 1: Start 0: Clear 1: Start 0: Clear 1: Start 0: Selects the serial I/O circuit 1: Selects the start/stop condition generation circuit 0: ACK 1: NACK Bit Name Bit Symbol Function NOTES: 1. When each condition is generated, the STAREQ, RSTAREQ or STPREQ bit is set to "0". When a condition generation is incomplete, the bit remains unchanged as "1". SCL Wait Output Bit 3 SCL Output Stop Enable Bit 0: SCL "L" hold disabled 1: SCL "L" hold enabled 0: Disabled 1: Enabled 0: Serial I/O data output 1: ACK data output STSPSEL ACKD ACKC SCLHI STAREQ STPREQ RSTAREQ SWC9 RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 16.8 U0SMR4 to U4SMR4 Registers

Page 181 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O)T38/C23M,38/C23M(puorG38/C23M External Interrupt Request Cause Select Register Symbol Address After Reset IFSR 031F 16 0016 RW INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit (1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity Select Bit(1) INT5 Interrupt Polarity Select Bit (1) 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges Bit Name Bit Symbol Function NOTES: 1.Set this bit to "0" to select level sensitive. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). UART1, UART4 Interrupt Cause Select Bit UART0, UART3 Interrupt Cause Select Bit 0 : One edge 1 : Both edges IFSR3 IFSR4 IFSR5 IFSR6 IFSR0 IFSR2 IFSR1 IFSR7 RW RW RW RW RW RW RW RW 0 : UART3 bus conflict, start condition detect, stop condition detect, fault error detect 1 : UART0 bus conflict, start condition detect, stop condition detect, fault error detect 0 : UART4 bus conflict, start condition detect, stop condition detect, fault error detect 1 : UART1 bus conflict, start condition detect, stop condition detect, fault error detect b7 b6 b5 b4 b3 b2 b1 b0 Figure 16.9 IFSR Register

Page 182 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Clock Synchronous Serial I/O))T38/C23M,38/C23M(puorG38/C23M

16.1 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1 lists specifications of clock synchronous serial I/O mode. Table 16.2 lists registers to be used and settings. Tables 16.3 to 16.5 list pin settings. When UARTi (i=0 to 4) operation mode is selected, the TxDi pin outputs an "H" signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 16.10 shows transmit and receive timings in clock synchronous serial I/O mode. Table 16.1 Clock Synchronous Serial I/O Mode Specifications Item Specification Transfer Data Format • Transfer data : 8 bits long Transfer Clock • The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected): fj=f1, f8, f2n(1)m :setting value of the UiBRG register 0016 to FF16.

The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin Transmit/Receive Control
Selected from the CTS function, RTS function or CTS/RTS function disabled Transmit Start Condition • To start transmitting, the following requirements must be met(2): - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) - Apply an "L" signal to the CTSi pin when the CTS function is selected Receive Start Condition • To start receiving, the following requirements must be met(2): - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit to "1" (transmit enable) - Set the TI bit to "0" (data in the UiTB register) Interrupt Request Generation Timing• Transmit interrupt timing can be selected from the followings: - The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed) : when a data transfer from the UARTi transmit register is completed
Receive interrupt timing When data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detect • Overrun error(3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register Selectable Function • CLK polarity Transferred data is output and input on either the rising edge or falling edge of the transfer clock
LSB first / MSB first Data is transmitted or received in either bit 0 or in bit 7
Continuous receive mode Data can be received simultaneously by reading the UiRB register
Serial data logic inverse This function inverses transmitted or received data logically NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L"). 3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). fj 2(m+1)

Page 183 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Clock Synchronous Serial I/O))T38/C23M,38/C23M(puorG38/C23M Table 16.2 Registers to be Used and Setting Value in Clock Synchronous Serial I/O Mode Register Bit Function UiTB 0 to 7 Set transmit data UiRB 0 to 7 Received data can be read OER Overrun error flag UiBRG 0 to 7 Set bit rate UiMR SMD2 to SMD0 Set to "001 2" CKDIR Select the internal clock or external clock IOPOL Set to "0" UiC0 CLK1 to CLK0 Select count source for the UiBRG register CRS Select CTS or RTS when using either TXEPT Transmit register empty flag CRD Enables or disables the CTS or RTS function NCH Select output format of the TxDi pin CKPOL Select transmit clock polarity UFORM Select either LSB first or MSB first UiC1 TE Set to "1" to enable data transmission and reception TI Transmit buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select how the UARTi transmit interrupt is generated UiRRM Set to "1" when using continuous receive mode UiLCH Set to "1" when using data logic inverse SCLKSTPB Set to "0" UiSMR 0 to 7 Set to "00 16" UiSMR2 0 to 7 Set to "00 16" UiSMR3 0 to 2 Set to "000 2" NODC Select clock output format 4 to 7 Set to "0000 2" UiSMR4 0 to 7 Set to "00 16" i=0 to 4

Page 184 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Clock Synchronous Serial I/O))T38/C23M,38/C23M(puorG38/C23M Table 16.3 Pin Settings in Clock Synchronous Serial I/O Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P6 0 CTS0 input PS0_0=0 - PD6_0=0 RTS0 output PS0_0=1 - - P6 1 CLK0 input PS0_1=0 - PD6_1=0 CLK0 output PS0_1=1 - - P6 2 RxD0 input PS0_2=0 - PD6_2=0 P6 3 TxD0 output PS0_3=1 - - P6 4 CTS1 input PS0_4=0 - PD6_4=0 RTS1 output PS0_4=1 PSL0_4=0 - P6 5 CLK1 input PS0_5=0 - PD6_5=0 CLK1 output PS0_5=1 - - P6 6 RxD1 input PS0_6=0 - PD6_6=0 P6 7 TxD1 output PS0_7=1 - - Table 16.4 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 - P71(1) RxD2 input PS1_1=0 - - PD7_1=0 P7 2 CLK2 input PS1_2=0 - - PD7_2=0 CLK2 output PS1_2=1 PSL1_2=0 PSC_2=0 - P7 3 CTS2 input PS1_3=0 - - PD7_3=0 RTS2 output PS1_3=1 PSL1_3=0 PSC_3=0 - NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.5 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PD9 Register (1) P9 0 CLK3 input PS3_0=0 - PD9_0=0 CLK3 output PS3_0=1 - - P9 1 RxD3 input PS3_1=0 - PD9_1=0 P9 2 TxD3 output PS3_2=1 PSL3_2=0 - P9 3 CTS3 input PS3_3=0 PSL3_3=0 PD9_3=0 RTS3 output PS3_3=1 - - P9 4 CTS4 input PS3_4=0 PSL3_4=0 PD9_4=0 RTS4 output PS3_4=1 - - P9 5 CLK4 input PS3_5=0 PSL3_5=0 PD9_5=0 CLK4 output PS3_5=1 - - P9 6 TxD4 output PS3_6=1 - - P9 7 RxD4 input PS3_7=0 - PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 185 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Clock Synchronous Serial I/O))T38/C23M,38/C23M(puorG38/C23M D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK Pulse stops because TE bit = 0 Data is set in the UiTB register Transfer Clock TE bit in UiC1 register TI bit in UiC1 register CLKi TxDi TXEPT bit in UiC0 register "H" "L" CTSi IR bit in SiTIC register "0" "1" Pulse stops because CTSi = H Data is transferred from the UiTB register to the UARTi transmit register Set to "0" by an interrupt request acknowledgement or by program TC =2(m+1)/fj fj : Count source frequency set in the UiBRG register (f1, f8, f2n(1)) m : Setting value of the UiBRG register i = 0 to 4 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division ( n=0) or divide-by-2n (n=1 to 15). The above applies to the following settings:

The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
The CRD bit in the UiC 0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "0" (CTS function selected)
The CKPOL bit the in UiC 0 register is set to "0" (data transmitted on the falling edge of the transfer clock)
The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register) (1) Transmit Timing (Internal clock selected) "0" "1" "0" "1" "0" "1" Dummy data is set in the UiTB registerTE bit in UiC1 register TI bit in UiC1 register CLKi RxDi RI bit in UiC1 register RTSi RE bit in UiC1 register Received data is taken in Data is transferred from the UiTB register to the UARTi transmit register Read by the UiRB register The above applies to the following settings:
The CKDIR bit in the UiMR register is set to "1" (external clock selected)
The CRD bit in the UiC 0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "1" (RTS function selected)
The CKPOL bit in the UiC0 register is set to "0" (Data is received on the rising edge of the transfer clock) IR bit in SiRIC register Set to "0" by an interrupt request acknowledgement or by program 1 / fEXT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 0 D 1 D 2 D 3 D 4 D 5D 7D 6 OER bit in UiRB register D 6 Meet the following conditions while "H" is applied to the CLKi pin before receiving data:
Set the TE bit in the UiC 1 register to "1" (transmit enable)
Set the RE bit in the UiC1 register to "1" (receive enable)
Write dummy data to the UiTB register fEXT : External clock frequency i=0 to 4 (2) Receive Timing (External clock selected) "H" "L" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" Becomes "L" when the UiRB register is read Data transferred from UARTi register to UiRB register Figure 16.10 Transmit and Receive Operation

Page 186 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Clock Synchronous Serial I/O))T38/C23M,38/C23M(puorG38/C23M D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 0 TXD i R XD i CLK i (1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0" (Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 TXD i R XD i CLK i (2) When the CKPOL bit in the UiC0 register is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) NOTES: 1. The CLKi pin is held high ("H") when no data is transferred. 2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). NOTES: 3. The CLKi pin is held low ("L") when no data is transferred. 4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 re gister is set to "0" (not inversed). (1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0" (LSB first) D 0 D 1 D 2 D 4D 3 D 5 D 6 D 7TXD i R XD i CLK i TXD i R XD i CLK i (2) When the UFORM bit in the UiC0 register is set to "1" (MSB first) NOTES: 2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). D 0 D 1 D 2 D 4D 3 D 5 D 6 D 7 D 7 D 6 D 5 D 3D 4 D 2 D 1 D 0 D 7 D 6 D 5 D 3D 4 D 2 D 1 D 0

16.1.1 Selecting CLK Polarity

As shown in Figure 16.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the transfer clock. Figure 16.11 Transfer Clock Polarity

16.1.2 Selecting LSB First or MSB First

As shown in Figure 16.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format. Figure 16.12 Transfer Format

Page 187 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Clock Synchronous Serial I/O))T38/C23M,38/C23M(puorG38/C23M D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7TxD i (no inverse) Transfer clock "H" "L" "H" "L" TxD i (inverse) "H" "L" (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed) Transfer clock "H" "L" (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge) and the UFORM bit in the UiC register is set to "0" (LSB first). D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

16.1.3 Continuous Receive Mode

When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set dummy data in the UiTB register by program.

16.1.4 Serial Data Logic Inverse

When the UiLCH bit in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 16.13 shows a switching example of the serial data logic. Figure 16.13 Serial Data Logic Inverse

Page 188 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (UART))T38/C23M,38/C23M(puorG38/C23M

16.2 Clock Asynchronous Serial I/O (UART) Mode

In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format. Table 16.6 lists specifications of UART mode. Table 16.6 UART Mode Specifications Item Specification Transfer Data Format • Character bit (transfer data ) : selected from 7 bits, 8 bits, or 9 bits long

Start bit: 1 bit long
Parity bit: selected from odd, even, or none
Stop bit: selected from 1 bit or 2 bits long Transfer Clock • The CKDIR bit in the UiMR register is set to "0" (internal clock selected) : fj/16(m+1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register 0016 to FF16
The CKDIR bit is set to "1" (external clock selected) : fEXT /16(m+1) fEXT : clock applied to the CLKi pin Transmit/Receive Control
Select from CTS function, RTS function or CTS/RTS function disabled Transmit Start Condition• To start transmitting, the following requirements must be met: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) - Apply an "L" signal to the CTSi pin when the CTS function is selected Receive Start Condition• To start receiving, the following requirements must be met: - Set the RE bit in the UiC1 register to "1" (receive enable) - The start bit is detected Interrupt Request • Transmit interrupt timing can be selected from the followings: Generation Timing - The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed) : when data transmission from the UARTi transfer register is completed
Receive interrupt timing when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detect • Overrun error(2) This error occurs when the bit before the last stop bit of the next received data is read prior to reading the UiRB register (the first stop bit when selecting 2 stop bits)
Framing error This error occurs when the number of stop bits set is not detected
Parity error When parity is enabled, this error occurs when the number of "1" in parity and character bits does not match the number of "1" set
Error sum flag This flag is set to "1" when any of an overrun, framing or parity errors occur Selectable Function • LSB first / MSB first Data is transmitted or received in either bit 0 or in bit 7
Serial data logic inverse Logic values of data to be transmitted or received data are inversed. The start bit and stop bit are not inversed
TxD, RxD I/O polarity switching TxD pin output and RxD pin input are inversed NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register remains unchanged as "1" (interrupt requested).

Page 189 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (UART))T38/C23M,38/C23M(puorG38/C23M to 4) operation mode is selected, the TxDi pin outputs an "H" signal before transfer is started (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 16.14 shows an example of a transmit operation in UART mode. Figure 16.15 shows an example of a receive operation in UART mode. Table 16.7 Registers to be Used and Settings in UART Register Bit Function UiTB 0 to 8 Set transmit data (1) UiRB 0 to 8 Received data can be read (1) OER, FER, Error flags PER, SUM UiBRG 0 to 7 Set bit rate UiMR SMD2 to SMD0 Set to "100 2" when transfer data is 7 bits long Set to "1012" when transfer data is 8 bits long Set to "1102" when transfer data is 9 bits long CKDIR Select the internal clock or external clock STPS Select stop bit length PRY, PRYE Select parity enable or disable, odd or even IOPOL Select TxD / RxD I/O polarity UiC0 CLK0, CLK1 Select count source for the UiBRG register CRS Select either CTS or RTS when using either TXEPT Transfer register empty flag CRD Enables or disables the CTS or RTS function NCH Select output format of the TxDi pin CKPOL Set to "0" UFORM Select the LSB first or MSB first when a transfer data is 8 bits long Set to "0" when transfer data is 7 bits or 9 bits long UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select how the UARTi transmit interrupt is generated UiRRM Set to "0" UiLCH Select whether or not data logic is inversed when transfer data length is 7 or 8 bits. Set to "0" when transfer data length is 9 bits. UiERE Set to either "0" or "1" UiSMR 0 to 7 Set to "00 16" UiSMR2 0 to 7 Set to "00 16" UiSMR3 0 to 7 Set to "00 16" UiSMR4 0 to 7 Set to "00 16" NOTES: 1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long.

Page 190 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (UART))T38/C23M,38/C23M(puorG38/C23M Table 16.8 Pin Settings in UART (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P6 0 CTS0 input PS0_0=0 – PD6_0=0 RTS0 output PS0_0=1 –– P6 1 CLK0 input PS0_1=0 – PD6_1=0 P6 2 RxD0 input PS0_2=0 – PD6_2=0 P6 3 TxD0 output PS0_3=1 –– P6 4 CTS1 input PS0_4=0 – PD6_4=0 RTS1 output PS0_4=1 PSL0_4=0 – P6 5 CLK1 input PS0_5=0 – PD6_5=0 P6 6 RxD1 input PS0_6=0 – PD6_6=0 P6 7 TxD1 output PS0_7=1 –– Table 16.9 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 P7 2 CLK2 input PS1_2=0 –– PD7_2=0 P7 3 CTS2 input PS1_3=0 –– PD7_3=0 RTS2 output PS1_3=1 PSL1_3=0 PSC_3=0 – NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.10 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PD9 Register (1) P9 0 CLK3 input PS3_0=0 – PD9_0=0 P9 1 RxD3 input PS3_1=0 – PD9_1=0 P9 2 TxD3 output PS3_2=1 PSL3_2=0 – P9 3 CTS3 input PS3_3=0 PSL3_3=0 PD9_3=0 RTS3 output PS3_3=1 –– P9 4 CTS4 input PS3_4=0 PSL3_4=0 PD9_4=0 RTS4 output PS3_4=1 –– P9 5 CLK4 input PS3_5=0 PSL3_5=0 PD9_5=0 P9 6 TxD4 output PS3_6=1 –– P9 7 RxD4 input PS3_7=0 – PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers set immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 191 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (UART))T38/C23M,38/C23M(puorG38/C23M Stop bit Stop bit Start bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1STSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SPSP TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register Start bit Parity bit TxDi CTSi "1" "0" "1" "L" "H" IR bit in SiTIC register Set to "0" by an interrupt request acknowledgement or by program TE bit in UiC1 register TI bit in UiC1 register TxDi TXEPT bit in UiC0 register "0" "1" "0" "1" "0" "1" i=0 to 4 The above timing applies under the following conditions:

The PRYE bit in the UiMR register is set to "0" (parity disabled)
The STPS bit in the UiMR register is set to "1" (2 stop bits)
The CRD bit in the UiC0 register is set to "1" (CTS function disabled)
The UilRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) Transfer Clock Tc Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj: count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m: setting value of the UiBRG register NOTE: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). IR bit in SiTIC register "0" "1" Tc Transfer Clock Pulse stops because the TE bit is set to "0"Stop bit Data is transferred from the UiTB register to the UARTi transmit register The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin, when the stop bit state is verified. The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin Data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register Data is set in the UiTB register"0" i=0 to 4 The above timing applies under the following conditions:
The PRYE bit in the UiMR register is set to "1" (parity enabled)
The STPS bit in the UiMR register is set to "0" (1 stop bit)
The CRD bit in the UiC 0 register is set to "0" and the CRS bit is set to "0" (CTS function selected)
The UilRS bit in the UiC1 register is set to "1" (transmission completed) Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj: count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m: setting value of the UiBRG register NOTE: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (1) 8-bit Data Transmit Timing (with a parity and 1 stop bit) (2) 9-bit Data Transmit Timing (with no parity and 2 stop bits) "1" "0" "1" "0" Set to "0" by an interrupt request acknowledgement or by program SP SP Figure 16.14 Transmit Operation

Page 192 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (UART))T38/C23M,38/C23M(puorG38/C23M D 0Start bit Determine if it is "L" Capture a received data Count Source set in UiBRG register RE bit in UiC1 register RxDi Transfer Clock RI bit in UiC1 register RTSi Stop bit "1" "0" "0" "1" "H" "L" IR bit in SiRIC register "0" "1" Data is transferred from the URTi receive register to the UiRB register Start receiving when the transfer clock is generated on the falling edge of the start bit D 7D 1 Set to "0" by an interrupt request acknowledgement or by program Change to "L" by reading the UiRB register 8-bit Data Reception Timing (with no parity and 1 stop bit) i=0 to 4 NOTES: 1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled), the SRPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set to "1" (RTS function selected). Figure 16.15 Receive Operation

16.2.1 Bit Rate

In UART mode, bit rate is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4) register and again divided by 16. Table 16.11 lists an example of bit rate setting. Table 16.11 Bit Rate etaRtiB )spb( tnuoC ecruoS fo GRBiU :kcolCnoitcnuFlarehpireP zHM61 :kcolCnoitcnuFlarehpireP zHM42 :kcolCnoitcnuFlarehpireP zHM23 eulaVgnitteS :GRBiUfo n etaRtiBlautcA )spb( eulaVgnitteS :GRBiUfo n etaRtiBlautcA )spb( eulaVgnitteS :GRBiUfo n etaRtiBlautcA )spb( 00218 f) h76(3012 021) h69(5512 021) hFC(7022 021 00428 f) h33(154 042) h64(774 042) h76(3014 042 00848 f) h91(528 084) h62(838 084) h33(158 084 00691 f) h76(3015 169) h69(5515 169) hFC(7025 169 004411 f) h44(863 9441) h76(3013 2441) hA8(8318 8341 002911 f) h33(151 3291) h64(771 3291) h76(3011 3291 008821 f) h22(431 7582) h33(156 4882) h44(866 8982 052131 f) hF1(130 5213) hF2(740 5213) hF3(360 5213 004831 f) h91(522 6483) h62(832 6483) h33(152 6483 002151 f) h31(910 0005) hC1(824 2715) h62(832 8215

Page 193 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (UART))T38/C23M,38/C23M(puorG38/C23M ST : Start bit P : Parity bit SP : Stop bit CLKi TxD i RxD i D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 P SPST SPST P (1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first) P SPST SPST P (2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first) CLKi TxD i RxD i NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (no inverse). D

0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

16.2.2 Selecting LSB First or MSB First

As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format. This function is available for 8-bit transfer data. Figure 16.16 Transfer Format

16.2.3 Serial Data Logic Inverse

After the UiLCH bit in the UiC1 register is set to "1", data logic is inversed when writing to the UiTB register (i=0 to 4) and reading from the UiRB register. Figure 16.17 shows a switching example of the serial data logic. P SPST SPST P TxD i (no inverse) Transfer Clock“H ” “L” “H ” “L” (1) When the UiLCH bit in the UiC1 register (i=0 to 4) = 0 (no inverse) TxD i (inverse) “H ” “L” Transfer Clock “H ” “L” (2) When the UiLCH bit in the UiC1 register = 1 (inverse) NOTES: 1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Figure 16.17 Serial Data Logic Inverse

Page 194 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (UART))T38/C23M,38/C23M(puorG38/C23M P SPST SPST P P SPST SPST P TxD i (no inverse) Transfer Clock“H ” “L” “H ” “L” (1) When the IOPOL bit in the UiMR register (i=0 to 4) is set to "0" (no inverse) RxD i (no inverse) “H ” “L” TxD i (inverse) Transfer Clock“H ” “L” “H ” “L” (2) When the IOPOL bit in the UiMR register is set to "1" ( inverse) RxD i (inverse) “H ” “L” NOTES: 1. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). ST : Start bit P : Even parity SP : Stop bit D D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

16.2.4 TxD and RxD I/O Polarity Inverse

TxD pin output and RxD pin input are inversed. All I/O data level, including the start bit, stop bit and parity bit, are inversed. Figure 16.18 shows TxD and RxD I/O polarity inverse. Figure 16.18 TxD, RxD I/O Polarity Inverse

Page 195 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M

16.3 Special Mode 1 (I2C Mode)

I2C mode is a mode to communicate with external devices with a simplified I2C . Table 16.12 lists specifi- cations of I2C mode. Table 16.13 lists registers to be used and settings, Table 16.14 lists each function. Figure 16.19 shows a block diagram of I2C mode. Figure 16.20 shows timings for transfer to the UiRB register and interrupts. Tables 16.14 to 16.16 list pin settings. As shown in Table 16.14, I2C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to "0102" and the IICM bit in the UiMR register is set to "1". SDAi output changes after SCLi becomes low ("L") and stabilizes due to a SDAi output via the delay circuit. Table 16.12 I2C Mode Specifications Item Specifications Interrupt Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment detect Selectable Function • Arbitration lost The update timing of the ABT bit in the UiRB register can be selected. Refer to 16.3.3 Arbitration.

SDAi digital delay Selected from no digital delay or 2 to 8 cycle delay of the count source of BRG. Refer to 16.3.5 SDA Output.
Clock phase setting Selected from clock delay or no clock delay. Refer to 16.3.4 Transfer Clock.

Page 196 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M I/O Timer Delay Circuit UARTi Receive Register External Clock Arbitration Detects Start Condition Detects Stop Condition Falling edge detect UARTi Transmission NACK Interrupt Request UARTi Reception ACK Interrupt Request DMAi Request 9th Pulse Port reading * When the IICM bit is set to "1", port pin can be read regardless of the direction register being set to "1". i=0 to 4 NOTES: 1. Set the PSj (j=0,1,3), PSLj or PSC register to determine. IICM : Bit in the UiSMR register IICM2 : Bit in the UiSMR2 register LSYN bit Bus Conflict Start Condition Detect Stop Condition Detect Interrupt Request Bus Conflict Detect I/O Noise Filter SDAi SCLi CLK Control Internal ClockUARTi UARTi I/0 Timer CLK i Data Register D T Q D T Q D T Q NACK ACK UARTi UARTi R IICM IICM=1 and IICM2=0 IICM IICM=1 IICM=0 S R Q Bus busy IICM ALS R S SWC Falling Edge of 9th Pulse IICM=1 and IICM2=0 IICM=0 or IICM2=1 IICM=0 or IICM2=1 SWC2 SDHI To DMAi To DMAi Transmit Register UARTi (Note1) (Note 1) Noise Filter Noise Filter IICM (Note 1) Figure 16.19 I2C Mode Block Diagram

Page 197 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.13 Registers To Be Used and Settings (I2C Mode) Register Bit Function Master Slave UiTB 0 to 7 Set transmit data UiRB 0 to 7 Received data can be read

8 ACK or NACK bit can be read

ABT Arbitration lost detect flag Disabled OER Overrun error flag UiBRG 0 to 7 Set bit rate Disabled UiMR SMD2 to SMD0 Set to "010 2" CKDIR Set to "0" Set to "1" IOPOL Set to "0" UiC0 CLK1 to CLK0 Select count source of the UiBRG register Disabled CRS Disabled because CRD = 1 TXEPT Transfer register empty flag CRD, NCH Set to "1" CKPOL Set to "0" UFORM Set to "1" UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiRRM, UiLCH, Set to "0" UiERE UiSMR IICM Set to "1" ABC Select an arbitration lost detect timing Disabled BBS Bus busy flag 3 to 7 Set to "00000 2" UiSMR2 IICM2 See Table 16.14 CSC Set to "1" to enable clock synchronization Set to "0" SWC Set to "1" to output fixed "L" from the SDAi on the falling edge of the ninth bit of the transfer clock ALS Set to "1" to terminate SDA output when Not used. Set to "0" detecting the arbitration lost STC Not used. Set to "0" Set to "1" to reset UARTi by detecting a start condition SWC2 Set to "1" to forcibly output an "L" signal from SCL SDHI Set to "1" to disable SDA output SU1HIM Set to "0" UiSMR3 SSE Set to "0" CKPH See Table 16.14. DINC, NODC, ERR Set to "0" DL2 to DL0 Set digital delay value UiSMR4 STAREQ Set to "1" when generating start condition Not used. Set to "0" RSTAREQ Set to "1" when generating restart condition STPREQ Set to "1" when generating stop condition STSPSEL Set to "1" when using a condition generating function ACKD Select ACK or NACK ACKC Set to "1" to output ACK data SCLHI Set to "1" to enable SCL output stop when Not used. Set to "0" detecting stop condition SWC9 Not used. Set to "0" Set to "1" to output fixed "L" from SCLi on the falling edge of the ninth bit of the transfer clock IFSR IFSR6, IFSR7 Set to "1" i=0 to 4

Page 198 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M noitcnuF suonorhcnySkcolC edoMO/IlaireS 100=0DMSot2DMS( 2, )0=MCII I2 010=0DMSot2DMS(edoMC 2 )1=MCII, 0=2MCII )tpurretniKCA/KCAN( 1=2MCII )tpurretnieviecerTRAU/timsnartTRAU( 0=HPKC )yaledkcolcoN( 1=HPKC )yaledkcolC( 0=HPKC )yaledkcolcoN( 1=HPKC )yaledkcolC( ot93srebmuNtpurretnI detareneG14 )1( )02.61erugiFeeS( - )71.61elbaTeeS(tcetednoitidnocpotsronoitidnoctratS ,91,71rebmuNtpurretnI 73dna53,33 detareneG )1( )02.61erugiFeeS( -noissimsnarTiTRAU rodetratsnoissimsnarT ybdetceles(detelpmoc )retsigerSRIiUeht tceteDtnemegelwonkcAoN -)KCAN( iLCSfotibht9foegdegnisiR iTRAU -noissimsnarT foegdegnisiR iLCSfotibht9 -noissimsnarTiTRAU ehtretfaegdegnillaftxeN iLCSfotibht9 ,02,81srebmuNtpurretnI 83dna63,43 detareneG )1( )02.61erugiFeeS( -noitpeceRiTRAU tibht8tagnivieceR )egdegnisir(0=LOPKC )egdegnillaf(1=LOPKC tceteDtnemegelwonkcA) KCA(- iLCSfotibht9foegdegnisiR -noitpeceRiTRAU iLCSfotibht9foegdegnillaF morfgnimiTrefsnarTataD tfihSevieceRTRAUeht retsigeRBRiUehtotretsigeR )egdegnisir(0=LOPKC )egdegnillaf(1=LOPKC iLCSfotibht9foegdegnisiR foegdegnillaF iLCSfotibht9 egdegnisirdnaegdegnillaF iLCSfotibht9fo tuptuOtimsnarTiTRAU yaleD yaledoNy aleD 6P 3 6P, 7 7P, 0 9P, 2 9P, 6 snoitcnuFniP tuptuoiDxTt uptuodnatupniiADS 6P 2 6P, 6 7P, 1 9P, 1 9P, 7 snoitcnuFniP tupniiDxRt uptuodnatupniiLCS 6P 1 6P, 5 7P, 2 9P, 0 9P, 5 snoitcnuFniP rotupniiKLCtceleS tuptuo InidesutoN(– 2 )edomC htdiWretliFesioNs n51s n002 iLCSdnaiDxRgnidaeR sleveLniP tropfidaerebnaC "0"ottessitibnoitcerid tibnoitceridtropehtfosseldragerdaerebnaC ,iDxTfoeulaVtluafeD tuptuOiADS )H(0=LOPKC )L(1=LOPKC IgniretneerofebretsigertropehtnitesseulaV 2 edomC )2( dnEdnatluafeDiLCS eulaV – HL HL detareneGAMD )02.61erugiFeeS( noitpeceriTRAU cetedtnemegelwonkcAt )KCA( -noitpeceRiTRAU iLCSfotib9foegdegnillaF ataDdevieceRerotS ehtfostibht8otts1 derotseraataddeviecer ehtni7ot0stibotni retsigerBRiU deviecerehtfostibht8otts1 0ot7stibotniderotseraatad retsigerBRiUehtni derotseraataddeviecerehtfostibht7otts1 sitibht8.retsigerBRiUehtni0ot6stibotni .retsigerBRiUehtni8tibotniderots otniderotserastibht8otts1 retsigerBRiUehtni0ot7stib )3( ataDdevieceRgnidaeRd aersisutatsretsigerBRiUehT BRiUehtni0ot6stiB stretsiger )4( 7tibsadaerera BRiUehtni8tiB.1ot 0tibsadaersiretsiger Table 16.14 I2C Mode Functions i=0 to 4 NOTES: 1. Follow the procedures below to change how an interrupt is generated. (a) Disable interrupt of corresponding interrupt number. (b) Change how an interrupt is generated. (c) Set the IR bit of a corresponding interrupt number to "0" (no interrupt requested). (d) Set the ILVL2 to ILVL0 bits of a corresponding interrupt number. 2. Set default value of the SDAi output when the SMD2 to SMD0 bits in the UiMR register are set to "000 (serial I/O disabled). 3. Second data transfer to the UiRB register (on the rising edge of the ninth bit of SCLi). 4. First data transfer to the UiRB register (on the falling edge of the ninth bit of SCLi).

Page 199 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M (4) When IICM2 is set to "1" and CKPH is set to "1" (3) When IICM2 is set to "1" (UART transmit or receive interrupt) and CKPH is set to "0" SDAi SCLi Receive interrupt (DMA request) Transmit interrupt SDAi SCLi i=0 to 4 IICM2 : Bit in the UiSMR2 register CKPH : Bit in the UiSMR3 regiser The above timing applies to the following setting :

CKDIR bit in the UiMR register = 1 (select slave) (1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay) D 6 D 5 D 4 D 3 D 2 D 1 D 8 (ACK or NACK)D 7SDAi SCLi D 0 ACK interrupt (DMA request) or NACK interrupt (2) When IICM2 is set to "0" and CKPH is set to "1" (clock delay) SDAi SCLi 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15
•• b9 b8 b7 b0 D 8 Contents of the UiRB register b15
•• b9 b8 b7 b0 b15
•• b9 b8 b7 b0 b15
•• b9 b8 b7 b0 b15
•• b9 b8 b7 b0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 6 D 5 D 4 D 3 D 2 D 1D 7 D 0 ACK interrupt (DMA request) or NACK interrupt D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 6 D 5 D 4 D 3 D 2 D 1D 7 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1D 0 D 6 D 5 D 4 D 3 D 2 D 1D 7 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1D 0 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D 8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D 8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit Data is transferred to the UiRB register Data is transferred to the UiRB register Data is transferred to the UiRB register. Receive interrupt (DMA request) Transmit interrupt Data is transferred to the UiRB register. Data is transferred to the UiRB register Contents of the UiRB register Contents of the UiRB register Contents of the UiRB registerContents of the UiRB register Figure 16.20 UiRB Register Transfer and Interrupt Timings Table 16.15 Pin Settings in I2C Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P62 SCL0 output PS0_2=1 PSL0_2=0 - SCL0 input PS0_2=0 - PD6_2=0 P63 SDA0 output PS0_3=1 - - SDA0 input PS0_3=0 - PD6_3=0 P66 SCL1 output PS0_6=1 PSL0_6=0 - SCL1 input PS0_6=0 - PD6_6=0 P67 SDA1 output PS0_7=1 - - SDA1 input PS0_7=0 - PD6_7=0

Page 200 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.16 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) SDA2 output PS1_0=1 PSL1_0=0 PSC_0=0 - SDA2 input PS1_0=0 - - PD7_0=0 P71(1) SCL2 output PS1_1=1 PSL1_1=0 PSC_1=0 SCL2 input PS1_1=0 - - PD7_1=0 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.17 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PD9 Register (1) P9 1 SCL3 output PS3_1=1 PSL3_1=0 - SCL3 input PS3_1=0 - PD9_1=0 P9 2 SDA3 output PS3_2=1 PSL3_2=0 - SDA3 input PS3_2=0 - PD9_2=0 P9 6 SDA4 output PS3_6=1 - - SDA4 input PS3_6=0 - PD9_6=0 P9 7 SCL4 output PS3_7=1 PSL3_7=0 - SCL4 input PS3_7=0 - PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

16.3.1 Detecting Start Condition and Stop Condition

The microcomputer detects either a start condition or stop condition. The start condition detect interrupt is generated when the SCLi (i=0 to 4) pin is held high ("H") and the SDAi pin changes high ("H") to low ("L"). The stop condition detect interrupt is generated when the SCLi pin is held high ("H") and the SDAi pin changes low ("L") to high ("H"). The start condition detect interrupt shares interrupt control registers and vectors with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which interrupt is requested. Setup time Hold time SCLi SDAi (Start condition) SDAi (Stop condition) 3 to 6 cycles < setup time(1) 3 to 6 cycles < hold time(1) i=0 to 4 NOTES: 1. These cycles are main clock generation frequency cycles (XIN). Figure 16.21 Start Condition or Stop Condition Detect

Page 201 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Function Start condition and stop condition output Timing to generate a start condition and stop condition interrupt request STSPSEL = 1 The STAREQ bit, RSTAREQ bit and STPREQ bit determine how the start condition or stop condition is output Start condition and stop condition generation are completed STSPSEL = 0 Program with a port determines how the start condition or stop condition is output The start condition and stop condition are detected SDAi Start condition detect interrupt Stop condition detect interrupt (1) In slave mode, CKDIR is set to "1" (external clock) STSPSEL is set to "0" (no start condition and stop condition output) SCLi SDAi Start condition detect interrupt Stop condition detect interrupt SCLi STAREQ=1 (start) STPREQ=1 (start) (1) In master mode, CKDIR is set to "0" (internal clock) STSPSEL is set to "1" (start condition and stop condition output) 0 1 0 01Setting value of the STSPEL bit i=0 to 4

16.3.2 Start Condition or Stop Condition Output

The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1" (start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1" (start). The stop condition is generated when the STPREQ bit in the UiSMR4 is set to "1" (start). The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4 register is set to "1" (start or stop condition generation circuit selected). The restart condition is output when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition is output when the STPREQ bit and the STSPSEL bit are set to "1". When the start condition, stop condition or restart condition is output, do not generate an interrupt be- tween the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the STSPSEL bit is set to "1". Table 16.18 lists function of the STSPSEL bit. Figure 16.22 shows functions of the STSPSEL bit. Table 16.18 STSPSEL Bit Function Figure 16.22 STSPSEL Bit Function

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16.3.3 Arbitration

The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB register. On the rising edge of SCLi, the microcomputer determines whether a transmit data matches data input to the SDAi pin. When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" as soon as a data discrepancy is detected. The ABT bit is set to "0" if not detected. When the ABC bit is set to "1", the ABT bit is set to "1" (detected-arbitration is lost) on the falling edge of the ninth bit of the transfer clock if any discrepancy is detected. When the ABT bit is updated per byte, set the ABT bit to "0" (not detected-arbitration is won) between an ACK detection in the first byte data and the next byte data to be transferred. When the ALS bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost occurs. As soon as the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state.

16.3.4 Transfer Clock

The transfer clock transmits and receives data as is shown in Figure 16.22 The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi) with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous en- abled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal input to the SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals from the internal SCLi and the SCLi pin. The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit is set to "1". The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to output an "L" signal on the falling edge of the ninth cycle of the transfer clock or not. When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop condition is detected (high-impedance). When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin forcibly outputs an "L" signal while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC2 bit to "0" (transfer clock) and the transfer clock is input to and output from the SCLi pin. When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to "1" (SCL "L" hold enabled), the SCLi pin is fixed to output an "L" signal on the next falling edge after the ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to "0" (SCL "L" hold disabled).

16.3.5 SDA Output

Values in bits 7 to 0 (D7 to D0) in the UiTB register (i=0 to 4) are output in descending order from D7. The ninth bit (D8) is ACK or NACK. Set the default value of SDAi transmit output when the IICM bit is set to "1" (I2C mode) and the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled). The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8 UiBRG register count source cycles. When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly placed in a high-impedance state. Do not set in the SDHI bit on the rising edge of the URTi transfer clock. The ABT bit in the UiRB register may be set to "1" (detected).

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16.3.6 SDA Input

When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK. When the IICM2 bit is set to "1", the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the UiRB register. Store the eighth bit (D0) into bit 8 in the UiRB register. If the IICM bit in the UiSMR register is set to "1" and the CKPH bit is set to "1", the same data as that of when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising edge of the ninth bit of the transfer clock.

16.3.7 ACK, NACK

When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin outputs the value set in the ACKD bit. If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H") on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock. When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection.

16.3.8 Transmit and Receive Reset

When the STC bit in the UiSMR2 register is set to "1" (UARTi initialization enabled) and a start condition is detected, - the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift register. The first bit starts transmitting when the next clock is input. UARTi output value remains unchanged between when clock is input and when data of the first bit is output. The value remains the same value as when start condition was detected. - the receive shift register is reset and the first bit starts receiving when the next clock is input. - the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes low ("L") on the falling edge of the ninth bit of the transfer clock. If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains unchanged. Select the external clock as the transfer clock when using this function.

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16.4 Special Mode 2

In special mode 2, serial communication between one or multiple masters and multiple slaves is available. The SSi input pin (i=0 to 4) controls the serial bus communication. Table 16.19 lists specifications of special Table 16.19. Special Mode 2 Specifications Item Specification Transfer Data Format Transfer data : 8 bits long Transfer Clock The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected) : fj/2(m+1) fj = f1, f8, f2n(1) m : setting value of the UiBRG register 0016 to FF16 The CKDIR bit to "1" (external clock selected) : input clock from the CLKi pin Transmit/Receive Control SSi input pin function Transmit Start Condition•To start transmitting, the following requirements must be met(2) : - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Receive Start Condition• To start receiving, the following requirement must be met(2) : - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit to "1" (receive enable) - Set the TI bit to "0" (data in the UiTB register) Interrupt Request • Transmit interrupt timing can be selected from the followings: Generation Timing - The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transmission started) - The UiIRS register is set to "1" (transmission completed): when data transmission from UARTi transfer register is completed

Receive interrupt timing When data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection •Overrun error(3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register
Fault error In master mode, the fault error occurs an "L" signal is applied to the SSi pin Selectable Function • CLK polarity Select from the rising edge or falling edge of the transfer clock when transferred data is output and input
LSB first / MSB first Data is transmitted or received in either bit 0 or in bit 7
Continuous receive mode Reception is enabled simultaneously by reading the UiRB register
Serial data logic inverse This function inverses transmitted or received data logically
TxD, RxD I/O polarity Inverse TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
Clock phase Select from one of 4 combinations of transfer data polarity and phases
SSi input pin function Output pin is placed in a high-impedance state to avoid data conflict between master and other masters or slaves NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L"). 3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested).

Page 205 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.20. Registers To Be Used and Settings in Special Mode 2 Register Bit Function UiTB 0 to 7 Set transmit data UiRB 0 to 7 Received data can be read OER Overrun error flag UiBRG 0 to 7 Set bit rate UiMR SMD2 to SMD0 Set to "001 2" CKDIR Set to "0" in master mode or "1" in slave mode IOPOL Set to "0" UiC0 CLK0, CLK1 Select count source for the UiBRG register CRS Disabled since CRD = 1 TXEPT Transfer register empty flag CRD Set to "1" NCH Select the output format of the TxDi pin CKPOL Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in the UiSMR3 register UFORM Select either LSB first or MSB first UiC1 TE Set to "1" to enable data transmission and reception TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select how the UARTi transmit interrupt is generated UiRRM Set to "1" to enable continuous receive mode UiLCH, SCLKSTPB Set to "0" UiSMR 0 to 7 Set to "00 16" UiSMR2 0 to 7 Set to "00 16" UiSMR3 SSE Set to "1" CKPH Clock phase can be set by the combination of the CKPH bit and the CKPOL bit in the UiC0 register DINC Set to "0" in master mode or "1" in slave mode NODC Set to "0" ERR Fault error flag 5 to 7 Set to "000 2" UiSMR4 0 to 7 Set to "00 16" IFSR IFSR6, IFSR7 Select how fault error occurs i=0 to 4

Page 206 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.21 Pin Settings in Special Mode 2 (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P6 0 SS0 input PS0_0=0 – PD6_0=0 P6 1 CLK0 input (slave) PS0_1=0 – PD6_1=0 CLK0 output (master) PS0_1=1 –– P6 2 RxD0 input (master) PS0_2=0 – PD6_2=0 STxD0 output (slave) PS0_2=1 PSL0_2=1 – P6 3 TxD0 output (master) PS0_3=1 –– SRxD0 input (slave) PS0_3=0 – PD6_3=0 P6 4 SS1 input PS0_4=0 – PD6_4=0 P6 5 CLK1 input (slave) PS0_5=0 – PD6_5=0 CLK1 output (master) PS0_5=1 –– P6 6 RxD1 input (master) PS0_6=0 – PD6_6=0 STxD1 output (slave) PS0_6=1 PSL0_6=1 – P6 7 TxD1 output (master) PS0_7=1 –– SRxD1 input (slave) PS0_7=0 – PD6_7=0 Table 16.21 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output (master) PS1_0=1 PSL1_0=0 PSC_0=0 – SRxD2 input (slave) PS1_0=0 –– PD7_0=0 P71(1) RxD2 input (master) PS1_1=0 –– PD7_1=0 STxD2 output (slave) PS1_1=1 PSL1_1=1 PSC_1=0 – P7 2 CLK2 input (slave) PS1_2=0 –– PD7_2=0 CLK2 output (master) PS1_2=1 PSL1_2=0 PSC_2=0 – P7 3 SS2 input PS1_3=0 –– PD7_3=0 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.23 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PD9 Register (1) P9 0 CLK3 input (slave) PS3_0=0 – PD9_0=0 CLK3 output (master) PS3_0=1 –– P9 1 RxD3 input (master) PS3_1=0 – PD9_1=0 STxD3 output (slave) PS3_1=1 PSL3_1=1 – P9 2 TxD3 output (master) PS3_2=1 PSL3_2=0 – SRxD3 input (slave) PS3_2=0 – PD9_2=0 P9 3 SS3 input PS3_3=0 PSL3_3=0 PD9_3=0 P9 4 SS4 input PS3_4=0 PSL3_4=0 PD9_4=0 P9 5 CLK4 input (slave) PS3_5=0 PSL3_5=0 PD9_5=0 CLK4 output (master) PS3_5=1 –– P9 6 TxD4 output (master) PS3_6=1 –– SRxD4 input (slave) PS3_6=0 PSL3_6=0 PD9_6=0 P9 7 RxD4 input (master) PS3_7=0 – PD9_7=0 STxD4 output (slave) PS3_7=1 PSL3_7=1 – NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 207 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M P13 P12 Microcomputer P93(SS 3) P92(TxD 3) P90(CLK 3) P91(RxD 3) P93(SS 3) P92(SRxD 3) P90(CLK 3) P91(STxD 3) P93(SS 3) P92(SRxD 3) P90(CLK 3) P91(STxD 3) Master Slave Slave Microcomputer Microcomputer

16.4.1 SSi Input Pin Function (i=0 to 4)

When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the SSi input pin function is selected, activating the pin function. The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave. When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting deter- mines which master microcomputer is active and when.

16.4.1.1 When Setting the DINC Bit to "1" (Slave Mode)

When an "H" signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a high-imped- ance state and the transfer clock input to the CLKi pin is ignored. When a low-level signal ("L") is applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled.

16.4.1.2 When Setting the DINC Bit to "0" (Master Mode)

When an "H" signal is applied to the SSi pin, serial communication is available due to transmission privilege. The master outputs the transfer clock. When an "L" signal is applied to the SSi pin, it indi- cates that another master is active and TxDi, RxDi and CLKi pins are placed in a high-impedance state. Moreover, a fault error occurs and the IR bit in the BCNiIC register is set to "1" (interrupt requested). The ERR bit in the UiSMR3 register indicates whether a fault error occurs. In master mode, software interrupt numbers 39, 40 and 41 are used for the fault error interrupt. The fault error interrupt is generated when the ERR bit changes "0" to "1". The fault error interrupt of UART0 and of UART3 share an interrupt vector. The fault error interrupt of UART1 and of UART4 share an interrupt vector. The IFSR6 and IFSR7 bits in the IFSR register determine which fault error interrupt is used. Communication is not terminated even if a fault error is generated while communicating. To stop communication, the SMD 2 to SMD0 bit in the UiMR register is set to "000 2" (serial I/O disabled). ___ Figure 16.23 Serial Bus Communication Control with SS Pin

Page 208 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Input Signal to the SS Pin in the Master Data Output Timing Data Input Timing D 0 D 1 D 2 D 3 D 4 D 6 D 7D 5 "H" "L" Clock Output (CKPOL=0, CKPH=0) "H" "L" Clock Output (CKPOL=1, CKPH=0) "H" "L" Clock Output (CKPOL=0, CKPH=1) "H" "L" Clock Output (CKPOL=1, CKPH=1) "H" "L" "H" "L"

16.4.2 Clock Phase Setting Function

The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four combinations of transfer clock polarity and phases. The transfer clock phase and polarity must be the same between the master and the slave involved in the transfer.

16.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))

Figure 16.24 shows transmit and receive timing.

16.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))

When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the transfer clock. Figure 16.25 shows the transmit and receive timing. When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high ("H"), the STxDi pin is placed in a high-impedance state. When the SSi pin becomes low ("L"), the first data is output. The serial transmission is synchronized with the transfer clock. Figure 16.26 shows the transmit and receive timing. Figure 16.24 Transmit and Receive Timing in Master Mode (Internal Clock)

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16.5 Special Mode 3 (GCI Mode)

In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial I/O mode. Table 16.24 lists specifications of GCI mode. Table 16.25 lists registers to be used and settings. Tables 16.25 to 16.27 list pin settings. Table16.24 GCI Mode Specifications Item Specification Transfer Data Format Transfer data : 8 bits long Transfer Clock The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected): an input from the CLKi pin Clock Synchronization Function The CTSi pin inputs a trigger Transmit/Receive Start When a trigger signal is applied to the CTSi pin under the following conditions: Conditions • Set the TE bit in the UiC1 register to "1" (transmit enable)

Set the RE bit in the UiC1 register to "1" (receive enable)
Set the TI bit in the UiC1 register to "0" (data in UiTB register) Interrupt Request Transmit interrupt timing can be selected from the followings: Generation Timing • The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty) : when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
The UiIRS bit is set to "1" (transmit completed): when a data transmission from the UARTi transfer register is completed Receive interrupt timing when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection Overrun error (1) This error occurs when the seventh bit of the next received data is read before reading the UiRB register. NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested).

Page 211 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.25 Registers To Be Used and Settings in GCI Mode Register Bit Function UiTB 0 to 7 Set transmit data UiRB 0 to 7 Received data OER Overrun error flag UiBRG 0 to 7 Set to "00 16" UiMR SMD2 to SMD0 Set to "001 2" CKDIR Set to "1" IOPOL Set to "0" UiC0 CLK1 to CLK0 Set to "00 2" CRS Disabled because CRD = 1 TXEPT Transfer register empty flag CRD Set to "1" NCH Select the output format of the TxDi pin CKPOL Set to "0" UFORM Set to "0" UiC1 TE Set to "1" to enable data transmission and reception TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select how the UARTi transmit interrupt is generated UiRRM, UiLCH Set to "0" SCLKSTPB Set to "0" UiSMR 0 to 6 Set to "0000000 2" SCLKDIV See Table 16.29 UiSMR2 0 to 6 Set to "0000000 2" SU1HIM See Table 16.29 UiSMR3 0 to 2 Set to "000 2" NODC Set to "0" 4 to 7 Set to "0000 2" UiSMR4 0 to 7 Set to "00 16" i=0 to 4

Page 212 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.26 Pin Settings in CGI Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P6 0 CTS0 input(1) PS0_0=0 – PD6_0=0 P6 1 CLK0 input PS0_1=0 – PD6_1=0 P6 2 RxD0 input PS0_2=0 – PD6_2=0 P6 3 TxD0 output PS0_3=1 –– P6 4 CTS1 input(1) PS0_4=0 – PD6_4=0 P6 5 CLK1 input PS0_5=0 – PD6_5=0 P6 6 RxD1 input PS0_6=0 – PD6_6=0 P6 7 TxD1 output PS0_7=1 –– NOTES: 1. CTS input is used to input a trigger. Table 16.27 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 P7 2 CLK2 input PS1_2=0 –– PD7_2=0 P7 3 CTS2 input(2) PS1_3=0 –– PD7_3=0 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. 2. CTS input is used to input a trigger. Table 16.28 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PD9 Register (1) P9 0 CLK3 input PS3_0=0 – PD9_0=0 P9 1 RxD3 input PS3_1=0 – PD9_1=0 P9 2 TxD3 output PS3_2=1 PSL3_2=0 – P9 3 CTS3 input(2) PS3_3=0 PSL3_3=0 PD9_3=0 P9 4 CTS4 input(2) PS3_4=0 PSL3_4=0 PD9_4=0 P9 5 CLK4 input PS3_5=0 PSL3_5=0 PD9_5=0 P9 6 TxD4 output PS3_6=1 –– P9 7 RxD4 input PS3_7=0 – PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. 2. CTS input is used to input a trigger.

Page 213 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M To generate the internal clock synchronized with the external clock, first set the SU1HIM bit in the UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 16.29. Then apply a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an external clock operation. Figure 16.27 shows an example of the clock-divided synchronous function. Table 16.29 Clock-Divided Synchronous Function Select SCLKDIV Bit in SU1HIM Bit in Clock-Divided Synchronous Function Example of Waveform UiSMR Register UiSMR2 Register 0 0 Not synchronized - 0 1 Same division as the external clock A in Figure 16.27 1 0 or 1 Same division as the external clock B in Figure 16.27 divided by 2 i=0 to 4 Figure 16.27 Clock-Divided Synchronous Function Trigger Signal from the CTSi Pin External Clock from the CLKi Pin Transfer Clock TxDi A Transfer Clock i=0 to 4 A, B : See Table 16.29. TxDi B 12345678 12345678 1234567 8 The SCLKSTPB bit in the UiC1 register stops the clock

Page 214 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M

16.6 Special Mode 4 (IE Mode)

In IE mode, devices connected with the IEBus can communicate in UART mode. Table 16.30. Registers To Be Used and Settings in IE Mode Register Bit Function UiTB 0 to 8 Set transmit data UiRB 0 to 8 Received data can be read OER, FER, Error flags PER, SUM UiBRG 0 to 7 Set bit rate UiMR SMD2 to SMD0 Set to "110 2" CKDIR Select the internal clock or external clock STPS Set to "0" PRY Disabled because PRYE=0 PRYE Set to "0" IOPOL Select TxD and RxD I/O polarity UiC0 CLK1 to CLK0 Select the count source for the UiBRG register CRS Disabled because CRD=1 TXEPT Transfer register empty flag CRD Set to "1" NCH Select output format of the TxDi pin CKPOL Set to "0" UFORM Set to "0" UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select how the UARTi transmit interrupt is generated UiRRM, UiLCH, Set to "0" SCLKSTPB UiSMR 0 to 3 Set to "0000 2" ABSCS Select bus conflict detect sampling timing ACSE Set to "1" to automatically clear the transmit enable bit SSS Select transmit start condition SCLKDIV Set to "0" UiSMR2 0 to 7 Set to "00 16" UiSMR3 0 to 7 Set to "00 16" UiSMR4 0 to 7 Set to "00 16" IFSR IFSR6, IFSR7 Select how the bus conflict interrupt occurs i=0 to 4

Page 215 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.31 Pin Settings in IE Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P61 CLK0 input PS0_1=0 – PD6_1=0 CLK0 output PS0_1=1 –– P62 RxD0 input PS0_2=0 – PD6_2=0 P63 TxD0 output PS0_3=1 –– P65 CLK1 input PS0_5=0 – PD6_5=0 CLK1 output PS0_5=1 –– P66 RxD1 input PS0_6=0 – PD6_6=0 P67 TxD1 output PS0_7=1 –– Table 16.32 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 P72 CLK2 input PS1_2=0 –– PD7_2=0 CLK2 output PS1_2=1 PSL1_2=0 PSC_2=0 – NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.33 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PD9 Register (1) P90 CLK3 input PS3_0=0 – PD9_0=0 CLK3 output PS3_0=1 –– P91 RxD3 input PS3_1=0 – PD9_1=0 P92 TxD3 output PS3_2=1 PSL3_2=0 – P95 CLK4 input PS3_5=0 PSL3_5=0 PD9_5=0 CLK4 output PS3_5=1 –– P96 TxD4 output PS3_6=1 –– P97 RxD4 input PS3_7=0 – PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 216 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M If the output level of the TxDi pin (i=0 to 4) differs from the input level of the RxDi pin, an interrupt request is generated. UART0 and UART3 are assigned software interrupt number 40. UART1 and UART4 are assigned number 41. When using the bus conflict detect function of UART0 or UART3, of UART1 or UART4, set the IFSR6 bit and the IFSR7 bit in the IFSR register accordingly. When the ABSCS bit in the UiSMR register is set to "0" (rising edge of the transfer clock), it is determined, on the rising edge of the transfer clock, if the output level of the TxD pin and the input level of the RxD pin match. When the ABSCS bit is set to "1" (timer Aj underflow), it is determined when the timer Aj (timer A3 in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3, the timer A4 in UART4) overflows. Use the timer Aj in one-shot timer mode. When the ACSE bit in the UiSMR register is set to "1" (automatic clear at bus conflict) and the IR bit in the BCNiIC register to "1" (discrepancy detected), the TE bit is set to "0" (transmit disable). When the SSS bit in the UiSMR register is set to "1" (synchronized with RxDi), the TxDi pin starts transmit- ting data on the falling edge of the RxDi pin. Figure 16.28 shows bits associated with the bus conflict detect function.

Page 217 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M (1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected) Bus conflict is detected on the rising edge of the transfer clock when ABSCS is set to "0" Transfer Clock Timer Aj (2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared) IR bit in BCNilC register TE bit in UiC1 register (3) The SSS bit in the UiSMR Register (Transmit start condition selected) TxDi transmit enable conditons are met CLKi TxDi RxDi NOTES: 1. Data is transmitted on the falling edge of RxDi when IOPOL is set to "0". Data is transmitted on the rising edge of RxDi when IOPOL is set to "1". 2. Data transmission condition must be met before the falling edge of RxD. When SSS is set to "0", data is transmitted after one transfer clock cycle if data transmission is enabled. TxDi RxDi ST SP Trigger signal is applied to the TAjIN pin When ABSCS is set to "1", bus conflict is detected when the timer Aj underflows (in the one-shot mode). An interrupt request is generated. Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2 Transfer Clock TxDi RxDi ST SP Transfer Clock ST SP ST D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 SP When SSS is set to "1", data is transmitted on the rising edge of RxDi(1) (Note 2) (i=0 to 4) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 Figure 16.28 Bit Function Related Bus Conflict Detection

Page 218 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M

16.7 Special Mode 5 (SIM Mode)

In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are available and the TxDi pin (i=0 to 4) can output an "L" signal when a parity error is detected. Table 16.34 lists specifications of SIM mode. Table 16.35 lists registers to be used and register settings in SIM mode. Tables 16.36 to 16.38 list the pin settings. Table16.34 SIM Mode Specifications Item Specification Transfer Data Format • Transfer data: 8-bit UART mode

One stop bit
In direct format Parity: Even Data logic: Direct Transfer format: LSB first
In inverse format Parity: Odd Data logic: Inverse Transfer format: MSB first Transfer Clock The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected): fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register 0016 to FF16 Do not set the CKDIR bit to "1" (external clock selected) Transmit/Receive ControlThe CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled) Other Setting Items The UiIRS bit in the UiC1 register is set to "1" (transmission completed) Transmit Start Condition To start transmitting, the following requirements must be met:
Set the TE bit in the UiC1 register to "1" (transmit enable)
Set the TI bit in the UiC1 register to "0" (data being in the UiTB register) Receive Start Condition To start receiving, the following requirements must be met:
Set the RE bit in the UiC1 register to "1" (receive enable)
Detect the start bit Interrupt Request Transmit interrupt timing Generation Timing • The UiIRS bit is set to "1" (transmission is completed): when data transmission from the UARTi transfer register is completed Receive interrupt timing when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection • Overrun error(1) This error occurs when the eighth bit of the next data is received before reading the UiRB register
Framing error This error occurs when the number of the stop bit set is not detected
Parity error This error occurs when the number of "1" in parity bit and character bits differ from the number set.
Error sum flag The SUM bit is set to "1" when an overrun error, framing error or parity error occurs. NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 219 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.35 Registers To Be Used and Settings Register Bit Function UiTB 0 to 7 Set transmit data UiRB 0 to 7 Received data can be read OER, FER, Error flags PER, SUM UiBRG 0 to 7 Set bit rate UiMR SMD2 to SMD0 Set to "101 2" CKDIR Set to "0" STPS Set to "0" PRY Set to "1" for direct format or "0" for inverse format PRYE Set to "1" IOPOL Set to "0" UiC0 CLK1 to CLK0 Select count source for the UiBRG register CRS Disabled because CRD=1 TXEPT Transfer register empty flag CRD Set to "1" NCH Set to "1" CKPOL Set to "0" UFORM Set to "0" for direct format or "1" for inverse format UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Set to "1" UiRRM Set to "0" UiLCH Set to "0" for direct format or "1" for inverse format UiERE Set to "1" UiSMR 0 to 3 Set to "00 16" UiSMR2 0 to 7 Set to "00 16" UiSMR3 0 to 7 Set to "00 16" UiSMR4 0 to 7 Set to "00 16" i=0 to 4

Page 220 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Table 16.36 Pin Settings in SIM Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P6 2 RxD0 input PS0_2=0 – PD6_2=0 P6 3 TxD0 output PS0_3=1 –– P6 6 RxD1 input PS0_6=0 – PD6_6=0 P6 7 TxD1 output PS0_7=1 –– Table 16.37 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.38 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PD9 Register (1) P9 1 RxD3 input PS3_1=0 – PD9_1=0 P9 2 TxD3 output PS3_2=1 PSL3_2=0 – P9 6 TxD4 output PS3_6=1 –– P9 7 RxD4 input PS3_7=0 – PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Figure 16.29 shows an example of a SIM interface operation. Figure 16.30 shows an example of a SIM interface connection. Connect TxDi to RxDi for a pull-up.

Page 221 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Figure 16.29 SIM Interface Operation D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP Start bit Parity bit "0" "1" "0" "1" "0" "1" Set to "0" by an interrupt request acknowledgement or by program Tc Transfer Clock Stop bit Data is written to the UiTB register An "L" signal is applied from the SIM card due to a parity error An interrupt routine detects "H" or "L" TxDi "0" "1" Transfer Clock Read the UiRB register Signal Line Level(3) TxDi Signal Line Level(2) NOTES: 1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit. 2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi pin and parity error signal from the receiving end, is generated. 3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end and parity error signal from the TxDi pin, is generated. 4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15). Data is transferred from the UiTB register to the UARTi transmit register (Note 1) RE bit in the UiC1 register RI bit in the UiC1 register IR bit in the SiRIC register TE bit in the UiC1 register TI bit in the UiC1 register TXEPT bit in the UiC0 register IR bit in the SiTIC registeri=0 to 4 The above applies under the following conditions:

The PRYE bit in the UiMR register is set to "1" (parity enabled)
The STPS bit in the UiMR register is set to "0" (1 stop bit)
The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated when transmission completed) Tc = 16(m+1) / f j fj: count source frequency of the UiBRG register (f1, f8, f2n(4)) m: setting value of the UiBRG register Start bit Set to "0" by an interrupt request acknowledgement or by program Stop bit TxDi outputs "L" due to a parity error i=0 to 4 The above applies under the following conditions:
The PRYE bit in the UiMR register is set to "1" (parity enabled)
The STPS bit in the UiMR register is set to "0" (1 stop bit) Tc = 16(m+1) / f j fj: count source frequency of the UiBRG register (f1, f8, f2n(4)) m: setting value of the UiBRG register Parity bit "0" "1" "0" "0" "1" (1) Transmit Timing (2) Receive Timing Parity Error Signal returned from Receiving End Transmit Waveform from the Transmitting End "1" SP An interrupt routine detects "H" or "L" SP

Page 222 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M Figure 16.30 SIM Interface Connection

16.7.1 Parity Error Signal

16.7.1.1 Parity Error Signal Output Function

When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1", the parity error signal can be output. The parity error signal is output when a parity error is detected upon receiving data. TxDi outputs an "L" signal in the timing shown in Figure 16.31. When reading the UiRB register during a parity error output, the PER bit in the UiRB register is set to "0" and TxDi again outputs an "H" signal simulta- neously.

16.7.1.2 Parity Error Signal

To determine whether the parity error signal is output, the port that shares a pin with RxDi is read by using a transmit complete interrupt routine. Microcomputer SIM card TxD i RxD i i=0 to 4 Figure 16.31 Parity Error Signal Output Timing (LSB First) P SPST Hi-Z RxDi TxDi Recieve Complete Flag "H" "L" "H" "L" "1" "0" NOTES: 1. The above applies to direct format conditions (PRY=1, UFORM=0, UiLCH=0). D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ST : Start bit P : Even parity SP : Stop bit i=0 to 4

Page 223 884fo6002,13.naJ13.1.veR 1310-4300B90JER 16. Serial I/O (Special Function))T38/C23M,38/C23M(puorG38/C23M

16.7.2 Format

16.7.2.1 Direct Format

Set the PRYE bit in the UiMR register (i=0 to 4) to "1", the PRY bit to "1", the UFORM bit in the UiC0 register to "0" and the UiLCH bit in the UiC1 register to "0". When data are transmitted, data set in UiTB register are transmitted with the even-numbered parity, starting from D 0. When data are re- ceived, received data are stored in the UiRB register, starting from D0. The even-numbered parity determines whether a parity error occurs.

16.7.2.2 Inverse Format

Set the PRYE bit to "1", the PRY bit to "0", the UFORM bit to "1" and the UiLCH bit to "1". When data are transmitted, values set in the UiTB register are logically inversed and are transmitted with the odd-numbered parity, starting from D 7. When data are received, received data are logically inversed to be stored in the UiRB register, starting from D7. The odd-numbered parity determines whether a parity error occurs. D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 P Transfer Clock TxD i TxD i D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 P (1) Direct Format Transfer Clock (2) Inverse Format P : Odd parity "H" "L" "H" "L" "H" "L" "H" "L" P : Even parity i=0 to 4 Figure 16.32 SIM Interface Format

Page 224 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M NOTE 17. A/D Converter The A/D converter consists of two 10-bit successive approximation A/D converters, each with a capacitive coupling amplifier. The result of an A/D conversion is stored into the A/D register corresponding to selected pins. Table 17.1 lists specifications of the A/D converter. Figure 17.1 shows a block diagram of the A/D converter. Table 17.2 lists the differences between A/D0 and A/D1 conversions, which share the same conversion method. A/D0 and A/D1 can perform conversions simultaneously. Table 17.3 lists settings of the following pins; AN 0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0, ANEX1 and AD TRG . Figures 17.2 to 17.7 show registers associated with the A/D converter. In this section, the 144-pin package is given as the example. The AN150 to AN157 pins are not included in the 100-pin package.

Page 225 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Table 17.1 A/D Converter Specifications Item Specification A/D Conversion Method Successive approximation (with a capacitive coupling amplifier) Analog Input Voltage(1) 0V to AVCC (VCC ) Operating Clock, Ø AD (2) fAD , fAD /2, fAD /3, fAD /4 Resolution Select from 8 bits or 10 bits Operating Mode One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1 Analog Input Pins(3) 34 pins 8 pins each for AN (AN0 to AN7), AN0 (AN00 to AN07), AN2 (AN20 to AN27), AN15 (AN150 to AN157) 2 extended input pins (ANEX0 and ANEX1) A/D Conversion Start Condition Software trigger

The ADST bit in the ADiCON0 (i=0, 1) register is set to "1" (A/D conversion started) by program
The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a conversion simultaneously) by program External trigger (re-trigger is enabled) When a falling edge is applied to the ADTRG pin after the ADST bit is set to "1" by program Hardware trigger (re-trigger is enabled) One of the following interrupt requests is generated after the ADST bit is set to "1" by program:
The timer B2 interrupt request of the three-phase motor control timer functions (after the ICTB2 counter completes counting)
The intelligent I/O interrupt request Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1) Conversion Rate Per Pin • Without the sample and hold function 8-bit resolution : 49 Ø AD cycles 10-bit resolution : 59 Ø AD cycles
With the sample and hold function 8-bit resolution : 28 Ø AD cycles 10-bit resolution : 33 Ø AD cycles NOTES: 1. Analog input voltage is not affected by the sample and hold function status. 2. Ø AD frequency must be under 16 MHz when VCC =5V. Ø AD frequency must be under 10 MHz when VCC =3.3V. Without the sample and hold function, the Ø AD frequency must be 250 kHz or more. With the sample and hold function, the Ø AD frequency must be 1 MHz or more. 3. AVCC = VREF = VCC , A/D input voltage (for AN0 to AN7, AN00 to AN07, AN2 0 to AN27, AN15 0 to AN157, ANEX0 and ANEX1) ≤ VCC . Table 19.2 Difference between A/D0 and A/D1 Item A/D0 A/D1 Analog Input Pins(1) AN (AN0 to AN7) Select from AN0 (AN0 0 to AN07), AN2 (AN20 to AN27) or AN15 (AN150 to AN157) Extended Analog Input Pins ANEX0, ANEX1 Not provided External Op-Amp(1) Enabled Disabled Intelligent I/O used as a Trigger Channel 1 in group 2 Channel 1 in group 3 NOTES: 1. When the ADS bit in the AD0CON2 register is set to "0" (channel replacement disabled)

Page 226 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M AD10 register AD11 register AD12 register AD13 register AD14 register AD15 register AD16 register AD17 register AD1CON0 register 000 AN0 0 001 AN0 1 010 AN0 2 011 AN0 3 100 AN0 4 AN0 5 101 110 AN0 6 111 AN0 7 000 AN2 0 001 AN2 1 010 AN2 2 011 AN2 3 100 AN2 4 AN2 5 101 110 AN2 6 111 AN2 7

000 AN15 0

(Note 1) (Note 1) (Note 2)

001 AN15 1

010 AN15 2

011 AN15 3

100 AN15 4

110 AN15 6

111 AN15 7

AD1CON1 registerAD0CON1 register 1/21/2 CSK0 bit in AD1CON0 register CSK1 bit in AD1CON1 register CSK0 bit in AD0CON0 register CSK1 bit in AD0CON1 register fAD 1/21/2 fAD ANEX0 ANEX1 OPA1 to OPA0 bits in AD0CON1 register CH2 to CH0 bits in AD0CON0 register CH2 to CH0 bits in AD1CON0 register ADS bit in AD0CON2 register 01 0 1 TRG1 to TRG0 bits in ADiCON2 register 01 1

10 TRG bit in

Intelligent I/O group2 channel 1 interrupt request (A/D0)
Intelligent I/O group3 channel 1 interrupt request (A/D1) Comparator 0 Comparator 1 Decoder Decoder Successive conversion register Resistor ladder Successive conversion register Resistor ladder Ø AD1 i=0,1 NOTES: 1. These pins are available in single-chip mode. 2. These pins are provided in the 144-pin package. APS1 to APS0 bits in AD1CON2 register Ø AD0 Figure 17.1 A/D Converter Block Diagram

Page 227 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Table 17.3 Pin Settings Port Function Bit and Setting Name PD10, PD0, PD2, PS3 (3), PS9 PSL3, IPS PUR0, PUR3, PD15, PD9(3) Registers Registers Registers PUR4 Registers P100 AN 0 PD10_0 = 0 - - PU30 = 0 P101 AN 1 PD10_1 = 0 P102 AN 2 PD10_2 = 0 P103 AN 3 PD10_3 = 0 P104 AN 4 PD10_4 = 0 PU31 = 0 P105 AN 5 PD10_5 = 0 P106 AN 6 PD10_6 = 0 P107 AN 7 PD10_7 = 0 P00 AN0 0(1) PD0_0 = 0 - - PU00 = 0 P01 AN0 1(1) PD0_1 = 0 P02 AN0 2(1) PD0_2 = 0 P03 AN0 3(1) PD0_3 = 0 P04 AN0 4(1) PD0_4 = 0 PU01 = 0 P05 AN0 5(1) PD0_5 = 0 P06 AN0 6(1) PD0_6 = 0 P07 AN0 7(1) PD0_7 = 0 P20 AN2 0(1) PD2_0 = 0 - - PU04 = 0 P21 AN2 1(1) PD2_1 = 0 P22 AN2 2(1) PD2_2 = 0 P23 AN2 3(1) PD2_3 = 0 P24 AN2 4(1) PD2_4 = 0 - - PU05 = 0 P25 AN2 5(1) PD2_5 = 0 P26 AN2 6(1) PD2_6 = 0 P27 AN2 7(1) PD2_7 = 0 P150 AN15 0(2) PD15_0 = 0 PS9_0 = 0 IPS2 = 1 PU42 = 0 P151 AN15 1(2) PD15_1 = 0 PS9_1 = 0 P152 AN15 2(2) PD15_2 = 0 - P153 AN15 3(2) PD15_3 = 0 - P154 AN15 4(2) PD15_4 = 0 PS9_4 = 0 PU43 = 0 P155 AN15 5(2) PD15_5 = 0 PS9_5 = 0 P156 AN15 6(2) PD15_6 = 0 - P157 AN15 7(2) PD15_7 = 0 - P95 ANEX0 PD9_5 = 0 PS3_5 = 0 PSL3_5 = 1 PU27 = 0 P96 ANEX1 PD9_6 = 0 PS3_6 = 0 PSL3_6 = 1 P97 AD TRG PD9_7 = 0 PS3_7 = 0 - - NOTES: 1. This pin is available in single-chip mode. 2. This pin is provided in the 144-pin package. 3. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 228 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Figure 17.2 AD0CON0 Register Function A/D0 Control Register 0(1) Bit NameBit Symbol Symbol Address After Reset AD0CON0 0396 16 00 16 RW RW RW RW RW RW RW RW RW CH0 CH1 CH2 Analog Input Pin Select Bit (2, 3, 4) MD0 MD1 TRG CKS0 ADST A/D Operation Mode Select Bit 0(2) A/D Conversion Start Flag Trigger Select Bit Frequency Select Bit(6) 0 : Software trigger 1 : External trigger, hardware trigger(5) 0 : A/D conversion stops 1 : A/D conversion starts (5) 0 : Select from fAD /3 or fAD /4 1 : Select from fAD /1 or fAD /2 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 b1 b0 0 0 0 : AN0 0 0 1 : AN1 0 1 0 : AN2 0 1 1 : AN3 1 0 0 : AN4 1 0 1 : AN5 1 1 0 : AN6 1 1 1 : AN7 b3b4 CKS0 CKS1 AD 0 0 f AD divided by 4 0 1 f AD divided by 3 1 0 f AD divided by 2 1 1 fAD NOTES: 1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Analog input pins must be set again after changing A/D operation mode. 3. This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. 4. Set the PSC_7 bit in the PSC register to "1" (AN 4 to AN7) to use the P10 pin as a analog input pin. 5. To set the TRG bit to "1", select the cause of trigger by setting the TRG1 and TRG0 bits in the AD0CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1". 6. AD frequency must be under 16 MHz when VCC =5V. AD frequency must be under 10 MHz when VCC =3.3V. Combination of the CKS0 and CKS1 bits selects AD . b7 b6 b5 b4 b3 b2 b1 b0

Page 229 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Function A/D0 Control Register 1(1) Bit NameBit Symbol Symbol Address After Reset AD0CON1 0397 16 00 16 RW RW RW RW RW RW RW RW RW SCAN0 SCAN1 MD2 A/D Sweep Pin Select Bit (2) BITS CKS1 VCUT OPA1 OPA0 8/10-bit Mode Select Bit External Op-Amp Connection Mode Bit (5) 0 : No VREF connection(4) 1 : VREF connection 0 0 : ANEX0 and ANEX1 are not used(6) 0 1 : Signal into ANEX0 is A/D converted 1 0 : Signal into ANEX1 is A/D converted 1 1 : External op-amp connection mode V REF Connection Bit 0 : Select from fAD /2 or fAD /4 1 : Select from fAD /1 or fAD /3 0 : 8-bit mode 1 : 10-bit mode A/D Operation Mode Select Bit 1 0 0 : AN0, AN1 (AN0) 0 1 : AN0 to AN3 (AN0, AN1) 1 0 : AN0 to AN5 (AN0 to AN2) 1 1 : AN0 to AN7 (AN0 to AN3) 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 Frequency Select Bit(3) b1b0 b7b6 NOTES: 1. When the AD0CON1 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. This bit is disabled in one-shot mode and repeat mode. Pins in parentheses are those most commonly used in the A/D conversions when the MD2 bit is set to "1". 3. AD frequency must be under 16 MHz when VCC =5V. AD frequency must be under 10 MHz when VCC =3.3V. Combination of the CKS0 and CKS1 bits selects AD (see the AD0CON0 register). 4. Do not set the VCUT bit to "0" during the A/D conversion. This is a reference voltage for the A/D0. It does not affect D/A conversion. 5. In single sweep mode and repeat sweep mode 0 or 1, the OPA1 and OPA0 bits cannot be set to "012"or "102". 6. When the OPA1 to OPA0 bits is set to "002", set the PSL3_5 bit in PSL3 register to "0" (other than ANEX0) and the PSL3_6 bit to "0" (other than ANEX1). b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.3 AD0CON1 Register

Page 230 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Function A/D0 Control Register 2(1) Bit NameBit Symbol Symbol Address After Reset AD0CON2 0394 16 X000 0000 2 RW RW RW RW RW RW WO SMP ADS (b3 - b1) TRG0 TRG1 A/D Conversion Method Select Bit 0 : Without the sample and hold function 1 : With the sample and hold function Reserved Bit Set to "0" 0 : Disables channel replacement 1 : Enables channel replacement(5) PST External Trigger Request Cause Select Bit A/D Channel Replace Select Bit (2) Simultaneous Start Bit (2, 3, 4) b6 b5 When this bit is set to "1", A/D0 and A/D1 start conversions simultaneously. When read, its content is indeterminate. 0 0 : Selects ADTRG 0 1 : Selects a timer B2 interrupt request of the three-phase motor control timer functions (after ICTB2 counter completes counting) 1 0 : Selects the intelligent I/O group 2 channel 1 interrupt 1 1 : Do not set to this value NOTES: 1. When the AD0CON2 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Do not set the APS1 and APS0 bits to "1" while either A/D0 or A/D1 is operating. 3. The PST bit is enabled when the TRG bit in the AD0CON0 register is set to "0" (software trigger). Do not set the PST bit to "1" when the TRG bit is set to "1" (external trigger). 4. Set both A/D0 and A/D1 to the same setting. 5. If the ADS bit is set to "1", do not select single sweep mode or repeat sweep mode as the A/D operation mode. b7 b6 b5 b4 b3 b2 b1 b0 000 Figure 17.4 AD0CON2 Register, AD00 to AD07 Registers Function A/D0 Register i (i =0 to 7) Symbol Address After Reset AD00 to AD02 0381 16 - 038016, 038316 - 038216, 038516 - 038416 Indeterminate AD03 to AD05 0387 16 - 038616, 038916 - 038816, 038B16 - 038A16 Indeterminate AD06 to AD07 038D 16 - 038C16, 038F16 - 038E16 Indeterminate RW RO RO 8 low-order bits in an A/D conversion result Nothing is assigned. When write, set to "0". When read, its content is indeterminate. In 10-bit mode In 8-bit mode : 2 high-order bits in an A/D conversion result : When read, its contents is indeterminate. b7 b0b15 b8

Page 231 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Figure 17.5 AD1CON0 Register Function A/D1 Control Register 0(1) Bit NameBit Symbol Symbol Address After Reset AD1CON0 01D6 16 00 16 RW RW RW RW RW RW RW RW RW CH0 CH1 CH2 Analog Input Pin Select Bit (2, 3, 4, 5, 6) MD0 MD1 TRG CKS0 ADST A/D Operation Mode Select Bit 0(2) A/D Conversion Start Flag Trigger Select Bit Frequency Select Bit(8) 0 : Software trigger 1 : External trigger, hardware trigger(7) 0 : A/D conversion stops 1 : A/D conversion starts(7) 0 : Select from fAD /3 or fAD /4 1 : Select from fAD /1 or fAD /2 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 0 0 0 : ANi0 0 0 1 : ANi1 0 1 0 : ANi2 0 1 1 : ANi3 1 0 0 : ANi4 1 0 1 : ANi5 1 1 0 : ANi6 1 1 1 : ANi7 b2 b1 b4 b3 (i=0, 2, 15) CKS0 CKS1 AD 0 0 f AD divided by 4 0 1 f AD divided by 3 1 0 f AD divided by 2 1 1 fAD NOTES: 1. When the AD1CON0 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Set analog input pins again after changing A/D operation mode. 3. This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. 4. The APS1 to APS0 bit in the AD1CON2 register select i=0, 2 or 15. 5. i=0 or 2 is available in single-chip mode only. 6. i=15 is available in the 144-pin package. 7. To set the TRG bit to "1", select the cause of trigger by setting the the TRG1 and TRG0 bits in the AD1CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1". AD frequency must be under 16 MHz when VCC =5V. AD frequency must be under 10 MHz when VCC =3.3V. Combination of the CKS0 and CKS1 bits selects AD . b7 b6 b5 b4 b3 b2 b1 b0

Page 232 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Function A/D1 Control Register 1(1) Bit NameBit Symbol Symbol Address After Reset AD1CON1 01D7 16 XX00 0000 2 RW RW RW RW RW RW RW SCAN0 SCAN1 MD2 A/D Sweep Pin Select Bit (2, 3, 4) BITS CKS1 VCUT (b7 - b6) 8/10-bit Mode Select Bit VREF Connection Bit0 : VREF not connected(6) 1 : VREF connected Frequency Select Bit(5) 0 : Select from fAD /2 or fAD /4 1 : Select from fAD /1 or fAD /3 0 : 8-bit mode 1 : 10-bit mode A/D Operation Mode Select Bit 1 0 0 : ANi0,ANi1 (ANi0) 0 1 : ANi0 to ANi3 (ANi0,ANi1) 1 0 : ANi0 to ANi5 (ANi0 to ANi2) 1 1 : ANi0 to ANi7 (ANi0 to ANi3) (i=0, 2, 15) 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 b1 b0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. When the AD1CON1 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. This bit is disabled in one-shot mode and repeat mode. Pins in parentheses are those most commonly used for A/D conversions when the MD2 bit is set to "1" (repeat sweep mode 1). 3. The APS1 to APS0 bits in the AD1CON2 register select i=0, 2 or 15. 4. i=15 is available in the 144-pin package. AD frequency must be under 16 MHz when VCC =5V. AD frequency must be under 10 MHz when VCC =3.3V. Combination of the CKS0 and CKS1 bits selects AD (see the AD1CON0 register). 6. Do not set the VCUT bit to "0" during the A/D conversion. This is a reference voltage for the A/D1. It does not affect the D/A conversion. b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.6 AD1CON1 Register

Page 233 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Bit name A/D1 Control Register 2(1) Bit NameBit Symbol Symbol Address After Reset AD1CON2 01D4 16 X00X X000 2 RW RW RW RW RW RW SMP APS0 APS1 A/D Conversion Method Select Bit 0 : Without the sample and hold function 1 : With the sample and hold function Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. TRG0 (b4 - b3) (b7) TRG1 External Trigger Request Cause Select Bit Analog Input Port Select Bit 0 0 : AN15 0 to AN157(2) 0 1 : Do not set to this value 1 0 : AN00 to AN07(3) 1 1 : AN20 to AN27(3) b2 b1 0 0 : Selects ADTRG 0 1 : Selects a timer B2 interrupt request of the three-phase motor control timer functions (after the ICTB2 counter completes counting) 1 0 : Selects the Intelligent I/O group 3 channel 1 interrupt 1 1 : Do not set to this value NOTES: 1. When the AD1CON2 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. AN15 0 to AN157 are provided in the 144-pin package. 3. AN00 to AN07, AN20 to AN27 are available in single-chip mode only. b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.7 AD1CON2 Register, AD10 to AD17 Register Function A/D1 Register j (j=0 to 7) Symbol Address After Reset AD10 to AD12 01C1 16 - 01C016, 01C316 - 01C216, 01C516 - 01C416 Indeterminate AD13 to AD15 01C7 16 - 01C616, 01C916 - 01C816, 01CB16 - 01CA16 Indeterminate AD16 to AD17 01CD 16 - 01CC16, 01CF16 - 01CE16 Indeterminate RW RO RO 8 low-order bits in an A/D conversion result Nothing is assigned. When write, set to "0". When read, its content is indeterminate. In 10-bit mode In 8-bit mode : 2 high-order bits in an A/D conversion result : When read, its content is indeterminate. b7 b0b15 b8

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17.1 Mode Description

17.1.1 One-shot Mode

In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 17.4 lists specifications of one-shot mode. Table 17.4 One-shot Mode Specifications Item Specification Function Analog voltage, applied to a pin selected by the CH2 to CH0 bits in the ADiCON0 register (i=0, 1), is converted to a digital code once. Start Condition When the TRG bit in the ADiCON0 register is set to "0" (software trigger),

The ADST bit in the ADiCON0 register is set to "1" (A/D conversion starts) by program
The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a conversion simultaneously) by program When the TRG bit is set to "1" (external trigger, hardware trigger),
A falling edge is applied to the ADTRG pin after the ADST bit is set to "1" by program
One of the following interrupt requests is generated after the ADST bit is set to "1" by program: - The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 counter completes counting) is generated - The intelligent I/O interrupt request is generated Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1) Stop Condition •A/D conversion is completed (the ADST bit is set to "0" when the internal trigger is selected)
The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingA/D conversion is completed Analog Voltage Input Pins Select one from AN0 to AN7, ANEX0, or ANEX1 Select one from ANj0 to ANj7 (j=0, 2, 15) Reading of A/D Conversion ResultThe ADik register (k=0 to 7) corresponding to selected pin

17.1.2 Repeat Mode

In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 17.5 lists specifications of repeat mode. Table 17.5 Repeat Mode Specifications Item Specification Function Analog voltage, applied to a pin selected by the CH2 to CH0 bits in the ADiCON0 register (i=0, 1), is converted to a digital code once. Start Condition Same as one-shot mode Stop Condition The ADST bit in the ADiCON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingNot generated Analog Voltage Input Pins Select one from AN0 to AN7, ANEX0, or ANEX1 Select from ANj0 to ANj7 (j=0, 2, 15) Reading of A/D Conversion ResultThe ADik register (k=0 to 7) corresponding to selected pins

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17.1.3 Single Sweep Mode

In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 17.6 lists specifications of single sweep mode. Table 17.6 Single Sweep Mode Specifications Item Specification Function Analog voltage, applied to pins selected by the SCAN1 to SCAN0 bits in the ADiCON0 register (i=0, 1), are converted one-by-one to a digital code Start Condition Same as one-shot mode Stop Condition •A/D conversion is completed (the ADST bit in the ADiCON0 register is set to "0" when the internal trigger is selected)

The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingSweep operation is completed Analog Voltage Input Pins Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN 7 (8 pins) Select from ANj0 (j=0, 2, 15) to ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to ANj7 (8 pins) Reading of A/D Conversion ResultThe ADik register (k=0 to 7) corresponding to selected pins

17.1.4 Repeat Sweep Mode 0

In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 17.7 lists specifications of repeat sweep mode 0. Table 17.7 Repeat Sweep Mode 0 Specifications Item Specification Function Analog voltage, applied to pins selected by the SCAN1 to SCAN0 bits in the ADiCON0 register (i=0, 1), are repeatedly converted to a digital code Start Condition Same as one-shot mode Stop Condition The ADST bit in the ADiCON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingNot generated Analog Voltage Input Pins Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN 7 (8 pins) Select from ANj0 (j=0, 2, 15) to ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to ANj7 (8 pins) Reading of A/D Conversion ResultThe ADik register (k=0 to 7) corresponding to selected pins

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17.1.5 Repeat Sweep Mode 1

In repeat sweep mode 1, analog voltage selectively applied to eight pins is repeatedly converted to a digital code. Table 17.8 lists specifications of repeat sweep mode 1. Table 17.8 Repeat Sweep Mode 1 Specifications Item Specification Function Analog voltage selectively applied to 8 pins selected by the SCAN1 to SCAN0 bits in the ADiCON1 register (i=0,1) is repeatedly converted to a digital code. e.g., When ANj0 is selected (j =none, 0, 2, 15), analog voltage is converted to a digital code in the following order: Start Condition Same as one-shot mode Stop Condition The ADST bit in the ADiCON1 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingNot generated Analog Voltage Input Pins ANj 0 to ANj7 (8 pins) Prioritized Pins Select from AN 0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), or AN0 to AN3 (4 pins) Select from ANj 0 (j=0, 2, 15) (1 pin), ANj0 to ANj1 (2 pins), AN0 to AN2 (3 pins), ANj0 to ANj3 (4 pins) Reading of A/D Conversion ResultThe ADik register (k=0 to 7) corresponding to selected pins

17.2 Function

17.2.1 Resolution Select Function

The BITS bit in the ADiCON1 (i=0, 1) register determines the resolution. When the BITS bit is set to "1" (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADij register (j = 0 to 7). When the BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADij register.

17.2.2 Sample and Hold

When the SMP bit in the ADiCON2 register is set to "1" (with the sample and hold function), A/D conver- sion rate per pin increases to 28 Ø AD cycles for 8-bit resolution and 33 Ø AD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold function is to be used or not.

17.2.3 Trigger Select Function

The TRG bit in the ADiCON0 register and the TRG1 to TRG0 bits in the ADiCON2 register determine the trigger to start the A/D conversion. Table 17.9 lists settings of the trigger select function.

Page 237 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M Table 17.9 Trigger Select Function Settings Bit and Setting Trigger ADiCON0 Register ADiCON2 Register TRG = 0 - Software trigger The A/Di starts the A/D conversion when the ADST bit in the ADiCON0 register is set to "1" - Two-circuit simultaneous start A/D0 and A/D1 start the A/D conversion simultaneously when the PST bit in the AD0CON2 register is set to "1" by program (Refer to

17.2.4 Two-Circuit Simultaneous Start)

TRG = 1(1) TRG1 to TRG0 = 002 External trigger(2) Falling edge of a signal applied to ADTRG TRG1 to TRG0 = 012 Hardware trigger(2) The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 counter completes counting) TRG1 to TRG0 = 102 Hardware trigger(2) The intelligent I/O interrupt request is generated Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1) i= 0,1 NOTES: 1. The A/Di starts the A/D conversion when the ADST bit is set to "1" (A/D conversion started) and a trigger is generated. 2. The A/D conversion is restarted if an external trigger or a hardware trigger is inserted during the A/D conversion. (The A/D conversion in process is aborted.)

17.2.4 Two-Circuit Simultaneous Start (Software Trigger)

A/D0 and A/D1 start simultaneously when the PST bit in the AD0CON2 register is set to "1" (two-circuit simultaneous start). Do not set the PST bit to "1" while either A/D0 or A/D1 is performing an A/D conversion, or if the TRG bit is set "1" (external trigger). Do not set the ADST bit to "1" (A/D conversion started) when using the PST bit.

17.2.5 Pin Input Replacement Function

When the ADS bit in the AD0CON2 register is set to "1" (channel replacement enabled), channels of the A/D0 can be replaced with channels of the A/D1 and vice versa. Voltage applied to the ANj (j = 0 to 7) pin is converted to digital code in the A/D1 and the conversion result is stored into the AD1j register. Voltage applied to the AN0j, AN2j or AN15j pin is converted to digital code in the A/D0 and the conversion results are stored into the AD0j register. To set the ADS bit to "1", set the MD1 to MD0 bits in the AD0CON0 register to "002" (one-shot mode) or "012" (repeat mode). Single sweep, repeat sweep 0, and repeat sweep 1 modes cannot be used. Set the OPA1 to OPA0 bits in the AD0CON1 register to "002" (no ANEX0 and ANEX1 used). Set the same value to both AD0CON0 register and AD1CON0 register, and to both AD0CON1 register and AD1CON1 register.

Page 238 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M AN 0 AN 7 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 ANEX1 ANEX0 Microcomputer Resistor ladder Successive conversion register Analog input External op-amp Comparator

17.2.6 Extended Analog Input Pins

In one-shot mode and repeat mode, the ANEX0 and ANEX1 pins can be used as analog input pins. The OPA1 to OPA0 bits in the AD0CON1 register select which pins to use as analog input pins. An A/D conversion result for the ANEX0 pin is stored into the AD00 register. The result for the ANEX1 pin is stored into the AD01 register.

17.2.7 External Operation Amplifier (Op-Amp) Connection Mode

In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp using extended analog input pins ANEX0 and ANEX1. When the OPA1 to OPA0 bits in the AD0CON1 register are set to "11 2" (external op-amp connection), voltage applied to the AN0 to AN7 pins are output from ANEX0. Amplify this output signal by an external op-amp and apply it to ANEX1. Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored into the corresponding ADij register (i=0, 1; j=0 to 7). A/D conversion rate varies depending on the response of the external op-amp. Do not connect the ANEX0 pin to the ANEX1 pin directly. Figure 17.8 shows an example of an external op-amp connection. Table 17.10 Extended Analog Input Pin Settings AD0CON1 Register ANEX0 Function ANEX1 Function OPA1 OPA0 0 0 Not used Not used

01 P 9 5 as an analog input Not used

1 0 Not used P9 6 as an analog input 1 1 Output to an external op-amp Input from an external op-amp Figure 17.8 External Op-Amp Connection

Page 239 884fo6002,13.naJ13.1.veR 1310-4300B90JER 17. A/D Converter)T38/C23M,38/C23M(puorG38/C23M

17.2.8 Power Consumption Reducing Function

When the A/D converter is not used, the VCUT bit in the ADiCON1 register (i=0, 1) isolates the resistor ladder of the A/D converter from the reference voltage input pin (VREF ). Power consumption is reduced by shutting off any current flow into the resistor ladder from the VREF pin. When using the A/D converter, set the VCUT bit to "1" (VREF connection) before setting the ADST bit in the ADiCON0 register to "1" (A/D conversion started). Do not set the ADST bit and VCUT bit to "1" simultaneously, nor set the VCUT bit to "0" (no V REF connection) during the A/D conversion. The VCUT bit does not affect the VREF performance of the D/A converter.

17.2.9 Analog Input Pin and External Sensor Equivalent Circuit

Figure 17.9 shows an example of the analog input pin and external sensor equivalent circuit. Figure 17.9 Analog Input Pin and External Sensor Equivalent Circuit R 0 R (7.8k ) C (2.0pF) VIN Microcomputer Sensor equivalent circuit VC Sampling time (the time needed until the capacitor is fully charged after closing switch) Sample and hold function is enabled : 3 φ AD φADSample and hold function is disabled :

Page 240 884fo6002,13.naJ13.1.veR 1310-4300B90JER 18. D/A Converter)T38/C23M,38/C23M(puorG38/C23M 18. D/A Converter The D/A converter consists of two separate 8-bit R-2R ladder D/A converters. Digital code is converted to an analog voltage when a value is written to the corresponding DAi registers (i=0,1). The DAiE bit in the DACON register determines whether the D/A conversion result is output or not. Set the DAiE bit to "1" (output enabled) to disable a pull-up of a corresponding port. Output analog voltage (V) is calculated from value n (n=decimal) set in the DAi register. V = (n = 0 to 255) V REF : reference voltage (not related to VCUT bit setting in the ADiCON1 register) Table 18.1 lists specifications of the D/A converter. Table 18.2 lists pin settings of the DA0 and DA1 pins. Figure 18.1 shows a block diagram of the D/A converter. Figure 18.2 shows the D/A control register. Figure 18.3 shows a D/A converter equivalent circuit. When the D/A converter is not used, set the DAi register to "00 16" and the DAiE bit to "0" (output disabled). Table 18.1 D/A Converter Specifications Item Specification D/A Conversion Method R-2R Resolution 8 bits Analog Output Pin 2 channels Table 18.2 Pin Settings Port Function Bit and Setting PD9 Register(1) PS3 Register(1) PSL3 Register P9 3 DA 0 output PD9_3=0 PS3_3=0 PSL3_3=1 P9 4 DA 1 output PD9_4=0 PS3_4=0 PSL3_4=1 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. VREF x n 256

Page 241 884fo6002,13.naJ13.1.veR 1310-4300B90JER 18. D/A Converter)T38/C23M,38/C23M(puorG38/C23M /LiteDiagLines DA0 Register R-2R Resistor Ladder /LiteDiagLines Low-Order Bits of Data Bus /LiteDiagLines R-2R Resistor Ladder DA1 Register DA0E DA1E DA 0 DA 1 DA0E, DA1E: Bits in the DACON register Figure 18.1 D/A Converter

Page 244 884fo6002,13.naJ13.1.veR 1310-4300B90JER 19. CRC Calculation)T38/C23M,38/C23M(puorG38/C23M CRC Calculation and Setup Procedure to Generate CRC Code for "80C416" CRC Code : a remainder of a division, (1) Inverse a bit position of "80C416" per byte by program (2) Set "000016" (default value) CRCD register CRCD register CRCIN register Generator Polynomial : X16 + X12 + X5 + 1 (1 0001 0000 0010 00012) value of the CRCIN register with inversed bit position generator polynomial CRC Calculation for M32C Setting Steps Details of CRC Calculation (3) Set "0116" Bit position of the CRC code for "8016" (918816) is inversed to "118916", which is stored into the CRCD register in 3rd cycle. CRCD register Generator Polynomial data 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 - 1 = 1 CRCIN register (4) Set "2316" CRC Code 1 0001 0000 0010 0001 1000 1000 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 Bit position of the CRC code for "80C4 16" (825016) is inversed to "0A4116", which is stored into the CRCD register in 3rd cycle. As shown in (3) above, bit position of "0116" (000000012) written to the CRCIN register is inversed and becomes "100000002". Add "1000 0000 0000 0000 0000 00002", as "100000002" plus 16 digits, to "000016" as the default value of the CRCD register to perform the modulo-2 division. "0001 0001 1000 10012 (118916)", the remainder "1001 0001 1000 10002 (918816)" with inversed bit position, can be read from the CRCD register. When going on to (4) above, "23 16 (001000112)" written in the CRCIN register is inversed and becomes "110001002". Add "1100 0100 0000 0000 0000 00002", as "110001002" plus 16 digits, to "1001 0001 1000 10002" as a remainder of (3) left in the CRCD register to perform the modulo-2 division. "0000 1010 0100 0001 2 (0A4116)", the remainder with inversed bit position, can be read from CRCD register. Modulo-2 Arithmetic is calculated on the law below. b15 b0 b15 b0 b7 b0 118916 b15 b0 b7 b0 0A4116 Figure 19.3 CRC Calculation

Page 245 884fo6002,13.naJ13.1.veR 1310-4300B90JER 20. XY Conversion)T38/C23M,38/C23M(puorG38/C23M 20. X/Y Conversion The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and inverses high-order bits and low-order bits of a 16-bit data. Figure 20.1 shows the XYC register. The 16-bit XiR register (i=0 to 15) and 16-bit YjR register (j=0 to 15) are allocated to the same address. The XiR register is a write-only register, while the YjR register is a read-only register. Access the XiR and YjR registers from an even address in 16-bit units. Performance cannot be guaranteed if the XiR and YiR registers are accessed in 8-bit units. Function X/Y Control Register Bit NameBit Symbol Symbol Address After Reset XYC 02E0 16 XXXX XX00 2 RW Read-Mode Set Bit Write-Mode Set Bit Noting is assigned. When write, set to "0". When read, its content is indeterminate. 0 : Data conversion 1 : No data conversion 0 : No bit alignment conversion 1 : Bit alignment conversionXYC1 (b7 - b2) XYC0 RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 20.1 XYC Register

Page 248 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M 21. Intelligent I/O The intelligent I/O is a multifunctional I/O port for time measurement, waveform generation, clock synchro- nous serial I/O, clock asynchronous serial I/O (UART), IEBus(1) communications, HDLC data processing and more. The intelligent I/O consists of four groups. Each group has one 16-bit base timer for free-running operation, eight 16-bit registers for time measurement and waveform generation and two 8-bit shift registers (or one 16-bit shift register) for communications. Table 21.1 lists functions and channels of the intelligent I/O. NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. Table 21.1 Intelligent I/O Functions and Channels noitcnuF0 puorG1 puorG2 puorG3 puorG 1,0puorG dedacsac tnemerusaeMemiT )1( slennahc8 )slennahc3( )2( slennahc4 )slennahc2( toN elbaliavA toN elbaliavA slennahc8 )slennahc3( retliFlatigiD slennahc8 )slennahc3( slennahc4 )slennahc2( slennahc8 )slennahc3( relacserPtupnIreggirTs lennahc2s lennahc2s lennahc2 etaGtupnIreggirTs lennahc2s lennahc2s lennahc2 noitareneGmrofevaW slennahc4 )slennahc2( slennahc8 )slennahc3( slennahc8 )slennahc3( slennahc8 )slennahc2( slennahc8 )slennahc3( tuptuOmrofevaWesahp-elgniS elbaliavAe lbaliavA elbaliavAe lbaliavA elbaliavAtuptuOmrofevaWdeyaled-esahP tuptuOmrofevaWRS edoMMWPnoitaludoMtiB toN elbaliavA toN elbaliavA toN elbaliavAedoMPTR edoMPTRlellaraP noitacinummoCd exifstib8e lbairaVs tib61ro8 toN elbaliavA edoMO/IlaireSsuonorhcnySkcolC elbaliavA elbaliavAe lbaliavA toN elbaliavA edoMTRAU toN elbaliavA toN elbaliavAedoMgnissecorPataDCLDH edoMsuBEIe lbaliavAtoNe lbaliavA :SETON sniperahsnoitcnufnoitarenegmrofevawdnanoitcnuftnemerusaememiT.1 .)(esehtetnerapnidetacidnieraegakcapnip-001ehtnielbaliavaslennahcforebmunehT.2 The time measurement function and waveform generation function can be selected for each channel. The communication function is available by a combination of multiple channels.

Page 249 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figures 21.1 to 21.4 show block diagram of the intelligent I/O groups 0 to 3. Figure 21.1 Intelligent I/O Group 0 Block Diagram Reception G0TM0, G0PO0 register G0TM1, G0PO1 register G0TM2, G0PO2 register G0TM3, G0PO3 register G0TM4, G0PO4 registerG0TM5, G0PO5 registerG0TM6, G0PO6 registerG 0TM 7, G0PO 7 register Base timer PWM output PWM output PWM output Group0 base timer reset Request by matching the base timer with the G0PO0 register Request from the INT pin Request from the group1 Divider by 2(n+1) DIV4 to DIV0 fBT0 Edge select Digital filter Edge select Digital filter Gate function Gate function Edge select Digital filter Edge select Digital filter Edge select Digital filter Edge select Digital filter Edge select Digital filter Edge select Digital filterINPC0 0 BCK1 to BCK0 0010 : fBT0 11 : f1 10 : fBT0 11 : f1 10 : fBT0 11 : f1 10 : fBT0 11 : f1 10 : fBT0 11 : f1 10 : fBT0 11 : f1 10 : fBT0 11 : f1 10 : fBT0 11 : f1 INPC0 1 / ISCLK0 INPC0 2 / ISRxD0 INPC0 3 INPC0 4 INPC0 5 INPC0 6 INPC0 7 BTS BT0S DF1 to DF0 CTS1 to CTS0 DF1 to DF0 CTS1 to CTS0 D F1 to DF0 CTS1 to CTS0 DF1 to D F0 CTS1 to CTS0 DF1 to DF0 CTS1 to CTS0 D F1 to DF0 CTS1 to CTS0 DF 1 to DF0 CTS1 to CTS0 DF1 to DF0 CTS1 to CTS0 GT GT PR PR Ch0 to ch7 interrupt request signal OUTC0 0/ISTxD0 OUTC0 1/ISCLK0 OUTC0 4 OUTC0 5 Arbitration Comparator Comparator Comparator Comparator Special interrupt check G0CMP3 registerG0CMP3 register G0CMP3 register G0CMP3 register Buffer register Shift register Prescaler function Prescaler function Start bit generation circuit Bit insert circuit SOF generation circuit Stop bit generation circuit Transmit latch Transmit data generation circuit G0TCRC register Data selector Clock wait control circuit Transmit register Transmit buffer Polarity inverse G0TO register Transmit register Transmit buffer G0RB register Receive register Receive buffer Receive data generation circuit Start bitcheck Bit insertcheck Stop bitcheck G0RCRC registerG0RI register Receive register Receive buffer Polarity inverse Clock selector Clock selector Waveform generation match signal for group1 (For cascaded connection) Time measurement trigger for the group1 (For cascaded connection) Overflow of base timer bit 15 Base timer interrupt request(3) HDLC data receive interrupt request Transmit interrupt request (SIO0TR)(3) (G0TOR) (3) (SIO0RR)(3) (SRT0R)(3) (G0RIR)(3) HDLC data transmit interrupt request Receive interrupt request Special communication interrupt request Transmission (Note 1) (Note 1) G0DR register (Receive data register) Two-phase pulse signal is applied G0TB register (Transmit buffer register) ch0 ch3 ch2 ch1 ch3 External clock Transmit operation clock Receive operation clock External clock 111 000 to 010 111 000 to 010 MOD2 to MOD0 MOD2 to MOD0 Data selector TXSL OPOL1 RXSL IPOL DIV4 to DIV0 bits, BCK1 to BCK0 bits : Bits in the G0BCR0 register BTS : Bit in the G0BCR1 register BT0S : Bit in BTSR register CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G0TMCRj register (j = 0 to 7) MOD2 to MOD0 : Bits in the G0POCRj register TXSL, RXSL : Bits in the G0EMR register OPOL, IPOL : Bits in the G0CR register NOTES: 1. These pins are not connected to external pins in the 100-pin package. 2. Each register enters a reset state after the G0BCR0 register supplies the clock. 3. See Figure 10.14. Reset

Page 250 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figure 21.2 Intelligent I/O Group 1 Block Diagram Reception Transmission G1TM0, G1PO0 register G1TM1, G1PO1 register G1TM2, G1PO2 register G1TM3, G1PO3 register G1TM4, G1PO4 registerG1TM5, G1PO5 registerG1TM6, G1PO6 registerG 1TM7, G1PO 7 register PWM output PWM output PWM output PWM output Group1 base timer reset Divider by 2(n+1) Edge select Digital filter Gate function Edge select Digital filter Gate function Edge select Digital filterINPC1 1 / ISCLK1 INPC1 6 INPC1 7 DIV4 to DIV0 GT GT PR PR CAS Ch0 to ch7 interrupt request signal OUTC1 0/ISTxD1/ BE1 OUT OUTC1 1/ISCLK1 OUTC1 4 OUTC1 5 Arbitration Special interrupt check buffer register Shift register Prescaler function Prescaler function Start bit generation circuit Bit insert circuit SOF generation circuit Stop bit generation circuit Transmit latch Transmit data generation circuit Clock wait control circuit Transmit register Transmit buffer Polarity inverse Transmit register Transmit buffer Receive register Receive buffer Receive data generation circuit Start bitcheck Bit insertcheck Stop bit check G1RI register Receive register Receive buffer OUTC1 6 OUTC1 7 OUTC1 2 OUTC1 3 Waveform generation match signal from the group 0 (For cascaded connection) Time measurement trigger from the group 0 (For cascaded connection) HDLC data receive interrupt request Transmit interrupt request Receive interrupt request Special communication interrupt requestComparatorComparator Comparator Comparator (Note 1) (Note 2) (Note 2) G1CMP3 register G1CMP3 register G1CMP3 register G1CMP3 register G1RB register G1TO register G1TB register (Transmit buffer register) G1DR register (Receive data register) Base timerfBT1 overflow of bit 15 in the group0 base timer Edge select Digital filterINPC1 2 / ISRxD1 Two-phase pulse signal is applied G1TCRC register G1RCRC register 111 000 to 010 000 to 010 MOD2 to MOD0 111 MOD2 to MOD0 Data selector TXSL OPOL1 Data selector RXSL IPOL Polarity inverse Clock selector Clock selector ch0 ch3 ch2 ch1 ch3 External clock Transmit operation clock Receive operation clock External clock DIV4 to DIV0, BCK1 to BCK0 : Bits in the G1BCR0 register CAS, BTS : Bits in the G1BCR1 register BT1S : Bit in the BTSR register CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj register (j = 0 to 7) MOD2 to MOD0 : Bits in the G1POCRj register TXSL, RXSL : Bits in the G1EMR register Request from the INT pin Request from the group0 BTS BT1S Request by matching the base timer with the G1PO0 register NOTES: 1. The G1TM0 register can be used in a 32-bit cascaded connection only. 2. These pins are not connected to external pins in the 100-pin package. 3. Each register is in a reset state after the G1BCR0 register supplies the clock. 4. See Figure 10.14. HDLC data transmit interrupt request (SIO1TR)(4) (G1TOR) (4) (G1RIR)(4) (SIO1RR)(4) (SRT1R)(4) Overflow of bit 15 in the base timer Base timer interrupt request (BT1R)(4) BCK1 to BCK0 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 CTS1 to CTS0 CTS1 to CTS0 DF1 to DF0 DF1 to DF0 DF1 to DF0 00 0 DF1 to DF0 CTS1 to CTS0 CTS1 to CTS0

Page 251 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M PWM output control G2PO0 register G2PO1 register G2PO2 register G2PO3 register G2PO4 register G2PO5 register G2PO6 register G2PO7 register Base timer Group2 base timer reset Request from the communication function Request from the group1 Divider by 2(n+1) fBT2 BT2S BTS DIV4 to DIV0 Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM PWM output control PWM output control OUTC2 0 /ISTxD2/IEOUTPWM output control OUTC2 1 /ISCLK2 OUTC2 2 OUTC2 3 OUTC2 4 OUTC2 5 OUTC2 6 OUTC2 7 OPOL Waveform generation interrupt request Clock selector Clock synchronous serial I/O mode receive interrupt request Clock synchronous serial I/O mode transmit interrupt requestPolarity inverse Receive register Output control function IE start bit interrupt request Real time port output value Digital filterIEIN /ISRxD2 ISCLK2 Bit counter Transmit register G2TB register Transmit parity calculation Polarity inverse Transmit latch Arbitration lost detection Byte counter IE, serial I/O interrupt control IE receive interrupt request IE transmit interrupt request ACK calculation Receive parity calculation Start bit detection G2RB register ID detection ALL "F" detection Address detect function Statement length detect function (Note 1) (SIO2TR)(3) (IE0R to IE2R)(3) (IE0R to IE2R)(3) (IE0R to IE2R)(3) PO2jR (3) (SIO2RR)(3) Overflow of bit 15 in the base timer Base timer interrupt request BT2R(3) BCK1 to BCK0 DF IPOL 111 000 to 010,

100 MOD2 to MOD0

000 to 010, 100 MOD2 to MOD0 DIV4 to DIV0, BCK1 to BCK0 : Bits in the G2BCR0 register BTS : Bit in the G2BCR1 register BT2S : Bit in the BTSR register OPOL, IPOL : Bits in the G2CR register DF : Bit in the IECR register MOD2 to MOD0 : Bits in the G2POCRj register (j = 0 to 7) NOTES: 1. In the 100-pin package, these pins are not connected to external pins. 2. Each register enters a reset state after the G2BCR0 register supplies the clock. 3. See Figure 10.14. Request by matching the base timer with the G2PO0 register Figure 21.3 Intelligent I/O Group 2 Block Diagram

Page 252 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figure 21.4 Intelligent I/O Group 3 Block Diagram Reception Transmission IPOL Polarity inverse G3MK7 register G3MK6 register G3MK5 register G3MK4 register PWM output control G3PO0 register G3PO1 register G3PO2 register G3PO3 register G3PO4 register G3PO5 register G3PO6 register G3PO7 register Base timerDivider by 2(n+1)f1 Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM PWM output control PWM output control OUTC3 0/ISTxD3 PWM output control OUTC3 1/ISCLK3(1) OUTC3 2 OUTC3 3 OUTC3 4 OUTC3 5 OUTC3 6 OUTC3 7 Waveform generation interrupt request G3TB register Transmit Shift register G3RB registerReceive shift register Shift counter Receive interrupt request Transmit interrupt request Mode controller Mode controllerReceive operation clock Transmit operation clock Shift counter ISCLK3(1) ISRxD3 Real time port output value (Note 1) DIV4 to DIV0 fBT3 (PO3jR)(3) Overflow of the bit 15 in the base timer Base timer interrupt request (BT3R)(3) BCK1 to BCK0 111 000 to 010, 100 MOD2 to MOD0 111 000 to 010, 100 MOD2 to MOD0 OPOL Polarity inverse DIV4 to DIV0, BCK1 to BCK0 : Bits in the G3BCR0 register BTS : Bit in the G3BCR1 register BT3S : Bit in the BTSR register MOD2 to MOD0 : Bits in the G3POCRj register (j = 0 to 7) OPOL, IPOL : Bits in the G3CR register NOTES: 1. In the 100-pin package, these pins are not connected to external pins. 2. Each register enters a reset state after the G3BCR0 register supplies the clock. Clock selector (SIO3RR)(3) (SIO3TR)(3) Group3 base timer reset Request from communication function Request from group2 BT3S BTS Request by matching the base timer with the G3PO0 register Reset

Page 253 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figures 21.5 to 21.15 show registers associated with the intelligent I/O base timer, the time measurement function and waveform generation function. (For registers associated with the communication function, see Figure 21.5 G0BT to G3BT Register and G0BCR0 to G3BCR0 Register Group i Base Timer Register (i=0 to 3)(2) Symbol Address After Reset G0BT,G1BT 00E1 16 - 00E016, 012116 - 012016 Indeterminate G2BT,G3BT 0161 16 - 016016, 01A116 - 01A016 Indeterminate RW RW Function Setting Range 000016 to FFFF16 b8b15 b7 NOTES: 1. Each base timer stops only when the BCK1 to BCK0 bits in the GiBCR0 register are set to "002" (clock stopped). The base timer counts when the BCK1 to BCK0 bits are set to a value other than "002". When the BTiS bit in the BTSR register and the BTS bit in the GiBCR1 register are set to "0", the base timer is reset continually, remaining set to "0000 16". This, in effect, places the base timer in a "no counting" state. When either BTiS bit or BTS bit is set to "1", this state is cleared and counting starts. 2. The GiBT register reflects the value of the base timer with a delay of one half fBT i cycle. When the base timer is counting: When read, the value of the counter can be read. When write, the counter starts counting from the value written. When the base timer is reset, the GiBT register is set to "0000 16"(1). When the base timer is reset: The GiBT register is set to "0000 16" but the value is indeterminate. No value is written(1). Group i Base Timer Control Register 0 (i=0 to 3)(1) Symbol Address After Reset G0BCR0 to G3BCR0 00E216, 012216, 016216, 01A216 0016 RW RW RW RW RW RW RW RW RWBit Name FunctionBit Symbol : Clock stops : Do not set to this value : Two-phase pulse signal is applied (2) : f1 BCK0 BCK1 DIV0 Count Source Select Bit DIV1 Count Source Divide Ratio Select Bit DIV2 DIV3 IT Base Timer Interrupt Select Bit 0 : Bit 15 overflows 1 : Bit 14 overflows DIV4 If setting value is n (n = 0 to 31), count source is divided by 2(n + 1). No division if n=31. (n=0) 0 0 0 0 0 : Divide-by-2 (n=1) 0 0 0 0 1 : Divide-by-4 (n=2) 0 0 0 1 0 : Divide-by-6 (n=30) 1 1 1 1 0 : Divide-by-62 (n=31) 1 1 1 1 1 : No division b6 b5 b4 b3 b2 NOTES: 1. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement, waveform gene- ration function), set the G0BCR0 register and G1BCR0 register to the same value. 2. This setting can be used only when the UD1 to UD0 bits in the GjBCR1 register (j=0, 1) of group 0 or 1 are set to "102" (two-phase signal processing mode). Do not set the BCK1 to BCK0 bits to "102" in other modes or in group 2 or 3. b7 b6 b5 b4 b3 b2 b1 b0

Page 254 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figure 21.6 G0BCR1 and G1BCR1 Registers Group i Base Timer Control Register 1 (i=0,1) Symbol Address After Reset G0BCR1, G1BCR1 00E316, 012316 0016 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol RST0 RST1 RST2 (b3) Base Timer Reset Cause Select Bit 0 Base Timer Start Bit (5, 6)BTS UD0 CAS UD1 Base Timer Reset Cause Select Bit 1 Base Timer Reset Cause Select Bit 2 Counter Increment/ D ecrement C ontrol Bit 0: Base timer is reset 1: Base timer starts counting : Counter increment mode : Counter increment/decrement mode : Two-phase pulse signal processing mode (7) : Do not set to this value Groups 0 and 1 C ascaded C onnection Function Select Bit 0: 16-bit time measurement or waveform generation function 1: 32-bit time measurement or waveform generation function (4) Reserved Bit Set to "0" NOTES: 1. In group 0, the base timer is reset by synchronizing with the group 1 base timer reset. In group 1, the base timer is reset by synchronizing with the group 0 base timer reset. 2. The base timer is reset two fBTi clock cycles after the base timer matches the value set in the GiPO0 register. (See Figure 21.13 for details on the GiPO0 register.) When the RST1 bit is set to "1", the value of the GiPOj register (j=1 to7) for the waveform generation function and communication function must be set to a smaller value than that of the GiPO0 register. 3. In group 0, the base timer is reset when "L" is applied to the INT0 pin. In group 1, the base timer is reset when "L" is applied to the INT1 pin. 4. When the CAS bit is set to "1" (32-bit time measurement, waveform generation function), set the G0BCR1 register to "81 16" and the G1BCR1 register to "1000 0XX02". 5. When starting the group 0 or 1 base timer separately, set the BTS bit to "1" after the BTkS bit (k=0 to 1) in the BTSR register is set to "0". 6. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS bit to "0". 7. In two-phase pulse signal processing mode, the base timer is not reset, even when the RST1 bit is set to "1", if the counter is decremented two clock cycles after the base timer matches the value set in the GiPO0 register The base timer is not reset by synchronizing with the base timer reset 1: The base timer is reset by synchronizing with the base timer reset(1) 0: The base timer is not reset by matching with the GiPO0 register 1: The base timer is reset by matching with the GiPO0 register(2) 0: The base timer is not reset by applying "L" to the INTi pin 1: The base timer is reset by applying "L" to the INTi pin(3) b7 b6 b5 b4 b3 b2 b1 b0

Page 255 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Group 2 Base Timer Control Register 1 Symbol Address After Reset G2BCR1 0163 16 00 16 RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. The base timer is reset two fBT2 clock cycles after the base timer matches the value set in the G2PO0 register. (See Figure 21.13 for details on the G2PO0 register.) When the RST1 bit is set to "1", the value of the G2POi register (i=1 to7), for the waveform generation function and communication function, must be set to a smaller value than that of the G2PO0 register. 2. The PRP bit is valid when the RTP bit in the G2POCRi register is set to "1" (not used) 3. When starting the group 2 base timer, set the BTS bit to "1" after the BT2S bit in the BTSR register is set to "0". 4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS bit to "0". RST0 RST1 RST2 Base Timer Reset Cause Select Bit 0 Base Timer Start Bit (3, 4)BTS (b3) (b6 - b5) Base Timer Reset Cause Select Bit 1 Base Timer Reset Cause Select Bit 2 Set to "0" 0 : Base timer is reset 1 : Base timer starts counting Parallel Real-Time Port Function Select Bit (2) PRP 0 : RTP output mode 1 : Parallel RTP output mode Reserved Bit Reserved Bit Set to "0" 000 b7 b6 b5 b4 b3 b2 b1 b0 0 : The base timer is not reset by matching with the G2PO0 register 1 : The base timer is reset by matching with the G2PO0 register(1) 0 : The base timer is not reset by a reset request from the communication function 1 : The base timer is reset by a reset request from the communication function 0 : The base timer is not reset by synchronizing with the group 1 base timer reset 1 : The base timer is reset by synchronizing with the group 1 base timer reset Figure 21.7 G2BCR1 Register

Page 256 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Group 3 Base Timer Control Register 1 Symbol Address After Reset G3BCR1 01A3 16 00 16 RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. The base timer is reset after two fBT3 clock cycles after the base timer matches the value set in the G3PO0 register. (See Figure 21.13 for details on the G3PO0 register.) When the RST1 bit is set to "1", the value of the G3POi register (i=1 to7), for the waveform generation function and communication function, must be set to a smaller value than that of the G2PO0 register. 2. The PRP bit is valid when the RTP bit in the G3POCRi register is set to "1" (not used) 3. When starting the group 3 base timer, set the BTS bit to "1" after the BT3S bit in the BTSR register is set to "0". 4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS bit to "0". 0 : The base timer is not reset by matching with the G3PO0 register 1 : The base timer is reset by matching with the G3PO0 register(1) 0 : The base timer is not reset by a reset request from the communication function 1 : The base timer is reset by a reset request from the communication function RST0 RST1 Base Timer Reset Cause Select Bit 0 Base Timer Start Bit (3, 4)BTS Base Timer Reset Cause Select Bit 1 Base Timer Reset Cause Select Bit 2 Set to "0" 0 : Base timer is reset 1 : Base timer starts counting Parallel R eal-Time Port Function Select Bit (2) PRP 0 : RTP output mode 1 : Parallel RTP output mode RST2 (b3) (b6 - b5)Reserved Bit Reserved Bit Set to "0" 000 b7 b6 b5 b4 b3 b2 b1 b0 0 : The base timer is not reset by synchronizing with the group 2 base timer reset 1 : The base timer is reset by synchronizing with the group 2 base timer reset Figure 21.8 G3BCR1 Register

Page 257 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Base Timer Start Register(1, 2) Symbol Address After Reset BTSR 0164 16 XXXX 0000 2 RW RW RW RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. BT0S BT1S BT2S Group 0 Base Timer Start Bit BT3S (b7 - b4) 0 : Base timer reset 1 : Base timer starts counting 0 : Base timer reset 1 : Base timer starts counting 0 : Base timer reset 1 : Base timer starts counting 0 : Base timer reset 1 : Base timer starts counting Group 1 Base Timer Start Bit Group 2 Base Timer Start Bit Group 3 Base Timer Start Bit b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Set registers as follows before using the intelligent I/O: (1) Set the G2BCR0 register to supply the clock to the group 2 base timer (2) Set all BT0S to BT3S bits in the BTSR register to "0" (base timer reset) (3) Set other registers associated with the intelligent I/O The BTiS bit (i=0 to 3) allows the base timers in multiple groups to start counting simultaneously. When starting the base timers separately, set the BTiS bit to "0" before setting the BTS bit in the GiBCR1 register. 2. Use the following procedure to start base timers in multiple groups simultaneously (including groups 1 and 2 cascaded connections). This procedure is not required when starting the base timers individually.

Set the BCK1 to BCK0 bits and DIV4 to DIV0 bits in the GiBCR0 register (i=0 to 3) of the groups to be started simultaneously, to the same value.
After the BCK1 to BCK0 bits or DIV4 to DIV0 bits are changed, use the following procedure to start the base timer twice. (1) Set the BTiS bit in the BTSR register to "1" (base timer starts counting). (2) Set the BTiS bit to "0" (base timer stops counting) after one f BTi clock cycle. (3) After waiting at least one additional fBTi clock cycle, set the BTiS bit to "1" (base timer starts counting). Figure 21.9 BTSR Register

Page 258 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Group i Time Measurement Control Register j (i=0,1; j=0 to 7)(1) Symbol G0TMCR0 to G0TMCR3 G0TMCR4 to G0TMCR7 G1TMCR0 to G1TMCR3 G1TMCR4 to G1TMCR7 Address 00D8 16, 00D916, 00DA16, 00DB16 00DC 16, 00DD16, 00DE16, 00DF16 011816, 011916, 011A16, 011B16 011C16, 011D16, 011E16, 011F16 After Reset 0016 0016 0016 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol CTS0 CTS1 DF0 Time Measurement Trigger Select Bit DF1 Gate Function Select Bit(2, 4)GT GOC PR GSC Digital Filter Function Select Bit Gate Function Clear Select Bit(2, 3, 5) 0 : Gate function is not used 1 : Gate function is used Gate Function Clear Bit (2, 3) Prescaler Function Select Bit (2) : No time measurement : Rising edge : Falling edge : Both edges : No digital filter : Do not set to this value : f BTi : f1 0 : Not cleared 1 : The gate is cleared when the base timer matches the GiPOk register The gate is cleared by setting the GSC bit to "1" 0 : Not used 1 : Used NOTES: 1. If the CAS bit in the GiBCR1 register is set to "0" (16-bit time measurement function), the G1TMCR0 and G1TMCR3 to G1TMCR5 registers cannot be used. When write, set these registers to "00 16". If the CAS bit is set to "1" (32-bit time measurement function), set the same values in the G0TMCRj and G1TMCRj registers. 2. These bits are in the GiTMCR6 and GiTMCR7 registers. Set all bits 4 to 7 in the GiTMCR0 to GiTMCR5 registers to "0". 3. These bits are enabled only when the GT bit is set to "1" 4. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), set the GT bit to "0". The gate function cannot be used. 5. The GOC bit is set to "0" after the gate function is cleared. See Figure 18.13 for details on the GiPOk register (k=4 when j=6; k=5 when j=7). b7 b6 b5 b4 b3 b2 b1 b0 Group i Time Measurement Prescale Register j (i=0,1; j=6,7) Symbol Address After Reset G0TPR6 to G0TPR7 00E4 16, 00E516 0016 G1TPR6 to G1TPR7 0124 16, 012516 00 16 RW RW Function Setting Range If the setting value is n, the value of the base timer is stored into GiTMj register whenever a trigger input is counted by n+1 (1) 0016 to FF16 NOTES: 1. The first prescaler, after the PR bit in the GiTMCRj register is changed from "0" (prescaler function used) to "1" (prescaler function not used), may be divided by n rather than n+1. The subsequent prescaler is divided by n+1. b7 b0 Figure 21.10 G0TMCR0 to G0TMCR7, G1TMCR0 to G1TMCR7, G0TPR6, G0TPR7, G1TPR6, and G1TPR7 Registers

Page 259 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figure 21.11 G0TM0 to G0TM7, G1TM0 to G1TM7, Registers and G0POCR0 to G0POCR7, G1POCR0 to G1POCR7 Registers Group i Time Measurement Register j (i=0,1; j=0 to 7) RW RO Function Setting Range b15 b8 Symbol G0TM0 to G0TM2 G0TM3 to G0TM5 G0TM6 to G0TM7 G1TM0 to G1TM2 G1TM3 to G1TM5 G1TM6 to G1TM7 Address 00C1 16 - 00C016, 00C3 16 - 00C216, 00C5 16 - 00C416 00C7 16 - 00C616, 00C9 16 - 00C816, 00CB 16 - 00CA16 00CD 16 - 00CC16, 00CF 16 - 00CE16 010116 - 010016, 010316 - 010216, 010516 - 010416 010716 - 010616, 010916 - 010816, 010B16 - 010A16 010D 16 - 010C16, 010F16 - 010E16 After Reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate The value of the base timer is stored every trigger input. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), 16 low-order bits are stored into the G0TMj register and 16 high-order bits are into stored the G1TMj register. b7 b0 Group i Waveform Generation Control Register j (i=0 to 1; j=0 to 7)(1) Symbol Address After reset G0POCR0 to G0POCR3 00D0 16, 00D116, 00D216, 00D316 0X00 X000 2 G0POCR4 to G0POCR7 00D4 16, 00D516, 00D616, 00D716 0X00 X000 2 G1POCR0 to G1POCR3 0110 16, 011116, 011216, 011316 0X00 X000 2 G1POCR4 to G1POCR7 0114 16, 011516, 011616, 011716 0X00 X000 2 RW RW RW RW RW RW RW Bit Name FunctionBit Symbol MOD0 MOD1 MOD2 (b3) (b6) Operation Mode Select Bit Output Initial Value Select BitIVL RLD INV 0: Outputs "L" as default value 1: Outputs "H" as default value Inverse Output Function Select Bit(5) : Single waveform output mode : SR waveform output mode (2) : Phase-delayed waveform output mode : Do not set to this value : Do not set to this value : Do not set to this value : Do not set to this value (3) : Use a communication function output (4) 0: Output is not inversed 1: Output is inversed GiPOj Register Value Reload Timing Select Bit NOTES: 1. Groups 0 and 1 have 16-bit and 32-bit waveform generation functions. If the CAS bit in the GiBCR1 register is set to "0" (16-bit waveform generation function), the G0POCR2 to G0POCR3 and G0POCR 6 to G0POCR7 registers cannot be used. When write, set these registers to "00 16". If the CAS bit is set to "1" (32-bit waveform generation function), set the same values in the G0POCRj and G1POCRj registers. 2. This setting is valid only for even channels. In SR waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. Even channels output waveforms. Odd channels output no waveform. 3. To receive data in UART mode of group 0 and 1, set the GiPOCR2 register to "0000 0110 2". 4. This setting is valid only for channels 0 and 1. To use ISTxDi, set the MOD2 to MOD0 bits in the GiPOCR0 register to "1112". To use ISCLKi for an output, set the MOD2 to MOD0 bits in the GiPOCR1 register to"1112". Do not set the MOD2 to MOD0 bits to "1112" except in the channels 0 and 1 and for the communication function. 5. The inverse output function is the final step in the waveform generation process. If the INV bit is set to "1", the output signal is "H" when the IVL bit is set to "0" and "L" when the IVL bit is set to "1". Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0: Reloads the GiPOj register when value is written 1: Reloads the GiPOj register when the base timer is reset b7 b6 b5 b4 b3 b2 b1 b0

Page 260 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figure 21.12 G2POCR0 to G2POCR7 and G3POCR0 to G3POCR7 Registers Group i Waveform Generation Control Register j (i=2 to 3; j=0 to 7) Symbol Address After Reset G2POCR0 to G2POCR3 0150 16, 015116, 015216, 015316 00 16 G2POCR4 to G2POCR7 0154 16, 015516, 015616, 015716 00 16 G3POCR0 to G3POCR3 0190 16, 019116, 019216, 019316 00 16 G3POCR4 to G2POCR7 0194 16, 019516, 019616, 019716 00 16 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol MOD0 MOD1 MOD2 Operation Mode Select Bit(5) Output Initial Value Select BitIVL RLD INV 0: Outputs "L" as default value 1: Outputs "H" as default value Parallel Real-time Port Output Trigger Select Bit (4) PRT Inverse Output Function Select Bit(3) : Single waveform output mode : SR waveform output mode (1) : Inverse waveform output mode : Do not set to this value Bit-modulation PWM mode : Do not set to this value : Do not set to this value Use a communication function output(2) 0: Output is not inversed 1: Output is inversed RTP Real-time Port Function Select Bit 0: Not used 1: Used (RTP output mode or parallel RTP output mode) GiPOj Register Value Reload Timing Select Bit NOTES: 1. This setting is valid only for even channels. In SR waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. Even channels output waveforms. Odd channels output no waveforms. 2. This setting is valid only for channels 0 and 1 in the groups 2 and 3. To use ISTxD2 or IE OUT , set the MOD2 to MOD0 bits in the G2POCR0 register to "1112". To use ISCLK2 for an output, set the MOD2 to MOD0 bits in the G2POCR1 register to "1112". Do not set the MOD2 to MOD0 bits to "1112" except in the channels 0 and 1. To use ISTxD3, set the MOD2 to MOD0 bits in the G3POCR0 register to "1112". To use ISCLK3 for an output, set the MOD2 to MOD0 bits in the G3POCR1 register to"1112". Do not set the MOD2 to MOD0 bits to "1112" except in the channels 0 and 1. 3. The inverse output function is the final step in the waveform generation process. If the INV bit is set to "1" (output inversed), the output signal is "H" when the IVL bit is set to "0" (outputs "L" as an initial value) and "L" when the IVL bit is set to "1" (outputs "H" as an initial value). 4. The PRT bit is valid when the RTP bit is set to "1" (real-time port function used) and the PRP bit in the GiBCR1 register is set to "1" (parallel RTP output mode). 5. When the RTP bit is set to "1", the value written to the MOD2 to MOD0 bits is ignored. Not triggered by matching the base timer with the GiPO0 to GiPO7 registers 1: Triggered by matching the base timer with the GiPO0 to GiPO7 registers 0: Reloads the GiPOj register when counter is written to 1: Reloads the GiPOj register when the base timer is reset b7 b6 b5 b4 b3 b2 b1 b0

Page 261 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figure 21.13 G0PO0 to G0PO7, G1PO0 to G1PO7, G2PO0 to G2PO7, G3PO0 to G3PO7 Registers and G3MK4 to G3MK7 Registers Group 3 Waveform Generation Mask Register j (j=4 to 7) Symbol Address After Reset G3MK4, G3MK5 0199 16-019816, 019B16-019A16 Indeterminate G3MK6, G3MK7 019D 16-019C16, 019F16-019E16 Indeterminate RW RW Function NOTES: 1. This function is enabled in single-phase waveform output mode or phase-delayed waveform output mode. Set the G3MKi register to "000016" in other modes. When one or more bit k (k=0 to 15) in this register is set to "1", the bit k in the group 3 base timer is masked. The masked value is compared to the G3POj register (1). b7 b0 Setting Range 000016 to FFFF 16 b15 b8 Group i Waveform Generation Register j (i=0 to 3; j=0 to 7) Symbol G0PO0 to G0PO2 G0PO3 to G0PO5 G0PO6 to G0PO7 G1PO0 to G1PO2 G1PO3 to G1PO5 G1PO6 to G1PO7 G2PO0 to G2PO2 G2PO3 to G2PO5 G2PO6 to G2PO7 G3PO0 to G3PO2 G3PO3 to G3PO5 G3PO6 to G3PO7 RW RW Function Setting Range b15 b8 Address 00C1 16-00C016, 00C3 16-00C216, 00C5 16-00C416 00C7 16-00C616, 00C9 16-00C816, 00CB 16-00CA16 00CD 16-00CC16, 00CF 16-00CE16 010116-010016, 010316-010216, 010516-010416 010716-010616, 010916-010816, 010B16-010A16 010D 16-010C16, 010F16-010E16 014116-014016, 014316-014216, 014516-014416 014716-014616, 014916-014816, 014B16-014A16 014D 16-014C16, 014F16-014E16 018116-018016, 018316-018216, 018516-018416 018716-018616, 018916-018816, 018B16-018A16 018D 16-018C16, 018F16-018E16 After Reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate

When the RLD bit in the GiPOCRj register is set to "0", value written is immediately reloaded into the GiPOj register to output, for example, a waveform reflecting the value
When the RLD bit is set to "1", the value is reloaded when the base timer is reset. The value written can be read until reload. b7 b0 000016 to FFFF 16

Page 262 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O)T38/C23M,38/C23M(puorG38/C23M Figure 21.14 G0FS and G1FS Registers and G0FE to G3FE Registers Group i Function Select Register (i=0, 1) Symbol Address After Reset G0FS, G1FS 00E7 16, 012716 00 16 RW RW RW RW RW RW RW RW RW Bit NameBit Symbol b7 b6 b5 b3 b2 b1b4 b0 FSC0 FSC1 FSC2 Channel 0 Time Measurement/ Waveform Generation Function Select Bit FSC3 FSC4 FSC5 FSC7 Function FSC6 0 : Selects the waveform generation function 1 : Selects the time measurement function Channel 1 Time Measurement/ Waveform Generation Function Select Bit Channel 2 Time Measurement/ Waveform Generation Function Select Bit Channel 3 Time Measurement/ Waveform Generation Function Select Bit Channel 4 Time Measurement/ Waveform Generation Function Select Bit Channel 5 Time Measurement/ Waveform Generation Function Select Bit Channel 6 Time Measurement/ Waveform Generation Function Select Bit Channel 7 Time Measurement/ Waveform Generation Function Select Bit NOTES: 1. No 16-bit waveform generation function is provided for channels 2, 3, 6 and 7 of the group 0. No 16-bit time measurement function is provided for channels 0, 3, 4 and 5 of the group 1. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement or waveform generation function), set the same values in the G0FS and G1FS registers. Group i Function Enable Register (i=0 to 3) Symbol Address After Reset G0FE to G3FE 00E6 16, 012616, 016616, 01A616 00 16 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Bit NameBit Symbol IFE0 IFE1 IFE2 Channel 0 Function Enable Bit IFE3 IFE4 IFE5 IFE7 Function IFE6 0 : Disables functions for channel j 1 : Enables functions for channel j (j=0 to 7)Channel 1 Function Enable Bit Channel 2 Function Enable Bit Channel 3 Function Enable Bit Channel 4 Function Enable Bit Channel 5 Function Enable Bit Channel 6 Function Enable Bit Channel 7 Function Enable Bit

Page 263 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Base Timer))T38/C23M,38/C23M(puorG38/C23M Figure 21.15 G2RTP AND G3RTP Registers Group i RTP Output Buffer Register (i=2, 3) Symbol Address After Reset G2RTP, G3RTP 0167 16, 01A716 00 16 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Bit NameBit Symbol RTP0 RTP1 RTP2 Channel 0 RTP Output Buffer RTP3 RTP4 RTP5 RTP7 Function RTP6 0 : Outputs "L" 1 : Outputs "H" Channel 1 RTP Output Buffer Channel 2 RTP Output Buffer Channel 3 RTP Output Buffer Channel 4 RTP Output Buffer Channel 5 RTP Output Buffer Channel 6 RTP Output Buffer Channel 7 RTP Output Buffer

Page 264 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Base Timer))T38/C23M,38/C23M(puorG38/C23M

21.1 Base Timer

The base timer is a free-running counter that counts an internally generated count source. Table 21.2 lists specifications of the base timer. Figures 21.5 to 21.9 show registers associated with the base timer. Figure 21.16 shows a block diagram of the base timer. Figure 21.17 shows an example of a cascaded connection. Figure 21.18 shows an example of the base timer in counter increment mode. Figure 21.19 shows an example of the base timer in counter increment/decrement mode. Figure 21.20 shows an example of two-phase pulse signal processing mode. Table 21.2 Base Timer Specifications Item Specification Count Source (fBTi) (i=0 to 3) f 1 divided by 2(n+1) (Group 0 to 3), two-phase pulse input divided by 2(n+1) (Group 0 and 1) n: determined by the DIV4 to DIV0 bits in the GiBCR0 register n=0 to 31; however no division when n=31 Counting Operation The base timer increments the counter The base timer increments/decrements the counter Two-phase pulse signal processing Counter Start Condition • When starting the base timer of each group separately, set the BTS bit in the GiBCR1 register to "1" (base timer starts counting)

When starting the base timer of multiple groups simultaneously, set the BTiS bit in the BTSR register to "1" (base timer starts counting) Counter Stop Condition Set the BTiS bit in the BTSR register to "0" (base timer reset) and the BTS bit in the GiBCR1 register to "0" (base timer reset) Base Timer Reset Condition • Synchronized with the base timer reset in different groups: Group0 : synchronized with group 1 base timer reset Group1 : synchronized with group 0 base timer reset Group2 : synchronized with group 1 base timer reset Group3 : synchronized with group 2 base timer reset
Matching values in the base timer and GiPO0 register
"L" signal applied to the external interrupt pin Group 0 : INT0 pin Group 1 : INT1 pin
Reset request from communication function (Group 2 and 3) Value when the Base Timer is Reset"000016" Interrupt Request The BTiR bit in the interrupt request register is set to "1" (interrupt requested) when bit 14 or bit 15 in the base timer overflows (See Figure 10.14.) Read from Base Timer • The GiBT register indicates counter value while the base timer is running
The GiBT register is indeterminate when the base timer is reset Write to Base Timer When a value is written while the base timer is running, the counter immediately starts counting from this value. No value can be written while the base timer is reset. Selectable Function • Cascaded connection (Group 0 and 1) Group 1 base timer is incremented every time bit 15 in the group 0 base timer overflows (See Figure 21.17)
Counter increment/decrement mode (Group 0 and 1) The base timer starts when the BTS bit or the BTiS bit is set to "1". After incrementing to "FFFF16", the counter is then decremented back to "000016". If the RST1 bit in the GiBCR1 register is set to "1" (the base timer is reset by matching with the GiPO0 register), the counter decrements after the base timer matches the GiPO0 register. The base timer increments the counter again when the counter becomes "000016." (See Figure 21.19.)

Page 265 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Base Timer))T38/C23M,38/C23M(puorG38/C23M Table 21.2 Base Timer Specifications (Continued) Item Specification Selectable Function • Two-phase pulse processing mode (Group 0 and 1) Two-phase pulse signals from P76 and P77 pins in group 0, and P80 and P81 pins in group 1 are counted (See Figure 21.20) Figure 21.16 Base Timer Block Diagram Table 21.3 Base Timer Associated Register Settings (for Time Measurement Function, Waveform Generation Function, and Communication Function) Register Bit Function G2BCR0 - Supplies operation clock to the BTSR register. Set to "0111 1111 2". BTSR - Set to "0000 0000 2" GiBCR0 BCK1 to BCK0 Select count source DIV4 to DIV0 Select divide ratio of count source IT Selects the base timer interrupt GiBCR1 RST2 to RST1 Select factors for a base timer reset BTS Used to start the base timer independently UD1 to UD0 Select how to count (Group 0 and 1) CAS Selects cascaded connection (Group 0 and 1) GiBT - Read or write base timer value Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register). GiPOCR0 MOD2 to MOD0 Set to "000 2" (single-phase waveform output mode) GiPO0 - Set reset cycle GiFS FSC0 Set to "0" (waveform generation function) GiFE IFE0 Set to "1" (channel operation start) i : Bit configurations and functions vary with each group The timer increments counter on all edge The timer decrements counter on all deges P76, P80 P77, P81 f1 Divider by 2(n+1) RST0 RST1 RST2 Other base timer reset Matching with the GiPO0 register Apply "L" to the INTi pin (Group0,1) Base timer b14 b15 Base timer interrupt request BCK1 to BCK0 IT BTiS bit in BTSR register BTS bit in GiBCR1 register Request from communication function (Group2,3) Apply two-phase pulse signal ( Group0,1) (See the BTiR bit in Figure 10.14) Overflow signal Base timer reset fBTi NOTES: 1. Divider is reset when both BTiS bit and BTS bit are set to "0". i = 0 to 3 BCK1 to BCK0, IT : Bits in the GiBCR0 register RST2 to RST0 : Bits in the GiBCR1 register (1) b0 to b13

Page 267 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Base Timer))T38/C23M,38/C23M(puorG38/C23M Figure 21.19 Counter Increment/ Decrement Mode (Group 0 and 1) b15 overflow signal BTkR bit in IIOjIR register"1" "0" "1" "0" Write "0" by program if setting to "0" (1) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "0" (bit 15 in the base timer overflows) b14 overflow signal BTkR bit in IIOjIR register "1" "0" "1" "0" Write "0" by program if setting to "0" (2) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "1" (bit 14 in the base timer overflows) FFFF 16 800016 Base Timer i Base Timer i 000016 400016 C000 16 FFFF 16 800016 Base Timer i The above applies under the following conditions: The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).

The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode). The above applies under the following conditions:
The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).
The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode). (3) When the RST1 bit in the GiBCR1 register (i= 0 to 1) is set to "1" (the base timer is reset by matching with the GiPO0 register) 800016 000016 800216 The above applies under the following conditions:
Value of GiPO0 register: "800016"
The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode).

Page 268 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Base Timer))T38/C23M,38/C23M(puorG38/C23M Figure 21.20 Base Timer Operation in Two-phase Pulse Signal Proccessing Mode (Group 0 and 1) (1) When the base timer is reset while the base timer increments the counter (2) When the base timer is reset while the base timer decrements the counter m fBTi When selects no division with the divider by 2(n+1) Base Timer i min 1 µs (Note 1) min 1 µs m+1 1 2 0 Set to "0" in this timing The base timer starts counting Group0 : P76 Group1 : P80 (A-phase) Group0 : P77 Group1 : P81 (B-phase) Group0 : INT0 Group1 : INT1 (Z-phase) Set to "1" in this timing min 1 µs (Note 1) min 1 µs m Input waveform Base Timer i m-1 FFFF 16 FFFE 160 Set to "0" in this timing i=0, 1 NOTES: 1. 1.5 f BTi clock cycles or more are required. The base timer starts counting Group0 : P76 Group1 : P80 (A-phase) Group0 : P77 Group1 : P81 (B-phase) Group0 : INT0 Group1 : INT1 (Z-phase) Set to "FFFF16" in this timing Input waveform ( ) fBTi When selects no division with the divider by 2(n+1) ( ) "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L"

Page 269 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Time Measurement Function))T38/C23M,38/C23M(puorG38/C23M

21.2 Time Measurement Function (Group 0 and 1)

When external trigger is applied, the value of the base timer is stored into the GiTMj register (i=0 to 1; j=0 to 7). Table 21.4 shows specifications of the time measurement function. Table 21.5 lists pin settings of the time measurement function. Table 21.6 lists settings of time measurement function associated registers. Figures 21.21 and 21.22 show operating examples of the time measurement function. Figure 21.23 shows an operating example of the prescaler function and gate function. Table 21.4 Time Measurement Function Specifications Item Specification Measurement Channel Group 0: Channels 0 to 7 Group 1: Channels 1, 2, 6, 7 Trigger Input Polarity Rising edge, falling edge or both edges of the INPCij pin(1) Measurement Start Condition The IFEj bit in the GiFE register is set to "1" (channel j function enabled) when the FSCj bit (i=0 to1; j=0 to 7) in the GiFS register is set to "1" (time measurement function selected) Measurement Stop Condition The IFEj bit is set to "0" (channel j function disabled) Time Measurement Timing • No prescaler : every time a trigger signal is applied

Prescaler (for channel 6 and channel 7): every GiTPRk register (k=6, 7) +1 times a trigger signal is applied Interrupt Request Generation TimingThe TMijR bit in the interrupt request register (See Figure 10.14) is set to "1" (interrupt requested) at time measurement timing INPCij Pin Function(1) Trigger input pin Selectable Function • Digital filter function The digital filter samples a trigger input signal level every f1 or fBTi cycles and passes pulse signals, matching trigger input signal level, three times
Cascaded connection function Group 0 and group 1 are connected to operate as a 32-bit base timer
Prescaler function (for channel 6 and channel 7) Time measurement is executed every GiTPRk register value +1 times a trigger signal is applied
Gate function (for channel 6 and channel 7) After time measurement by the first trigger input, trigger input cannot be received. However, trigger input can be received again by matching the base timer with the GiPOp register, or by setting the GSC bit in the GiTMCRK register to "1", when the GOC bit in the GiTMCRk register is set to "1" (gate cleared by matching the base timer with the GiPOp register (p=4 when k=6, p=5 when k=7)) NOTES: INPC0 0 to INPC07, INPC11 to INPC12, INPC16 to INPC17 pins (INPC00 to INPC07 pins during cascaded connection)

Page 270 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Time Measurement Function))T38/C23M,38/C23M(puorG38/C23M Table 21.5 Pin Settings for Time Measurement Function Pin(2) Bit and Setting PS1, PS2, PS5, PS8, PS9 PD7, PD8, PD11, PD14, PD15 IPS Register Registers Registers P74/INPC11 PS1_4 = 0 PD7_4 = 0 IPS1 = 0 P75/INPC12 PS1_5 = 0 PD7_5 = 0 P76/INPC00 PS1_6 = 0 PD7_6 = 0 IPS0 = 0 P77/INPC01 PS1_7 = 0 PD7_7 = 0 P80/INPC02 PS2_0 = 0 PD8_0 = 0 P11 1/INPC11(1) PS5_1 = 0 PD11_1 = 0 IPS1 =1 P11 2/INPC12(1) PS5_2 = 0 PD11_2 = 0 P14 2/INPC16(1) PS8_2 = 0 PD14_2 = 0 P14 3/INPC17(1) PS8_3 = 0 PD14_3 = 0 P15 0/INPC00(1) PS9_0 = 0 PD15_0 = 0 IPS0 = 1, IPS2 = 0 P15 1/INPC01(1) PS9_1 = 0 PD15_1 = 0 P15 2/INPC02(1) PD15_2 = 0 P15 3/INPC03(1) PD15_3 = 0 IPS2 = 0 P15 4/INPC04(1) PS9_4 = 0 PD15_4 = 0 P15 5/INPC05(1) PS9_5 = 0 PD15_5 = 0 P15 6/INPC06(1) PD15_6 = 0 P15 7/INPC07(1) PD15_7 = 0 NOTES: 1. This port is provided in the 144-pin package only. 2. Apply trigger to INPC0j pin (j=0 to 7) when the CAS bit in the GiBCR register is set to "1" (32-bit time measurement function). Trigger input to INPC1k pin (k=1, 2, 6, 7) is invalid. Table 21.6 Time Measurement Function Associated Register Settings Register Bit Function GiTMCRj CTS1 to CTS0 Select a time measurement trigger DF1 to DF0 Select the digital filter function GT, GOC, GSC Select the gate function PR Select the prescaler function GiTPRk - Setting value of the prescaler GiFS FSCj Set to "1" (time measurement function) GiFE IFEj Set to "1" (channel j function enabled) i = 0 to 1; j = 0 to 7; k = 6, 7 Bit configurations and functions vary with channels and groups used. Registers associated with the time measurement function must be set after setting registers associated with the base timer.

Page 271 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Time Measurement Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.21 Time Measurement Function (1) FFFF 16 p p n n m m Base timer i Input to the INPCij pin 000016 GiTMj register TMijR bit Write "0" by program if setting to "0" i=0,1 j=0 to 7 (except j=1, 2, 6, 7 when i=1) TMijR bit : Bits in the IIO0IIR to IIO8IR and IIO10IR to IIO11IR registers To set the base timer to "000016" (setting the RST1 bit to "1" and the RST0 and RST2 bits to "0") when the base timer matches the GiPO0 register, the base timer is set to "000016" after it reaches the value set in the GiPO0 register + 2. The above applies under the following conditions: The CTS1 to CTS0 bits in the GiTMCRj register are set to "012" (rising edge). The PR bit is set to "0" (no prescaler used) and the GT bit is set to"0" (no gate function used). The RTS2 to RTS0 bits in the GiBCR1 register are set to "0002" (no base timer reset). The UD1 to UD0 bits are set to "002" (counter increment mode) and the CAS bit is set to "0" (16-bit time measurement or waveform generation function). "H" "L" "1" "0"

Page 272 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Time Measurement Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.22 Time Measurement Function (2) n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n+5 n+8 n-2 n-1 n n+1 n+2 n+3 n+4 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 Delayed by max. 1 clock fBTi(1) Base timer i INPCij pin input GiTMj register (1) When selecting the rising edge as a time measurement trigger (The CTS1 to CTS0 bits in the GiTMCR register (i=0,1, j=0 to 7)=012) TMijR bit(2) NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments counter every time the group 0 base timer overflows. 2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR bit if the CAS bit is set to "1". 3. Input pulses applied to the INPCij pin require 1.5 f BTi clock cycles or more. (Note 3) (2) When selecting both edges as a time measurement trigger (The CTS1 to CTS0 bits=112) Maximum 3.5 fi or fBTi(1) clock cycles (3) Trigger signal when using the digital filter (The DF1 to DF0 bits in the GiTMCR register =102 or 112) Signal, which does not match three times, is stripped off fBTi(1) Base timer i INPCij pin input GiTMj register TMijR bit(2) fi or fBTi(1) INPCij pin Trigger signal after passing the digital filter NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments the counter whenever the group 0 base timer overflows. 2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR register if the CAS bit is set to "1". 3. No interrupt is generated if the microcomputer receives a trigger signal when the TMijR bit is set to "1". Howver, the value of the GiTMj register changes. NOTES: 1. f BTi when the DF1 to DF0 bits are set to "102", and f1 when to "112". The trigger signal is delayed by the digital filter Write "0" by program if setting to "0" Write "0" by program if setting to "0" n+5 n+6 (Note 3) "H" "L" "H" "L" "1" "0" "1" "0" "H" "L" "H" "L" nn + 2 n+5 n+8 n+12n+6

Page 273 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Time Measurement Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.23 Prescaler Function and Gate Function fBTi(1) Base timer i TMijR bit(3) GiTMj register Internal time measurement trigger Prescaler (2) (1) With the prescaler function (When the GiTPRj register (i=0, 1, j=6, 7) =0216, the PR bit in the GiTMCR register=1) fBTi(1) Base timer i INPCij pin input Internal time measurement trigger IFEj bit in GiFE register GiPOk register match signal Gate control signal (2) GiTMj register TMijR bit(3) Value of the GiPOk register This trigger input is disabled due to the gate function. 21 0 FFFF 16 000016 n-2 n-1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+14 n n+12 NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments the counter every time the group 0 base timer overflows. 2. This applies to the second or later prescaler cycles after the PR bit in the GiTMCRj register is set to "1". 3. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11IR registers. The TM0jR register if the CAS bit is set to "1". (2) With the gate function (The gate function is cleared by matching the base timer with the GiPOk register. the GT bit in the GiTMCRj register=1, the GOC bit=1) INPCij pin input Gate GateGate cleared n+12 n+13 Write "0" by program if setting to "0" Write "0" by program if setting to "0" NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments the counter every time the group 0 base timer overflows. 2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11IR registers. The TM0jR register if the CAS bit is set to "1". "H" "L" "H" "L" "1" "0" "1" "0" "H" "L" "H" "L" "H" "L" "H" "L" "1" "0" n+1n

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21.3 Waveform Generation Function

Waveforms are generated when the value of the base timer matches the GiPOj register (i=0 to 3; j=0 to 7). The waveform generation function has the following six modes :

Single-phase waveform output mode (group 0 to 3)
Phase-delayed waveform output mode (group 0 to 3)
Set/Reset waveform output (SR waveform output) mode (group 0 to 3)
Bit modulation PWM output mode (group 2 and 3)
Real-time port output (RTP output) mode (group 2 and 3)
Parallel real-time port output (parallel RTP output) mode (group 2 and 3) Table 21.7 lists pin settings of the waveform generation function. Table 21.8 lists registers associated with the waveform generation function. Table 21.7 Pin Settings for Waveform Generation Function (1/2) Pin Bit and Setting PS0 to PS2, PS5 to PS9 RegistersPSL0, PSL1, PSL2, PSL3 RegistersPSC Register P64/OUTC2 1 PS0_4 = 1 PSL0_4 = 1 - P70/OUTC2 0 PS1_0 = 1 PSL1_0 = 0 PSC_0 = 1 P71/OUTC2 2 PS1_1 = 1 PSL1_1 = 0 PSC_1 = 1 P73/OUTC1 0(2) PS1_3 = 1 PSL1_3 = 0 PSC_3 = 1 P74/OUTC1 1(2) PS1_4 = 1 PSL1_4 = 0 PSC_4 = 1 P75/OUTC1 2(2) PS1_5 = 1 PSL1_5 = 1 - P76/OUTC0 0(2) PS1_6 = 1 PSL1_6 = 0 PSC_6 = 0 P77/OUTC0 1(2) PS1_7 = 1 - - P81/OUTC3 0 PS2_1 = 1 PSL2_1 = 1 - P82/OUTC3 2 PS2_2 = 1 PSL2_2 = 0 - P92/OUTC2 0 PS3_2 = 1 PSL3_2 = 1 - P11 0/OUTC1 0(1,2) PS5_0 = 1 - - P11 1/OUTC1 1(1,2) PS5_1 = 1 P11 2/OUTC1 2(1,2) PS5_2 = 1 P11 3/OUTC1 3(1,2) PS5_3 = 1 P12 0/OUTC3 0(1) PS6_0 = 1 - - P12 1/OUTC3 1(1) PS6_1 = 1 P12 2/OUTC3 2(1) PS6_2 = 1 P12 3/OUTC3 3(1) PS6_3 = 1 P12 4/OUTC3 4(1) PS6_4 = 1 P12 5/OUTC3 5(1) PS6_5 = 1 P12 6/OUTC3 6(1) PS6_6 = 1 P12 7/OUTC3 7(1) PS6_7 = 1 P13 0/OUTC2 4(1) PS7_0 = 1 - - P13 1/OUTC2 5(1) PS7_1 = 1 NOTES: 1. This port is provided in the 144-pin package only. 2. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), the OUTC1j pin (j=0 to 7) outputs a waveform and the OUTC0k pin (k=0, 1, 4, 5), set as above, outputs a 16-bit low-order waveform.

Page 275 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M Table 21.7 Pin Settings for Waveform Generation Function (2/2) Pin Bit and Setting PS0 to PS2, PS5 to PS9 RegistersPSL0, PSL1, PSL2, PSL3 RegistersPSC Register P132/OUTC2 6(1) PS7_2 = 1 - - P133/OUTC2 3(1) PS7_3 = 1 P134/OUTC2 0(1) PS7_4 = 1 P135/OUTC2 2(1) PS7_5 = 1 P136/OUTC2 1(1) PS7_6 = 1 P137/OUTC2 7(1) PS7_7 = 1 P141/OUTC1 5(1,2) PS8_1 = 1 P142/OUTC1 6(1,2) PS8_2 = 1 P143/OUTC1 7(1,2) PS8_3 = 1 P151/OUTC0 1(1,2) PS9_1 = 1 P154/OUTC0 4(1,2) PS9_4 = 1 P155/OUTC0 5(1,2) PS9_5= 1 NOTES: 1. This port is provided in the 144-pin package only. 2. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), the OUTC1j pin (j=0 to 7) outputs a waveform and the OUTC0k pin (k=0, 1, 4, 5), set as above, outputs a 16-bit low-order waveform. Table 21.8 Waveform Generation Function Associated Register Settings Register Bit Function GiPOCRj MOD2 to MOD0 Select waveform output mode PRT (1) Set to "1" when using the parallel RTP output mode IVL Select default value RLD Select reload timing of GiPOj register value RTP (1) Set to "1" when using the RTP output or the parallel RTP output mode MOD2 to MOD0 bits are invalid when the RTP bit is set to "1" INV Select inversed output G2BCR1 PRP Set to "1" when using the parallel RTP output mode G3BCR1 GiPOj - Select output waveform inverse timing G3MK4 to - Set masked values of the base timer and G3PO4 to G3PO7 registers G3MK7 (group 3 only) GiFS FSCj Set to "0" (waveform generation function) (group 0 and 1 only) GiFE IFEj Set to "1" (enables channel j function) G2RTP RTP0 to Set RTP output value in RTP output or parallel RTP output mode G3RTP RTP7 i = 0 to 3; j = 0 to 7 Bit configurations and functions vary with channels and groups used. Set registers associated with the waveform generation function after setting registers associated with the base timer. NOTES: 1. This bit is in the G2POCRj and G3POCRj registers only.

Page 276 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M m fBTi 65536-m f BTi n+2 f BTi m f BTi n+2-m f BTi 65536 f BTi

21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3)

Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) becomes high ("H") when the value of the base timer matches that of the GiPOj register . The "H" signal switches to an "L" signal when the base timer reaches "0000 16". If the IVL bit in the GiPOCRj register is set to "1" (outputs "H" as default value), an "H" signal is output when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the waveform being output is inversed. See Figure 21.24 for details on single-phase waveform mode opera- tion. Table 21.9 lists specifications of single-phase waveform mode. Table 21.9 Single-phase Waveform Output Mode Specifications Item Specification Output Waveform(3) • Free-running operation (the RST2 to RST0 bits in the GiBCR1 (i=0 to 3) register are set to "0002") Cycle : "L" width : "H" width : m : setting value of the GiPOj register (j=0 to 7), 0000 16 to FFFF16

The base timer is reset by matching the base timer with the GiPO0 register (the RST1 bit is set to "1", and the RST0 and the RST2 bit are set to "0") Cycle : "L" width : "H" width : m : setting value of the GiPOj register (j=1 to 7), 0000 16 to FFFF16 n : setting value of the GiPO0 register, 000116 to FFFD16 If m ≥ n+2, the output level is fixed to "L" Waveform Output Start Condition(1) The IFEj bit in the GiFE register is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. (See Figure 10.14) OUTCij Pin(2) Pulse signal output pin Selectable Function • Default value set function : Set starting waveform output level
Inversed output function : Waveform output level is inversed and output from the OUTCij pin
Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 2. OUTC00, OUTC01, OUTC04, OUTC05, OUTC10 to OUTC17, OUTC20 to OUTC27, and OUTC30 to OUTC37 pins (OUTC10 to OUTC17 pins when using group 0 and group 1 cascaded connection) 3. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed

Page 277 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.24 Single-Phase Waveform Output Mode FFFF 16 m m fBTi 65536-m f BTi 65536 f BTi Base Timer i (1) Free-Running Operation (The RST2 to RST0 bits in the GiBCR1 register are set to "0002") (2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register (The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") 000016 OUTCij pin(1) OUTCij pin(2) POijR bit in the IIOiIR register POijR bit in the IIOiIR register i=0 to 3; j=0 to 7 (however, i=0 when j=0, 1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) POijR bit: Bits in the IIO0IR to IIO11IR register OUTCij pin m n+2 Base Timer i 000016 m fBTi n+2-m f BTi n+2 f BTi i=0 to 3; j=1 to 7 (however, i=0 when j=1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) n : Setting value of the GiPO0 register (000116 to FFFD16) POijR bit: Bits in the IIO0IR to IIO11IR register The above diagram applies under the following conditions:

The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as default value). The INV bit is set to "0" (not inverse).
The UD1 to UD0 bits in the GiBCR1 register are set to "00 2" (counter increment mode), and the CAS bit to "0" (16-bit waveform generation function)
m < n+2 NOTES: 1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and the IVL bit is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" (output "H" as default value). Write "0" by program if setting to "0" Write "0" by program if setting to "0" "H" "L" "L" "0" "1" "H" "H" "L" "0" "1" The above applies applies under the following conditions:
The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset), the UD1 to UD0 bits to "002" (counter increment mode), and CAS bit to "0" (16-bit waveform generation function)

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21.3.2 Phase-Delayed Waveform Output Mode (Group 0 to 3)

Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) is inversed every time the value of the base timer matches that of the GiPOj register. Table 21.10 lists specifications of phase-delayed waveform mode. Figure 21.25 shows an example of phase-delayed waveform mode operation. Table 21.10 Phase-delayed Waveform Output Mode Specifications Item Specification Output Waveform • Free-running operation (the RST2 to RST0 bits in the GiBCR1 register (i=0 to 3) are set to "0002") Cycle : "H" and "L" width : Setting value of the GiPOj (j=0 to 7) register is 000016 to FFFF16

The base timer is reset by matching the base timer with the GiPO0 register (the RST1 bit is set to "1", and the RST0 and RST2 bit are set to "0") Cycle : "H" and "L" width : n : setting value of the GiPO0 register, 000116 to FFFD16 Setting value of the GiPOj (j=1 to 7) register is 000016 to FFFF16 If GiPOj register ≥ n+2, the output level is not inversed Waveform Output Start Condition(1) The IFEj bit (j=0 to 7) in the GiFE register is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. (See Figure 10.14) OUTC1j Pin Pulse signal output pin Selectable Function • Default value set function : Set starting waveform output level
Inversed output function : Waveform output level is inversed and output from the OUTCij pin
Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 2. OUTC00, OUTC01, OUTC04, OUTC05, OUTC10 to OUTC17, OUTC20 to OUTC27, and OUTC30 to OUTC37 pins (OUTC10 to OUTC17 pins when using group 0 and group 1 cascaded connection) 65536 x 2 fBTi 65536 f BTi 2(n+2) f BTi n+2 f BTi

Page 279 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.25 Phase-delayed Waveform Output Mode FFFF 16 m 65536 fBTi 65536X2 f BTi 000016 m n+2 000016 65536 fBTi m f BTi n+2 f BTi n+2 f BTi 2(n+2) f BTi Base Timer i (1) Free-Running Operation (The RST2 to RST0 bits in the GiBCR1 register are set to "0002") OUTCij pin(1) OUTCij pin(2) POijR bit i=0 to 3; j=0 to 7 (however, i=0 when j= 0, 1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) POijR bit: Bits in the IIO0IR to IIO11IR registers Inverse Inverse Write "0" by program if setting to "0" Inverse Inverse (2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register (The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") PO1jR bit OUTCij pin Base Timer i Write "0" by program if setting to "0" Inverse i=0 to 3; j=0 to 7 (however, i=0 when j=1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) n : Setting value of the GiPO0 register (000116 to FFFD16) POijR bit: Bits in the IIO0IR to IIO11IR registers The above diagram applies under the following conditions:

The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as initial value). The INV bit is set to "0" (not inversed).
The UD1 to UD0 bits in the G1BCR1 register are set to "00 2" (counter increment mode) and the CAS bit to "0" (16-bit waveform generation function).
m < n+2 Inverse Inverse "H" "L" "H" "H" "1" "0" "L" "L" "1" "0 " NOTES: 1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and the IVL bit is set to "0" (output "L" as initial value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" (output "H" as initial value). The above diagram applies under the following condition:
The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset), the UD1 to UD0 bits to "002" (counter increment mode), and the CAS bit to "0" (16-bit waveform generation function).

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21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode (Group 0 to 3)

Output signal level of the OUTCij pin (i=0 to 3; j=0, 2, 4, 6) becomes "H" when the value of the base timer matches that of the GiPOj register. The "H" signal switches to an "L" signal when the value of the base timer matches that of the GiPOk register (k=j+1) or when the base timer is set to "0000 16". If the IVL bit in the GiPOCRj register (j=0 to 7) is set to "1" (outputs "H" as initial value), an "H" signal is output when waveform output starts. If the INV bit is set to "1" (output is inversed), the level of the waveform being output is inversed. Table 21.11 lists specifications of SR waveform mode. Figure 21.26 shows an ex- ample of a SR waveform mode operation. Table 21.11 SR Waveform Output Mode Specifications (1/2) Item Specification Output Waveform(2) • Free-running operation (the RST2 to RST0 bits in the GiBCR1 register are set to "0002") (1) m < n "H" width : "L" width : (2) m ≥ n "H" width : "L" width : m : setting value of the GiPOj register (j=0, 2, 4, 6) n : setting value of the GiPOk register (k=j+1) m, n=000016 to FFFF16

The base timer is reset by matching the base timer with the GiPO0 register(1) (the RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") (1) m < n < p+2 "H" width : "L" width : (2) m < p+2 ≤ n "H" width : "L" width : (3) If m ≥ p+2, the output level is fixed to "L" m : setting value of the GiPOj register (j=2, 4, 6) n : setting value of the GiPOk register (k=j+1) p : setting value of the GiPO0 register m, n=0000 16 to FFFF16 p=000116 to FFFD16 NOTES: 1. When the GiPO0 register resets the base timer, the channel 0 and 1 SR waveform generation functions are not available. 2. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. 3. Waveform from base timer reset until when output level becomes "H". 4. Waveform from when output level becomes "L" until base timer reset. m (3) fBTi n - m fBTi + 65536 - n(4) fBTi 65536 - m fBTi m f BTi n-m f BTi m (3) fBTi + p + 2 - n(4) fBTi p + 2 - n fBTi m f BTi

Page 281 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M Table 21.11 SR Waveform Output Mode Specifications (2/2) Item Specification Waveform Output Start Condition(5) The IFEq bit (q=0 to 7) in the GiFE register is set to "1" (channel q function enabled) Waveform Output Stop Condition The IFEq bit is set to "0" (channel q function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. The POikR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOk register. (See Figure 10.14) OUTCij Pin(6) Pulse signal output pin Selectable Function • Default value set function : Set starting waveform output level

Inversed output function : Waveform output level is inversed and output from the OUTCij pin
Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 5. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 6. OUTC00, OUTC0 4, OUTC1 0, OUTC1 2, OUTC1 4, OUTC1 6, OUTC2 0, OUTC2 2, OUTC2 4, OUTC2 6, OUTC3 0, OUTC3 2, OUTC34, and OUTC36 pins (OUTC10, OUTC12, OUTC14, and OUTC16 pins when using group 0 and group 1 cascaded connection)

Page 282 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M FFFF 16 m n n-m fBTi 65536 f BTi 000016 m p+2 n 000016 65536-n+m fBTi n-m f BTi p+2-n+m f BTi p+2 f BTi (1) Free-Running Operation (The RST2 to RST0 bits in the GiBCR1 register are set to "0002") i=0, 3; j=0, 2, 4, 6 (however, i=0 when j=0, 4); k=j+1 m : Setting value of the GiPOj register (000016 to FFFF16) n : Setting value of the GiPOk register (000016 to FFFF16) POijR, POikR bits: Bits in the IIO0IR to IIO11IR registers Write "0" by program if setting to "0" Write "0" by program if setting to "0" (2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register (The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") i=0 to 3; j=2, 4, 6 (however, i=0 when j=4); k=j+1 m : Setting value of the GiPOj register (000016 to FFFF16) n: Setting value of the GiPOk register (000016 to FFFF16) p: Setting value of the GiPO0 register (000116 to FFFD16) POijR, POikR bits: Bits in the IIO0IR to IIO11IR registers Write "0" by program if setting to "0" Write "0" by program if setting to "0" Base timer i OUTCij pin POijR bit POikR bit Base Timer i OUTCij pin(1) OUTCij pin(2) POijR bit POikR bit The diagram above applies under the following conditions:

The IVL bit in the GiPOCRk register is set to "0" (outputs "0" as default value). The INV bit is set to "0" (not inversed).
The UD1 to UD0 bits in the GiBCR1 register are set to "00 2" (counter increment mode) and the CAS bit to "0" (16-bit waveform generation function).
m < n < p+2 NOTES: 1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and the IVL bit is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" (output "H" as default value). "H" "H" "L" "L" "0" "1" "0" "1" "H" "L" "0" "0" "1" "1" The diagram above applies under the following condition:
The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset), the UD1 to UD0 bits to "002" (counter increment mode), and the CAS bit to "0" (16-bit waveform generation function).
m < n Figure 21.26 SR Waveform Output Mode

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21.3.4 Bit Modulation PWM Output Mode (Group 2 and 3)

In bit modulation PWM output mode, PWM output has a 16-bit resolution. Pulses are output in repetitive cycles, each cycle consisting of span t repeated 1024 times. Span t, itself, has a cycle of . The six high-order bits in the GiPOj register (i=2 to 3; j=0 to 7) determine the "L" base width. The 10 low-order bits determine the number of span t, within a cycle, in which "L" width is extended by the minimum resolution bit width (1 clock cycle). If the INV bit is set to "1" (output is inversed), the level of the waveform being output is inversed. Table 21.12 lists specifications of bit modulation PWM output mode. Table 21.13 lists the number of modulated span and minimum resolution bit width altered span t. Figure 21.27 shows an example of bit modulation PWM mode operation. Table 21.12 Bit Modulation PWM Output Mode Specifications Item Specification Output Waveform(1,2) PWM-repeated cycle T: (= X1024) Cycle of span t: "L" width: of m spans of (1024-m) spans Average "L" output width: X (n+ ) n: Setting values (six high-order bits) of the GiPOj register (i=2 to 3; j=0 to 7) 16 to 3F16 m: Setting values (ten low-order bits) of the GiPOj register 0016 to 3FF16 Waveform Output Start Condition The IFEj bit in the GiFE register is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" when the value of the six low-order bits of the base timer matches those set in the six high-order bits of the GiPOj register (see Figure 10.14). OUTCij Pin Pulse signal output pin Selectable Function • Default value set function : Set starting waveform output level

Inversed output function : Waveform output level is inversed and output from the OUTCij pin NOTES: 1. Set the RST2 to RST0 bits in the GiBCR1 register to "0002" when using the bit modulation PWM mode. 2. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. Table 21.13. Number of Modulated Spans and Minimum Resolution Bit Width Extended Span t Number of Modulated Spans Minimum Resolution Bit Width Extended Span t 00 0000 00002 none 00 0000 00012 t512 00 0000 00102 t256, t768 00 0000 01002 t128, t384, t640, t896 00 0000 10002 t64, t192, t320, t448, t576, t704, t832, t960 10 0000 00002 t1, t3, t5, t7, t1019, t1021, t1023 fBTi n+1 f BTi n f BTi m 1024 65536 f BTi f BTi f BTi
••

Page 284 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M /LiteDiagLines /LiteDiagLines /LiteDiagLines 0016 3F16 PWM-repeated cycle T "L" width of m span out of 1024 is extended by minimum resolution bit width n b15 b10 b9 b0 n+1 n t1 t2 t3 1 span n fBTi n Minimum resolution bit width 0016 3F16 Inverse Inverse "L" level "L" level Write "0" by program if setting to "0" Write "0" by program if setting to "0" m=1; i=2 to 3; j=0 to 7 POijR bit : Bits in the IIO3IR to IIO11IR registers The above applies to the following conditions.

The IVL bit in the GiPOCR is set to "0" (default value output as "L")
The INV bit is set to "0" (no output inversed) 6 low-order bits in the base timer Base width n=0 to 63 (3F16) Modulated span m=0 to 1023 (3FF16) GiPOj register OUTCij pin Internal signal OUTCij pin POijR bit 6 low-order bits in the base timer t510 t512 t3t511 t513 t514 t1022 t1023 t1024 Figure 21.27 Bit Modulation PWM Mode

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21.3.5 Real-Time Port (RTP) Output Mode (Group 2 and 3)

The OUTCij pin outputs the value set in the GiRTP register in one-byte units by matching the value of the base timer with that of the GiPOj register (i=2 to 3, j=0 to 7). Table 21.14 lists specifications of RTP output mode. Figure 21.28 shows a block diagram of the RTP output function. Figure 21.29 shows an example of RTP output mode operation. Table 21.14 RTP Output Mode Specifications Item Specification Waveform Output Start ConditionThe IFEj bit in the GiFE register (i=2 to 3, j=0 to 7) is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" when the value of the base timer matches that of the GiPOj register (000016 to FFFF16(1)). (See Figure 10.14.) OUTCij Pin RTP output pin Selectable Function • Default value set function : Set starting waveform output level

Inversed output function : Waveform output level is inversed and output from the OUTCij pin NOTES: 1. Set the GiPO0 register to 000116 to FFFD16 when setting the base timer to "000016" (the RST1 bit in the GiBCR1 register is set to "1", and the RST0 and RST2 bits are set to "0") while the values in the base timer and the GiPO0 register match /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines GiPO0 register Base Timer DQ T RTP0 RTP6 RTP7 DQ T DQ T GiPO6 register GiPO7 register Real-time Port Output OUTCi 0 OUTCi 6 OUTCi 7 GiRTP register Figure 21.28 Real-time Port Output Function Block Diagram

Page 286 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M Base timer i (1) Free-running operation (RST2 to RST0 bits in the GiBCR1 register are set to "0002") OUTCij pin POijR bit i=2 to 3, j=0 to 7 m : Setting value of the GiPOj register (000016 to FFFF16) POijR bit : Bits in the IIO3IR to IIO11IR registers The above applies to the following conditions. The IVL bit in the GiPOCRj register is set to "0" (output "L" as an initial value). The INV bit is set to "0" (no output inversed). RST2 to RST0 bits in the GiBCR1 register are set to "000 2" (no base timer reset). (2) The base timer is reset when the base timer matches the GiPO0 register (The RST1 bit is set to "1" and both RST0 and RST2 bits are set to "0") i=2 to 3, j=1 to 7 m : Setting value of the GiPOj register (000016 to FFFF16) n: Setting value of the GiPO0 register (000116 to FFFD16) POijR bit : Bits in the IIO0IR to IIO11IR registers The above applies to the following condition. The IVL bit in the GiPOCRj register is set to "0" (output "L" as an initial value). The INV bit is set to "0" (no output inversed). m < n+2 FFFF 16 m 0 1 m 65535 000016 m n+2 FFFF 16 m n+2 0 1 000016 RTPj bit Base timer i OUTCij pin POijR bit Write "0" by program if setting to "0" Write "0" by program if setting to "0" "H" "L" "1" "0" "H" "L" "1" "0" RTPj bit Figure 21.29 Real-time Port Output Mode

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21.3.6 Parallel Real-Time Port Output Mode (Group 2 and 3)

The OUTCij pin outputs the value set by the GiRTP register in one-byte units when the value of the base timer matches that of the GiPOj register (i=2 to 3, j=0 to 7). Table 21.15 lists specifications of the parallel RTP output mode. Figure 21.30 shows a block diagram of the parallel RTP output function. Figure 21.31 shows an example of the parallel RTP output mode operation. (See Figure 21.7 for the G2BCR1 register and Figure 21.8 for the G3BCR1 register.) Table 21.15 Parallel RTP Output Mode Specifications Item Specification Waveform Output Start ConditionThe IFEj bit in the GiFE register (i=2 to 3, j=0 to 7) is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" when value of the base timer matches that of the GiPOj register (000016 to FFFF16(1)). (See Figure 10.14.) OUTCij Pin RTP output Selectable Function • Default value set function: Set starting waveform output level

Inverse output function: Waveform output level is inversed and output from the OUTCij pin NOTES: 1. Set the GiPO0 register to 000116 to FFFD16 when setting the base timer to "000016" (the RST1 bit in the GiBCR1 register is set to "1", and the RST0 and RST2 bits are set to "0") while the values in the base timer and the GiPO0 register match /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines DQ T RTP0 RTP1 RTP2 RTP3 RTP4 RTP5 RTP6 RTP7 DQ T DQ T DQ T DQ T DQ T DQ T DQ T Real-time Port Output GiRTP register GiPO0 register Base Timer GiPO1 register GiPO2 register GiPO3 register GiPO4 register GiPO5 register GiPO6 register GiPO7 register OUTCi 0 OUTCi 1 OUTCi 2 OUTCi 3 OUTCi 4 OUTCi 5 OUTCi 6 OUTCi 7i=2 to 3 Figure 21.30 Parallel RTP Output Function Block Diagram

Page 288 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Waveform Generation Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.31 Parallel RTP Output Mode FFFF 16 XCX3 X6 m n p X0 X1 Base timer i 000016 GiRTP register OUTCi 0 pin OUTCi 1 pin OUTCi 2 pin OUTCi 3 pin m : Setting value of the GiPO0 register n : Setting value of the GiPO1 register p : Setting value of the GiPO2 register POi0R, POi1R, POi2R bit : Bits in the IIO3IR to IIO11IR registers i=2,3 POi0R bit POi1R bit POi2R bit (1) Free-running operation The above applies to the following conditions. The IVL in the of GiPOCRj register is set to "0" (output "L" as an initial value). The INV bit is set to "0" (no output inversed). All RST0 to RST2 bits in the GiBCR1 register are set to "000 2" (no base timer reset). m < n < p

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21.4 Communication Unit 0 and 1 Communication Function

The communication function is available when two 8-bit shift registers are used with either timer measure- ment function or waveform generation function. In the intelligent I/O groups 0 and 1, 8-bit clock synchronous serial I/O, 8-bit clock asynchronous serial I/O (UART) and HDLC data processing are available. Figures 21.32 to 21.38 show registers associated with the communication function. Figure 21.32 G0RI to G1RI Registers and G0TO to G1TO Registers Group i Receive Input Register (i=0,1) Symbol Address After Reset G0RI,G1RI 00EC 16, 012C16 Indeterminate RW WO Function Setting Range b7 b0 Set data to be transmitted to a received data generation circuit 0016 to FF16 Group i Transmit Output Register (i=0,1) Symbol Address After Reset G0TO, G1TO 00EE 16, 012E16 Indeterminate RW RO Function b7 b0 Can read data transmitted by a transmitted data generation circuit

Page 290 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.33 G0CR to G1CR Registers Group i SI/O Communication Control Register (i=0,1) Symbol Address After Reset G0CR, G1CR 00EF 16, 012F16 0000 X000 2 RW RW RW RO RO RO Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its contents is indeterminate. TI TXEPT RI (b3) Transmit Buffer Empty Flag TE RE Receive Complete Flag Transmit Enable Bit Receive Enable Bit 0 : No data in the GiRB register 1 : Data in the GiRB register 0 : Transmit disable 1 : Transmit enable Transmit Register Empty Flag 0 : Data in the GiTB register 1 : No data in the GiTB register b7 b6 b5 b4 b3 b2 b1 b0 0 : Receive disable 1 : Receive enable 0 : Data in the transmit register (during transmission) 1 : No data in the transmit register (transmit completed) RW RWIPOL OPOL ISRxD Input Polarity Switch Bit ISTxD Output Polarity Switch Bit 0 : No inverse 1 : Inverse(1) 0 : No inverse 1 : Inverse (1) NOTES: 1. Set to "1" when using UART mode

Page 291 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Function Group i SI/O Receive Buffer Register (i=0,1) Bit NameBit Symbol Symbol Address After Reset G0RB, G1RB 00E9 16-00E816, 012916-012816 XX00 XXXX XXXX XXX 2 RW RW RO ROFER Received data OER (b11 - b8) (b7 - b0) (b15 - b14) 0 : No overrun error 1 : Overrun error found Nothing is assigned. When read, its content is indeterminate. Nothing is assigned. When read, its content is indeterminate. Framing Error Flag 0 : No framing error 1 : Framing error found Overrun Error Flag b7 b0b15 b8 Group i SI/O Communication Mode Register (i=0,1) Symbol Address After Reset G0MR,G1MR 00ED 16, 012D16 00 16 RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. Do not set except when using in motor vehicles GMD0 GMD1 CKDIR Communication Mode Select Bit STPS UFORM (b5 - b4) IRS Internal/External Clock Select Bit Stop Bit Length Select Bit Transfer Direction Select Bit Transmit Interrupt Cause Select Bit 0 : Internal clock 1 : External clock 0 : 1 stop bit 1 : 2 stop bits 0 : LSB first 1 : MSB first 0 : No data in the transmit buffer (TI=1) 1 : Transmission is completed (TXEPT=1) : UART mode : Clock synchronous serial I/O mode : Special communication mode (1) : HDLC data processing mode b7 b6 b5 b4 b3 b2 b1 b0 Reserved Bit Set to "0" Figure 21.34 G0RB to G1RB Registers and G0MR to G1MR Registers

Page 292 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.35 G0EMR to G1EMR Registers and G0ETC to G1ETC Registers Group i SI/O Expansion Mode Register (i=0,1)(1) Symbol Address After Reset G0EMR ,G1EMR 00FC 16, 013C16 00 16 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. The GiEMR register is used in special communication mode or HDLC data processing mode. Do not use in clock synchronous serial I/O mode or UART mode. 2. The CRC is reset when a data in the GiCMP3 register matches a received data. SMODE CRCV ACRC BSINT RXSL TXSL CRC0 CRC1 Synchronous Mode Select Bit Receive Source Switch Bit Transmit Source Switch Bit 0 : Not reset 1 : Reset(2) 0 : Not used 1 : Used 0 : ISRxDi pin 1 : GiRI register 0 : ISTxDi pin 1 : GiTO register 0 : No re-synchronous mode used 1 : Re-synchronous mode CRC Default Value Select Bit 0 : Set to "0000 16" 1 : Set to "FFFF16" CRC Reset Select Bit Bit Stuffing Error Interrupt Select Bit CRC Generation Polynomial Select Bit : X8+X4+X+1 : Do not set to this value : X 16+X 15+X 2+1 : X16+X 12+X 5+1 b7 b6 b5 b4 b3 b2 b1 b0 Group i SI/O Expansion Transmit Control Register (i=0,1)(1) Symbol Address After Reset G0ETC,G1ETC 00FF 16, 013F16 0000 0XXX 2 RW RW RW RW RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. The GiETC register is used in special communication mode or HDLC data processing mode. Do not use in clock synchronous serial I/O mode or UART mode. SOF (b2 - b0) TCRCE ABTE TBSF0 TBSF1 Transmit CRC Enable Bit Arbitration Enable Bit Transmit Bit Stuffing "1" Insert Select Bit 0 : Not used 1 : Used 0 : Not used 1 : Used SOF Transmit Request Bit 0 : No request to transmit SOF 1 : Request to transmit SOF Transmit Bit Stuffing "0" Insert Select Bit 0 : "1" is not inserted 1 : "1" is inserted 0 : "0" is not inserted 1 : "0" is inserted b7 b6 b5 b4 b3 b2 b1 b0

Page 293 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.36 G0ERC to G1ERC Registers Group i SI/O Expansion Receive Control Register (i=0,1)(1) Symbol Address After Reset G0ERC,G1ERC 00FD 16, 013D16 00 16 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol CMP0E CMP1E CMP2E Data Compare Function 0 Select Bit CMP3E RCRCE RSHTE RBSF0 RBSF1 Receive CRC Enable Bit Receive Shift Operation Enable Bit 0 : Not used 1 : Used 0 : Disables receive shift operation 1 : Enables receive shift operation Data Compare Function 1 Select Bit Data Compare Function 2 Select Bit Data Compare Function 3 Select Bit 0 : "1" is not deleted 1 : "1" is deleted 0 : "0" is not deleted 1 : "0" is deleted b7 b6 b5 b4 b3 b2 b1 b0 0 : The GiDR register (transmit data register) is not compared with the GiCMP1 register 1 : The GiDR register is compared with the GiCMP1 register 0 : The GiDR register (transmit data register) is not compared with the GiCMP2 register 1 : The GiDR register is compared with the GiCMP2 register 0 : The GiDR register (transmit data register) is not compared with the GiCMP3 register 1 : The GiDR register is compared with the GiCMP3 register(2) NOTES: 1. The GiERC register is used in special communication mode or HDLC data processing mode. Set to "0010 0000 2" in clock synchronous serial I/O mode. Do not use in UART mode. 2. When the ACRC bit in the GiEMR register is set to "1" (CRC reset function used), set the CMP3E bit to "1". 0 : The GiDR register (transmit data register) is not compared with the GiCMP0 register 1 : The GiDR register is compared with the GiCMP0 register Receive Bit Stuffing "0" Delete Select Bit Receive Bit Stuffing "1" Delete Select Bit

Page 294 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.37 G0IRF to G1IRF Registers and G0TB to G1TB Registers Group i SI/O Special Communication Interrupt Detect Register (i=0,1)(1,2) Symbol Address After Reset G0IRF,G1IRF 00FE 16, 013E16 0000 00XX 2 RW RW RW RW RW RW RWBit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. The GiETC register is used in special communication mode or HDLC data processing mode. Do not use in clock synchronous serial I/O mode or UART mode. 2. The SRTiR bit in the IIO4IR register is set to "1" if the BSERR bit, ABT bit or the IRF0 to IRF3 bits is set to "0". ABT BSERR Arbitration Lost Detect Flag Bit Stuffing Error Detect Flag 0 : Not detected 1 : Detected 0 : Not detected 1 : Detected IRF0 IRF1 IRF2 Interrupt Cause Determination Flag 0 (2) IRF3 Interrupt Cause Determination Flag 1 (2) Interrupt Cause Determination Flag 2 (2) Interrupt Cause Determination Flag 3 (2) b7 b6 b5 b4 b3 b2 b1 b0 0 : The GiDR register (receive data register) does not match the GiCMP0 register 1 : The GiDR register matches the GiCMP0 register 0 : The GiDR register (receive data register) does not match the GiCMP1 register 1 : The GiDR register matches the GiCMP1 register 0 : The GiDR register (receive data register) does not match the GiCMP2 register 1 : The GiDR register matches the GiCMP2 register 0 : The GiDR register (receive data register) does not match the GiCMP3 register 1 : The GiDR register matches the GiCMP3 register (b1 - b0) Group i Transmit Buffer (Receive Data) Register (i=0,1)(1) Symbol Address After Reset G0TB,G0DR 00EA 16 Indeterminate G1TB,G1DR 012A16 Indeterminate RW WO (RO) Function b7 b0 Set data to be transmitted. Values written in these registers are written to the GiTB register. Data read from these registers in HDLC data processing mode are values written in the GiDR register NOTES: 1. The GiTB register and the GiDR register share addresses.

Page 295 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.38 G0CMP0 to G0CMP3 Registers, G1CMP0 to G1CMP3 Registers, G0MSK0 to G0MSK1 Registers, G1MSK0 to G1MSK1 Registers, G0TCRC to G1TCRC Registers, and G0RCRC to G1RCRC Registers Group i Data Compare Register j (i=0,1; j=0 to 3) Symbol Address After Reset G0CMP0 to G0CMP3 00F0 16, 00F116, 00F216, 00F316 Indeterminate G1CMP0 to G1CMP3 013016, 013116, 013216, 013316 Indeterminate RW RW Function Setting Range b7 b0 Data to be compared 0016 to FF16 NOTES: 1. Set the GiMSK0 register to use the GiCMP0 register. Set the GiMSK1 register to use the GiCMP1 register. Group i Data Mask Register j (i=0,1; j=0,1) Symbol Address After Reset G0MSK0,G0MSK1 00F4 16, 00F516 Indeterminate G1MSK0,G1MSK1 0134 16, 013516 Indeterminate Function Setting Range RW RW b7 b0 Masked data for received data Set bits not being compared to "1" 0016 to FF16 Group i Transmit CRC Code Register (i=0,1) Symbol Address After Reset G0TCRC, G1TCRC 00FB 16-00FA16, 013B16-013A16 0000 16 Function RW RO Result of the transmit CRC calculation(1,2) b7b15 b8 NOTES: 1. Calculation results are reset by setting the TE bit in the GiCR register to "0" (transmit disabled). Default value is determined by setting the CRCV bit in the GiEMR register. 2. Transmit CRC calculation is performed with every bit of transmit data transmitted while the TCRCE bit in the GiETC register is set to "1" (used). Group i Receive CRC Code Register (i=0,1) Symbol Address After Reset G0RCRC, G1RCRC 00F9 16-00F816, 013916-013816 Indeterminate Function Result of the receive CRC calculation(1, 2, 3) b7b15 b8 RW RO NOTES: 1. The calculation result is reset by setting the RCRCE bit in the GiERC register to "0" (not used). If the the ACRC bit in the GiCMPj register is set to "1" (reset), the result is reset by matching the data in the GiCMPj register with the received data. 2. The result is reset to the default value selected by the CRCV bit in the GiEMR register before reception starts. 3. Receive CRC calculation occurs with every bit of transmit data transmitted while the RCRCE bit in the GiERC register is set to "1" (used).

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21.4.1 Clock Synchronous Serial I/O Mode (Groups 0 and 1)

In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. When the internal clock is selected as the transfer clock, the channel 0 and channel 3 waveform generation func- tions generate the internal clock. ISTxDi (i=0, 1), ISCLKi, and ISRxDi share pins with INPCi0 to INPCi2 and OUTCi0 to OUTCi2. Table 21.16 lists specifications of clock synchronous serial I/O mode. Table 21.17 lists registers to be transmit and receive operation. Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Groups 0 and 1) Item Specification Transfer Data Format Transfer data : 8 bits long Transfer Clock(1, 2) When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) : n : setting value of the GiPO0 register, 000016 to FFFF16

The GiPO0 register determines the bit rate and the transfer clock is generated in phase-delayed waveform output mode by the channel 3 waveform generation func- tion. When the CKDIR bit is set to "1" (external clock) : input from the ISCLKi pin Transmit Start Condition Set registers associated with the waveform generation function, the GiMR register and the GiERC register. Then set as written below after at least one transfer clock cycle:
Set the TE bit in the GiCR register to "1" (transmit enable)
Set the TI bit in the GiCR register to "0" (data in the GiTB register) Receive Start Condition Set registers associated with the waveform generation function, the GiMR register and GiERC register. Then set as written below after at least one transfer clock cycle:
Set the RE bit in the GiCR register to "1" (receive enable)
Set the TE bit to "1" (transmit enable)
Set the TI bit to "0" (data in the GiTB register) Interrupt Request • While transmitting, one of the following conditions can be selected to set the SIOiTR bit to "1" (see Figure 10.14): _ The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data is transferred to the transmit register from the GiTB register _ The IRS bit is set to "1" (transmission completed) and data transfer from the transmit register is completed
While receiving, the following condition can be selected to set the SIOiRR bit to "1" (see Figure 10.14): Data is transferred from the receive register to the GiRB register Error Detection Overrun error (3) This error occurs when the 8th bit of the next data is received before reading the GiRB register Selectable Function • LSB first/MSB first Select either bit 0 or bit 7 to transmit/receive data
ISTxDi and ISRxDi I/O polarity inverse ISTxDi pin output level and ISRxDi pin input level are inversed NOTES: 1. The transfer clock must be fBTi divided by six or more. 2. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive shift operation enabled). 3. When an overrun error occurs, the GiRB register is indeterminate. When the OPOL bit in the GiCR register is set to "0" (no ISTxDi output polarity inversed), the ISTxDi pin outputs an "H" signal after selecting operation mode until transfer starts. When the OPOL bit is set to "1", the ISTxDi pin outputs an "L" signal. fBTi 2(n+2)

Page 297 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.17 Registers to be Used and Settings Register Bit Function GiBCR0 BCK1 to BCK0 Set to "11 2" DIV4 to DIV0 Select divide ratio of count source IT Set to "0" GiBCR1 7 to 0 Set to "0001 0010 2" GiPOCR0 7 to 0 Set to "0000 0111 2" GiPOCR1 7 to 0 Set to "0000 0111 2" GiPOCR3 7 to 0 Set to "0000 0010 2" (1) GiPO0 15 to 0 Set the bit rate = transfer clock frequency(1) GiPO3 15 to 0 Set to a value smaller than the GiPO0 register (1) GiFS FSC3,1,0 Set to "0" GiFE IFE3,1,0 Set to "1" GiERC 7 to 0 Set to "0010 0000 2" GiMR GMD1 to GMD0 Set to "01 2" CKDIR Select the internal clock or external clock STPS Set to "0" UFORM Select either LSB first or MSB first IRS Select how the transmit interrupt is generated GiCR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE Set to "1" to enable transmission and reception RE Set to "1" to enable reception IPOL Select ISRxD input polarity (usually set to "0") OPOL Select ISTxD output polarity (usually set to "0") GiTB 7 to 0 Write data to be transmitted GiRB 15 to 0 Received data and error flag are stored i = 0 to 1 NOTES: 1. The CKDIR bit in the GiMR register is set to "0" (internal clock) Table 21.18 Pin Settings (1) Port Function Bit and Setting Register (1) Name PS1 Register PSL1 Register PSC Register PD7 Register IPS Register P73 ISTxD1 output PS1_3 = 1 PSL1_3 = 0 PSC_3 = 1 - - G1POCR0 P74 ISCLK1 input PS1_4 = 0 - - PD7_4 = 0 IPS1 = 0 - ISCLK1 output PS1_4 = 1 PSL1_4 = 0 PSC_4 = 1 - - G1POCR1 P75 ISRxD1 input PS1_5 = 0 - - PD7_5 = 0 IPS1 = 0 - P76 ISTxD0 output PS1_6 = 1 PSL1_6 = 0 PSC_6 = 0 - - G0POCR0 P77 ISCLK0 input PS1_7 = 0 - - PD7_7 = 0 IPS0 = 0 - ISCLK0 output PS1_7 = 1 - - - - G0POCR1 NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used). Table 21.19 Pin Settings (2) Port Function Bit and Setting Register Name PS2 Register PD8 Register IPS register P80 ISRxD0 input PS2_0 = 0 PD8_0 = 0 IPS0 = 0 - fBTi 2x(setting value + 2)

Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M

Table 21. 20 Pin Settings (3)

Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication

Table 21. 21 Pin Settings (4)

Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication

The CKDIR bit in the GiMR register is set to "0" (internal clock)
The UFORM bit in the GiMR register is be set to "0" (LSB first)
The IPOL and OPOL bits in the GiCR register are set to "0" (no inverse) n : Setting value of the GiPO0 register m : Setting value of the GiPO3 register i : 0,1 SIOiTR bit : Bit in the IIOjIR register (j = 1,3) SIOiRR bit : Bit in the IIOkIR register (k = 0,2) IRS bit : Bit in the GiMR register Bit 1 Bit 2 Bit 6Bit 0 Bit 7 Bit 1 Bit 2 Bit 6Bit 0 Bit7 SIOiRR bit Write "0" by program if setting to "0" Write "0" by program if setting to "0" Write "0" by program if setting to "0" Figure 21.39 Transmit and Receive Operation

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21.4.2 Clock Asynchronous Serial I/O Mode (UART) (Groups 0 and 1)

In clock asynchronous serial I/O mode (UART), data is transmitted at a desired bit rate and in a desired transfer data format. Table 21.22 lists specifications of UART mode groups 0 and 1. Table 21.23 lists example of transmit operation. Figure 21.41 shows an example of receive operation. Table 21.22 UART Mode Specifications Item Specification Transfer Data Format • Character Bit (transfer data) : 8 bits long

Start bit : 1 bit long
Stop bit : select length from 1 bit or 2 bits Transfer Clock(1, 2) When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) : n : setting value of the GiPO0 register, 000016 to FFFF16.
The GiPO0 register determines the bit rate. Transmit clock is generated in phase-delayed waveform output mode of the chan- nel 3 waveform generation function. Receive clock is generated with the channel 2 time measurement function. Transmit Start Condition Set the registers associated with the waveform generation function, the GiMR register and GiERC register. Then, set as written below after at least one transfer clock cycle.
Set the TE bit in the GiCR register to "1" (transmit enable)
Set the TI bit in the GiCR register to "0" (data in the GiTB register) Receive Start Condition Set the registers associated with the waveform generation function, the GiMR register and GiERC register. Then, set as written below after at least one transfer clock cycle.
Set the RE bit in the GiCR register to "1" (receive enable)
Detect the start bit Interrupt Request • While transmitting, one of the following conditions can be selected to set the SIOiTR bit to "1" (see Figure 10.14): _ The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data is transferred to the transmit register from the GiTB register. _ The IRS bit is set to "1" (transmission completed) and data transfer from the transmit register is completed
While receiving, the following condition can be selected to set the SIOiRR bit to "1" (see Figure 10.14) : Data is transferred from the receive register to the GiRB register (data reception is completed) Error detection • Overrun error(3) This error occurs when the final stop bit of the next data is received before reading the GiRB register
Framing Error This error occurs when the number of the stop bits set is not detected Selectable function • Stop bit length The length of the stop bit is selected from 1 bit or 2 bits
LSB first/MSB first Select either bit 0 or bit 7 to transmit/receive data NOTES: 1. The transfer clock must be fBTi divided by six or more. 2. Set the GiPOCR2 register and the GiTMCR2 register. 3. When an overrun error occurs, the GiRB register is indeterminate. fBTi 2(n+2)

Page 300 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.23 Registers to be Used and Settings Register Bit Function GiBCR0 BCK1 to BCK0 Set to "11 2" DIV4 to DIV0 Select divide ratio of count source IT Set to "0" GiBCR1 7 to 0 Set to "0001 0010 2" GiPOCR0 7 to 0 Set to "0000 0111 2" GiPOCR2 7 to 0 Set to "0000 0110 2" GiPOCR3 7 to 0 Set to "0000 0010 2" GiTMCR2 7 to 0 Set to "0000 0010 2" GiPO0 15 to 0 Set bit rate = transfer clock frequency GiPO3 15 to 0 Set to a value smaller than the GiPO0 register GiFS FSC3 to FSC0 Set to "0100 2" GiFE IFE3 to IFE0 Set to "1101 2" GiMR GMD1 to GMD0 Set to "00 2" CKDIR Set to "0" STPS Select stop bit length UFORM Select LBS first or MSB first IRS Select how the receive interrupt is generated GiCR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE Set to "1" to enable transmission RE Set to "1" to enable reception IPOL Set to "1" OPOL Set to "1" GiTB 7 to 0 Write data to be transmitted GiRB 15 to 0 Received data and error flag are stored i = 0 to 1 fBTi 2 x (setting value + 2)

Page 301 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.24 Pin Settings in UART Mode (1) Port Function Bit and Setting Register (1) Name PS1 Register PSL1 Register PSC Register PD7 Register IPS Register P73 ISTxD1 output PS1_3 = 1 PSL1_3 = 0 PSC_3 = 1 - - G1POCR0 P75 ISRxD1 input PS1_5 = 0 - - PD7_5 = 0 IPS1 = 0 - P76 ISTxD0 output PS1_6 = 1 PSL1_6 = 0 PSC_6 = 0 - - G0POCR0 NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used). Table 21.25 Pin Settings (2) Port Function Bit and Setting Register Name PS2 Register PSL2 Register PD8 Register IPS Register P80 ISRxD0 input PS2_0 = 0 - PD8_0 = 0 IPS0 = 0 - Table 21.26 Pin Settings (3) Port Function Bit and Setting Register (1) Name PS5 Register PD11 Register IPS Register P110 ISTxD1 output PS5_0 = 1 - - G1POCR0 P112 ISRxD1 input PS5_2 = 0 PD11_2 = 0 IPS1 = 1 - NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used). Table 21.27 Pin Settings (4) Port Function Bit and Setting Register (1) Name PS9 Register PD15 Register IPS Register P150 ISTxD0 output PS9_0 = 1 - - G0POCR0 P152 ISRxD0 input - PD15_2 = 0 IPS0 = 1 - NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used).

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21.4.3 HDLC Data Processing Mode (Group 0 and 1)

In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are available for HDLC control. The channel 0 and 1 are used to generate the transfer clock. No pins are used. To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion result is restored after data conversion. If any data are in the GiTO register after data conversion, the conversion is terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless of there being no data in the transmit output buffer. A CRC value is calculated every time one bit is converted. If no data is in the GiRI register, received data conversion is terminated. Table 21.28 list specifications of the HDLC data processing mode. Table 21.29 lists registers to be used and their settings. Table 21.28 HDLC Processing Mode Specifications Item Specification Input Data Format 8-bit data fixed, bit alignment is optional Output Data Format 8-bit data fixed Transfer Clock When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) : n : setting value of the GiPO0 register 000016 to FFFF16

The GiPO0 register determines bit rate. The transfer clock is generated in phase-delayed waveform output mode of the channel 1 waveform generation function. When the RSHTE bit in the GiERC register is set to "1" (reception shift operation enabled), the transfer clock is generated in the receiver I/O Method • While transmitting, value set in the GiTB register is converted in HDLC data processing mode and transferred to the GiTO register
While receiving, value set in the GiRI register is converted in HDLC data processing mode and transferred to the GiRB register. The value in the GiRI register is also transferred to the GiDR register (received data register). Bit Stuffing While transmitting, "0" following five consecutive "1" is inserted. While receiving, "0" following five consecutive "1" is deleted. Flag Detection Write the flag data "7E 16" to the GiCMP3 register to use the special communication interrupt (the SRTiR bit in the IIO4IR register) Abort Detection Write the masked data "01 16" to the GiMSKk(k=0, 1) register CRC The CRC1 to CRC0 bits are set to "11 2" (X16+X 12+X 5+1) The CRCV bit is set to "1" (set to "FFFF16")
While transmitting, CRC calculation result is stored into the GiTCRC register. The TCRCE bit in the GiETC register is set to "1" (transmit CRC used). The CRC calculation result is reset when the TE bit in the GiCR register is set to "0" (transmit disabled)(1).
While receiving, CRC calculation result is stored into the GiRCRC register. The RCRCE bit in the GiERC register is set to "1" (receive CRC used). The CRC calculation result is reset by comparing the flag data "7E16" and matching the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR regis- ter is set to "1" (CRC reset) (2) fBTi n+2

Page 304 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.28 HDLC Processing Mode Specifications (Continued) Item Specification Data Processing The following conditions are required to start transmit data processing: Start Conditions • The TE bit in the GiCR register is set to "1" (transmit enable)

Data is written to the GiTB register The following conditions are required to start receive data processing:
The RE bit in the GiCR register is set to "1" (receive enable)
Data is written to the GiRI register Interrupt Request(3) During transmit data processing, (1) One of the following conditions can be selected to set the GiTOR bit in the interrupt request register to "1" (interrupt request) (see Figure 10.14) _ When the IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data is transferred from the GiTB register to the transmit register (transmit start) _ When the IRS bit is set to "1" (transmission completed) and data transfer from the transmit register to the GiTO register is completed (2) When data, which is already converted to HDLC data, is transferred from the receive register of the GiTO register to the transmit buffer, the GiTOR bit is set to "1" During received data processing, (1) When data is transferred from the GiRI register to the GiRB register (reception completed), the GiRIR bit is set to "1" (See Figure 10.14) (2) When received data is transferred from the receive buffer of the GiRI register to the receive register, the GiRIR bit is set to "1" (3) When the GiTB register is compared to the GiCMPj register (j=0 to 3), the SRTiR bit is set to "1" NOTES: 1. Set the CRCV bit and ACRC bit in the GiEMR register to "1". 2. The CRC calculation circuit is reset after the GiRCRC register stores CRC data. 3. See Figure 10.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.

Page 305 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.29 Registers to be Used and Settings Register Bit Function GiBCR0 BCK1 to BCK0 Select count source DIV4 to DIV0 Select divide ratio of count source IT Select the base timer interrupt GiBCR1 7 to 0 Set to "0001 0010 2" GiPOCR0 7 to 0 Set to "0000 0000 2" GiPOCR1 7 to 0 Set to "0000 0000 2" GiPO0 15 to 0 Set bit rate GiPO1 15 to 0 Set the timing of the rising edge of the transfer clock. Timing of the falling edge (high-level signal ("H") width of the transfer clock) is fixed. Setting value of GiPO1 ≤ Setting value of GiPO0 . GiFS FSC1 to FSC0 Set to "00 2" GiFE IFE1 to IFE0 Set to "11 2" GiMR GMD1 to GMD0 Set to "11 2" CKDIR Set to "0" UFORM Set to "0" IRS Select how the transmit interrupt is generated GiEMR 7 to 0 Set to "1111 0110 2" GiCR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE Transmit enable bit RE Receive enable bit GiETC SOF Set to "0" TCRCE Select whether the transmit CRC is used or not ABTE Set to "0" TBSF0, TBSF1 Transmit bit stuffing GiERC CMP2E to CMP0E S elect whether received data is compared or not CMP3E Set to "1" RCRCE Select whether receive CRC is used or not RSHTE Set to "1" to use it in the receiver RBSF0, RBSF1 Receive bit stuffing GiIRF BSERR, ABT Set to "0" IRF3 to IRF0 Select how an interrupt is generated GiCMP0, 7 to 0 Write "FE 16" to abort processing GiCMP1 GiCMP2 7 to 0 Data to be compared GiCMP3 7 to 0 Write "7E 16" GiMSK0, 7 to 0 Write "01 16" to abort processing GiMSK1 GiTCRC 15 to 0 Transmit CRC calculation result can be read GiRCRC 15 to 0 Receive CRC calculation result can be read GiTO 7 to 0 Data, which is output from a transmit data generation circuit, can be read GiRI 7 to 0 Set data input to a receive data generation circuit GiRB 7 to 0 Received data is stored GiTB 7 to 0 For transmission : write data to be transmitted For reception : received data for comparison is stored i = 0,1

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21.5 Group 2 Communication Function

The communication function is available when two 8-bit shift registers are used with the waveform genera- tion function. In the intelligent I/O group 2, the variable clock synchronous serial I/O or IEBus (1) communication function is available. Figures 21.42 to 21.45 show registers associated with the communication function. NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. Function Group 2 SI/O Transmit Buffer Register Bit NameBit Symbol Symbol Address After Reset G2TB 016D 16-016C16 Indeterminate RW RO RW RW RW RW RW RW SZ0 (b7 - b0) (b12 - b11) SZ2 SZ1 b7 b0b15 b8 Transfer Bit Length Select Bit Transmit Buffer Data to be transmitted : 8 bits long : 1 bits long : 2 bits long : 3 bits long : 4 bits long : 5 bits long : 6 bits long : 7 bits long b10 A PC P ACK Function Select Bit Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Parity Calculation Continuing Bit(1) Parity Function Select Bit 0 : Adds no ACK bit 1 : Adds the ACK bit after last transmit bit 0 : Adds the parity bit after a data to be transmitted 1 : Carries over a parity to a data to be transmitted 0 : No parity 1 : Parity (even parity only) NOTES: 1. Set the P bit to "0" before setting the PC bit to "1" Function Group 2 SI/O Receive Buffer Register Bit NameBit Symbol Symbol Address After Reset G2RB 016F 16 - 016E16 Indeterminate RW RO RO Received data OER (b7 - b0) (b11 - b8) (b15 - b13) 0 : No overrun error 1 : Overrun error found Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Receive Buffer Overrun Error Flag(1) NOTES: 1. The OER bit is set to "0" when the GMD1 to GMD0 bits in the G2MR register are set to "002" (communication unit reset) or the RE bit in the G2CR register is set to "0" (receive disable). b7 b0b15 b8 Figure 21.42 G2TB and G2RB Register

Page 307 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.43 G2MR and G2CR Register GMD0 GMD1 CKDIR (b5 - b3) Communication Mode Select Bit UFORM IRS Internal/External Clock Select Bit Transfer Format Select Bit Transmit Interrupt Cause Select Bit 0 : Internal clock 1 : External clock 0 : LSB first 1 : MSB first 0 : No data is in the transmit buffer 1 : Transmission is completed b7 b6 b5 b4 b3 b2 b1 b0 : Communication unit is reset (The OER bit is set to "0")(1) : Clock synchronous serial I/O mode (2) : IE mode(2) : Do not set to this value Group 2 SI/O Communication Mode Register Symbol Address After Reset G2MR 016A 16 00XX X000 2 RW RW RW RW RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. Run the base timer clock for one or more cycles after the GMD1 to GMD0 bits are set to "002" (communication unit reset). 2. Set the GMD1 to GMD0 bits to "012" (clock synchronous serial I/O mode) or "102" (IE mode) while the base timer clock is stopped. Group 2 SI/O Communication Control Register Symbol Address After Reset G2CR 016B 16 0000 X000 2 RW RW RW RO RO RO RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 TE TXEPT RI Transmit Enable Bit TI (b3) RE IPOL OPOL Receive Complete Flag Transmit Buffer Empty Flag Receive Enable Bit1 0 : No data is in the G2RB register 1 : Data is in the G2RB register 0 : Data is in the G2TB register 1 : No data is in the G2TB register Transmit Register Empty Flag 0 : Data is in the transmit register (during transmission) 1 : No data is in the transmit register (transmission is completed) 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled ISRxD Input Polarity Switch Bit (1) ISTxD Output Polarity Switch Bit 0 : No inverse 1 : Inverse 0 : No inverse 1 : Inverse NOTES: 1. The group 2 base timer may be reset when rewriting the RE or IPOL bit. To avoid resetting, set the RST2 bit in the G2BCR1 register to "0" (no base timer reset by a reset request from the communication function).

Page 308 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.44 IECR and IEAR Registers Group 2 IEBus Control Register Symbol Address After Reset IECR 0172 16 00XX X000 2 RW RW RW RO RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 0 : Idle state 1 : Busy state (start condition is detected) IEB IETS IEBBS (b5 - b3) IEBus Enable Bit(1) DF IEBus Transmit Start Request Bit Digital Filter Select Bit 0 : Transmission is completed 1 : Transmission is started 0 : Disables IEBus(2) 1 : Enables IEBus 0 : No digital filter 1 : Digital filter IEM IEBus Busy Flag IEBus Mode Select Bit 0 : Mode 1 1 : Mode 2 NOTES: 1. Set the IEB bit while the base timer clock is stopped. 2. After the IEB bit is set to "0", keep "0" for at least 1 f BT2 cycle. Set the BCK1 to BCK0 bits in the G2BCR0 register to "002" (clock stop) when setting the IEB bit to "1". Group 2 IEBus Address Register Symbol Address After Reset IEAR 0171 16 - 017016 Indeterminate RW RW RW Function b7 b0 Address data Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Address data b15 b8

Page 309 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 0, 1 Communication Function))T38/C23M,38/C23M(puorG38/C23M Group 2 IEBus Transmit Interrupt Cause Determination Register Symbol Address After Reset IETIF 0173 16 XXX0 0000 2 RW RW RW RW RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its contents is indeterminate. NOTES: 1. This bit can be set to "0" by program, but cannot be set to "1". Set to "0" by setting the IEB bit in the IECR register to "0" (IEBus disabled to use). 0 : No error found 1 : Error found 0 : Transmission is completed in error 1 : Transmission is completed as expected 0 : No error found 1 : Error found 0 : No error found 1 : Error found 0 : No error found 1 : Error found IETNF IEACK IETMB Normal Complete Flag(1) IETT IEABL (b7 - b5) ACK Error Flag(1) Arbitration Lost Flag(1) Maximum Transfer Byte Error Flag(1) Timing Error Flag(1) b7 b6 b5 b4 b3 b2 b1 b0 Group 2 IEBus Receive Interrupt Cause Determination Register Symbol Address After Reset IERIF 0174 16 XXX0 0000 2 RW RW RW RW RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its contents is indeterminate. NOTES: 1. This bit can be set to "0" by program, but not to "1". Set to "0" by setting the IEB bit in the IECR register to "0" (IEBus disabled to use). IERNF IEPAR IERMB IERT IERETC (b7 - b5) Parity Error Flag(1) Other Cause Receive Completed Flag(1) Max. Transfer Byte Error Flag (1) Timing Error Flag(1) Normal Completed Flag (1) b7 b6 b5 b4 b3 b2 b1 b0 0 : No error found 1 : Error found 0 : Transmission is completed in error 1 : Transmission is completed as expected 0 : No error found 1 : Error found 0 : No error found 1 : Error found 0 : No error found 1 : Error found Figure 21.45 IETIF and IERIF Registers

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21.5.1 Variable Clock Synchronous Serial I/O Mode (Group 2)

In variable clock synchronous serial I/O mode, data is transmitted and received using the transfer clock. The length of data transferred is selected from 1 to 8 bits. Table 21.30 lists specifications of the group 2 variable clock synchronous serial I/O mode. Table 21.31 lists registers to be used and their settings. Tables 21.32 to 21.35 lists pin settings. Figure 21.46 shows an example of a transmit and receive operation. Table 21.30 Variable Clock Synchronous Serial I/O Mode Specifications (Group 2) Item Specification Transfer Data Format • Transfer data length : 1 to 8 bits Transfer Clock(1) • When the CKDIR bit in the G2MR register is set to "0" (internal clock) : n : setting value of the G2PO0 register 000016 to FFFF16 The G2PO0 register determines bit rate and the transfer clock is generated in phase-delayed waveform output mode of the channel 2 waveform generation func- tion.

When the CKDIR bit is set to "1" (external clock) : input from the ISCLK2 pin(2) Transmit Start Condition • To start transmitting, the following conditions are required : - Set the TE bit in the G2CR register to "1" (transmit enable) - Write data to the G2TB register Receive Start Condition • To start receiving, the following conditions are required : - Set the RE bit in the G2CR register to "1" (receive enable) - Set the TE bit in the G2CR register to "1" (transmit enable) - Write data to the G2TB register Interrupt Request • While transmitting, one of the following conditions can be selected to set the SIO2TR bit in the IIO6IR register to "1" (see Figure 10.14): - The IRS bit in the G2MR register is set to "0" (no data in the G2TB register): when data is transferred from the G2TB register to the transmit register. - The IRS bit is set to "1" (reception completed): when data transfer from the transmit register is completed
While receiving, the following condition can be selected to set the SIO2RR bit in the IIO5IR register to "1" (interrupt request) (see Figure 10.14): when data is transferred from the receive register to the G2RB register (data recep- tion is completed) Error Detection Overrun error (3) This error occurs when receiving the j bit (j=1 to 8) of the next data (transfer data length: j bits) before reading the G2RB register Selectable Function • LSB first/MSB first Select either bit 0 or bit 7 to transmit/receive data
ISTxD2 and ISRxD2 I/O polarity inverse ISTxD2 pin output level and ISRxD2 pin input level are inversed
Data transfer bit length Select from 1 to 8 bits NOTES: 1. The transfer clock must be fBT2 divided by six or more when both transfer clock and transfer data are transmitted. Under conditions other than this, the transfer clock must be fBT2 divided by 20 or more. 2. Transfer clocks must be fBT2 divided by 20 or more. 3. When an overrun error occurs, the G2RB register is indeterminate. fBT2 2(n+2)

Page 311 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 2 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.31 Register to be Used and Settings Register Bit Function G2BCR0 BCK1 to BCK0 Set to "11 2" DIV4 to DIV0 Select divide ratio of count source IT Set to "0" G2BCR1 7 to 0 Set to "0001 0010 2" G2POCR0 7 to 0 Set to "0000 0111 2" G2POCR1 7 to 0 Set to "0000 0111 2" G2BCR2 7 to 0 Set to "0000 0010 2" G2PO0 15 to 0 Set bit rate = transfer clock frequency G2PO2 15 to 0 Set to a value smaller than the G2PO0 register G2FE IFE2 to IFE0 Set to "111 2" G2MR GMD1 to GMD0 Set to "01 2" CKDIR Select internal or external clock UFORM Select either LSB first or MSB first IRS Select how the transmit interrupt is generated G2CR TE When transmission is enabled, set to "1" TXEPT Transmit register empty flag TI Transmit buffer empty flag RE When reception is enabled, set to "1" RI Receive complete flag OPOL ISTxD2 output polarity inverse (usually set to "0") IPOL ISRxD2 input polarity inverse (usually set to "0") G2TB 15 to 0 Write transfer bit length and transmit data G2RB 15 to 0 Received data and error flag are stored fBT2 2 x (setting value + 2)

Page 312 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 2 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.32 Pin Settings (1) Port Function Bit and Setting Register (2) Name PS1 RegisterPSL1 Register PSC Register PD7 Register IPS Register P70(1) ISTxD2 output PS1_0 = 1 PSL1_0 = 0 PSC_0 = 1 - - G2POCR0 P71 ISRxD2 input PS1_1 = 0 - - PD7_1 = 0 IPS5 to 4 = 00 2 - NOTES: 1. P70 is a port for the N-channel open drain output. 2. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function is used). Table 21.33 Pin Settings (2) Port Function Bit and Setting Register (2) Name PS3 Register(1) PSL3 RegisterPD9 Register(1) IPS Register P9 1 ISRxD2 input PS3_1=0 - PD9_1=0 IPS5 to 4=01 2 - P9 2 ISTxD2 output PS3_2=1 PSL3_2=1 - - G2POCR0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. 2. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used). Table 21.34 Pin Settings (3) Port Function Bit and Setting Register (1) Name PS0 Register PSL0 Register PD6 Register IPS Register P64 ISCLK2 input PS0_4 = 0 - PD6_4 = 0 IPS6 = 0 - ISCLK2 output PS0_4 = 1 PSL0_4 = 1 - - G2POCR1 NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used). Table 21.35 Pin Settings (4) Port Function Bit and Setting Register (1) Name PS7 Register PD13 Register IPS Register P13 4 ISTxD2 output PS7_4 = 1 - - G2POCR0 P135 ISRxD2 input PS7_5 = 0 PD13_5 = 0 IPS5 to 4 = 102 - P136 ISCLK2 input PS7_6 = 0 PD13_6 = 0 IPS6 = 1 - ISCLK2 output PS7_6 = 1 - - G2POCR1 NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used).

Page 313 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 2 Communication Function))T38/C23M,38/C23M(puorG38/C23M k + 2 t Base timer 2 Second write to transmit buffer Received data bit 0 bit 1 bit 2 bit 7bit 6 bit 8 bit 9 bit 10 bit 11 bit 0 bit 1 bit 2 bit 7bit 6 bit 8 bit 9 bit 10 bit 11bit 5 Set data in the transmit register (4-bit data) Transfer to the receive registerTransfer to the receive register First write to transmit buffer The base timer is reset by the channel 0 waveform generation function Transmit/Receive clock by the channel 2 waveform generation Set data in the transmit register (8-bit data) t : Value set in the channel 2 waveform generation register Value set in the channel 3 waveform generation registerFigure 21.46 Transmit and Receive Operation

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21.5.2 IEBus Mode (Group 2)

Table 21.36 lists specifications of IEBus mode. Table 21.37 lists registers to be used and settings. Tables 21.38 to 21.40 lists pin settings. Table 21.36 IEBus Mode Specifications Item Specification Transfer Data Format • Transfer data length: 1 to 8 bits Transfer Clock • When the CKDIR bit in the G2MR register is set to "0" (internal clock) : n : setting value of the G2PO0 register, 000016 to FFFF16. The G2PO0 register determines bit rate and the transfer clock is generated in phase-delayed waveform output mode of the channel 2 waveform generation function. The G2PO2 register = (n+2)/2(1)

When the CKDIR bit is set to "1" (external clock) : input from the ISCLK2 pin(2) Transmit Start Condition To start transmitting, the following conditions are required :
Set the TE bit in the G2CR register to "1" (transmit enable)
Write data to G2TB register Receive Start Condition To start receiving, the following requirements must be met:
Set the RE bit in the G2CR register to "1" (receive enable)
Set the TE bit in the G2CR register to "1" (transmit enable)
Write data to the G2TB register Interrupt Request • While transmitting, the following conditions can be selected to set the SIO2TR bit in the IIO6IR register to "1" (see Figure 10.14): - The IRS bit in the G2MR register is set to "0" (no data in the G2TB register): when data is transferred to the transmit register from the G2TB register (transmis- sion started) - The IRS bit is set to "1" (transmission completed): when data transfer from the transmit register to the G2TO register is completed
While receiving, the following condition can be selected to set the SIO2RR bit in the IIO5IR register to "1" (see Figure 10.14): when data is transferred from receive register to the G2RB register (data reception is completed) Error Detection Overrun error (3) This error occurs when receiving the j bit (j=1 to 8) of the next data (transfer data length: j bits) before reading the G2RB register Selectable Function • LSB first/MSB first select Select either bit 0 or bit 7 to transmit/receive data
ISTxD2 and ISRxD2 I/O polarity inverse ISTxD2 pin output and ISRxD2 pin input levels are inversed
Data transfer bit length Select from 1 to 8 bits NOTES: 1. The transfer clock must be fBT2 divided by six or more when both transfer clock and transfer data are transmitted. Under conditions other than this, the transfer clock must be fBT2 divided by 20 or more. 2. Transfer clock must be input fBT2 divided by 20 or more. 3. When an overrun error occurs, the G2RB register is indeterminate. fBT2 2(n+2)

Page 315 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 2 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.37 Registers to be Used and Settings Register Bit Function G2BCR0 BCK1 to BCK0 Set to "11 2" DIV4 to DIV0 Select divide ratio of count source IT Set to "0" G2BCR1 7 to 0 Set to "00010010 2" G2POCR0 MOD2 to MOD0 Set to "111 2" to G2POCR7 PRT Set to "0" IVL Set to "0" RLD Set to "0" RTP Set to "0" INV Set to "0" G2PO0 to 15 to 0 Set compared data for waveform generation G2PO7 G2FE 7 to 0 Set bit of corresponding channel to "1" G2MR GMD1 to GMD0 Select serial I/O mode CKDIR Select internal clock or external clock UFORM Select either LSB first or MSB first IRS Select how the transmit interrupt is generated G2CR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE When transmission is enabled, set to "1" RE When reception is enabled, set to "1" IPOL ISRxD2 input polarity inverse (usually set to "0") OPOL ISTxD2 output polarity inverse (usually set to "0") IECR IEB Set to "1" IETS When transmission starts, set to "1" IEBBS Select IEBus busy flag DF Select whether the digital filter is available or not IEM Select mode IEAR 11 to 0 Set address data IETIF IETNF Normal complete flag when transmitting IEACK ACK error flag when transmitting IETMB Maximum transfer byte error flag when transmitting IETT Timing error flag when transmitting IEABL Arbitration lost flag when transmitting IERIF IERNF Normal complete flag when receiving IEPAR Parity error flag when receiving IERMB Maximum transfer byte error flag when receiving IERT Timing error flag when receiving IERETC Other cause receive completed flag when receiving G2RB 7 to 0 Received data and error flag are stored OER Overrun error flag G2TB 7 to 0 Write transfer bit length and data to be transmitted

Page 316 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 2 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.38 Pin Settings (1) Port Function Bit and Setting Register (2) Name PS1 Register PSL1 Register PSC Register PD7 Register IPS Register P70(1) IEOUT output PS1_0 = 1 PSL1_0 = 0 PSC_0 = 1 - - G2POCR0 P71 IEIN input PS1_1 = 0 - - PD7_1 = 0 IPS5 to 4 = 002 - NOTES: 1. P70 is a port for the N-channel open drain output. 2. Set the MOD2 to MOD0 bits in the G2POCR0 register to "1112". Table 21.39 Pin Settings (2) Port Function Bit and Setting Register (1) Name PS3 Register(2) PSL3 Register PD9 Register(2) IPS Register P91 IEIN input PS3_1 = 0 - - IPS5 to 4 = 012 - P92 IEOUT output PS3_2 = 1 PSL3_2 = 1 PD9_2 = 0 - G2POCR0 NOTES: 1. Set the MOD2 to MOD0 bits in the G2POCR0 register to "1112". 2. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Table 21.40 Pin Settings (3) Port Function Bit and Setting Register (1) Name PS7 Register PSL7 Register IPS Register P134 IEOUT output PS7_4 = 1 - - G2POCR0 P135 IEIN input PS7_5 = 0 PD13_5 = 0 IPS5 to 4 = 102 - NOTES: 1. Set the MOD2 to MOD0 bits in the G2POCR0 register to "1112".

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21.6 Group 3 Communication Function

The communication function is available when two 16-bit shift registers are used with the waveform gen- eration function. In the intelligent I/O group 3, 8-bit or 16-bit synchronous communication function is available. Figures 21.47 to 21.49 show registers associated with the communication function. Figure 21.47 G3TB Register and G3RB Register Function Group 3 SI/O Transmit Buffer Register Bit Name Symbol Address After Reset G3TB 017D 16 - 017C16 Indeterminate RW WO WO Transmit Buffer Data to be transmitted (8 low-order bits) Data to be transmitted (8 high-order bits) b15 b8 b7 b0 Function Group 3 SI/O Receive Buffer Register Bit Name Symbol Address After Reset G3RB 017F 16 - 017E16 Indeterminate RW RO RO Receive Buffer Received data (8 low-order bits) Received data (8 high-order bits) b15 b8 b7 b0

Page 318 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 3 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.48 G3MR Register and G3CR Register Group 3 SI/O Communication Mode Register Symbol Address After Reset G3MR 017A 16 00XX 0000 2 RW RW RW RW RW RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b2 b1b3 b0 0 : Internal clock 1 : External clock GMD0 GMD1 CKDIR Communication Mode Select Bit UFORM IRS (b5 - b4) Internal/External Clock Select Bit Transfer Format Select Bit Transmit Interrupt Cause Select Bit 0 : LSB first 1 : MSB first 0 : No data is in the transmit buffer 1 : Transmission is completed : Communication unit is reset (The ROER bit is set to "0") : Clock synchronous serial I/O mode : Do not set to this value : Do not set to this value TLD Transfer Data Length Select Bit 0 : 16 bits long 1 : 8 bits long Group 3 SI/O Communication Control Register Symbol Address After Reset G3CR 017B 16 0000 X000 2 RW RW RW RO RO RO RW RW Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 TE TXEPT RI Transmit Enable Bit TI (b3) RE IPOL OPOL Receive Complete Flag Transmit Buffer Empty Flag Receive Enable Bit 0 : No data is in the G3RB register 1 : Data is in the G3RB register 0 : Data is in the G3TB register 1 : No data is in the G3TB register Transmit Register Empty Flag 0 : Data is in transmit register (during transmission) 1 : No data is in the transmit register (transmission is completed) 0 : Transmit disable 1 : Transmit enable 0 : Receive disabled 1 : Receive enabled ISRxD Input Polarity Switch Bit ISTxD Output Polarity Switch Bit 0 : No inverse 1 : Inverse 0 : No inverse 1 : Inverse

Page 319 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 3 Communication Function))T38/C23M,38/C23M(puorG38/C23M Figure 21.49 G3FLG Register Group 3 SI/O Communication Flag Register Symbol Address After Reset G3FLG 01AD 16 XXXX XXX0 2 RW RO Bit Name FunctionBit Symbol NOTES: 1. The ROER bit is set to "0" when the RE bit in the G3CR register is set to "0". b7 b6 b5 b4 b3 b2 b1 b0 ROER (b7 - b1) Receive Overrun Error Flag(1) 0 : No error found 1 : Error found Nothing is assigned. When write, set to "0". When read, its content is indeterminate.

Page 320 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 3 Communication Function))T38/C23M,38/C23M(puorG38/C23M 21.6.1 8-bit or 16-bit Clock Synchronous Serial I/O Mode (Group 3) In 8-bit or 16-bit clock synchronous serial I/O mode, data is transmitted and received using the transfer clock. When the internal clock is selected as the transfer clock, the channel 0 and channel 2 waveform generation functions generate the transfer clock. ISTxD3, ISCLK3 and ISRxD3 share pins with OUTC30 to OUTC32 and are available in the 144-pin package only. Table 21.41 lists specifications of clock synchronous serial I/O mode. Table 21.42 lists registers to be example of transmit and receive operation. Table 21.41 Clock Synchronous Serial I/O Mode (Group 3) Item Specification Transfer Data Format • Transfer data : 8 bits or 16 bits long Transfer Clock(1) • When the CKDIR bit in the G3MR register is set to "0" (internal clock) : n : setting value of the G3PO0 register, 000116 to FFFD16 _ The G3PO0 register determines the bit rate and the transfer clock is generated in phase- delayed waveform output mode of the channel 2 waveform generation function.

When the CKDIR bit is set to "1" (external clock) : input from the ISCLK3 pin Transmit Start Condition(2) Set registers associated with the waveform generation function and the G3MR register. Then, set as written below after waiting at least one transfer clock cycle.
Set the TE bit in the G3CR register to "1" (transmit enable)
Set the TI bit in the G3CR register to "0" (data in the G3TB register) Receive Start Condition Set registers associated with the waveform generation function and the G3MR register. Then, set as written below after waiting at least one transfer clock cycle.
Set the RE bit in the G3CR register to "1" (receive enable)
Set theTE bit to "1" (transmit enable)
Set the TI bit to "0" (data in the G3TB register) Interrupt Request • While transmitting, one of the following conditions can be selected to set the SIO3TR bit in the IIO10IR register to "1" (see Figure 10.14) : _ When the IRS bit in the G3MR register is set to "0" (no data in the transmit buffer), one transfer clock cycle after data transmission starts _ When the IRS bit is set to "1" (reception completed), 15 transfer clock cycles after data transmission starts in 16-bit clock synchronous serial I/O mode (set the DLS bit in the G3MR register to "0"), or 7 transfer clock cycles after data transmission starts in 8-bit clock clock synchronous serial I/O mode (set the DLS bit to "1").
While receiving, the following condition can be selected to set the SIO3RR bit in the IIO9IR register to "1" (see Figure 10.14) : 15.5 transfer clock cycles after data transmission starts in 16-bit clock synchronous serial I/O mode, or 7.5 transfer clock cycles after data transmission starts in 8-bit clock synchronous serial I/O mode Error Detection • Overrun error(3) This error occurs in 16-bit clock synchronous serial I/O mode when the 15th bit of the next data is received before reading the G3RB register. This error occurs in 8-bit clock synchronous serial I/O mode when the 7th bit of the next data is received before reading the G3RB register. Selectable Function • LSB first/MSB first Select either bit 0 or bit 7 to transmit/receive data
ISTxD3 and ISRxD3 I/O polarity inverse ISTxD3 pin output level and ISRxD3 pin input level are inversed NOTES: 1. The transfer clock must be fBT3 divided by six or more. 2. Transmit interrupt request is generated when the TE bit is set to "1". Set the interrupt-associated registers after setting the TE bit. 3. When an overrun error occurs, the G3RB register is indeterminate. fBT3 2(n+2)

Page 321 884fo6002,13.naJ13.1.veR 1310-4300B90JER 21. Intelligent I/O (Group 3 Communication Function))T38/C23M,38/C23M(puorG38/C23M Table 21.42 Registers to be Used and Settings Register Bit Function G3BCR0 BCK1 to BCK0 Set to "11 2" DIV4 to DIV0 Select divide ratio of count source IT Set to "0" G3BCR1 7 to 0 Set to "0001 0010 2" G3POCR0 7 to 0 Set to "0000 0111 2" G3POCR1 7 to 0 Set to "0000 0111 2" G3POCR2 7 to 0 Set to "0000 0010 2" G3PO0 15 to 0 Set bit rate = transfer clock frequency G3PO2 15 to 0 Set to a value smaller than the G3PO0 register G3FE 7 to 0 Set to "0000 0111 2" G3MR GMD1 to GMD0 Set to "01 2" CKDIR Select the internal clock or external clock TLD Select transfer data length UFORM Select either LSB first or MSB first IRS Select how the transmit interrupt is generated G3CR TE Set to "1" to enable transmission TXEPT Transmit register empty flag TI Transmit buffer empty flag RE Set to "1" to enable reception RI Receive complete flag OPOL ISTxD3 output polarity inverse (usually set to "0") IPOL ISRxD3 input polarity inverse G3TB 15 to 0 Write transmit data G3RB 15 to 0 Received data is stored Table 21.43 Pin Setting in Clock Synchronous Serial I/O Mode (Group 3) Port Function Bit and Setting Register (1) Name PS2 Register PSL2 Register PD8 Register IPS Register P81 ISTxD3 output PS2_1 = 1 PSL2_1 = 1 - - G3POCR0 P82 ISRxD3 input PS2_2 = 0 - PD8_2 = 0 IPS7 = 0 - NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used). Table 21.44 Pin Setting (Continued) Port Function Bit and Setting Register (1) Name PS6 Register PD12 Register IPS Register P120 ISTxD3 output PS6_0 =1 - - G3POCR0 P121 ISCLK3 input PS6_1 = 0 PD12_1 = 0 - - ISCLK3 output PS6_1 = 1 - - G3POCR1 P122 ISRxD3 input PS6_2 = 0 PD12_2 = 0 IPS7 = 1 - NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication function used). fBT3 2 x (setting value + 2)

Intelligent I/O (Group 3 Communication Function))T38/C23M,38/C23M(puorG38/C23M

Figure 21. 50 Transmit and Receive Operation (8-bit Length) The above timing applies under the following settings.

The CKDIR bit in the G3MR register is set to "0" (internal clock)
The UFORM bit in the G3MR register is set to "0" (LSB first)
The IPOL bit and OPOL bit in the G3CR register are set to "0" (no inverse)
The TLD bit in the G3CR register is set to "1" (8 bits long) n : Setting value of the G3PO0 register m : Setting value of the G3PO2 register SIO3TR bit : Bit in the IIO10IR register SIO3RR bit : Bit in the IIO9IR register IRS bit : Bit in the G3MR register Bit 1 Bit 2 Bit 6Bit 0 Bit 7 Bit 1 Bit 2 Bit 6Bit 0 Bit 7 Write "0" by program if setting to "0" SIO3RR bit Write "0" by program if setting to "0" Write "0" by program if setting to "0"

Intelligent I/O (Group 3 Communication Function))T38/C23M,38/C23M(puorG38/C23M

Figure 21. 51 Transmit and Receive Operation (16-bit Length) The above timing applies under the following settings.

The CKDIR bit in the G3MR register is set to "0" (internal clock)
The UFORM bit in the G3MR register is set to "0" (LSB first)
The IPOL bit and OPOL bit in the G3CR register are set to "0" (no inverse)
The TLD bit in the G3CR register is set to "1" (16 bits long) n : Setting value of the G3PO0 register m : Setting value of the G3PO2 register SIO3TR bit : Bit in the IIO10IR register SIO3RR bit : Bit in the IIO9IR register IRS bit : Bit in the G3MR register Bit 1 Bit 2 Bit 14Bit 0 Bit 15 Bit 1 Bit 2 Bit 14Bit 0 Bit 15 SIO3RR bit Write "0" by program if setting to "0" Write "0" by program if setting to "0" Write "0" by program if setting to "0"

Page 324 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M 22. CAN Module The CAN (Controller Area Network) module incorporated in the M32C/83 group is a Full CAN module, compatible with CAN Specification 2.0 Part B. Table 22.1 lists specifications of the CAN module. Table 22.1 CAN Module Specifications Item Specification Protocol CAN Specification 2.0 Part B Message Slots 16 slots Polarity Dominant: "L" Recessive: "H" Acceptance Filter Global mask: 1 mask (for message slots 0 to 13) Local mask: 2 masks (for message slots 14 and 15 respectively) Baud Rate Baud rate = --- Max. 1 Mbps Tq clock cycle = Tq per bit = SS + PTS +PBS1+PBS2 Tq: Time quantum BRP: Setting value in the C0BRP and C1BRP registers, 1-255 SS: Synchronization Segment; 1 Tq PTS: Propagation Time Segment; 1 to 8 Tq PBS1: Phase Buffer Segment 1; 2 to 8 Tq PBS2: Phase Buffer Segment 2 ; 2 to 8 Tq Remote Frame Automatic Message slot that receives the remote frame transmits the data frame Answering Function automatically Time Stamp Function Time stamp function with a 16-bit counter. Count source can be selected from the CAN bus bit clock divided by 1, 2, 3 or 4. BasicCAN Mode BasicCAN function can be used with the CANi message slots 14 and 15. Transmit Abort Function Transmit request is aborted Loopback Function Frame transmitted by the CAN module is received by the same CAN module Forcible Error Active The CAN module is forced into an error active state Clear Function NOTES: 1. Use an oscillator with maximum 1.58% oscillation tolerance. Figure 22.1 shows a block diagram of the CAN module. Figure 22.2 shows CANi message slot buffer (the message slot buffer) (i=0,1) and CANi message slot (the message slot) j (j=0 to 15). Table 22.2 lists pin settings of the CAN module. The message slot cannot be accessed directly from the CPU. Allocate the message slot j to be used to the message slot buffer 0 or 1. The message slot j is accessed via the message slot buffer address. The CiSBS register selects the message slot j to be allocated. Figure 22.2 shows the 16-byte message slot buffer and message slot. Tq clock cycle x Tq per bit BRP + 1

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22.1 CAN-Associated Registers

Figures 22.3 to 22.26 show registers associated with CAN. To access the associated registers, set the MCD4 to MCD0 bits in the MCD register to "100102" (no division of CPU clock), the PM13 bit in the PM1 register to "1" (2 wait states), and the CM07 bit in the CM0 register to "0" (XIN-XOUT selected).

22.1.1 CAN0 Control Register 0 (C0CTLR0 Register)

Symbol Address After Reset (1) C0CTLR0 0201 16 - 020016 XXXX 0000 XX01 0X012 RW RESET1 TSPRE0 TSRESET CAN Reset Bit 1 Time Stamp Counter Reset Bit 0: CAN module reset exited 1: CAN module is reset(2) RESET0 (b2) (b5) (b7 - b6) (b15 - b12) LOOPBACK BASICCAN CAN Reset Bit 0 Loop Back Mode Select Bit Basic CAN Mode Select Bit 0 0: Selects the CAN bus bit clock 0 1: Selects the CAN bus bit clock divided by 2 1 0: Selects the CAN bus bit clock divided by 3 1 1: Selects the CAN bus bit clock divided by 4 b9 b8 0 : Disables BasicCAN mode function 1 : Enables BasicCAN mode function 0: Disables Loop back function 1: Enables Loop back function 0: CAN module reset exited 1: CAN module is reset(2) TSPRE1 When this bit is set to "1", the C0TSR register is set to "0000 16". After that, this bit is automatically set to "0".(3) ECRESET Error Counter Reset Bit When this bit is set to "1", the C0TEC and C0REC registers are set to "00 16". After that, this bit is automatically set to "0".(3) Time Stamp Prescaler Select Bit Reserved Bit Set to "0". Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 2. Set the RESET0 bit and RESET1 bit to the same value simultaneously. 3. This bit can be set to "1" by program, but cannot be set to "0". b7 b0b15 b8 Figure 22.3 C0CTLR0 Register

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22.1.1.1 RESET0 Bit and RESET1 Bit

When both RESET0 and RESET1 bits are set to "1", the CAN module is immediately reset regard- less of ongoing CAN communication. After the RESET0 and RESET1 bits are set to "1" and the CAN module reset is completed, the C0TSR register is set to "0000 16". The C0TEC and C0REC registers are set to "0016" and the STATE_ERRPAS and STATE_BUSOFF bits in the C0STR register are set to "0" as well. When both RESET0 and RESET1 bits are changed "1" to "0", the C0TSR register starts counting. CAN communication is available after 11 continuous recessive bits are detected. NOTES: 1. Set the same value in both RESET0 and RESET1 bits simultaneously. 2. Set CAN configuration upon confirming that the STATE_RESET bit in the C0STR register is set to "1" (CAN module reset completed) after setting the RESET0 and RESET1 bits to "1". 3. The CAN OUT pin outputs an "H" signal as soon as the RESET0 and RESET1 bits are set to "1". CAN bus error may occur when the RESET0 and RESET1 bits are set to "1" while the CAN frame is transmitting. 4. For CAN communication, set the PS1, PS2, PSL1, PSL2, PSC, and IPS registers when the STATE_RESET bit is set to "1" (CAN module reset completed).

22.1.1.2 LOOPBACK Bit

When the LOOPBACK bit is set to "1" (loopback function enabled) and the receive message slot has a matched ID and frame format with a transmitted frame, the transmitted frame is stored to the receive message slot. NOTES: 1. No ACK for the transmitted frame is returned. 2. Change the LOOPBACK bit only when the STATE_RESET bit is set to "1" (CAN module reset completed).

22.1.1.3 BASICCAN Bit

When the BASICCAN bit is set to "1", the message slots 14 and 15 enter BasicCAN mode. In BasicCAN mode, the message slots 14 and 15 are used as dual-structured buffers. The message slot 14 and 15 alternately store a received frame having matched ID detected by acceptance filtering. The ID in the message slot 14 and the C0LMAR0 to C0LMAR4 registers are used for acceptance filtering when the message slot 14 is active (the next received frame is to be stored in the message slot 14). The ID in the message slot 15 and the C0LMBR0 to C0LMBR4 registers are used when the message slot 15 is active. Both data frame and remote frame can be received. When entering BasicCAN mode, set the same ID in two message slots and set the same values in the C0LMAR0 to C0LMAR4 registers and in the C0LMBR0 to C0LMBR4 registers. Follow the procedure below to enter BasicCAN mode. (1) Set the BASICCAN bit to "1". (2) Set IDs in the message slots 14 and 15. Set the C0LMAR0 to C0LMAR4 registers and C0LMBR0 to C0LMBR4 registers. (Set to the same values.) (3) Set the IDE14 and 15 bits in the C0IDR register to select a frame format (standard or extended) for the message slots 14 and 15. (Set to the same format.) (4) Set the REMACTIVE bit in the C0MCTL14 and C0MCTL15 registers in the message slots 14 and 15 to "0" (data frame received) and the RECREQ bit to "1" (request to receive).

Page 328 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M NOTES: 1. Change the BASICCAN bit only when the STATE_RESET bit is set to "1" (CAN module reset completed). 2. The message slot 14 is the first slot to become active after the RESET0 and RESET1 bits are set to "0". 3. The message slots 0 to 13 are not affected by entering BasicCAN mode.

22.1.1.4 TSPRE1, TSPRE0 Bits

The TSPRE1 and TSPRE0 bits determine which count source is used for the time stamp counter. NOTES: 1. Change the TSPRE1 to TSPRE0 bits only when the STATE_RESET bit is set to "1" (CAN module reset completed).

22.1.1.5 TSRESET Bit

When the TSRESET bit is set to "1" (counter reset), the C0TSR register is set to "000016". The TSRESET bit is automatically set to "0" after the C0TSR register is set to "000016".

22.1.1.6 ECRESET Bit

When the ECRESET bit is set to "1", the C0TEC and C0REC registers are set to "0016". The CAN module forcibly goes into an error active state. The ECRESET bit is automatically set to "0" after the CAN module enters an error active state. NOTES: 1. In an error active state, the CAN module is ready to communicate when 11 continuous reces- sive bits are detected on the CAN bus.

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22.1.2 CAN0 Control Register 1 (C0CTLR1 Register)

(b1 - b0) (b2) (b5 - b4) (b7 - b6) CAN0 Control Register 1 Symbol Address After Reset (1) C0CTLR1 0241 16 XX00 00XX 2 RW CAN0 Bank Switch Bit 0 : Selects the message slot control register 1 : Selects the masked register Bit Name FunctionBit Symbol Reserved Bit Set to "0" Reserved Bit Set to "0" Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. b7 b6 b5 b4 b3 b2 b1 b0 000 Figure 22.4 C0CTLR1 Register

22.1.2.1 BANKSEL Bit

The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 022016 to 023F16. The C0MCTL0 to C0MCTL15 registers can be accessed by setting the BANKSEL bit to "0". The C0GMR0 to C0GMR4 registers, C0LMAR0 to C0LMAR4 registers and C0LMBR0 to C0LMBR4 reg- isters can be accessed by setting the BANKSEL bit to "1".

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22.1.3 CAN0 Sleep Control Register (C0SLPR Register)

Figure 22.5 C0SLPR Register

22.1.3.1 SLEEP Bit

When the SLEEP bit is set to "0", the clock supplied to the CAN module stops running and enters sleep mode. When the SLEEP bit is set to "1", the clock supplied to the CAN module starts running and exits sleep mode. NOTES: 1. Enter sleep mode after the STATE_RESET bit in the C0STR register is set to "1" (CAN module reset completed). SLEEP (b7 - b1) CAN0 Sleep Control Register Symbol Address After Reset C0SLPR 0242 16 XXXX XXX0 2 RW Sleep Mode Control Bit0 : Enters sleep mode 1 : Exits sleep mode (Note 1) Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW NOTES: 1. Set up CAN module configuration after CAN sleep mode is exited. While the CAN module is in sleep mode, no SFR (addresses 01E016 to 024516) for the CAN module, except the C0SLPR register, can be accessed. b7 b6 b5 b4 b3 b2 b1 b0

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22.1.4 CAN0 Status Register (C0STR Register)

Figure 22.6 C0STR Register

22.1.4.1 MBOX3 to MBOX0 Bits

The MBOX3 to MBOX0 bits store relevant slot numbers when the CAN module has completed trans- mitting data or storing received data.

22.1.4.2 TRMSUCC Bit

The TRMSUCC bit is set to "1" when the CAN module has transmitted data as expected. The TRMSUCC bit is set to "0" when the CAN module has received data as expected. CAN0 Status Register Symbol Address After reset (1) C0STR 0203 16 - 020216 X000 0X01 0000 0000 2 RW 0 0 0 0 : Message slot 0 0 0 0 1 : Message slot 1 0 0 1 0 : Message slot 2 0 0 1 1 : Message slot 3 b2b3 b0b1 MBOX0 TRMSUCC RECSUCC Active Slot Determination Bit TRMSTATE RECSTATE STATE_RESET STATE_LOOPBACK (b10) (b15) STATE_BASICCAN STATE_BUSERROR STATE_ERRPAS STATE_BUSOFF Transmit Complete State Flag Receive Complete State Flag Transmit State Flag Receive State Flag CAN Reset State Flag Loop Back State Flag BasicCAN State Flag CAN Bus Error State Flag Error Passive State Flag Bus-off State Flag 0: Transmission is not completed 1: Transmission is completed 0: Reception is not completed 1: Reception is completed 0: Not transmitting 1: During transmission 0: Not receiving 1: During reception 0: CAN module is operating CAN module reset is completed 0: Mode except Loop back mode 1: Loop back mode 0: Mode except BasicCAN mode 1: BasicCAN mode 0: No error occurs 1: Error occurs 0: No error passive state 1: Error passive state 0: No bus-off state 1: Bus-off state MBOX1 MBOX2 MBOX3 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RO RO RO RO RO RO RO RO RO RO RO RO RO RO NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 1 1 0 1 : Message slot 13 1 1 1 0 : Message slot 14 1 1 1 1 : Message slot 15 b7 b0b15 b8

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22.1.4.3 RECSUCC Bit

The RECSUCC bit is set to "1" when the CAN module has received data as expected. (Whether received message has been stored in the message slot or not is irrelevant.) If the received message is transmitted in loopback mode, the TRMSUCC bit is set to "1" and the RECSUCC bit is set to "0". The RECSUCC bit is set to "0" when the CAN module has transmitted data as expected.

22.1.4.4 TRMSTATE Bit

The TRMSTATE bit is set to "1" when the CAN module is performing as a transmit node. The TRMSTATE bit is set to "0" when the CAN module is in a bus-idle state or starts performing as a receive node.

22.1.4.5 RECSTATE Bit

The RECSTATE bit is set to "1" when the CAN module is performing as a receive node. The RECSTATE bit is set to "0" when the CAN module is in a bus-idle state or starts performing as a transmit node.

22.1.4.6 STATE_RESET Bit

After both RESET0 and RESET1 bits are set to "1" (CAN module reset), the STATE_RESET bit is set to "1" as soon as the CAN module is reset. The STATE_RESET bit is set to "0" when the RESET0 and RESET1 bits are set to "0".

22.1.4.7 STATE_LOOPBACK Bit

The STATE_ LOOPBACK bit is set to "1" when the CAN module is in loopback mode. The STATE_LOOPBACK bit is set to "1" when the LOOPBACK bit in the C0CTLR0 register is set to "1" (loop back function enabled). The STATE_LOOPBACK bit is set to "0" when the LOOPBACK bit is set to "0" (loop back function disabled).

22.1.4.8 STATE_BASICCAN Bit

The STATE_BASICCAN bit is set to "1" when the CAN module is in BasicCAN mode. Refer to 22.1.1.3 BASICCAN Bit for BasicCAN mode. The STATE_BASICCAN bit is set to "0" when the BASICCAN bit is set to "0" (BasicCAN mode function disabled). The STATE_BASICCAN bit is set to "1" when the BASICCAN bit is set to "1" (BasicCAN mode function enabled), the REMACTIVE bits in the C0MCTL14 and C0MCTL15 registers in the message slot 14 and 15 are set to "0" (data frame received) and the RECREQ bit is set to "1" (request to receive the frame).

22.1.4.9 STATE_BUSERROR Bit

The STATE_BUSERROR bit is set to "1" when an CAN communication error is detected. The STATE_BUSERROR bit is set to "0" when the CAN module has transmitted or received data as expected. Whether a received message has been stored into the message slot or not is irrelevant. NOTES: 1. When the STATE_BUSERROR bit is set to "1", the STATE_BUSERROR bit remains un- changed even if both RESET 0 and RESET1 bits are set to "1" (CAN module reset).

22.1.4.10 STATE_ERRPAS Bit

The STATE_ERRPAS bit is set to "1" when the value of the C0TEC or C0REC register exceeds 127 and places the CAN module in an error-passive state. The STATE_ERRPAS bit is set to "0" when the CAN module in an error passive state is placed in another error state. The STATE_ERRPAS bit is set to "0" when both RESET0 and RESET1 bits are set to "1" (CAN module is reset).

22.1.4.11 STATE_BUSOFF Bit

The STATE_BUSOFF bit is set to "1" when the value of the C0TEC register exceeds 255 and the CAN module in a bus-off state. The STATE_BUSOFF bit is set to "0" when the CAN module in a bus-off state is placed in an error- active state. The STATE_BUSOFF bit is set to "0" when both RESET0 and RESET1 bits are set to "1" (CAN module reset).

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22.1.5 CAN0 Extended ID Register (C0IDR Register)

Symbol Address After Reset (1) C0IDR 0205 16 - 020416 0000 16 RW IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 Extended ID15 (message slot 15) IDE9 IDE8 IDE7 IDE6 IDE5 Standard or extended format is set by the corresponding message slot IDE4 IDE3 IDE2 IDE1 IDE0 Extended ID14 (message slot 14) Extended ID13 (message slot 13) Extended ID12 (message slot 12) Extended ID11 (message slot 11) Extended ID10 (message slot 10) Extended ID9 (message slot 9) Extended ID8 (message slot 8) Extended ID7 (message slot 7) Extended ID6 (message slot 6) Extended ID5 (message slot 5) Extended ID4 (message slot 4) Extended ID3 (message slot 3) Extended ID2 (message slot 2) Extended ID1 (message slot 1) Extended ID0 (message slot 0) 0: Standard format 1: Extended format Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. b7 b0b15 b8 Figure 22.7 C0IDR Register Bits in the C0IDR register determine the frame format in the message slot corresponding to each bit. The standard format is selected when the bit is set to "0". The extended format is selected when the bit is to set "1". NOTES: 1. Set each bit in the C0IDR register when neither transmit request nor receive request from the message slot is generated.

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22.1.6 CAN0 Configuration Register (C0CONR Register)

CAN0 Configuration Register Symbol Address After Reset (1) C0CONR 0207 16 - 020616 0000 0000 0000 XXXX 2 RW 0 0 0 : PTS = 1Tq 0 0 1 : PTS = 2Tq 0 1 0 : PTS = 3Tq 0 1 1 : PTS = 4Tq 1 0 0 : PTS = 5Tq 1 0 1 : PTS = 6Tq 1 1 0 : PTS = 7Tq 1 1 1 : PTS = 8Tq b6b7 b5 0 0 0 : Do not set to this value 0 0 1 : PBS1 = 2Tq 0 1 0 : PBS1 = 3Tq 0 1 1 : PBS1 = 4Tq 1 0 0 : PBS1 = 5Tq 1 0 1 : PBS1 = 6Tq 1 1 0 : PBS1 = 7Tq 1 1 1 : PBS1 = 8Tq b9b10 b8 0 0 0 : Do not set to this value 0 0 1 : PBS2 = 2Tq 0 1 0 : PBS2 = 3Tq 0 1 1 : PBS2 = 4Tq 1 0 0 : PBS2 = 5Tq 1 0 1 : PBS2 = 6Tq 1 1 0 : PBS2 = 7Tq 1 1 1 : PBS2 = 8Tq b12b13 b11 0 0 : SJW = 1Tq 0 1 : SJW = 2Tq 1 0 : SJW = 3Tq 1 1 : SJW = 4Tq b14b15 PTS1 PBS11 PBS21 Propagation Time Segment Phase Buffer Segment 1 Phase Buffer Segment 2 reSynchronization Jump Width SJW0 SJW1 PBS20 PBS22 PBS10 PBS12 PTS0 PTS2 Bit Name FunctionBit Symbol Sampling Number 0: Sampled once 1: Sampled three times Nothing is assigned. When write, set to "0". When read, its content is indeterminate. SAM (b3 - b0) PTS: Propagation Time Segment, PBS1: Phase Buffer Segment 1, PBS2: Phase Buffer Segment 2, SJW: reSynchronization Jump Width RW RW RW RW RW RW RW RW RW RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. b7 b0b15 b8 Figure 22.8 C0CONR Register

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22.1.6.1 SAM Bit

The SAM bit determines the number of sample points to be taken per bit. When the SAM bit is set to "0", only one sample is taken per bit at the end of the Phase Buffer Segment 1 (PBS1) to determine the value of the bit. When the SAM bit is set to "1", three samples per bit are taken; one time quantum and two time quanta before the end of PBS1, and at the end of PBS1. The sample result value which is detected more than twice becomes the value of the bit sampled.

22.1.6.2 PTS2 to PTS0 Bits

The PTS2 to PTS0 bits determine PTS width.

22.1.6.3 PBS12 to PBS10 Bits

The PBS12 to PBS10 bits determine PBS1 width. Set the PBS12 to 10 bits to "001 2" or more.

22.1.6.4 PBS22 to PBS20 Bits

The PBS22 to PBS20 bits determine PBS2 width. Set the PBS22 to PBS20 bits to "0012" or more.

22.1.6.5 SJW1 to SJW0 Bits

The SJW1 to SJW0 bits determine SJW width. Set the SJW1 to SJW0 bits to a value equal to or less than that of the PBS12 to PBS10 bits and PBS22 to PBS20 bits. Table 22.3 Bit Timing when CPU Clock = 30 MHz Baud Rate BRP Tq Clock Cycles (ns) Tq Per Bit PTS+PBS1 PBS2 Sample Point 1Mbps 1 66.7 15 12 2 87% 1 66.7 15 11 3 80% 1 66.7 15 10 4 73% 2 100 10 7 2 80% 2 100 10 6 3 70% 2 100 10 5 4 60% 500Kbps 2 100 20 16 3 85% 2 100 20 15 4 80% 2 100 20 14 5 75% 3 133.3 15 12 2 87% 3 133.3 15 11 3 80% 3 133.3 15 10 4 73% 4 166.7 12 9 2 83% 4 166.7 12 8 3 75% 4 166.7 12 7 4 67% 5 200 10 7 2 80% 5 200 10 6 3 70% 5 200 10 5 4 60%

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22.1.7 CAN0 Time Stamp Register (C0TSR Register)

Symbol Address After reset (1) C0TSR 0209 16 - 020816 0000 16 RWFunction Value of Time Stamp RO b15 b8 b7 b0 NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. Figure 22.9 C0TSR Register The C0TSR register is a 16-bit counter. The TSPRE0 and TSPRE1 bits in the C0CTLR0 register select the CAN bus bit clock divided by 1, 2, 3 or 4 as the count source for the C0TSR register. When data transmission or reception is completed, the value of the C0TSR register is automatically stored into the message slot. The C0TSR register starts a counter increment when the RESET0 and RESET1 bits in the C0CTLR0 register are set to "0". The C0TSR register is set to "000016":

at the next count timing after the C0TSR register is set to "FFFF16";
when the RESET0 and RESET1 bits are set to "1" (CAN module reset) by program, or
when the TSRESET bit is set to "1" (C0TSR register reset) by program. In loopback mode, when either data frame receive message slot or remote frame receive message slot is available to store the message, the value of the C0TSR register is also stored into the mes- sage slot when data reception is completed. The value of the C0TSR register is not stored when data transmission is completed.

22.1.8 CAN0 Transmit Error Count Register (C0TEC Register)

Figure 22.10 C0TEC Register In an error active or an error passive state, the count value of a transmission error is stored into the C0TEC register. The counter is decremented when the CAN module has transmitted data as ex- pected or is incremented when an transmit error occurs. In a bus-off state, an indeterminate value is stored into the C0TEC register. The C0TEC register is set to "00 16" when the CAN module is placed in an error active state again. CAN0 Transmit Error Count Register Symbol Address After Reset (1) C0TEC 020A 16 00 16 RWFunction Counter Value of Transmit Errors RO NTOES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. b7 b0

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22.1.9 CAN0 Receive Error Count Register (C0REC Register)

CAN0 Receive Error Count Register Symbol Address After Reset (1) C0REC 020B 16 00 16 RWFunction Counter Value of Receive Error RO NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. b7 b0 Figure 22.11 C0REC Register In an error active or an error passive state, a count value of the reception error is stored into the C0REC register. The counter is decremented when the CAN module has received data as expected or is incremented when a receive error occurs. The C0REC register is set to 127 when the C0REC register is 128 (error passive state) or more and the CAN module has received as expected. In a bus-off state, an indeterminate value is stored into the C0REC register. The C0REC register is set to "00 16" when the CAN module is placed in an error active state again.

22.1.10 CAN0 Baud Rate Prescaler (C0BRP Register)

Symbol Address After reset (1) C0BRP 0217 16 01 16 RWFunction Setting Range 0116 to FF16(2)If setting value is n, the CPU clock is divided by (n+1). RW NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 2. Do not set to "0016" (divide-by-1). b7 b0 Figure 22.12 C0BRP Register The C0BRP register determines the Tq clock cycle of the CAN bit timing. The baud rate is obtained from Tq clock cycle x Tq per bit. Tq clock cycle = (BRP+1) / f1 Baud rate = Tq per bit = SS + PTS + PBS1 + PBS2 Tq: Time quantum BRP: Setting value of the C0BRP register; 1-255 SS: Synchronization Segment; 1 Tq PTS: Propagation Time Segment; 1 to 8 Tq PBS1: Phase Buffer Segment 1; 2 to 8 Tq PBS2: Phase Buffer Segment 2; 2 to 8 Tq Tq clock cycle x Tq per bit

Page 338 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M CAN0 Slot Interrupt Status Register Symbol Address After Reset (1) C0SISTR 020D 16 - 020C16 0000 16 RW SIS15 SIS14 SIS13 SIS12 SIS11 SIS10 Message Slot 15 Interrupt Request Status Bit SIS9 SIS8 SIS7 SIS6 SIS5 Message Slot 14 Interrupt Request Status Bit Message Slot 13 Interrupt Request Status Bit Message Slot 12 Interrupt Request Status Bit Message Slot 11 Interrupt Request Status Bit Message Slot 10 Interrupt Request Status Bit Message Slot 9 Interrupt Request Status Bit Message Slot 8 Interrupt Request Status Bit Message Slot 7 Interrupt Request Status Bit Message Slot 6 Interrupt Request Status Bit Message Slot 5 Interrupt Request Status Bit Message Slot 4 Interrupt Request Status Bit Message Slot 3 Interrupt Request Status Bit Message Slot 2 Interrupt Request Status Bit Message Slot 1 Interrupt Request Status Bit Message Slot 0 Interrupt Request Status Bit SIS4 SIS3 SIS2 SIS1 SIS0 0: No interrupt requested 1: Interrupt requested(Note 2) Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Determines whether an interrupt of a corresponding message slot is requested or not. NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 2. Set to "0" by program. If it is set to "1", the value before setting to "1" remains. b7 b0b15 b8

22.1.11 CAN0 Slot Interrupt Status Register (C0SISTR Register)

Figure 22.13 C0SISTR Register

Page 339 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M When using the CAN interrupt, the C0SISTR register indicates which message slot is requesting an interrupt. The SISi bits (i=0 to 15) are not automatically set to "0" (no interrupt requested) when an interrupt is acknowledged. Set the SISj bits to "0" by program (1). Refer to 22.3 CAN Interrupt for details.

22.1.11.1 Message Slot for Transmission

The SISi bit is set to "1" (interrupt requested) when the C0TSR register is stored into the message slot i after data transmission is completed.

22.1.11.2 Message Slot for Reception

The SISi bit is set to "1" when the received message is stored in the message slot i after data reception is completed. NOTES: 1. Use the MOV instruction, instead of the bit clear instruction, to set the SISi bit to "0". Bits in the C0SISTR register, which are not being changed to "0", must be to "1". For example: To set the SIS0 bit to "0" Assembly language: mov.w #07FFFh, C0SISTR C language: c0sistr = 0x7FFF; 2. If the automatic answering function is enabled in the remote frame receive message slot, the SISi bit is set to "1" after the remote frame is received and after the data frame is transmitted. 3. In the remote frame transmit message slot, the SISi bit is set to "1" after the remote frame is transmitted and after the data frame is received. 4. The SISi bit is set to "1" if the SISi bit is set to "1" by an interrupt request and "0" by program simultaneously.

Page 340 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M CAN0 Slot Interrupt Mask Register Symbol Address After Reset (1) C0SIMKR 0211 16 - 021016 0000 16 SIM15 SIM14 SIM13 SIM12 SIM11 SIM10 Slot 15 Interrupt Request Mask Bit SIM9 SIM8 SIM7 SIM6 SIM5 Slot 14 Interrupt Request Mask Bit Slot 13 Interrupt Request Mask Bit Slot 12 Interrupt Request Mask Bit Slot 11 Interrupt Request Mask Bit Slot 10 Interrupt Request Mask Bit Slot 9 Interrupt Request Mask Bit Slot 8 Interrupt Request Mask Bit Slot 7 Interrupt Request Mask Bit Slot 6 Interrupt Request Mask Bit Slot 5 Interrupt Request Mask Bit Slot 4 Interrupt Request Mask Bit Slot 3 Interrupt Request Mask Bit Slot 2 Interrupt Request Mask Bit Slot 1 Interrupt Request Mask Bit Slot 0 Interrupt Request Mask Bit SIM4 SIM3 SIM2 SIM1 SIM0 Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0: Masks (disables) an interrupt request 1: Enables an interrupt request Determines whether the interrupt request of the corresponding message slot is enabled or masked. NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. b7 b0b15 b8

22.1.12 CAN0 Slot Interrupt Mask Register (C0SIMKR Register)

Figure 22.14 C0SIMKR Register The CiSIMKR register determines whether an interrupt request that is generated by a data transmission or reception in the corresponding message slot is enabled or disabled. When the SIMi bit (i=0 to 15) is set to "1", an interrupt request generated by a data transmission or reception in the corresponding message slot is enabled. Refer to 22.3 CAN Interrupt for details.

Page 341 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M BOIM EPIM BEIM (b7 - b3) CAN0 Error Interrupt Mask Register Symbol Address After Reset (1) C0EIMKR 0214 16 XXXX X000 2 RW 0: Masks (disables) an interrupt request 1: Enables an interrupt request Bit Name FunctionBit Symbol Bus-off Interrupt Mask Bit Error-passive Interrupt Mask Bit CAN bus-error Interrupt Mask Bit Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying the clock to the CAN module after reset. 0: Masks (disables) an interrupt request 1: Enables an interrupt request 0: Masks (disables) an interrupt request 1: Enables an interrupt request b7 b6 b5 b4 b3 b2 b1 b0

22.1.13 CAN0 Error Interrupt Mask Register (C0EIMKR Register)

Figure 22.15 C0EIMKR Register

22.1.13.1 BOIM Bit

The BOIM bit determines whether an interrupt request is enabled or disabled when the CAN module is placed in a bus-off state. When the BOIM bit is set to "1", the bus-off interrupt request is enabled.

22.1.13.2 EPIM Bit

The EPIM bit determines whether an interrupt request is enabled or disabled when the CAN module is placed in an error passive state. When the EPIM bit is set to "1", the error passive interrupt request is enabled.

22.1.13.3 BEIM Bit

The BEIM bit determines whether an interrupt request is enabled or disabled when a CAN bus error occurs. When the BEIM bit is set to "1", the CAN bus error interrupt request is enabled. Refer to 22.3 CAN Interrupt for details.

Page 342 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M CAN0 Error Interrupt Status Register Symbol Address After Reset (1) C0EISTR 0215 16 XXXX X000 2 RW BOIS EPIS BEIS (b7 - b3) Bus-Off Interrupt Status Bit (2) Error-Passive Interrupt Status Bit (2) CAN Bus-Error Interrupt Status Bit (2) 0: No interrupt is requested 1: Interrupt is requested 0: No interrupt is requested 1: Interrupt is requested 0: No interrupt is requested 1: Interrupt is requested Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying the clock to the CAN module after reset. 2. Set to "0" by program. If it is set to "1", the value before setting to "1" remains. b7 b6 b5 b4 b3 b2 b1 b0

22.1.14 CAN0 Error Interrupt Status Register (C0EISTR Register)

Figure 22.16 C0EISTR Register When using the CAN interrupt, the C0EISTR register indicates the cause of the generated error inter- rupt. The BOIS, EPIS and BEIS bits are not automatically set to "0" (no interrupt requested) even if an interrupt is acknowledged. Set these bits to "0" by program (1). Refer to 22.3 CAN Interrupt for details.

22.1.14.1 BOIS Bit

The BOIS bit is set to "1" when the CAN module is placed in a bus-off state.

22.1.14.2 EPIS Bit

The EPIS bit is set to "1" when the CAN module is placed in an error passive state.

22.1.14.3 BEIS Bit

The BEIS bit is set to "1" when a CAN bus error is detected. NOTES: 1. Use the MOV instruction, instead of the bit clear instruction, to set each bit in the CoEISTR register to "0". Bits not being changed to "0" must be set to "1". For example: To set the BOIS bit to "0" Assembly language: mov.b#006h, C0EISTR C language: c0eistr = 0x06;

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22.1.15 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask

Register B (C0GMRj (j=0 to4), C0LMARj and C0LMBRj Registers) The C0GMRj, C0LMARj and C0LMBRj registers are used for acceptance filtering. The C0GMRj register determines whether the IDs in the message slots 0 to 13 are verified. The C0LMARj register determines whether the ID in the message slot 14 is verified. The C0LMBRj register determines whether the ID in the message slot 15 is verified.

When bits in these registers are set to "0", each ID bit, standard ID 0 to 1 bit and extended ID0 to 2 bit in the CAN0 message slots i (i=0 to 15) corresponding to the bits in the above registers, is masked while acceptance filtering. (The corresponding bits are assumed to have matching IDs.)
When bits in these registers are set to "1", corresponding ID bits are compared with received IDs while acceptance filtering. If the received ID matches the ID in the message slot i, the received data having the matching ID is stored into that message slot. NOTES: 1. Change the C0GMRj register only when the message slots 0 to 13 have no receive request. 2. Change the C0LMARj register only when the message slot 14 has no receive request. 3. Change the C0LMBRj register only when the message slot 15 has no receive request. Figure 22.17 C0GMR0, C0LMAR0 and C0LMBR0 Registers CAN0 Global Mask Register Standard ID0(1) CAN0 Local Mask Register A Standard ID0(1) CAN0 Local Mask Register B Standard ID0(1) Symbol Address After Reset (2) C0GMR0 0228 16 XXX0 0000 2 C0LMAR0 0230 16(3) XXX0 0000 2 C0LMBR0 0238 16(4) XXX0 0000 2 RW SID6M SID7M SID8M SID9M Standard ID6 0: No ID is checked 1: ID is checked Standard ID7 Standard ID8 Standard ID9 SID10M (b7 - b5) Standard ID10 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR0 register shares the same address with the C0MCTL0 register. 4. The C0LMBR0 register shares the same address with the C0MCTL8 register. b7 b6 b5 b4 b3 b2 b1 b0

Page 344 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M CAN0 Global Mask Register Standard ID1(1) CAN0 Local Mask Register A Standard ID1(1) CAN0 Local Mask Register B Standard ID1(1) Symbol Address After Reset (2) C0GMR1 0229 16 XX00 0000 2 C0LMAR1 0231 16(3) XX00 0000 2 C0LMBR1 0239 16(4) XX00 0000 2 RW Standard ID0 0: No ID is checked 1: ID is checked Standard ID1 Standard ID2 Standard ID3 Standard ID4 Standard ID5 SID0M SID1M SID2M SID3M SID4M SID5M (b7 - b6) Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR1 register shares the same address with the C0MCTL1 register. 4. The C0LMBR1 register shares the same address with the C0MCTL9 register. b7 b6 b5 b4 b3 b2 b1 b0 CAN0 Global Mask Register Extended ID0(1) CAN0 Local Mask Register A Extended ID0(1) CAN0 Local Mask Register B Extended ID0(1) Symbol Address After Reset (2) C0GMR2 022A 16 XXXX 0000 2 C0LMAR2 0232 16(3) XXXX 0000 2 C0LMBR2 023A 16(4) XXXX 0000 2 RW EID14M EID15M EID16M EID17M (b7 - 4) Extended ID14 0: No ID is checked 1: ID is checked Extended ID15 Extended ID16 Extended ID17 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR2 register shares the same address with the C0MCTL2 register. 4. The C0LMBR2 register shares the same address with the C0MCTL10 register. b7 b6 b5 b4 b3 b2 b1 b0 Figure 22.18 C0GMR1, C0LMAR1 and C0LMBR1 Registers and C0GMR2, C0LMAR2 and C0LMBR2 Registers

Page 345 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M CAN0 Global Mask Register Extended ID1(1) CAN0 Local Mask Register A Extended ID1(1) CAN0 Local Mask Register B Extended ID1(1) Symbol Address After Reset (2) C0GMR3 022B 16 00 16 C0LMAR3 0233 16(3) 00 16 C0LMBR3 023B 16(4) 00 16 EID6M EID7M EID8M EID9M EID10M EID11M EID13M EID12M Extended ID6 0: No ID is checked 1: ID is checked Extended ID7 Extended ID8 Extended ID9 Extended ID10 Extended ID11 Extended ID12 Extended ID13 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR3 register shares the same address with the C0MCTL3 register. 4. The C0LMBR3 register shares the same address with the C0MCTL11 register. CAN0 Global Mask Register Extended ID2(1) CAN0 Local Mask Register A Extended ID2(1) CAN0 Local Mask Register B Extended ID2(1) Symbol Address After Reset (2) C0GMR4 022C 16 XX00 0000 2 C0LMAR4 0234 16(3) XX00 0000 2 C0LMBR4 023C 16(4) XX00 0000 2 EID0M EID1M EID2M EID3M EID4M EID5M (b7 - b6) Extended ID0 0: No ID is checked 1: ID is checked Extended ID1 Extended ID2 Extended ID3 Extended ID4 Extended ID5 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR4 register shares the same address with the C0MCTL4 register. 4. The C0LMBR4 register shares the same address with the C0MCTL12 register. b7 b6 b5 b4 b3 b2 b1 b0 Figure 22.19 C0GMR3, C0LMAR3 and C0LMBR3 Registers and C0GMR4, C0LMAR4 and C0LMBR4 Registers

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22.1.16 CAN0 Message Slot i Control Register (C0MCTLi Register) (i=0 to 15)

CAN0 Message Slot i Control Register (i=0 to 15)(1) Symbol Address After Reset (2) C0MCTL0 to C0MCTL3 0230 16(3), 023116(3), 023216(3), 023316(3) 0000 00002 C0MCTL4 to C0MCTL7 023416(3), 023516, 023616, 023716 0000 00002 C0MCTL8 to C0MCTL11 0238 16(3), 023916(3), 023A16(3), 023B16(3) 0000 00002 C0MCTL12 to C0MCTL15 023C 16(3), 023D 16, 023E16, 023F16 0000 00002 When receive,NEWDATAWhen transmit,SENTDATA When receive,INVALDATAWhen transmit,TRMACTIVE MSGLOST REMACTIVE RSPLOCK REMOTE TRMREQ RECREQ Receive Complete Flag Transmit Complete Flag Receiving Flag Transmitting Flag In modes other than BasicCan mode 0: Data frame 1: Remote frame In BasicCan mode 0: Receives the data frame (status) 1: Receives the remote frame (status) 0: Enables automatic answering of the remote frame 1: Disables automatic answering of the remote frame 0: Transmits/receives the data frame 1: Transmits/receives the remote frame 0: No request to receive the frame 1: Request to receive data 0: No request to transmit the frame 1: Request to transmit data Overwrite Flag Remote Frame Transmit/Receive Status Flag Automatic Answering Disable Mode Select Bit Remote Frame Set Bit Receive Request Bit Transmit Request Bit 0: No overrun error occurs 1: Overrun error occurs (Note 4) 0: Not transmitted(4) 0: Not received(4) 1: Transmit complete 1: Receive complete When transmitting When receiving 0: Stops transmitting 0: Stops receiving 1: Transmits 1: Stores received data When transmitting When receiving Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 RW RW RO RW RO RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0MCTL0 to C0MCTL4 registers each share addresses with the C0MAR0 to C0MAR4 registers. 4. Each bit can be set to "0" by program. If it is set to "1", the value before setting to "1" remains. Figure 22.20 C0MCTL0 to C0MCTL15 Registers Table 22.4 C0MCTLi Register (i= 0 to 15) Settings and Transmit/Receive Mode Settings for the C0MCTLi Register TRMREQ RECREQ REMOTE RSPLOCK REMACTIVE MSGLOST TRMACTIVE SENTDATA Transmit/Receive Mode INVALDATA NEWDATA 0000 0 0 0 0 No frame is transmitted or received 0 1 0 0 0 0 0 0 Data frame is received 0 1 1 1 0 0 0 0 Remote frame is received or (The data frame is transmitted 0 after receiving the remote frame.) 1 0 0 0 0 0 0 0 Data frame is transmitted 1010 0 0 0 0 Remote frame is transmitted (The data frame is received after transmitting the remote frame)

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22.1.16.1 SENTDATA/NEWDATA Bit

The SENTDATA/NEWDATA bit indicates that the CAN module has transmitted or received the CAN message. Set the SENTDATA/NEWDATA bit to "0 " (not transmitted or not received) by program before data transmission and reception is started. The SENTDATA/NEWDATA bit is not set to "0" automatically. When the TRMACTIVE/INVALDATA bit is set to "1" (during transmission or storing received data), the SENTDATA/NEWDATA bit cannot be set to "0". SENTDATA : The SENTDATA bit is set to "1" (transmit complete) when a data transmission is completed in the transmit message slot. NEWDATA : The NEWDATA bit is set to "1" (receive complete) when the message to be stored into the message slot i (i=0 to 15) is received in the receive message slot as expected. NOTES: 1. To read a received data from the message slot i, set the NEWDATA bit to "0" before reading. If the NEWDATA bit is set to "1" immediately after reading, this indicates that new received data has been stored into the message slot while reading and the data read contains an indetermi- nate value. In this case, discard the data with indeterminate value and then read the message slot again after the NEWDATA bit is set to "0". 2. When the remote frame is transmitted or received, the SENTDATA/NEWDATA bit remains un- changed after the remote frame transmission or reception is completed. The SENTDATA/ NEWDATA bit is set to "1" when a subsequent data frame transmission or reception is completed.

22.1.16.2 TRMACTIVE/INVALDATA Bit

The TRMACTIVE/INVALDATA bit indicates that the CAN module is transmitting or receiving a mes- sage and accessing the message slot i. The TRMACTIVE/INVALDATA bit is set to "1" when the CAN module is accessing the message slot and to "0 " when not accessing the message slot. TRMACTIVE : The TRMACTIVE bit is set to "1" (transmitting) when a data transmission is started in the message slot. The TRMACTIVE bit is set to "0" (stops transmitting) if the CAN module loses in bus arbitration and a CAN bus error occurs or when a data transmission is completed. INVALDATA : The INVALDATA bit is set to "1" (storing received data) when receiving a message and storing a received data into the message slot i. Data, if read from the message slot i while this bit is set to "1", is indeterminate.

22.1.16.3 MSGLOST Bit

The MSGLOST bit is valid only when the message slot is set for reception. The MSGLOST bit is set to "1" (overrun error occurred) when the message slot i is overwritten by a new received message while the NEWDATA bit set to "1" (already received). The MSGLOST bit is not automatically set to "0". Set to "0" (no overrun error occurred) by program.

22.1.16.4 REMACTIVE Bit

The C0MCTL0 to C0MCTL15 registers all have the same function when the STATE_BASICCAN bit is set to "0" (other than BasicCAN mode). The REMACTIVE bit is set to "1" (remote frame) when the message slot i is set to transmit or receive the remote frame. The REMACTIVE bit is set to "0" (data frame) after the remote frame has been transmitted or received. The functions of the C0MCTL14 and C0MCTL15 registers change when the STATE_BASICCAN bit is set to "1" (BasicCAN mode). When the REMACTIVE bit is set to "0", this indicates that a message stored into the message slot is the data frame. When the REMACTIVE bit is set to "1", this indicates a message stored into the message slot is the remote frame.

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22.1.16.5 RSPLOCK Bit

The RSPLOCK bit is valid only when remote frame reception shown in Table 22.4 is selected. The RSPLOCK bit determines whether the received remote frame is processed or not. When the RSPLOCK bit is set to "0" (automatic answering of the remote frame enabled), the slot automatically changes to a transmit slot after the remote frame is received, and the message stored into the message slot is automatically transmitted as the data frame. When the RSPLOCK bit is set to "1" (automatic answering of the remote frame disabled), message is not automatically transmitted upon receiving the remote frame. Set the RSPLOCK bit to "0" to select any transmit/receive mode other than the remote frame recep- tion.

22.1.16.6 REMOTE Bit

The REMOTE bit selects transmit/receive mode shown in Table 22.4. Set the REMOTE bit to "0" to transmit or receive data frame. Set to "1" to transmit or receive remote frame. The followings occur during remote frame transmission or reception.

Transmitting the remote frame A message stored into the message slot i (i=0 to 15) is transmitted as the remote frame. After transmission, the slot automatically becomes ready to receive data frame. If the data frame is received before the remote frame is transmitted, the data frame is stored into the message slot i. The remote frame is not transmitted.
Receiving the remote frame The message slot receives the remote frame. The RSPLOCK bit determines whether or not to process the received remote frame.

22.1.16.7 RECREQ Bit

The RECREQ bit selects transmit/receive mode shown in Table 22.4. Set the RECREQ bit to "1" (receive requested) when data frame or remote frame is received. Set the RECREQ bit to "0" (no receive requested) when data frame or remote frame is transmitted. When a data frame is automatically transmitted after a remote frame is received, the RECREQ bit remains set to "1". Set the RECREQ bit to "0" to transmit a remote frame. After a remote frame is transmitted, a data frame is automatically received while the RECREQ bit remains set to "0". When setting the TRMREQ bit to "1" (transmit requested), do not set the RECREQ bit to "1" (receive requested).

22.1.16.8 TRMREQ Bit

The TRMREQ bit selects transmit/receive mode shown in Table 22.4. Set the TRMREQ bit to "1" (transmit requested) when data frame or remote frame is transmitted. Set the TRMREQ bit to "0" (no request to transmit the frame) when data frame or remote frame is received. When the data frame is automatically received after the remote frame is transmitted, the TRMREQ bit remains set to "1". Set the TRMREQ bit to "0" to receive the remote frame. After the remote frame is received, data frame is automatically transmitted while the TRMREQ bit remains set to "0". If the RECREQ bit is set to "1" (request to receive the frame), do not set the TRMREQ bit to "1" ( request to transmit the frame).

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22.1.17 CAN0 Slot Buffer Select Register (C0SBS Register)

Figure 22.21 C0SBS Register

22.1.17.1 SBS03 to SBS00 Bits

If the SBS03 to SBS00 bits select a number i (i=0 to 15), the message slot i is allocated to the CAN0 message slot buffer 0. The message slot i can be accessed via addresses 01E0 16 to 01EF16.

22.1.17.2 SBS13 to SBS10 Bits

If the SBS13 to SBS10 bits select a number i, the message slot i is allocated to the CAN0 message slot buffer 1. The message slot i can be accessed via addresses 01F0 16 to 01FF16.

22.1.18 Message Slot Buffer

The message slot, selected by setting the C0SBS register, is read by reading the message slot buffer. A message can be written in the message slot selected by the C0SBS register if the message is written to the message slot buffer. CAN0 Slot Buffer Select Register Symbol Address After Reset (2) C0SBS 0240 16 00 16 SBS00 SBS01 CAN0 Message Slot Buffer 0 Number Select Bit CAN0 Message Slot Buffer 1 Number Select Bit SBS02 SBS03 SBS10 SBS11 SBS12 SBS13 0 0 0 0 : Message slot 0 0 0 0 1 : Message slot 1 0 0 1 0 : Message slot 2 0 0 1 1 : Message slot 3 (Note 1) (Note 1) Bit Name FunctionBit Symbol b3 b2 b1 b0 1 1 0 0 : Message slot 12 1 1 0 1 : Message slot 13 1 1 1 0 : Message slot 14 1 1 1 1 : Message slot 15 0 0 0 0 : Message slot 0 0 0 0 1 : Message slot 1 0 0 1 0 : Message slot 2 0 0 1 1 : Message slot 3 b3 b2 b1 b0 1 1 0 0 : Message slot 12 1 1 0 1 : Message slot 13 1 1 1 0 : Message slot 14 1 1 1 1 : Message slot 15 RW RW RW RW RW RW RW RW RW NOTES: 1. 16 CAN0 message slots provided. Each message slot can be selected as a transmit or a receive slot. 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. b7 b6 b5 b4 b3 b2 b1 b0

Page 350 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M Figure 22.22 C0SLOT0_0, C0SLOT1_0 Registers and C0SLOT0_1, C0SLOT1_1 Registers CAN0 Message Slot Buffer i Standard ID0 (i=0,1)(1) Symbol Address After Reset C0SLOT0_0, C0SLOT1_0 01E016, 01F016 Indeterminate SID6 SID7 SID8 SID9 SID10 (b7 - b5) Standard ID6 Standard ID7 Standard ID8 Standard ID9 Standard ID10 Read or write the standard ID6 in the message slot j (j=0 to 15) Read or write the standard ID7 in the message slot j Read or write the standard ID8 in the message slot j Read or write the standard ID9 in the message slot j Read or write the standard ID10 in the message slot j Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_0 register. RW RW RW RW RW RW CAN0 Message Slot Buffer i Standard ID1 (i=0,1)(1) Symbol Address After Reset C0SLOT0_1, C0SLOT1_1 01E116, 01F116 Indeterminate SID0 SID1 SID2 SID3 SID4 SID5 (b7 - b6) Standard ID0 Read or write the standard ID0 in the message slot j (j=0 to 15) Standard ID1 Standard ID2 Standard ID3 Standard ID4 Standard ID5 Read or write the standard ID1 in the message slot j Read or write the standard ID2 in the message slot j Read or write the standard ID3 in the message slot j Read or write the standard ID4 in the message slot j Read or write the standard ID5 in the message slot j Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW NOTES: 1. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_0 register.

Page 351 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M Figure 22.23 C0SLOT0_2, C0SLOT1_2 Registers and C0SLOT0_3, C0SLOT1_3 Registers CAN0 Message Slot Buffer i Extended ID0 (i=0,1)(1, 2) Symbol Address After Reset C0SLOT0_2, C0SLOT1_2 01E216, 01F216 Indeterminate EID14 EID15 Extended ID14 Extended ID15 Read or write the extended ID14 in the message slot j (j=0 to 15) Read or write the extended ID15 in the message slot j EID16 EID17 (b7 - b4) Extended ID16 Extended ID17 Read or write the extended ID16 in the message slot j Read or write the extended ID17 in the message slot j Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. If the receive slot is standard ID formatted, the EID17 to EID14 bits are indeterminate when the received data is stored. 2. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_2 register. RW RW RW RW RW CAN0 Message Slot Buffer i Extended ID1 (i=0,1)(1, 2) Symbol Address After Reset C0SLOT0_3, C0SLOT1_3 01E316, 01F316 Indeterminate EID6 EID7 EID8 EID9 Extended ID6 Read or write the extended ID6 in the message slot j (j=0 to 15) Extended ID7 Extended ID8 Extended ID9 Read or write the extended ID 7 in the message slot j Read or write the extended ID 8 in the message slot j Read or write the extended ID 9 in the message slot j EID10 EID11 Extended ID10 Extended ID11 Read or write the extended ID 10 in the message slot j Read or write the extended ID 11 in the message slot j EID12 EID13 Extended ID12 Extended ID13 Read or write the extended ID 12 in the message slot j Read or write the extended ID 13 in the message slot j Bit Name FunctionBit Symbol NOTES: 1. If the receive slot is standard ID formatted, the EID13 to EID6 bits are indeterminate when the received data is stored. 2. Select, by setting the C0SBS register the message slot j to be accessed by the C0SLOTi_3 register. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW

Page 352 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M Figure 22.24 C0SLOT0_4, C0SLOT1_4 Registers and C0SLOT0_5 and C0SLOT1_5 Registers CAN0 Message Slot Buffer i Extended ID2 (i=0,1)(1, 2) Symbol Address After Reset C0SLOT0_4, C0SLOT1_4 01E416, 01F416 Indeterminate EID0 EID1 EID2 EID3 Extended ID0 Read or write the extended ID0 in the message slot j (j=0 to 15) Extended ID1 Extended ID2 Extended ID3 Read or write the extended ID1 in the message slot j Read or write the extended ID2 in the message slot j Read or write the extended ID3 in the message slot j EID4 EID5 (b7 - b6) Extended ID4 Extended ID5 Read or write the extended ID4 in the message slot j Read or write the extended ID5 in the message slot j Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. If the receive slot is standard ID formatted, the EID 5 to EID0 bits are indeterminate when received data is stored. 2. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_4 register. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW CAN0 Message Slot Buffer i Data Length Code (i=0,1)(1) Symbol Address After Reset C0SLOT0_5, C0SLOT1_5 01E516, 01F516 Indeterminate Read or write the data length set bit in the message slot j (j=0 to 15) DLC0 DLC1 DLC2 DLC3 (b7 - b4) Data Length Set Bit Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_5 register. RW RW RW RW RW

Page 353 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M Figure 22.25 C0SLOT0_6 to C0SLOT0_13, C0SLOT1_6 to C0SLOT1_13, C0SLOT0_14, C0SLOT1_14, C0SLOT0_15 and C0SLOT1_15 Registers CAN0 Message Slot Buffer i Data k (i=0,1 k=0 to 7)(1) Symbol Address After Reset C0SLOT0_q(q=k+6,k=0 to 3) 01E6 16, 01E716, 01E816, 01E916 Indeterminate C0SLOT0_q(q=k+6,k=4 to 7) 01EA 16, 01EB16, 01EC16, 01ED16 Indeterminate C0SLOT1_q(q=k+6,k=0 to 3) 01F6 16, 01F716, 01F816, 01F916 Indeterminate C0SLOT1_q(q=k+6,k=4 to 7) 01FA 16, 01FB16, 01FC16, 01FD16 Indeterminate RW RW Function Setting Range Read or write data k in the message slot j (j=0 to 15) 0016 to FF16 NOTES: 1. Select, by setting the C0SBS register, the data k in the message slot j to be accessed by the C0SLOTi_q register. b7 b0 CAN0 Message Slot Buffer i Time Stamp High-Ordered (i=0,1)(1) Symbol Address After Reset C0SLOT0_14, C0SLOT1_14 01EE16, 01FE 16 Indeterminate RW RW Function Setting Range Read or write the time stamp high-ordered in the message slot j (j=0 to 15) 0016 to FF16 NOTES: 1. Select, by setting the COSBS register, the time stamp high-ordered in the message slot j to be accessed by the C0SLOTi_14 register. b7 b0 CAN0 Message Slot Buffer i Time Stamp Low-Ordered (i=0,1)(1) Symbol Address After Reset C0SLOT0_15, C0SLOT1_15 01EF16, 01FF16 Indeterminate RW RW Function Setting Range Read or write the time stamp low-ordered in the message slot j (j=0 to 15) 0016 to FF16 NOTES: 1. Select, by setting the COSBS register, the time stamp low-ordered in the message slot j to be accessed by the C0SLOTi_15 register. b7 b0

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22.1.19 CAN0 Acceptance Filter Support Register (C0AFS Register)

Figure 22.26 C0AFS Register The C0AFS register enables prompt performance of the table search to determine the validity of a received ID. This function is for standard-formatted ID only. CAN0 Acceptance Filter Support Register Symbol Address After Reset (1) C0AFS 0245 16 - 024416 0100 16 RW RW Function Setting Range Generates data to determine a received ID 000016 to FFFF16 NOTES: 1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying the clock to the CAN module after reset. b15 b0 b8 b7 b15 b0 SID5 SID4 SID3 SID2 SID1 SID0 SID10SID9 SID8 SID7SID6 SID5 SID4 SID3CSID2 CSID1 CSID0 SID10SID9 SID8 SID7 SID6CSID5 CSID4 CSID3CSID7 CSID6 Write Read 3-8 decoding b7b8b15 b0 00716 "0" 00616 "0" 00516 "0" 00416 "0" 00316 "0" 00216 "0" 00116 "1" 00016 "0" 00F16 "1" 00E16 "0" 00D 16 "0" 00C 16 "0" 00B16 "0" 00A16 "0" 00916 "0" 00816 "0" 6F716 "0" 6F616 "0" 6F516 "0" 6F416 "0" 6F316 "1" 6F216 "0" 6F116 "0" 6F016 "0" 7F716 "0" 7F616 "0" 7F516 "0" 7F416 "0" 7F316 "0" 7F216 "0" 7F116 "0" 7F016 "1" 7FF16 "0" 7FE 16 "0" 7FD 16 "1" 7FC 16 "0" 7FB 16 "0" 7FA16 "0" 7F916 "0" 7F816 "0" Top+0016 Top+0116 Top+FE16 Top+FF16 Top+DE 16 b7 b6 b5 b4 b3 b2 b1 b0 Address search information Bit search information Write to the C0AFS register 0011001100011011 SID4 SID3 SID2 SID1 SID0 SID10SID9 SID8 SID7 SID6 11011110011 SID10 SID0 Read from the C0AFS register 0000100011011110 Divide it to 8 bits and 3 bits Received ID Bit search information Address search information SID5 b7b8 b0b15 b7b8 b0 b7 b0 b15 0116 0216 0416 0816 1016 2016 4016 8016 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 116 216 316 416 516 616 716 Bit search information 3 low-order bits of received ID 8 bits 3 bits Because the value of the 3 bits is 3, b3 in the table on the left is 1. (If the value of the 3 bits is 4, b4 in the table in the left is 1.) Data used to search a data table is generated from a received ID in stan- dard format. The table search with this data determines whether or not a re- ceived ID is valid.

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22.2 Timing with CAN-Associated Registers

22.2.1 CAN Module Reset Timing

Figure 22.27 shows an operation example of when the CAN module is reset. (1) The CAN module can be reset when the STATE_RESET bit in the C0STR register is set to "1" (CAN module reset completed) after the RESET0 and RESET1 bits in the C0CTLR0 register are set to "1" (CAN module reset). (2) Set necessary CAN-associated registers. (3) CAN communication can be established after the STATE_RESET bit is set to "0" (resetting) after the RESET0 and RESET1 bits are set to "0" (CAN module reset exited) . Figure 22.27 Example of CAN Module Reset Operation

22.2.2 CAN Transmit Timing

Figure 22.28 shows an operation example of when the CAN transmits a frame. (1) When the TRMREQ bit is set to "1" (request to transmit the data frame) while the CAN bus is in as idle state, the TRMACTIVE bit in the C0MCTLi register (i=0 to 15) is set to "1" (during transmis- sion) and the TRMSTATE bit in the C0STR register is set to "1" (during transmission). The CAN starts transmitting the frame. (2) After a CAN frame transmission is completed, the SENTDATA bit in the C0MCTLi register is set to "1" (already transmitted), the TRMSUCC bit in the C0STR register to "1" (transmission completed) and the SISi bit in the C0SISTR register to "1" (interrupt requested). The MBOX3 to MBOX0 bits in the C0STR register store transmitted message slot numbers. RESET0 bit "1" "0" RESET1 bit "1" "0" STATE_RESET bit "1" "0" CAN counfiguration Verify the STATE_RESET bit CAN operation Set to "1" by program simultaneously Operation (1) Set to "0" by program simultaneously Operation (2) Operation (3) Verify the STATE_RESET bit

Page 356 884fo6002,13.naJ13.1.veR 1310-4300B90JER 22. CAN Module)T38/C23M,38/C23M(puorG38/C23M Figure 22.28 Example of CAN Data Frame Transmit Operation

22.2.3 CAN Receive Timing

Figure 22.29 shows an operation example of when the CAN receives a frame. (1) When the RECREQ bit in the C0MCTLi register (i=0 to 15) is set to "1" (receive requested), the CAN is ready to receive the frame at anytime. (2) When the CAN starts receiving the frame, the RECSTATE bit in the C0STR register is set to "1" (during reception). (3) After the CAN frame reception is completed, the INVALDTA bit in the C0MCTLi register is set to "1" (storing received data), the NEWDATA bit in the C0MCTLi register is set to "1" (receive com- plete) and the RECSUCC bit in the C0STR register is set to "1" (reception completed). (4) After data is written to the message slot, the INVALDATA bit is set to "0" (stops receiving) and the SISi bit is set to "1" (interrupt requested). The MBOX3 to MBOX0 bits store received message slot numbers. SENTDATA bit TRMREQ bit MBOX3 - MBOX0 bits Bus idle Start transmtting (1) Intermission field CAN bus Transmit frame Transmission completed (2) "1" "0" "1" "0" TRMACTIVE bit "1" "0" Set to "1" by program simultaneously TRMSUCC bit "1" "0" TRMSTATE bit "1" "0" SISi bit "1" "0" Transmission-completed message slot number Transmit frame Bus idle i = 0 to 15 NEWDATA bit RECREQ bit MBOX3 - MBOX0 bits Start receiving (2) Intermission field CAN bus Receive frame Reception completed INVALDATA bit Reception-completed message slot number RECSUCC bit RECSTATE bit SISi bit (1) (4)(3) Set to "1" by program simultaneously Bus idle Bus idleReceive frame "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" i = 0 to 15 Figure 22.29 Example of CAN Data Frame Receive Operation

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22.2.4 CAN Bus Error Timing

Figure 22.30 shows an operation example of when a CAN bus error occurs. (1) When a CAN bus error is detected, the STATE_BUSERROR bit in the CiSTR register is set to "1", (error occurred) and the BEIS bit in the CiEISTR register is set to "1" (interrupt requested). The CAN starts transmitting the error frame. STATE_BUSERROR bit CAN bus Error frameTransmit / receive frame BEIS bit (1) Error detected "1" "0" "1" "0" Figure 22.30 Operation Timing when CAN Bus Error Occurs

22.3 CAN Interrupts

The CANj interrupt (j=0 to 2) is provided as the CAN interrupt. Figure 22.31 shows a block diagram of the CAN interrupt. The following factors cause the CAN-associated interrupt request to be generated. - The CAN0 slot i (i=0 to 15) completes a transmission - The CAN0 slot i completes a reception - The CAN0 module detects a bus error - The CAN0 module moves into an error-passive state - The CAN0 module moves into a bus-off state The CANj interrupt, caused by one of the CANi interrupt request factors listed above, is generated via the OR circuit. If an interrupt request factor is established, the corresponding bit in the C0SISTR register is set to "1" (interrupt requested) when the CAN0 slot k completes a transmission or a reception. The corresponding bit in the C0EISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error, moves into an error-passive state, or moves into a bus-off state. The CAN0 interrupt request signal is set to "1" when the corresponding bit in the C0SISTR or C0EISTR is set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR is set to "1". When the CAN0 interrupt request signal changes from "0" to "1", all CANjR bits in the IIO9IR to IIO11IR registers are set to "1" (interrupt requested). If at least one of the CANjE bits in the IIO9IE to IIO11IE registers is set to "1" (interrupt enabled), the IR bits in the corresponding CANjIC registers are set to "1" (interrupt requested). The CAN0 interrupt request signal remains set to "1" if another interrupt request causes a corresponding bit in the C0SISTR or C0EISTR to be set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR to be set to "1" after the CAN0 interrupt request signal changes "0" to "1". The CANjR and IR bits also remain unchanged. Bits in the C0SISTR or C0EISTR register and CANjR bits (j=0 to 2) in the IIO9IR to IIO11IR registers are not set to "0" automatically, interrupt acknowledgment notwithstanding. Set these bits to "0" by pro- gram. The CANi interrupts are acknowledged when the CANjR bit in the IIO9IR to IIO11IR register and the corresponding bit in the C0SISTR or C0EISTR register, which are set to enable interrupts though setting the C0SIMKR or C0EIMKR register, are set to "0". If these bits remain set to "1", all CAN-associated interrupt request factors become invalid.

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SIM0 bit CAN0 slot 0 received CAN0 slot 0 transmitted SIS0 bit SIM15 bit CAN0 slot15 received CAN0 slot15 transmitted CAN0 bus error detection SIS15 bit BEIM bit BEIS bit CAN0 transition into error-passive state EPIM bit EPIS bit CAN0 transition into bus-off state BOIM bit BOIS bit CAN0 interrupt request signal CAN0(request) CAN0R bit in IIO9IR register CAN0(enable) CAN0E bit in IIO9IE register CAN1(request) CAN1R bit in IIO10IR register CAN1(enable) CAN1E bit in IIO10IE register CAN2(request) CAN2R bit in IIO11IR register CAN2(enable) CAN2E bit in IIO11IE register IR bit in CAN0IC register IR bit in CAN1IC register IR bit in CAN2IC register Figure 22.31 CAN Interrupts

Page 359 884fo6002,13.naJ13.1.veR 1310-4300B90JER 23. DRAMC)T38/C23M,38/C23M(puorG38/C23M 23. DRAMC The DRAM controller (DRAMC) controls the DRAM area, which ranges from 512 Kbytes to 8 Mbytes. Table 23.1 lists specifications of the DRAMC. Table 23.1 DRAMC Specifications Item Specification DRAM Area 512 KB, 1 MB, 2 MB, 4 MB, 8 MB Bus Control 2CAS/1W Refresh CAS-before-RAS refresh, Self refresh Supported Function Mode EDO, fast page mode Wait State Insertion 1-wait state, 2-wait state Table 23.2 shows pins associated with DRAMC. Signals listed in Table 23.2 are output by setting the AR2 to AR0 bits in the DRAMCONT register for the DRAM area and accessing DRAM. See Table 7.9 for RAS, CASL, CASH and DW signal operations. Figure 23.1 shows the DRAMCONT register and REFCNT regis- ter. Table 23.2 DRAMC-associated Pins Port Bus for Device Access except DRAM(1) Bus for DRAM Access P0 D 0 to D7 D 0 to D7 P1 D 8 to D15 D 8 to D15(2) P3 A 8 to D15 MA 0 to MA7 P40 to P44 A16 to A20 MA 8 to MA12 P50 WRL / WR CASL P51 WRH / BHE CASH P52 ____ RD DW P56 ALE RAS NOTES: 1. This is an example of the separate bus and 16-bit data bus. 2. This bus is available when the DS2 bit in the DS register is set to "1" (16-bit data bus) and the PM02 bit in the PM0 register is set to "1" (RD/WRL/WRH in R/W mode).

Page 360 884fo6002,13.naJ13.1.veR 1310-4300B90JER 23. DRAMC)T38/C23M,38/C23M(puorG38/C23M Function DRAM Control Register Bit NameBit Symbol Symbol Address After Reset DRAMCONT 0040 16 Indeterminate (1) RW AR1 AR2 (b6 - b4) WT AR0 SREF Notes: 1. Contents of the DRAMCONT register is indeterminate. DRAMC starts operation when this register is written to. 3. Refer to 23.2.2 Self-refresh for SREF bit setup procedure. When the SREF bit is set to "1", both RAS and CAS output "L". When any external device, excluding DRAM, is attached, the WR signal is "L". 4. The DS register determines the data bus width . CASH is indeterminate when the 8-bit data bus is selected. Self-refresh Mode Bit (3) 0 : 2-wait state 1 : 1-wait state b3 b2 b1 0 0 0 : Disables DRAM 0 0 1 : Do not set to this value 0 1 0 : 512KB 0 1 1 : 1MB 1 0 0 : 2MB 1 0 1 : 4MB 1 1 0 : 8MB 1 1 1 : Do not set to this value 0 : Self-refresh is off 1 : Self-refresh is on Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Wait Select Bit(2) RW RW RW RW RW DRAM Area Select Bit b7 b6 b5 b4 b3 b2 b1 b0 Setting RangeFunction RW If setting value is n, Refresh interval = CPU clock cycle X (n + 1) X 320016 to FF16 RW Symbol Address After Reset REFCNT 0041 16 Indeterminate DRAM Refresh Interval Set Register b7 b0 Figure 23.1 DRAMCONT Register and REFCNT Register

Page 361 884fo6002,13.naJ13.1.veR 1310-4300B90JER 23. DRAMC)T38/C23M,38/C23M(puorG38/C23M DRAMC is not available when the PM11 to PM10 bits in the PM1 register are set to "112" (mode 3). Set the PM11 to PM10 bits to "002," "012" or "102" (mode 0 to 2). When the 16-bit DRAM data bus is selected, set the PM02 bit in the PM0 register to "1" (RD/WRH/WRL). Required wait time between DRAM power-on and memory operation, and necessary processing of dummy cycle for refresh varies with externally attached DRAM specifications.

23.1 DRAMC Multiplexed Address Output

DRAMC outputs signals, which are multiplexed row addresses and column addresses, to address bus A8 to A20. Figure 23.2 shows an output format for multiplexed addresses.

23.2 Refresh

23.2.1 Refresh

Refresh method is the CAS-before-RAS refresh. The REFCNT register controls the refresh interval. Re- fresh signals are not output in a hold state. The setting value of the REFCNT register is obtained as follows: The value of the REFCNT register (00 16 to FF16) = refresh interval time / (CPU clock frequency X 32) - 1

23.2.2 Self-Refresh

The refresh signal described in 23.2.1 stops while the CPU stops in stop mode, etc. The DRAM self- refresh function can be activated by setting the self-refresh before the CPU stops. Setting and cancella- tion procedures for the self-refresh are as follows: (1) Setting self-refresh (with 1 wait state, 4 Mbytes)

•• mov.b #00000001b,DRAMCONT ;Set the AR2 to AR0 bits to "000 2" (DRAM disabled) mov.b #10001011b,DRAMCONT ;Set the AR2 to AR0 bits again and the SREF bit to "1" (self-refresh on) simultaneously nop ;Execute the nop instruction twice nop ;
•• (2) Cancellation of self-refresh (with 1 wait state, 4M bytes)
•• mov.b #00000001b,DRAMCONT ;Set the AR2 to 0 bits to "000 2" (self-refresh cancellation) and the SREF bit to "0" (DRAM disabled) simultaneously mov.b #00001011b,DRAMCONT ;Set the AR2 to AR0 bits again mov.b 400h, 400h ;DRAM access is disabled immediately after cancellation. This is an example of a dummy read operation.
•• Both RAS and CAS are held "L" during self-refresh. When devices other than DRAM are attached, the WR signal is held "L". Take procedures such as applying an "H" signal to the CS. Figures 23.3 to 23.5 show bus timings during DRAM access.

Page 362 884fo6002,13.naJ13.1.veR 1310-4300B90JER 23. DRAMC)T38/C23M,38/C23M(puorG38/C23M A9(A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10 A0(A22) (A22) A8 A7 A6 A5 A4 A3 A2 A1 (1) In 8-bit Bus Mode Address used for 512K-byte and 1M-byte DRAM area Address used for 2M-byte and 4M-byte DRAM area Address used for 8M-byte DRAM area MA1MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 A9(A20) A18 A17 A16 A15 A14 A13 A12 A11 A10 A0(A22) A8 A7 A6 A5 A4 A3 A2 A1 A19 A19 A20A21 A9A18 A17 A16 A15 A14 A13 A12 A11 A10 A0(A22) A8 A7 A6 A5 A4 A3 A2 A1 A19 A21A22 A20 (A9)(A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10 (A0)(A22) (A20) A8 A7 A6 A5 A4 A3 A2 A1 (2) In 16-bit Bus Mode (A9)(A20) (A19) (A18) (A17) (A16) (A15) (A14) (A13) (A12) (A11) (A10)Pin Function MA1MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 (A9)(A20) A18 A17 A16 A15 A14 A13 A12 A11 A10 (A0)(A22) A8 A7 A6 A5 A4 A3 A2 A1 A19 A9A20 (A9)A18 A17 A16 A15 A14 A13 A12 A11 A10 (A0)A8 A7 A6 A5 A4 A3 A2 A1 Row Address A19 A9A21 A20 A22 ( ): disabled bits, :bits which output addresses changed by data bus width and the DRAM area –: indetermimate NOTES: 1. The above applies when using a 4Mx1 or 4Mx4 memory configuration. When using a 4Mx16 configuration, implement the following combinations: For row addresses, MA0 to MA12; for column addresses, MA2 to MA8, MA11 and MA12. Or for row addresses, MA1 to MA12; for column addresses, MA2 to MA9, MA11 and MA12. (A8) MA0 (A8) MA0 Row Address Row Address Pin Function Row Address Row Address Row Address Column Address Column Address Column Address Column Address Column Address Column Address Address used for 4M-byte and 8M-byte(1) DRAM area Address used for 512K-byte DRAM area Address used for 1M-byte and 2M-byte DRAM area Figure 23.2 Multiplexed Address Output Pattern

Page 363 884fo6002,13.naJ13.1.veR 1310-4300B90JER 23. DRAMC)T38/C23M,38/C23M(puorG38/C23M BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 (EDO mode) BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 'H' (1) Read cycle (WT bit = 0 with 2 wait states) (2) Write cycle (WT bit = 0) Row address Row address Column address 1 Column address 2 Column address 3 Column address 1 Column address 2 Column address 3 NOTES: 1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data. NOTES: 1. With an 8-bit data bus, only CASL outputs data enabled to read. CASH outputs an indeterminate data. Figure 23.3 Bus Timing during DRAM Access (1)

Page 364 884fo6002,13.naJ13.1.veR 1310-4300B90JER 23. DRAMC)T38/C23M,38/C23M(puorG38/C23M BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 (EDO mode) BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 (1) Read cycle (WT bit = 1 with 1 wait state) (2) Write cycle (WT bit = 1) Row address Row address 'H' Column address 1 Column address 2 Column address 3 Column address 4 Column address 1 Column address 2 Column address 3 Column address 4 NOTES: 1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data. NOTES: 1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data. Figure 23.4 Bus Timing during DRAM Access (2)

Page 365 884fo6002,13.naJ13.1.veR 1310-4300B90JER 23. DRAMC)T38/C23M,38/C23M(puorG38/C23M BCLK RAS CASH CASL BCLK RAS "H" DW CASH CASL "H" DW (1) CAS-before-RAS refresh cycle (1) Self-Refresh cycle NOTES: 1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data. NOTES: 1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data. Figure 23.5 Bus Timing during DRAM Access (3)

Page 366 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M 24. Programmable I/O Ports 87 programmable I/O ports from P0 to P10 (excluding P85) are available in the 100-pin package and 123 programmable I/O ports from P0 to P15 (excluding P85) are in the 144-pin package. The direction registers determine each port status, input or output. The pull-up control registers determine whether the ports, divided into groups of four ports, are pulled up or not. P8 5 is an input port and no pull-up for this port is allowed. The P8_5 bit in the P8 register indicates an NMI input level since P85 shares pins with NMI. Figures 24.1 to 24.4 show programmable I/O port configurations. Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus control pin. To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each function. Refer to 7. Bus when used as the bus control pin. The registers, described below, are associated with the programmable I/O ports.

24.1 Port Pi Direction Register (PDi Register, i=0 to 15)

Figure 24.5 shows the PDi register. The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register corresponds to a port. In memory expansion and microprocessor mode, pins being used as bus control pins (A0 to A22, A23, D0 to D 15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE, RD/DW, BCLK/ALE/CLK OUT , HLDA/ALE, HOLD, ALE/RAS, and RDY) cannot be controlled by the PDi register. No bits controlling P85 are provided in the direction registers .

24.2 Port Pi Register (Pi Register, i=0 to 15)

Figure 24.6 shows the Pi register. The Pi register writes and reads data to communicate with external devices. The Pi register consists of a port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port. In memory expansion and microprocessor mode, pins being used as bus control pins (A0 to A22, A23, D0 to D 15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE, RD/DW, BCLK/ALE/CLK OUT , HLDA/ALE, HOLD, ALE/RAS, and RDY) cannot be controlled by the Pi register.

24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9)

Figures 24.7 to 24.11 show the PSj registers. The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a periph- eral function output (excluding DA0 and DA1.) Tables 24.3 to 24.12 list peripheral function output control settings for each pin. When multiple peripheral function outputs are assigned to a pin, set the PSLk (k=0 to 3) and PSC registers to select which function is used.

24.4 Function Select Register Bk (PSLk Register) (k=0 to 3)

Figures 24.12 and 24.13 show the PSL0 to PSL3 registers. When multiple peripheral function outputs are assigned to a pin, the PSL0 to PSL3 registers select which peripheral function output is used. Refer to 24.9 Analog Input and Other Peripheral Function Input for the PSL3_3 to PSL3_6 bits in the PSL3 register.

Page 367 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M

24.5 Function Select Register C (PSC Register)

Figure 24.14 show the PSC register. When multiple peripheral function outputs are assigned to a pin, the PSC register select which peripheral function output is used. Refer to 24.9 Analog Input and Other Peripheral Function Input for the PSC_7 bit in the PSC register.

24.6 Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)

Figures 24.15 to 24.16 show the PUR0 to PUR4 registers. The PUR0 to PUR4 registers select whether the ports, divided into groups of four ports, are pulled up or not. Ports with bits in the PUR0 to PUR4 registers set to "1" (pull-up) and the direction registers set to "0" (input mode) are pulled up. Set bits in the PUR0 and PUR1 registers which control P0 to P5, running as bus, to "0" (no pull-up) in memory expansion and microprocessor mode. P0, P1, P4 0 to P43 can be pulled up when they are used as input ports in memory expansion mode and microprocessor mode.

24.7 Port Control Register (PCR Register)

Figure 24.17 shows the PCR register. The PCR register selects either CMOS output or N-channel open drain output as the P1 output format. If the PCR0 bits is set to "1" (N-channel open drain output), N-channel open drain output is selected because the P-channel in the CMOS port is turned off. This is, however, not a perfect open drain. Therefore, the absolute maximum rating of the input voltage is from -0.3V to Vcc + 0.3V. If P1 is used as the data bus in memory expansion and microprocessor mode, set the PCR0 bit to "0" (CMOS output). If P1 is used as a port in memory expansion and microprocessor mode, the PCR0 bit determines the output format.

24.8 Input Function Select Register (IPS Register)

Figure 24.18 shows the IPS registers. The IPS0 to IPS1 and IPS3 bits in the IPS register and the IPSA_0 and IPSA_3 bits in the IPSA register select which pin is assigned the intelligent I/O or CAN input functions. Refer to 24.9 Analog Input and Other Peripheral Function Input for the IPS2 bit.

24.9 Analog Input and Other Peripheral Function Input

The PSL3_3 to PSL3_6 bits in the PSL3 register, the PSC_7 bit in the PSC register and the IPS2 bit in the IPS register each separate analog I/O ports from other peripheral functions. Setting the corresponding bit to "1" (analog I/O) to use the analog I/O port (DA0, DA1, ANEX0, ANEX1, AN 4 to AN7 or AN150 to AN157) prevents an intermediate potential from being impressed to other peripheral functions. The impressed inter- mediate potential may cause increase in power consumption. Set the corresponding bit to "0" (except analog I/O) when analog I/O is not used. All peripheral function inputs except the analog I/O port are available when the corresponding bit is set to "0". These inputs are indeterminate when the bit is set to "1". When the PSC_7 bit is set to "1", key input interrupt request remains unchanged regardless of KI0 to KI3 pin input level change.

Page 368 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.1 Programmable I/O Ports (1) Direction Register Port Latch Input to each Peripheral Function Analog Signal Select Pull-Up Data Bus A B C P00 to P07 P20 to P27 P30 to P37 P40 to P47 P50 to P52 P54 P55 P56 P57 P83, P84 P86 P87 P100 to P103 P104 to P107 P114 P144 to P146 P152, P153 P156, P157 Option Port (A) Hysteresis Circuit (B) Peripheral Function Input Circuit (C) Analog I/F (Note 1) NOTES: 1. These ports are provided in the 144-pin package only. : Available, : Not available Programmable I/O Ports

Page 369 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.2 Programmable I/O Ports (2) P10 to P14 Option Port (A) Hysteresis Circuit (B) Peripheral Function Input P15 to P17 Direction Register Port Latch Input to each Peripheral Function Select Pull-Up Data Bus A B PCR Register : Available, : Not available Programmable I/O Ports with the Port Control Register Port : P72, P73, P74, P75, P80, P81 Direction Register Port Latch Input to each Peripheral Function Select Pull-up RESET NMI INV05 INV02 Data Bus Output from each Peripheral Function PS1 and PS2 Registers R T Programmable I/O Ports with the Function Select Register QD INV03 Write Signal to INV03 Value written to INV03

Page 370 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.3 Programmable I/O Ports (3) A B C P53 P60 to P67 P82 P90 to P92 P93 to P96 P111, P112 P113 P120 P135, P136 P121, P122 P123 to P127 P130 to P134 P137 P140, P141 P150, P151 P154, P155 Option Port (A) Hysteresis Circuit (B) Peripheral Function Input Circuit (C) Analog I/F P70, P71 P76, P77 P97 P110 P142, P143 Circuit (D) Direction Register Port Latch Input to each Peripheral Function Analog Signal Select Pull-Up Data Bus PS0 to PS9 Register NOTES: 1. P7 0 and P71 are ports for the N-channel open drain output. 2. These ports are provided in the 144-pin package only. D Output from each Peripheral Function (Note 1) (Note 2) : Available, : Not available Programmable I/O Ports with the Function Select Register

Page 372 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.6 P0 to P15 Registers NOTES: 1. In memory expansion and microprocessor mode, the direction register of pins being used as bus control pins (A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/CLK OUT , HLDA/ALE, HOLD, ALE/RAS, and RDY) cannot be changed. 2. The P11 to P15 registers are provided in the 144-pin package only. 3. P7 0 and P71 are ports for the N-channel open drain output. The pins go into a high-impedance state when P70 and P71 output a high-level signal ("H"). 4. The P85 bit is for read only. 5. Nothing is assigned to the P11_5 to P11_7 bits in the P11 register and the P14_7 bit in the P14 register. If write, set these bits to "0". When read, their contents are indeterminate. Function Port Pi Register (i=0 to 15)(1, 2) Bit NameBit Symbol Symbol Address After Reset P0 to P5 03E0 16, 03E116, 03E416, 03E516, 03E816, 03E916 Indeterminate P6 to P10 03C0 16, 03C116(3), 03C416(4), 03C516, 03C816 Indeterminate P11 to P15 03C9 16(5), 03CC16, 03CD16, 03D016(5), 03D116 Indeterminate RW Pi_0 Pi_1 Pi_2 Port Pi

0 Register

Pi_3 Pi_4 Pi_5 Pi_7 Pi_6 Port Pi

1 Register

Pin levels can be read by reading bits corresponding to programmable ports in input mode. Pin levels can be controlled by writing to bits corresponding to programmable ports in output mode. 0 : "L" level 1 : "H" level b7 b6 b5 b4 b3 b2 b1 b0

Page 373 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.7 PS0 Register and PS1 Register Function Function Select Register A0 Bit NameBit Symbol Symbol Address After Reset PS0 03B0 16 00 16 RW PS0_0 PS0_1 Port P60 Output Function Select Bit PS0_3 PS0_4 PS0_5 PS0_7 0 : I/O port 1 : RTS0 0 : I/O port 1 : CLK0 output 0 : I/O port 1 : TXD0/SDA0 output 0 : I/O port 1 : Selected by the PSL0_4 bit 0 : I/O port 1 : CLK1 output 0 : I/O port 1 : TXD1/SDA1 output Port P61 Output Function Select Bit Port P63 Output Function Select Bit Port P64 Output Function Select Bit Port P65 Output Function Select Bit Port P67 Output Function Select Bit PS0_2 Port P62 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL0_2 bit PS0_6 Port P66 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL0_6 bit RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Function Select Register A1 Bit NameBit Symbol Symbol Address After Reset PS1 03B1 16 00 16 RW PS1_0 PS1_1 Port P70 Output Function Select Bit PS1_3 PS1_4 PS1_5 PS1_7 0 : I/O port 1 : Selected by the PSL1_0 bit 0 : I/O port 1 : OUTC01/ISCLK0 output Port P71 Output Function Select Bit Port P73 Output Function Select Bit Port P74 Output Function Select Bit Port P75 Output Function Select Bit Port P77 Output Function Select Bit PS1_6 Port P76 Output Function Select Bit PS1_2 Port P72 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL1_1 bit 0 : I/O port 1 : Selected by the PSL1_2 bit 0 : I/O port 1 : Selected by the PSL1_3 bit 0 : I/O port 1 : Selected by the PSL1_4 bit 0 : I/O port 1 : Selected by the PSL1_5 bit 0 : I/O port 1 : Selected by the PSL1_6 bit RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0

Page 374 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.8 PS2 Register and PS3 Register Function Function Select Register A2 Bit NameBit Symbol Symbol Address After Reset PS2 03B4 16 00X0 0000 2 PS2_0 PS2_1 Port P80 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL2_0 bit Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Port P81 Output Function Select Bit PS2_2 (b4 - b3) (b5) (b7 - b6) Port P82 Output Function Select Bit Reserved Bit Set to "0" Reserved Bit Set to "0" RW RW RW RW RW RW 0 : I/O port 1 : Selected by the PSL2_1 bit 0 : I/O port 1 : Selected by the PSL2_2 bit b7 b6 b5 b4 b3 b2 b1 b0 0000 Function Function Select Register A3(1) Bit NameBit Symbol Symbol Address After Reset PS3 03B5 16 00 16 PS3_0 PS3_1 Port P90 Output Function Select Bit PS3_3 PS3_4 PS3_5 PS3_7 0 : I/O port 1 : CLK3 output 0 : I/O port 1 : RTS3 0 : I/O port 1 : CLK4 output Port P91 Output Function Select Bit Port P93 Output Function Select Bit Port P94 Output Function Select Bit Port P95 Output Function Select Bit Port P97 Output Function Select Bit PS3_6 0 : I/O port 1 : TXD4/SDA4 output Port P96 Output Function Select Bit PS3_2 Port P92 Output Function Select Bit 0 : I/O port 1 : RTS4 0 : I/O port 1 : Selected by the PSL3_1 bit 0 : I/O port 1 : Selected by the PSL3_2 bit 0 : I/O port 1 : Selected by the PSL3_7 bit NOTES: 1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 register. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW

Page 375 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.9 PS5 Register and PS6 Register Function Function Select Register A5(1) Bit NameBit Symbol Symbol Address After Reset PS5 03B9 16 XXX0 0000 2 RW PS5_0 PS5_1 Port P110 Output Function Select Bit 0 : I/O port 1 : OUTC10/ ISTXD1/BE1OUT 0 : I/O port 1 : OUTC1 1/ ISCLK1 output NOTES: 1. The PS5 register is provided in the 144-pin package only. Port P111 Output Function Select Bit PS5_2 Port P112 Output Function Select Bit 0 : I/O port 1 : OUTC12 PS5_3 (b4) (b7 - b5) Port P113 Output Function Select Bit 0 : I/O port 1 : OUTC1 Reserved Bit Set to "0" Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Select Register A6(1) Bit NameBit Symbol Symbol Address After Reset PS6 03BC 16 00 16 RW PS6_0 PS6_1 Port P120 Output Function Select Bit PS6_3 PS6_4 PS6_5 PS6_7 0 : I/O port 1 : OUTC30/ISTxD3 0 : I/O port 1 : OUTC31/ISCLK3 output 0 : I/O port 1 : OUTC33 0 : I/O port 1 : OUTC3 0 : I/O port 1 : OUTC3 0 : I/O port 1 : OUTC3 Port P121 Output Function Select Bit Port P123 Output Function Select Bit Port P124 Output Function Select Bit Port P125 Output Function Select Bit Port P127 Output Function Select Bit PS6_6 0 : I/O port 1 : OUTC36 Port P126 Output Function Select Bit PS6_2 Port P122 Output Function Select Bit 0 : I/O port 1 : OUTC32 NOTES: 1. The PS6 register is provided in the 144-pin package only. RW RW RW RW RW RW RW RW Function b7 b6 b5 b4 b3 b2 b1 b0

Page 376 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.10 PS7 Register and PS8 Register Function Function Select Register A7(1) Bit NameBit Symbol Symbol Address After Reset PS7 03BD 16 00 16 PS7_0 PS7_1 Port P130 Output Function Select Bit PS7_3 PS7_4 PS7_5 PS7_7 0 : I/O port 1 : OUTC24 0 : I/O port 1 : OUTC2 0 : I/O port 1 : OUTC2 0 : I/O port 1 : OUTC20/ISTXD2/IEOUT 0 : I/O port 1 : OUTC22 0 : I/O port 1 : OUTC2 Port P131 Output Function Select Bit Port P133 Output Function Select Bit Port P134 Output Function Select Bit Port P135 Output Function Select Bit Port P137 Output Function Select Bit PS7_6 0 : I/O port 1 : OUTC21/ISCLK2 output Port P136 Output Function Select Bit PS7_2 Port P132 Output Function Select Bit 0 : I/O port 1 : OUTC26 NOTES: 1. The PS7 register is provided in the 144-pin package only. RW RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Function Select Register A8(1) Bit NameBit Symbol Symbol Address After Reset PS8 03A0 16 X000 0000 2 PS8_0 PS8_1 Port P140 Output Function Select Bit 0 : I/O port 1 : OUTC14 0 : I/O port 1 : OUTC1 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Port P14

1 Output

PS8_2 Port P142 Output Function Select Bit 0 : I/O port 1 : OUTC16 0 : I/O port 1 : OUTC1 PS8_3 (b6 - b4) (b7) Port P143 Output Function Select Bit 00 0 Reserved Bit Set to "0" NOTES: 1: The PS8 register is provided in the 144-pin package only. RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0

Page 377 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Function Function Select Register A9(1) Bit NameBit Symbol Symbol Address After Reset PS9 03A1 16 00 16 PS9_0 PS9_1 Port P150 Output Function Select Bit PS9_4 PS9_5 (b3 - b2) (b7 - b6) 0 : I/O port 1 : OUTC00/ ISTXD0/BE0OUT 0 : I/O port 1 : OUTC0 1/ ISCLK0 output 0 : I/O port 1 : OUTC04 0 : I/O port 1 : OUTC0 Port P151 Output Function Select Bit Port P154 Output Function Select Bit Port P155 Output Function Select Bit Reserved Bit Set to "0" Reserved Bit Set to "0" NOTES: 1. The PS9 register is provided in the 144-pin package only. RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 000 0 Figure 24.11 PS9 Register

Page 378 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.12 PSL0 Register and PSL1 Register Function Function Select Register B0 Bit NameBit Symbol Symbol Address After Reset PSL0 03B2 16 00 16 PSL0_4 Port P64 Output Peripheral Function Select Bit 0 : RTS1 1 : OUTC21/ISCLK2 output PSL0_6 Port P66 Output Peripheral Function Select Bit 0 : SCL1 output 1 : STXD1 PSL0_2 (b1 - b0) (b3) (b5) (b7) Port P62 Output Peripheral Function Select Bit 0 : SCL0 1 : ST XD0 Reserved Bit Set to "0" Reserved bit Set to "0" Reserved Bit Set to "0" Reserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 000 0 0 RW RW RW RW RW RW RW RW Function Function Select Register B1 Bit NameBit Symbol Symbol Address After Reset PSL1 03B3 16 00 16 PSL1_0 PSL1_1 Port P70 Output Peripheral Function Select Bit PSL1_3 PSL1_4 PSL1_5 0 : Selected by the PSC_0 bit 1 : TA0OUT output 0 : Selected by the PSC_1 bit 1 : STXD2 0 : Selected by the PSC_3 bit 1 : V 0 : Selected by the PSC_4 bit 1 : W 0 : W 1 : OUTC1 2 Port P71 Output Peripheral Function Select Bit Port P73 Output Peripheral Function Select Bit Port P74 Output Peripheral Function Select Bit Port P75 Output Peripheral Function Select Bit PSL1_6 (b7) 0 : Selected by the PSC_6 bit 1 : TA3OUT output Port P76 Output Peripheral Function Select Bit PSL1_2 Port P72 Output Peripheral Function Select Bit 0 : Selected by the PSC_2 bit 1 : TA1OUT output Reserved Bit Set to "0" RW RW RW RW RW RW RW RW RW NOTES: 1. Set the corresponding PSC_i bit in the PSC register to "0" when setting the PSL1_i bit (i=0 to 4, 6) to "1". b7 b6 b5 b4 b3 b2 b1 b0

Page 379 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.13 PSL2 Register and PSL3 Register Function Function Select Register B2 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit NameBit Symbol Symbol Address After Reset PSL2 03B6 16 00X0 0000 2 PSL2_0 PSL2_1 Port P80 Output Peripheral Function Select Bit 0 : TA4OUT output 1 : U Port P81 Output Peripheral Function Select Bit PSL2_2 (b4 - b3) (b5) (b7 - b6) 0 : OUTC3 2 1 : CANOUT Port P82 Output Peripheral Function Select Bit RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 0 : U 1 : OUTC30/ISTxD3 Reserved Bit Set to "0" Reserved Bit Set to "0" 0 00 0 Function Function Select Register B3 Bit NameBit Symbol Symbol Address After Reset PSL3 03B7 16 00 16 PSL3_1 (b0) PSL3_3 PSL3_4 PSL3_5 PSL3_7 0 : SCL3 output 1 : STxD3 0 : Other than DA0 1 : DA0(1) 0 : Other than ANEX0 1 : ANEX0 (1) 0 : SCL4 output 1 : STxD4 Port P91 Output Peripheral Function Select Bit Port P93 Output Peripheral Function Select Bit Port P94 Output Peripheral Function Select Bit Port P95 Output Peripheral Function Select Bit Port P97 Output Peripheral Function Select Bit PSL3_6 Port P96 Output Peripheral Function Select Bit PSL3_2 Port P92 Output Peripheral Function Select Bit 0 : TxD3/SDA3 output 1 : OUTC20/ISTxD2/IEOUT RW RW RW RW RW RW RW RW RW 0 : Other than DA1 1 : DA1 (1) 0 : Other than ANEX1 1 : ANEX1 (1) NOTES: 1. Although DA0, DA1, ANEX0 and ANEX1 can be used when this bit is set to "0", power consumption may increase. b7 b6 b5 b4 b3 b2 b1 b0 Reserved Bit Set to "0"

Page 380 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.14 PSC Register Function Function Select Register C Bit NameBit Symbol Symbol Address After Reset PSC 03AF 16 00X0 0000 2 PSC_0 PSC_3 PSC_4 (b5) PSC_7 0 : TxD2/SDA2 output 1 : OUTC20/ISTXD2/IEOUT 0 : RTS2 1 : OUTC1 0/ISTxD1/BE1OUT 0 : TA2OUT output 1 : OUTC11/ISCLK1 output 0 : P104 to P107 or KI0 to KI3 1 : AN4 to AN7(1) Port P70 Output Peripheral Function Select Bit Port P73 Output Peripheral Function Select Bit Port P74 Output Peripheral Function Select Bit Key Input Interrupt Validity Select Bit PSC_6 0 : OUTC00/ISTXD0/BE0OUT 1 : CANOUT Port P76 Output Peripheral Function Select Bit PSC_2 Port P72 Output Peripheral Function Select Bit 0 : CLK2 output 1 : V Nothing is assigned. When write, set to "0". When read, its content is indeterminate. PSC_1 Port P71 Output Peripheral Function Select Bit 0 : SCL2 output 1 : OUTC2 RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Set the ILVL2 to ILVL0 bits in the KUPIC register to "0002" (interrupt disabled) when changing the PSC_7 bit. Although the AN4 to AN7 pins can be used when this bit is set to "0", power consumption may increase.

Page 381 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.15 PUR0 Register, PUR1 Register and PUR2 Register Function Pull-Up Control Register 0(1) Bit NameBit Symbol Symbol Address After Reset PUR0 03F0 16 00 16 RW PU00 PU01 PU02 P00 to P03 Pull-Up PU03 PU04 PU05 PU07 PU06 P04 to P07 Pull-Up P10 to P13 Pull-Up P14 to P17 Pull-Up P20 to P23 Pull-Up P24 to P27 Pull-Up P30 to P33 Pull-Up P34 to P37 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up NOTES: 1. Set each bit in the PUR0 register to "0" since P0 to P5 operate as the address bus in the memory expansion mode and microprocessor mode. Pull-up or no pull-up setting can be selected when using these ports as I/O ports. RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Pull-Up Control Register 1(1) Bit NameBit Symbol Symbol Address After Reset PUR1 03F1 16 XXXX 0000 2 RW PU10 PU11 PU12 P40 to P43 Pull-Up PU13 (b7 - b4) P44 to P47 Pull-Up P50 to P53 Pull-Up P54 to P57 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up NOTES: 1. Set each bit in the PUR1 register to "0" since P0 to P5 operate as the address bus in the memory expansion mode and microprocessor mode. Pull-up or no pull-up setting can be selected when using these ports as I/O ports. RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Function Pull-Up Control Register 2 Bit NameBit Symbol Symbol Address After Reset PUR2 03DA 16 00 16 RW PU20 PU21 PU22 P60 to P63 Pull-Up PU23 PU24 PU25 PU27 PU26 P64 to P67 Pull-Up P72 to P73 Pull-Up(1) P74 to P77 Pull-Up P80 to P83 Pull-Up P84 to P87 Pull-Up(2) P90 to P93 Pull-Up P94 to P97 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up NOTES: 1. P70 and P71 cannot be pulled up. 2. P85 cannot be pulled up. RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0

Page 382 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Figure 24.16 PUR3 Register and PUR4 Register Function Pull-Up Control Register 3 Bit NameBit Symbol Symbol Address After Reset PUR3 03DB 16 00 16 RW PU30 PU31 PU32 P100 to P103 Pull-Up PU33 PU34 PU35 PU37 PU36 P104 to P107 Pull-Up P110 to P113 Pull-Up P114 Pull-Up P120 to P123 Pull-Up P124 to P127 Pull-Up P130 to P133 Pull-Up P134 to P137 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up RW RW RW RW RW RW RW RW <144-pin package> b7 b6 b5 b4 b3 b2 b1 b0 Function Pull-Up Control Register 3 Bit NameBit Symbol Symbol Address After Reset PUR3 03DB 16 00 16 RW PU30 P10 0 to P103 Pull-Up PU31 (b7 - b2) P104 to P107 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up RW RW <100-pin package> RWReserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 00000 0 Function Pull-Up Control Register 4(1) Bit NameBit Symbol Symbol Address After Reset PUR4 03DC 16 XXXX 0000 2 RW PU40 PU41 PU42 P140 to P143 Pull-Up PU43 (b7 - b4) P144 to P147 Pull-Up P150 to P153 Pull-Up P154 to P157 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up NOTES: 1. Set the PUR4 register to "0016" in the 100-pin package. RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate.

Page 384 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Table 24.1 Unassigned Pin Settings in Single-chip Mode Pin Name Setting P0 to P15 Enter input mode and connect each pin to V SS via a resistor (pull-down); (excluding P85)(1,2,3.4,6)or enter output mode and leave pins open XOUT (5) Leave pin open NMI(P85) Connect pin to V CC via a resistor (pull-up) AV CC Connect pin to VCC AV SS , VREF , BYTE Connect pins to VSS NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. If the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset. While the port is in input mode, voltage level on the pins is indeterminate and power consumption may increase. Direction register settings may be changed by noise or failure caused by noise. Configure direction register settings regulary to increase the reliability of the program. 3. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm). 4. P7 0 and P71 must output low-level ("L") signals if they are in output mode. They are ports for the N- channel open drain outputs. 5. When the external clock is applied to the XIN pin, set the pin as written above. 6. In the 100-pin package, set "FF16" in the following addresses, in addition to the above settings: Addresses 0003CB16, 0003CE16, 0003CF16, 0003D216, 0003D316 Table 24.2 Unassigned Pin Setting in Memory Expansion Mode and Microprocessor Mode Pin Name Setting P6 to P15 Enter input mode and connect each pin to V SS via a resistor (pull-down); (excluding P85)(1,2,3.4,6)or enter output mode and leave pins open BHE, ALE, HLDA, Leave pin open XOUT (5), BCLK NMI(P85), RDY, HOLD Connect pin to VCC via a resistor (pull-up) AV CC Connect pin to VCC AV SS , VREF Connect pins to VSS NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. If the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset. While the port is in input mode, voltage level on the pins is indeterminate and power consumption may increase. Direction register settings may be changed by noise or failure caused by noise. Configure direction register settings regulary to increase the reliability of the program. 3. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm). 4. P7 0 and P71 must output low-level ("L") signals if they are in output mode. They are ports for the N- channel open drain outputs. 5. When the external clock is applied to the XIN pin, set the pin as written above. 6. In the 100-pin package, set "FF16" in the following addresses, in addition to the above settings: Addresses 0003CB16, 0003CE16, 0003CF16, 0003D216, 0003D316

Page 385 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M P0 to P15(1) (except for P85) (Input mode)··

(Input mode) (Output mode) NMI(P85) XOUT AV CC BYTE AV SS VREF Microcomputer VCC VSS In single-chip mode P6 to P15(1) (except for P85) (Input mode)··
(Input mode) (Output mode) XOUT AV CC AV SS VREF Open Microcomputer VCC VSS In memory expansion mode or microprocessor mode HOLD RDY ALE BCLK BHE HLDA Open Open Open
··
·· NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. M32C/83T cannot be used in memory expansion mode and microprocessor mode. NMI(P8 Figure 24.19 Unassigned Pin Handling

Page 386 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Table 24.3 Port P6 Peripheral Function Output Control PS0 Register PSL0 Register Bit 0 1: RTS0 Bit 1 0: P61/CLK0 (input) Set to "0" 1: CLK0 (output) Bit 2 0: P62/RxD0/SCL0 (input) 0: SCL0 (output) 1: Selected by the PSL0 register 1: STxD0 Bit 3 0: P63/SRxD0/SDA0 (input) Set to "0" 1: TxD0/SDA0 (output) Bit 4 0: P64/CTS1/SS1/ISCLK2 (input) 0: RTS1 1: Selected by the PSL0 register 1: OUT21/ISCLK2(output) Bit 5 0: P65/CLK1(input) Set to "0" 1: CLK1(output) Bit 6 0: P66/RxD1/SCL1 (input) 0: SCL1(output) 1: Selected by the PSL0 register 1: STxD1 Bit 7 0: P67/SRxD1/SDA1 (input) Set to "0" 1: TxD1/SDA1 (output) Table 24.4 Port P7 Peripheral Function Output Control PS1 Register PSL1 Register PSC Register (1) Bit 0 0: P70/SRxD2/TA0OUT (input)/ SDA2(input) 0: Selected by the PSC register 0: TxD2/SDA2(output) 1: Selected by the PSL1 register 1: TA0 OUT (output) 1: OUTC2 0/ISTxD2/IEOUT Bit 1 0: P71/TB5IN/TA0IN/RxD2/ISRxD2/IEIN/ 0: Selected by the PSC register 0: SCL2(output) SCL2(input) 1: Selected by the PSL1 register 1: STxD2 1: OUTC2 2 Bit 2 0: P72/TA1OUT (input)/CLK2(input) 0: Selected by the PSC register 0: CLK2(output) 1: Selected by the PSL1 register 1: TA1 OUT (output) 1: V Bit 3 0: P73/TA1IN/CTS2/SS2 0: Selected by the PSC register 0: RTS2 1: Selected by the PSL1 register 1: V 1: OUTC1 0/ISTxD1/BE1OUT Bit 4 0: P74/INPC11/ISCLK1(input)/TA2OUT (input) 0: Selected by the PSC register 0: TA2OUT (output) 1: Selected by the PSL1 register 1: W 1: OUTC1 1/ISCLK1(output) Bit 5 0: P75/TA2IN/INPC12/ISRxD1/BE1IN ___ 0: W Set to "0" 1: Selected by the PSL1 register 1: OUTC1 2 Bit 6 0: P76/INPC00/TA3OUT (input) 0: Selected by the PSC register 0: OUTC0 0/ISTxD0/BE0OUT 1: Selected by the PSL1 register 1: TA3 OUT (output) 1: CAN0 OUT Bit 7 0: P77/TA3IN/CAN IN/ISCLK0(input)/INPC01 Set to "0" 0: P10 4 to P107 or KI0 to KI3 1: OUTC01/ISCLK0(output) 1: AN4 to AN 7 (No relation to P77) NOTES: 1. Set the corresponding PSC_i bit to "0" when setting the PSL1_i bit (i=0 to 4, 6) to "1".

Page 387 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Table 24.5 Port P8 Peripheral Function Output Control PS2 Register PSL2 Register Bit 0 0: P8 0/INPC02/ISRxD0/BE0OUT /TA4OUT (input) 0: TA4 OUT (output) 1: Selected by the PSL2 register 1: U Bit 1 0: P8 1/TA4IN ___ 0: U 1: Selected by the PSL2 register 1: OUTC3 2/ISTxD3 Bit 2 0: P82/INT0/ISRxD3 0: OUTC3 2 1: Selected by the PSL2 register 1: CAN OUT Bit 3 to 7 Set to "0" Table 24.6 Port P9 Peripheral Function Output Control PS3 Register PSL3 Register Bit 0 0: P9 0/TB0IN/CLK3(input) Set to "0" 1: CLK3(output) Bit 1 0: P9 1/TB1IN/RxD3/ISRxD2/SCL3(input)/IEIN 0: SCL3(output) 1: Selected by the PSL3 register 1: STxD3 Bit 2 0: P9 2/TB2IN/SRxD3/SDA3(input) 0: TxD3/SDA3(output) 1: Selected by the PSL3 register 1: OUTC2 0/ISTxD2/IEIN Bit 3 0: P93/TB3IN/CTS3/SS3/DA0(output) 0: Except DA0 1: RTS3 1: DA0 Bit 4 0: P94/TB4IN/CTS4/SS4/DA1(output) 0: Except DA1 1: RTS4 1: DA1 Bit 5 0: P9 5/ANEX0/CLK4(input) 0: Except ANEX0 1: CLK4(output) 1: ANEX0 Bit 6 0: P9 6/SRxD4/ANEX1/SDA4(input) 0: Except ANEX1 1: TxD4/SDA4(output) 1: ANEX1 Bit 7 0: P97/RxD4/ADTRG /SCL4(input) 0: SCL4(output ) 1: Selected by the PSL3 register 1: STxD4 Table 24.7 Port P10 Peripheral Function Output Control PSC Register Bit 7 0: P104 to P107 or KI0 to KI3 1: AN4 to AN7

Page 388 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Table 24.8 Port P11 Peripheral Function Output Control PS5 Register Bit 0 0: P11 0 1: OUTC10/ISTxD1/BE1OUT Bit 1 0: P111/INPC11/ISCLK1(input) 1: OUTC11/ISCLK1(output) Bit 2 0: P11 2/INPC12/ISRxD1/BE1 IN 1: OUTC12 Bit 3 0: P11 3 1: OUTC13 Bit 4 to 7 Set to "0" Table 24.9 Port P12 Peripheral Function Output Control PS6 Register Bit 0 0: P12 0 1: OUTC30/ISTxD3 Bit 1 0: P12 1/ISCLK3(input) 1: OUTC31/ISCLK3(output) Bit 2 0: P12 2/ISRxD3 1: OUTC32 Bit 3 0: P12 3 1: OUTC33 Bit 4 0: P12 4 1: OUTC34 Bit 5 0: P12 5 1: OUTC35 Bit 6 0: P12 6 1: OUTC36 Bit 7 0: P12 7 1: OUTC37

Page 389 884fo6002,13.naJ13.1.veR 1310-4300B90JER 24. Programmable I/O Port)T38/C23M,38/C23M(puorG38/C23M Table 24.10 Port P13 Peripheral Function Output Control PS7 Register Bit 0 0: P13 0 1: OUTC24 Bit 1 0: P13 1 1: OUTC25 Bit 2 0: P13 2 1: OUTC26 Bit 3 0: P13 3 1: OUTC23 Bit 4 0: P13 4 1: OUTC20/ISTxD2/IEOUT Bit 5 0: P13 5/ISRxD2/IEIN 1: OUTC22 Bit 6 0: P13 6/ISCLK2(input) 1: OUTC21/ISCLK2(output) Bit 7 0: P13 7 1: OUTC27 Table 24.11 Port P14 Peripheral Function Output Control PS8 Register Bit 0 0: P14 0 1: OUTC14 Bit 1 0: P14 1 1: OUTC15 Bit 2 0: P14 2/INPC16 1: OUTC16 Bit 3 0: P14 3/INPC17 1: OUTC17 Bit 4 to 7 Set to " 0" Table 24.12 Port P15 Peripheral Function Output Control PS9 Register Bit 0 0: P15 0/INPC00/AN150 1: OUTC00/ISTxD0/BE0OUT Bit 1 0: P15 1/INPC01/AN151/ISCLK0(input) 1: OUTC01/ISCLK0(output) Bit 2 to 3 Set to "0" Bit 4 0: P15 4/INPC04/AN154 1: OUTC04 Bit 4 0: P15 5/INPC05/AN155 1: OUTC05 Bit 6 to 7 Set to " 0"

Page 390 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M 25. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM version. In the flash memory version, rewrite operations to the flash memory can be performed in three modes: CPU rewrite mode, standard serial I/O mode and parallel I/O mode. Table 25.1 lists specifications of the flash memory version. See Tables 1.1 and 1.2 for the items not listed in Table 25.1. Table 25.1 Flash Memory Version Specifications Item Specification Supply Voltage 4.2V to 5.5V (f(X IN) = 32MHz, no wait) 3.0V to 5.5V (f(XIN) = 20MHz, no wait) Program and Erase Voltage 4.2V to 5.5V (through VDC), 3.0V to 3.6V (not through VDC) CPU clock=12.5MHz (1 wait state), CPU clock=6.25MHz (no wait) Flash Memory Rewrite Mode 3 modes (CPU rewrite, standard serial I/O, parallel I/O) Erase Block User ROM Area See Figure 25.1 Boot ROM Area 1 block (8 Kbytes)(1) Program Method Per page (256 bytes) Erase Method All block erase, erase per block Program and Erase Control MethodSoftware commands control programming and erasing on the flash memory Protect Method The lock bit protects each block in the flash memory Number of Commands 8 commands Program and Erase Endurance 100 cycles (3) Data Retention 10 years ROM Code Protection Standard serial I/O mode and parallel I/O mode supported NOTES: 1. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before ship- ment. This space can be rewritten in parallel I/O mode only. Table 25.2 Flash Memory Rewrite Mode Overview yromeMhsalF edoMetirweR edoMetirweRUPCe doMO/IlaireSdradnatSe doMO/IlellaraP noitcnuFn oitucexednammocerawtfoS MORresuehtsetirwerUPCyb .aera lairesdetacidedA resuehtsetirwerremmargorp .aeraMOR :1edomO/IlairesdradnatS O/IlairessuonorhcnyskcolC :2edomO/IlairesdradnatS TRAU lellarapdetacidedA ehtsetirwerremmargorp resudnaaeraMORtoob .aeraMOR hcihwecapS ebnac nettirweR aeraMORresUa eraMORresUa eraMORresU aeraMORtooB gnitarepO edoM edompihc-elgniS edomnoisnapxeyromeM edomtooB edomtooBe domO/IlellaraP remmargorPe noNr emmargorplaireSr emmargorplellaraP

Page 391 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M User ROM Area Boot ROM Area NOTES: 1. The boot ROM area can be rewritten in parallel I/O mode only. (Refer to 25.5.1 Boot Mode) 2. When specifying a block, use the highest-order even address in the block to be specified.

8 KbytesFFE000 16

Block 3 : 32 Kbytes FF800016 Block 2 : 8 Kbytes FFA000 16 Block 1 : 8 Kbytes Block 0 : 16 KbytesFFC000 16 FFFFFF 16 FD0000 16 Block 5 : 64 Kbytes FC0000 16 Block 6 : 64 Kbytes FE0000 16 Block 4 : 64 Kbytes Block 8 : 64 Kbytes Block 9 : 64 Kbytes Block 7 : 64 Kbytes Block 10 : 64 Kbytes FB0000 16 FA0000 16 F9000016 F8000016

25.1 Memory Map

The flash memory contains a user ROM area, with space to store microcomputer operating programs in single-chip mode or memory expansion mode, and a separate 8-Kbyte boot ROM area. Figure 25.1 shows a block diagram of the flash memory. The user ROM area is divided into several blocks, each of which can be protected (locked) from program and erase. The user ROM area can be rewritten in CPU rewrite, standard serial I/O and parallel I/O modes. The boot ROM area is allocated in the same addresses as the user ROM area. It can only be rewritten in parallel I/O mode (refer to 25.5 Parallel I/O Mode). A program in the boot ROM area is executed after a hardware reset occurs while an "H" signal is applied to the CNV SS and P50 pins and an "L" signal is applied to the P55 pin (refer to 25.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs while an "L" signal is applied to the CNVSS pin. Consequently, the boot ROM area cannot be read. Figure 25.1 Flash Memory Block Diagram

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25.1.1 Boot Mode

The microcomputer enters boot mode when a hardware reset is performed while an "H" signal is applied to the CNVSS and P50 pins and an "L" signal is applied to the P55 pin. The program in the boot ROM area is executed. In boot mode, the FMR05 bit in the FMR0 register selects access to either the boot ROM area or the user ROM area. The rewrite control program for standard serial I/O mode (refer to 25.4 Standard Serial I/O Mode) is stored in the boot ROM area before shipment. The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase- write mode is written in the boot ROM area, the flash memory can be rewritten according to the system implemented.

25.2 Functions to Prevent the Flash Memory from Rewriting

The flash memory has the ROM code protect function for parallel I/O mode and the ID code verify function for standard I/O mode to prevent the flash memory from reading or rewriting.

25.2.1 ROM Code Protect Function

The ROM code protect function prevents the flash memory from reading and rewriting in parallel I/O mode. Figure 25.2 shows the ROMCP register. The ROMCP register is located in the user ROM area. The ROM code protect function is enabled when the ROMCP1 bit is set to "00 2". The ROM code protect function is disabled when the ROMCR bit is set to "002", regardless of the ROMCP1 bit setting. Therefore, set the ROMCR bit to "112" and the ROMCP1 bit to "002" when setting up the ROM code protect function. Once the ROM code protect function is enabled, the ROMCR bit cannot be changed in parallel I/O mode. Rewrite the ROMCR bit to "00 2" in standard serial I/O mode or CPU rewrite mode when disabling the ROM code protect function.

25.2.2 ID Code Verify Function

Use the ID code verify function in standard serial I/O mode. The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match. If the ID codes do not match, commands sent from the serial programmer are not accepted. However, if the four bytes of the reset vector are "FFFFFFFF 16", ID codes are not compared, and all commands are accepted. The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFFDF 16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and 0FFFFFB16. The flash memory must have a program with the ID codes set in these addresses.

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25.3 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer mounted on a board, without using a parallel or serial programmer. Write the rewrite control program to either the user ROM area or the boot ROM area, beforehand. No program in the flash memory can be executed in CPU rewrite mode. Therefore, transfer rewrite control program to an area other than flash memory (internal RAM, etc.), and execute. CPU rewrite mode can be entered when the microcomputer is in single-chip, memory expansion, and boot mode. Software commands, listed in Table 25.3, can be used in CPU rewrite mode. Refer to 25.3.3 Software Command for details of each command. Read or write commands and data from or to even addresses in the user ROM area, in 16-bit units. The 8 high-order bits (D15 to D8) are ignored when writing command codes. Table 25.3 Software Commands Software Command Page Program Clear Status Register Read Array Read Status Register X X X X First Bus Cycle Second Bus Cycle Third Bus Cycle xxFF16 xx7016 xx5016 xx4116 Write Write Write Write X SRDRead Write Lock Bit Program X xx7716Write BA xxD016Write Erase All Unlocked Block X xxA716Write X xxD016Write WA+2 WDWriteWA WD Block Erase X xx2016Write xxD016Write BA Read Lock Bit Status X xx7116Write BA D 6 Mode Address Mode Address Mode AddressData (D15 to D0) Data (D15 to D0) Data (D15 to D0) SRD: Data in the SRD register (D7 to D0) WA: Address to be written (Increment A7 to A0 by 2 from "0016" to "FE16".) WD: 16-bit write data BA: Highest-order block address (A 0 = 0) D 6: Lock bit (D6=1: unlock, D6=0: locked) X: Any even address in the user ROM area (A0 = 0) xx: 8 high-order bits of command code (ignored) Read

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25.3.1 Flash Memory Control Register 0 (FMR0 Register)

Figure 25.4 shows the FMR0 register. Function Flash Memory Control Register 0 Bit NameBit Symbol Symbol Address After Reset FMR0 0057 16 XX00 0001 2 Noting is assigned. When write, set to "0". When read, its content is indeterminate. RW RO RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 FMR00 FMR01 RY/BY Signal Status Bit FMR03 FMR05 (b4) (b7 - b6) 0 : BUSY (auto-writing, auto-erasing) 1 : READY (auto-write completed, auto-erase completed) 0 : Disables CPU rewrite mode 1 : Enables CPU rewrite mode By setting the bit to "1" just after setting it to "0", a flash memory access is interrupted to reset the flash memory control circuit 0: Access the boot ROM area 1: Access the user ROM area CPU Rewrite Mode Select Bit(1, 6) Flash Memory Reset Bit(5) User ROM Area Select Bit (Available in boot mode only) (2, 6) FMR02 Lock Bit Disable Bit(1, 3, 4)0 : Enables the lock bit 1 : Disables the lock bit Reserved Bit Set to"0" NOTES: 1. Set this bit to "1" immediately after setting it to "0". Do not generate an interrupt or a DMA transfer between setting the bit to "0" and setting it to "1". Write "0" to this bit when setting it to "0". 2. Set the FMR05 bit by program in a space other than the flash memory. 3. When the FMR01 bit is set to "0", the FMR02 bit is also set to "0" simultaneously. 4. The FMR02 bit can be set only when the FMR01 bit is set to "1". 5. When the FMR01 bit is set "0", set the FMR03 bit to "0". Access the FMR03 bit when the FMR01 bit is set to "1". 6. Set the FMR05 bit while applying "H" to the NMI pin. Figure 25.4 FMR0 Register

25.3.1.1 FMR00 Bit

The FMR00 bit indicates the write status machine (WSM) operation state during an auto write and auto erase operation. The FMR00 bit is set to "0" during an auto write or auto erase operation and is set to "1" when an auto write or auto erase operation is completed. The FMR00 bit changes while executing the page program, block erase, erase all unlocked block or lock bit program command. Determine whether the auto write or erase operation is completed by reading the FMR00 bit . The FMR00 bit is changed by the above commands only.

25.3.1.2 FMR01 Bit

Commands can be accepted when the FMR01 bit is set to "1" (CPU rewrite mode). To set the FMR01 bit to "1", set to "1" immediately after setting it to "0". To set the FMR01 bit to "0", set it to "0". CPU rewrite mode is entered by setting the FMR01 bit to "1" and programs in the flash memory cannot be executed. Execute an instruction written to this bit in a space (internal RAM, etc.) other than the flash memory. If a command for CPU rewrite mode is executed in boot mode, set the FMR05 bit to "1" (user ROM area access).

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25.3.1.3 FMR02 Bit

The lock bit set for each block can be disabled by setting the FMR02 bit to "1" (lock bit disabled). (Refer to 25.3.3 Data Protect Function.) The lock bit is enabled by setting the FMR02 bit to "0" (lock bit enabled). The FMR02 bit can be set when the FMR01 bit is set to "1". To set the FMR02 bit to "1", set it to "1" immediately after setting it to "0". To set the FMR02 bit to "0", set it to "0". The FMR02 bit does not change the lock bit state, but disables the lock bit function. If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to "1", the lock bit state changes "0" (locked) to "1" (unlocked) after command execution is completed.

25.3.1.4 FMR03 Bit

By setting the FMR03 bit to "0" following "1", access to the user ROM area is interrupted to reset the flash memory control circuit. The flash memory enters read array mode after reset. The FMR00 bit is set to "1" (READY) and the Status register is set to "80 16". (Refer to 25.3.2 Status Register.) When the FMR03 bit resets the flash memory control circuit during an auto write or auto erase opera- tion, an auto write or auto erase operation is interrupted. Data in the block is invalid. To set the FMR03 bit to "0", set it to "0" immediately after setting it to "1".

25.3.1.5 FMR05 Bit

The FMR05 bit selects the boot ROM or user ROM area in boot mode. Set to "0" to access (read) the boot ROM area or to "1" (user ROM access) to access (read, write or erase) the user ROM area. Execute an instruction written to the FMR05 bit in a space (internal RAM, etc.) other than the flash memory. In modes other than boot mode, the user ROM area is accessed (read) regardless of the FMR05 bit setting.

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25.3.2 Status Register

The write state machine (WSM) in the flash memory controls programming and erasing of the flash memory. The status register indicates whether or not the WSM is operating as expected, and whether or not a program or erase operation is completed as expected. Refer to 25.3.6 Full Status Check for details on each error. Table 25.4 lists the status register. The status register can be read by the read status command (Refer to 25.3.5 Software Command). Table 25.4 Status Register Symbol SR4 (D4) SR5 (D5) SR7 (D7) SR6 (D6) Status Name Definition SR1 (D1) SR2 (D2) SR3 (D3) SR0 (D0) Program status Erase status Write state machine (WSM) status Reserved bit Reserved bit Reserved bit Block status after program Reserved bit READYBUSY Error (erase error) Error (excessive write error) Error (program error) Completed as expected D 7 to D0 : These data bus are read when the read status register command is executed. Completed as expected Completed as expected

25.3.2.1 Block Status After Program (SR3)

The SR3 bit is set to "1" when a page program command execution is completed with an excessive write error. The SR3 bit is set to "0" when the clear status command is executed. The SR3 bit is set to "0" after reset or after setting the FMR03 bit to "0" following "1".

25.3.2.2 Program Status (SR4)

The SR4 bit is set to "1" when a program error occurs while the page program or lock bit program command is being executed. The SR4 bit is set to "0" when the clear status command is executed. The SR4 bit is set to "0" after reset or after setting the FMR03 bit to "0" following "1".

25.3.2.3 Erase Status (SR5)

The SR5 bit is set to "1" when an erase error occurs while the block erase or erase all unlocked block command is being executed. The SR5 bit is set to "0" when the clear status command is executed. The SR5 bit is set to "0" after reset or after setting the FMR03 bit to "0" following "1".

25.3.2.4 Write State Machine (WSM) Status (SR7)

The SR7 bit indicates the WSM operation state. The SR7 bit is set to "0" during auto write or auto erase and to "1" when an auto write or auto erase operation is completed. The SR7 bit changes while the page program, block erase, erase all unlocked block or lock bit program command is being ex- ecuted. The SR7 bit changes with the above commands only. The SR7 bit is set to "1" after reset or after setting the FMR03 bit to "0" following "1",. The FMR00 bit indicates the WSM status. Read the FMR00 bit to determine whether the auto write or erase operation is completed.

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25.3.3 Data Protect Function

Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to "0" (lock bit enabled). The lock bit individually protects (locks) each block against program and erase. This prevents data from being inadvertently written to or erased from the flash memory. When the lock bit status is set to "0", the block is locked (block is protected against program and erase).

When the lock bit status is set to "1", the block is not locked (block can be programmed or erased). The lock bit status is set to "0" (locked) by executing the lock bit program command and to "1" (unlocked) by erasing the block. The lock bit status cannot be set to "1" by any commands. The lock bit status can be read by the read lock bit status command. The lock bit function is disabled by setting the FMR02 bit to "1". All blocks are unlocked. However, individual lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit to "0". Lock bit status is retained. If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to "1", the target block or all blocks are erased regardless of lock bit status. The lock bit status of each block is set to "1" after an erase operation has been completed. Refer to 25.3.5 Software Commands for details on each command.

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25.3.4 How to Enter and Exit CPU Rewrite Mode

Figure 25.5 shows how to enter and exit CPU rewrite mode. No program in the flash memory can be executed in CPU rewrite mode. Execute rewrite control program in a space other than the flash memory (internal RAM, etc.) after transferring the program to that space. Jump to the rewrite control program transferred to space other than the flash memory. (On the following steps, use the rewrite control program in space other than the flash memory.) In boot mode only Set the FMR05 bit to "1" (User ROM area accessed) Set the FMR01 bit to "0" (CPU rewrite mode disabled) In boot mode only Set the FMR05 bit to "0" (boot ROM area accessed) (3) Jump to a desired address in the flash memory Execute software commands Set the FMR03 bit to "0" after executing a read array command or after setting the FMR03 bit to "1" (2) Set the FMR01 bit to "1" (CPU rewrite mode enabled) following "0" NOTES: 1. Set the MCD register to the following CPU clock frequency: When the PM12 bit in the PM1 register is set to "0" (no internal access wait), 6.25 MHz or less When the PM12 bit in the PM1 register is set to "1" (internal access wait), 12.5 MHz or less 2. Exit CPU rewrite mode after excuting the read array command or resetting the flash memory. 3. When CPU rewrite mode is exited while the FMR05 bit is set to "1", the user ROM area can be accessed. Rewrite control program Set the PM0, PM1 and MCD register(1) Single-chip mode, Memory expansion mode, Boot mode Transfer the rewrite control program in CPU rewrite mode to space other than the flash memory Figure 25.5 How to Enter and Exit CPU Rewrite Mode

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25.3.5 Software Commands

Read or write commands and data from or to even addresses in the user ROM area, in 16-bit units. When writing a command code, 8 high-order bits (D15 to D8) are ignored.

25.3.5.1 Read Array Command

The read array command reads the flash memory. Read array mode is entered by writing command code "xxFF 16" in the first bus cycle. Content of a specified address can be read after the next bus cycle. The microcomputer remains in read array mode until another command is written. Therefore, contents from multiple addresses can be read consecutively.

25.3.5.2 Read Status Register Command

The read status register command reads the status register (refer to 25.3.7 Status Register for details). By writing command code "xx7016" in the first bus cycle, the status register can be read in the second bus cycle. Read an even address in the user ROM area.

25.3.5.3 Clear Status Register Command

The clear status register command clears the status register. By writing "xx5016" in the first bus cycle, the SR5 to SR3 bits in the status register (see Table 25.4) are set to "0".

25.3.5.4 Page Program Command

The page program command executes programs in 128-word (256-byte) units. After writing command code "xx41 16" in the first bus cycle, write data to the 2nd through 129th bus cycles in 16-bit units. Increment by two, from "0016" to "FE16", the 8 low-order bits of the write address. Auto write, programming and verification of data, is performed when 128 word data has been written. Do not access the flash memory or execute the next command during auto write operation. The FMR00 bit in the FMR0 register indicates whether an auto program operation is completed. After an auto write operation is completed, the Status register indicates whether the auto write opera- tion is completed as expected or not. (Refer to 25.3.6 Full Status Check.) Figure 25.6 shows a flow chart of the page program command programming. When programming a space which is already programmed, execute erase (block erase) before programming. If the page program command is executed to a space already programmed, no program error occurs but the page is indeterminate. The lock bit can protect blocks from being programmed. (Refer to 25.3.3 Data Protect Function.)

Page 401 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M Figure 25.6 Program Command n = FE16 Start Write command code "xx4116" n = 0 Write data to the address to be written Full status check Page program operation is completed Address to be written address to be written + 2 n = n + 2 NO YES NO YES FMR00 bit = 1? (auto write operation completed?) See Figure 25.11

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25.3.5.5 Block Erase Command

The block erase command erases each block. By writing command code "xx2016" in the first bus cycle and "xxD016" to the highest-order even address of a block in the second bus cycle, an auto erase operation (erase and verify) starts in the specified block. Do not access the flash memory or execute the next command during auto erase operations. The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed. After the completion of an auto erase operation, the Status register indicates whether or not the auto erase operation has been completed as expected. (Refer to 25.3.6 Full Status Check.) Figure 25.7 shows a flow chart of the block erase command programming. The lock bit can protect blocks from being erased. (Refer to 25.3.6 Data Protect Function.) Figure 25.7 Block Erase Command Write command code "xx2016" Write "xxD016" to the highest-order block address Block erase operation is completed Start NO YES FMR00 bit = 1? (auto erase operation completed?) See Figure 25.11Full status check

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25.3.5.6 Erase All Unlocked Block Command

By writing command code "xxA716" in the first bus cycle and "xxD016" in the second bus cycle, an auto erase (erase and verify) operation will run in all blocks. Do not access the flash memory or execute the next command during auto erase operations. The FMR00 bit in the FMR0 register indicates whether an auto erase operation is completed. After the completion of an auto erase operation, the Status register indicates whether or not the auto erase operation is completed as expected. Figure 25.8 shows a flow chart of the erase all unlocked block command programming. The lock bit can protect each block from being erased. (Refer to 25.3.6 Data Protect Function.) Write command code "xxA716" All unlocked block erase operation is completed Start NO YES FMR00 bit = 1? (auto erase operation completed?) See Figure 25.11Full status check Write "xxD016" Figure 25.8 Erase All Unlocked Block Command

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25.3.5.7 Lock Bit Program Command

The lock bit program command sets the lock bit for a specified block to "0" (locked). By writing command code "xx7716" in the first bus cycle and "xxD016" to the highest-order even ad- dress of a block in the second bus cycle, auto write operation starts, and the lock bit for the specified block is set to "0". Do not access the flash memory or execute the next instructions during the lock bit program operation. The FMR00 bit in the FMR0 register indicates whether or not the lock bit program operation has been completed. After the completion of a lock bit program operation, the Status register indicates whether or not the operation has been completed as expected. (Refer to 25.3.6 Full Status Check.) Figure 25.9 shows a flow chart of the lock bit program command programming. Refer to 25.3.6 Data Protect Function for details on how to set the lock bit function to "0" (unlocked). Write command code "xx7716" Write "xxD016" to the highest- order block address Lock bit program operation is completed Start NO YES FMR00 bit = 1? (auto write operation completed?) See Figure 25.11Full status check Figure 25.9 Lock Bit Program Command

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25.3.5.8 Read Lock Bit Status Command

The read lock bit status command reads the lock bit state of a specified block. By writing command code "xx71 16" in the first bus cycle and reading the highest-order address (how- ever, A0=0) of a block in the second bus cycle, the lock bit state information of a specified block is read out to the data bus (D6). Figure 25.10 shows a flow chart of the read lock bit status command programming. Figure 25.10 Read Lock Bit Status Command D 6 = 0? NO Blocks are locked No block is locked YES Start Read the value in the highest-order block address Write command code "xx7116"

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25.3.6 Full Status Check

If an error occurs when a program or erase operation is completed, the SR3 to SR5 bits in the status register are set to "1", indicating a specific error. Therefore, execution results can be confirmed by verify- ing these bits (full status check). Table 25.5 lists errors and status register state. Figure 25.12 shows a flow chart of the full status check and handling procedure for each error. Table 25.5 Errors and Status Register State Status Register Error Error Occurrence Conditions SR5 SR4 SR3 1 1 0 Command sequence error 1 0 0 Erase error 0 1 0 Program error 0 0 1 Excessive write error NOTES: 1. The flash memory enters read array mode when command code "xxFF16" is written in the second bus cycle of these commands. The command code written in the first bus cycle becomes invalid. 2. If the FMR02 bit is set to "1" (lock bit disabled), no error occurs even under the conditions listed above.

An incorrect command is written
A value other than "xxD016" or "xxFF16" is written in the sec- ond bus cycle of the lock bit program, block erase or erase all unlocked block command (1)
The block erase command is executed on a locked block2
The block erase or erase all unlocked block command is executed on an unlock block but the erase operation is not completed as expected
The page program command is executed on a locked block (2)
The page program command is executed in an unlocked block but the program operation is not completed as ex- pected
The lock bit program command is executed but the pro- gram operation is not completed as expected Excessive write occurs after the page program command is executed

Page 407 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M Figure 25.11 Full Status Check and Handling Procedure for Each Error Start SR5=0 ? Completed NO NO YES Erase error YES Command sequence error SR4=1 and SR5=1 SR4=0 ? NO YES Program error SR3=0 ? NO YES Excessive write error (1) Execute the clear status register command, and set the SR4 and SR5 bits to "0". (2) Execute the correct command again. NOTE: If similar error occurs, that block cannot be used. NOTE: When any of the SR5 to SR3 bits are set to "1", the page program, block erase, erase all unlocked block and lock bit program commands cannot be accepted. Execute the clear status register command before each command. (1) Execute the clear status register command and set the SR5 bit to "0". (2) Execute the lock bit read status command, and set the FMR02 bit to "1" if the lock bit in the block where the error occurred is set to "0" (locked). (3) Execute the block erase or erase all unlocked block command again. NOTE: If similar error occurs, that block cannot be used. If the lock bit is set to "1" (unlocked) in (2) above, that block cannot be used. (1) Execute the clear status register command and set the SR4 bit to "0". (2) Execute the read lock bit status command, and set the FMR02 bit to "1" if the lock bit in the block where the error occurred is set to "0" (locked) . (3) Execute the page program command again. NOTE: If similar error occurs, that block cannot be used. If the lock bit is set to "1" (unlocked) in (2) above, that block cannot be used. (1) Execute the clear status register command and set the SR3 bit to "0". (2) Execute the block erase command to erase the block where the error occurred. (3) Execute the page program command again. NOTE: If similar error occurs, that block cannot be used. [When a page program operation is executed] [When a lock bit program operation is executed] Write command code "xx7016" Read even address in user ROM area (1) Execute the clear status register command and set the SR4 bit to "0". (2) Set the FMR02 bit to "1". (3) Execute the block erase command to erase the block where the error occurred. (4) Execute the lock bit program command again. NOTE: If similar error occurs, that block cannot be used.

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25.3.7 Precautions in CPU Rewrite Mode

25.3.7.1 Operating Speed

Set the MCD register to the following CPU clock before entering CPU rewrite mode . When the PM12 bit in the PM register is set to "0" (no wait state), 6.25MHz or less When the PM12 bit in the PM register is set to "1" (wait state), 12.5MHz or less

25.3.7.2 Prohibited Instructions

In CPU rewrite mode, programs cannot be executed, nor can interrupt vectors be read in the flash memory. Execute the rewrite control program after the program is transferred to a space other than the flash memory. (See Figure 25.5.) The following instructions cannot be used because the CPU tries to read data in the flash memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction.

25.3.7.3 Interrupts

To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM area.
The NMI and watchdog timer interrupts are available since the FMR01 is forcibly reset when either interrupt occurs. Allocate the jump addresses for each interrupt service routine and write to the fixed vector table. Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt occurs. Execute the rewrite program again after exiting the interrupt routine.
The address match interrupt is not available since the CPU tries to read data in the flash memory.

25.3.7.4 Reading and Writing Commands and Data

Read or write 16-bit commands and data from or to even addresses in the user ROM area.

25.3.7.5 Reset

Reset is always enabled.

25.3.7.6 Access Prohibited

Write the FMR01 bit and FMR05 bit in a space other than the flash memory.

25.3.7.7 How to Access

To set the FMR01 bit and FMR02 bits to "1", set to "1" immediately after setting to "0". Do not generate an interrupt or a DMA transfer between the instruction to set the bits to "1" and the instruction to set the bits to "0". Set the FMR01 bit to "1" after an "H" signal is applied to the P85/NMI pin.

25.3.7.8 Rewriting in the User ROM Area

If the supply voltage drops while in CPU rewrite mode, when rewriting the block where the rewrite control program is stored, the flash memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error occurs, rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode.

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25.4 Standard Serial I/O Mode

In standard serial I/O mode, the serial programmer supporting the M32C/83 group can be used to rewrite the flash memory user ROM area, while the microcomputer is mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual included with your serial programmer for instructions. Standard serial I/O mode includes:

Standard serial I/O mode 1 (clock synchronous)
Standard serial I/O mode 2 (clock asynchronous)

25.4.1 Pin Function

Table 25.6 lists pin descriptions (flash memory standard serial I/O mode). Figures 2.12 to 25.14 show pin connections in serial I/O mode.

25.4.2 ID Code Verify Function

The ID code verify function determines whether the ID codes sent from the serial programmer matches those written in the flash memory. (Refer to 25.2 Functions to Prevent Flash Memory from Rewrit- ing.)

Page 410 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M Table 25.6 Pin Description (Flash Memory Standard Serial I/O Mode) Symbol Function I/O Type Description VCC Power Supply I Apply 4.2 V to 5.5 V to the VCC pin VSS Input Apply 0 V to the VSS pin CNV SS CNV SS I Connect this pin to VCC RESET Reset Input I Reset input pin. Apply 20 or more clock cycles to the X IN pin while "L" is applied to the RESET pin. XIN Clock Input I Connect a ceramic resonator or crystal oscillator between XIN and XOUT Clock Output O X OUT . To use the external clock, input the clock from XIN and leave XOUT open. BYTE BYTE Input I Connect this pin to V SS or VCC AV CC Analog Power I Connect AV CC to VCC AV SS Supply Input I Connect AV SS to VSS VREF Reference I Reference voltage input pin for the A/D converter. Voltage Input P00 to P07 Input Port P0 I Apply "H" or "L" to this pin, or leave open P10 to P17 Input Port P1 I Apply "H" or "L" to this pin, or leave open P20 to P27 Input Port P2 I Apply "H" or "L" to this pin, or leave open P30 to P37 Input Port P3 I Apply "H" or "L" to this pin, or leave open P40 to P47 Input port P4 I Apply "H" or "L" to this pin, or leave open P5 0 ___ CE Input I Apply "H" to this pin. P5 5 EPM Input I Apply "L" to this pin. P51 to P54 Input Port P5 I Apply "H" or "L" to this pin, or leave open P56, P57 P60 to P63 Input Port P6 I Apply "H" or "L" to this pin, or leave open P6 4 BUSY Output O Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Program running verify monitor P6 5 SCLK Input I Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Apply "L" to this pin P6 6 RxD I Serial data input pin P6 7 TxD O Serial data output pin (1) P70 to P77 Input Port P7 I Apply "H" or "L" to this pin, or leave open P80 to P84 Input Port P8 I Apply "H" or "L" to this pin, or leave open P86, P87 P8 5 ____ NMI Input I Connect this pin to V CC P90 to P97 Input Port P9 I Apply "H" or "L" to this pin, or leave open P10 0 to P107 Input Port P10 I Apply "H" or "L" to this pin, or leave open P11 0 to P114(2) Input Port P11 I Apply "H" or "L" to this pin, or leave open P12 0 to P127(2) Input Port P12 I Apply "H" or "L" to this pin, or leave open P13 0 to P137(2) Input Port P13 I Apply "H" or "L" to this pin, or leave open P14 0 to P146(2) Input Port P14 I Apply "H" or "L" to this pin, or leave open P15 0 to P157(2) Input Port P15 I Apply "H" or "L" to this pin, or leave open NOTES: 1. In standard serial I/O mode 1, apply an "L" signal to the TxD pin while applying "L" to the RESET pin. Connect P67 to VSS via a resistor. P67 becomes a data output pin after reset. Adjust the value of the pull-down resistor on your system so as not to affect data transfer. 2. These pins are provided in the 144-pin package only.

Page 411 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M Figure 25.12 Pin Connections in Standard Serial I/O Mode (1) 1 2 3 4 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 515253545556575859606162636465666768697071727374757677787980 100 Vcc Vss TxD RxD SCLK CNVss CE EPM BUSY RESET Connect to oscillation circuit M32C/83 Group (M32C/83, M32C/83T) Flash Memory Version (PRQP0100JB-A(100P6S-A)) Signal Value CNVss Vcc EPM Vss RESET Vss >> Vcc CE Vcc Mode settings

Page 412 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M Figure 25.13 Pin Connections in Standard Serial I/O Mode (2) 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CNV SS RESET VSS VCC CE BUS Y EPM SCLK R XD TX D Connect to oscillation circuit Signal Value CNVss Vcc EPM Vss RESET Vss >> Vcc CE Vcc Mode settings M32C/83 Group (M32C/83, M32C/83T) Flash Memory Version (PLQP0100KB-A(100P6Q-A))

Page 413 884fo6002,13.naJ13.1.veR 1310-4300B90JER 25. Flash Memory Version)T38/C23M,38/C23M(puorG38/C23M Figure 25.14 Pin Connections in Standard Serial I/O Mode (3) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 7374757677798081828384858687888990919293949596979899100101102103104105106107108 78 1234 7 6 8 9 1 0 1 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 8 2 93 05 31 32 33 34 35 36 CNV SS RESET EPM CE VCC VSS TxD RxD SCLK BUSY M32C/83 Group (M32C/83, M32C/83T) Flash Memory Version (PLQP0144KA-A(144P6Q-A)) Signal Value CNVss Vcc EPM Vss RESET Vss >> Vcc CE Vcc Mode settings Connect to oscillation circuit

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25.4.3 Precautions in Standard Serial I/O Mode

Serial I/O mode cannot be used after boot ROM area is written in parallel I/O mode.
If an user reset signal becomes "L" in serial I/O mode, break connection between the user reset signal and the RESET pin by using, for example, a jumper selector.

25.4.4 Circuit Application in Standard Serial I/O Mode

Figure 25.15 shows an example of a circuit application in standard serial I/O mode 1. Figure 25.16 shows an example of a circuit application in serial I/O mode 2. Refer to the user's manual of your serial program- mer to handle pins controlled by the serial programmer. Figure 25.15 Circuit Application in Standard Serial I/O Mode 1 BUSY SCLK TXD CNVss Clock Input BUSY Output Reset Input Data Output P50(CE) P55(EPM) Microcomputer NMI RESET User Reset Signal RxDData Input NOTES: 1. Control pins and external circuitry vary with serial programmer. Refer to the user's manual included with the serial programmer. 2. In this example, a selector is used to switch between single-chip mode and standard serial I/O mode. 3. In standard serial I/O mode 1, if the user reset signal becomes "L" while in serial I/O mode, break connection between the user reset signal and the RESET pin using, for example, a jumper selector. BUSY SCLK R XD TXD CNVss Data Input Data Output P50(CE) P55(EPM) NMI Monitor Output Microcomputer NOTES: 1. In this example, a selector is used to switch between single-chip mode and standard serial I/O mode. Figure 25.16 Circuit Application in Standard Serial I/O Mode 2

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25.5 Parallel I/O Mode

In parallel I/O mode, the user ROM area and the boot ROM area (see Figure 25.1) can be rewritten by a parallel programmer supporting the M32C/83 Group. Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user's manual included with your parallel pro- grammer for instructions.

25.5.1 Boot ROM Area

Within the boot ROM area, 8K bytes equal one block. The rewrite control program in standard serial I/O mode is written in the boot ROM area before shipment. Do not rewrite the boot ROM area if using a serial programmer. In parallel I/O mode, the boot ROM area is allocated to addresses 0FFE00016 to 0FFFFFF16. Rewrite only this address range when rewriting the boot ROM area. (Do not access addresses other than ad- dresses 0FFE000 16 to 0FFFFFF16.)

25.5.2 ROM Code Protect Function

The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O mode. (Refer to 25.2 Functions to Prevent Flash Memory from Rewriting.)

25.5.3 Precautions on Parallel I/O Mode

Standard serial I/O mode cannot be used if rewriting the boot ROM area in parallel I/O mode. (Refer to 25.4 Standard Serial I/O Mode.)

Page 416 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M 26. Electrical Characteristics

26.1 Electrical Characteristics (M32C/83)

Table 26.1 Absolute Maximum Ratings lobmySr etemaraPn oitidnoCe ulaVt inU V CC egatloVylppuSV CC VA= CC 0.6ot3.0- V VA CC egatloVylppuSgolanAV CC VA= CC 0.6ot3.0- V VI egatloVtupnIV NC,TESER SS 0P,ETYB, 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7, 3P 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0- 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( V, FER X, NI Vot3.0- CC 3.0+V 7P 0 7P, 1 0.6ot3.0-V VO egatloVtuptuO0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )1( X, TUO Vot3.0- CC 3.0+V dPn oitapissiDrewoP C°52=rpoT0 05W m rpoTe rutarepmeTtneibmAgnitarepO ot02-5 8C ° gtsTe rutarepmeTegarotS 051ot56-C ° :SETON .egakcapnip-441ehtnidedivorpera51Pot11P.1

Page 417 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M Table 26.2 Recommended Operating Conditions (VCC = 3.0V to 5.5V at Topr = – 20 to 85oC) lobmySr etemaraPd radnatSt inU niMp yTx aM V CC )CDVhguorhT(egatloVylppuS 0.30 .55 .5V )CDVhguorhttoN(egatloVylppuS 0.33 .36 .3V VA CC egatloVylppuSgolanA V CC V V SS egatloVylppuS 0V VA SS egatloVylppuSgolanA 0V V HI )"H"(hgiHtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0- 8P 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( X, NI VNC,TESER, SS ETYB, V8.0 CC V CC V 7P 0 7P, 1 V8.0 CC 0.6 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(V 8.0 CC V CC V 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( V5.0 CC V CC V V LI )"L"(woLtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0- 8P 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( X, NI VNC,TESER, SS ETYB, 0V 2.0 CC V 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(0 V 2.0 CC V 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( 0V 61.0 CC V I )kaep(HO tuptuOkaeP )"H"(hgiH tnerruC )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01-A m I )gva(HO tuptuOegarevA )"H"(hgiH tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5-A m I )kaep(LO tuptuOkaeP )"L"(woL tnerruC )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01A m I )gva(LO tuptuOegarevA )"L"(woL tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5A m X(f NI )k colCniaM tupnI ycneuqerF CDVhguorhTV CC V5.5ot2.4= V CC V3.4ot0.3= zHM zHM CDVhguorhttoNV CC 6.3ot0.3=0 0 2z HM X(f NIC )y cneuqerFnoitallicsOkcolCbuS 867.230 5z Hk :SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(HO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08-ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(LO 8P,7P,6P,5P,4P,3Prof 0 8Pot 4 .sselroAm08ebtsum31Pdna21P, IlatoT )kaep(HO 7P,6P,5P,4P,3Prof 2 7Pot 7 8P, 0 8Pot 4 .sselroAm08-ebtsum31Pdna21P, .3V HI Vdna LI 8Profecnerefer 7 8Pnehwseilppa 7 .troptupnielbammargorpasadesusi 8PotylppatonseodtI 7 Xsadesu NIC . .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.4

Page 418 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M Table 26.3 Electrical Characteristics (VCC =4.2 to 5.5V, VSS =0V at Topr= –20 to 85oC, f(XIN)=32MH Z unless otherwise specified) lobmySr etemaraPn oitidnoCd radnatSt inU niMp yTx aM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO Am5-=0 .2-ccVV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO 002-= µA3 .0-ccV X TUO I HO Am1-=0 .3V X TUOC deilppadaoloN3 .3V V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO 002= µA5 4.0V X TUO I LO Am1=0 .2V X TUOC deilppadaoloN0 V V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI -0TNI, DA,5TNI GRT ,4KLC-0KLC,4STC-0STC, 0AT TUO 4AT- TUO ,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS , ETYB VI V5=0 .5 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS , ETYB VI V0=0 .5- µA R PULLUP ecnatsiseRpu-lluP0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( VI V0=0 30 57 61k Ω fR NIX ecnatsiseRkcabdeeFX NI 5.1M Ω fR NICX ecnatsiseRkcabdeeFX NIC 01M Ω V MAR egatloVybdnatSMARC DVhguorhT5 .2V I CC ylppuSrewoP tnerruC :snoitidnoctnemerusaeM tuptuo,edompihc-elgnisnI rehtodnanepotfelerasnip Votdetcennocerasnip SS . X(f NI ,evawerauqs,zHM23=) noisividon 044 5A m X(f NIC ,etatstiawahtiw,zHk23=) 52=rpoTC ° 074 µA 52=rpoTk colcehtnehwC° spots 4.00 2 µA :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

Page 419 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M Table 26.4 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5V, Vss = AVSS = 0V at Topr = –20 to 85oC, f(XIN) = 32MHZ unless otherwise specified) lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU niMp yTx aM -n oituloseRV FER V= CC 01s tiB LNIr orrEytiraenilnoNlargetnIV FER V= CC V5= NA 0 NAot 7 NA 0XE NA, 1XE BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orrEytiraenilnoNlaitnereffiD 1±B SL -r orrEtesffO 3±B SL -r orrEniaG 3±B SL R REDDAL reddaLrotsiseRV FER V= CC 80 4k Ω t VNOC emiTnoisrevnoCtib-01 1.2 µs t VNOC emiTnoisrevnoCtib-8 8.1 µs t PMAS emiTelpmaS 2.0 µs V FER egatloVecnerefeR 2V CC V V AI egatloVtupnIgolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM61gnideecxefi,) φ .sselrozHM61taycneuqerfDA lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU niMp yTx aM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV ylppuSrewoPecnerefeR tnerruCtupnI )1etoN(5 .1A m :SETON ehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwstlusertnemerusaeM.1 00"ottessidesugniebtonretrevnocA/D 61 .deulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOCiDAehtnitibTUCVehtfineveswolf FER .)noitcennoc Table 26.5 D/A Conversion Characteristics (VCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V at Topr = –20 to 85oC, f(XIN) = 32MHZ unless otherwise specified) Table 26.6 Flash Memory Version Electrical Characteristics retemaraP dradnatS tinU niMp yTx aM )egaprep(emiTmargorP8 0 21s m )kcolbrep(emiTesarEkcolB0 50 06s m :SETON deificepsesiwrehto

Page 420 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP dradnatS tinU niMx aM cte miTelcyCtupnIkcolClanretxE 33s n wt )H( htdiWesluP)"H"(hgiHtupnIkcolClanretxE 31s n wt )L( htdiWesluP)"L"(woLtupnIkcolClanretxE 31s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n tac1(RD – DB) = f(BCLK) X 2 – 35109 [ns] tac2(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) tac1(AD – DB) = f(BCLK) – 3510 9 [ns] tac2(AD – DB) = – 3510 X n [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) tac3(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD – DB) = f(BCLK) X 2 – 3510 X n9 [ns] (n=5 with 2 wait states and n=7 with 3 wait states) tac4(RAS – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS – DB) = – 3510 X n9 [ns] (n=1 with 1 wait state and n=3 when 2 wait states) tac4(CAD – DB) = f(BCLK ) – 3510 X l9 [ns] (l=1 with 1 wait state and l=2 with 2 wait states) f(BCLK) f(BCLK) X 2 Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.7 External Clock Input Table 26.8 Memory Expansion and Microprocessor Modes lobmySr etemaraP dradnatS tinU niMx aM 1cat )BD-DR( )etatstiawonhtiw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 1cat )BD-DA( )etatstiawonhtiw,dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DR( )etatstiawahtiw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DA( )etatstiawahtiw,dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 3cat )BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 3cat )BD-DA( dexelpitlumehthtiwecapsagnisseccanehw,dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )sub )1etoN(s n 4cat )BD-SAR( )ecapsMARDagnisseccanehw,dradnatsSAR(emiTsseccAtupnIataD )1etoN(s n 4cat )BD-SAC( )ecapsMARDagnisseccanehw,dradnatsSAC(emiTsseccAtupnIataD )1etoN(s n 4cat )BD-DAC( )ecapsMARDagnisseccanehw,dradnatsDAC(emiTsseccAtupnIataD )1etoN(s n ust )KLCB-BD( emiTputeStupnIataD 62s n ust )KLCB-YDR( emiTputeStupnIYDR 62s n ust )KLCB-DLOH( emiTputeStupnIDLOH 03s n ht )BD-DR( emiTdloHtupnIataD 0s n ht )BD-SAC( emiTdloHtupnIataD 0s n ht )YDR-KLCB( emiTdloHtupnIYDR 0s n ht )DLOH-KLCB( emiTdloHtupnIDLOH 0s n dt )ADLH-KLCB( emiTyaleDtuptuOADLH 52s n :SETON rewolroetatstiawatresnI.ycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepoeht KLCB .evitagensieulavdetaluclacehtfi,)

Page 421 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU niMx aM wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU niMx aM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiWesluP)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiWesluP)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.9 Timer A Input (Count Source Input in Event Counter Mode) Table 26.10 Timer A Input (Gate Input in Timer Mode) Table 26.11 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 26.12 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 26.13 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Page 422 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.14 Timer B Input (Count Source Input in Event Counter Mode) Table 26.15 Timer B Input (Pulse Period Measurement Mode) Table 26.16 Timer B Input (Pulse Width Measurement Mode) Table 26.17 A/D Trigger Input Table 26.18 Serial I/O Table 26.19 External Interrupt INTi Input lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiWesluP)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiWesluP)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiWesluP)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiWesluP)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )DA( DA GRT )reggirt-errofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiWesluP)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU niMx aM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiWesluP)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiWesluP)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTpUteStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU niMx aM wt )HNI( htdiWesluP)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiWesluP)"L"(woLtupnIiTNI 052s n

Page 423 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M See Figure 26.1 lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceles-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceles-pihC 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n dt )ELA-KLCB( emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( emiTdloHtuptuOlangiSELA 2-s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 3-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )1etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n wt )RW( htdiWtuptuORW )1etoN(s n :SETON .ycneuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 td(DB – WR) = f(BCLK) 10 9 – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2 10 9 – 15 [ns] Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.20 Memory Expansion Mode and Microprocessor Mode (with No Wait State)

Page 424 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceles-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceles-pihC 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n dt )ELA-KLCB( emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( emiTdloHtuptuOlangiSELA 2-s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 3-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )1etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n wt )RW( htdiWtuptuORW )1etoN(s n :SETON .ycneuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 [ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) td(DB – WR) = f(BCLK)

10 X n9

– 20 th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states) tw( WR) = 10 X n9 – 15f(BCLK) X 2 See Figure 26.1 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.21 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory)

Page 425 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )1etoN(s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceles-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DA-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 3-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )1etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 2-s n dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )1etoN(s n ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )1etoN(s n zdt )DA-DR( emiTecnadepmI-hgiHtuptuOsserddA 8s n :SETON .ycneuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 td(DB – WR) = 10 X m – 25 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 10 9 – 20 [ns] th(ALE – AD) = f(BCLK ) X 2 10 9 – 10 [ns] f(BCLK) X 2 See Figure 26.1 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.22 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting a Space with the Multiplexed Bus)

Page 426 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =5V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DAR-KLCB( emiTyaleDtuptuOsserddAwoR 81s n ht )DAR-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddAwoR 3-s n dt )DAC-KLCB( emiTyaleDtuptuOsserddAnmuloC 81s n ht )DAC-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddAnmuloC 3-s n ht )DAR-SAR( tuptuOSARretfaemiTdloHtuptuOsserddAwoR )1etoN(s n dt )SAR-KLCB( )dradnatsKLCB(emiTyaleDtuptuOSAR 81s n ht )SAR-KLCB( )dradnatsKLCB(emiTdloHtuptuOSAR 3-s n t PR emiTdloH)"H"(hgiHSAR )1etoN(s n dt )SAC-KLCB( )dradnatsKLCB(emiTyaleDtuptuOSAC 81s n ht )SAC-KLCB( )dradnatsKLCB(emiTdloHtuptuOSAC 3-s n dt )WD-KLCB( )dradnatsKLCB(emiTyaleDtuptuOWD 81s n ht )WD-KLCB( )dradnatsKLCB(emiTdloHtuptuOWD 5-s n ust )SAC-BD( tuptuOBDretfaemiTputeStuptuOSAC )1etoN(s n ht )BD-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSBD 7-s n ust )SAR-SAC( )hserfer(tuptuOSARerofebemiTputeStuptuOSAC )1etoN(s n :SETON .ycneuqerfKLCBotgnidrocca,noitauqegniwollofehtmorfdeniatboebnacseulaV.1 tsu(CAS – RAS) = f(BCLK) X 2 – 13 [ns] th(RAS – RAD) = f(BCLK) X 2 10 9 – 13 [ns] tRP = f(BCLK) X 2

10 X 39

– 20 [ns] tsu(DB – CAS) = f(BCLK) 10 9 – 20 [ns] See Figure 26.1 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.23 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting the DRAM Space)

Page 427 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M P10 30pF P14 P13 P12 P15 P11 Note 1 NOTES: 1. P11 to P15 are provided in the 144-pin package only. Figure 26.1 P0 to P15 Measurement Circuit

Page 428 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M Figure 26.2 VCC =5V Timing Diagram (1) B C L K A L E - 2 n s . m i n R D 1 8 n s . m a x -5ns.min H i - Z D B 0ns.min 0ns.min td(BCLK-ALE) th B C L K A L E ts D B B C L K td B C L K R D 26ns.min(1) C S i td B C L K C S n s m a A D i th B C L K A D -3ns.min th B C L K C S - 3n s . m i n B H E t c y c td B C L K A D 0 n s . m i n tac1(AD-DB)(2) W R , W R L , W R H 1 8 n s . m a x - 3 n s . m i n B C L K C S i td B C L K C S 1 8 n s . m a x A D i td(BCLK-AD) 1 8 n s . m a x td B C L K A L E -3ns.min 3 n s . m i n tcyc BHE D B i td(BCLK-WR) A L E 18ns.max - 2 n s . m i n th W R D B td D B W R )= ( t c y c - 2 0 ) n s . m i n th W R D B t c y c n s m i n th W R A D t c y c n s m i n th W R C S t c y c n s m i n tw( W R t c y c n s m i n Vcc=5V th B C L K R D th(RD-DB) th(RD-AD) th R D C S th(BCLK-WR) th(BCLK-ALE) th B C L K A D th(BCLK-CS) th W R C S th(WR-AD) (3) tw(WR) (3) ta c R D D B n s m a Re a d T i m i n g W r i t e T i m i n g ( w r i t t e n i n 2 c y c l e s w i t h n o w a i t s t a t e ) NO T E S: Va r i e s w i t h o p e r a t i o n f r e q u e n c y : M e a s u r e m e n t C o n d i t i o n s : VC C = t o V I n p u t h i g h a n d l o w v o l t a g e VI H = V VI V O u t p u t h i g h a n d l o w v o l t a g e VO H = V VO V M e m o r y Ex p a ns i o n M o d e a n d M i c r o p r o c e s s o r M o d e ( w i t h n o w a i t s t a t e ) NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB)=(tcyc/2-35)ns.max tac1(AD-DB)=(tcyc-35)ns.max 18ns.max td(DB-WR) (3)

Page 429 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M B C L K A L E 1 8 n s . m a x 2 n s . m i n RD 8 n s . m a x 5 n s . m i n H i - Z D B 0ns.min td B C L K A L E ) th B C L K A L E td B C L K R D 26ns.min(1) ta c R D D B C S i td B C L K C S n s m a A D i n s m a th B C L K A D - 3 n s . m i n th B C L K C S 3 n s . m i n B H E t c y c td B C L K A D ta c A D D B W R , W R L , W R H 1 8 n s . m a x B C L K C S i 1 8 n s . m a x ADi 1 8 n s . m a x 3 n s . m i n 3 n s . m i n tcyc BHE D B i td B C L K W R A L E 18ns.max - 2 n s . m i n V c c = 5 V th B C L K R D th R D D B )ts u D B B C L K th R D C S n s . m i n td B C L K C S td B C L K A D td B C L K A L E th B C L K A D th B C L K C S th(WR-CS) (3) td(DB-WR) (3) th(WR-DB) (3) th W R A D td(DB-WR) =(tcyc x n-20)ns.min (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states) N O T E S : V a r i e s w i t h o p e r a t i o n f r e q u e n c y M e a s u r e m e n t c o n d i t i o n s VC C = t o V I n p u t h i g h a n d l o w v o l t a g e VI H = V VI V O u t p u t h i g h a n d l o w v o l t a g e VO H = V VO V th(BCLK-ALE) R e a d T i m i n g W r i t e T i m i n g ( w r i t t e n i n 2 c y c l e s w i t h n o w a i t s t a t e ) M e m o r y E x p a n s i o n M o d e a n d M i c r o p r o c e s s o r M o d e ( w i t h a w a i t s t a t e ) th R D A D tw W R th(BCLK-WR) 0ns.min N o t e s : V a l u e g u a r a n t e e d o n l y w h e n t h e m i c r o c o m p u t e r i s u s e d i n d e p e n d e n t l y A ma x i m u m o f n s i s g u a r a n t e e d f o r td B C L K A D ts u D B B C L K V a r i e s w i t h o p e r a t i o n f r e q u e n c y ta c R D D B t c y c x m n s m a x m w i t h w a i t s t a t e m w i t h w a i t s t a t e s a n d m w i t h w a i t s t a t e s ta c A D D B t c y c x n n s m a x n w i t h w a i t s t a t e n w i t h w a i t s t a t e s a n d n w i t h w a i t s t a t e s -3ns.min Figure 26.3 VCC =5V Timing Diagram (2)

Page 430 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M BCLK CSi 18ns.max ADi 18ns.max RD 18ns.max -5ns.min th(BCLK-AD) -3ns.min -3ns.min BHE ADi /DBi 0ns.min 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.min tcyc BHE ADi /DBi Data output WR,WRL, WRH Address AddressData input 26ns.min td(BCLK-RD) th(WR-CS) (2) Address td(AD-ALE)(2) Address tsu(DB-BCLK) tac3(RD-DB)(1) tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 18ns.max td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states) ALE 18ns.max -2ns.mintd(BCLK-ALE) th(ALE-AD)(1) td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min Vcc=5V td(BCLK-CS) td(AD-ALE)(1) th(ALE-AD)(1) th(BCLK-RD) th(RD-AD)(1) th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)(1) td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) (2) td(DB-WR) (2) th(WR-DB) (2) th(BCLK-ALE) th(BCLK-ALE) tcyc NOTES: 2. Varies with operation frequency: Measurement Conditions:

V CC =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VO H =2.0V, VO L=0.8V NOTES: 1. Varies with operation frequency: Read Timing Write Timing (written in 2 cycles with no wait state) Memory Expansion Mode and Microprocessor Mode (with a wait state, when accessing an external memory and using the multiplexed bus) tac3(AD-DB)(1) Figure 26.4 VCC =5V Timing Diagram (3)

Page 431 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M BCLK DW DB MAi Vcc=5V RAS CASL CASH Hi-Z tac4(CAS-DB)(2) 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) tac4(RAS-DB)(2) Row address Column address th(BCLK-RAD) -3ns.min 18ns.max(1) td(BCLK-CAD) 18ns.max(1) td(BCLK-RAS) 18ns.max(1) td(BCLK-CAS) th(RAS-RAD) (2) tRP (2) tac4(CAD-DB)(2) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min 0ns.min tsu(DB-BCLK) 26ns.min(1) th(CAS-DB) Measurement Conditions:

VCC =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VOH =2.0V, VOL =0.8V Read Timing Memory Expansion Mode and Microprocessor Mode (When accessing the DRAM area) NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for the following combinations. td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) 2. Varies with operation frequency: tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states) th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min Figure 26.5 VCC =5V Timing Diagram (4)

Page 432 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M BCLK DW DB MAi th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Vcc=5V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) -3ns.min 18ns.max td(BCLK-CAD) 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(RAS-RAD) (1) tRP (1) 18ns.max td(BCLK-DW) tsu(DB-CAS)(1) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) -5ns.min Row address Column address NOTES: 1. Varies with operation frequency: Measurement Conditions:

VCC =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VOH =2.0V, VOL =0.8V Write Timing Memory Expansion Mode and Microprocessor Mode (When accessing the DRAM area) Figure 26.6 VCC =5V Timing Diagram (5)

Page 433 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M tcyc 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min tsu(CAS-RAS)(1) 18ns.max tcyc td(BCLK-CAS) tsu(CAS-RAS)(2) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min 18ns.max td(BCLK-RAS) BCLK DW tsu(CAS-RAS)=(tcyc/2-13)ns.min Vcc=5V RAS CASL CASH BCLK DW tsu(CAS-RAS)=(tcyc/2-13)ns.min RAS CASL CASH NOTES : 1. Varies with operation frequency: Measurement Conditions:

VCC =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VOH =2.0V, VOL =0.8V Refresh Timing (CAS-before-RAS refresh) Memory Expansion Mode and Microprocessor Mode NOTES: 2. Varies with operation frequency: Refresh Timing (Self-refresh) Figure 26.7 VCC =5V Timing Diagram (6)

Page 434 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M tsu(D–C) TAiIN input TAiOUT input In event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN input (When counting on the falling edge) TAiIN input (When counting on the rising edge) TAiOUT input (Counter increment/ decrement input) INTi input AD TRG input Vcc=5V NMI input 2 clock cycles + 300ns ore more ("L" width) 2 clock cycles + 300ns or more Figure 26.8 VCC =5V Timing Diagram (7)

Page 435 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Hi–Z Measurement Conditions:

VCC =4.2 to 5.5V
Input high and low voltage: VIH=4.0V, VIL=1.0V
Output high and low voltage: VOH =2.5V, VOL =2.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 (Valid with a wait state or with no wait state) (Valid only with a wait state) RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Vcc=5V Figure 26.9 VCC =5V Timing Diagram (8)

Page 436 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M Table 26.24 Electrical Characteristics (VCC =3.0 to 3.6V, VSS =0V at Topr = –20 to 85oC, f(XIN)=20MH Z unless otherwise specified) lobmySr etemaraPn oitidnoCd radnatSt inU niMp yTx aM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO Am1-=6 .0-ccVV X TUO I HO Am1.0-=7 .2V X TUOC deilppadaoloN3 .3V V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO Am1=5 .0V X TUO I LO Am1.0=5 .0V X TUOC deilppadaoloN0 V V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI -0TNI, DA,5TNI GRT 0AT,4KLC-0KLC,4STC-0STC, TUO - 4AT TUO ,4LCS-0LCS,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS , ETYB VI V3=0 .4 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS , ETYB VI V0=0 .4- µA R PULLUP ecnatsiseRpu-lluP0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( VI V0=6 60 210 05k Ω fR NIX ecnatsiseRkcabdeeFX NI 0.3M Ω fR NICX ecnatsiseRkcabdeeFX NIC 0.02M Ω V MAR ybdnatSMAR egatloV CDVhguorhT5 .2V CDVhguorhttoN0 .2V I CC ylppuSrewoP tnerruC :noitidnoctnemerusaeM tuptuo,edompihc-elgnisnI rehtodnanepotfelerasnip Votdetcennocerasnip SS . X(f NI ,evawerauqs,zHM02=) noisividon 628 3A m X(f NIC ,etatstiawahtiw,zHk23=) 52=rpoT,CDVhguorhttonC ° 0.5 µA X(f NIC ,etatstiawahtiw,zHk23=) 52=rpoT,CDVhguorhtC ° 043 µA 52=rpoTs potskcolcehtnehwC° 4.00 2 µA :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

Page 437 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M Table 26.25 A/D Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6V, V SS = AVSS = 0V at Topr = –20 to 85oC, f(XIN) = 20MHZ unless otherwise specified) Table 26.26 D/A Conversion Characteristics (VCC = VREF = 3.0 to 3.6V, VSS = AVSS = 0V at Topr = –20 to 85oC, f(XIN) = 20MHZ unless otherwise specified) lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMp yTx aM -n oituloseRV FER V= CC 01s tiB LNIr orrEytiraenilnoNlargetnI) tib-8(noitcnufH&SoNV CC V= FER V3.3=2 ±B SL LNDr orrEytiraenilnoNlaitnereffiD) tib-8(noitcnufH&SoN1 ±B SL -r orrEtesffO) tib-8(noitcnufH&SoN2 ±B SL -r orrEniaG) tib-8(noitcnufH&SoN2 ±B SL R REDDAL reddaLrotsiseRV FER V= CC 80 4k Ω t VNOC emiTnoisrevnoCtib-8 9.4 µs V FER egatloVecnerefeR 0.3V CC V V AI egatloVtupnIgolanA 0V FER V dlohdnaelpmaS:H&S :SETON X(fediviD.1 NI peekot,zHM01gnideecxefi,) φ .sselrozHM01taycneuqerfDA lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU niMp yTx aM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(0 .1A m :SETON tonretrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwstlusertnemerusaeM.1 00"ottessidesugnieb 61 .deulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOCiDAehtnitibTUCVehtfineveswolf FER .)noitcennoc Table 26.27 Flash Memory Version Electrical Characteristics retemaraP dradnatS tinU niMp yTx aM )egaprep(emiTmargorP8 0 21s m )kcolbrep(emiTesarEkcolB0 50 06s m :SETON deificepsesiwrehto

Page 438 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.28 External Clock Input Table 26.29 Memory Expansion Mode and Microprocessor Mode lobmySr etemaraP dradnatS tinU niMx aM cte miTelcyCtupnIkcolClanretxE 05s n wt )H( htdiWesluP)"H"(hgiHtupnIkcolClanretxE 22s n wt )L( htdiWesluP)"L"(woLtupnIkcolClanretxE 22s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n tac1(RD – DB) = f(BCLK) X 2 – 35109 [ns] tac2(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) tac1(AD – DB) = f(BCLK) – 3510 9 [ns] tac2(AD – DB) = – 3510 X n [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) tac3(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD – DB) = f(BCLK) X 2 – 3510 X n9 [ns] (n=5 with 2 wait states and n=7 with 3 wait states) tac4(RAS – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS – DB) = – 3510 X n9 [ns] (n=1 with 1 wait state and n=3 when 2 wait states) tac4(CAD – DB) = f(BCLK ) – 3510 X l9 [ns] (l=1 with 1 wait state and l=2 with 2 wait states) f(BCLK) f(BCLK) X 2 lobmySr etemaraP dradnatS tinU niMx aM 1cat )BD-DR( )etatstiawonhtiw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 1cat )BD-DA( )etatstiawonhtiw,dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DR( )etatstiawahtiw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DA( )etatstiawahtiw,dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 3cat )BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 3cat )BD-DA( emiTsseccAtupnIataD )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsSC,dradnatsDA( )1etoN(s n 4cat )BD-SAR( )ecapsMARDagnisseccanehw,dradnatsSAR(emiTsseccAtupnIataD )1etoN(s n 4cat )BD-SAC( )ecapsMARDagnisseccanehw,dradnatsSAC(emiTsseccAtupnIataD )1etoN(s n 4cat )BD-DAC( )ecapsMARDagnisseccanehw,dradnatsDAC(emiTsseccAtupnIataD )1etoN(s n ust )KLCB-BD( emiTputeStupnIataD 03s n ust )KLCB-YDR( emiTputeStupnIYDR 04s n ust )KLCB-DLOH( emiTputeStupnIDLOH 06s n ht )BD-DR( emiTdloHtupnIataD 0s n ht )BD-SAC( emiTdloHtupnIataD 0s n ht )YDR-KLCB( emiTdloHtupnIYDR 0s n ht )DLOH-KLCB( emiTdloHtupnIDLOH 0s n dt )ADLH-KLCB( emiTyaleDtuptuOADLH 52s n :SETON rewolroetatstiawatresnI.ycneuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepo KLCB .evitagensieulavdetaluclacehtfi,)

Page 439 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.30 Timer A Input (Count Source Input in Event Counter Mode) Table 26.31 Timer A Input (Gate Input in Timer Mode) Table 26.32 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 26.33 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 26.34 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU niMx aM wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU niMx aM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiWesluP)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiWesluP)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n

Page 440 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.35 Timer B input (Count Source Input in Event Counter Mode) Table 26.36 Timer B input (Pulse Period Measurement Mode) Table 26.37 Timer B input (Pulse Width Measurement Mode) Table 26.38 A/D Trigger Input Table 26.39 Serial I/O Table 26.40 External Interrupt INTi input lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiWesluP)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiWesluP)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiWesluP)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiWesluP)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )DA( DA GRT )reggirt-errofderiuqer(htdiWesluP)"H"(hgiHtupnI 0001s n wt )LDA( DA GRT htdiWesluP)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU niMx aM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiWesluP)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiWesluP)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTpUteStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU niMx aM wt )HNI( htdiWesluP)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiWesluP)"L"(woLtupnIiTNI 052s n

Page 441 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceles-pihC 0s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceles-pihC 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n dt )ELA-KLCB( emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( emiTdloHtuptuOlangiSELA 2-s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )1etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n wt )RW( htdiWtuptuORW )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidroccasnoitauqegniwollofehtmorfdeniatboebnacseulaV.1 td(DB – WR) = f(BCLK) 10 9 – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2 10 9 – 15 [ns] See Figure 26.1 Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC, unless otherwise specified) Table 26.41 Memory Expansion Mode and Microprocessor Mode (with No Wait State)

Page 442 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceles-pihC 0s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceles-pihC 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n dt )ELA-KLCB( emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( emiTdloHtuptuOlangiSELA 2-s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )1etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n wt )RW( htdiWtuptuORW )1etoN(s n :SETON .ycneuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 [ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) td(DB – WR) = f(BCLK) – 20 th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n=5w i t h3w a i ts t a t e s ) tw( WR) = 10 X n9 – 15f(BCLK) X 2 See Figure 26.1 Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.42 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory)

Page 443 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )1etoN(s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceles-pihC 0s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceles-pihC )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DA-KLCB( emiTdloHtuptuOlangiSDR 3-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )1etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 2-s n dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )1etoN(s n ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )1etoN(s n zdt )DA-DR( emiTecnadepmI-hgiHtuptuOsserddA 8s n :SETON .ycneuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 td(DB – WR) = 10 X m9 – 25 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 –10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 10 9 – 20 [ns] th(ALE – AD) = f(BCLK ) X 2 10 9 – 10 [ns] f(BCLK) X 2 See Figure 26.1 Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.43 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting a Space with the Multiplexed Bus)

Page 444 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics VCC =3.3V )T38/C23M,38/C23M(puorG38/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU niMx aM dt )DAR-KLCB( emiTyaleDtuptuOsserddAwoR 81s n ht )DAR-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddAwoR 0s n dt )DAC-KLCB( emiTyaleDtuptuOsserddAnmuloC 81s n ht )DAC-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddAnmuloC 0s n ht )DAR-SAR( tuptuOSARretfaemiTdloHtuptuOsserddAwoR )1etoN(s n dt )SAR-KLCB( )dradnatsKLCB(emiTyaleDtuptuOSAR 81s n ht )SAR-KLCB( )dradnatsKLCB(emiTdloHtuptuOSAR 0s n t PR emiTdloH)"H"(hgiHSAR )1etoN(s n dt )SAC-KLCB( )dradnatsKLCB(emiTyaleDtuptuOSAC 81s n ht )SAC-KLCB( )dradnatsKLCB(emiTdloHtuptuOSAC 0s n dt )WD-KLCB( )dradnatsKLCB(emiTyaleDtuptuOWD 81s n ht )WD-KLCB( )dradnatsKLCB(emiTdloHtuptuOWD 3-s n ust )SAC-BD( tuptuoBDretfaemiTputeStuptuOSAC )1etoN(s n ht )BD-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSBD 7-s n ust )SAR-SAC( )hserfer(tuptuOSARerofebemiTputeStuptuOSAC )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 tsu(CAS – RAS) = f(BCLK ) X 2 – 13 [ns] th(RAS – RAD) = f(BCLK) X 2 10 9 – 13 [ns] tRP = f(BCLK) X 2 – 20 [ns] tsu(DB – CAS) = f(BCLK) 10 9 – 20 [ns] See Figure 26.1 Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 26.44 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting the DRAM Area)

Page 445 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M Figure 26.10 VCC =3.3V Timing Diagram (1) BCLK ALE -2ns.min RD 18ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) tsu(DB-BCLK) td(BCLK-RD) 30ns.min(1) CSi td(BCLK-CS) 18ns.max(1) ADi th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) 0ns.min tac2(AD-DB)(2) WR,WRL, WRH 18ns.max 0ns.min BCLK CSi td(BCLK-CS) 18ns.max ADi td(BCLK-AD) 18ns.max td(BCLK-ALE) 0ns.min 0ns.min tcyc BHE td(DB-WR) (1) DBi td(BCLK-WR) ALE -2ns.min th(WR-DB) (1) td(DB-WR) =(tcyc-20)ns.min th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2-15)ns.min Vcc=3.3V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (1) th(WR-AD) (1) tac2(RD-DB)(2) 18ns.max(1) Read Timing Write Timing NOTES: 1. Varies with operation frequency. Measurement Conditions:

VCC =3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH =1.5V, VOL =1.5V Memory Expansion Mode and Microprocessor Mode (with no wait state) NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency: tac2(RD-DB)=(tcyc/2-35)ns.max tac2(AD-DB)=(tcyc-35)ns.max 18ns.max tw(WR) (1) 18ns.max

Page 446 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M BCLK ALE 18ns.max -2ns.min RD 18ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 30ns.min(1) tac2(RD-DB)(2) CSi td(BCLK-CS) 18ns.max(1) ADi 18ns.max(1) th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)(2) WR,WRL, WRH 18ns.max 0ns.min BCLK CSi 18ns.max ADi 18ns.max 0ns.min 0ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min Vcc=3.3V th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (1) td(DB-WR) (1) th(WR-DB) (1) th(WR-AD) (1) td(DB-WR) =(tcyc x n-20)ns.min (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) t h(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states NOTES: 1. Varies with operation frequency. Measurement Conditions:

VCC =3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH =1.5V, VOL =1.5V NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) th(BCLK-ALE) Read Timing Write Timing Memory Expansion Mode and Microprocessor Mode (with a wait state) tw(WR) (1) Figure 26.11 VCC =3.3V Timing Diagram (2)

Page 447 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M BCLK CSi 18ns.max ADi 18ns.max RD 18ns.max -3ns.min th(BCLK-AD) 0ns.min 0ns.min BHE ADi /DBi 0ns.min 18ns.max 0ns.min BCLK CSi 18ns.max ADi 18ns.max 0ns.min 0ns.mintcyc BHE ADi /DBi Data output WR,WRL, WRH Address AddressData input 30ns.min td(BCLK-RD) th(WR-CS) (1) Address td(AD-ALE)(1) Address tsu(DB-BCLK) tac3(RD-DB)(1) tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 18ns.max ALE -2ns.min td(BCLK-ALE) th(ALE-AD)(1) Vcc=3.3V td(BCLK-CS) td(AD-ALE)(1) th(ALE-AD)(1) th(BCLK-RD) th(RD-AD)(1) th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)(1) td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) () td(DB-WR) (1) th(WR-DB) (1) th(BCLK-ALE) th(BCLK-ALE) tcyc NOTES: 1. Varies with operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (m=3 with 2 wait states and m=5 with 3 wait states) Measurement Conditions:

VCC =3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH =1.5V, VOL =1.5V NOTES: 1. Varies with operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states) Read Timing Write Timing Memory Expansion Mode and Microprocessor Mode (with a wait state, when accessing an external memory and using the multiplexed bus) 18ns.max tac3(AD-DB)(1) Figure 26.12 VCC =3.3V Timing Diagram (3)

Page 448 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M B C L K D W D B M A i V c c = 3 . 3 V R A S C A S L C A S H H i - Z ta c C A S D B s m a th B C L K C A D 0 n s . m i n t c y c td B C L K R A D ta c R A S D B R o w a d d r e s s C o l u m n a d d r e s s th B C L K R A D 0 n s . m i n n s m a td B C L K C A D s m a td B C L K R A S s m a td B C L K C A S th( R A S R A D ) tR ta c C A D D B th B C L K R A S 0 n s . m i n th B C L K C A S 0n s . m i n 0 n s . m i n ts u D B B C L K 30n s m i th C A S D B M e a s u r e m e n t C o n d i t i o n s : VC C = t o V I n p u t h i g h a n d l o w v o l t a g e VI H = V VI V O u t p u t h i g h a n d l o w v o l t a g e VO H = V VO V R e a d T i m i n g M e m o r y Ex p a ns i o n M o d e a n d M i c r o p r o c e s s o r M o d e W i t h w a i t s t a t e s w h e n a c c e s s i n g t h e D R A M a r e a N O T E S : V a l u e s g u a r a n t e e d o n l y w h e n t h e m i c r o c o m p u t e r i s u s e d i n d e p e n d e n t l y A m a x i m u m o f n s i s g u a r a n t e e d f o r t h e f o l l o w i n g s td B C L K R A S ts u D B B C L K td B C L K C A S ts u D B B C L K td B C L K C A D ts u D B B C L K I t v a r i e s w i t h t h e o p e r a t i o n f r e q u e n c y ta c R A S D B t c y c x m n s m a x m w i t h w a i t s t a t e a n d m w i t h w a i t s t a t e s ta c C A S D B t c y c x n n s m a x n w i t h w a i t s t a t e a n d n w i t h w a i t s t a t e s ta c C A D D B t c y c x l n s m a x l w i t h w a i t s t a t e a n d l w i t h w a i t s t a t e s th R A S R A D t c y c n s m i n tR t c y c x n s m i n Figure 26.13 VCC =3.3V Timing Diagram (4)

Page 449 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M BCLK DW DB MAi Vcc=3.3V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 18ns.max th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) 0ns.min 18ns.max td(BCLK-CAD) 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) tRP (1) 18ns.max td(BCLK-DW) tsu(DB-CAS)(1) th(BCLK-RAS) 0ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) 0ns.min Row address Column address NOTES: 1. Varies with operation frequency. th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Measurement Conditions:

VCC =3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH =1.5V, VOL =1.5V Write Timing Memory Expansion Mode and Microprocessor Mode (With 2 wait states, when accessing the DRAM area) th(RAS-RAD) (1) Figure 26.14 VCC =3.3V Timing Diagram (5)

Page 450 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M tcyc 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min tsu(CAS-RAS)(1) 18ns.max tcyc td(BCLK-CAS) tsu(CAS-RAS)(1) th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min 18ns.max td(BCLK-RAS) BCLK DW Vcc=3.3V RAS CASL CASH BCLK DW RAS CASL CASH NOTES: 1. Varies with operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Measurement Conditions:

VCC =3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH =1.5V, VOL =1.5V Refresh Timing (CAS-before-RAS refresh) Memory Expansion Mode and Microprocessor Mode NOTES: 1. Varies with operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Refresh Timing (Self-refresh) Figure 26.15 VCC =3.3V Timing Diagram (6)

Page 451 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M tsu(D–C) TAiIN input TAiOUT input In event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When counting on falling edge) TAiIN input (When counting on rising edge) TAiOUT input (Counter increment/ decrement input) INTi input AD TRG input Vcc=3.3V NMI input 2 clock cycles + 300ns or more 2 clock cycles + 300ns or more ("L" width) Figure 26.16 VCC =3.3V Timing Diagram (7)

Page 452 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics)T38/C23M,38/C23M(puorG38/C23M Measurement Conditions:

VCC=3.0 to 3.6V
Input high and low voltage: VIH=2.4V, VIL=0.6V
Output high and low voltage: VOH =1.5V, VOL =1.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 (Valid with a wait state and no wait state) (Valid only with a wait state) RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Hi–Z th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Vcc=3.3V Figure 26.17 VCC =3.3V Timing Diagram (8)

Page 453 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M

26.2 Electrical Characteristics (M32C/83T)

Table 26.45 Absolute Maximum Ratings lobmySr etemaraPn oitidnoCe ulaVt inU V CC egatloVylppuSV CC VA= CC 0.6ot3.0- V VA CC egatloVylppuSgolanAV CC VA= CC 0.6ot3.0- V VI egatloVtupnIV NC,TESER SS 0P,ETYB, 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7, 3P 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0- 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( V, FER X, NI Vot3.0- CC 3.0+V 7P 0 7P, 1 0.6ot3.0-V VO egatloVtuptuO0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )1( X, TUO Vot3.0- CC 3.0+V dPn oitapissiDrewoP C°52=rpoT0 04W m rpoTe rutarepmeTtneibmAgnitarepO noisrevTo t04-5 8C ° gtsTe rutarepmeTegarotS 051ot56-C ° :SETON .egakcapnip-441ehtnidedivorpera51Pot11P.1

Page 454 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M Table 26.46 Recommended Operating Conditions (VCC =4.2 to 5.5V, VSS =0V at Topr = -40 to 85oC (T version) unless otherwise specified) lobmySr etemaraP dradnatS tinU.niM. pyT. xaM V CC egatloVylppuS 2.40 .55 .5V VA CC egatloVylppuSgolanA V CC V V SS egatloVylppuS 0V VA SS egatloVylppuSgolanA 0V V HI )"H"(hgiHtupnI egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4, 21P 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( X, NI , VNC,TESER SS ETYB, V8.0 CC V CC V 7P 0 7P, 1 V8.0 CC 0.6 V LI )"L"(woLtupnI egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4, 21P 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( X, NI , VNC,TESER SS ETYB, 0V 2.0 CC V I )kaep(HO tuptuOkaeP )"H"(hgiH tnerruC )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01-A m I )gva(HO tuptuOegarevA )"H"(hgiH tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5-A m I )kaep(LO woLtuptuOkaeP tnerruC)"L"( )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01A m I )gva(LO tuptuOegarevA )"L"(woL tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5A m X(f NI )t upnIkcolCniaM ycneuqerF V CC V5.5ot2.4=0 2 3z HM X(f NIC )y cneuqerFnoitallicsOkcolCbuS 867.230 5z Hk :SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(HO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08-ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(LO 8P,7P,6P,5P,4P,3Prof 0 8Pot 4 .sselroAm08ebtsum31Pdna21P, IlatoT )kaep(HO 7P,6P,5P,4P,3Prof 2 7Pot 7 8P, 0 8Pot 4 .sselroAm08-ebtsum31Pdna21P, .3V HI Vdna LI 8Profecnerefer 7 8Pnehwseilppa 7 .troptupnielbammargorpasadesusi 8PnehwylppatonseodtI 7 Xsadesusi NIC . .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.4

Page 455 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M VCC =5VTable 26.47 Electrical Characteristics (VCC = 4.2 to 5.5 V, VSS = 0V at Topr = –40 to 85oC(T version), f(XIN)=32MH Z unless otherwise specified) lobmySr etemaraPn oitidnoCd radnatSt inU niMp yTx aM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO Am5-=V CC 0.2-V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO 002-= µAV CC 3.0- X TUO I HO Am1-=0 .3V X TUOC deilppadaoloN3 .3V V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO 002= µA5 4.0V X TUO I LO Am1=0 .2V X TUOC deilppadaoloN0 V V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT -0KLC,4STC-0STC, 0AT,4KLC TUO 4AT- TUO -0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS,4DxR 2.00 .1V TESER 2.08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI ,TESER, VNC SS ETYB, VI V5=0 .5 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI ,TESER, VNC SS ETYB, VI V0=0 .5- µA R PULLUP ecnatsiseRpu-lluP0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( VI V0=0 30 57 61k Ω fR NIX ecnatsiseRkcabdeeFX NI 5.1M Ω fR NICX ecnatsiseRkcabdeeFX NIC 01M Ω V MAR egatloVybdnatSMAR 5.2V I CC ylppuSrewoP tnerruC :snoitidnoctnemerusaeM tuptuo,edompihc-elgnisnI rehtodnanepotfelerasnip Votdetcennocerasnip SS X(f NI ,evawerauqs,zHM23=) noisividon 044 5A m X(f NIC ,etatstiawahtiw,zHk23=) 52=rpoTC ° 074 µA spotskcolcehtnehwC°52=rpoT 4.00 2 µA :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

Page 456 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M VCC =5V Table 26.48 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5V, Vss = AVSS = 0V at Topr = –40 to 85oC (T version), f(XIN) = 32MHZ unless otherwise specified) Table 26.49 D/A Conversion Characteristics (VCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V at Topr = –40 to 85oC (T version), f(XIN) = 32MHZ unless otherwise specified) Table 26.50 Flash Memory Version Electrical Characteristics lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU niMp yTx aM -n oituloseRV FER V= CC 01s tiB LNIr orrEytiraenilnoNlargetnIV FER V= CC V5= NA 0 NAot 7 NA 0XE NA, 1XE BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orrEytiraenilnoNlaitnereffiD 1±B SL -r orrEtesffO 3±B SL -r orrEniaG 3±B SL R REDDAL reddaLrotsiseRV FER V= CC 80 4k Ω t VNOC emiTnoisrevnoCtib-01 1.2 µs t VNOC emiTnoisrevnoCtib-8 8.1 µs t PMAS emiTelpmaS 2.0 µs V FER egatloVecnerefeR 2V CC V V AI egatloVtupnIgolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM61gnideecxefi,) φ .sselrozHM61taycneuqerfDA lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU niMp yTx aM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV ylppuSrewoPecnerefeR tnerruCtupnI )1etoN(5 .1A m :SETON ehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwstlusertnemerusaeM.1 00"ottessidesugniebtonretrevnocA/D 61 .deulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOCiDAehtnitibTUCVehtfineveswolf FER .)noitcennoc retemaraP dradnatS tinU niMp yTx aM )egaprep(emiTmargorP8 0 21s m )kcolbrep(emiTesarEkcolB0 50 06s m :SETON V.1 CC deificepsesiwrehtosselnu,C°06ot0=rpoTtaV5.5ot2.4=

Page 457 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M VCC =5V Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –40 to 85oC (T version) unless otherwise specified) Table 26.51 External Clock Input lobmySr etemaraP dradnatS tinU niMx aM cte miTelcyCtupnIkcolClanretxE 33s n wt )H( htdiWesluP)"H"(hgiHtupnIkcolClanretxE 31s n wt )L( htdiWesluP)"L"(woLtupnIkcolClanretxE 31s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n

Page 458 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M VCC =5V lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU niMx aM wt )HAT( iAT NI htdiWesluP)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiWesluP)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU niMx aM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiWesluP)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiWesluP)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –40 to 85oC (T version) unless otherwise specified) Table 26.52 Timer A Input (Count Source Input in Event Counter Mode) Table 26.53 Timer A Input (Gate Input in Timer Mode) Table 26.54 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 26.55 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 26.56 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Page 459 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M VCC =5V Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –40 to 85oC (T version) unless otherwise specified) Table 26.57 Timer B Input (Count Source Input in Event Counter Mode) Table 26.58 Timer B Input (Pulse Period Measurement Mode) Table 26.59 Timer B Input (Pulse Width Measurement Mode) Table 26.60 A/D Trigger Input Table 26.61 Serial I/O Table 26.62 External Interrupt INTi Input lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiWesluP)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiWesluP)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiWesluP)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiWesluP)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiWesluP)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiWesluP)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )DA( DA GRT )reggirt-errofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiWesluP)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU niMx aM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiWesluP)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiWesluP)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTpUteStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU niMx aM wt )HNI( htdiWesluP)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiWesluP)"L"(woLtupnIiTNI 052s n

Page 460 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M P10 30pF P14 P13 P12 P15 P11 Note 1 NOTES: 1. P11 to P15 are provided in the 144-pin package only. Figure 26.18 P0 to P15 Measurement Circuit

Page 461 884fo6002,13.naJ13.1.veR 1310-4300B90JER 26. Electrical Characteristics (M32C/83T))T38/C23M,38/C23M(puorG38/C23M tsu(D–C) TAiIN input TAiOUT input In event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN input (When counting on the falling edge) TAiIN input (When counting on the rising edge) TAiOUT input (Counter increment/ decrement input) INTi input AD TRG input Vcc=5V NMI input 2 clock cycles + 300ns or more ("L" width) 2 clock cycles + 300ns or more Figure 26.19 VCC = 5 V Timing Diagram(1)

Page 462 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M 27. Precautions

27.1 Processor Mode

27.1.1 Microprocessor Mode

SFR, internal RAM and external space can be accessed when in microprocessor mode. The internal ROM cannot be accessed. The internal ROM cannot be accessed, despite entering memory expansion mode or single-chip mode , if the microcomputer begins operation in microprocessor mode while the CNV SS is held high ("H") after reset. 27. Precautions (Processor Mode)

Page 463 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M

27.2 Bus

27.2.1 HOLD Signal

When entering microprocessor mode or memory expansion mode from single-chip mode and using HOLD input, set the PM01 to PM00 bits to "112" (microprocessor mode) or to "102" (memory expansion mode) after setting the PD4_0 to PD4_7 bits in the PD4 register and the PD5_0 to PD5_2 bits in the PD5 register to "0" (input mode). P40 to P47 (A16 to A22, A23, CS0 to CS3, MA8 to MA12) and P50 to P52 (RD/WR/BHE, RD/WRL,WRH) do not enter a high-impedance state even when an "L" signal is applied to the HOLD pin, if the PM01 to PM00 bits are set to "11 2" (microprocessor mode) or to "102" (memory expansion mode) after setting the PD4_0 to PD4_7 bits in the PD4 register and the PD5_0 to PD5_2 bits in the PD5 register to "1" (output mode) in single-chip mode.

27.2.2 External Bus

The internal ROM cannot be read when an "H" signal is applied to the CNVSS pin and the hardware reset (hardware reset 1 or hardware reset 2) occurs. 27. Precautions (Bus)

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27.3 SFR

27.3.1 100-Pin Package Set address space for 03CB16, 03CE16, 03CF 16, 03D216, 03D316 to "FF16" after reset when using the 100-pin package. 03DC16 must be set to "0016" after reset.

27.3.2 Register Settings

Table 27.1 lists registers containing bits which can only be written to. Set these registers with immediate values. When establishing the next value by altering the present value, write the present value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 27.1 Registers with Write-only Bits Register Address Register Address WDTS register 000E 16 U2BRG register 0339 16 G0RI register 00EC 16 U2TB register 033B 16, 033A16 G1RI register 012C 16 UDF register 0344 16 G2TB register 016D 16, 016C16 TA0 register(1) 034716, 034616 G3TB register 017D 16, 017C16 TA1 register(1) 034916, 034816 U4BRG register 02F9 16 TA2 register(1) 034B16, 034A16 U4TB register 02FB 16, 02FA16 TA3 register(1) 034D 16, 034C16 TA11 register 0303 16, 030216 TA4 register(1) 034F16, 034E16 TA21 register 0305 16, 030416 U0BRG register 0369 16 TA41 register 0307 16, 030616 U0TB register 036B 16, 036A16 DTT register 030C 16 U1BRG register 02E9 16 ICTB2 register 030D 16 U1TB register 02EB 16, 02EA16 U3BRG register 0329 16 AD0CON2 register 0394 16 U3TB register 032B 16, 032A16 NOTES : 1. In one-shot timer mode and pulse width modulation mode only. 27. Precautions (SFR)

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27.4 Clock Generation Circuit

27.4.1 PLL Frequency Synthesizer

Stabilize supply voltage when using the PLL frequency synthesizer. The ripple of supply voltage at 5V must be less than 10kHz in frequency, 0.5V (peak to peak) in voltage fluctuation range, and 1V/ms in voltage fluctuation rate. The ripple of supply voltage at 3.3V must be less than 100Hz in frequency, 0.2V (peak to peak) in voltage fluctuation range, and 0.1V/ms in voltage fluctuation rate.

27.4.2 Power Consumption Control

When resetting the microcomputer to exit stop mode, apply an "L" signal to the RESET pin until the main clock oscillation stabilizes.
Write at least 4 NOP instructions after the WAIT instruction or instructions to set the CM10 bit in the CM1 register to "1" (all clocks stop). When entering wait mode or stop mode, the instruction queue reads ahead to instructions following the WAIT instruction and instructions to set the CM10 bit to "1", and the program stops. The next instruction may be executed before entering wait mode or stop mode, depend- ing on the combination of instructions and their execution timing.
The followings are suggestions for reducing power consumption when programming or designing sys- tems: Ports: I/O ports maintains the same state despite the microcomputer entering wait mode or stop mode. Current flows through active output ports. Feedthrough current flows through input ports in a high-impedance state. Set unused ports as input ports and stablize electrical potential before entering wait mode or stop mode. A/D Converter: If the A/D conversion is not performed, set the VCUT bit in the AD0CON1 register to "0"(no V REF connection). Set the VCUT bit to "1" (VREF connection) and wait at least 1µs before starting the A/D conversion. D/A Converter: Set the DAi bit (i=0 to 1) in the DACON register to "0" (output disabled) and set the DAi register to "0016" when the D/A conversion is not performed. Peripheral Function Stop: Set the CM02 bit in the CM0 register while in wait mode to stop unneces- sary peripheral functions. However, this does not reduce power consumption because the peripheral function clock (fc32) generating from the sub clock does not stop. When in low-speed mode and low- power consumption mode, do not enter wait mode when the CM02 bit is set to "1" (peripheral clock stops in wait mode). External Clock: When an external clock is selected as the CPU clock, set the CM05 bit in the CM0 register to "1" (main clock stops). This disables the X OUT pin and reduces power consumption. (When using an external clock input, the clock is applied regardless of the CM05 bit setting.) 27. Precautions (Clock Generation Circuit)

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27.4.3 Wait Mode

When entering wait mode, the instruction queue reads ahead to instructions following the WAIT instruc- tion, and the program stops. Write at least 4 NOP instructions after WAIT instruction.

27.4.4 Stop Mode

If stop mode is exited by any reset, apply an "L" signal to the RESET pin until a main clock oscillation is stabilized enough.
When entering stop mode, the instruction queue reads ahead to instructions following the instruction setting the CM10 bit in the CM1 register to "1" (all clocks stopped), and the program stops. When the microcomputer exits stop mode, the instruction lined in the instruction queue is executed before the interrupt routine for recovery is done. Write the JMP.B instruction as follows, after the instruction setting the CM10 bit to "1". e.g., bset 0, prcr ; protection removed fset I ; I flag set bset 0, cm1 ; all clocks stopped (stop mode) jmp.b LABEL_001 ; jmp.b instruction executed (no instruction between jmp.b and LABEL) LABEL_001; nop ; nop (1) nop ; nop (2) nop ; nop (3) nop ; nop (4) mov.b #0, prcr ; Protection set 27. Precautions (Clock Generation Circuit)

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27.5 Protection

The PRC2 bit in the PRCR register is changed to "0" (write disable) when an instruction is written to any address after the PRC2 bit is set to "1" (write enable). Write instruction immediately after setting the PRC2 bit to "1" to change registers protected by the PRC2 bit. Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the following instruction. 27. Precautions (Protection)

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27.6 Interrupts

27.6.1 ISP Setting

After reset, the ISP is set to "00000016". The program runs out of control if an interrupt is acknowledged before the ISP is set. Therefore, the ISP must be set before an interrupt request is acknowledged. Set the ISP to an even address, which allows interrupt sequences to be executed at a higher speed. To use NMI interrupt, set the ISP at the beginning of the program. The NMI interrupt can be acknowl- edged after the first instruction has been executed after reset.

27.6.2 NMI Interrupt

NMI interrupt cannot be denied. Connect the NMI pin to VCC via a resistor (pull-up) when not in use.
The P8_5 bit in the P8 register indicates the NMI pin value. Read the P8_5 bit only to determine the pin level after a NMI interrupt occurs.
H" and "L" of a signal applied to the NMI pin must be over 2 CPU clock cycles + 300 ns wide.

27.6.3 INT Interrupt

Edge sensitive "H" and "L" of a signal applied to the INT0 to INT5 pins must be at least 250 ns wide, regardless of the CPU clock.
Level sensitive "H" and "L" of a signal applied to the INT0 to INT5 pins must be at least 1 CPU clock cycle + 200 ns wide. For example, "H" and "L" must be at least 234ns wide if XIN=30MHz with no division.
The IR bit may change to "1" (interrupt requested) when switching the polarity of the INT0 to INT5 pins. Set the IR bit to "0" (no interrupt requested) after selecting the polarity. Figure 27.1 shows an example of the switching procedure for the INT interrupt. Figure 27.1 Switching Procedure for INT Interrupt Set the POL bit in the INTiIC register Set the IR bit in the INTiIC register to "0" Set the ILVL2 to ILVL0 bits to "0012" (level 1) to "1112" (level 7) (INT interrupt request acknowledgement enabled) Set the ILVL2 to ILVL0 bits in the INTiIC register (i = 0 to 5) to "000 2" (level 0) (INT interrupt disabled) 27. Precautions (Interrupts)

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27.6.4 Watchdog Timer Interrupt

Reset the watchdog timer after a watchdog timer interrupt occurs.

27.6.5 Changing Interrupt Control Register

To change the interrupt control register while the interrupt request is disabled, follow the instructions below. Changing Bits Except IR Bit When an interrupt request occurs while executing an instruction, the IR bit may not be set to "1" (interrupt requested) and the interrupt may be ignored. If this is a problem, use the following instruc- tions to change the register: AND, OR, BCLR, BSET Changing IR bit The IR bit may not change to "0" (no interrupt requested) depending on the instructions written. If this is a problem, use the following instruction to change the register: MOV

27.6.6 Changing IIOiIR Register (i = 0 to 11)

Use the following instructions to set bits 1 to 7 in the IIOilR register to "0" (no interrupt requested). AND, BCLR

27.6.7 Changing RLVL Register

The DMAII bit is indeterminate after reset. When using the DMAII bit to generate an interrupt, set the interrupt control register after setting the DMACII bit to "0" (interrupt priority level 7 available for inter- rupts). 27. Precautions (Interrupts)

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27.7 DMAC

Set DMAC-associated registers while the MDi1 to MDi0 bits (i=0 to 3) in the channel to be used are set to "002" (DMA disabled). Set the MDi1 to MDi0 bits to "012" (single transfer) or "112" (repeat transfer) at the end of the setup procedure to start DMA requests.
Do not set the DRQ bit in the DMiSL register to "0" (no request). When a DMA request is generated but the receiving channel is not ready to receive(1), the DMA transfer does not occur and the DRQ bit is set to "0". NOTES: 1. The MDi1 to MDi0 bits are set to "002" or the DCTi register is set to "000016" (transferred 0 times).
To start a DMA transfer by a software trigger, set the DSR bit and DRQ bit in the DMiSL register to "1" simultaneously. e.g., OR.B #0A0h,DMiSL Set the DSR and DRQ bits to "1" simultaneously.
Do not generate a channel i DMA request when setting the MDi1 to MDi0 bits in the DMDj register (j=0,1) corresponding to channel i to "01 2" (single transfer) or "112" (repeat transfer), if the DCTi register of channel i is set to "1".
Select the peripheral function which causes the DMA request after setting the DMA-associated registers. If none of the conditions above (setting INT interrupt as DMA request source) apply, do not write "1" to the DCTi register.
Enable DMA(2) after setting the DMiSL register (i=0 to 3) and waiting 6 BCLK cycles or more by pro- gram. NOTES: 2. DMA is enabled when the values set in the MDi1 to MDi0 bits in the DMDj register are changed from "002" (DMA disabled) to "012" (single transfer) or "112" (repeat transfer). 27. Precautions (DMAC)

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27.8 Timer

27.8.1 Timers A and B

The timers stop after reset. Set the TAiS(i=0 to 4) bit or TBjS(j=0 to 5) bit in the TABSR register or TBSR register to "1" (starts counting) after setting operation mode, count source and counter. Set the following registers and bits while the TAiS bit or TBjS bit is set to "0" (stops counting).

TAiMR, TBjMR register
TAi, TBj register
UDF register
TAZIE, TA0TGL, TA0TGH bits in the ONFS register
TRGSR register

27.8.2 Timer A

27.8.2.1 Timer A (Timer Mode)

(a) The TAiS bit (i=0 to 4) in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit to "1" (starts counting) after selecting operation mode and setting the TAi register. (b) The TAi register indicates the counter value during counting at any given time. However, the counter will read "FFFF16" when reloading. The setting value can be read after setting the TAi regis- ter while the counter is stopped and before the counter starts counting. (c) TA1OUT , TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is applied to the NMI pin while INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three-phase output by an "L" signal applied to the NMI pin)

27.8.2.2 Timer A (Event Counter Mode)

(a) TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit to "1" (starts counting) after selecting operation mode and setting the TAi register. (b) The TAi register indicates the counter values during counting at any given time. However, the counter will read "FFFF16" during underflow and "000016" during overflow, when reloading. The setting value can be read after setting the TAi register while the counter is stopped and before the counter starts counting. (c) The TA1 OUT , TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is applied to the NMI pin while the INV03 to INV02 bit in the INVC0 register are set to "112" (forced cutoff of the three-phase output by an "L" signal applied to the NMI pin).

27.8.2.3 Timer A (One-shot Timer Mode)

(a) TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set TAiS bit to "1" (starts counting) after selecting operation mode and setting the TAi register. (b) The followings occur when setting the TABSR register to "0" (stops counting) while counting:

The counter stops counting and the microcomputer reloads contents of the reload register.
The TAiOUT pin becomes low ("L").
The IR bit in the TAiIC register is set to "1" (interrupt requested) after 1 CPU clock cycle. (c) The output of the one-shot timer is synchronized with an internal count source. When set to an external trigger, there is a delay of 1 count source cycle maximum, from trigger input to the TAiIN pin to the one-shot timer output. 27. Precautions (Timer)

Page 472 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M (d) The IR bit is set to "1" when the timer operation mode is selected as follows:

one-shot timer mode is selected after reset.
timer mode is switched to one-shot timer mode.
event counter mode is switched to one-shot timer mode. Therefore, set the IR bit to "0" by program when generating a timer Ai interrupt (IR bit), if the timer operation mode is selected as is described above. (e) When a trigger is generated while counting, the reload register reloads and continues counting after the counter has downcounted once following a re-trigger. To generate a trigger while counting, wait at least 1 count source cycle after the previous trigger has been generated and generate a re- trigger. (f) The TA1 OUT , TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is applied to the NMI pin while the INV03 to INV02 bits in the INVC0 register is set to "112" (forced cutoff of the three-phase output by an "L" signal applied to the NMI pin). (g) If an external trigger input is selected to start counting in timer A one-shot timer mode, do not provide another external trigger input again for 300 ns before the timer A counter value reaches "0000 16". One-shot timer may stop counting.

27.8.2.4 Timer A (Pulse Width Modulation Mode)

(a) TAiS(i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set TAiS bit to "1" (starts counting) after selecting an operating mode and setting the TAi register. (b) The IR bit is set to "1" when the timer operation mode is selected as follows:

PWM mode is selected after reset.
timer mode is switched to PWM mode.
event counter mode is switched to PWM mode. Therefore, set the IR bit to "0" by program when generating a timer Ai interrupt (IR bit), if the timer operation mode is selected as is described above. (c) The followings occur when the TAiS bit is set to "0" (stops counting) while PWM pulse is output:
The counter stops counting.
The IR bit changes to "1" and the output level changes to low ("L") when TAiOUT pin is held high ("H").
The IR bit and the output level remain unchanged when TAiOUT pin is held low ("L"). (d) The TA1OUT , TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is applied to the NMI pin while the INV03 to INV02 bits in the INVC0 register are set to "1" (three-phase output forced cutoff enabled). 27. Precautions (Timer)

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27.8.3 Timer B

27.8.3.1 Timer B (Timer Mode, Event Counter Mode)

(a) TBiS (i=0 to 5) bit is set to "0" (stops counting) after reset. Set TBiS bit to "1" (starts counting) after selecting an operation mode and setting the TBi register. The TB0S to TB2S bits are the bits 5 to 7 in the TABSR register. The TB3S to TB5S bits are bits 5 to 7 in the TBSR register. (b) The TBi register indicates the counter value during counting at any given time. However, the counter will read "FFFF16" when reloading . The setting value can be read after setting the TBi register while the counter stops and before the counter starts counting.

27.8.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode)

(a) The IR bit in the TBiIC register is set to "1" (overflow) when the valid edge of a pulse to be mea- sured is input and when the timer Bi counter overflows. The MR3 bit in the TBiMR register deter- mines the interrupt source within an interrupt service routine. (b) Count overflow on a different timer if an interrupt source cannot be determined by the MR3 bit, such as when a pulse to be measured is input at the same time the timer overflows. (c) To set the MR3 bit in the TBiMR register to "0" (no overflow), set when the TBiS bit is set to "1" (count starts) and at least one count is counted after the MR3 bit is set to "1" (overflow). (d) The IR bit in the TBiIC register is used to detect overflow only. Use the MR3 bit only to determine interrupt source within an interrupt service routine. (e) Indeterminate values are transferred to the reload register during the first valid edge input following the start of the count. Timer B interrupt request is not acknowledged at this time. (f) The counter value is indeterminate at the start of a count. Therefore, the MR3 bit may change to "1" (overflow) and cause timer B interrupt requests to be generated, until a valid edge is input after the count begins. (g) The IR bit may be set to "1" (interrupt requested) if the MR1 to MR0 bits in the TBiMR register are set to a different value after a count begins. If the MR1 to MR0 bits are rewritten, but to the same value as before, the IR bit remains unchanged. (h) Pulse width measurement measures pulse width continuously. Use program to determine whether measurement results are high ('"H") or low ("L"). 27. Precautions (Timer)

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27.9 Three-Phase Motor Control Timer Functions

27.9.1 Changing TAi and TAi1 (i=1, 2, 4) Registers

Do not write to the TAi and TAi1 registers at the same time timer B2 underflows. Follow the procedure below when rewriting the TAi1 register. (1) Write value to the TAi1 register (2) Wait 1 timer Ai count source cycle (3) Write the same value to the TAi1 register again 27. Precautions (Three-Phase Motor Control Functions)

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27.10 Serial I/O

27.10.1 Clock Synchronous Serial I/O Mode

27.10.1.1 Transmission / Reception

When the RTS function is used while an external clock is selected, the output level of the RTSi pin is held low ("L") indicating that the microcomputer is ready for reception. The transmitting microcomputer is notified that reception is possible. The output level of the RTSi pin becomes high ("H") when recep- tion begins. Therefore, connecting the RTSi pin to the CTSi pin of the transmitting microcomputer synchronizes transmission and reception. The RTS function is disabled if an internal clock is selected. The RTS2 pin and CLK2 pin are placed in high-impedance states when an "L" signal is applied to the NMI pin while the INV02 to INV01 bits in the INVC0 register are set to "112" (forced cutoff of the three- phase output by low-level signal ("L") applied to NMI pin).

27.10.1.2 Transmission

When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the external clock is held high ("H") or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the transfer clock and received on the falling edge) and the external clock is held low ("L"), meet the following conditions:

Set the TE bit in the UiC1 register to "1" (transmit enabled)
Set the TI bit in the UiC1 register to "0" (data in the UiBT register)
Apply "L" signal to the CTSi pin if the CTS function is selected

27.10.1.3 Reception

Activating the transmitter in clock synchronous serial I/O mode generates the shift clock. Therefore, set for transmission even if the microcomputer is used for reception only. Dummy data is output from the TxDi pin while receiving. If an internal clock is selected, the shift clock is generated when the TE bit in the UiC1(i=0 to 2) registers is set to "1" (receive enable) and dummy data is set in the UiTB register. If an external clock is selected, the shift clock is generated when the external clock is input into CLKi pin while the TE bit is set to "1" (receive enable) and dummy data is set in the UiTB register. When receiving data consecutively while the RE bit in the UiC1(i=0 to 2) register is set to "1" (data in the UiRB register) and the next data is received by the UARTi reception register, an overrun error occurs and the OER bit in the UiRB register becomes "1" (overrun error). In this case, the UiRB register is indeterminate. When overrun error occurs, program both reception and transmission regis- ters to retransmit earlier data. The IR bit in the SiRIC does not change when an overrun error occurs. When receiving data consecutively, feed dummy data to the low-order byte in the UiTB register every time a reception is made. When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the external clock is held high ("H") or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the transfer clock and received on the falling edge) and the external clock is held low ("L"), meet the following conditions:

Set the RE bit in the UiC1 register to "1" (receive enabled)
Set the TE bit in the UiC1 register to "1" (transmit enabled)
Set the TI bit in the UiC1 register to "0" (data in the UiTB register) 27. Precautions (Serial I/O)

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27.10.2 UART Mode

Set the UiERE bit in the UiC1 register after setting the UiMR register.
The RTS2 and CLK2 pins will enter a high-impedance state when an "L" signal is applied to the NMI pin while the INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three- phase output by an "L" signal applied to the NMI pin).

27.10.3 Special Mode 2

The RTS2 and CLK2 pins will enter high-impedance states when an "L" signal is applied to the NMI pin while the INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three-phase output by an "L" signal applied to the NMI pin). 27. Precautions (Serial I/O)

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27.11 A/D Converter

Set the ADiCON0 (i=0,1) (bit 6 excluded), ADiCON1, and ADiCON2 registers while the A/D conversion is stopped (before trigger is generated).
Wait a minimum of 1µs before starting the A/D conversion when changing the VCUT bit in the ADiCON1 register from "0" (VREF no connection) to "1" (VREF connection). Change the VCUT bit from "1" to "0" after the A/D conversion is completed.
Insert capacitors between pins AVCC , VREF , analog input pin ANjk (j=none, 0, 2, 15; k=0 to 7) and AVSS to prevent latch-ups and malfunctions due to noise and to minimize conversion errors. The same ap- plies to pins VCC and VSS . Figure 27.2 shows the procedure. Microcomputer Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF (reference) Note 2: Use thick and shortest possible wiring to connect capacitors. VCC VSS AV CC AV SS VREF ANjk C4 C1 C2 Figure 27.2 Use of Capacitors to Reduce Noise
Set the bit in the port direction register, which corresponds to the pin being used as the analog input, to "0" (input mode). Set the bit in the port direction register, which corresponds to the ADTRG pin, to "0" (input mode) if the TRG1 to TRG0 bits in the ADiCON2 register are set to "002" (ADTRG ).
When generating a key input interrupt, do not use the AN4 to AN7 pins as analog input pins (key input interrupt request is generated when the A/D input voltage becomes "L").
When the sample and hold function is not activated, Ø AD frequency must be 250kHz or more. If the sample and hold function is activated, Ø AD frequency must be 1MHz or more.
Set the CH2 to CH0 bits in the ADiCON0 register or the SCAN1 to SCAN0 bits in the ADiCON1 register to select analog input pins again when changing A/D conversion mode. 27. Precautions (A/D Converter)

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Wrong values are stored in the ADij register (i=0,1; j=0 to 7) if the CPU reads the ADij register while the ADij register is storing results from a completed A/D conversion. This occurs when the CPU clock is set to a divided main clock or a sub clock. In one-shot mode or single sweep mode, read the corresponding ADij register after verifying that the A/ D conversion has been completed. The IR bit in the ADiIC register can determine the completion of the A/D conversion. In repeat mode, repeat sweep mode 0 and repeat sweep mode 1, use an undivided main clock as the CPU clock.
Conversion results of the A/Di is indeterminate if the ADST bit in the ADiCON0 register (i=0,1) is set to "0" (A/D conversion stopped) and the conversion is forcibly terminated by program. The ADij register (j=0 to 7) not performing an A/D conversion may also be indeterminate. If A/Di is forcibly terminated, do not use any values obtained from the ADij registers. If either A/D0 or A/D1 is forcibly terminated while the ADS bit in the ADiCON2 register is set to "0" (channel replacement disabled), the other A/D converter, A/Di, will perform normally. The values of ADij registers not performing an A/D conversion remain unchanged. 27. Precautions (A/D Converter)

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27.12 Intelligent I/O

27.12.1 Register Setting

Operations controlled by the values written to the GiBT (i=0 to 3), GiBCR1, BTSR, GjTMCR0 to GjTMCR7 (j=0,1), GiTPR6, GiTPR7, GjTM0 to GjTM7, GiPOCR0 to GiPOCR7, GiPO0 to GiPO7, G3MK4 to G3MK7, GjFS, GiFE, G2RTP, and G3RTP registers are affected by the count source (f BT i) set in the BCK1 to BCK0 bits in the GiBCR0 register. Set the BCK1 to BCK0 bits before setting the GiBT, GiBCR1, BTSR, GjTMCR0 to GjTMCR7, GiTPR6, GiTPR7, GjTM0 to GjTM7, GiPOCR0 to GiPOCR7, GiPO0 to GiPO7, G3MK4 to G3MK7, GjFS, GiFE, G2RTP, and G3RTP registers. Operations controlled by the values written to the GjRI, GjTO, GiCR, GiRB, GiMR, GjEMR, GjETC, GjERC, GjIRF, GiTB, GjCMP0 to GjCMP3, GjMSK0, GjMSK1, GjTCRC, GjRCRC, IECR, IEAR, IETIF, IERIF, and G3FLG registers are affected by the transfer clock. Set transfer clock before setting the GjRI, GjTO, GiCR, GiRB, GiMR, GjEMR, GjETC, GjERC, GjIRF, GiTB, GjCMP0 to GjCMP3, GjMSK0,GjMSK1, GjTCRC, GjRCRC, IECR, IEAR, IETIF, IERIF, and G3FLG registers.

27.12.2 BTSR Register Setting

The BTSR register is a located in the intelligent I/O group 2. When starting the base timer using the BTiS bit in the BTSR register, set the BTiS bit to "1" (base timer starts counting) after selecting the count source for the intelligent I/O group 2. If the BTiS bit is not being used, set the BTiS bit to "0" (base timer reset) after selecting the count source for the intelligent I/O group 2. Set only either the BTiS bit or the BTS bit in the GiBCR1 register to "1" when starting the base timer. If both BTiS bit and the BTS bit are set to "0", both bits must be set "0" when stopping the base timer. 27. Precautions (Intelligent I/O)

Page 480 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M

27.13 Programmable I/O Port

Because ports P72 to P75, P80, and P81 have the three-phase PWM output forced cutoff function, they are affected by the three-phase motor control timer function and the NMI pin when these ports are set for output functions (port output, timer output, three-phase PWM output, serial I/O output, intelligent I/O output). Table 27.2 shows the relationship between the INVC0 register setting, the NMI pin input level and the state of output ports. Table 27.2 INVC0 Register and the NMI Pin NOTES : 1. The INV03 bit is set to "0" after an "L" signal is applied to the NMI pin. The input threshold voltage differs with programmable I/O ports and peripheral functions. Therefore, if the level of the voltage applied to a pin shared by both programmable I/O ports and peripheral functions is not within the recommended operating condition, V IH and VIL (neither "H" nor "L"), the level determined will differ with the programmable I/O ports and peripheral functions. 27. Precautions (Programmable I/O Port) retsigeR0CVNIfoeulaVgnitteS leveLtupnI niPIMNot 7PfosetatS 2 7Pot 5 8P, 0,P dna8 1 (sniPw ) niptuptuonagnittesnehtib20VNIt ib30VNI esahp-eerhtgnisuton(0 )noitcnuflortnocrotom -- ,1SPehtnidetcelessnoitcnuftuptuO ,2SP,CSP,1LSPd nas retsiger,2LSP rotomesahp-eerhtgnisu(1 noitcnufremitlortnoc MWPesahp-eerht(0 )delbasidtuptuo - ecnadepmi-hgiH MWPesahp-eerht(1 )delbanetuptuo )1( H, 1SPehtnidetcelessnoitcnuftuptuO sretsiger,2LSPdna,2SP,CSP,1LSP ylbicrof(L )detanimret ecnadepmi-hgiH

Page 481 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M

27.14 Flash Memory Version

27.14.1 Differences Between Flash Memory Version and Masked ROM Version

Due to differences in internal ROM and layout pattern, flash memory version and mask ROM version have varying electrical characteristics such as attributes, performance margins, noise endurance capac- ity, and noise radiation. When switching to masked ROM version, administer system evaluation tests equal to those held on the flash memory version. 27. Precautions (Flash Memory Version)

Page 482 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M 27. Precautions (Noise)

27.15 Noise

Connect a bypass capacitor (approx. 0.1µF) between Vcc and Vss by shortest path, using thick wires.

Page 483 884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M Set PRC3 bit in PRCR register to "1" (write enable) Set VDC0 register to "0F16" Set VDC0 register to "8F16" Set PRC3 bit in PRCR register to "0" (write disable) 27. Precautions (Low Voltage Operations)

27.16 Low Voltage Operations

The voltage down converter (VDC) is a circuit used to step down external supply voltage to the internal operation voltage of 3.3V. Disconnect the VDC when applying a 3.3V supply voltage to reduce power consumption. Figure 27.3 shows the procedure for disconnecting the VDC. Perform these settings immediately after reset, while the CPU clock is divided by 8. Do not set the VDC0 register (001B 16) to other values. Furthermore, do not write to the VDC0 register when applying a supply voltage of 3.3V or more. Figure 27.3 VDC Disconnection Procedure

Page 484 884fo6002,13.naJ13.1.veR 1310-4300B90JER Package Dimensions)T38/C23M,38/C23M(puorG38/C23M Package Dimensions PLQ0144KA-A (144P6Q-A) Plastic 144pin 20 X 20 mm body LQFP Terminal cross section bp c 1.0 0.125 0.20 1.25 1.25 0.08 0.200.1450.09 0.270.220.17 MaxNomMin Dimension in Millimeters Symbol Reference 20.120.019.9D 20.120.019.9E 1.4A2 22.222.021.8 22.222.021.8 1.7A 0.150.10.05 0.650.50.35L x 8°0° c 0.5e 0.10y HD HE bp ZD ZE P-LQFP144-20x20-0.50 1.2g MASS[Typ.] 144P6Q-A / FP-144L / FP-144LVPLQP0144KA-A RENESAS CodeJEITA Package Code Previous Code F 1 36 73108 109 144 x Index mark y HE E D HD bp ZD ZE Detail F c A L A1 A2 DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. e 0.80.5 0.825 0.575 ZE ZD bp HE HD y 0.10 e 0.65 c 0° 10° L 0.4 0.6 0.8 0 0.1 0.2 A 3.05 16.5 16.8 17.1 22.5 22.8 23.1 A 2 2.8 E 13.8 14.0 14.2 D 19.8 20.0 20.2 Reference Symbol Dimension in Millimeters Min Nom Max 0.25 0.3 0.4 0.13 0.15 0.2 P-QFP100-14x20-0.65 1.6g MASS[Typ.] 100P6S-APRQP0100JB-A RENESAS CodeJEITA Package Code Previous Code y Index mark 100 80 51 301 F ZE ZD e bp A HD D E HE c Detail F A1 A2 L INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. PRQP0100JB-A (100P6S-A) Plastic 100pin 14 X 20 mm body LQFP

Page 485 884fo6002,13.naJ13.1.veR 1310-4300B90JER Package Dimensions)T38/C23M,38/C23M(puorG38/C23M Terminal cross section bp c DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark x 12 5 5175 100 F ZE ZD E D HD HE bp Detail F A2A1 L A c ZE ZD bp HE HD y 0.08 e 0.5 c 0° 8° x L 0.35 0.5 0.65 0.05 0.1 0.15 A 1.7 15.8 16.0 16.2 15.8 16.0 16.2 A2 1.4 E 13.9 14.0 14.1 D 13.9 14.0 14.1 Reference Symbol Dimension in Millimeters Min Nom Max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 Previous CodeJEITA Package Code RENESAS Code PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6gP-LQFP100-14x14-0.50 e PLQP0100KB-A (100P6Q-A) Plastic 100pin 14 X 14 mm body LQFP

884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M Register Index A AD00 to AD07 230 AD0CON0 228 AD0CON1 229 AD0CON2 230 AD10 to AD17 233 AD1CON0 231 AD1CON1 232 AD1CON2 233 AIER 107 B BTSR 257 C C0AFS 354 C0BPR 337 C0CONR 334 C0CTLR0 326 C0CTLR1 329 C0EIMKR 341 C0EISTR 342 C0GMR0 343 C0GMR1 344 C0GMR2 344 C0GMR3 345 C0GMR4 345 C0IDR 333 C0LMAR0 343 C0LMAR1 344 C0LMAR2 344 C0LMAR3 345 C0LMAR4 345 C0LMBR0 343 C0LMBR1 344 C0LMBR2 344 C0LMBR3 345 C0LMBR4 345 C0MCTL0 to C0MCTL15 346 C0REC 337 C0SBS 349 C0SIMKR 340 C0SISTR 338 C0SLOT0_0 350 C0SLOT0_1 350 C0SLOT0_2 351 C0SLOT0_3 351 C0SLOT0_4 352 C0SLOT0_5 352 C0SLOT0_6 to C0SLOT0_13 353 C0SLOT0_14 353 C0SLOT0_15 353 C0SLOT1_0 350 C0SLOT1_1 350 C0SLOT1_2 351 C0SLOT1_3 351 C0SLOT1_4 352 C0SLOT1_5 352 C0SLOT1_6 to C0SLOT1_13 353 C0SLOT1_14 353 C0SLOT1_15 353 C0SLPR 330 C0STR 331 C0TEC 336 C0TSR 336 CM0 67,1 1 3 CM1 68 CM2 70 CPSRF 71 CRCD 243 CRCIN 243 D DA0 to DA1 242 DACON 242 DCT0 to DCT3 119 DM0SL to DM3SL 116 DMA0 to DMA3 120 DMD0 to DMD1 117, 118 DRA0 to DRA3 120 DRAMCONT 360 DRC0 to DRC3 119 DS 52 DSA0 to DSA3 120 DTT 166

page 487 884fo6002,13.naJ13.1.veR 1310-4300B90JER Register Index)T38/C23M,38/C23M(puorG38/C23M F FMR0 395 G G0BCR0 to G3BCR0 253 G0BCR1 and G1BCR1 254 G0BT to G3BT 253 G0CMP0 to G0CMP3 295 G0CR to G1CR 290 G0EMR to G1EMR 292 G0ERC to G1ERC 293 G0ETC to G1ETC 292 G0FE to G3FE 262 G0FS and G1FS 262 G0IRF to G1IRF 294 G0MR to G1MR 291 G0MSK0 to G0MSK1 295 G0PO0 TO G0PO7 261 G0POCR0 to G0POCR7 259 G0RB to G1RB 291 G0RCRC to G1RCRC 295 G0RI to G1RI 289 G0TB to G1TB 294 G0TCRC to G1TCRC 295 G0TM0 to G0TM7 259 G0TMCR0 to G0TMCR7 258 G0TO to G1TO 289 G0TPR6 and G0TPR7 258 G1CMP0 to G1CMP3 295 G1MSK0 to G1MSK1 295 G1PO0 to G1PO7 261 G1POCR0 to G1POCR7 259 G1TM0 to G1TM7 259 G1TMCR0 to G1TMCR7 258 G1TPR6 and G1TPR7 258 G2BCR1 255 G2CR 307 G2MR 307 G2PO0 to G2PO7 261 G2POCR0 to G2POCR7 260 G2RB 306 G2RTP and G3RTP 263 G2TB 306 G3BCR1 256 G3CR 318 G3FLG 319 G3MK4 to G3MK7 261 G3MR 318 G3PO0 to G3PO7 261 G3POCR0 to G3POCR7 260 G3RB 317 G3TB 317 I ICTB2 167 IDB0 to IDB1 166 IEAR 308 IECR 308 IERIF 309 IETIF 309 IFSR 105, 181 IIO0IE to IIO11IE110 IIO0IR to IIO11IR109 Interrupt Control96, 97 INVC0 164 INVC1 165 IPS 383 M MCD 69 O ONSF 138 P P0 to P15 372 PCR 383 PD0 to PD15 371 PLC0 72 PLC1 73 PLV 72 PM0 49 PM1 50 PRCR 88 PS0 373 PS1 373 PS2 374 PS3 374 PS5 375 PS6 375 PS7 376 PS8 376

884fo6002,13.naJ13.1.veR 1310-4300B90JER )T38/C23M,38/C23M(puorG38/C23M PS9 377 PSC 380 PSL0 378 PSL1 378 PSL2 379 PSL3 379 PUR0 381 PUR1 381 PUR2 381 PUR3 382 PUR4 382 R REFCNT 360 RLVL 98, 126 RMAD0 to RMAD7 107 ROMCP 393 T TA0 to TA4 136 TA0MR to TA4MR 137, 142, 145, 148, 150 TA1, TA2, TA4, TA11, TA21, TA41167 TA1MR, TA2MR, TA4MR 169 TABSR 137, 153, 168 TB0 to TB5 152 TB0MR to TB5MR 153, 155, 157, 159 TB2 168 TB2MR 169 TB2SC 167 TBSR 154 TCSPR 71, 139 TRGSR 139, 168 U U0BRG to U4BRG 175 U0C0 to U4C0 176 U0C1 to U4C1 177 U0MR to U4MR 175 U0RB to U4RB 174 U0SMR to U4SMR 177 U0SMR2 to U4SMR2 178 U0SMR3 to U4SMR3 179 U0SMR4 to U4SMR4 180 U0TB to U4TB 174 UDF 138 W WCR 58 WDC 112 WDTS 112 X X0R to X15R 245 XYC 245 Y Y0R to Y15R 245

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-1 1.01 2002-12 All Full-fledged revision

Modify the notation system of registers and bits

23 Reset

Delete the figure “Device’s internal status after a reset is cleared”.

65 System Clock

Modify the figure “Clock Generation Circuit”.
Add descriptions about the ‘PLL clock’.
Modify the figure “Status Transition”.

88 Interrupt

Modify the figure “Intelligent I/O Interrupt and CAN Interrupt”.
Add tables ‘registers to be used and settings’.
Change symbols of the bits in the interrupt request register.
Change symbols of the bits in the interrupt enable register.

137 Timer A

Modify the figure “Timer A Configuration”.
Add tables ‘registers to be used and settings’.

154 Timer B

Modify the figure “Timer B Configuration”.
Add tables ‘registers to be used and settings’.

163 Three-Phase Control Timer Function

Change the bit name, the ‘INV17bit’ in the INVC1 register to reserved bit.

174 Serial I/O

Modify the figure “UARTi Block Diagram”.
Add the table ‘registers to be used and settings’ in each mode.
Add distributions about the ‘clock-divided synchronous function (GCI mode)’.
Add descriptions about the ‘bus conflict detect function (IE mode)’.

264 Intelligent I/O

Modify the figure “Intelligent I/O Group 0 Block Diagram”.
Modify the figure “Intelligent I/O Group 1 Block Diagram”.
Modify the figure “Intelligent I/O Group 2 Block Diagram”.
Modify the figure “Intelligent I/O Group 3 Block Diagram”.
Add the table ‘registers and settings’ associated with each function and mode.
Add a bit function of ‘the BCK0 to BCK1 bit in the G0BCR0 to G3BCR0 register’. -Group 0 and 1
Add descriptions about the ‘HDLC data processing mode’. -Group 0 and 1
Add distributions about the ‘IEBus mode’. -Group2
Add descriptions about the ‘8-bit and 16-bit clock synchronous serial I/O function’. -Group3

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-2 1.02 2003-1

338 A/D Convertor

Modify the figure “A/D Convertor Block Diagram”.
Add the table ‘pin settings’.

355 D/A Convertor

Add the table ‘pin settings’.

394 Usage Precaution

Add descriptions about the ‘PLL synthesizer’.
Add descriptions about the ‘Timer A’ and ‘Timer B’.
Add descriptions about the ‘Low-Voltage Operation’. Overview 3 • Delete 8-bit or 16-bit clock synchronous serial I/O:1 channel (group3) on ‘Peripheral function’ row in Table 1.1.2. SFR 33 • Modify 00?0 X000 2 to 0000 X0002 on ‘value after RESET’ column on ‘017B16’ row. System Clock 78 • Modify 0 to 1 on ‘PLC00’ column and ‘10MHz’ row in Table 1.8.2. 78 • Modify the PLC02 to PLC0 bits and the PLC05 to PLC04 bits to the PLC0 register in the third step in Figure 1.8.13. 80 • Modify 1 to 0 on ‘CM00’ column and ‘BCLK output’ row in Table 1.8.5. DMAC 117 • Add the note 3 in Figure 1.11.2. Timer 141 • Modify TA4 and TA1 to TA0 and TA2 on the TA1TGL and TA1TGH in the top figure of Table 1.14.5.
Modify TA4 and TA1 to TA1 and TA3 on the TA2TGL and TA2TGH in the top figure of Table 1.14.5.
Modify TA4 and TA1 to TA2 and TA4 on the TA3TGL and TA3TGH in the top figure of Table 1.14.5.
Modify TA4 and TA1 to TA3 and TA0 on the TA4TGL and TA4TGH in the top figure of Table 1.14.5. Serial I/O 186 • Modify PD7_0=0 to PD7_2=0 on ‘PD7 register’ column and ‘CLK2 input’ row in Table 1.18.4. 192 • Modify PD7_0=0 to PD7_2=0 on ‘PD7 register’ column and ‘CLK2 input’ row in Table 1.19.4. 206 • Modify a function description on ‘UiRRM’ row in Table 1.20.9.

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-3 207 • Modify PD7_2=0 to PD7_0=0 on ‘PD7 register’ column and ‘SRxD2 input’ row in Table 1.20.11.

Modify PD7_0=0 to PD7_2=0 on ‘PD7 register’ column and ‘CLK2 input’ row in Table 1.20.11. 216 • Modify PS3_4=0 to PS3_5=0 on ‘PS3 register’ column and ‘CLK4 input’ row in Table 1.20.23. CAN Module 226 • Modify PSL2_2=0 to PSL2_1=0 on ‘PSL1 and PSL2 registers’ column and ‘P82’ row in Table 1.21.2. Intelligent I/O 296 • Modify Setting value of the GiPO0 register to Setting value of the GiPOk register as n and m on the second figure in Figure 1.22.26. 304 • Modify RxD to ISRxD on ‘IPOL’ row and TxD to ISTxD on ‘OPOL’ row in Figure 1.22.33. 315 • Modify IPS=1 to IPS1=1 on IPS registers column and ‘P112’ row in Table 1.22.26. 317 • Modify TCRCRC to TCRCE on ‘CRC’ row in Table 1.22.28.
Delete SIOiTR and SIOiRR and add SRTiR in note 3 in Table 1.22.28. 320 • Modify IER to OER in note 1 in the second figure of Figure 1.22.42. 334 • Modify GiCR to G3CR in Table 1.22.41. DRAMC 364 • Modify SRDF to SREF in note 3 in Figure 1.27.1. 385 • Modify IOUTC1 0 to OUTC10 on ‘PSC_3’ row in Figure 1.28.14. 388 • Modify P0 to P5 to P1 in note 1 in Table 1.28.17. Programable I/O Port 390 • Modify INPC 1 to INPC11 on ‘PS1 register’ column and ‘Bit 4’ row in Table 1.28.4. 391 • Modify INPC 0 to INPC02 on ‘PS2 register’ column and ‘Bit 0’ row in table 1.28.5. 393 • Modify ISCLK input to ISCLK0 input on ‘Bit 1’ row in table 1.28.12. Usage Precaution 394
Modify PM0 to PM00 in “HOLD Signal”
Modify all SP to ISP in (1) SP Setting of “Interrupts”. 398 • Modify all TAi to TBi in 1. Timer Mode and Event Counter Mode of “Timer B”. 400 • Modify the CAN module to the microcomputer in “Resetting CNVSS Pin with H”.
Delete a discription of ‘Difference between Flash Memory version and Masked ROM’ Electric Charactistics 429 • Modify IOH=5mA to IOL=5mA on ‘VOL’ row and ‘Mesurement Condition’ column in Table 1.31.3.

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-4 All PagesChapter numbers, section numbers, etc., added; Table and Figure numbers modified; Chapter sequence modified; Word Phrasing in Revision History changed Overview 2, 3 • Tables 1.1 and 1.2 M32C/83 Group Performance Shortest Instruction Execution Time modified: 31.3ns(f(BCLK)=30MHz changed to 31.3ns(f(BCLK)=32MHz, 50ns(f(BCLK)=20MHz added; Performance details of Multifunction Timer, Intelligent I/O, Clock Generating Circuit, and Electrical Characteristics revised; Oscillator Stop Detect Function added; 32MHz added to Supply Voltage and Power Consumption Note 3 added 4• Figure 1.1 M32C/83 Block Diagram modified 5• Table 1.3 M32C/83 Group Product deleted 9, 13 • Tables 1.4 and 1.5 Pin Characteristics VREF pin changed from “analog pin” to “control pin” 15 to 18 • Table 1.6 Pin Description SDA0 to SDA4 changed from “output” to “input”; Descriptions of A/D-related pin functions revised Centeral Processing Unit 20 • Figure 2.1 CPU Register modified Memory 23 • Figure 3.1 Memory Map Product deleted; Diagram modified SFR 24 to 45 Value after reset and lisiting sequence modified

“? : Indetermination” changed to “X : Indeterminate”
Notation “Users cannot use any symbols with *” deleted
Register names, symbols, and Values after RESET of addresses 001F 16 to 002516, 003016 to 003516, 005516 to 005616, 01AC16, and 01AE16 to 01BF16 deleted
Notations added to PM0 and TCSPR registers
Value after reset in the RLVL register modified Reset 46 • Figure 5.1 Reset Circuit modified 47 • Figure 5.2 Reset Sequence Diagram modified; Note 1 added 48 • 5.3 Watchdog Timer Reset added 49 • Figure 5.3 CPU Register after Reset modified Processor Mode 50 • 6.2.2 Applying V CC to CNVSS Pin Contents added 1.10 2004-3

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-5 Bus 55 • 7.1.3.2 Multiplexed Bus revised 60 • 7.2.4 Bus Timing revised

7.6 RDY Signal revised
Figure 7.7 RD Signal Output Extended by RDY Signal modified Clock Generating Circuit Chapter name changed from “System Clock “ to “Clock Generating Circuit” 67 • Table 8.1 Clock Generation Circuit Specifications Main clock clock frequency modified; “Ceramic oscillator” changed to “Ceramic resonator”; Reference point added to PLL Frequency Synthesizer 68 • Figure 8.1 Clock Generation Circuit revised 69 • Figure 8.2 CM0 Register Bit 3 function changed from “Nothing is assigned” to “Reserved Bit” 72 • Figure 8.5 CM2 Register CM21 bit function modified; Note 5 revised 75 • Figure 8.8 PLC1 Register Note 3 revised; Note 4 added 77 • 8.1.2 Sub Clock revised 79 • Figure 8.11 Switching Procedure form On-chip Oscillator Clock to Main Clock modified
8.1.4 PLL Clock revised
Table 8.2 Bit Settings to Use PLL Clock as CPU Clock Source Setting added for when f(X IN) is 8MHz 80 • Figure 8.13 Procedure to Use PLL Clock as CPU Clock Source modified 81 • 8.2 CPU Clock and BCLK revised 84 • 8.5.2.2 Before Entering Wait Mode revised 85 • 8.5.2.5 Entering Wait Mode added 86 • 8.5.3 Stop Mode revised
8.5.3.1 Before Entering Stop Mode revised
8.5.3.3 Exiting Stop Mode revised 87 • 8.5.3.4 Entering Stop Mode added 88 • Figure 8.15 Status Transition modified Interrupts 93 • Table 10.1 Fixed Vector Table Point of reference changed 95 • Table 10.2 Relocatable Vector Tables Reserved Space added 99 • Figure 10.5 RLVL Register Value after reset changed; Note 3 revised; Note 4 added
10.6.2.3 RLVL2 to RLVL0 Bits revised 103 • Figure 10.8 Interrupt Priority “Oscillation Stop Detect” added 104 • Figure 10.9 Interrupt Priority Level Select Circuit modified 106 • 10.8 NMI Interrupt revised

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-6 108 • “ 10.11 Intelligent I/O and CAN Interrupt” changed to “10.11 Intelligent I/O Interrupt and CAN Interrupt”

Precautions pertaining to Interrupts are compiled into one chapter, “27. Precaution” Watchdog Timer

111 Contents revised

115 • 12. DMAC revised 114 • Table 12.1 DMAC Specifications CAN interrupt added to DNA Request Factors; Note 1 revised

Precautions pertaining to DMAC are compiled into one chapter, “27. Precaution” DMAC II 125 • Table 13.1 DMAC II Specifications Note 2 added 126 • Figure 13.1 RLVL Register Values after reset modified; Note 3 revised; Note 4 added 129 • 13.3 Transfer Data Contents added 130 • 13.4.2 Burst Transfer revised
13.4.4 Chain Transfer revised 132 • 13.5 Execution Time revised Timer 135 • 14.1 Timer A Contents added 140 • Table 14.1 Pin Settings for Output from TAiOUT Pin (i= 0 to 4) modified 149 • 14.1.4 Pulse Width Modulation Mode Settings changed for 16-bit PWM and 8-bit PWM 152 • 14.2 Timer B Contents added 159 • Figure 14.22 TB0MR to TB5MR Registers (Pulse Period/ Pulse Width Measurement Mode) Values after reset modified Three-Phase Motor Control Timer Function 161 • Table 15.1 Three-Phase Motor Control Timer Functions Specification modified 162 • Figure 15.1 Three-Phase Motor Control Function Block Diagram modified 163 • Figure 15.2 INVC0 Register modified 164 • Figure 15.3 INVC1 Register modified 166 • Figure 15.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers and TB2SC Register Notes 2 and 3 added to ICTB2 register; Note 7 added to TAi and TAi1 registers 168 • Figure 15.7 TAiMR Register (i=1, 2, 4) MR1 bit function modified

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-7 169 • Figure 15.8 Triangular Wave Modulation Operation modified 170 • Figure 15.9 Sawtooth Wave Modulation Operation modified Serial I/O 173 • Figure 16.2 U0TB to U4TB Registers and U0RB to U4RB Registers Note 3 added to U0RB to U4RB registers 175 • Figure 16.4 UiC0 Register Note 3 added to UFORM bit 176 • Figure 16.5 UiC1 Register Note 2 added to UiLCH bit; Note 1 added to SCLKSTPB (UiERE) bit 181 • Table 16.1 Clock Synchrnous Serial I/O Mode Specifications Explanation of CLK Polarity in Selectable Functions revised Settings Points of reference deleted 183 • Table 16.3 Pin Settings in Clock Synchronous Serial I/O Mode (1) revised 184 • Figure 16.10 Transmit and Receive Operation modified 188 • Table 16.7 Registers to be Used and Settings in UART Mode Function of the UiERE bit in the UiC1 register modified 189 • Table 16.8 Pin Settings in UART (1) revised 190 • Figure 16.14 Transmit Operation modified 192 • Figure 16.17 Serial Data Logic Inverse modified 195 • Table 16.12 Registers to be Used and Settings (I2C Mode) Setting values for master and slave indicated separately 196 • Table 16.13 I2C Mode Functions “P61, P65, P72, P90, P75 Pin Functions” changed to “P61, P65, P72, P90, P95 Pin Functions” 197, 198 • Tables 16.14 to 16.16 Pin Settings in I2C Mode modified 200 • 16.3.4 Transfer Clock revised 203 • Table 16.19 Registers to be Used and Settings in Special Mode 2 Functions of the UFORM bit in the UiC0 register and the UiRRM bit in the UiC1 register modified 204 • Table 16.20 Pin Settings in Special Mode 2 (1) revised

Table 16.21 Pin Settings in Special Mode 2 (2) revised
Table 16.22 Pin Settings in Special Mode 2 (3) revised 208 • Table 16.23 GCI Mode Specifications Explanations of Transmit/Receive Start Conditions revised 210 • Table 16.25 Pin Settings in GCI Mode (1) revised
Table 16.26 Pin Settings in GCI Mode (2) revised
Table 16.27 Pin Settings in GCI Mode (3) revised 213 • Table 16.31 Pin Settings in IE Mode (2) revised
Table 16.32 Pin Settings in IE Mode (3) revised 219 • Figure 16.29 SIM Interface Operation modified

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-8 221 • Figure 16.32 SIM Interface Format modified A/D Converter Sequence of content modified 223 • Table 17.1 A/D Converter Specifications Explanaition of A/D Conversion Start Conditions revised; φ A/D frequency modified 226, 227 • Figure 17.2 AD0CON0 Register, Figure 17.3 AD0CON1 Register φ A/D frequency modified 229, 230 • Figure 17.5 AD1CON0 Register, Figure 17.6 AD1CON1 Register φ A/D frequency modified 232 • Table 17.4 One-shot Mode Specifications Explanation of Start Condition revised 235 • Table 17.9 Trigger Select Function Settings Table modified; Note 2 added 237 • Figure 17.9 Analog Input Pin and External Sensor Equivalent Circuit Capacitance of the capacitor modified 238 to 247Sequence of the following Chapters have been changed: D/A Converter, CRC Calculation, XY Conversion Intelligent I/O 248 • Figure 21.2 Intelligent I/O Group 1 Block Diagram modified 251 • Figure 21.5 G0BT to G3BT Registers and G0BCR0 to G3BCR0 Registers Note 2 added to G0BT to G3BT registers, Note 3 deleted from G0BCR0 to G3BCR0 registers 252 • Table 21.2 Base Timer Specifications Explanation of Counter increment/ decrement mode in Selectable Function modified Associated Register Settings Point of reference deleted 266 • Figure 21.18 Counter Increment Mode (Group 0 and 1) modified 265 • Figure 21.19 Counter Increment/Decrement Mode (Group 0 and 1) modified 266 • Figure 21.20 Base Timer Operation in Two-Phase Pulse Signal Processing Mode Note 1 revised 267 • 21.2 Time Measurement Function (Group 0 and 1) Contents added 270 • Figure 21.22 Time Measurement Function (2) modified 271 • Figure 21.23 Prescaler Function and Gate Function Diagram modified; Note 2 of Gate Function deleted 272 • Table 21.7 Pin Settings for Waveform Generation Function modified 273 • Table 21.8 Waveform Generation Function Associated Register Settings Note 1 added 274 • 21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3) revised

Table 21.9 Single-Phase Waveform Output Mode Specifications revised 275 • Figure 21.24 Single-Phase Waveform Output Mode modified

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-9 276 • Table 21.10 Phase-Delayed Waveform Output Mode Specifications revised 277 • Figure 21.25 Phase-Delayed Waveform Output Mode modified 278 • 21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode revised

Table 21.11 SR Waveform Output Mode Specifications revised 280 • Figure 21.26 SR Waveform Output Mode modified 281 • 21.3.4 Bit-Modulation PWM Output Mode revised
Table 21.12 Bit Modulation PWM Output Mode revised
Figure 21.27 Bit Modulation PWM Mode Pulse numbering added 283 • 21.3.5 Real-Time Port (RTP) Output Mode (Group 2 and 3) revised
Table 21.14 RTP Output Mode Specifications Note 1 added 284 • Figure 21.29 Real-Time Port Output Mode modified 285 • 21.3.6 Parallel Real-Time Port Output Mode (Group 2 and 3) revised
Table 21.15 Parallel RTP Output Mode Note 1 added 286 • Figure 21.31 Parallel RTP Output Mode modified 290 • Figure 21.35 G0EMR to G1EMR Registers and G0ETC to G1ETC Registers Note 1 added 291 • Figure 21.36 G0ERC to G1ERC Registers Note 1 added 292 • Figure 21.37 G0IRF to G1IRF Registers and G0TB to G1TB Registers Notes 1 and 2 in G0IRF to G1IRF registers revised; Note 1 added to G0TB to G1TB registers 293 • Figure 21. 38 G0CMP0 to G0CMP3 Registers, G1CMP0 to G1CMP3 Registers, G0MSK0 to G0MSK1 Registers, G1MSK0 to G1MSK1 Registers, G0TCRC to G1TCRC Registers, and G0RCRC to G1RCRC Registers Note 1 revised and Note 2 added to G0TCRC to G1TCRC registers; Note 3 in G0RCRC to G1RCRC registers revised 294 • Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Group 0 and 1) Explanation of transfer clock revised 297 • Table 21.22 UART Mode Specifications (Group 0 and 1) Explanation of transfer clock and Note 2 revised 301 • Table 21.28 HDLC Processing Mode Specifications (Group 0 and 1) Explanation of transfer clock revised 308 • Table 21.30 Variable Clock Synchronous Serial I/O Mode Specifications (Group 2) Explanation of transfer clock revised 312 • Table 21.36 IE Bus Mode Specification Explanation of transfer clock revised 318 • Table 21.41 Clock Synchronous Serial I/O Mode (Group 3) Explanation of transfer clock revised CAN 322 Bit symbols of each register are now capitalized (e.g. Reset0 is changed to RESET0)

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-10 325 • 22.1.1.3 BASICCAN Bit revised 344 • 22.1.16 CANi Message Slotj Control Register (CiMCTLj Register) (i=0, 1; j=0 to 15) Funtion of the INVALDATA/TRMACTIVE bit when set to “1” changed to “Transmits”; Note 4 in REMACTIVE deleted; RW modified to RO

Table 22.4 C0MCTLi Register (i=0 to 15) Setting and Transmit/Receive Mode Hyphens (-) changed to “0” 345 • 22.1.16.4 REMACTIVE Bit revised 346 • 22.1.16.5 RSPLOCK Bit revised Programmable I/O Port 364 • 24.4 Function Select Register Bk (PSLk Register) (k=0 to 3) revised 365 • 24.5 Function Select Register C (PSC Register) revised
24.7 Port Control Register (PCR Register) revised 367 • Figure 24.2 Programmable I/O Ports (2) modified 369 • Figure 24.5 PD0 to PD15 Registers Note 4 added 371 • Figure 24.7 PS0 Register and PS1 Register PS0 register revised 372 • Figure 24.8 PS2 Register and PS3 Register PS3 register revised 376 • Figure 24.12 PSL0 Register and PSL1 Register Note 1 added to PSL1 register 377 • Figure 24.13 PSL2 Register and PSL3 Register PSL3 register revised 378 • Figure 24.14 PSC Register revised 379 • Figure 24.15 PUR0 Register, PUR1 Register and PUR2 Register Note 1 revised 383 • Table 24.3 Port P6 Peripheral Function Output Control Bits 3 and 7 modified
Table 24.4 Port P7 Peripheral Function Output Control Note 1 added to PSC register; Bit 0 modified 384 • Table 24.6 Port P9 Peripheral Function Output Control Bit 2 and 6 modified Flash Memory Version 387 • Table 25.1 Flash Memory Version Specifications Supply voltage modified 389 • 25.2.1 ROM Code Protect Function revised
25.2.2 ID Code Check Function revised 393 • 25.3.1.3 FMR02 Bit revised 395 • 25.3.3 Data Protect Function revised 397 • 25.3.5.3 Clear status Register revised 405 • 25.3.7.8 Rewriting the User ROM Area 406 • 25.4.2 ID Code Check Function revised 412 • 25.5.2 ROM Code Protect Function revised

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-11

Electrical Characteristics

413 • Table 26.1 Absolute Maximum Ratings VREF , XIN P70 and P71 deleted and XOUT added to Output Voltage 414 • Table 26.2 Recommended Operation Conditions (VCC = 3.0V to 5.5V at Topr= -20 to 85°C) Maximum value of 50MHz added to f(XCIN) Sub Clock Oscillation Frequency 416 • Table 26.4 A/D Conversion Characteristics φAD frequency modified 416, 434 • Tables 26.6 Flash Memory Version Electrical Characteristics added Precautions 450 to 472• Overall structure modified All pages Words standardized: On-chip oscillator, A/D converter and D/A converter Interrupts 111 • Figure 10.15 IIO0IE to IIO11IE Registers Note 2 added Watchdog Timer 112 • Figure 11.1 Watchdog Timer Block Diagram modified 432 • Figure 26.8 VCC =5V Timing Diagram (7) Figure modified 449 • Figure 26.16 VCC =3.3V Timing Diagram (7) Figure modified 1.20 2004-6 All Pages M32C/83T version added; Package code changed: 144P6Q-A to PLQP0144KA- A, 100P6Q-A to PLQP0100KB-A, 100P6S-A to PRQP0100JB-A All Pages Word standardized: Clock Generation Circuit , On-chip Oscillator, A/D Converter, D/A Converter, XY Conversion, Low -power consumption Overview 1• 1.1 Applications Automobile added 2, 3 • Tables 1.1 and 1.2 M32C/83 Group (M32C/83, M32C/83T) Performance 5• Table 1.3 M32C/83 Group (1) (M32C/83) Information updated

Table 1.3 M32C/83 Group (2) (M32C/83T) M32C/83T product information added
Figure 1.2 Product Numbering System Classification modified
Table 1.4 Pin Characteristics for 144-Pin Package Note 1 added
Table 1.5 Pin Characteristics for 100-Pin Package Note 1 added
Table 1.6 Pin Description modified, notes added Memory 21 • Figure 3.1 Memory Map modified; Note 2 modified, notes 3 and 4 added Special Function Registers (SFR) 22 to 23 • Note 2 added Reset 45 • Figure 5.2 Reset Sequence Note 2 added 1.31 2006-1

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-12 Processor Mode 48 • Chapter Note added 49 • Figure 6.1 PM0 Register Note 9 added 50 • Figure 6.2 PM1 Register Note 6 added Bus 52 • Chapter note added

Figure 7.1 DS Register Note 2 added 54 • Table 7.2 Processor Mode and Port Function Note 3 modified 58 • Table 7.3 WCR Register Note 3 added Clock Generation Circuit 67 • Figure 8.2 CM0 Register Function of the CM07 bit modified 68 • Figure 8.3 CM1 Register Note mark position changed 71 • Figure 8.6 TCSPR and CPSRF Register Note 2 added for TCSPR register 74 • Figure 8.9 Main Clock Circuit Connection modified 75 • Figure 8.10 Sub Clock Connection Circuit modified 76 • 8.1.3.2 How to Use Oscillation Stop Detect Function partially modified 78 • Figure 8.12 External Circuit with PLL Frequency Synthesizer modified 80 • Table 8.5 BLCK/CLKOUT Pin in Memory Expansion Mode and Microprocessor Mode Note 4 added 81 • 8.5.1 Normal Operation Mode Description partially modified 82 • 8.5.2 Wait Mode modified 83 • Table 8.6 Pin States in Wait Mode Note 2 added 84-85 • 8.5.3 Stop Mode modified 85 • Table 8.8 Pin Status in Stop Mode Note 2 added 86 • Figure 8.14 Status Transition in Wait Mode and Stop Mode The mode between stop mode and low-speed mode, low-power consumption mode changed; Note 2 deleted Interrupts 97 • Figure 10.4 Interrupt Control Register (2) Note mark position changed 98 • Figure 10.5 RLVL Register Note 3 modified 109 • Figure 10.14 IIO0IR to IIO11IR Registers partially modified 110 • Figure 10.15 IIO0IE to IIO11IE Registers partially modified Watchdog Timer 113 • Figure 11.3 CM0 Register Function of the CM07 bit modified DMAC 115 • Table 12.1 DMAC Specifications Specification of DMA Transfer Cycles partially modified 119 • Figure 12.4 DCT0 to DCT3 Registers Notes 3 and 4 modified; DRC0 to DRC3 Registers Notes 2 and 4 modified

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-13 120 • Figure 12.5 DMA0 to DMA Registers Notes 3 and 4 modified; DSA0 to DSA3 Registers Notes 3 and 4 modified DMACII 126 • Figure 13.1 RLVL Register Note 3 modified 140 • 13.4.2 Burst Transfer partially added Timer 139 • Figure 14.7 TCSPR Register Note 2 added 141-156 • Table 14.4 Specification in Event Counter Mode (when not processing two - phase pulse signal) to Table 14.7 Specifications in Pulse Width Modulation Mode; Table 14.9 Specifiations in Timer Mode and Table 14.10 Specifications in Event Counter Mode Condition for “Write to Timer” modified Serial I/O 173 • Figure 16.1 UARTi Block Diagram modified between transmit control circuit and CTSi/RTSi pins 175 • Figure 16.3 U0BRG to U4BRG Registers Note 3 added 176 • Figure 16.4 U0C0 to U4C0 Registers Note 4 added 177 • Figure 16.5 U0C1 to U4C1 Register and U0SMR to U4SMR Registers RI bit revised 191 • Figure 16.14 Transmit Operation Timing modified 192 • 16.2.1 Bit Rate added 204 • Table 16.19 Special Mode 2 Specifications Transmit Start Condition modified; Specification for Error Detection partially added 221 • Figure 16.29 SIM Interface Operation Timing modified A/D Converter 225 • Table 17.1 A/D Converter Specifications Note 3 added D/A Converter 242 • Figure 18.3 D/A Converter Equivalent Circuit modified Intelligent I/O 250 • Figure 21.2 Intelligent I/O Group 1 Block Diagram modified 274, 275 • Table 21.7 Pin Settings for Waveform Generation Function PSL3 register added 296 • Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Groups 0 and 1) Specification for interrupt request modified 297 • Table 21.19 Pin Settings (2) Bit and Setting modified for the PD8 register 299 • Table 21.22 UART Mode Specifications Specification for interrupt request modified 304 • Table 21.28 HDLC Processing Mode Specifications Specification for interrupt request modified

REVISION HISTORY M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual Rev. Date Description Page Summary C-14 314 • Table 21.36 IEBus Mode Specifications Specification for interrupt request modified 315 • Table 21.37 Registers to be Used and Settings Description for the IPOL bit in the G2CR register is modified Programmable I/O Ports 369 • Figure 24.2 Programmable I/O Ports (2) Figure modified 384 • Table 24.1 Unassigned Pin Settings in Single-chip Mode Notes 2, 3, 4, and 6 added

Table 24.2 Unassigned Pin Settings in Memory Expansion Mode and Microprocessor Mode Notes 2, 3, 4, and 6 added 385 • Figure 24.19 Unassigned Pin Handling Note 2 added 387 • Table 24.7 Port P10 Peripheral Function Output Control Title modified Flash Memory Version 393 Figure 25.2 ROMCP Register Note 4 added

453-461 • 26.2 Electrical Characteristics (M32C/83T) Newly added 418 • Table 26.3 Electrical Characteristics Minimum standard values for VOH revised, values for ICC when f(XIN)=32 MHz, square wave, no division revised, one condition of “f(XIN)=32 MHz, square wave, no division” deleted 426 • Table 26.23 Memory Expansion Mode and Microprocessor Mode Symbols for Row Address Output Delay Time and for Row Address Output Hold Time (BCLK standard) modified 434

Figure 26.8 VCC =5 V Timing Diagram (7) Timing for NMI input added 436 • Table 26.24 Electrical Characteristics Minimum standard value for VOH revised 444 • Table 26.44 Memory Expansion Mode and Microprocessor Mode Symbols for Row Address Output Delay Time and for Row Address Output Hold Time (BCLK standard) modified 451
Figure 26.8 VCC =3.3 V Timing Diagram (7) Timing for NMI input added 453-461 • 26.2 Electrical Characteristics (M32C/83T) Newly added Precautions 476 • 27.4.3 Wait Mode modified
27.4.4 Stop Mode modified 472 27.8.2.3 Timer A (One-shot Timer Mode) Information (g) newly added

RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M32C/83 Group (M32C/83, M32C/83T) Publication Data: Rev.1.01 Dec. 2002 Rev.1.31 Jan. 31, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.

M32C/83 Group (M32C/83, M32C/83T) Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan

Product Information

M32C83T specifications and overview.

Summary

16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

Description

16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

Source title M32C83T Datasheet(PDF) - Renesas Technology Corp

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