M32C/86

Renesas Technology Corp

RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

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RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES M32C/86 Group (M32C/86, M32C/86T)16/32 Rev. 1.00 Revision Date: Sep. 08, 2005 Hardware Manual www.renesas.com Before using this material, please visit our website to verify that this is the most current document available. REJ09B0204-0100

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis- tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari- ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Introduction This hardware manual provides detailed information on the M32C/86 group (M32C/86, M32C/86T) microcom- puters. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. Function XXX Register Bit NameBit Symbol Symbol Address After Reset XXX XXX 00 16 RW RW RW WO RO XXX0 XXX1 (b2) (b4 - b3) XXX bit Reserved bit XXX7 Set to "0" 0: XXX 1: XXX Nothing is assigned. When write, set to "0". When read, its content is indeterminate. XXX bit 0 0: XXX 0 1: XXX 1 0: Do not set a value 1 1: XXX b1b0 XXX bit Function varies depending on mode of operation XXX5 XXX6 RW RW b7 b6 b5 b4 b3 b2 b1 b0 Blank:Set to "0" or "1" according to the application 0: Set to "0" 1: Set to "1" X: Nothing is assigned RW: Read and write RO: Read only WO: Write only –: Nothing is assigned

Reserved bit Reserved bit. Set to specified value.
Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to "0" when writing to this bit.
Do not set a value The operation is not guaranteed when a value is set.
Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode.

M16C Family Documents The following documents were prepared for the M16C family. (1) Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer perfor- mance of each instruction Application Note • Application examples of peripheral functions

Sample programs
Introduction to the basic functions in the M16C family
Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to verify that this is the most current document available.

9.3.1 f

Three-Phase Motor Control Timer Functions ____ 172

17.3 Special Mode 1 (I

18.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion ...252 22.4.2 Clock Asynchronous Serial I/O (UART) Mode (Communication Unit 1) .. 303

23.1.19 CANi Global Mask Register, CANi Local Mask Register A and CANi Local Mask

27.10.3 Special Mode 1 (I

Quick Reference by Address B-1 Address Register Page 000016 000116 000216 000316

000416 Processor Mode Register 0 (PM0) 51

000516 Processor Mode Register 1 (PM1) 62

000616 System Clock Control Register 0 (CM0) 73

000716 System Clock Control Register 1 (CM1) 74

000916 Address Match Interrupt Enable Register (AIER) 116

000A 16 Protect Register (PRCR) 96 000B 16 External Data Bus Width Control Register (DS) 54 000C 16 Main Clock Division Register (MCD) 75 000D 16 Oscillation Stop Detection Register (CM2) 76 000E 16 Watchdog Timer Start Register (WDTS) 122000F16 Watchdog Timer Control Register (WDC) 001016

001116 Address Match Interrupt Register 0 (RMAD0) 116

001316 Processor Mode Register 2 (PM2) 79

001516 Address Match Interrupt Register 1 (RMAD1) 116

001716 Voltage Detection Register 2 (VCR2) 44

001916 Address Match Interrupt Register 2 (RMAD2) 116

001B 16 Voltage Detection Register 1 (VCR1) 44 001C 16 001D 16 Address Match Interrupt Register 3 (RMAD3) 116 001E 16 001F16 002016 002116 002216 002316 002416 002516

002616 PLL Control Register 0 (PLC0) 78

002716 PLL Control Register 1 (PLC1)

002916 Address Match Interrupt Register 4 (RMAD4) 116

002D 16 Address Match Interrupt Register 5 (RMAD5) 116 002E 16 002F16 Low Voltage Detection Interrupt Register (D4INT)45 Address Register Page 003016 003116 003216 003316 003416 003516 003616 003716 003816

003916 Address Match Interrupt Register 6 (RMAD6) 116

003D 16 Address Match Interrupt Register 7 (RMAD7) 116 003E 16 003F16 004016 004116 004216 004316 004416 004516 004616 004716

004816 External Space Wait Control Register 0 (EWCR0)

004916 External Space Wait Control Register 1 (EWCR1)

60004A 16 External Space Wait Control Register 2 (EWCR2) 004B 16 External Space Wait Control Register 3 (EWCR3) 004C 16 004D 16 004E 16 004F16 005016 005116 005216 005316 005416

005516 Flash Memory Control Register 1 (FMR1) 399

005716 Flash Memory Control Register 0 (FMR0) 398

Blank spaces are reserved. No access is allowed. Quick Reference by Address

Quick Reference by Address B-2 Address Register Page 006016 006116 006216 006316 006416 006516 006616 006716

006816 DMA0 Interrupt Control Register (DM0IC)

006916 Timer B5 Interrupt Control Register (TB5IC)

006A 16 DMA2 Interrupt Control Register (DM2IC) 006B 16 UART2 Receive /ACK Interrupt Control Register (S2RIC) 006C 16 Timer A0 Interrupt Control Register (TA0IC) 006D 16 UART3 Receive /ACK Interrupt Control Register (S3RIC) 006E 16 Timer A2 Interrupt Control Register (TA2IC) 006F16 UART4 Receive /ACK Interrupt Control Register (S4RIC)

007016 Timer A4 Interrupt Control Register (TA4IC)

UART0 Bus Conflict Detect Interrupt Control Register (BCN0IC)/ 007116 105UART3 Bus Conflict Detect Interrupt Control Register (BCN3IC)

007216 UART0 Receive/ACK Interrupt Control Register (S0RIC)

007316 A/D0 Conversion Interrupt Control Register (AD0IC)

007416 UART1 Receive/ACK Interrupt Control Register (S1RIC)

Intelligent I/O Interrupt Control Register 0 (IIO0IC)/

007516 CAN Interrupt 3 Control Register (CAN3IC)

007616 Timer B1 Interrupt Control Register (TB1IC)

007716 Intelligent I/O Interrupt Control Register 2 (IIO2IC)

007816 Timer B3 Interrupt Control Register (TB3IC)

007916 Intelligent I/O Interrupt Control Register 4 (IIO4IC)

007A 16 INT5 Interrupt Control Register (INT5IC) 106 007B 16 007C 16 INT3 Interrupt Control Register (INT3IC) 106 007D 16 Intelligent I/O Interrupt Control Register 8 (IIO8IC) 105 007E 16 INT1 Interrupt Control Register (INT1IC) 106 Intelligent I/O Interrupt Control Register 10 (IIO10IC)/ 007F16 105CAN Interrupt 1 Control Register (CAN1IC) 008016

008116 CAN Interrupt 2 Control Register (CAN2IC) 105

008816 DMA1 Interrupt Control Register (DM1IC)

008916 UART2 Transmit /NACK Interrupt Control Register (S2TIC)

008A 16 DMA3 Interrupt Control Register (DM3IC) 008B 16 UART3 Transmit /NACK Interrupt Control Register (S3TIC) 105008C 16 Timer A1 Interrupt Control Register (TA1IC) 008D 16 UART4 Transmit /NACK Interrupt Control Register (S4TIC) 008E 16 Timer A3 Interrupt Control Register (TA3IC) 008F16 UART2 Bus Conflict Detect Interrupt Control Register (BCN2IC) Address Register Page

009016 UART0 Transmit /NACK Interrupt Control Register (S0TIC)

UART1 Bus Conflict Detect Interrupt Control Register (BCN1IC)/

009116 UART4 Bus Conflict Detect Interrupt Control Register (BCN4IC)

009216 UART1 Transmit/NACK Interrupt Control Register (S1TIC)

009316 Key Input Interrupt Control Register (KUPIC)

009416 Timer B0 Interrupt Control Register (TB0IC)

105Intelligent I/O Interrupt Control Register 1 (IIO1IC)/

009516 CAN Interrupt 4 Control Register (CAN4IC)

009616 Timer B2 Interrupt Control Register (TB2IC)

009716 Intelligent I/O Interrupt Control Register 3 (IIO3IC)

009816 Timer B4 Interrupt Control Register (TB4IC)

009916 CAN Interrupt 5 Control Register (CAN5IC)

009A 16 INT4 Interrupt Control Register (INT4IC) 106 009B 16 009C 16 INT2 Interrupt Control Register (INT2IC) 106 Intelligent I/O Interrupt Control Register 9 (IIO9IC)/ 009D 16 105CAN Interrupt 0 Control Register (CAN0IC) 009E 16 INT0 Interrupt Control Register (INT0IC) 106 009F16 Exit Priority Control Register (RLVL) 107 00A0 16 Interrupt Request Register 0 (IIO0IR) 00A1 16 Interrupt Request Register 1 (IIO1IR) 00A2 16 Interrupt Request Register 2 (IIO2IR) 11900A3 16 Interrupt Request Register 3 (IIO3IR) 00A4 16 Interrupt Request Register 4 (IIO4IR) 00A5 16 Interrupt Request Register 5 (IIO5IR) 00A6 16 00A7 16 00A8 16 Interrupt Request Register 8 (IIO8IR) 00A9 16 Interrupt Request Register 9 (IIO9IR) 11900AA 16 Interrupt Request Register 10 (IIO10IR) 00AB 16 Interrupt Request Register 11 (IIO11IR) 00AC 16 00AD 16 00AE 16 00AF 16 00B0 16 Interrupt Enable Register 0 (IIO0IE) 00B1 16 Interrupt Enable Register 1 (IIO1IE) 00B2 16 Interrupt Enable Register 2 (IIO2IE) 12000B3 16 Interrupt Enable Register 3 (IIO3IE) 00B4 16 Interrupt Enable Register 4 (IIO4IE) 00B5 16 Interrupt Enable Register 5 (IIO5IE) 00B6 16 00B7 16 00B8 16 Interrupt Enable Register 8 (IIO8IE) 00B9 16 Interrupt Enable Register 9 (IIO9IE) 12000BA 16 Interrupt Enable Register 10 (IIO10IE) 00BB 16 Interrupt Enable Register 11 (IIO11IE) 00BC 16 00BD 16 00BE 16 00BF 16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address B-3 Address Register Page 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 00E0 16 00E1 16 00E2 16 00E3 16 00E4 16 00E5 16 00E6 16 00E7 16 00E8 16 SI/O Receive Buffer Register0 (G0RB) 29000E9 16 00EA 16 Transmit Buffer/Receive Data Register 0 (G0TB/G0DR)296 00EB 16 00EC 16 Receive Input Register 0 (G0RI) 289 00ED 16 SI/O Communication Mode Register 0 (G0MR) 291 00EE 16 Transmit Output Register 0 (G0TO) 289 00EF 16 SI/O Communication Control Register 0 (G0CR) 290 Address Register Page 00F016 Data Compare Register 00 (G0CMP0) 00F116 Data Compare Register 01 (G0CMP1) 00F216 Data Compare Register 02 (G0CMP2) 29700F316 Data Compare Register 03 (G0CMP3) 00F416 Data Mask Register 00 (G0MSK0) 00F516 Data Mask Register 01 (G0MSK1) 00F616 Communication Clock Select Register (CCS) 298 00F716 00F816 Receive CRC Code Register 0 (G0RCRC)00F916 29700FA 16 Tramsmit CRC Code Register 0 (G0TCRC)00FB 16 00FC 16 SI/O Extended Mode Register 0 (G0EMR) 292 00FD 16 SI/O Extended Receive Control Register 0 (G0ERC)294 00FE 16 SI/O Special Communication Interrupt Detect Register 0 (G0IRF)295 00FF 16 SI/O Extended Transmit Control Register 0 (G0ETC)293

010016 Time Measurement Register 10 (G1TM0)/

010116 Waveform Generating Register 10 (G1PO0)

010216 Time Measurement Register 11 (G1TM1)/

010316 Waveform Generating Register 11 (G1PO1)

010416 Time Measurement Register 12 (G1TM2)/

010516 Waveform Generating Register 12 (G1PO2)

010616 Time Measurement Register 13 (G1TM3)/

010716 Waveform Generating Register 13 (G1PO3) 268/

010816 Time Measurement Register 14 (G1TM4)/ 269

010916 Waveform Generating Register 14 (G1PO4)

010A 16 Time Measurement Register 15 (G1TM5)/ 010B 16 Waveform Generating Register 16 (G1PO5) 010C 16 Time Measurement Register 16 (G1TM6)/ 010D 16 Waveform Generating Register 16 (G1PO6) 010E 16 Time Measurement Register 17 (G1TM7)/ 010F16 Waveform Generating Register 17 (G1PO7)

011016 Waveform Generating Control Register 10 (G1POCR0)

011116 Waveform Generating Control Register 11 (G1POCR1)

011216 Waveform Generating Control Register 12 (G1POCR2)

011316 Waveform Generating Control Register 13 (G1POCR3)

268011416 Waveform Generating Control Register 14 (G1POCR4)

011516 Waveform Generating Control Register 15 (G1POCR5)

011616 Waveform Generating Control Register 16 (G1POCR6)

011716 Waveform Generating Control Register 17 (G1POCR7)

011816 Time Measurement Control Register 10 (G1TMCR0)

011916 Time Measurement Control Register 11 (G1TMCR1)

011A 16 Time Measurement Control Register 12 (G1TMCR2) 011B 16 Time Measurement Control Register 13 (G1TMCR3) 267011C 16 Time Measurement Control Register 14 (G1TMCR4) 011D 16 Time Measurement Control Register 15 (G1TMCR5) 011E 16 Time Measurement Control Register 16 (G1TMCR6) 011F16 Time Measurement Control Register 17 (G1TMCR7) Blank spaces are reserved. No access is allowed.

Quick Reference by Address B-4 Address Register Page 012016 Base Timer Register1 (G1BT)012116 265

012216 Base Timer Control Register 10 (G1BCR0)

012316 Base Timer Control Register 11 (G1BCR1) 266

012416 Time Measurement Prescaler Register 16 (G1TPR6)

267012516 Time Measurement Prescaler Register 17 (G1TPR7)

012616 Function Enable Register 1 (G1FE) 270

012716 Function Select Register 1 (G1FS) 269

SI/O Receive Buffer Register 1 (G1RB) 290012916 012A 16 Transmit Buffer/Receive Data Register 1 (G1TB/G1DR)296 012B 16 012C 16 Receive Input Register 1 (G1RI) 289 012D 16 SI/O Communication Mode Register 1 (G1MR) 291 012E 16 Transmit Output Register 1 (G1TO) 289 012F16 SI/O Communication Control Register 1 (G1CR) 290

013016 Data Compare Register 10 (G1CMP0)

013116 Data Compare Register 11 (G1CMP1)

013216 Data Compare Register 12 (G1CMP2)

297013316 Data Compare Register 13 (G1CMP3)

013416 Data Mask Register 10 (G1MSK0)

013516 Data Mask Register 11 (G1MSK1)

Receive CRC Code Register1 (G1RCRC)013916 297013A 16 Transmit CRC Code Register1 (G1TCRC)013B 16 013C 16 SI/O Extended Mode Register 1 (G1EMR) 292 013D 16 SI/O Extended Receive Control Register 1 (G1ERC)294 013E 16 SI/O Special Communication Interrupt Detect Register 1 (G1IRF)296 013F16 SI/O Extended Transmit Control Register 1 (G1ETC)293 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A 16 014B 16 014C 16 014D 16 014E 16 014F16 Address Register Page 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A 16 015B 16 015C 16 015D 16 015E 16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A 16 016B 16 016C 16 016D 16 016E 16 016F16 017016 017116 017216 017316 017416 017516 017616 017716

017816 Input Function Select Register (IPS) 385

017916 Input Function Select Register A (IPSA) 386

Blank spaces are reserved. No access is allowed.

Quick Reference by Address B-5 Address Register Page 01E0 16 CAN0 Message Slot Buffer 0 Standard ID0 (C0SLOT0_0) 35401E1 16 CAN0 Message Slot Buffer 0 Standard ID1 (C0SLOT0_1) 01E2 16 CAN0 Message Slot Buffer 0 Extended ID0 (C0SLOT0_2) 35501E3 16 CAN0 Message Slot Buffer 0 Extended ID1 (C0SLOT0_3) 01E4 16 CAN0 Message Slot Buffer 0 Extended ID2 (C0SLOT0_4) 35601E5 16 CAN0 Message Slot Buffer 0 Data Length Code (C0SLOT0_5) 01E6 16 CAN0 Message Slot Buffer 0 Data 0 (C0SLOT0_6) 01E7 16 CAN0 Message Slot Buffer 0 Data 1 (C0SLOT0_7) 01E8 16 CAN0 Message Slot Buffer 0 Data 2 (C0SLOT0_8) 01E9 16 CAN0 Message Slot Buffer 0 Data 3 (C0SLOT0_9) 01EA 16 CAN0 Message Slot Buffer 0 Data 4 (C0SLOT0_10) 35701EB 16 CAN0 Message Slot Buffer 0 Data 5 (C0SLOT0_11) 01EC 16 CAN0 Message Slot Buffer 0 Data 6 (C0SLOT0_12) 01ED 16 CAN0 Message Slot Buffer 0 Data 7 (C0SLOT0_13) 01EE 16 CAN0 Message Slot Buffer 0 Time Stamp High-Order (C0SLOT0_14) 01EF 16 CAN0 Message Slot Buffer 0 Time Stamp Low-Order (C0SLOT0_15) 01F016 CAN0 Message Slot Buffer 1 Standard ID0 (C0SLOT1_0) 35401F116 CAN0 Message Slot Buffer 1 Standard ID1 (C0SLOT1_1) 01F216 CAN0 Message Slot Buffer 1 Extended ID0 (C0SLOT1_2) 35501F316 CAN0 Message Slot Buffer 1 Extended ID1 (C0SLOT1_3) 01F416 CAN0 Message Slot Buffer 1 Extended ID2 (C0SLOT1_4) 35601F516 CAN0 Message Slot Buffer 1 Data Length Code (C0SLOT1_5) 01F616 CAN0 Message Slot Buffer 1 Data 0 (C0SLOT1_6) 01F716 CAN0 Message Slot Buffer 1 Data 1 (C0SLOT1_7) 01F816 CAN0 Message Slot Buffer 1 Data 2 (C0SLOT1_8) 01F916 CAN0 Message Slot Buffer 1 Data 3 (C0SLOT1_9) 01FA 16 CAN0 Message Slot Buffer 1 Data 4 (C0SLOT1_10) 35701FB 16 CAN0 Message Slot Buffer 1 Data 5 (C0SLOT1_11) 01FC 16 CAN0 Message Slot Buffer 1 Data 6 (C0SLOT1_12) 01FD 16 CAN0 Message Slot Buffer 1 Data 7 (C0SLOT1_13) 01FE 16 CAN0 Message Slot Buffer 1 Time Stamp High-Order (C0SLOT1_14) 01FF 16 CAN0 Message Slot Buffer 1 Time Stamp Low-Order (C0SLOT1_15) 020016 CAN0 Control Register0 (C0CTLR0) 318020116 020216 CAN0 Status Register (C0STR) 323020316 020416 CAN0 Extended ID Register (C0IDR) 326020516 020616 CAN0 Configuration Register (C0CONR) 327020716

020816 CAN0 Time Stamp Register (C0TSR) 330

020A 16 CAN0 Transmit Error Count Register (C0TEC) 331 020B 16 CAN0 Receive Error Count Register (C0REC) 020C 16 CAN0 Slot Interrupt Status Register (C0SISTR) 332020D 16 020E 16 020F16 Address Register Page 021016 CAN0 Slot Interrupt Mask Register (C0SIMKR) 334021116 021216 021316

021416 CAN0 Error Interrupt Mask Register (C0EIMKR) 335

021516 CAN0 Error Interrupt Status Register (C0EISTR)336

021616 CAN0 Error Cause Register (C0EFR) 337

021716 CAN0 Baud Rate Prescaler (C0BRP) 329

021916 CAN0 Mode Register (C0MDR) 338

CAN0 Single Shot Control Register (C0SSCTLR) 340022116 022216 022316 022416 CAN0 Single Shot Status Register (C0SSSTR) 341022516 022616 022716

022816 CAN0 Global Mask Register Standard ID0 (C0GMR0)342

022916 CAN0 Global Mask Register Standard ID1 (C0GMR1)343

022A 16 CAN0 Global Mask Register Extended ID0 (C0GMR2)344 022B 16 CAN0 Global Mask Register Extended ID1 (C0GMR3)345 022C 16 CAN0 Global Mask Register Extended ID2 (C0GMR4)356 022D 16 022E 16 022F16 CAN0 Message Slot 0 Control Register (C0MCTL0)/349/

023016 CAN0 Local Mask Register A Standard ID0 (C0LMAR0)342

CAN0 Message Slot 1 Control Register (C0MCTL1)/349/

023116 CAN0Local Mask Register A Standard ID1 (C0LMAR1)343

CAN0 Message Slot 2 Control Register (C0MCTL2)/349/

023216 CAN0 Local Mask Register A Extended ID0 (C0LMAR2)344

CAN0 Message Slot 3 Control Register (C0MCTL3)/349/

023316 CAN0 Local Mask Register A Extended ID1 (C0LMAR3)345

CAN0 Message Slot 4 Control Register (C0MCTL4)/349/

023416 CAN0 Local Mask Register A Extended ID2 (C0LMAR4)346

023516 CAN0 Message Slot 5 Control Register (C0MCTL5)

023616 CAN0 Message Sot 6 Control Register (C0MCTL6)349

023716 CAN0 Message Slot 7 Control Register (C0MCTL7)

CAN0 Message Slot 8 Control register (C0MCTL8)/349/

023816 CAN0 Local Mask Register B Standard ID0 (C0LMBR0)342

Blank spaces are reserved . No access is allowed.

Quick Reference by Address B-6 Address Register Page CAN0 Message Slot 9 Control Register (C0MCTL9)/349/

023916 CAN0 Local Mask Register B Standard ID1 (C0LMBR1)343

CAN0 Message Slot 10 Control Register (C0MCTL10)/349/ 023A 16 CAN0 Local Mask Register B Extended ID0 (C0LMBR2)344 CAN0 Message Slot 11 Control Register (C0MCTL11)/349/ 023B 16 CAN0 Local Mask Register B Extended ID1 (C0LMBR3)345 CAN0 Message Slot 12 Control Register (C0MCTL12)/349/ 023C 16 CAN0 Local Mask Register B Extended ID2 (C0LMBR4)346 023D 16 CAN0 Message Slot 13 Control Register (C0MCTL13) 023E 16 CAN0 Message Slot 14 Control Register (C0MCTL14)349 023F16 CAN0 Message Slot 15 Control Register(C0MCTL15)

024016 CAN0 Slot Buffer Select Register (C0SBS) 353

024116 CAN0 Control Register 1 (C0CTLR1) 321

024216 CAN0 Sleep Control Register (C0SLPR) 322

CAN0 Acceptance Filter Support Register (C0AFS)358024516 024616 024716 024816 024916 024A 16 024B 16 024C 16 024D 16 024E 16 024F16

025016 CAN1 Slot Buffer Select Register (C1SBS) 353

025116 CAN1 Control Register 1 (C1CTLR1) 321

025216 CAN1 Sleep Control Register (C1SLPR) 322

CAN1 Acceptance Filter Support Register (C1AFS)358025516 025616 025716 025816 025916 025A 16 025B 16 025C 16 025D 16 025E 16 025F16 Address Register Page

026016 CAN1 Message Slot Buffer 0 Standard ID0 (C1SLOT0_0)

354026116 CAN1 Message Slot Buffer 0 Standard ID1 (C1SLOT0_1)

026216 CAN1 Message Slot Buffer 0 Extended ID0 (C1SLOT0_2)

355026316 CAN1 Message Slot Buffer 0 Extended ID1 (C1SLOT0_3)

026416 CAN1 Message Slot Buffer 0 Extended ID2 (C1SLOT0_4)

356026516 CAN1 Message Slot Buffer 0 Data Length Code (C1SLOT0_5)

026616 CAN1 Message Slot Buffer 0 Data 0 (C1SLOT0_6)

026716 CAN1 Message Slot Buffer 0 Data 1 (C1SLOT0_7)

026816 CAN1 Message Slot Buffer 0 Data 2 (C1SLOT0_8)

026916 CAN1 Message Slot Buffer 0 Data 3 (C1SLOT0_9)

026A 16 CAN1 Message Slot Buffer 0 Data 4 (C1SLOT0_10) 357026B 16 CAN1 Message Slot Buffer 0 Data 5 (C1SLOT0_11) 026C 16 CAN1 Message Slot Buffer 0 Data 6 (C1SLOT0_12) 026D 16 CAN1 message Slot Buffer 0 Data 7 (C1SLOT0_13) 026E 16 CAN1 Message Slot Buffer 0 Time Stamp High-Order (C1SLOT0_14) 026F16 CAN1 Message Slot Buffer 0 Time Stamp Low-Order (C1SLOT0_15)

027016 CAN1 Message Slot Buffer 1 Standard ID0 (C1SLOT1_0)

354027116 CAN1 Message Slot Buffer 1 Standard ID1 (C1SLOT1_1)

027216 CAN1 Message Slot Buffer 1 Extended ID0 (C1SLOT1_2)

355027316 CAN1 Message Slot Buffer 1 Extended ID1 (C1SLOT1_3)

027416 CAN1 Message Slot Buffer 1 Extended ID2 (C1SLOT1_4)

356027516 CAN1 Message Slot Buffer 1 Data Length Code (C1SLOT1_5)

027616 CAN1 Message Slot Buffer 1 Data 0 (C1SLOT1_6)

027716 CAN1 Message Slot Buffer 1 Data 1 (C1SLOT1_7)

027816 CAN1 Message Slot Buffer 1 Data 2 (C1SLOT1_8)

027916 CAN1 Message Slot Buffer 1 Data 3 (C1SLOT1_9)

027A 16 CAN1 Message Slot Buffer 1 Data 4 (C1SLOT1_10) 357027B 16 CAN1 Message Slot Buffer 1 Data 5 (C1SLOT1_11) 027C 16 CAN1 Message Slot Buffer 1 Data 6 (C1SLOT1_12) 027D 16 CAN1 Message Slot Buffer 1 Data 7 (C1SLOT1_13) 027E 16 CAN1 Message Slot Buffer 1 Time Stamp High-Order (C1SLOT1_14) 027F16 CAN1 Message Slot Buffer 1 Time Stamp Low-Order (C1SLOT1_15) 028016 CAN1 Control Register0 (C1CTLR0) 318028116 028216 CAN1 Status Register (C1STR) 323028316 028416 CAN1 Extended ID Register (C1IDR) 326028516 028616 CAN1 Configuration Register (C1CONR) 327028716 028816 CAN1 Time Stamp Register (C1TSR) 330028916 028A 16 CAN1 Transmit Error Count Register (C1TEC) 331 028B 16 CAN1 Receive Error Count Register (C1REC) 028C 16 CAN1 Slot Interrupt Control Register (C1SISTR) 332028D 16 028E 16 028F16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address B-7 Address Register Page 029016 CAN1 Slot Interrupt Mask Register (C1SIMKR) 334029116 029216 029316

029416 CAN1 Error Interrupt Mask Register (C1EIMKR) 335

029516 CAN1 Error Interrupt Status Register (C1EISTR) 336

029616 CAN1 Error Factor Register (C1EFR) 337

029716 CAN1 Baud Rate Prescaler (C1BRP) 329

029916 CAN1 Mode Register (C1MDR) 338

CAN1 Single Shot Control Register (C1SSCTLR) 34002A1 16 02A2 16 02A3 16 02A4 16 CAN1 Single Shot Status Register (C1SSSTR) 34102A5 16 02A6 16 02A7 16 02A8 16 CAN1 Global Mask Register Standard ID0 (C1GMR0)342 02A9 16 CAN1 Global Mask Register Standard ID1 (C1GMR1)343 02AA 16 CAN1 Global Mask Register Extended ID0 (C1GMR2)344 02AB 16 CAN1 Global Mask Register Extended ID1 (C1GMR3)345 02AC 16 CAN1 Global Mask Register Extended ID2 (C1GMR4)346 02AD 16 02AE 16 02AF 16 CAN1 Message Slot 0 Control Register (C1MCTL0)/349/ 02B0 16 CAN1 Local Mask Register A Standard ID0 (C1LMAR0)342 CAN1 Message Slot 1 Control Register (C1MCTL1)/349/ 02B1 16 CAN1 Local Mask Register A Standard ID1 (C1LMAR1)343 CAN1 Message Slot 2 Control Register (C1MCTL2)/349/ 02B2 16 CAN1 Local Mask Register A Extended ID0 (C1LMAR2)344 CAN1 Message Slot 3 Control Register (C1MCTL3)/349/ 02B3 16 CAN1 Local Mask Register A Extended ID1 (C1LMAR3)345 CAN1 Message Slot 4 Control Register (C1MCTL4)/349/ 02B4 16 CAN1 Local Mask Register A Extended ID2 (C1LMAR4)346 02B5 16 CAN1 Message Slot 5 Control Register (C1MCTL5) 02B6 16 CAN1 Message Slot 6 Control Register (C1MCTL6)349 02B7 16 CAN1 Message Slot 7 Control Register (C1MCTL7) CAN1 Message Slot 8 Control Register (C1MCTL8)/349/ 02B8 16 CAN1 Local Mask Register B Standard ID0 (C1LMBR0)342 CAN1 Message Slot 9 Control Register (C1MCTL9)/349/ 02B9 16 CAN1 Local Mask Register B Standard ID1 (C1LMBR1)343 Address Register Page CAN1 Message Slot 10 Control Register (C1MCTL10)/349/ 02BA 16 CAN1 Local Mask Register B Extended ID0 (C1LMBR2)344 CAN1 Message Slot 11 Control Register (C1MCTL11)/349/ 02BB 16 CAN1 Local Mask Register B Extended ID1 (C1LMBR3)345 CAN1 Message Slot 12 Control Register (C1MCTL12)/349/ 02BC 16 CAN1 Local Mask Register B Extended ID2 (C1LMBR4)346 02BD 16 CAN1 Message Slot 13 Control Register (C1MCTL13) 02BE 16 CAN1 Message Slot 14 Control Register (C1MCTL14)349 02BF 16 CAN1 Message Slot 15 Control Register (C1MCTL15) 02C0 16 X0 Register Y0 Register (X0R,Y0R)02C1 16 02C2 16 X1 Register Y1 Register (X1R,Y1R)02C3 16 02C4 16 X2 Register Y2 Register (X2R,Y2R)02C5 16 02C6 16 X3 Register Y3 Register (X3R,Y3R)02C7 16 02C8 16 X4 Register Y4 Register (X4R,Y4R)02C9 16 02CA 16 X5 Register Y5 Register (X5R,Y5R)02CB 16 02CC 16 X6 Register Y6 Register (X6R,Y6R)02CD 16 02CE 16 X7 Register Y7 Register (X7R,Y7R)02CF 16 25902D0 16 X8 Register Y8 Register (X8R,Y8R)02D1 16 02D2 16 X9 Register Y9 Register (X9R,Y9R)02D3 16 02D4 16 X10 Register Y10 Register (X10R,Y10R)02D5 16 02D6 16 X11 Register Y11 Register (X11R,Y11R)02D7 16 02D8 16 X12 Register Y12 Register (X12R,Y12R)02D9 16 02DA 16 X13 Register Y13 Register (X13R,Y13R)02DB 16 02DC 16 X14 Register Y14 Register (X14R,Y14R)02DD 16 02DE 16 X15 Register Y15 Register (X15R,Y15R)02DF 16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address B-8 Address Register Page 02E0 16 X/Y Control Register (XYC) 259 02E1 16 02E2 16 02E3 16 02E4 16 UART1 Special Mode Register 4 (U1SMR4) 191 02E5 16 UART1 Special Mode Register 3 (U1SMR3) 190 02E6 16 UART1 Special Mode Register 2 (U1SMR2) 189 02E7 16 UART1 Special Mode Register (U1SMR) 188 02E8 16 UART1 Transmit/Receive Mode Register (U1MR) 18602E9 16 UART1 Bit Rate Register (U1BRG) 02EA 16 UART1 Transmit Buffer Register (U1TB) 18502EB 16 02EC 16 UART1 Transmit/Receive Control Register 0 (U1C0)187 02ED 16 UART1 Transmit/Receive Control Register 1 (U1C1)188 02EE 16 UART1 Receive Buffer Register (U1RB) 18502EF 16 02F016 02F116 02F216 02F316 02F416 UART4 Special Mode Register 4 (U4SMR4) 191 02F516 UART4 Special Mode Register 3 (U4SMR3) 190 02F616 UART4 Special Mode Register 2 (U4SMR2) 189 02F716 UART4 Special Mode Register (U4SMR) 188 02F816 UART4 Transmit/Receive Mode Register (U4MR) 18602F916 UART4 Bit Rate Register (U4BRG) 02FA 16 UART4 Transmit Buffer Register (U4TB) 18502FB 16 02FC 16 UART4 Transmit/Receive Control Register 0 (U4C0)187 02FD 16 UART4 Transmit/Receive Control Register 1 (U4C1)188 02FE 16 UART4 Receive Buffer Register (U4RB) 18502FF 16

030016 Timer B3,B4,B5 Count Start Flag (TBSR) 165

Timer A1-1 Register (TA11)030316 030416 Timer A2-1 Register (TA21) 178030516 030616 Timer A4-1 Register (TA41)030716

030816 Three-Phase PWM Control Register 0 (INVC0) 175

030916 Three-Phase PWM Control Register 1 (INVC1) 176

030A 16 Three-Phase Output Buffer Register 0 (IDB0) 177030B 16 Three-Phase Output Buffer Register 1 (IDB1) 030C 16 Dead Time Timer (DTT) 177 030D 16 Timer B2 Interrupt Generating Frequency Set Counter (ICTB2)178 030E 16 030F16 Address Register Page 031016 Timer B3 Register (TB3)031116 031216 Timer B4 Register (TB4) 163031316 031416 Timer B5 Register (TB5)031516 031616 031716 031816 031916 031A 16 031B 16 Timer B3 Mode Register (TB3MR) 031C 16 Timer B4 Mode Register (TB4MR) 164 031D 16 Timer B5 Mode Register (TB5MR) 031E 16 031F16 External Interrupt Request Source Select Register (IFSR)114 032016 032116 032216 032316

032416 UART3 Special Mode Register 4 (U3SMR4) 191

032516 UART3 Special Mode Register 3 (U3SMR3) 190

032616 UART3 Special Mode Register 2 (U3SMR2) 189

032716 UART3 Special Mode Register (U3SMR) 188

032816 UART3 Transmit/Receive Mode Register (U3MR)

186032916 UART3 Bit Rate Register (U3BRG)

UART3 Transmit Buffer Register (U3TB) 185032B 16 032C 16 UART3 Transmit/Receive Control Register 0 (U3C0)187 032D 16 UART3 Transmit/Receive Control Register 1 (U3C1)188 032E 16 UART3 Receive Buffer Register (U3RB) 185032F16 033016 033116 033216 033316

033416 UART2 Special Mode Register 4 (U2SMR4) 191

033516 UART2 Special Mode Register 3 (U2SMR3) 190

033616 UART2 Special Mode Register 2 (U2SMR2) 189

033716 UART2 Special Mode Register (U2SMR) 188

033816 UART2 Transmit/Receive Mode Register (U2MR)

186033916 UART2 Bit Rate Register (U2BRG)

UART2 Transmit Buffer Register (U2TB) 185033B 16 033C 16 UART2 Transmit/Receive Control Register 0 (U2C0)187 033D 16 UART2 Transmit/Receive Control Register 1 (U2C1)188 033E 16 UART2 Receive Buffer Register (U2RB) 185033F16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address B-9 Address Register Page

034016 Count Start Flag (TABSR) 148

034116 Clock Prescaler Reset Flag (CPSRF) 77

034216 One-Shot Start Flag (ONSF) 149

034316 Trigger Select Register (TRGSR) 150

034416 Up/Down Flag (UDF) 149

Timer A0 Register (TA0)034716 034816 Timer A1 Register (TA1)034916 034A 16 Timer A2 Register (TA2) 147034B 16 034C 16 Timer A3 Register (TA3)034D 16 034E 16 Timer A4 Register (TA4)034F16 035016 Timer B0 Register (TB0)035116 035216 Timer B1 Register (TB1) 163035316 035416 Timer B2 Register (TB2)035516

035616 Timer A0 Mode Register (TA0MR)

035716 Timer A1 Mode Register (TA1MR)

035816 Timer A2 Mode Register (TA2MR) 148

035916 Timer A3 Mode Register (TA3MR)

035A 16 Timer A4 Mode Register (TA4MR) 035B 16 Timer B0 Mode Register (TB0MR) 035C 16 Timer B1 Mode Register (TB1MR) 164 035D 16 Timer B2 Mode Register (TB2MR) 035E 16 Timer B2 Special Mode Register (TB2SC) 178 035F16 Count Source Prescaler Register (TCSPR) 77 036016 036116 036216 036316

036416 UART0 Special Mode Register 4 (U0SMR4) 191

036516 UART0 Special Mode Register 3 (U0SMR3) 190

036616 UART0 Special Mode Register 2 (U0SMR2) 189

036716 UART0 Special Mode Register (U0SMR) 188

036816 UART0 Transmit/Receive Mode Register (U0MR)

186036916 UART0 Bit Rate Register (U0BRG)

UART0 Transmit Buffer Register (U0TB) 185036B 16 036C 16 UART0 Transmit/Receive Control Register 0 (U0C0)187 036D 16 UART0 Transmit/Receive Control Register 1 (U0C1)188 036E 16 UART0 Receive Buffer Register (U0RB) 185036F16 Address Register Page 037016 037116 037216 037316 037416 037516 037616 037716

037816 DMA0 Request Source Select Register (DM0SL)

037916 DMA1 Request Source Select Register (DM1SL)

127037A 16 DMA2 Request Source Select Register (DM2SL) 037B 16 DMA3 Request Source Select Register (DM3SL) 037C 16 CRC Data Register (CRCD)037D 16 257 037E 16 CRC Input Register (CRCIN) 037F16 038016 A/D0 Register0 (AD00)038116 038216 A/D0 Register1 (AD01)038316 038416 A/D0 Register2 (AD02)038516 038616 A/D0 Register3 (AD03)038716 242038816 A/D0 Register4 (AD04)038916 038A 16 A/D0 Register5 (AD05)038B 16 038C 16 A/D0 Register6 (AD06)038D 16 038E 16 A/D0 Register7 (AD07)038F16 039016 039116

039216 A/D0 Control Register 4 (AD0CON4) 242

039416 A/D0 Control Register 2 (AD0CON2) 240

039516 A/D0 Control Register 3 (AD0CON3) 241

039616 A/D0 Control Register 0 (AD0CON0) 238

039716 A/D0 Control Register 1 (AD0CON1) 239

039816 D/A Register 0 (DA0) 256

039A 16 D/A Register 1 (DA1) 256 039B 16 039C 16 D/A Control Register (DACON) 256 039D 16 039E 16 039F16 Blank spaces are reserved. No access is allowed.

Quick Reference by Address B-10 Address Register Page 03A0 16 Function Select Register A8 (PS8) 376 03A1 16 Function Select Register A9 (PS9) 377 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 Function Select Register D1 (PSD1) 382 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 Function Select Register C2 (PSC2) 381 03AD 16 Function Select Register C3 (PSC3) 382 03AE 16 03AF 16 Function Select Register C (PSC) 381 03B0 16 Function Select Register A0 (PS0) 37303B1 16 Function Select Register A1 (PS1) 03B2 16 Function Select Register B0 (PSL0) 37803B3 16 Function Select Register B1 (PSL1) 03B4 16 Function Select Register A2 (PS2) 37403B5 16 Function Select Register A3 (PS3) 03B6 16 Function Select Register B2 (PSL2) 37903B7 16 Function Select Register B3 (PSL3) 03B8 16 03B9 16 Function Select Register A5 (PS5) 375 03BA 16 03BB 16 03BC 16 Function Select Register A6 (PS6) 375 03B5 16 Function Select Register A7 (PS7) 376 03B6 16 Function Select Register B6 (PSL6) 38003B7 16 Function Select Register B7 (PSL7) 03C0 16 Port P6 Register (P6) 372 03C1 16 Port P7 Register (P7) 03C2 16 Port P6 Direction Register (PD6) 37103C3 16 Port P7 Direction Register (PD7) 03C4 16 Port P8 Register (P8) 37203C5 16 Port P9 Register (P9) 03C6 16 Port P8 Direction Register (PD8) 37103C7 16 Port P9 Direction Register (PD9) 03C8 16 Port P10 Register (P10) 37203C9 16 Port P11 Register (P11) 03CA 16 Port P10 Direction Register (PD10) 37103CB 16 Port P11 Direction Register(PD11) 03CC 16 Port P12 Register (P12) 37203CD 16 Port P13 Register (P13) 03CE 16 Port P12 Direction Register (PD12) 37103CF 16 Port P13 Direction Register (PD13) Address Register Page 03D0 16 Port P14 Register (P14) 37203D1 16 Port P15 Register (P15) 03D2 16 Port P14 Direction Register (PD14) 37103D3 16 Port P15 Direction Register (PD15) 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-Up Control Register 2 (PUR2) 383 03DB 16 Pull-Up Control Register 3 (PUR3) 38403DC 16 Pull-Up Control Register 4 (PUR4) 03DD 16 03DE 16 Output Port Select Register (OPS) 311 03DF 16 03E0 16 Port P14 Register (P0) 37203E1 16 Port P14 Register (P1) 03E2 16 Port P14 Direction Register (PD0) 37103E3 16 Port P14 Direction Register (PD1) 03E4 16 Port P14 Register (P2) 37203E5 16 Port P14 Register (P3) 03E6 16 Port P14 Direction Register (PD2) 37103E7 16 Port P14 Direction Register (PD3) 03E8 16 Port P14 Register (P4) 37203E9 16 Port P14 Register (P5) 03EA 16 Port P14 Direction Register (PD4) 37103EB 16 Port P14 Direction Register (PD5) 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-up Control Register 0 (PUR0) 38303F116 Pull-up Control Register 1 (PUR1) 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register (PCR) 385 Blank spaces are reserved. No access is allowed.

M32C/86 Group (M32C/86, M32C/86T) SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 974fo5002,80.peS00.1.veR 0010-4020B90JER 1. Overview The M32C/86 group (M32C/86, M32C/86T) microcomputer is a single-chip control unit that utilizes high- performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/86 group (M32C/86, M32C/86T) is available in 144-pin plastic molded LQFP package. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili- ties to process complex instructions by less bytes and execute instructions at higher speed. It includes a multiplier and DMAC adequate for office automation, communication devices and industrial equipments, and other high-speed processing applications.

1.1 Applications

Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc.

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M

1.2 Performance Overview

Table 1.1 lists performance overview of the M32C/86 group (M32C/86, M32C/86T). Table 1.1 M32C/86 Group (M32C/86, M32C/86T) Performance Characteristic Performance M32C/86 M32C/86T CPU Basic Instructions 108 instructions Minimum Instruction Execution Time31.3 ns (f(BCLK)=32 MHz, VCC =4.2 V to 5.5 V) Operating Mode Single-chip mode, Memory expansionSingle-chip mode mode and Microprocessor mode Address Space 16 Mbytes Memory Capacity See Table 1.2 PeripheralI/O Port 123 I/O pins and 1 input pin Function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function or Waveform generating function: 16 bits x 8 channels Communication function (Clock synchronous serial I/O, Clock asyn- chronous serial I/O, HDLC data processing) Stepping Motor Control Function Serial I/O 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) CAN Module 2 channels Supporting CAN 2.0B specification A/D Converter 10-bit A/D converter: 1 circuit, 34 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 39 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation Stop Detect Function Main clock oscillation stop detect function Voltage Detection Circuit Available (optional) Not available (3) ElectricalSupply Voltage V CC= 4.2 V to 5.5 V (f(BCLK)=32 MHz) Charact- Power Consumption 28 mA (V CC= 5 V, f(BCLK)=32 MHz) eristics 10 µA (VCC =5 V, f(BCLK)=32 kHz, in wait mode) Flash Program/Erase Supply Voltage 5.0 V ± 0.5 V Memory Program and Erase Endurance 100 times (all space) Operating Ambient Temperature –20 to 85 oC –40 to 85 oC (T version) –40 to 85oC (optional) Package 144-pin plastic molded LQFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. The cold start-up/warm start-up determine function is available only at the user's option. All options are on a request basis.

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M

1.3 Block Diagram

Figure 1.1 shows a block diagram of the M32C/86 group (M32C/86, M32C/86T) microcomputer. Figure 1.1 M32C/86 Group (M32C/86, M32C/86T) Block Diagram Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Port P14 Port P15 Port P11 Port P12 Port P10 Port P9 Port P8 P85 Port P13 R0H R0L R1H R1L FB SB FLG INTB ISP USP PC SVF SVP VCT Multiplier M32C/80 series CPU Core Clock Generation Circuit XIN - XOUT XCIN - XCOUT On-chip Oscillator PLL Frequency Synthesizer A/D Converter: 1 circuit Standard: 10 inputs Maximum: 34 inputs UART/Clock Synchronous Serial I/O: 5 channels CRC Calculation Circuit (CCITT): X16+X12+X5+1 X/Y Converter: 16 bits x 16 bits D/A Converter: 8 bits x 2 channels Peripheral Functions ROM RAM Memory 78 588 8 8 7 888888 8 DMACII DMAC Watchdog Timer (15 bits) CAN Module: 2 channels Intelligent I/O Time Measurement: 8 channels Waveform Generating: 8 channels Communication Functions: Clock Synchronous Serial I/O, UART, HDLC Data Processing Stepping Motor Control Function Timer (16 bits) Timer A: 5 channels Timer B: 6 channels Three-Phase Motor Control Circuit

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Figure 1.2 Product Numbering System Package Type: GP = Package PLQP0144KA-A (144P6Q-A) ROM Capacity: J = 512 Kbytes Memory Type: F = Flash Memory Version M30 86 5 F J GP M32C/86 Group M16C Family RAM Capacity, Pin Count, etc Classification: Blank = General Industrial Use T = T Version

1.4 Product Information

Table 1.2 lists the product information. Figure 1.2 shows the product numbering system. Table 1.2 M32C/86 Group (1) (M32C/86) As of September, 2005 Table 1.2 M32C/86 Group (2) (T Version, M32C/86T) As of September, 2005 rebmuNepyTe pyTegakcaP MOR yticapaC MAR yticapaC skrameR 803MP GJF56) A-Q6P441(A-AK4410PQLP K4+K215K 42y romeMhsalF rebmuNepyTe pyTegakcaP MOR yticapaC MAR yticapaC skrameR 803MP GTJF56) A-Q6P441(A-AK4410PQLPK 4+K215K 42y romeMhsalF

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M CAN1 OUT / SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CAN1WU / CAN1 IN / CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 P146 P145 P144 OUTC1 7 / INPC17 / P143 OUTC1 6 / INPC16 / P142 OUTC1 5 / INPC15 / P141 OUTC1 4 / INPC14 / P140 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 CAN0 IN / CAN1IN / INT1 / P83 CAN0 OUT / CAN1OUT / INT0 / P82 INPC15 / OUTC15 / U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / INPC14 / OUTC14 / CAN0IN / TA3IN / P77 ISTxD0 / INPC13 / OUTC13 / CAN0OUT / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / INPC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (2)INPC1 7 / OUTC17 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 108 107 106 105 104 103 102 101 100 131 132 133 134 135 136 137 138 139 140 141 142 143 144 125 126 127 128 129 130 119 120 121 122 123 124 113 114 115 116 117 118 109 110 111 112 M32C/86 GROUP (M32C/86, M32C/86T) P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss 0 / A8 ( / D8 ) Vcc P12 0 / GASP0 P121 / GASM0 P122 / GACP0 P123 / GACM0 P124 / GASP1 P31 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 Vss 2 / A18 Vcc 3 / A19 D 8 / P10 AN0 7 / D7 / P07 AN06 / D6 / P06 AN05 / D5 / P05 AN04 / D4 / P04 P114 OUTC1 3 / INPC13 / P113 BE1 IN / ISRxD1 / OUTC12 / INPC12 / P112 ISCLK1 / OUTC11 / INPC11 / P111 BE1 OUT / ISTxD1 / OUTC10 / INPC10 / P110 AN03 / D3 / P03 AN02 / D2 / P02 AN01 / D1 / P01 AN00 / D0 / P00 AN15 7 / P157 AN156 / P156 AN155 / P155 AN15 4 / P154 AN153 / P153 ISRxD0 / AN152 / P152 ISCLK0 / AN151 / P151 Vss ISTxD0 / AN150 / P150 Vcc KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P125 / GASM1 P126 / GACP1 P127 / GACM1 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P130 / GASP2 P131 / GASM2 Vcc P13 2 / GACP2 Vss P13 3 / GACM2 P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P134 / GASP3 P135 / GASM3 P136 / GACP3 P137 / GACM3 P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 Vss 6 / RxD1 / SCL1 / STxD1 Vcc 7 / TxD1 / SDA1 / SRxD1 P70 (1, 2) NOTES: 1. P7 0 / TA0OUT / TxD2 / SDA2 / SRxD2 / INPC16 / OUTC16 2. P7 0 and P71 are ports for the N-channel open drain output. PLQP0144KA-A (144P6Q-A)

1.5 Pin Assignment

Figures 1.3 shows the pin assignment (top view). Figure 1.3 Pin Assignment

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M BYTE CNV SS XCIN XCOUT RESET X OUT VSS XIN VCC VCC VSS P96 P95 P94 P93 P92 P91 P90 P146 P145 P144 P143 P142 P141 P140 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P137 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4/CAN1 OUT CLK4/CAN1 IN/CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CAN0 IN/CAN1 IN CAN0 OUT /CAN1 OUT CAN0 IN CAN0 OUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 INPC1 7/OUTC1 7 INPC1 6/OUTC1 6 INPC1 5/OUTC1 5 INPC1 4/OUTC1 4 INPC1 5/OUTC1 5 ISRxD0 INPC1 4/OUTC1 4/ISCLK0 INPC1 3/OUTC1 3/ISTxD0 INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 INPC1 0/OUTC1 0/ISTxD1/BE1OUT INPC1 7/OUTC1 7 INPC1 6/OUTC1 6 GACM3 ANEX1 ANEX0 DA1 DA0 Intelligent I/O Pin Bus Control Pin (1)Analog PinInterrupt Pin Pin No. Control Pin Port Timer Pin UART/CAN Pin NOTES: 1. Bus control pins in M32C/86T cannot be used. Table 1.3 Pin Characteristics

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M VSS VCC VCC VSS VCC VSS P136 P135 P134 P57 P56 P55 P54 P133 P132 P131 P130 P53 P52 P51 P50 P127 P126 P125 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P124 P123 P122 P121 P120 P30 P27 P26 P25 Timer Pin UART/CAN Pin AN2 7 AN2 6 AN2 5 RDY ALE HOLD HLDA/ALE CLK OUT /BCLK/ALE RD WRH/BHE WRL/WR CS0/A CS1/A22 CS2/A21 CS3/A20 A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) A8(/D8) A7(/D7) A6(/D6) A5(/D5) Intelligent I/O Pin Bus Control Pin (1)Analog PinInterrupt Pin Pin No. Control Pin Port NOTES: 1. Bus control pins in M32C/86T cannot be used. GACP3 GASM3 GASP3 GACM2 GACP2 GASM2 GASP2 GACM1 GACP1 GASM1 GASP1 GACM0 GACP0 GASM0 GASP0 Table 1.3 Pin Characteristics (Continued)

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS VCC AV SS VREF AV CC P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P114 P113 P112 P111 P110 P03 P02 P01 P00 P157 P156 P155 P154 P153 P152 P151 P150 P107 P106 P105 P104 P103 P102 P101 P100 P97 INT5 INT4 INT3 KI KI2 KI1 KI0 Timer Pin RxD4/SCL4/STxD4 AN2 4 AN2 3 AN2 2 AN2 1 AN2 0 AN0 7 AN0 6 AN0 5 AN0 4 AN0 3 AN0 2 AN0 1 AN0 0 AN15 7 AN15 6 AN15 5 AN15 4 AN15 3 AN15 2 AN15 1 AN15 0 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 AD TRG A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Bus Control Pin(1)Analog PinInterrupt Pin Pin No. INPC1 3/OUTC1 3 INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 INPC1 0/OUTC1 0/ISTxD1/BE1OUT ISRxD0 ISCLK0 ISTxD0 Control Pin Port UART/CAN Pin Intelligent I/O Pin NOTES: 1. Bus control pins in M32C/86T cannot be used, Table 1.3 Pin Characteristics (Continued)

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Apply 4.2 V to 5.5 V to the VCC pin. Apply 0V to the VSS pin Supplies power to the A/D converter. Connect the AVCC pin to VCC and the AV SS pin to VSS The microcomputer is in a reset state when "L" is applied to the RESET pin Switches processor mode. Connect the CNVSS pin to VSS to start up in single-chip mode or to VCC to start up in microprocessor mode Switches data bus width in external memory space 3. The data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Set to either. Connect the BYTE pin to VSS to use the microcomputer in single-chip mode Inputs and outputs data (D 0 to D7) while accessing an external memory space with separate bus Inputs and outputs data (D 8 to D15) while accessing an external memory space with 16-bit separate bus Outputs address bits A0 to A22 Outputs inversed address bit A23 Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing while accessing an external memory space with multiplexed bus Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing while accessing an external memory space with 16-bit multiplexed bus Outputs CS0 to CS3 that are chip-select signals specifying an external space Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH can be switched with WR and BHE by program WRL, WRH and RD selected: If external data bus is 16 bits wide, data is written to an even address in external memory space when WRL is held "L". Data is written to an odd address when WRH is held "L". Data is read when RD is held "L". WR, BHE and RD selected: Data is written to external memory space when WR is held "L". Data in an external memory space is read when RD is held "L". An odd address is accessed when BHE is held "L". Select WR, BHE and RD for external 8-bit data bus. ALE is a signal latching the address The microcomputer is placed in a hold state while the HOLD pin is held "L" Outputs an "L" signal while the microcomputer is placed in a hold state Bus is placed in a wait state while the RDY pin is held "L" VCC VSS AV CC AV SS RESET CNV SS BYTE D 0 to D7 D 8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL / WR WRH / BHE RD ALE HOLD HLDA RDY Power Supply Analog Power Supply Reset Input CNV SS Input to Switch External Data Bus Width(1) Bus Control Pins(1) I I I I I I/O I/O O O I/O I/O O O O I O I Classsfication Symbol I/O Type Function I : Input O : Output I/O : Input and output NOTES: 1. Bus control pins in M32C/86T cannot be used.

1.6 Pin Description

Table 1.4 Pin Description

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M XIN XOUT XCIN XCOUT BCLK CLK OUT INT0 to INT2 INT3 to INT5 NMI KI0 to KI3 TA0 OUT to TA4 OUT TA0 IN to TA4 IN TB0 IN to TB5 IN U, U, V, V, ___ W, W CTS0 to CTS4 RTS0 to RTS4 CLK0 to CLK4 RxD0 to RxD4 TxD0 to TxD4 SDA0 to SDA4 SCL0 to SCL4 STxD0 to STxD4 SRxD0 to SRxD4 SS0 to SS4 Main Clock Input Main Clock Output Sub Clock Input Sub Clock Output BCLK Output(1) Clock Output INT Interrupt Input NMI Interrupt Input Key Input Interrupt Timer A Timer B Three-phase Motor Control Timer Output Serial I/O I2C Mode Serial I/O Special Function I O I O O O I I I I/O I I O I O I/O I O I/O O I I I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT . To apply external clock, apply it to XIN and leave XOUT open I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between X CIN and XCOUT . To apply external clock, apply it to XCIN and leave XCOUT open Outputs BCLK signal Outputs the clock having the same frequency as fC , f8 or f32 Input pins for the INT interrupt Input pin for the NMI interrupt Input pins for the key input interrupt I/O pins for the timer A0 to A4 (TA0OUT is a pin for the N-channel open drain output.) Input pins for the timer A0 to A4 Input pins for the timer B0 to B5 Output pins for the three-phase motor control timer Input pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Outputs serial data (TxD2 is a pin for the N-channel open drain output.) Inputs and outputs serial data (SDA2 is a pin for the N-channel open drain output.) Inputs and outputs the transfer clock (SCL2 is a pin for the N-channel open drain output.) Outputs serial data when slave mode is selected (STxD2 is a pin for the N-channel open drain output.) Inputs serial data when slave mode is selected Input pins to control serial I/O special function I : Input O : Output I/O : Input and output NOTES: 1. Bus control pins in M32C/86T cannot be used. Table 1.4 Pin Description (Continued) Classsfication Symbol I/O Type Function

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M VREF AN 0 to AN7 AN0 0 to AN07 AN2 0 to AN27 AD TRG ANEX0 ANEX1 DA0, DA1 INPC1 0 to INPC13 INPC1 4 to INPC17 OUTC1 0 to OUTC13 OUTC1 4 to OUTC17 ISCLK0 ISCLK1 ISRxD0 ISRxD1 ISTxD0 ISTxD1 BE1 IN BE1 OUT GASP0 to GASP3 GASM0 to GASM3 GACP0 to GACP3 GACM0 to GACM3 CAN0 IN CAN1 IN CAN0 OUT CAN1 OUT CAN1WU P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P90 to P97 P100 to P107 P80 to P84 P86, P87 P8 5 Reference Voltage Input A/D Converter D/A Converter Intelligent I/O CAN I/O Ports Input Port Applies reference voltage to the A/D converter and D/A converter Analog input pins for the A/D converter Input pin for an external A/D trigger Extended analog input pin for the A/D converter and output pin in external op-amp connection mode Extended analog input pin for the A/D converter Output pin for the D/A converter Input pins for the time measurement function Output pins for the waveform generating function (OUTC1 6 and OUTC17 assigned to P70 and P71 are pins for the N-channel open drain output.) Inputs and outputs the clock for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Output pins for the stepping motor control functionInput pins for the CAN communication function Output pins for the CAN communication function Input pin for the CAN1 wake-up interrupt I/O ports for CMOS. Each port can be programmed for input or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units I/O ports having equivalent functions to P0 (P70 and P71 are ports for the N-channel open drain output.) I/O ports having equivalent functions to P0 Shares a pin with NMI. NMI input state can be got by reading P85 I I I I/O I O I O I/O I O I O O I O I I/O I/O I/O I I : Input O : Output I/O : Input and output Table 1.4 Pin Description (Continued) Classsfication Symbol I/O Type Function

Overview 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M A/D Converter I/O Ports I I/O I/O Analog input pins for the A/D converter I/O ports having equivalent functions to P0 I/O ports having equivalent functions to P0 I : Input O : Output I/O : Input and output Table 1.4 Pin Description (Continued) AN15 0 to AN157 P11 0 to P114 P12 0 to P127 P13 0 to P137 P14 0 to P146 P15 0 to P157 Classsfication Symbol I/O Type Function

Page 14 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 2. Central Processing Unit (CPU)

2.1 General Registers

2.1.1 Data Registers (R0, R1, R2 and R3)

R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3.

2.1.2 Address Registers (A0 and A1)

A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith- metic and logic operations.

2.1.3 Static Base Register (SB)

SB is a 24-bit register for SB-relative addressing.

2.1.4 Frame Base Register (FB)

FB is a 24-bit register for FB-relative addressing.

2.1.5 Program Counter (PC)

PC, 24 bits wide, indicates the address of an instruction to be executed.

2.1.6 Interrupt Table Register (INTB)

INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.

2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.

2.1.8 Flag Register (FLG)

FLG is a 16-bit register indicating a CPU state.

2.1.8.1 Carry Flag (C)

The C flag indicates whether carry or borrow has occurred after executing an instruction.

2.1.8.2 Debug Flag (D)

The D flag is for debug only. Set to "0".

2.1.8.3 Zero Flag (Z)

The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".

2.1.8.4 Sign Flag (S)

The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".

Page 15 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 2. Central Processing Unit (CPU)

2.1.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1".

2.1.8.6 Overflow Flag (O)

The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".

2.1.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged.

2.1.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.1.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.1.8.10 Reserved Space

When writing to a reserved space, set to "0". When reading, its content is indeterminate.

2.2 High-Speed Interrupt Registers

Registers associated with the high-speed interrupt are as follows: - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT) Refer to 11.4 High-Speed Interrupt for details.

2.3 DMAC-Associated Registers

Registers associated with DMAC are as follows: - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1) Refer to 13. DMAC for details.

Memory 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 3. Memory Figure 3.1 shows a memory map of the M32C/86 group (M32C/86, M32C/86T). The M32C/86 group (M32C/86, M32C/86T) provides 16-Mbyte address space addressed from 00000016 to FFFFFF 16. The internal ROM is allocated from address FFFFFF16 to lower. For example, a 64-Kbyte internal ROM is addressed from FF000016 to FFFFFF16. The fixed interrupt vectors are allocated from address FFFFDC16 to FFFFFF16. It stores the starting ad- dress of each interrupt routine. The internal RAM is allocated from address 000400 16 to higher. For example, a 10-Kbyte internal RAM is allocated from address 00040016 to 002BFF16. Besides storing data, it becomes stacks when the subrou- tine is called or an interrupt is acknowledged. SFR, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O, timers, is allocated from address 000000 16 to 0003FF16. All blank spaces within SFR are reserved and cannot be accessed by users. The special page vectors are addressed from FFFE00 16 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details. In memory expansion mode and microprocessor mode, some spaces are reserved and cannot be ac- cessed by users. SFR Internal RAM Reserved Space External Space(1) BRK Instruction Overflow Undefined Instruction FFFFFF 16 NMI 00000016 00040016 XXXXXX 16 00F00016 00FFFF 16 F0000016 YYYYYY 16 FFFFFF 16 Reserved Space(2) Internal ROM(4) Special Page Vector Table Address Match Watchdog Timer(5) Reset NOTES: 1. In memory expansion and microprocessor modes. 2. In memory expansion mode. This space becomes external space in microprocessor mode. 3. Additional 4-Kbyte space is provided for storing data. This space can be used in single-chip mode and memory expansion mode. This space becomes reserved space in microprocessor mode. 4. This space can be used in single-chip mode and memory expansion mode. This space becomes external space in microprocessor mode. 5. Watchdog timer interrupt, oscillation stop detection interrupt, and low voltage detection interrupt share vectors. FFFFDC FFFE00 16 Internal ROM(3) (Data space) Internal ROM Capacity

512 Kbytes

24 Kbytes

Figure 3.1 Memory Map

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 000016 000116 000216 000316 1000 00002(CNVss pin ="L")

000416 Processor Mode Register(1) PM0 0000 00112(CNVss pin ="H")

000516 Processor Mode Register 1 PM1 00 16

000616 System Clock Control Register 0 CM0 0000 1000 2

000716 System Clock Control Register 1 CM1 0010 0000 2

000916 Address Match Interrupt Enable Register AIER 00 16

000A 16 Protect Register PRCR XXXX 0000 2 XXXX 10002(BYTE pin ="L") 000B 16 External Data Bus Width Control Register(2) DS XXXX 00002(BYTE pin ="H") 000C 16 Main Clock Division Register MCD XXX0 1000 2 000D 16 Oscillation Stop Detection Register CM2 00 16 000E 16 Watchdog Timer Start Register WDTS XX 16 000F16 Watchdog Timer Control Register WDC 000X XXXX 2 001016

001116 Address Match Interrupt Register 0 RMAD0 000000 16

001316 Processor Mode Register 2 PM2 00 16

001516 Address Match Interrupt Register 1 RMAD1 000000 16

001716 Voltage Detection Register 2(2) VCR2 0016

001916 Address Match Interrupt Register 2 RMAD2 000000 16

001B 16 Voltage Detection Register 1(2) VCR1 0000 10002 001C 16 001D 16 Address Match Interrupt Register 3 RMAD3 000000 16 001E 16 001F16 002016 002116 002216 002316 002416 002516

002616 PLL Control Register 0 PLC0 0001 X010 2

002716 PLL Control Register 1 PLC1 000X 0000 2

002916 Address Match Interrupt Register 4 RMAD4 000000 16

002D 16 Address Match Interrupt Register 5 RMAD5 000000 16 002E 16 002F16 Low Voltage Detection Interrupt Register(2) D4INT 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The PM01 and PM00 bits in the PM0 register maintain values set before reset, even after software reset or watch- dog timer reset has been performed. 2. These registers in M32C/86T cannot be used. 4. Special Function Registers (SFR)

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 003016 003116 003216 003316 003416 003516 003616 003716 003816

003916 Address Match Interrupt Register 6 RMAD6 00000016

003D 16 Address Match Interrupt Register 7 RMAD7 00000016 003E 16 003F16 004016 004116 004216 004316 004416 004516 004616 004716

004816 External Space Wait Control Register 0(1) EWCR0 X0X0 00112

004916 External Space Wait Control Register 1(1) EWCR1 X0X0 00112

004A 16 External Space Wait Control Register 2(1) EWCR2 X0X0 00112 004B 16 External Space Wait Control Register 3(1) EWCR3 X0X0 00112 004C 16 004D 16 004E 16 004F16 005016 005116 005216 005316 005416

005516 Flash Memory Control Register 1 FMR1 0000 01012

005716 Flash Memory Control Register 0 FMR0 0000 00012

X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. These registers cannot be used in M32C/86T.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 006016 006116 006216 006316 006416 006516 006616 006716

006816 DMA0 Interrupt Control Register DM0IC XXXX X000 2

006916 Timer B5 Interrupt Control Register TB5IC XXXX X000 2

006A 16 DMA2 Interrupt Control Register DM2IC XXXX X000 2 006B 16 UART2 Receive /ACK Interrupt Control Register S2RIC XXXX X000 2 006C 16 Timer A0 Interrupt Control Register TA0IC XXXX X000 2 006D 16 UART3 Receive /ACK Interrupt Control Register S3RIC XXXX X000 2 006E 16 Timer A2 Interrupt Control Register TA2IC XXXX X000 2 006F16 UART4 Receive /ACK Interrupt Control Register S4RIC XXXX X000 2

007016 Timer A4 Interrupt Control Register TA4IC XXXX X000 2

007116 UART0/UART3 Bus Conflict Detect Interrupt Control Register BCN0IC/BCN3IC XXXX X000 2

007216 UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X000 2

007316 A/D0 Conversion Interrupt Control Register AD0IC XXXX X000 2

007416 UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X000 2

Intelligent I/O Interrupt Control Register 0/ IIO0IC/

007516 XXXX X000 2CAN Interrupt 3 Control Register CAN3IC

007616 Timer B1 Interrupt Control Register TB1IC XXXX X000 2

007716 Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X000 2

007816 Timer B3 Interrupt Control Register TB3IC XXXX X000 2

007916 Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X000 2

007A 16 INT5 Interrupt Control Register INT5IC XX00 X000 2 007B 16 007C 16 INT3 Interrupt Control Register INT3IC XX00 X000 2 007D 16 Intelligent I/O Interrupt Control Register 8 IIO8IC XXXX X000 2 007E 16 INT1 Interrupt Control Register INT1IC XX00 X000 2 Intelligent I/O Interrupt Control Register 10/ IIO10IC/ 007F16 XXXX X000 2CAN Interrupt 1 Control Register CAN1IC 008016

008116 CAN Interrupt 2 Control Register CAN2IC XXXX X000 2

008816 DMA1 Interrupt Control Register DM1IC XXXX X000 2

008916 UART2 Transmit /NACK Interrupt Control Register S2TIC XXXX X000 2

008A 16 DMA3 Interrupt Control Register DM3IC XXXX X000 2 008B 16 UART3 Transmit /NACK Interrupt Control Register S3TIC XXXX X000 2 008C 16 Timer A1 Interrupt Control Register TA1IC XXXX X000 2 008D 16 UART4 Transmit /NACK Interrupt Control Register S4TIC XXXX X000 2 008E 16 Timer A3 Interrupt Control Register TA3IC XXXX X000 2 008F16 UART2 Bus Conflict Detect Interrupt Control Register BCN2IC XXXX X000 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET

009016 UART0 Transmit /NACK Interrupt Control Register S0TIC XXXX X000 2

009116 UART1/UART4 Bus Conflict Detect Interrupt Control Register BCN1IC/BCN4IC XXXX X000 2

009216 UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X000 2

009316 Key Input Interrupt Control Register KUPIC XXXX X000 2

009416 Timer B0 Interrupt Control Register TB0IC XXXX X000 2

Intelligent I/O Interrupt Control Register 1/ IIO1IC/

009516 XXXX X000 2CAN Interrupt 4 Control Register CAN4IC

009616 Timer B2 Interrupt Control Register TB2IC XXXX X000 2

009716 Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X000 2

009816 Timer B4 Interrupt Control Register TB4IC XXXX X000 2

009916 CAN Interrupt 5 Control Register CAN5IC XXXX X000 2

009A 16 INT4 Interrupt Control Register INT4IC XX00 X000 2 009B 16 009C 16 INT2 Interrupt Control Register INT2IC XX00 X000 2 Intelligent I/O Interrupt Control Register 9/ IIO9IC/ 009D 16 XXXX X000 2CAN Interrupt 0 Control Register CAN0IC 009E 16 INT0 Interrupt Control Register INT0IC XX00 X000 2 009F16 Exit Priority Control Register RLVL XXXX 0000 2 00A0 16 Interrupt Request Register 0 IIO0IR 0000 000X 2 00A1 16 Interrupt Request Register 1 IIO1IR 0000 000X 2 00A2 16 Interrupt Request Register 2 IIO2IR 0000 000X 2 00A3 16 Interrupt Request Register 3 IIO3IR 0000 000X 2 00A4 16 Interrupt Request Register 4 IIO4IR 0000 000X 2 00A5 16 Interrupt Request Register 5 IIO5IR 0000 000X 2 00A6 16 00A7 16 00A8 16 Interrupt Request Register 8 IIO8IR 0000 000X 2 00A9 16 Interrupt Request Register 9 IIO9IR 0000 000X 2 00AA 16 Interrupt Request Register 10 IIO10IR 0000 000X 2 00AB 16 Interrupt Request Register 11 IIO11IR 0000 000X 2 00AC 16 00AD 16 00AE 16 00AF 16 00B0 16 Interrupt Enable Register 0 IIO0IE 00 16 00B1 16 Interrupt Enable Register 1 IIO1IE 00 16 00B2 16 Interrupt Enable Register 2 IIO2IE 00 16 00B3 16 Interrupt Enable Register 3 IIO3IE 00 16 00B4 16 Interrupt Enable Register 4 IIO4IE 00 16 00B5 16 Interrupt Enable Register 5 IIO5IE 00 16 00B6 16 00B7 16 00B8 16 Interrupt Enable Register 8 IIO8IE 00 16 00B9 16 Interrupt Enable Register 9 IIO9IE 00 16 00BA 16 Interrupt Enable Register 10 IIO10IE 00 16 00BB 16 Interrupt Enable Register 11 IIO11IE 00 16 00BC 16 00BD 16 00BE 16 00BF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 00E0 16 00E1 16 00E2 16 00E3 16 00E4 16 00E5 16 00E6 16 00E7 16 00E8 16 XXXX XXXX 2 SI/O Receive Buffer Register 0 G0RB00E9 16 XXX0 XXXX 2 00EA 16 Transmit Buffer/Receive Data Register 0 G0TB/G0DR XX 16 00EB 16 00EC 16 Receive Input Register 0 G0RI XX 16 00ED 16 SI/O Communication Mode Register 0 G0MR 00 16 00EE 16 Transmit Output Register 0 G0TO XX 16 00EF 16 SI/O Communication Control Register 0 G0CR 0000 X011 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 00F016 Data Compare Register 00 G0CMP0 XX 16 00F116 Data Compare Register 01 G0CMP1 XX 16 00F216 Data Compare Register 02 G0CMP2 XX 16 00F316 Data Compare Register 03 G0CMP3 XX 16 00F416 Data Mask Register 00 G0MSK0 XX 16 00F516 Data Mask Register 01 G0MSK1 XX 16 00F616 Communication Clock Select Register CCS XXXX 0000 2 00F716 00F816 XX 16 Receive CRC Code Register 0 G0RCRC00F916 XX 16 00FA 16 0016 Transmit CRC Code Register 0 G0TCRC00FB 16 0016 00FC 16 SI/O Expansion Mode Register 0 G0EMR 00 16 00FD 16 SI/O Expansion Receive Control Register 0 G0ERC 00 16 00FE 16 SI/O Special Communication Interrupt Detect Register 0 G0IRF 00 16 00FF 16 SI/O Expansion Transmit Control Register 0 G0ETC 0000 0XXX 2

010016 XX 16

Time Measurement/Waveform Generating Register 10 G1TM0/G1PO0010116 XX 16

010216 XX 16

Time Measurement/Waveform Generating Register 11 G1TM1/G1PO1010316 XX 16

010416 XX 16

Time Measurement/Waveform Generating Register 12 G1TM2/G1PO2010516 XX 16

010616 XX 16

Time Measurement/Waveform Generating Register 13 G1TM3/G1PO3010716 XX 16

010816 XX 16

Time Measurement/Waveform Generating Register 14 G1TM4/G1PO4010916 XX 16 010A 16 XX 16 Time Measurement/Waveform Generating Register 15 G1TM5/G1PO5010B 16 XX 16 010C 16 XX 16 Time Measurement/Waveform Generating Register 16 G1TM6/G1PO6010D 16 XX 16 010E 16 XX 16 Time Measurement/Waveform Generating Register 17 G1TM7/G1PO7010F16 XX 16

011016 Waveform Generating Control Register 10 G1POCR0 0000 X000 2

011116 Waveform Generating Control Register 11 G1POCR1 0X00 X000 2

011216 Waveform Generating Control Register 12 G1POCR2 0X00 X000 2

011316 Waveform Generating Control Register 13 G1POCR3 0X00 X000 2

011416 Waveform Generating Control Register 14 G1POCR4 0X00 X000 2

011516 Waveform Generating Control Register 15 G1POCR5 0X00 X000 2

011616 Waveform Generating Control Register 16 G1POCR6 0X00 X000 2

011716 Waveform Generating Control Register 17 G1POCR7 0X00 X000 2

011816 Time Measurement Control Register 10 G1TMCR0 00 16

011916 Time Measurement Control Register 11 G1TMCR1 00 16

011A 16 Time Measurement Control Register 12 G1TMCR2 00 16 011B 16 Time Measurement Control Register 13 G1TMCR3 00 16 011C 16 Time Measurement Control Register 14 G1TMCR4 00 16 011D 16 Time Measurement Control Register 15 G1TMCR5 00 16 011E 16 Time Measurement Control Register 16 G1TMCR6 00 16 011F16 Time Measurement Control Register 17 G1TMCR7 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET

012016 XX 16

Base Timer Register 1 G1BT012116 XX 16

012216 Base Timer Control Register 10 G1BCR0 00 16

012316 Base Timer Control Register 11 G1BCR1 X000 000X 2

012416 Time Measurement Prescaler Register 16 G1TPR6 00 16

012516 Time Measurement Prescaler Register 17 G1TPR7 00 16

012616 Function Enable Register 1 G1FE 00 16

012716 Function Select Register 1 G1FS 00 16

012816 XXXX XXXX 2

SI/O Receive Buffer Register 1 G1RB012916 X000 XXXX 2 012A 16 Transmit Buffer/Receive Data Register 1 G1TB/G1DR XX 16 012B 16 012C 16 Receive Input Register 1 G1RI XX 16 012D 16 SI/O Communication Mode Register 1 G1MR 00 16 012E 16 Transmit Output Register 1 G1TO XX 16 012F16 SI/O Communication Control Register 1 G1CR 0000 X011 2

013016 Data Compare Register 10 G1CMP0 XX 16

013116 Data Compare Register 11 G1CMP1 XX 16

013216 Data Compare Register 12 G1CMP2 XX 16

013316 Data Compare Register 13 G1CMP3 XX 16

013416 Data Mask Register 10 G1MSK0 XX 16

013516 Data Mask Register 11 G1MSK1 XX 16

013816 XX 16

Receive CRC Code Register 1 G1RCRC013916 XX 16 013A 16 0016 Transmit CRC Code Register 1 G1TCRC013B 16 0016 013C 16 SI/O Expansion Mode Register 1 G1EMR 00 16 013D 16 SI/O Expansion Receive Control Register 1 G1ERC 00 16 013E 16 SI/O Special Communication Interrupt Detection Register 1 G1IRF 00 16 013F16 SI/O Expansion Transmit Control Register 1 G1ETC 0000 0XXX 2 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A 16 014B 16 014C 16 014D 16 014E 16 014F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A 16 015B 16 015C 16 015D 16 015E 16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A 16 016B 16 016C 16 016D 16 016E 16 016F16 017016 017116 017216 017316 017416 017516 017616 017716

017816 Input Function Select Register IPS 00 16

017916 Input Function Select Register A IPSA 00 16

X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 01E0 16 CAN0 Message Slot Buffer 0 Standard ID0 C0SLOT0_0 XX 16 01E1 16 CAN0 Message Slot Buffer 0 Standard ID1 C0SLOT0_1 XX 16 01E2 16 CAN0 Message Slot Buffer 0 Extended ID0 C0SLOT0_2 XX 16 01E3 16 CAN0 Message Slot Buffer 0 Extended ID1 C0SLOT0_3 XX 16 01E4 16 CAN0 Message Slot Buffer 0 Extended ID2 C0SLOT0_4 XX 16 01E5 16 CAN0 Message Slot Buffer 0 Data Length Code C0SLOT0_5 XX 16 01E6 16 CAN0 Message Slot Buffer 0 Data 0 C0SLOT0_6 XX 16 01E7 16 CAN0 Message Slot Buffer 0 Data 1 C0SLOT0_7 XX 16 01E8 16 CAN0 Message Slot Buffer 0 Data 2 C0SLOT0_8 XX 16 01E9 16 CAN0 Message Slot Buffer 0 Data 3 C0SLOT0_9 XX 16 01EA 16 CAN0 Message Slot Buffer 0 Data 4 C0SLOT0_10 XX 16 01EB 16 CAN0 Message Slot Buffer 0 Data 5 C0SLOT0_11 XX 16 01EC 16 CAN0 Message Slot Buffer 0 Data 6 C0SLOT0_12 XX 16 01ED 16 CAN0 Message Slot Buffer 0 Data 7 C0SLOT0_13 XX 16 01EE 16 CAN0 Message Slot Buffer 0 Time Stamp High-Order C0SLOT0_14 XX 16 01EF 16 CAN0 Message Slot Buffer 0 Time Stamp Low-Order C0SLOT0_15 XX 16 01F016 CAN0 Message Slot Buffer 1 Standard ID0 C0SLOT1_0 XX 16 01F116 CAN0 Message Slot Buffer 1 Standard ID1 C0SLOT1_1 XX 16 01F216 CAN0 Message Slot Buffer 1 Extended ID0 C0SLOT1_2 XX 16 01F316 CAN0 Message Slot Buffer 1 Extended ID1 C0SLOT1_3 XX 16 01F416 CAN0 Message Slot Buffer 1 Extended ID2 C0SLOT1_4 XX 16 01F516 CAN0 Message Slot Buffer 1 Data Length Code C0SLOT1_5 XX 16 01F616 CAN0 Message Slot Buffer 1 Data 0 C0SLOT1_6 XX 16 01F716 CAN0 Message Slot Buffer 1 Data 1 C0SLOT1_7 XX 16 01F816 CAN0 Message Slot Buffer 1 Data 2 C0SLOT1_8 XX 16 01F916 CAN0 Message Slot Buffer 1 Data 3 C0SLOT1_9 XX 16 01FA 16 CAN0 Message Slot Buffer 1 Data 4 C0SLOT1_10 XX 16 01FB 16 CAN0 Message Slot Buffer 1 Data 5 C0SLOT1_11 XX 16 01FC 16 CAN0 Message Slot Buffer 1 Data 6 C0SLOT1_12 XX 16 01FD 16 CAN0 Message Slot Buffer 1 Data 7 C0SLOT1_13 XX 16 01FE 16 CAN0 Message Slot Buffer 1 Time Stamp High-Order C0SLOT1_14 XX 16 01FF 16 CAN0 Message Slot Buffer 1 Time Stamp Low-Order C0SLOT1_15 XX 16

020016 XX01 0X01 2(1)

CAN0 Control Register 0 C0CTLR0020116 XXXX 0000 2(1) 020216 0000 00002(1) CAN0 Status Register C0STR020316 X000 0X012(1) 020416 0016(1) CAN0 Extended ID Register C0IDR020516 0016(1) 020616 0000 XXXX 2(1) CAN0 Configuration Register C0CONR020716 0000 00002(1) 020816 0016(1) CAN0 Time Stamp Register C0TSR020916 0016(1) 020A 16 CAN0 Transmit Error Count Register C0TEC 00 16(1) 020B 16 CAN0 Receive Error Count Register C0REC 00 16(1) 020C 16 0016(1) CAN0 Slot Interrupt Status Register C0SISTR020D 16 0016(1) 020E 16 020F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 021016 0016(2) CAN0 Slot Interrupt Mask Register C0SIMKR021116 0016(2) 021216 021316

021416 CAN0 Error Interrupt Mask Register C0EIMKR XXXX X000 2(2)

021516 CAN0 Error Interrupt Status Register C0EISTR XXXX X000 2(2)

021616 CAN0 Error Cause Register C0EFR 00 16(2)

021716 CAN0 Baud Rate Prescaler C0BRP 0000 0001 2(2)

021916 CAN0 Mode Register C0MDR XXXX XX00 2(2)

022016 0016(2) CAN0 Single Shot Control Register C0SSCTLR022116 0016(2) 022216 022316 022416 0016(2) CAN0 Single Shot Status Register C0SSSTR022516 0016(2) 022616 022716

022816 CAN0 Global Mask Register Standard ID0 C0GMR0 XXX0 0000 2(2)

022916 CAN0 Global Mask Register Standard ID1 C0GMR1 XX00 0000 2(2)

022A 16 CAN0 Global Mask Register Extended ID0 C0GMR2 XXXX 0000 2(2) 022B 16 CAN0 Global Mask Register Extended ID1 C0GMR3 00 16(2) 022C 16 CAN0 Global Mask Register Extended ID2 C0GMR4 XX00 0000 2(2) 022D 16 022E 16 022F16 CAN0 Message Slot 0 Control Register / C0MCTL0/ 0000 0000 2(2)

023016 CAN0 Local Mask Register A Standard ID0 C0LMAR0 XXX0 0000 2(2)

CAN0 Message Slot 1 Control Register / C0MCTL1/ 0000 0000 2(2)

023116 CAN0 Local Mask Register A Standard ID1 C0LMAR1 XX00 0000 2(2)

CAN0 Message Slot 2 Control Register / C0MCTL2/ 0000 0000 2(2)

023216 CAN0 Local Mask Register A Extended ID0 C0LMAR2 XXXX 0000 2(2)

CAN0 Message Slot 3 Control Register / C0MCTL3/ 00 16(2)

023316 CAN0 local Mask Register A Extended ID1 C0LMAR3 00 16(2)

CAN0 Message Slot 4 Control Register / C0MCTL4/ 0000 0000 2(2)

023416 CAN0 Local Mask Register A Extended ID2 C0LMAR4 XX00 0000 2(2)

023516 CAN0 Message Slot 5 Control Register C0MCTL5 00 16(2)

023616 CAN0 Message Slot 6 Control Register C0MCTL6 00 16(2)

023716 CAN0 Message Slot 7 Control Register C0MCTL7 00 16(2)

CAN0 Message Slot 8 Control Register / C0MCTL8/ 0000 0000 2(2)

023816 CAN0 Local Mask Register B Standard ID0 C0LMBR0 XXX0 0000 2(2)

CAN0 Message Slot 9 Control Register / C0MCTL9/ 0000 0000 2(2)

023916 CAN0 Local Mask Register B Standard ID1 C0LMBR1 XX00 0000 2(2)

X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET CAN0 Message Slot 10 Control Register / C0MCTL10/ 0000 0000 2(2) 023A 16 CAN0 Local Mask Register B Extended ID0 C0LMBR2 XXXX 0000 2(2) CAN0 Message Slot 11 Control Register / C0MCTL11/ 00 16(2) 023B 16 CAN0 Local Mask Register B Extended ID1 C0LMBR3 00 16(2) CAN0 Message Slot 12 Control Register / C0MCTL12/ 0000 0000 2(2) 023C 16 CAN0 Local Mask Register B Extended ID2 C0LMBR4 XX00 0000 2(2) 023D 16 CAN0 Message Slot 13 Control Register C0MCTL13 00 16(2) 023E 16 CAN0 Message Slot 14 Control Register C0MCTL14 00 16(2) 023F16 CAN0 Message Slot 15 Control Register C0MCTL15 00 16(2)

024016 CAN0 Slot Buffer Select Register C0SBS 00 16(2)

024116 CAN0 Control Register 1 C0CTLR1 X000 00XX 2(2)

024216 CAN0 Sleep Control Register C0SLPR XXXX XXX0 2

024416 0016(2) CAN0 Acceptance Filter Support Register C0AFS024516 0116(2) 024616 024716 024816 024916 024A 16 024B 16 024C 16 024D 16 024E 16 024F16

025016 CAN1 Slot Buffer Select Register C1SBS 00 16(3)

025116 CAN1 Control Register 1 C1CTLR1 X000 00XX 2(3)

025216 CAN1 Sleep Control Register C1SLPR XXXX XXX0 2

025416 0016(3) CAN1 Acceptance Filter Support Register C1AFS025516 0116(3) 025616 025716 025816 025916 025A 16 025B 16 025C 16 025D 16 025E 16 025F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. 3. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET

026016 CAN1 Message Slot Buffer 0 Standard ID0 C1SLOT0_0 XX 16

026116 CAN1 Message Slot Buffer 0 Standard ID1 C1SLOT0_1 XX 16

026216 CAN1 Message Slot Buffer 0 Extended ID0 C1SLOT0_2 XX 16

026316 CAN1 Message Slot Buffer 0 Extended ID1 C1SLOT0_3 XX 16

026416 CAN1 Message Slot Buffer 0 Extended ID2 C1SLOT0_4 XX 16

026516 CAN1 Message Slot Buffer 0 Data Length Code C1SLOT0_5 XX 16

026616 CAN1 Message Slot Buffer 0 Data 0 C1SLOT0_6 XX 16

026716 CAN1 Message Slot Buffer 0 Data 1 C1SLOT0_7 XX 16

026816 CAN1 Message Slot Buffer 0 Data 2 C1SLOT0_8 XX 16

026916 CAN1 Message Slot Buffer 0 Data 3 C1SLOT0_9 XX 16

026A 16 CAN1 Message Slot Buffer 0 Data 4 C1SLOT0_10 XX 16 026B 16 CAN1 Message Slot Buffer 0 Data 5 C1SLOT0_11 XX 16 026C 16 CAN1 Message Slot Buffer 0 Data 6 C1SLOT0_12 XX 16 026D 16 CAN1 Message Slot Buffer 0 Data 7 C1SLOT0_13 XX 16 026E 16 CAN1 Message Slot Buffer 0 Time Stamp High-Order C1SLOT0_14 XX 16 026F16 CAN1 Message Slot Buffer 0 Time Stamp Low-Order C1SLOT0_15 XX 16

027016 CAN1 Message Slot Buffer 1 Standard ID0 C1SLOT1_0 XX 16

027116 CAN1 Message Slot Buffer 1 Standard ID1 C1SLOT1_1 XX 16

027216 CAN1 Message Slot Buffer 1 Extended ID0 C1SLOT1_2 XX 16

027316 CAN1 Message Slot Buffer 1 Extended ID1 C1SLOT1_3 XX 16

027416 CAN1 Message Slot Buffer 1 Extended ID2 C1SLOT1_4 XX 16

027516 CAN1 Message Slot Buffer 1 Data Length Code C1SLOT1_5 XX 16

027616 CAN1 Message Slot Buffer 1 Data 0 C1SLOT1_6 XX 16

027716 CAN1 Message Slot Buffer 1 Data 1 C1SLOT1_7 XX 16

027816 CAN1 Message Slot Buffer 1 Data 2 C1SLOT1_8 XX 16

027916 CAN1 Message Slot Buffer 1 Data 3 C1SLOT1_9 XX 16

027A 16 CAN1 Message Slot Buffer 1 Data 4 C1SLOT1_10 XX 16 027B 16 CAN1 Message Slot Buffer 1 Data 5 C1SLOT1_11 XX 16 027C 16 CAN1 Message Slot Buffer 1 Data 6 C1SLOT1_12 XX 16 027D 16 CAN1 Message Slot Buffer 1 Data 7 C1SLOT1_13 XX 16 027E 16 CAN1 Message Slot Buffer 1 Time Stamp High-Order C1SLOT1_14 XX 16 027F16 CAN1 Message Slot Buffer 1 Time Stamp Low-Order C1SLOT1_15 XX 16

028016 XX01 0X01 2(1)

CAN1 Control Register 0 C1CTLR0028116 XXXX 0000 2(1) 028216 0000 00002(1) CAN1 Status Register C1STR028316 X000 0X012(1) 028416 0016(1) CAN1 Extended ID Register C1IDR028516 0016(1) 028616 0000 XXXX 2(1) CAN1 Configuration Register C1CONR028716 0000 00002(1) 028816 0016(1) CAN1 Time Stamp Register C1TSR028916 0016(1) 028A 16 CAN1 Transmit Error Count Register C1TEC 00 16(1) 028B 16 CAN1 Receive Error Count Register C1REC 00 16(1) 028C 16 0016(1) CAN1 Slot Interrupt Status Register C1SISTR028D 16 0016(1) 028E 16 028F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 029016 0016 CAN1 Slot Interrupt Mask Register C1SIMKR029116 0016 029216 029316

029416 CAN1 Error Interrupt Mask Register C1EIMKR XXXX X000 2(2)

029516 CAN1 Error Interrupt Status Register C1EISTR XXXX X000 2(2)

029616 CAN1 Error Factor Register C1EFR 00 16(2)

029716 CAN1 Baud Rate Prescaler C1BRP 0000 0001 2(2)

029916 CAN1 Mode Register C1MDR XXXX XX00 2(2)

02A0 16 0016(2) CAN1 Single Shot Control Register C1SSCTLR02A1 16 0016(2) 02A2 16 02A3 16 02A4 16 0016(2) CAN1 Single Shot Status Register C1SSSTR02A5 16 0016(2) 02A6 16 02A7 16 02A8 16 CAN1 Global Mask Register Standard ID0 C1GMR0 XXX0 0000 2(2) 02A9 16 CAN1 Global Mask Register Standard ID1 C1GMR1 XX00 0000 2(2) 02AA 16 CAN1 Global Mask Register Extended ID0 C1GMR2 XXXX 0000 2(2) 02AB 16 CAN1 Global Mask Register Extended ID1 C1GMR3 00 16(2) 02AC 16 CAN1 Global Mask Register Extended ID2 C1GMR4 XX00 0000 2(2) 02AD 16 02AE 16 02AF 16 CAN1 Message Slot 0 Control Register / C1MCTL0/ 0000 0000 2(2) 02B0 16 CAN1 Local Mask Register A Standard ID0 C1LMAR0 XXX0 0000 2(2) CAN1 Message Slot 1 Control Register / C1MCTL1/ 0000 0000 2(2) 02B1 16 CAN1 Local Mask Register A Standard ID1 C1LMAR1 XX00 0000 2(2) CAN1 Message Slot 2 Control Register / C1MCTL2/ 0000 0000 2(2) 02B2 16 CAN1 Local Mask Register A Extended ID0 C1LMAR2 XXXX 0000 2(2) CAN1 Message Slot 3 Control Register / C1MCTL3/ 00 16(2) 02B3 16 CAN1 Local Mask Register A Extended ID1 C1LMAR3 00 16(2) CAN1 Message Slot 4 Control Register / C1MCTL4/ 0000 0000 2(2) 02B4 16 CAN1 Local Mask Register A Extended ID2 C1LMAR4 XX00 0000 2(2) 02B5 16 CAN1 Message Slot 5 Control Register C1MCTL5 00 16(2) 02B6 16 CAN1 Message Slot 6 Control Register C1MCTL6 00 16(2) 02B7 16 CAN1 Message Slot 7 Control Register C1MCTL7 00 16(2) CAN1 Message Slot 8 Control Register / C1MCTL8/ 0000 0000 2(2) 02B8 16 CAN1 Local Mask Register B Standard ID0 C1LMBR0 XXX0 0000 2(2) CAN1 Message Slot 9 Control Register / C1MCTL9/ 0000 0000 2(2) 02B9 16 CAN1 Local Mask Register B Standard ID1 C1LMBR1 XX00 0000 2(2) X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C1CTLR1 register switches functions for addresses 02A016 to 02BF16. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET CAN1 Message Slot 10 Control Register / C1MCTL10/ 0000 0000 2(2) 02BA 16 CAN1 Local Mask Register B Extended ID0 C1LMBR2 XXXX 0000 2(2) CAN1 Message Slot 11 Control Register / C1MCTL11/ 00 16(2) 02BB 16 CAN1 Local Mask Register B Extended ID1 C1LMBR3 00 16(2) CAN1 Message Slot 12 Control Register / C1MCTL12/ 0000 0000 2(2) 02BC 16 CAN1 Local Mask Register B Extended ID2 C1LMBR4 XX00 0000 2(2) 02BD 16 CAN1 Message Slot 13 Control Register C1MCTL13 00 16(2) 02BE 16 CAN1 Message Slot 14 Control Register C1MCTL14 00 16(2) 02BF 16 CAN1 Message Slot 15 Control Register C1MCTL15 00 16(2) 02C0 16 XX 16 X0 Register Y0 Register X0R,Y0R02C1 16 XX 16 02C2 16 XX 16 X1 Register Y1 Register X1R,Y1R02C3 16 XX 16 02C4 16 XX 16 X2 Register Y2 Register X2R,Y2R02C5 16 XX 16 02C6 16 XX 16 X3 Register Y3 Register X3R,Y3R02C7 16 XX 16 02C8 16 XX 16 X4 Register Y4 Register X4R,Y4R02C9 16 XX 16 02CA 16 XX 16 X5 Register Y5 Register X5R,Y5R02CB 16 XX 16 02CC 16 XX 16 X6 Register Y6 Register X6R,Y6R02CD 16 XX 16 02CE 16 XX 16 X7 Register Y7 Register X7R,Y7R02CF 16 XX 16 02D0 16 XX 16 X8 Register Y8 Register X8R,Y8R02D1 16 XX 16 02D2 16 XX 16 X9 Register Y9 Register X9R,Y9R02D3 16 XX 16 02D4 16 XX 16 X10 Register Y10 Register X10R,Y10R02D5 16 XX 16 02D6 16 XX 16 X11 Register Y11 Register X11R,Y11R02D7 16 XX 16 02D8 16 XX 16 X12 Register Y12 Register X12R,Y12R02D9 16 XX 16 02DA 16 XX 16 X13 Register Y13 Register X13R,Y13R02DB 16 XX 16 02DC 16 XX 16 X14 Register Y14 Register X14R,Y14R02DD 16 XX 16 02DE 16 XX 16 X15 Register Y15 Register X15R,Y15R02DF 16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C1CTLR1 register switches functions for addresses 02A016 to 02BF16. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 02E0 16 X/Y Control Register XYC XXXX XX00 2 02E1 16 02E2 16 02E3 16 02E4 16 UART1 Special Mode Register 4 U1SMR4 00 16 02E5 16 UART1 Special Mode Register 3 U1SMR3 00 16 02E6 16 UART1 Special Mode Register 2 U1SMR2 00 16 02E7 16 UART1 Special Mode Register U1SMR 00 16 02E8 16 UART1 Transmit/Receive Mode Register U1MR 00 16 02E9 16 UART1 Bit Rate Register U1BRG XX 16 02EA 16 XX 16 UART1 Transmit Buffer Register U1TB02EB 16 XX 16 02EC 16 UART1 Transmit/Receive Control Register 0 U1C0 0000 1000 2 02ED 16 UART1 Transmit/Receive Control Register 1 U1C1 0000 0010 2 02EE 16 XX 16 UART1 Receive Buffer Register U1RB02EF 16 XX 16 02F016 02F116 02F216 02F316 02F416 UART4 Special Mode Register 4 U4SMR4 00 16 02F516 UART4 Special Mode Register 3 U4SMR3 00 16 02F616 UART4 Special Mode Register 2 U4SMR2 00 16 02F716 UART4 Special Mode Register U4SMR 00 16 02F816 UART4 Transmit/Receive Mode Register U4MR 00 16 02F916 UART4 Bit Rate Register U4BRG XX 16 02FA 16 XX 16 UART4 Transmit Buffer Register U4TB02FB 16 XX 16 02FC 16 UART4 Transmit/Receive Control Register 0 U4C0 0000 1000 2 02FD 16 UART4 Transmit/Receive Control Register 1 U4C1 0000 0010 2 02FE 16 XX 16 UART4 Receive Buffer Register U4RB02FF 16 XX 16

030016 Timer B3, B4, B5 Count Start Flag TBSR 000X XXXX 2

030216 XX 16

Timer A1-1 Register TA11030316 XX 16

030416 XX 16

Timer A2-1 Register TA21030516 XX 16

030616 XX 16

Timer A4-1 Register TA41030716 XX 16

030816 Three-Phase PWM Control Register 0 INVC0 00 16

030916 Three-Phase PWM Control Register 1 INVC1 00 16

030A 16 Three-Phase Output Buffer Register 0 IDB0 XX11 1111 2 030B 16 Three-Phase Output Buffer Register 1 IDB1 XX11 1111 2 030C 16 Dead Time Timer DTT XX 16 030D 16 Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XX 16 030E 16 030F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET

031016 XX 16

Timer B3 Register TB3031116 XX 16

031216 XX 16

Timer B4 Register TB4031316 XX 16

031416 XX 16

Timer B5 Register TB5031516 XX 16 031616 031716 031816 031916 031A 16 031B 16 Timer B3 Mode Register TB3MR 00XX 0000 2 031C 16 Timer B4 Mode Register TB4MR 00XX 0000 2 031D 16 Timer B5 Mode Register TB5MR 00XX 0000 2 031E 16 031F16 External Interrupt Request Source Select Register IFSR 00 16 032016 032116 032216 032316

032416 UART3 Special Mode Register 4 U3SMR4 00 16

032516 UART3 Special Mode Register 3 U3SMR3 00 16

032616 UART3 Special Mode Register 2 U3SMR2 00 16

032716 UART3 Special Mode Register U3SMR 00 16

032816 UART3 Transmit/Receive Mode Register U3MR 00 16

032916 UART3 Bit Rate Register U3BRG XX 16

UART3 Transmit Buffer Register U3TB032B 16 XX 16 032C 16 UART3 Transmit/Receive Control Register 0 U3C0 0000 1000 2 032D 16 UART3 Transmit/Receive Control Register 1 U3C1 0000 0010 2 032E 16 XX 16 UART3 Receive Buffer Register U3RB032F16 XX 16 033016 033116 033216 033316

033416 UART2 Special Mode Register 4 U2SMR4 00 16

033516 UART2 Special Mode Register 3 U2SMR3 00 16

033616 UART2 Special Mode Register 2 U2SMR2 00 16

033716 UART2 Special Mode Register U2SMR 00 16

033816 UART2 Transmit/Receive Mode Register U2MR 00 16

033916 UART2 Bit Rate Register U2BRG XX 16

UART2 Transmit Buffer Register U2TB033B 16 XX 16 033C 16 UART2 Transmit/Receive Control Register 0 U2C0 0000 1000 2 033D 16 UART2 Transmit/Receive Control Register 1 U2C1 0000 0010 2 033E 16 XX 16 UART2 Receive Buffer Register U2RB033F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed. Address Register Symbol Value after RESET

034016 Count Start Flag TABSR 00 16

034116 Clock Prescaler Reset Flag CPSRF 0XXX XXXX 2

034216 One-Shot Start Flag ONSF 00 16

034316 Trigger Select Register TRGSR 00 16

034416 Up/Down Flag UDF 00 16

034616 XX 16

Timer A0 Register TA0034716 XX 16

034816 XX 16

Timer A1 Register TA1034916 XX 16 034A 16 XX 16 Timer A2 Register TA2034B 16 XX 16 034C 16 XX 16 Timer A3 Register TA3034D 16 XX 16 034E 16 XX 16 Timer A4 Register TA4034F16 XX 16

035016 XX 16

Timer B0 Register TB0035116 XX 16

035216 XX 16

Timer B1 Register TB1035316 XX 16

035416 XX 16

Timer B2 Register TB2035516 XX 16

035616 Timer A0 Mode Register TA0MR 00 16

035716 Timer A1 Mode Register TA1MR 00 16

035816 Timer A2 Mode Register TA2MR 00 16

035916 Timer A3 Mode Register TA3MR 00 16

035A 16 Timer A4 Mode Register TA4MR 00 16 035B 16 Timer B0 Mode Register TB0MR 00XX 0000 2 035C 16 Timer B1 Mode Register TB1MR 00XX 0000 2 035D 16 Timer B2 Mode Register TB2MR 00XX 0000 2 035E 16 Timer B2 Special Mode Register TB2SC XXXX XXX0 2 035F16 Count Source Prescaler Register(1) TCSPR 0XXX 0000 2 036016 036116 036216 036316

036416 UART0 Special Mode Register 4 U0SMR4 00 16

036516 UART0 Special Mode Register 3 U0SMR3 00 16

036616 UART0 Special Mode Register 2 U0SMR2 00 16

036716 UART0 Special Mode Register U0SMR 00 16

036816 UART0 Transmit/Receive Mode Register U0MR 00 16

036916 UART0 Bit Rate Register U0BRG XX 16

UART0 Transmit Buffer Register U0TB036B 16 XX 16 036C 16 UART0 Transmit/Receive Control Register 0 U0C0 0000 1000 2 036D 16 UART0 Transmit/Receive Control Register 1 U0C1 0000 0010 2 036E 16 XX 16 UART0 Receive Buffer Register U0RB036F16 XX 16

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 037016 037116 037216 037316 037416 037516 037616 037716

037816 DMA0 Request Source Select Register DM0SL 0X00 0000 2

037916 DMA1 Request Source Select Register DM1SL 0X00 0000 2

037A 16 DMA2 Request Source Select Register DM2SL 0X00 0000 2 037B 16 DMA3 Request Source Select Register DM3SL 0X00 0000 2 037C 16 XX 16 CRC Data Register CRCD037D 16 XX 16 037E 16 CRC Input Register CRCIN XX 16 037F16

038016 XXXX XXXX 2

A/D0 Register 0 AD00038116 0000 00002

038216 XX 16

A/D0 Register 1 AD01038316 XX 16

038416 XX 16

A/D0 Register 2 AD02038516 XX 16

038616 XX 16

A/D0 Register 3 AD03038716 XX 16

038816 XX 16

A/D0 Register 4 AD04038916 XX 16 038A 16 XX 16 A/D0 Register 5 AD05038B 16 XX 16 038C 16 XX 16 A/D0 Register 6 AD06038D 16 XX 16 038E 16 XX 16 A/D0 Register 7 AD07038F16 XX 16 039016 039116

039216 A/D0 Control Register 4 AD0CON4 XXXX 00XX 2

039416 A/D0 Control Register 2 AD0CON2 XX0X X000 2

039516 A/D0 Control Register 3 AD0CON3 XXXX X000 2

039616 A/D0 Control Register 0 AD0CON0 00 16

039716 A/D0 Control Register 1 AD0CON1 00 16

039816 D/A Register 0 DA0 XX 16

039A 16 D/A Register 1 DA1 XX 16 039B 16 039C 16 D/A Control Register DACON XXXX XX00 2 039D 16 039E 16 039F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 03A0 16 Function Select Register A8 PS8 X000 0000 2 03A1 16 Function Select Register A9 PS9 00 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 Function Select Register D1 PSD1 X0XX XX00 2 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 Function Select Register C2 PSC2 XXXX X00X 2 03AD 16 Function Select Register C3 PSC3 X0XX XXXX 2 03AE 16 03AF 16 Function Select Register C PSC 00X0 0000 2 03B0 16 Function Select Register A0 PS0 00 16 03B1 16 Function Select Register A1 PS1 00 16 03B2 16 Function Select Register B0 PSL0 00 16 03B3 16 Function Select Register B1 PSL1 00 16 03B4 16 Function Select Register A2 PS2 00X0 0000 2 03B5 16 Function Select Register A3 PS3 00 16 03B6 16 Function Select Register B2 PSL2 00X0 0000 2 03B7 16 Function Select Register B3 PSL3 00 16 03B8 16 03B9 16 Function Select Register A5 PS5 XXX0 0000 2 03BA 16 03BB 16 03BC 16 Function Select Register A6 PS6 00 16 03BD 16 Function Select Register A7 PS7 00 16 03BE 16 Function Select Register B6 PSL6 00 16 03BF 16 Function Select Register B7 PSL7 00 16 03C0 16 Port P6 Register P6 XX 16 03C1 16 Port P7 Register P7 XX 16 03C2 16 Port P6 Direction Register PD6 00 16 03C3 16 Port P7 Direction Register PD7 00 16 03C4 16 Port P8 Register P8 XX 16 03C5 16 Port P9 Register P9 XX 16 03C6 16 Port P8 Direction Register PD8 00X0 0000 2 03C7 16 Port P9 Direction Register PD9 00 16 03C8 16 Port P10 Register P10 XX 16 03C9 16 Port P11 Register P11 XX 16 03CA 16 Port P10 Direction Register PD10 00 16 03CB 16 Port P11 Direction Register PD11 XXX0 0000 2 03CC 16 Port P12 Register P12 XX 16 03CD 16 Port P13 Register P13 XX 16 03CE 16 Port P12 Direction Register PD12 00 16 03CF 16 Port P13 Direction Register PD13 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Address Register Symbol Value after RESET 03D0 16 Port P14 Register P14 XX 16 03D1 16 Port P15 Register P15 XX 16 03D2 16 Port P14 Direction Register PD14 X000 0000 2 03D3 16 Port P15 Direction Register PD15 00 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-Up Control Register 2 PUR2 00 16 03DB 16 Pull-Up Control Register 3 PUR3 00 16 03DC 16 Pull-Up Control Register 4 PUR4 XXXX 0000 2 03DD 16 03DE 16 Output Port Switch Register OPS 00 16 03DF 16 03E0 16 Port P0 Register P0 XX 16 03E1 16 Port P1 Register P1 XX 16 03E2 16 Port P0 Direction Register PD0 00 16 03E3 16 Port P1 Direction Register PD1 00 16 03E4 16 Port P2 Register P2 XX 16 03E5 16 Port P3 Register P3 XX 16 03E6 16 Port P2 Direction Register PD2 00 16 03E7 16 Port P3 Direction Register PD3 00 16 03E8 16 Port P4 Register P4 XX 16 03E9 16 Port P5 Register P5 XX 16 03EA 16 Port P4 Direction Register PD4 00 16 03EB 16 Port P5 Direction Register PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-Up Control Register 0 PUR0 00 16 03F116 Pull-Up Control Register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register PCR XXXX XXX0 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 37 974fo5002,80.peS00.1.veR 0010-4020B90JER 5. Reset)T68/C23M,68/C23M(puorG68/C23M 5. Reset Hardware reset 1, brown-out detection reset (hardware reset 2), software reset and watchdog timer reset are available to reset the microcomputer.

5.1 Hardware Reset 1

Pins, the CPU and SFR are reset by setting the RESET pin. If the supply voltage meets the recommended operating conditions, all pins are reset when a low-level ("L") signal is applied to the RESET pin (see Table 5.1). The oscillation circuit is also reset and the main clock starts oscillating. The CPU and SFR are reset when the signal applied to the RESET pin changes "L" to high level ("H"). The microcomputer executes the program in an address indicated by the reset vector. The internal RAM is not reset. When an "L" signal is applied to the RESET pin while writing data to the internal RAM, the internal RAM is in an indeterminate state. states while the RESET pin is held "L".

5.1.1 Reset on a Stable Supply Voltage

(1) Apply an "L" signal to the RESET pin (2) Provide 20 or more clock cycle inputs into the X IN pin (3) Apply an "H" signal to the RESET pin

5.1.2 Power-on Reset

(1) Apply an "L" signal to the RESET pin (2) Raise the supply voltage to the recommended operating level (3) Insert td(P-R) ms as wait time for the internal voltage to stabilize (4) Provide 20 or more clock cycle inputs into the XIN pin (5) Apply an "H" signal to the RESET pin Figure 5.1 Reset Circuit RESET VCC RESET VCC Recommended operating voltage 0.2VCC or below 0.2VCC or below td(P-R) + 20 or more clock cycle inputs provided into the XIN pin

Page 38 974fo5002,80.peS00.1.veR 0010-4020B90JER 5. Reset)T68/C23M,68/C23M(puorG68/C23M Figure 5.2 Reset Sequence BCLK XIN RESET RD WR A23 Address VCC RD WR A23 Address td(P-R) ms or more is equired 20 or more cycles are required 168 to 173 BCLK cycles Microprocessor Mode BYTE="H" Address Single-Chip Mode FFFFFE 16 FFFFFC 16 Content of reset vector Content of reset vector Content of reset vector FFFFFD 16FFFFFC 16 FFFFFE 16 FFFFFF 16 FFFFFE 16FFFFFC 16 XIN (2) Microprocessor Mode BYTE="L" (2) (1) NOTES: 1. Address data is not output from pins in single-chip mode. 2. M32C/86T cannot be used in memory expansion mode and microprocessor mode.

Page 39 974fo5002,80.peS00.1.veR 0010-4020B90JER 5. Reset)T68/C23M,68/C23M(puorG68/C23M Table 5.1 Pin States while RESET Pin is Held "L" Pin States(2) Pin Name CNVSS =V SS CNVSS =VCC BYTE=VSS BYTE=VCC P0 Input port (high-impedance) Inputs data (high-impedance) P1 Input port (high-impedance) Inputs data (high-impedance) Input port (high-impedance) P2, P3, P4 Input port (high-impedance) Output addresses (indeterminate) P50 Input port (high-impedance) Outputs the WR signal ("H")(2) P51 Input port (high-impedance) Outputs the BHE signal (indeterminate) P52 Input port (high-impedance) Outputs the RD signal ("H")(2) P53 Input port (high-impedance) Outputs the BCLK(2) P54 Input port (high-impedance) Outputs the HLDA signal (Output signal depends on an input signal to the HOLD pin.)(2) P55 Input port (high-impedance) Inputs the HOLD signal (high-impedance) P56 Input port (high-impedance) Outputs an "H" signal(2) P57 Input port (high-impedance) Inputs the RDY signal (high-impedance) P6 to P15(1)Input port (high-impedance) Input port (high-impedance) NOTES: 1. The availability of pull-up resistors is indeterminate until internal supply voltage stabilizes. 2. Each port is in this state after power is on and internal supply voltage stabilizes, but in an indeterminate state until internal supply voltage stabilizes.

5.2 Brown-Out Detection Reset (Hardware Reset 2)

Pins, the CPU and SFR are reset by using the built-in voltage detection circuit, which monitors the voltage applied to the V CC pin. When the VC26 bit in the VCR2 register is set to "1" (reset level detection circuit enabled), pins, the CPU and SFR are reset as soon as the voltage applied to the V CC pin drops to Vdet3 or below. Then, pins, the CPU and SFR are reset as soon as the voltage applied to the VCC pin reaches Vdet3r or above. The microcomputer executes the program in an address determined by the reset vector. The microcomputer executes the program after detecting Vdet3r and waiting td(S-R) ms . The same pins and registers are reset by the hardware reset 1 and brown-out detection reset, and are also placed in the same reset state. The microcomputer cannot exit stop mode by brown-out detection reset. Figure 5.3 shows an example of brown-out detection reset operation. NOTES: 1. Brown-out detection reset cannot be used in M32C/86T.

Page 40 974fo5002,80.peS00.1.veR 0010-4020B90JER 5. Reset)T68/C23M,68/C23M(puorG68/C23M Figure 5.3 Brown-out Detection Reset (Hardware Reset 2)

5.3 Software Reset

Pins, the CPU and SFR are reset when the PM03 bit in the PM0 register is set to "1" (microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector. Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is stable. In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details. Processor mode remains unchanged since the PM01 and PM00 bits in the PM0 register are not reset.

5.4 Watchdog Timer Reset

Pins, the CPU and SFR are reset when the CM06 bit in the CM0 register is set to "1" (reset) and the watchdog timer underflows. Then the microcomputer executes the program in an address determined by the reset vector. In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details. Processor mode remains unchanged since the PM01 and PM00 bits in the PM0 register are not reset. Vdet4 Vdet3 5.0V 5.0V VCC Internal Reset Signal VC13 Bit VC26 Bit VC27 Bit Set to "1" by program (reset level detection circuit enabled) Set to "1" by program (low voltage detection circuit enabled) When Stop Mode is not Used VSS Indeterminate RESET Vdet3s Vdet3r Indeterminate Indeterminate

Page 41 974fo5002,80.peS00.1.veR 0010-4020B90JER 5. Reset)T68/C23M,68/C23M(puorG68/C23M

5.5 Internal Space

Figure 5.4 shows CPU register states after reset. Refer to 4. SFR for SFR states after reset. b15 b0 b23 0016 000016 000016 00000016 00000016 00000016 00000016 00000016 00000016 00000016 Contents of addresses FFFFFE 16 to FFFFFC16 Data Register (R0H/R0L) Address Register (A0) Static Base Register (SB) Frame Base Register (FB) User Stack Pointer (USP) Interrupt Stack Pointer (ISP) Interrupt Table Register (INTB) Program Counter (PC) General Registers b15 b0 Flag Register (FLG) IPL U I O B S Z D C b7b8 X 0 0 0 X X X X 0 0 0 0 0 0 0 0 0016 0016 0016 Data Register (R2) Data Register (R3) Address Register (A1) Data Register (R1H/R1L) High-Speed Interrupt Registers b15 b0 b23 XXXX 16 XXXXXX 16 XXXXXX 16 DMAC-Associated Registers b7 b0 b23 0016 b15 Flag Save Register (SVF) PC Save Register (SVP) Vector Register (VCT) DMA Mode Register (DMD0) DMA Transfer Count Register (DCT0) DMA Transfer Count Reload Register (DRC0) DMA Memory Address Register (DMA0) DMA SFR Address Register (DSA0) DMA Memory Address Reload Register (DRA0) DMA Mode Register (DMD1) DMA Transfer Count Register (DCT1) DMA Transfer Count Reload Register (DRC1) DMA Memory Address Register (DMA1) DMA SFR Address Register (DSA1) DMA Memory Address Reload Register (DRA1) XXXX 16 XXXX 16 XXXX 16 XXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 XXXXXX 16 0 : "0" after reset X : Indeterminate after reset Figure 5.4 CPU Register States after Reset

Page 43 974fo5002,80.peS00.1.veR 0010-4020B90JER 6. Voltage Detection Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 6.2 WDC Register WDC7 WDC5 (b4 - b0) (b6) Reserved Bit Prescaler Select Bit Watchdog Timer Control Register High-Order Bit of the Watchdog Timer 0 : Divide-by-16 1 : Divide-by-128 0 : Cold start-up 1 : Warm start-up Set to "0" Symbol Address After Reset WDC 000F 16 000X XXXX 2 RW RO RW RW RW Bit Name FunctionBit Symbol Cold Start-up/ Warm Start-up Determine Flag (1,2, 3) NOTES: 1. The WDC5 bit remains set to "1", regardless of setting to "1" or "0". 2. The WDC5 bit is set to "0" when power is turned on and can be set to "1" by program only. 3. The WDC5 bit maintains a value set before reset, even after reset has been performed. b7 b6 b5 b4 b3 b2 b1 b0

Page 44 974fo5002,80.peS00.1.veR 0010-4020B90JER 6. Voltage Detection Circuit)T68/C23M,68/C23M(puorG68/C23M NOTES: 1. The VC13 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). The VC13 bit is set to "1" when the VC27 bit is set to "0" (low voltage detection circuit disabled). 2. The VCR1 register in M32C/86T cannot be used. Symbol Address After Reset VCR1 001B 16 0000 1000 2 Voltage Detection Register 1(2) RW RW RO RW VC13 (b2 - b0) (b7 - b4) Low Voltage Monitor Flag(1) Set to "0"Reserved Bit Set to "0"Reserved Bit 0 : VCC < Vdet4 1 : VCC ≥ Vdet4 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 00000 0 0 NOTES: 1. Set the VCR2 register after the PRC3 bit in the PRCR register is set to "1" (write enable). 2. To use the brown-out detection reset (hardware reset 2), set the VC26 bit to "1". 3. Set the VC27 bit to "1" to set the VC13 bit in the VCR1 register and the D42 bit in the D4INT register, or to set the D40 bit to "1" (low voltage detect interrupt enabled). 4. The reset level detection circuit and low voltage detection circuit start operating td(E-A) ms after the VC26 or VC27 bit is set to "1". 5. The VCR2 register in M32C/86T cannot be used. 6. The VC26 bit setting is disabled when the microcomputer is in stop mode. Its setting is not reset even if the voltage applied to the V CC pin drops below Vdet3. Symbol Address After Reset VCR2 0017 16 00 16(2) Voltage Detection Register 2(1, 5) RW RW RW RW (b5 - b0) VC26 Set to "0" VC27 Low Voltage Monitor Bit(3, 4) Reset Level Monitor Bit (2, 4, 6) Reserved Bit 0 : Disables reset level detection circuit 1 : Enables reset level detection circuit 0 : Disables low voltage detection circuit 1 : Enables low voltage detection circuit Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 000000 Figure 6.3 VCR1 and VCR2 Registers

Page 45 974fo5002,80.peS00.1.veR 0010-4020B90JER 6. Voltage Detection Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 6.4 D4INT Register 0 0 : CPU clock divided by 8 0 1 : CPU clock divided by 16 1 0 : CPU clock divided by 32 1 1 : CPU clock divided by 64 NOTES: 1. Set the D4INT registers after the PRC3 bit in the PRCR register is set to "1" (write enable). 2. The D40 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). Use the following procedure to set the D40 bit to "1": (1) Set the VC27 bit to "1" (2) Wait td(E-A) ms to start operating the voltage detection circuit (3) Wait required sampling time (see Table 6.2) (4) Set the D40 bit to "1" 3. When exiting stop mode using the low voltage detection circuit again after having already done so, set the D41 bit to "1" after setting it to "0". 4. The D42 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). The D42 bit is set to "0" when the VC27 bit is set to "0" (low voltage detection circuit disabled). 5. The bit is set to "0" by a program. (It remains unchanged even if it is set to "1".) 6. The D4INT register in M32C/86T cannot be used. Symbol Address After Reset D4INT 002F 16 00 16 Low Voltage Detection Interrupt Register(1,6) RW RW RW RW RW RW RW b5 b4 0: Disables the interrupt 1: Enables the interrupt 0: Disabled (cannot use the low voltage detection interrupt to exit stop/wait mode) 1: Enabled (can use the low voltage detection interrupt to exit stop/wait mode) 0: Not detected 1: Detects above or below Vdet4 0: Not detected 1: Detected D40 D41 D42 D43 WDT Overflow Detect Flag (5) Voltage Change Detect Flag (4, 5) Stop/Wait Mode Deactivation Control Bit (3) DF0 DF1 (b7 - b6) Bit Name FunctionBit Symbol Sampling Clock Select Bit Low Voltage Detection Interrupt Enable Bit(2) Reserved Bit When read, its content is indeterminate RO b7 b6 b5 b4 b3 b2 b1 b0

Page 46 974fo5002,80.peS00.1.veR 0010-4020B90JER 6. Voltage Detection Circuit)T68/C23M,68/C23M(puorG68/C23M

6.1 Low Voltage Detection Interrupt

If the D40 bit in the D4INT register is set to "1" (low voltage detection interrupt enabled), low voltage detection interrupt request is generated when the voltage applied to the VCC pin rises above or drops below Vdet4. The low voltage detection interrupt shares the same interrupt vector with the watchdog timer inter- rupt and oscillation stop detection interrupt. The D42 bit in the D4INT register determines whether the low voltage detection interrupt has been generated. Read the D42 bit using an interrupt routine when using the low voltage detection interrupt at the same time as the watchdog timer interrupt and oscillation stop detec- tion interrupt. Set the D41 bit in the D4INT register to "1" (enabled) to use the low voltage detection interrupt to exit stop mode or wait mode. The D42 bit is set to "1" (more or less than Vdet4 detected) as soon as the voltage applied to the V CC pin reaches Vdet4 due to the voltage rise and voltage drop. When the D42 bit setting changes "0" to "1", low voltage detection interrupt request is generated. Set the D42 bit to "0" (not detected) by program. However, when the D41 bit is set to "1" and the microcomputer is in stop mode or wait mode, low voltage detection interrupt request is generated, regardless of the D42 bit setting, if the voltage applied to the V CC pin is detected to be higher than Vdet4. The microcomputer then exits stop mode or wait mode. Table 6.1 shows how a low voltage detection interrupt request is generated. The DF1 and DF0 bits in the D4INT register determine sampling period that detects the voltage applied to the V CC pin rises above or drops below Vdet4. Table 6.2 shows the sampling periods. Table 6.1 Conditions to Generate Low Voltage Detection Interrupt Request - : "0" or "1" NOTES: 1. All states excluding wait mode and stop mode are handled as normal operating mode. (Refer to 9. Clock Generation Circuit.) 2. Refer to 6.1.1 Limitations for Exiting Stop/Wait Mode. 3. Sampling begins after the VC13 bit setting changes. An interrupt request is generated after sampling is completed. See Figure 6.6 for details. 4. Set to "0" by program before generating an interrupt. Table 6.2 Sampling Periods UPC kcolC )zHM( (kcolCgnilpmaS µ )s 8-yb-ediviD6 1-yb-ediviD2 3-yb-ediviD4 6-yb-ediviD 610 .30 .60 .210 .42 235 .10 .30 .60 .21 gnitarepO edoM tiB72CVt iB04Dt iB14Dt iB24D )4( 31CV tiB )3( lamroN gnitarepO edoM )1( "1"ot"0" "0"ot"1" edoMtiaW )2( , edoMpotS )2( 1- " 1"ot"0"

Page 48 974fo5002,80.peS00.1.veR 0010-4020B90JER 6. Voltage Detection Circuit)T68/C23M,68/C23M(puorG68/C23M

6.1.1 Limitations on Exiting Stop/Wait Mode

The low voltage detection interrupt is generated and the microcomputer exits stop mode as soon as the CM10 bit in the CM1 register is set to "1" (all clocks stopped) under the conditions below. Additionally, if WAIT instruction is executed under these same conditions, the low voltage detection interrupt is immedi- ately generated and the microcomputer exits wait mode. - the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled), - the D40 bit in the D4INT register is set to "1" (low voltage detection interrupt enabled), - the D41 bit in the D4INT register is set to "1" (low voltage detection interrupt is used to exit stop/wait mode), and - the voltage applied to the V CC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is set to "1") Set the CM10 bit to "1" when the VC13 bit is "0" (VCC < Vdet4), if the microcomputer is set to enter stop/ wait mode when the voltage applied to the VCC pin drops below Vdet4 and to exit stop/wait mode when the voltage applied rises to Vdet4 or above.

6.2 Cold Start-up / Warm Start-up Determine Function

The WDC5 bit in the WDC register determines either cold start-up, power-on reset, or warm start-up, reset during the microcomputer running. Default value of the WDC5 bit is "0" (cold start-up) when power-on. It is set to "1" (warm start-up) by writing desired values to the WDC register. The WDC5 bit is not reset, regardless of a software reset or reset signal input. Figure 6.7 shows a block diagram of the cold start-up/warm start-up determine function. Figure 6.8 shows its operation exmaple. Program running started Pch transistor ON (Approx. 4V) CPU reset release Set to "1" by program The WDC5 bit is set to "0" as soon as enough voltage is applied to V CC. T > 100µs "1" "0" VCC WDC5 Bit RESET Reset Sequence (Approx. 20µs @16MHz) NOTES: 1. Time difference between T1 and T2 may affect the WDC5 bit setting period. No change even if the voltage applied to RESET is 0V. Hardware Reset 1 when Power-on Write to WDC register S R Q COLD/WARM WDC5 Bit (Cold Start-up/Warm Start-up) Figure 6.7 Cold Start-up/Warm Start-up Determine Function Block Diagram Figure 6.8 Cold Start-up/Warm Start-up Determine Function Operation

Page 49 974fo5002,80.peS00.1.veR 0010-4020B90JER 7. Processor Mode)T68/C23M,68/C23M(puorG68/C23M 7. Processor Mode NOTE Use M32C/86T in single-chip mode only. M32C/86T cannot be used in memory expansion mode and microprocessor mode.

7.1 Types of Processor Mode

Single-chip mode, memory expansion mode or microprocessor mode can be selected as a processor mode. Table 7.1 lists a feature of the processor mode. Table 7.1 Processor Mode Feature edoMrossecorPe capSelbasseccAs troPO/IsasutatSniP edoMpihc-elgniSM ORlanretnI,MARlanretnI,RFS snipO/IotrostropO/IotdengissasnipllA snoitcnuflarehpirepehtrof edoMnoisnapxEyromeM lanretxE,MORlanretnI,MARlanretnI,RFS ecapS )1( sniplortnocsubotdengissasnipemoS )1( edoMrossecorporciMe capSlanretxE,MARlanretnI,RFS )1( sniplortnocsubotdengissasnipemoS )1( :SETON otrefeR.1 suB.8 .sliatedrof

Page 50 974fo5002,80.peS00.1.veR 0010-4020B90JER 7. Processor Mode)T68/C23M,68/C23M(puorG68/C23M

7.2 Setting of Processor Mode

The CNV SS pin state and the PM01 and PM00 bit settings in the PM0 register determine which processor mode is selected. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists processor mode selected by PM01 and PM00 bit settings. Table 7.2 Processor Mode after Hardware Reset Table 7.3 Processor Mode Selected by the PM01 and PM00 bit Settings VNCehtotnileveLtupnI SS nipe doMrossecorP V SS edoMpihc-elgniS V CC )2,1( edoMrossecorporciM :SETON gniylppanehw,sgnittestib00MPdna10MPfosseldrager,desseccaebtonnacMORlanretniehT.1 V CC VNCehtot SS tuo-nworbro1tesererawdrah(tesererawdrahehtgnitarenegdnanip .)tesernoitceted .saeraSCllaotdengissaebtonnacsubdexelpitluM.2 stiB00MPdna10MPe doMrossecorP 00 2 edoMpihc-elgniS 10 2 edoMnoisnapxEyromeM 01 2 eulavsihtottestonoD 11 2 edoMrossecorporciM If the PM01 and PM00 bits are rewritten, the mode corresponding to the PM01 and PM00 bits is selected regardless of CNVSS pin level. Do not change the PM01 and PM00 bits to "012" (memory expansion mode) or "112" (microprocessor mode) when the PM07 to PM02 bits in the PM0 register are being rewritten. Do not enter microprocessor mode while the CPU is executing a program in the internal ROM. Do not enter single-chip mode or memory expansion mode from microprocessor mode while the CPU is executing a program in an external memory space, the same address assigned for the internal ROM. The internal ROM cannot be accessed, regardless of PM01 and PM00 bit settings, when applying V CC to the CNVSS pin and generating the hardware reset (hardware reset 1 or brown-out detection reset). Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each processor mode.

Page 51 974fo5002,80.peS00.1.veR 0010-4020B90JER 7. Processor Mode)T68/C23M,68/C23M(puorG68/C23M 0 0 : Multiplexed bus is not used 0 1 : Access the CS2 area using the bus 0 1 : Access the CS1 area using the bus 1 1 : Access all CS areas using the bus(5) NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1"(write enable). 2. The PM01 and PM00 bits maintain values set before reset, even after software reset or watchdog timer reset has performed. 3. Set the PM01 and PM00 bits to "012" or "112" separately. Rewrite other bits before rewriting the PM01 and PM00 bits. 4. The PM04 and PM05 bits are available in memory expansion mode or microprocessor mode.

Set the PM05 and PM04 bits to "00 2" in mode 0.
Do not set the PM05 and PM04 bits to "012" in mode 2. 5. The PM05 and PM04 bits cannot be set to "112" in microprocessor mode since the microcomputer starts up with the separate bus after reset. When the PM05 and PM04 bits are set to "112" in memory expansion mode, the microcomputer can access each 64-Kbyte chip-select-assigned address space. The multiplexed bus is not available in mode 0. The microcomputer accesses the CS0 to CS2 in mode 1, CS0 and CS1 in mode 2 and CS0 to CS3 in mode 3. 6. No BCLK is output in single-chip mode even if the PM07 bit is set to "0". When a clock output is terminated in microprocessor mode or memory expansion mode, set the PM07 bit to "1" and the CM01 and CM00 bits in the CM0 register to "00 2" (I/O port P53). P53 outputs "L". 7. When the PM07 bit is set to "0" (BCLK output), set the CM01 and CM00 bits to "002". 8. M32C/86T cannot be used in memory expansion mode and microprocessor mode. Symbol Address After Reset PM0 0004 16 1000 0000 2 (CNVss = "L") 0000 0011 2 (CNVss = "H") Processor Mode Register 0(1) RW RW RW RW RW RW RW RW RW b1 b0 b5 b4 0: RD / BHE / WR 1: RD / WRH / WRL PM00 PM01 PM02 PM03 Software Reset Bit R/W Mode Select Bit PM04 PM05 (b6) 0 0: Single-chip mode 0 1: Memory expansion mode(8) 1 0: Do not set to this value 1 1: Microprocessor mode (8) Set to "0" PM07 BCLK Output Disable Bit(6) Reserved Bit 0 : BCLK is output(7) 1 : BCLK is not output The CM01 and CM00 bits in the CM0 register determine pin functions The microcomputer is reset when this bit is set to "1". When read, its content is "0". Bit Name FunctionBit Symbol Processor Mode Bit(2, 3) Multiplexed Bus Space Select Bit(4) b7 b6 b5 b4 b3 b2 b1 b0 Figure 7.1 PM0 Register

Page 52 974fo5002,80.peS00.1.veR 0010-4020B90JER 7. Processor Mode)T68/C23M,68/C23M(puorG68/C23M Figure 7.2 PM1 Register Processor Mode Register 1(1) After Reset 0016 Address 0005 Symbol PM1 RW RW RW RW RW RW RW RW PM10 PM11 PM12 External Memory Space Mode Bit(2, 4) PM13 Internal Memory Wait Bit 0 : No wait state 1 : Wait state SFR Area Wait Bit Reserved Bit Set to "0" PM14 PM15 (b7-b6) ALE Pin Select Bit(2, 4) 0 0 : No ALE 0 1 : P53/BCLK(3) 1 0 : P56 1 1 : P54/HLDA 0 0 : Mode 0 (A20 to A23 for P44 to P47) 0 1 : Mode 1 (A20 for P44, CS2 to CS0 for P45 to P47) 1 0 : Mode 2 (A20, A21 for P44, P45, CS1, CS0 for P46, P47) 1 1 : Mode 3 (CS3 to CS0 for P4 4 to P47) b1 b0 b5 b4 Bit Name FunctionBit Symbol NOTES: 1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. The PM15 and PM14 bit setting, PM11 and PM10 bit setting are available in memory expansion mode or microprocessor mode. 3. Set the CM01 and CM00 bits in the CM0 register to "002" (I/O port P53) when the PM15 and PM14 bits are set to "012" (P53/BCLK select). 4. M32C/86T cannot be used in memory expansion mode and microprocessor mode. 0 : 1 wait state 1 : 2 Wait states b7 b6 b5 b4 b3 b2 b1 b0

Page 53 974fo5002,80.peS00.1.veR 0010-4020B90JER 7. Processor Mode)T68/C23M,68/C23M(puorG68/C23M Figure 7.3 Memory Map in Each Processor Mode 000000 000400 010000 100000 200000 300000 400000 C00000 D00000 F00000 E00000 FFFFFF Single- Chip Mode Memory Expansion Mode Microprocessor Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 0 Mode 1 Mode 2 Mode 3 CS1

2 Mbytes

(1) External Space0 CS1

4 Mbytes

(2) External Space 0 CS1 (1) External Space 0 CS1 (2) External Space 0 CS2

3 Mbytes

CS1 1 MbyteExternal Space 0 CS1 1 MbyteExternal Space 0CS2 1 MbyteExternal Space 1 CS3 1 MbyteExternal Space 2CS0 1 MbyteExternal Space 3 CS2 1 MbyteExternal Space 1 CS3 1 MbyteExternal Space 2CS0 1 MbyteExternal Space 3 CS2 External Space 1External Space 2 External Space 2 External Space 1 External Space 0External Space 1 External Space 2 External Space 2 External Space 2 External Space 2 External Space 3 External Space 0 External Space 3 Internal ROM Internal ROM Not UsedNot Used Not UsedNot Used Not Used Not Used Not Used Not Used Not Used SFR SFR SFR SFR SFR SFR SFR SFR SFR Internal RAM Reserved Space Reserved Space Reserved Space Reserved Space Reserved Space Reserved Space Reserved Space Reserved Space Reserved Space Reserved Space Internal ROMReserved Space Internal ROMReserved Space Internal ROMReserved Space Internal RAM Internal RAM Internal RAM Internal RAM Internal RAM Internal RAM Internal RAM Internal RAM The EWCRi regi ster (i=0 to 3) can de termine ho w many wait states are inserted for each space CS0 to CS3. NOTES: 1. 200000 - 010000 =1984 Kbytes. 64K bytes less than 2 Mbytes. 2. 400000 - 010000 =4032 Kbytes. 64K bytes less than 4 Mbytes. 3. Addi tional 4-Kbyte space is provided i n the flash memory version for storing d ata. Block A (3) Block A (3) Block A (3) Block A (3) Block A (3) 00F000

Page 54 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M 8. Bus In memory expansion mode or microprocessor mode, some pins function as bus control pins to control the address bus and data bus. A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE, HLDA/ALE, HOLD, ALE, RDY are used as bus control pins. Bus control pins in M32C/86T cannot be used.

8.1 Bus Settings

The BYTE pin, the DS register, the PM05 and PM04 bits in the PM0 register and the PM11 and PM10 bits in the PM1 register determine bus settings. Table 8.1 lists how to change bus settings. Figure 8.1 shows the DS register. Table 8.1 Bus Settings Bus Setting Changed By Selecting External Address Bus Width DS register Setting Bus Width after Reset BYTE pin (external space 3 only) Selecting Between Separate Bus or Multiplexed Bus PM05 and PM04 bits in PM0 register Number of Chip-Select PM11 and PM10 bits in PM1 register Figure 8.1 DS Register Symbol Address After Reset DS 000B 16 XXXX 1000 2 (BYTE pin = "L") XXXX 0000 2 (BYTE pin = "H") External Data Bus Width Control Register RW RW RW RW RW DS0 DS1 DS2 DS3 (b7 - b4) 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. External Space 0 Data Bus Width Select Bit External Space 1 Data Bus Width Select Bit External Space 2 Data Bus Width Select Bit External Space 3 Data Bus Width Select Bit(1) NOTES: 1. The DS register in M32C/86T cannot be used. b7 b6 b5 b4 b3 b2 b1 b0 NOTE

Page 55 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M

8.1.1 Selecting External Address Bus

The number of externally-output address buses, the number of chip-select signals and chip-select-as- signed address space (CS area) vary depending on each external space mode. The PM11 and PM10 bits in the PM1 register determine the external space mode.

8.1.2 Selecting External Data Bus

The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the external space 3, after reset, becomes 16 bits wide when a low-level ("L") signal is applied to the BYTE pin and 8 bits wide when a high-level ("H") signal is applied. Keep the BYTE pin input level while the microcomputer is operating. Internal bus is always 16 bits wide.

8.1.3 Selecting Separate/Multiplexed Bus

The PM05 and PM04 bits in the PM0 register determine either separate or multiplexed bus as bus format.

8.1.3.1 Separate Bus

The separate bus is a bus format which allows the microcomputer to input and output data and ad- dress separatelly. The DS register selects 8-bit or 16-bit data bus as the external data bus per exter- nal space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0 becomes the data bus and port P1, the programmable I/O port. If one of the DSi bits is set to "1" (16-bit data bus), ports P0 and P1 become the data bus. Port P1 is indeterminate when the microcomputer accesses a space where the DSi bit is set to "0". The EWCRi register (i=0 to 3) determines the number of software wait states inserted, when the microcomputer accesses space using the separate bus.

8.1.3.2 Multiplexed Bus

The multiplexed bus is a bus format which allow the microcomputer to input and output data and address by timesharing. D 0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit data bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. The DSi bit controls the data bus width. The EWCRi register (i=0 to 3) controls the number of software wait states inserted, when the microcomputer accesses a space using the multiplexed bus. Refer to 8.2.4 Bus Timing for details. The multiplexed bus can be assigned to access the CS1 area, CS2 area or all CS areas. However, because the microcomputer starts operation using the separate bus after reset, the multiplexed bus cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits in the PM0 register are set to "112" (access all CS areas with the bus), 16 low-order bits, from A0 to A15, of an address are output. See Table 8.2 for details.

Page 56 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Table 8.2 Processor Mode and Port Function Access all CS Areas using the Separate Bus Single- Chip Mode Memory Expansion Mode/ Microprocessor Mode Memory Expansion Mode Data Bus Width Access all external space with 8-bit data bus NOTES: 1. The PM05 and PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in microprocessor mode because the microcomputer starts operation using the separate bus after reset. When the PM05 and PM04 bits are set to "11 2" in memory expansion mode, the microcomputer accesses 64-Kbyte memory space per chip-select using the address bus . 2. These ports become address buses when accessing space using the separate bus. 3. The PM15 and PM14 bits in the PM1 register determines which pin outputs the ALE signal. The PM02 bit in the PM0 register selects either "WRL,WRH" or "BHE,WR" combination. 6 provides an indeterminate output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port. 4. The PM11 and PM10 bits in the PM1 register determine the CS signal and address bus. PM05 to PM04 Bits in PM0 Register CS (Chip-select signal) or Address bus (A23) (Refer to 8.2 Bus Control for details)(4) Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK (Refer to 8.2 Bus Control for details)(3) P00 to P07 P10 to P17 Data bus D 0 to D 7 I/O port I/O port I/O port I/O port P20 to P27 I/O port Address bus Data bus(2) A0/D0 to A7/D7 I/O port I/O port I/O port I/O port P30 to P37 I/O port Address bus/ Data bus(2) A8/D8 to A15/D15 P40 to P43 I/O port I/O port I/O port P44 to P46 I/O port P47 I/O port P50 to P53 I/O port P54 I/O port P55 I/O port P56 I/O port P57 I/O port HOLD HOLD HOLD HOLD HOLD HOLD ALE (3) RDY RDY RDY RDY RDY RDY Access CS1 or CS2 using the Multiplexed Bus Access All Other CS Areas using the Separate Bus Data bus D 0 to D 7 Data bus D 0 to D 7 Data bus D 0 to D 7 Address bus Data bus (2) A0/D0 to A7/D7 Address bus A0 to A7 Address bus A0 to A7 Address bus Data bus A0/D0 to A7/D7 Address bus Data bus A 0/D0 to A7/D7 Address bus A8 to A15 Address bus A8 to A15 Address bus A8 to A15 Address bus A8 to A15 Address bus A16 to A19 Address bus A16 to A19 Address bus A16 to A19 Address bus A16 to A19 Data bus D 8 to D 15 Data bus D 8 to D 15 Address bus/ Data bus A8/D8 to A15/D15 Access all CS Areas using the Multiplexed Bus Access one or more external space with 16-bit data bus Access all external space with 8-bit data bus Access one or more external space with 16-bit data bus Access all external space with 8-bit data bus Access one or more external space with 16-bit data bus CS (Chip-select signal) or Address bus (A20 to A22) (Refer to 8.2 Bus Control for details)(4) HDLA (3) HDLA (3) HDLA (3) HDLA (3) HDLA (3) HDLA (3) ALE (3) ALE (3) ALE (3) ALE (3) ALE (3) Processor Mode

Page 57 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M

8.2 Bus Control

Signals, required to access external devices, are provided and software wait states are inserted as follows. The signals are available in memory expansion mode and microprocessor mode only.

8.2.1 Address Bus and Data Bus

Address bus is a signal accessing 16-Mbyte space and uses 24 control pins; A0 to A22 and A23. A23 is the inversed output signal of the highest-order address bit. Data bus is a signal for data input and output. The DS register selects an 8-bit data bus from D 0 to D7 or a 16-bit data bus from D0 to D15 for each external space. When applying a high-level ("H") signal to the BYTE pin, the data bus accessing the external memory space 3 becomes an 8-bit data bus after reset. When applying a low-level ("L") signal to the BYTE pin, the data bus accessing the external memory space 3 becomes the 16-bit data bus. When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate state until the microcomputer accesses an external memory space.

8.2.2 Chip-Select Signal

Chip-select signal shares pins with A20 to A22 and A23. The PM11 and PM10 bits in the PM1 register determine which CS area is accessed and how many chip-select signals are output. A maximum of four chip-select signals can be output. In microprocessor mode, no chip-select signal, aside from A23 which can perform as a chip-select signal, is output after reset. The chip-select signal becomes "L" while the microcomputer is accessing the external CSi area (i=0 to 3). It becomes "H" while the microcomputer is accessing other external memory space. Figure 8.2 shows an example of the address bus and chip-select signal output.

Page 58 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Figure 8.2 Address Bus and Chip-Select Signal Outputs (Separate Bus) Example 1: When the microcomputer accesses the external space j specified by another chip-select signal in the next cycle after having accessed the external space i, both address bus and chip-select signal change. NOTES: 1. The above applies to the address bus and chip-select signal in two consecutive cycles. By combining these examples, a chip-select signal extended by two or more cycles may be output. Data Bus Address Bus Chip-Select Signal CSk Access External Space i Chip-Select Signal CSp Access External Space jAddress DataData Example 2: When the microcomputer accesses the SFR or the internal ROM/RAM area in the next cycle after having accessed an external space, the chip-select signal changes but the address bus does not. Example 3: When the microcomputer accesses the space i specified by the same chip-select signal in the next cycle after having accessed the external space i, the address bus changes but the chip-select signal does not. Data Bus Address Bus Chip-Select Signal CSk Data Address Data Bus Address Bus Chip-Select Signal CSk Data Address Access External Space No Access Access External Space i Access External Space i Data Bus Address Bus Chip-Select Signal CSk Data Address Example 4: When the microcomputer does not access any space in the next cycle after having accessed an external space (no pre-fetch of an instruction is generated), neither address bus nor chip-select signal changes. Data Access External Space Access SFR, Internal ROM/RAM Area i = 0 to 3 k = 0 to 3 j = 0 to 3, excluding i p= 0 to 3, excluding k (See Figure 7.3 for i, j and p, k) k = 0 to 3 i = 0 to 3 k = 0 to 3 (See Figure 7.3 for i and k) k = 0 to 3

Page 59 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M

8.2.3 Read and Write Signals

When using a16-bit data bus, the PM02 bit in the PM0 register selects a combination of the "RD, WR and BHE" signals or the "RD, WRL and WRH" signals to determine the read or write signal. When the DS3 to DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). When any of the DS3 to DS0 bits are set to "1" (16-bit data bus) to access an 8-bit space, the combination of "RD, WR and BHE" is automatically selected regardless of the PM02 bit setting. Tables 8.3 and 8.4 list each signal operation. The RD, WR and BHE signals are combined for the read or write signal after reset. When changing the combination of "RD, WRL and WRH", set the PM02 bit first to write data to an external memory. Table 8.3 RD, WRL and WRH Signals Status of External Data BusRD BHEWR HLL LHL HLH LHH Write 1-byte data to odd address Read 1-byte data from odd address Write 1-byte data to even address Read 1-byte data from even address Data Bus A0 H H L L HLL L LHL L HL H / L LH H / L8 Bits Write data to both even and odd addresses Read data from both even and odd addresses Write 1-byte data Read 1-byte data

16 Bits

Status of External Data Bus Read data Write 1-byte data to even address Write 1-byte data to odd address Write data to both even and odd addresses WRHWRLRDData Bus

16 Bits H

H H H L H L H H L L L H H (1) L(1) L Not used Write 1-byte data Read 1-byte dataNot used8 Bits NOTES: 1. The WR signal is used instead of the WRL signal. Table 8.4 RD, WR and BHE Signals

Page 60 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M

8.2.4 Bus Timing

Bus cycle for the internal ROM and internal RAM is basically one BCLK cycle. When the PM12 bit in the PM1 register is set to "1" (wait state), the bus cycles are two BCLK cycles. Bus cycles for the SFR are basically two BCLK cycles. When the PM13 bit in the PM1 register is set to "1" (2 wait states), the bus cycles are three BCLK cycles. Basic bus cycle for an external space is 2ø (1ø+1ø) to read and to write. Bus cycle is selected by the EWCRi register (i=0 to 3) from 12 types of separate bus settings and 7 types of multiplexed bus settings. If the EWCRi04 to EWCRi00 bits are set to "00011 2" (1ø+3ø), bus cycles are four BCLK cycles. Figure 8.3 EWCR0 to EWCR3 Registers Symbol Address After Reset EWCR0 to EWCR3 0048 16, 004916, 004A16, 004B16 X0X0 00112 External Space Wait Control Register i (i=0 to 3)(3) RW RW RW RW RW RW RW EWCRi00 EWCRi01 EWCRi03 EWCRi04 (b5) (b7) EWCRi06 EWCRi02 0 0 0 0 1: 1φ + 1φ 0 0 0 1 0: 1φ + 2φ 0 0 0 1 1: 1φ + 3φ 0 0 1 0 0: 1φ + 4φ 0 0 1 0 1: 1φ + 5φ 0 0 1 1 0: 1φ + 6φ 0 1 0 1 0: 2φ + 2φ 0 1 0 1 1: 2φ + 3φ 0 1 1 0 0: 2φ + 4φ 0 1 1 0 1: 2φ + 5φ 1 0 0 1 1: 3φ + 3φ 1 0 1 0 0: 3φ + 4φ 1 0 1 0 1: 3φ + 5φ 1 0 1 1 0: 3φ + 6φ Do not set values other than the above Bit Name FunctionBit Symbol Bus Cycle Select Bit Nothing is assigned. When read, its content is indeterminate. Nothing is assigned. When read, its content is indeterminate. Recovery Cycle Addition Select Bit 0 : Adds no recovery cycle when accessing external space i 1 : Adds a recovery cycle when accessing external space i b7 b6 b5 b4 b3 b2 b1 b0 b4 b3 b2 b1 b0(1) (2) NOTES: 1. The number of bus cycles from "when bus access begins" to "when RD or WR signal becomes "L". 2. The number of bus cycles from "when RD or WR signal becomes "L" to "when it becomes "H". 3. The EWCR0 to EWCR3 registers in M32C/86T cannot be used.

Page 61 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Table 8.5 Software Wait State and Bus Cycle ecapS suBlanretxE sutatS retsigeR1MP retsigeRiRCWE )3ot0=i( selcyCsuB tiB31MPt iB21MP ot40iRCWE stiB00iRCWE RFS- -- ---- -- selcycKLCB2 1s elcycKLCB3 lanretnI MAR/MOR ---- -- selcycKLCB1 1s elcycKLCB2 lanretxE yromeM suBetarapeS- --- -- 10000 2 selcycKLCB2 01000 2 selcycKLCB3 11000 2 selcycKLCB4 00100 2 selcycKLCB5 10100 2 selcycKLCB6 01100 2 selcycKLCB7 01010 2 selcycKLCB4 11010 2 selcycKLCB5 00110 2 selcycKLCB6 11001 2 selcycKLCB6 00101 2 selcycKLCB7 01101 2 selcycKLCB9 suBdexelpitluM- --- -- 01010 2 selcycKLCB4 11010 2 selcycKLCB5 10110 2 selcycKLCB7 11001 2 selcycKLCB6 00101 2 selcycKLCB7 10101 2 selcycKLCB8 01101 2 selcycKLCB9

Page 62 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Figure 8.4 Bus Cycle with Separate Bus (1)

Bus Cycle 1φ + 1φ 1 bus cycle = 2φ
Bus Cycle 1φ + 2φ 1 bus cycle = 3φ
Bus Cycle 1φ + 3φ 1 bus cycle = 4φ • Bus Cycle 1φ + 4φ 1 bus cycle = 5φ
Bus Cycle 1φ + 5φ 1 bus cycle = 6φ
Bus Cycle 1φ + 6φ 1 bus cycle = 7φ i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH

Page 63 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Figure 8.5 Bus Cycle with Separate Bus (2)

Bus Cycle 2φ + 2φ 1 bus cycle = 4φ
Bus Cycle 2φ + 4φ BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 6φ
Bus Cycle 2φ + 3φ 1 bus cycle = 5φ i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH

Page 64 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Figure 8.6 Bus Cycle with Separate Bus (3)

Bus Cycle 3φ + 3φ 1 bus cycle = 6φ
Bus Cycle 3φ + 4φ 1 bus cycle = 7φ
Bus Cycle 3φ + 6φ 1 bus cycle = 9φ i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH

Page 65 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Figure 8.7 Bus Cycle with Multiplexed Bus (1) LA : Latch Address RD : ReadData WD : Write Data LA RD LA WD LA RD LA WD LA RD LA WD

Bus Cycle 2φ + 2φ BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE 1 bus cycle = 4φ • Bus Cycle 2φ + 3φ 1 bus cycle = 5φ
Bus Cycle 2φ + 5φ 1 bus cycle = 7φ i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE

Page 66 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M Figure 8.8 Bus Cycle with Multiplexed Bus (2) LA WD LA RD LA WD RD LA WD RD LA WD RD LA LA LA LA : Latch Address RD : Read Data WD : Write Data

Bus Cycle 3φ + 3φ 1 bus cycle = 6φ
Bus Cycle 3φ + 4φ 1 bus cycle = 7φ
Bus Cycle 3φ + 5φ 1 bus cycle = 8φ
Bus Cycle 3φ + 6φ 1 bus cycle = 9φ i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE

Page 67 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M

8.2.4.1 Bus Cycle with Recovery Cycle Added

The EWCRi06 bit in the EWCRi register (i=0 to 3) determines whether the recovery cycle is added or not. In the recovery cycle, addresses and wrie data outputs are provided continuously (using the separate bus only). Devices, which take longer address hold time and data hold time to write data, are connectable. Figure 8.9 Recovery Cycle LA LA WD RD A RD WD A : Address LA : Latch Address RD : Read Data WD : Write Data

Recovery Cycle with Separate Bus (For 1φ + 2φ) BCLK Address CS i (1) Data (Read) RD Data (Write) WR, WRL, WRH Recovery Cycle <--- Hold an Address <--- Hold Data
Recovery Cycle with Multiplexed Bus (For 2φ + 3φ) Recovery Cycle <--- Hold Data i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. BCLK CS i (1) Data (Read) RD Data (Write) WR (WRL) ALE

Page 68 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M

8.2.5 ALE Signal

The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the ALE signal. The PM15 and PM14 bits in the PM1 register determine the output pin for the ALE signal. The ALE signal is output to internal space and external space. Figure 8.10 ALE Signal and Address/Data Bus

8.2.6 RDY Signal

The RDY signal facilitates access to external devices requiring longer access time. When a low-level ("L") signal is applied to the RDY pin on the falling edge of the last BCLK of the bus cycle, wait states are inserted into the bus cycle. When a high-level ("H") signal is applied to the RDY pin on the falling edge of BCLK, the bus cycle starts running again. Table 8.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure 8.11 shows an example of the RD signal that is extended by the RDY signal. Table 8.6 Microcomputer States in Wait State(1) (1) 8-Bit Data Bus (2) 16-Bit Data Bus ALE Address Data Address D 0/A0 to D7/A7 A8 to A15 ALE Address Data Address D 0/A0 to D15/A15 A16 to A19 NOTES: 1. D0/A0 to D7/A7 are placed in high-impedance states when read. 2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port. Address Address or CSAddress or CS A16 to A19 (1) (1) (2)(2) A20/CS3 A21/CS2 A22/CS1 A23/CS0 A20/CS3 A21/CS2 A22/CS1 A23/CS0 NOTES: 1. The RDY signal cannot be accepted immediately before software wait states are inserted. metIe tatS noitallicsOn O ,suBataD,suBsserddA,langiSRW,langiSDR stroPO/IelbammargorP,ADLH,langiSELA,SC YDRnehwsaetatsemasehtsniatniaM deviecersawlangis stiucriClarehpirePlanretnIn O

Page 69 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M /LiteDiagLines/LiteDiagLines (1) Separate Bus with 2 Wait States (2) Multiplexed Bus with 2 Wait States BCLK RD CS i (i=0 to 3) RDY /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines BCLK RD CS i (i=0 to 3) RDY tsu(RDY - BCLK) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 1st cycle 2nd cycle 3rd cycle 4th cycle tsu(RDY - BCLK) Timing to receive RDY tsu(RDY-BCLK) : Setup time for RDY input Timing to receive RDY for j wait(s): j+1 cycles (j = 1 to 3) 1st cycle 2nd cycle 3rd cycle 4th cycle : Wait states inserted by RDY : Wait states inserted by program (1) (1) NOTES: 1. The chip-select signal (CSi) may be output longer depending on CPU state such as the instruction queue buffer. Timing to receive RDY Figure 8.11 RD Signal Output Extended by RDY Signal

Page 70 974fo5002,80.peS00.1.veR 0010-4020B90JER 8. Bus)T68/C23M,68/C23M(puorG68/C23M HOLD > DMAC > CPU metIs utatS noitallicsOn O EHB,SC,suBataD,suBsserddA,langiSRW,langiSDR ecnadepmi-hgiH 51Pot0P:stroPO/IelbammargorP deviecersawDLOHnehwsaetatsemasehtsniatniaM ADLH" L"stuptuO stiucriClarehpirePlanretnI )remitgodhctawehtgnidulcxe(nO langiSELA" L"stuptuO metI MARlanretnIdna,MORlanretnI,RFSgnisseccAnehwetatS suBsserddAd esseccatsalecapslanretxefosserddasdloH ataD suB daeRnehWe cnadepmi-hgiH etirWnehWe cnadepmi-hgiH HRW,LRW,RW,DR" H"stuptuO EHBd esseccatsalecapslanretxefoetatssdloH SC" H"stuptuO ELAE LAstuptuO

8.2.7 HOLD Signal

The HOLD signal transfers bus privileges from the CPU to external circuits. When a low-level ("L") signal is applied to the HOLD pin, the microcomputer enters a hold state after bus access is completed. While the HOLD pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal. Table 8.7 shows the microcomputer status in a hold state. Bus is used in the following priority order: HOLD, DMAC, CPU. Figure 8.12 Bus Priority Order Table 8.7 Microcomputer Status in Hold State

8.2.8 External Bus Status when Accessing Internal Space

Table 8.8 shows external bus states when an internal space is accessed. Table 8.8 External Bus States when Accessing Internal Space

8.2.9 BCLK Output

The CPU clock operates the CPU. P53 outputs the CPU clock signal as BCLK when the PM07 bit in the PM0 register is set to "0" (BCLK) and the CM01 and CM00 bits in the CM0 register are set to "002" (I/O port P53). No BCLK is output in single-chip mode. Refer to 9. Clock Generation Circuit for details.

Page 71 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M 9. Clock Generation Circuit

9.1 Types of the Clock Generation Circuit

Four circuits are included to generate the system clock signal:

Main clock oscillation circuit
Sub clock oscillation circuit
On-chip oscillator
PLL frequency synthesizer Table 9.1 lists specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Figures 9.2 to 9.8 show registers controlling the clock. metI kcolCniaM tiucriCnoitallicsO kcolCbuS tiucriCnoitallicsO rotallicsOpihc-nO ycneuqerFLLP rezisehtnyS esU, ecruoskcolcUPC noitcnuflarehpireP ecruoskcolc ,ecruoskcolcUPC kcolcBdnaAremiT ecruos ,ecruoskcolcUPC noitcnuflarehpireP ecruoskcolc ,ecruoskcolcUPC noitcnuflarehpireP ecruoskcolc ycneuqerFkcolCz HM23otpUz Hk867.23z HM1.xorppA zHM23otpU )3.9elbaTeeS( elbatcennoC rorotallisO tiucriClanoitiddA rotanosercimareC rotallicsolatsyrC rotallicsolatsyrC- --- -- rotallicsOrofsniP lanoitiddArofro tiucriC X NI X, TUO X NIC X, TUOC ---- -- /potSnoitallicsO noitcnuFtratseR elbaliavAe lbaliavAe lbaliavAe lbaliavA etatSrotallicsO teseRretfa gnitallicsOd eppotSd eppotSd eppotS rehtOd etarenegyllanretxE .deilppaebnackcolc detarenegyllanretxE .deilppaebnackcolc kcolcniamehtnehW eht,gnitallicsospots rotallicsopihc-no -otuagnitallicsostrats dnayllacitam ecruoskcolcsemoceb dnaUPCehtrof .noitcnuflarehpirep --- Table 9.1 Clock Generation Circuit Specifications

Page 72 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M CPU Clock fROC BCLK(1) CM07 PM27 to PM26 CM21 CM21 ca b e fCfROC Detecting Function Activated CM04 X CIN X COUT Sub Clock Oscillation Circuit S QR NMI RESET Software Reset WAIT Instruction (Wait Mode) CM02 PM26 X IN Clock S QR CM10=1 (Stop Mode) CST fAD f32f8 1/2 1/2n 1/m f2n fCANf1 fC32 CM05 X IN X OUT Main Clock Oscillation Circuit CM17 00 01 10 PM2401 CM10 CM20 PM21 PM21 PM27PM26 PM22 CM21 PM21 Wait Mode CM02 Wait Mode CM02 (Note 2) Main Clock Peripheral Function Clock Pheripheral FunctionClock Sub Clock fC CLK OUT Port P5 f8 f32 CM01 and CM00 00 01 10 11 X IN Clock CM21CM05 CPSR=1 DividerReset Output signal to determineinterrupt priority request level 0scillating Activated On-chipOscillator PLL FrequencySynthesizer PeripheralFunction Clock NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. The MCD4 to MCD0 bits in the MCD register select divide-by-m (m=1,2,3,4,6,8,10,12,14,16 ). PM21, PM22, PM24, PM26, PM27: Bits in the PM2 register CST: Bit in the TCSPR register CPSR: Bit in the CPSRF register Main ClockStop Detect CM00, CM01, CM02, CM04, CM07: Bits in the CM0 register CM10, CM17: Bits in the CM1 register CM20, CM21: Bits in the CM2 register Figure 9.1 Clock Generation Circuit InterruptRequest Signal a On-chip OscillatorClock f (ROC) On-Chip Oscillator Charge and Discharge Circuit Circuit to Generate Oscillation Stop Detection Interrupt Request Clock Edge Detect /Charge and Discharge Circuit Control Watchdog Timer Interrupt Request Oscillation Stop Detection Interrupt Request CM21 SwitchSignal b On-Chip Oscillator and Main Clock Stop Detection Reference Frequency Counter Phase Comparator ChargePump Programmable Counter Voltage Controlled Oscillator(VCO) 1/2 1/3 PLC12 PLL Clock c e PLC12 : Bit in the PLC1 register PLL Frequency Synthesizer

Page 73 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.2 CM0 Register Symbol Address After Reset CM0 0006 16 0000 1000 2 System Clock Control Register 0(1) CM00 CM01 CM02 Clock Output Function Select Bit(2) In Wait Mode, Peripheral Function Clock Stop Bit(9) Port XC Switch Bit Main Clock (XIN-XOUT ) Stop Bit(5, 9) CM04 CM05 CM06 CM07 RWFunctionBit NameBit Symbol RW RW RW RW RW RW RW RW 0 : Main clock oscillates 1 : Main clock stops(6) 0 0 : I/O port P53 0 1 : Outputs fC 1 0 : Outputs f8 1 1 : Outputs f32 0 : I/O port function 1 : XCIN-XCOUT oscillation function(4) XCIN-XCOUT Drive Capacity Select Bit(11) Watchdog Timer Function Select Bit CPU Clock Select Bit 0 (8, 9, 10) 0: Clock selected by the CM21 bit divided by MCD register setting 1: Sub clock 0 : Watchdog timer interrupt 1 : Reset(7) NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 and CM00 bits to "002". When the PM15 and PM14 bits in the PM1 register are set to "012" (ALE output to P53), set the CM01 and CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 and CM00 bits) in microprocessor or memory expansion mode, and the CM01 and CM00 bits are set to "00 2", an "L" signal is output from port P53 (port P53 does not function as an I/O port). 3. fc32 does not stop running. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode. 4. When setting the CM04 bit is set to "1", set the PD8_7 and PD8_6 bits in the PD8 register to "002" (port P87 and P86 in input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up). 5. When entering low-power consumption mode or on-chip oscillator low-power consumption mode, the CM05 bit stops running the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop running the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the CM05 bit is set to "1", the clock applied to X OUT becomes "H". The built-in feedback resistor remains ON. XIN is pulled up to XOUT ("H" level) via the feedback resistor. 6. When the CM05 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002" (divide-by-8 mode). In on-chip oscillation mode, the MCD4 to MCD0 bits are not set to "010002" even if the CM05 bit terminates XIN-XOUT . 7. Once the CM06 bit is set to "1", it cannot be set to "0" by program. 8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0". After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1". Do not set the CM07 bit and CM04 or CM05 bit simultaneously. 9. When the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM02, CM05 and CM07 bits do not change even when written. 10. After the CM07 bit is set to "0", set the PM21 bit to "1". 11. When stop mode is entered, the CM03 bit is set to "1". b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 0 : Peripheral clock does not stop in wait mode 1 : Peripheral clock stops in wait mode (3) CM03 0 : Low 1 : High

Page 74 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.3 CM1 Register CM10 (b4 - b1) (b5) (b6) CM17 System Clock Control Register 1(1) Reserved Bit All Clock Stop Control Bit(2, 5) Reserved Bit Reserved Bit CPU Clock Select Bit 1(4,5) Set to "0" Set to "0" Set to "1" 0 : Clock oscillates 1 : All clocks stop (stop mode)(3) 0 : Main clock 1 : PLL clock Symbol Address After Reset CM1 0007 16 0010 0000 2 FunctionBit NameBit Symbol RW RW RW RW RW RW NOTES: 1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the CM10 bit is set to "1", the clock applied to XOUT becomes "H" and the built-in feedback resistor is disabled. XIN, XCIN and XCOUT are placed in high-impedance states. 3. When the CM10 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002" (divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1". 4. The CM17 bit setting is enabled only when the CM21 bit in the CM2 register is set to "0". Use the procedure shown in Figure 9.12 to set the CM17 bit to "1". 5. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM10 and CM17 bits do not change when written. If the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer count source), the CM10 bit setting does not change when written. b7 b6 b5 b4 b3 b2 b1 b0 00 00 01

Page 75 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.4 MCD Register MCD0 MCD1 MCD2 MCD3 MCD4 (b7 - b5) Main Clock Division Register(1) Main Clock Division Select Bit(2, 4) 1 0 0 1 0 : Divide-by-1(no division) mode 0 0 0 1 0 : Divide-by-2 mode 0 0 0 1 1 : Divide-by-3 mode 0 0 1 0 0 : Divide-by-4 mode 0 0 1 1 0 : Divide-by-6 mode 0 1 0 0 0 : Divide-by-8 mode 0 1 0 1 0 : Divide-by-10 mode 0 1 1 0 0 : Divide-by-12 mode 0 1 1 1 0 : Divide-by-14 mode 0 0 0 0 0 : Divide-by-16 mode Symbol Address After Reset MCD 000C 16 XXX0 1000 2 FunctionBit NameBit Symbol RW RW RW RW RW RO RW NOTES: 1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the microcomputer enters stop mode or low-power consumption mode, the MCD4 to MCD0 bits are set to "010002". The MCD4 to MCD0 bits are not set to "010002" even if the CM05 bit in the CM0 register is set to "1" (XIN-XOUT stopped) in on-chip oscillator mode. 3. Bit combinations cannot be set not listed above. 4. Access CAN-associated register addresses after setting the MCD4 to MCD0 bits are set to "10010 2", when the PM24 bit in the PM2 register is set to "0" (clock selected by the CM07 bit). (Note 3) b4 b3 b2 b1 b0 Reserved Bit When read, its content is indeterminate b7 b6 b5 b4 b3 b2 b1 b0

Page 76 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.5 CM2 Register CM20 CM21 CM22 CM23 (b7 - b4) Oscillation Stop Detection Register(1) CPU Clock Select Bit 2(3, 4) Oscillation Stop Detection Enable Bit (2) Main Clock Monitor Flag (6) Oscillation Stop Detection Flag (5) Reserved Bit 0: Main clock oscillates 1: Main clock stops 0: Clock selected by the CM17 bit 1: On-chip oscillator clock 0: Main clock does not stop 1: Detects a main clock stop 0: Disables oscillation stop detect function 1: Enables oscillation stop detect function Set to "0" Symbol Address After Reset CM2 000D 16 00 16 FunctionBit NameBit Symbol RW RW RW RW RO RW NOTES: 1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM20 bit setting does not change when written. 3. When a main clock oscillation stop is detected while the CM20 bit is set to "1", the CM21 bit is set to "1". Although the main clock starts oscillating, the CM21 bit is not set to "0". If the main clock is used as a CPU clock source after the main clock resumes oscillating, set the CM21 bit to "0" by program. 4. When the CM20 bit is set to "1" and the CM22 bit is set to "1", do not set the CM21 bit to "0". 5. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0", not "1", by program. If the CM22 bit is set to "0" by program while the main clock stops, the CM22 bit cannot be set to "1" until the next main clock stop is detected. 6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop detection interrupt is generated. b7 b6 b5 b4 b3 b2 b1 b0 000 0

Page 77 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.6 TCSPR and CPSRF Registers CNT0 CNT1 CNT2 CNT3 (b6 - b4) CST NOTES: 1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "0". 2. Value of the TCSPR register is not reset by software reset or watchdog timer reset. Count Source Prescaler Register Division Rate Select Bit (1) Operation Enable Bit Reserved Bit 0: Divider stops 1: Divider starts If setting value is n, f2n is the main clock, on-chip oscillator clock or PLL clock divided by 2n. When n is set to "0", no division is selected. Symbol Address After Reset (2) TCSPR 035F 16 0XXX 0000 2 FunctionBit NameBit Symbol RW RW RW RW RW RO RW CPSR (b6 - b0) Clock Prescaler Reset Flag Clock Prescaler Reset Flag Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Symbol Address After Reset CPSRF 0341 16 0XXX XXXX 2 FunctionBit NameBit Symbol RW RWRW When the CPSR bit is set to "1", fC divided by 32 is reset. When read, its content is "0". When read, its content is indeterminate b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

Page 78 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M PLC12 (b0) (b1) (b3) (b4) Function PLL Control Register 1(1, 2, 3, 4) Reserved Bit 0 : Divide-by-2 1 : Divide-by-3 Set to "0" PLL Clock Division Switch Bit (b7 - b5) Bit NameBit Symbol Symbol Address After Reset PLC1 0027 16 000X 0000 2 RW RW Reserved Bit Set to "1" RW RW Reserved Bit Reserved Bit Reserved Bit Set to "0" Set to "0" RO RW RW NOTES: 1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the PLC1 register does not change when written. 3. Set the PLC1 register when the PLC07 bit is set to "0" (PLL off). 4. Set the PLC0 and PLC1 registers simultaneously in 16-bit units. When read, its content is indeterminate b7 b6 b5 b4 b3 b2 b1 b0 100000 Figure 9.7 PLC0 and PLC1 Registers PLC00 PLC01 PLC02 (b3) (b4) (b5) (b6) PLC07 Function PLL Control Register 0(1, 2, 5) Programmable Counter Select Bit(3) Reserved Bit Operation Enable Bit(4) 0: PLL is Off 1: PLL is On Set to "1" Reserved Bit Set to "0" Reserved Bit Reserved Bit Set to "1" Bit NameBit Symbol Symbol Address After Reset PLC0 0026 16 0001 X010 2 RW RW RW RW RO RW RW RW RW NOTES: 1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the PLC0 register setting does not change when written. 3. Set the PLC02 to PLC00 bits when the PLC07 bit is set to "0". Once these bits are set, they cannot be changed. 4. Set the CM17 bit in the CM1 register to "0" (main clock as CPU clock source) and the PLC07 bit to "0" before entering wait or stop mode. 5. Set the PLC0 and PLC1 registers simultaneously in 16-bit units. 0 1 1 : Multiply-by-6 1 0 0 : Multiply-by-8 Do not set to values other than the above b2 b1 b0 When read, its content is indeterminate b7 b6 b5 b4 b3 b2 b1 b0 101

Page 79 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.8 PM2 Register RW RW PM21 (b0) PM22 PM26 PM27 b6b7 RW RW 0 : Clock selected by the CM07 bit 1 : Main Clock 0 : f1 1 : Main Clock CPU Clock Select Bit 3 CAN Clock Select Bit PM24 PM25 RW (b3) Processor Mode Register 2(1) After Reset 0016 Address 0013 Symbol PM2 RW System Clock Protect Bit(2, 3) RWWDT Count Source Protect Bit(2, 4) Bit Name FunctionBit Symbol RWReserved Bit Set to "0" 0 : Protects the clock by a PRCR register setting 1 : Disables a clock change 0 : Selects BCLK as count source of the watchdog timer 1 : Selects the on-chip oscillator clock as count source of the watchdog timer Reserved Bit Set to "0" NOTES: 1. Rewrite the PM2 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. Once the PM22 and PM21 bits are set to "1", they can not be set to "0" by program. 3. When the PM21 bit is set to "1", the CPU clock keeps running when the WAIT instruction is executed; nothing is changed even if following bits are set to either "0" or "1".

the CM02 bit in the CM0 register (the peripheral function clock is not stopped in wait mode.)
the CM05 bit in the CM0 register (the main clock is not stopped.)
the CM07 bit in the CM0 register (a CPU clock source is not changed.)
the CM10 bit in the CM1 register (the microcomputer does not enter stop mode.)
the CM17 bit in the CM1 register (a CPU clock source is not changed.)
the CM20 bit in the CM2 register (oscillation stop detect function settings are not changed.)
all bits in the PLC0 and PLC1 registers (PLL frequency synthesizer function settings are not changed.) 4. When the PM22 bit is set to "1", the on-chip oscillator clock becomes a count source of the watchdog timer after the on-chip oscillator starts; write to the CM10 bit is disabled (the microcomputer does not enter stop mode.); the watchdog timer keeps running when the microcomputer is in wait mode and hold state. 0 0 : Peripheral function clock 0 1 : X IN clock 1 0 : On-chip oscillator clock 1 1 : Do not set to this value f 2n Count source Select Bit RW b7 b6 b5 b4 b3 b2 b1 b0

Page 80 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M

9.1.1 Main Clock

Main clock oscillation circuit generates the main clock. The main clock becomes clock source of the CPU clock and peripheral function clock. The main clock oscillation circuit is configured by connecting an oscillator or resonator between the X IN and XOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the oscillation circuit in stop mode to reduce power consumption. An external clock can be applied to the XIN pin in the main clock oscillation circuit. Figure 9.9 shows an example of a main clock circuit connection. Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscil- lator manufacturer. The main clock divided-by-eight becomes a CPU clock source after reset. To reduce power consumption, set the CM05 bit in the CM0 register to "1" (main clock stopped) after switching the CPU clock source to the sub clock or on-chip oscillator clock. In this case, the clock applied to X OUT becomes high ("H"). XIN is pulled up by XOUT via the feedback resistor which remains on. When an external clock is applied to the XIN pin, do not set the CM05 bit to "1". All clocks, including the main clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details. Figure 9.9 Main Clock Circuit Connection External ClockXIN XOUT Open VCC VSS NOTES: 1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting. Use values recommended by each oscillator manufacturer. Place a feedback resistor between X IN and XOUT if the oscillator manufacturer recommends placing the resistor externally. Oscillator Rd (1) C IN C OUT XIN XOUT Microcomputer (Built-in Feedback Resistor) Microcomputer (Built-in Feedback Resistor) VSS

Page 81 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M

9.1.2 Sub Clock

Sub clock oscillation circuit generates the sub clock. The sub clock becomes clock source of the CPU clock and for the timers A and B. The same frequency, fc, as the sub clock can be output from the CLK OUT pin. The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and XCOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the oscillation circuit in stop mode to reduce power consumption. An external clock can be applied to the XCIN pin. Figure 9.10 shows an example of a sub clock circuit connection. Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscillator manufacturer. The sub clock stops after reset. The feedback resistor is separated from the oscillation circuit. When the PD8_6 and PD8_7 bits in the PD8 register are set to "0" (input mode) and the PU25 bit in the PUR2 register is set to "0" (no pull-up), set the CM04 bit in the CM0 register to "1" (X CIN-XCOUT oscillation function). The sub clock oscillation circuit starts oscillating. To apply an external clock to the XCIN pin, set the CM04 bit to "1" when the PD8_7 bit is set to "0" and the PU25 bit to "0". The clock applied to the XCIN pin becomes a clock source of the sub clock. When the CM07 bit in the CM0 register is set to "1" (sub clock) after the sub clock oscillation has stabi- lized, the sub clock becomes a CPU clock source. All clocks, including the sub clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details. Figure 9.10 Sub Clock Circuit Connection External ClockXC IN XC OUT Open VCC VSS NOTES: 1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting. Use values recommended by each oscillator manufacturer. Place a feedback resistor between X CIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally. Oscillator R C d(1) C CIN C COUT XCIN XCOUT Microcomputer (Built-in Feedback Resistor) Microcomputer (Built-in Feedback Resistor) VSS

Page 82 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M

9.1.3 On-Chip Oscillator Clock

On-chip oscillator generates the on-chip oscillator clock. The 1-MHz on-chip oscillator clock becomes a clock source of the CPU clock and peripheral function clock. The on-chip oscillator clock stops after reset. When the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock), the on-chip oscillator starts oscillating. Instead of the main clock, the on-chip oscillator clock becomes clock source of the CPU clock and peripheral function clock. Table 9.2 shows bit settings for on-chip oscillator start condition. Table 9.2 Bit Settings for On-Chip Oscillator Start Condition

9.1.3.1 Oscillation Stop Detect Function

When the main clock is terminated by external source, the on-chip oscillator automatically starts oscil- lating to generate another clock. When the CM 20 bit in the CM2 registser is set to "1" (oscillation stop detect function enabled), an oscilla- tion stop detection interrupt request is generated as soon as the main clock stops. Simultaneously, the on- chip oscillator starts oscillating. Instead of the main clock, the on-chip oscillator clock becomes clock source for the CPU clock and peripheral function clock. Associated bits are set as follows:

The CM21 bit is set to "1" (on-chip oscillator clock becomes a clock source of the CPU clock.)
The CM22 bit is set to "1" (main clock stop is detected.)
The CM23 bit is set to "1" (main clock stops.) (See Figure 9.14)

9.1.3.2 How to Use Oscillation Stop Detect Function

The oscillation stop detection interrupt shares vectors with the watchdog timer interrupt and the low voltage detection interrupt. When these interrupts are used simultaneously, read the CM22 bit with an interrupt routine to determine if an oscillation stop detection interrupt request has been gener- ated.
When the main clock resumes running after an oscillation stop is detected, set the main clock as clock source of the CPU clock and peripheral function clock. Figure 9.11 shows the procedure to switch the on-chip oscillator clock to the main clock.
In low-speed mode, when the main clock is stopped by setting the CM20 bit to "1", the oscillation stop detection interrupt request is generated. Simultaneously, the on-chip oscillator starts oscillat- ing. The sub clock remains the CPU clock source. The on-chip oscillator clock becomes a clock source for the peripheral function clock.
When the peripheral function clock stops running, the oscillation stop detect function is also dis- abled. To enter wait mode while the oscillation stop detect function is in use, set the CM02 bit in the CM0 register to "0" (peripheral clock does not stop in wait mode). The oscillation stop detect function is provided to handle main clock stop caused by external source. Set the CM20 bit to "0" (oscillation stop detect function disabled) when the main clock is terminated by program, i.e., entering stop mode or setting the CM05 bit to "1" (main clock oscillation stop).
When the main clock frequency is 2MHz or less, the oscillation stop detect function is not available. Set the CM20 bit to "0". retsigeR2MCr etsigeR2MP sadesU tiB12MC tiB22MPs tiB62MPdna72MP 10 0 0k colcnoitcnuflarehpireproecruoskcolcUPC ecruos 01 0 0e cruoskcolcgnitareporemitgodhctaW ).edompotsgniretnenehwgninnurspeekkcolcehT( 00 1 0f n2 ecruostnuoc

Page 83 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.11 Switching Procedure from On-chip Oscillator Clock to Main Clock Switch to the main clock Determine several times whether the CM23 bit is set to "0" (main clock oscillates) Set the CM22 bit to "0" (main clock does not stop) Set the MCD4 to MCD0 bits to "010002" (divide-by-8 mode) Set the CM21 bit to "0" (main clock as CPU clock source) MCD4 to MCD0 bits : Bits in the MCD Register CM23 to CM21 bits : Bits in the CM2 Register Yes No End

Page 84 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.12 Procedure to Use PLL Clock as CPU Clock Source Use PLL clock as CPU clock source Set the PLC0 and the PLC1 registers (Set the PLC07 bit to "0") Set the CM17 bit to "1" (PLL clock as CPU clock source) PLC07 bit : Bit in the PLC0 Register CM17 bit : Bit in the CM1 Register Set the PLC07 bit to "1" (PLL on) Wait tsu(PLL)ms End

9.1.4 PLL Clock

The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be used as clock source for the CPU clock and peripheral function clock. The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL frequency synthesizer starts operating. Wait tsu(PLL) ms for the PLL clock to stabilize. The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function clock, set each bit as is shown in Table 9.3. Figure 9.12 shows the procedure to use the PLL clock as the CPU clock source. To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), set the PLC07 bit in the PLC0 register to "0" (PLL off) and then enter wait or stop mode. Table 9.3 Bit Settings to Use PLL Clock as CPU Clock Source X(f NI ) retsigeR0CLPr etsigeR1CLP kcolCLLP tiB20CLPt iB10CLPt iB00CLPt iB12MC zHM010 1 1 0z HM03 1z HM02 zHM81 0 0 0z HM23 1z HM3.12

Page 85 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M

9.2 CPU Clock and BCLK

The CPU operating clock is referred to as the CPU clock. The CPU clock is also a count source for the watchdog timer. After reset, the CPU clock is the main clock divided-by-8 . In memory expansion or micro- processor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Refer to 9.4 Clock Output Function for details. The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the CPU clock. Table 9.4 shows CPU clock source and bit settings. When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock, the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock. The MCD4 to MCD0 bits in the MCD register select the clock division. When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip oscillator clock is the CPU clock), the MCD4 to MCD0 bits are set to "01000 2" (divide-by-8 mode). There- fore, when the main clock starts running, the CPU clock enters medium-speed mode (divide-by-8). Table 9.4 CPU Clock Source and Bit Settings NOTES: 1. Refer to 23.2 CAN Clock for details.

9.3 Peripheral Function Clock

The peripheral function clock becomes an operating clock or count source for peripheral functions exclud- ing the watchdog timer. 9.3.1 f1, f8, f32 and f2n f1, f8 and f32 are the peripheral function clock, selected by the CM21 bit, divided-by-1, -8, or -32. The PM27 and PM26 bits in the PM2 register selects a f2n count source from the peripheral clock, XIN clock, and the on-chip oscillator clock. The CNT3 to CNT0 bits in the TCSPR register selects a f2n division. (n=0 to 15. No division when n=0.) f 1, f8, f32 and f2n stop when the CM02 bit in the CM0 register to "1" (peripheral function stops in wait mode) to enter wait mode or when in low-power consumption mode. f1, f8 and f2n are used as an operating clock of the serial I/O and count source of the timers A and B. f1 is also used as an operating clock for the intelligent I/O. The CLKOUT pin outputs f8 and f32 . Refer to 9.4 Clock Output Function for details. 9.3.2 fAD fAD is an operating clock for the A/D converter and has the same frequency as either the main clock(1) or the on-chip oscillator clock. The CM21 bit determines which clock is selected. If the CM02 bit is set to "1" (peripheral function stop in wait mode) to enter wait mode, fAD stops. fAD also stops in low-power consumption mode. NOTES: 1. The PLL clock, instead of the main clock, when the CM17 bit is set to "1" (PLL clock). ecruoSkcolCUPC retsigeR0MCr etsigeR1MCr etsigeR2MCr etsigeR2MP tiB70MCt iB71MCt iB12MCt iB42MP kcolCniaM 0000 )edoMtceriDkcolCniaM(kcolCniaM )1( 000 1 kcolCbuS1 0 0 0 kcolCrotallicsOpihC-nO0 0 1 0 kcolCLLP0 1 0 0

Page 86 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M (3) 002, 102, 112, Outputs BCLK Outputs "L" (not P53) Outputs fc Outputs f8 0 (3) 0 (3)0 1 Outputs f32 Outputs ALE 0 (3) PM07 Bit CM01 Bit CM00 BitPM14 Bit CLK OUT Pin Function PM15 Bit PM0 Register(1) CM0 Register(2)PM1 Register(1) PM07 Bit CM01 Bit CM00 Bit CLK OUT Pin Function P53 I/O port Outputs fc Outputs f8 Outputs f32 PM0 Register (1) CM0 Register (2) 9.3.3 fC32 fC32 is the sub clock divided by 32. fC32 is used as a count source for the timers A and B. fC32 is available when the sub clock is running. 9.3.4 fCAN fCAN has the same frequency as the main clock. It is a clock for the CAN module only.

9.4 Clock Output Function

The CLKOUT pin outputs fC , f8 or f32. In memory expansion mode or microprocessor mode, a clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Table 9.5 lists CLK OUT pin function in single-chip mode. Table 9.6 lists CLKOUT pin function in memory expansion mode and microprocessor mode. Table 9.5 CLKOUT Pin in Single-Chip Mode - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). Table 9.6 CLKOUT Pin in Memory Expansion Mode and Microprocessor Mode - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM1 and PM0 registers after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 3. When the PM07 bit is set to "0" (selected in the CM01 and CM00 bits) or the PM15 and PM14 bits are set to "012" (P53/BCLK), set the CM01 and CM00 bits to "002" (I/O port P53). 4. M32C/86T cannot be used in memory expansion mode and microprocessor mode.

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9.5 Power Consumption Control

Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operating mode in this section. Figure 9.13 shows a block diagram of status transition in wait mode and stop mode. Figure 9.14 shows a block diagram of status transition in all modes.

9.5.1 Normal Operating Mode

The normal operating mode is further separated into six modes. In normal operating mode, the CPU clock and peripheral function clock are supplied to operate the CPU and peripheral function. The power consumption control is enabled by controlling a CPU clock fre- quency. The higher the CPU clock frequency is, the more processing power increases. The lower the CPU clock frequency is, the more power consumption decreases. When unnecessary oscillation circuit stops, power consumption is further reduced.

9.5.1.1 High-Speed Mode

(1) becomes the CPU clock and a clock source of the peripheral function clock. When the sub clock runs, fC32 can be used as a count source for the timers A and B.

9.5.1.2 Medium-Speed Mode

The main clock(1) divided-by-2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The main clock(1) is a clock source for the peripheral function clock. When the sub clock runs, fC32 can be used as a count source for the timers A and B.

9.5.1.3 Low-Speed Mode

The sub clock becomes the CPU clock . The main clock(1) is a clock source for the peripheral function clock. fC32 can be used as a count source for the timers A and B.

9.5.1.4 Low-Power Consumption Mode

The microcomputer enters low-power consumption mode when the main clock stops in low-speed mode. The sub clock becomes the CPU clock. Only f C32 can be used as a count source for the timers A and B and the peripheral function clock. In low-power consumption mode, the MCD4 to MCD0 bits in the MCD register are set to "01000 2" (divide-by-8 mode). Therefore, when the main clock resumes running, the microcomputer is in midium-speed mode (divide-by-8 mode).

9.5.1.5 On-Chip Oscillator Mode

The on-chip oscillator clock divided-by-1 (no division), -2, -3, 4-, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is a clock source for the peripheral function clock. When the sub clock runs, f C32 can be used as a count source for the timers A and B.

9.5.1.6 On-Chip Oscillator Low-Power Consumption Mode

The microcomputer enters on-chip oscillator low-power consumption mode when the main clock stops in on-chip oscillator mode . The on-chip oscillator clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, - 12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is a clock source for the peripheral function clock. When the sub clock runs, f C32 can be used as a count source for the timers A and B. NOTES: 1. The PLL clock, instead of the main clock, when the CM17 bit is set to "1" (PLL clock).

Page 88 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Switch the CPU clock after the clock to be switched to stabilize. Sub clock oscillation will take longer(2) to stabilize. Wait, by program, until the clock stabilizes directly after turning the microcomputer on or exiting stop mode. To switch the on-chip oscillator clock to the main clock, enter medium-speed mode (divide-by-8) after the main clock is divided by eight in on-chip oscillator mode (the MCD4 to MCD0 bits in the MCD register are set to "01000 2"). Do not enter on-chip oscillator mode or on-chip oscillator low-power consumption mode from low-speed mode or low-power consumption mode and vice versa. NOTES: 2. Contact your oscillator manufacturer for oscillation stabilization time.

9.5.2 Wait Mode

In wait mode, the CPU clock stops running. The CPU and watchdog timer, operated by the CPU clock, also stop. When the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer count source), the watchdog timer continues operating. Because the main clock, sub clock and on-chip oscillator clock continue running, peripheral functions using these clocks also continue operating.

9.5.2.1 Peripheral Function Clock Stop Function

If the CM02 bit in the CM0 register is set to "1" (peripheral function clock stops in wait mode), f 1, f8, f32, f2n (when peripheral clock is selected as a count source), and fAD stop in wait mode. Power consump- tion can be reduced. f2n, when XIN clock or on-chip oscillator clock is selected as a count source, and fC32 do not stop running.

9.5.2.2 Entering Wait Mode

If wait mode is entered after setting the CM02 bit to "1", set the MCD4 to MCD0 bits in the MCD register to be the 10-MHz or less CPU clock flequency after dividing the main clock. Enter wait mode after setting the followings.

Initial Setting Set each interrupt priority level after setting the exit priority level required to exit wait mode, con- trolled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
Before Entering Wait Mode (1) Set the I flag to "0" (2) Set the interrupt priority level of the interrupt being used to exit wait mode (3) Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0" (4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL Interrupt priority level of the interrupt used to exit wait mode > IPL = the exit priority level (5) Set the PRC0 bit in the PRCR register to "1" (6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock) and PLC07 bit in the PLC0 register to "0" (PLL off) (7) Set the I flag to "1" (8) Execute the WAIT instruction
After Exiting Wait Mode Set the exit priority level to "7" as soon as exiting wait mode.

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9.5.2.3 Pin Status in Wait Mode

Table 9.7 lists pin states in wait mode. Table 9.7 Pin States in Wait Mode Pin Memory Expansion Mode (1) Single-Chip Mode Microprocessor Mode(1) Address Bus, Data Bus, CS0 to CS3, Maintains state immediately BHE before entering wait mode RD, WR, WRL, WRH "H" HLDA, BCLK "H" ALE "L" Ports Maintains state immediately before entering wait mode CLK OUT When fC is selected Outputs clock When f8, f32 are selected Outputs the clock when the CM02 bit in the CM0 register is set to "0" (peripheral function clock does not stop in wait mode). Maintains state immediately before entering wait mode when the CM02 bit is set to "1" (peripheral function clock stops in wait mode). NOTES: 1. M32C/86T cannot be used in memory expansion mode and microprocessor mode.

9.5.2.4 Exiting Wait Mode

Wait mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts. When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupt disabled) before executing the WAIT instruction. CM02 bit setting affects the peripheral function interrupts. When the CM02 bit in the CM0 register is set to "0" (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to "1" (peripheral function clock stops in wait mode), peripheral functions using the peripheral function clock stop. Therefore, the peripheral function interrupts cannot be used to exit wait mode. However, the peripheral function interrupts caused by an external clock, f C32 , or f2n whose count source is the XIN clock or on-chip oscillator clock, can be used to exit wait mode. The CPU clock used when exiting wait mode by the peripheral function interrupts or NMI interrupt is the same CPU clock used when the WAIT instruction is executed. Table 9.8 shows interrupts to be used to exit wait mode and usage conditions.

Page 90 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Table 9.8 Interrupts to Exit Wait Mode

9.5.3 Stop Mode

In stop mode, all oscillators and resonators stop. The CPU clock and peripheral function clock, as well as the CPU and peripheral functions operated by these clocks, also stop. The least power required to operate the microcomputer is in stop mode. The internal RAM holds its data when the voltage applied to the V CC pin is more than or equal to VRAM . If the voltage applied to the VCC pin is 2.7V or less, the voltage must be Vcc ≥ VRAM . The following interrupts can be used to exit stop mode:

NMI interrupt
Key Input Interrupt
INT interrupt
Timer A and B interrupt (Available when the timer counts external pulse, having its 100Hz or less frequency, in event counter mode)
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9.5.3.1 Entering Stop Mode

Stop mode is entered when setting the CM10 bit in the CM10 register to "1" (all clocks stops). The MCD4 to MCD0 bits in the MCD register become set to "01000 2" (divide-by-8 mode). Enter stop mode after setting the followings.

Initial Setting Set each interrupt priority level after setting the exit priority level required to exit stop mode, con- trolled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
Before Entering stop mode (1) Set the I flag to "0" (2) Set the interrupt priority level of the interrupt being used to exit stop mode (3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0" (4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL Interrupt priority level of the interrupt used to exit stop mode > IPL = the exit priority level (5) Set the PRC0 bit in the PRCR register to "1" (write enable) (6) Select the main clock as the CPU clock
When the CPU clock source is the sub clock, (a) set the CM05 bit in the CM0 register to "0" (main clock oscillates) (b) set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by MCD register setting)
When the CPU clock source is the PLL clock, (a) set the CM17 bit in the CM1 register to "0" (main clock) (b) set the PLC07 bit in the PLC0 register to "0" (PLL off)
When main clock direct mode is used, (a) set the PRC1 bit in the PRCR register to "1" (write enable) (b) set the PM24 bit in the PM2 register to "0" (clock selected by the CM07 bit)
When the CPU clock source is the on-chip oscillator clock, (a) set MCD4 to MCD0 bits to "01000 2" (divide-by-8 mode) (b) set the CM05 bit to "0" (main clock oscillates) (c) set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit) (7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscilla- tion stop detect fucntion disabled) (8) Set the I flag to "1" (9) Set the CM10 bit to "1" (all clocks stops)
After Exiting Stop Mode Set the exit priority level to "7" as soon as exiting stop mode.

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9.5.3.2 Exiting Stop Mode

Stop mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts (key input interrupt and INT interrupt). When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to "000 2" (interrupt disabled) before setting the CM10 bit to "1" (all clocks stops).

9.5.3.3 Pin Status in Stop Mode

Table 9.9 lists pin status in stop mode. Table 9.9 Pin Status in Stop Mode Pin Memory Expansion Mode (1) Single-Chip Mode Microprocessor Mode(1) Address Bus, Data Bus, CS0 to CS3, BHEMaintains state immediately before entering stop mode RD, WR, WRL, WRH "H" HLDA, BCLK "H" ALE "H" Ports Maintains state immediately before entering stop mode CLK OUT When fC selected "H" When f8, f32 selected Maintains state immediately before entering stop mode XIN Placed in a high-impedance state XOUT "H" XCIN, XCOUT Placed in a high-impedance state NOTES: 1. M32C/86T cannot be used in memory expansion mode and microprocessor mode.

Page 93 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Wait Mode Normal Operating Mode CPU operation is stopped CM10=1 CM10=1 All oscillation is stopped Interrupt Wait Mode Wait Mode Stop Mode Stop Mode Wait Mode WAIT Instruction WAIT Instruction WAIT Instruction WAIT Instruction Interrupt Interrupt Interrupt Interrupt Interrupt Reset Middle-Speed Mode (divide-by-8 mode) High-Speed / Middle-Speed Mode Low-Speed/ Low-Power Consumption Mode (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) (Note 3) On-Chip Oscillator / On- Chip Oscillator Low-Power Consumption Mode NOTES: 1. See Figure 9.14. 2. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source) and the PLC07 bit is set to "0" (PLL off). Then enter wait mode or stop mode. 3. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source) and the PLC07 bit is set to "0" (PLL off). Then enter low-speed or low-power consumption mode. (Note 2) Figure 9.13 Status Transition in Wait Mode and Stop Mode

Page 94 974fo5002,80.peS00.1.veR 0010-4020B90JER 9. Clock Generation Circuit)T68/C23M,68/C23M(puorG68/C23M Figure 9.14 Status Transition Main Clock OscillationSub Clock StopOn-Chip Oscillator Clock StopPLL Clock StopCPU Clock: f(X IN )/8 CM07=0 MCD=08 CM21=0 CM05=0 CM04=0 PLC07=0CM17=0 MCD=XX (Note 1) Main Clock OscillationSub Clock OscillationOn-Chip Oscillator Clock StopPLL Clock Stop CPU clock :f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=1 PLC07=0CM17=0CPU clock: f(X IN )/n CM07=0 MCD=XX CM21=0 CM05=0 CM04=1 PLC07=0CM17=0 CM04=1 (Note 1) Main Clock Oscillation Sub Clock Stop On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: On-Chip Oscillator Clock / n CM07=0 MCD=XX CM21=1 CM05=0 CM04=0 PLC07=0 CM17=0 CM21=1 (Note 1) CM21=0 CM05=1 CM05=0 High-Speed Mode CM04=0 CM04=1 On-Chip Oscillator Mo de CM21=1 (Note 1) CM21=0 CM04=0 CM04=1 CM04=0 CM04=1 Main clock stopis detected whenCM20=1 (Note 5) Low-Speed Mode CM07=0 (Note 1)CM07=1 (Note 2) PLC07=0PLC07=1 Low-Speed Mode CM21=1(Note 1) CM21=0 Low-Power Consumption Mode Low-Power Consumption Mode CM05=1 CM05=0 CM05=1 CM05=0 CM07=0 CM07=1(Note 2) (Note 3) After reset,Medium-Speed Mode (Divide-by-8) (Note 4) Main clock stopis detected whenCM20=1 Medium-Speed Mode Main Clock OscillationSub Clock StopOn-Chip Oscillator Clock StopPLL Clock StopCPU clock: f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=0 PLC07=0CM17=0CPU clock: f(X IN )/n CM07=0 MCD=XX CM21=0 CM05=0 CM04=0 PLC07=0CM17=0High-Speed ModeMedium-Speed Mode Main Clock Stop Sub Clock Stop On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: On-Chip Oscil lator Clock / n CM07=0 MCD=XX CM21=1 CM05=1 CM04=0 PLC07=0 CM17=0On-Chip Oscillator Lo w-Power Consumption Mode CM05=1 CM05=0 Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: On-Chip Oscil lator Clock / n CM07=0 MCD=XX CM21=1 CM05=0 CM04=1 PLC07=0 CM17=0On-Chip Oscillator Mo de Main Clock Stop Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: On-Chip Oscillator Clock / n CM07=0 MCD=XX CM21=1 CM05=1 CM04=1 PLC07=0 CM17=0 Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Stop PLL Clock Stop CPU clock: f(X CIN CM07=1 CM21=0 CM05=0 CM04=1 PLC07=0 CM17=0 Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: f(X CIN CM07=1 CM21=1 CM05=0 CM04=1 PLC07=0 CM17=0 Main Clock Stop Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: f(X CIN CM07=1 MCD=08 CM21=1 CM05=1 CM04=1 PLC07=0 CM17=0 Main Clock Stop Sub Clock Oscillation On-Chip Oscillator Clock Stop PLL Clock Stop CPU Clock: f(X CIN CM07=1 MCD=08 CM21=0 CM05=1 CM04=1 PLC07=0 CM17=0 Main Clock OscillationSub Clock OscillationOn-Chip Oscillator Clock stopPLL Clock Oscillation CPU clock: f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=1 PLC07=1CM17=0CPU clock: f(X IN )/n CM07=0 MCD=XX CM21=0 CM05=0 CM04=1 PLC07=1CM17=0High-Speed ModeMedium-Speed Mode Main Clock OscillationSub Clock OscillationOn-Chip Oscillator Clock StopPLL Clock Oscillation CPU clock: f(X PLL CM07=0 MCD=12 CM21=0 CM05=0 CM04=1 PLC07=1CM17=1CPU clock: f(X PLL )/n CM07=0 MCD=XX CM21=0 CM05=0 CM04=1 PLC07=1CM17=1High-Speed ModeMedium-Speed Mode CM17=0 CM17=1 PLC07=0PLC07=1 Main Clock OscillationSub Clock StopOn-Chip Oscillator Clock StopPLL Clock Oscillation CPU clock: f(X PLL CM07=0 MCD=12 CM21=0 CM05=0 CM04=0 PLC07=1CM17=1CPU clock: f(X PLL )/n CM07=0 MCD=XX CM21=0 CM05=0 CM04=0 PLC07=1CM17=1High-Speed ModeMedium-Speed Mode Main Clock OscillationSub Clock StopOn-Chip Oscillator Clock StopPLL Clock Oscillation CPU clock: f(X IN CM07=0 MCD=12 CM21=0 CM05=0 CM04=0 PLC07=1CM17=0CPU clock: f(X IN )/n CM07=0 MCD=XX CM21=0 CM05=0 CM04=0 PLC07=1CM17=0High-Speed ModeMedium-Speed Mode CM17=0CM17=1 On-Chip Oscillator Lo w-Power Consumption Mode : An arrow shows mode can be changed. Do not chan ge mode to another mode when no arrow is shown. MCD=XX : Set the MCD to MCD0 bits in th e MCD register to the desired division. NOTES: 1. Switch the clock after main clock oscillation is full y stabilized. 2. Switch the clock after sub clock oscillation is full y stabilized. 3. The MCD4 to MCD0 bits in th e MCD register are set to "01000 2" (devide-by-8 mode) automatically. 4. The CM05 bit is not s et to "1" when the microcomputer detects a main clock oscillation stop throu gh the oscillation stop detection circuit . 5. The on-chip oscillator clock runs when setting the PM22 bit to "1" ( on-chip oscillator clock as watchdog timer count source) and setting the PM27 and PM26 bits to "10 2" ( on-chip oscillator clock ), even if the CM21 bit is set to "0". (Note 3)

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9.6 System Clock Protect Function

The system clock protect function prohibits the CPU clock from changing clock sources when the main clock is selected as the CPU clock source. This prevents the CPU clock from stopping the program crash. When the PM21 bit in the PM2 register is set to "1" (clock change disable), the following bits cannot be written to:

The CM02 bit, CM05 bit and CM07 bit in the CM0 register
The CM10 bit and CM17 bit in the CM1 register
The CM20 bit in the CM2 register
All bits in the PLC0 and PLC1 registers The CPU clock continues running when the WAIT instruction is executed. To use the system clock protect function, set the CM05 bit in the CM0 register to "0" (main clock oscillation) and CM07 bit to "0" (main clock as BCLK clock source) and follow the procedure below. (1) Set the PRC1 bit in the PRCR register to "1" (write enable). (2) Set the PM21 bit in the PM2 register to "1" (protects the clock). (3) Set the PRC1 bit in the PRCR register to "0" (write disable). When the PM21 bit is set to "1", do not execute the WAIT instruction.

Page 97 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Undefined Instruction (UND Instruction) Overflow (INTO Instruction) BRK Instruction BRK2 Instruction (2) INT Instruction Software (Non-Maskable Interrupt) Hardware Interrupt NMI Watchdog Timer Oscillation Stop Detection Low voltage Detection (3) Single-Step(2) Address Match DMACII Special (Non-Maskable Interrupt) Peripheral Function (1) (Maskable Interrupt) NOTES: 1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt. 2. Do not use this interrupt. For development support tools only. 3. Low voltage detection interrupt cannot be used in M32C/86T. 11. Interrupts

11.1 Types of Interrupts

Figure 11.1 shows types of interrupts. Figure 11.1 Interrupts

Maskable Interrupt The I flag enables or disables an interrupt. The interrupt priority order based on interrupt priority level can be changed.
Non-Maskable Interrupt The I flag does not enable nor disable an interrupt . The interrupt priority order based on interrupt priority level cannot be changed.

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11.2 Software Interrupts

Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable inter- rupts.

11.2.1 Undefined Instruction Interrupt

The undefined instruction interrupt occurs when the UND instruction is executed.

11.2.2 Overflow Interrupt

The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic operation) and the INTO instruction is executed. Instructions to set the O flag are : ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX

11.2.3 BRK Interrupt

The BRK interrupt occurs when the BRK instruction is executed.

11.2.4 BRK2 Interrupt

The BRK2 interrupt occurs when the BRK2 instruction is executed. Do not use this interrupt. For development support tools only.

11.2.5 INT Instruction Interrupt

The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 8 to 49, 52 to 54 and 57 are assigned to the vector table used for the peripheral function interrupt. Therefore, the microcomputer executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt occurs. When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the relocatable vector of specified software interrupt numbers. Where the stack is saved varies depending on a software interrupt number. ISP is selected as the stack for software interrupt numbers 0 to 31 (setting the U flag to "0"). SP, which is set before the INT instruction is executed, is selected as the stack for software interrupt numbers 32 to 63 (the U flag is not changed). With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select) when an interrupt request is acknowledged. With software interrupt numbers 32 to 49, 52 to 54 and 57, SP to be used varies depending on whether the interrupt is generated by the peripheral function interrupt request or by the INT instruction.

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11.3 Hardware Interrupts

Special interrupts and peripheral function interrupts are available as hardware interrupts.

11.3.1 Special Interrupts

Special interrupts are non-maskable interrupts.

11.3.1.1 NMI Interrupt

The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal to a low-level ("L") signal. Refer to 11.8 NMI Interrupt for details.

11.3.1.2 Watchdog Timer Interrupt

The watchdog timer interrupt occurs when a count source of the watchdog timer underflows. Refer to 12. Watchdog Timer for details.

11.3.1.3 Oscillation Stop Detection Interrupt

The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscilla- tion stop. Refer to 9. Clock Generation Circuit for details.

11.3.1.4 Low Voltage Detection Interrupt

The low voltage detection interrupt occurs when the voltage applied to V CC is above or below Vdet4. Refer to 6. Voltage Detection Circuit for details. NOTES: 1. Low voltage detection interrupt cannot be used in M32C/86T.

11.3.1.5 Single-Step Interrupt

Do not use the single-step interrupt. For development support tool only.

11.3.1.6 Address Match Interrupt

The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 7) when the AIERi bit in the AIER register is set to "1" (address match interrupt enabled). Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur when a table data or addresses of the instruction other than the starting address, if the instruction has multiple addresses, is set. Refer to 11.10 Address Match Interrupt for details.

11.3.2 Peripheral Function Interrupt

The peripheral function interrupt occurs when a request from the peripheral functions in the microcom- puter is acknowledged. The peripheral function interrupts and software interrupt numbers 8 to 49, 52 to 54 and 57 for the INT instruction use the same interrupt vector table. The peripheral function inter- rupt is a maskable interrupt. See Table 11.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details.

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11.4 High-Speed Interrupt

The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in three cycles. When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "111 2" (level 7) to use the high-speed interrupt. Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority level 7 available for interrupts). Set the starting address of the high-speed interrupt routine in the VCT register. When the high-speed interrupt is acknowledged, the FLG register is saved into the SVF register and PC is saved into the SVP register. The program is executed from an address indicated by the VCT register. Execute the FREIT instruction to return from the high-speed interrupt routine. The values saved into the SVF and SVP registers are restored to the FLG register and PC by executing the FREIT instruction. The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used.

11.5 Interrupts and Interrupt Vectors

There are four bytes in one vector. Set the starting address of interrupt routine in each vector table. When an interrupt request is acknowledged, the interrupt routine is executed from the address set in the interrupt vectors. Figure 11.2 shows the interrupt vector. Figure 11.2 Interrupt Vector /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Middle-order bits of an address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low-order bits of an address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines High-order bits of an address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 16 Vector Address + 0 Vector Address + 1 Vector Address + 2 Vector Address + 3 LSBMSB

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11.5.1 Fixed Vector Tables

The fixed vector tables are allocated addresses FFFFDC16 to FFFFFF16. Table 11.1 lists the fixed vector tables. Refer to 25.2 Functions to Prevent Flash Memory from Rewriting for fixed vectors of flash memory. Table 11.1 Fixed Vector Table NOTES: 1. Low voltage detection interrupt cannot be used in M32C/86T.

11.5.2 Relocatable Vector Tables

The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 11.2 lists the relocatable vector tables. Set an even address as the starting address of the vector table set in the INTB register to increase interrupt sequence execution rate. tpurretnI ybdetareneG sesserddArotceV )H(sserddAot)L(sserddA skrameRe cnerefeR denifednU noitcurtsnI CDFFFF 61 FDFFFFot 61 seireS08/C23M launaMerawtfoS wolfrevO0 EFFFF 61 3EFFFFot 61 noitcurtsnIKRB4 EFFFF 61 7EFFFFot 61 7EFFFFsserddafotnetnocehtfI 61 si FF 61 ehtmorfdetucexesimargorpa, tpurretnierawtfosotniderotssserdda elbatrotcevelbatacolerehtni0rebmun hctaMsserddA8 EFFFF 61 BEFFFFot 61 -C EFFFF 61 FEFFFFot 61 ecapsdevreseR remiTgodhctaW0 FFFFF 61 3FFFFFot 61 ehtrofdesuerasesserddaesehT noitallicso,tpurretniremitgodhctaw woldna,tpurretninoitcetedpots tpurretninoitcetedegatlov )1( ,teseR ,tiucriCnoitareneGkcolC remiTgodhctaW -4 FFFFF 61 7FFFFFot 61 ecapsdevreseR IMN8 FFFFF 61 BFFFFFot 61 teseRC FFFFF 61 FFFFFFot 61 teseR

Page 102 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Table 11.2 Relocatable Vector Tables Interrupt Generated by Vector Table Address Software Reference Address(L) to Address(H)(1) Interrupt Number BRK Instruction(2) +0 to +3 (000016 to 000316) 0 M32C/80 Series Reserved Space +4 to +31 (0004 16 to 001F16) 1 to 7 Software Manual DMA0 +32 to +35 (0020 16 to 002316) 8 DMAC DMA1 +36 to +39 (0024 16 to 002716)9 DMA2 +40 to +43 (0028 16 to 002B16)1 0 DMA3 +44 to +47 (002C 16 to 002F16)1 1 Timer A0 +48 to +51 (0030 16 to 003316) 12 Timer A Timer A1 +52 to +55 (0034 16 to 003716)1 3 Timer A2 +56 to +59 (0038 16 to 003B16)1 4 Timer A3 +60 to +63 (003C 16 to 003F16)1 5 Timer A4 +64 to +67 (0040 16 to 004316)1 6 UART0 Transmission, NACK(3) +68 to +71 (004416 to 004716) 17 Serial I/O UART0 Reception, ACK(3) +72 to +75 (004816 to 004B16)1 8 UART1 Transmission, NACK(3) +76 to +79 (004C16 to 004F16)1 9 UART1 Reception, ACK(3) +80 to +83 (005016 to 005316)2 0 Timer B0 +84 to +87 (0054 16 to 005716) 21 Timer B Timer B1 +88 to +91 (0058 16 to 005B16)2 2 Timer B2 +92 to +95 (005C 16 to 005F16)2 3 Timer B3 +96 to +99 (0060 16 to 006316)2 4 Timer B4 +100 to +103 (0064 16 to 006716)2 5 INT5 +104 to +107 (0068 16 to 006B16) 26 Interrupt INT4 +108 to +111 (006C 16 to 006F16)2 7 INT3 +112 to +115 (0070 16 to 007316)2 8 INT2 +116 to +119 (0074 16 to 007716)2 9 INT1 +120 to +123 (0078 16 to 007B16)3 0 INT0 +124 to +127 (007C 16 to 007F16)3 1 Timer B5 +128 to +131 (0080 16 to 008316) 32 Timer B UART2 Transmission, NACK(3) +132 to +135 (008416 to 008716) 33 Serial I/O UART2 Reception, ACK(3) +136 to +139 (008816 to 008B16)3 4 UART3 Transmission, NACK(3) +140 to +143 (008C16 to 008F16)3 5 UART3 Reception, ACK(3) +144 to +147 (009016 to 009316)3 6 UART4 Transmission, NACK(3) +148 to +151 (009416 to 009716)3 7 UART4 Reception, ACK(3) +152 to +155 (009816 to 009B16)3 8

Page 103 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Table 11.2 Relocatable Vector Tables (Continued) Interrupt Generated by Vector Table Address Software Reference Address(L) to Address(H)(1) Interrupt Number Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39 Serial I/O Stop Condition Detect (UART2)(3), Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316)4 0 Stop Condition Detect (UART3/UART0)(4) Bus Conflict Detect, Start Condition Detect, +164 to +167 (00A416 to 00A716)4 1 Stop Condition Detect (UART4/UART1)(4) A/D0 +168 to +171 (00A8 16 to 00AB16) 42 A/D Converter Key Input +172 to +175 (00AC 16 to 00AF16) 43 Interrupts Intelligent I/O Interrupt 0, CAN 3 +176 to +179 (00B016 to 00B316) 44 Intelligent I/O Intelligent I/O Interrupt 1, CAN 4 +180 to +183 (00B416 to 00B716) 45 CAN Intelligent I/O Interrupt 2 +184 to +187 (00B8 16 to 00BB16)4 6 Intelligent I/O Interrupt 3 +188 to +191 (00BC 16 to 00BF16)4 7 Intelligent I/O Interrupt 4 +192 to +195 (00C0 16 to 00C316)4 8 CAN 5 +196 to +199 (00C4 16 to 00C716) 49 CAN Reserved Space +200 to +207 (00C8 16 to 00CF16) 50, 51 Intelligent I/O Interrupt 8 +208 to +211 (00D0 16 to 00D316) 52 Intelligent I/O Intelligent I/O Interrupt 9, CAN 0 +212 to +215 (00D416 to 00D716) 53 CAN Intelligent I/O Interrupt 10, CAN 1 +216 to +219 (00D816 to 00DB16)5 4 Reserved Space +220 to +227 (00DC 16 to 00E316) 55, 56 CAN 2 +228 to +231 (00E4 16 to 00E716) 57 CAN Reserved Space +232 to +255 (00E8 16 to 00FF16) 58 to 63 INT Instruction(2) +0 to +3 (000016 to 000316) to 0 to 63 Interrupts +252 to +255 (00FC16 to 00FF16) NOTES: 1. These addresses are relative to those in the INTB register. 2. The I flag does not disable interrupts. 3. In I2C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated. 4. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in UART3. The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in UART4.

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11.6 Interrupt Request Acknowledgement

Software interrupts and special interrupts occur when conditions to generate an interrupt are met. The peripheral function interrupts are acknowledged when all conditions below are met.

I flag = "1"
IR bit = "1"
ILVL2 to ILVL0 bits > IPL The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.

11.6.1 I Flag and IPL

The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically set to "0" after reset. IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7. If a requested interrupt has higher priority level than indicated by IPL, the interrupt is acknowledged. Table 11.3 lists interrupt priority levels associated with IPL. Table 11.3 Interrupt Priority Levels IPL2 IPL1 IPL0 Interrupt Priority Levels 0 0 0 Level 1 and above 0 0 1 Level 2 and above 0 1 0 Level 3 and above 0 1 1 Level 4 and above 1 0 0 Level 5 and above 1 0 1 Level 6 and above 1 1 0 Level 7 and above 1 1 1 All maskable interrupts are disabled

11.6.2 Interrupt Control Register and RLVL Register

The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 11.3 and 11.4 show the interrupt control register. Figure 11.5 shows the RLVL register.

Page 105 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Interrupt Control Register After Reset XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 XXXX X000 2 Address 006C 16, 008C16, 006E16, 008E16, 007016 009416, 007616, 009616, 007816, 009816, 006916 009016, 009216, 008916, 008B16, 008D16 007216, 007416, 006B16, 006D16, 006F16 007116, 009116, 008F16, 007116(1), 009116(2) 006816, 008816, 006A16, 008A16 007316 009316 007516, 009516, 007716, 009716, 007916 007D 16, 009D16, 007F16 009D 16, 007F16, 008116(3) 007516, 009516, 009916(3) Symbol TA0IC to TA4IC TB0IC to TB5IC S0TIC to S4TIC S0RIC to S4RIC BCN0IC to BCN4IC DM0IC to DM3IC AD0IC KUPIC IIO0IC to IIO4IC IIO8IC to IIO10IC CAN0IC to CAN2IC CAN3IC to CAN5IC RW RW RW RW RW ILVL0 ILVL1 ILVL2 Interrupt Priority Level Select Bit IR (b7 - b4) NOTES: 1. The BCN0IC register shares an address with the BCN3IC register. 2. The BCN1IC register shares an address with the BCN4IC register. 3. The IIO9IC register shares an address with the CAN0IC register. The IIO10IC register shares an address with the CAN1IC register. The IIO0IC register shares an address with the CAN3IC register. The IIO1IC register shares an address with the CAN4IC register. 4. The IR bit can be set to "0" only (do not set to "1"). Interrupt Request Bit0 : No interrupt requested 1 : Interrupt requested (4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 Figure 11.3 Interrupt Control Register (1)

Page 106 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Figure 11.4 Interrupt Control Register (2)

11.6.2.1 ILVL2 to ILVL0 Bits

The ILVL2 to ILVL0 bits determines an interrupt priority level. The higher the interrupt priority level is, the higher interrupt priority is. When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits are set to "000 2" (level 0), its interrupt is ignored.

11.6.2.2 IR Bit

The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and an interrupt routine in the corresponding interrupt vector is executed. The IR bit can be set to "0" by program. Do not set to "1". Interrupt Control Register After Reset XX00 X000 XX00 X0002 Address 009E 16, 007E16, 009C16 007C 16, 009A16, 007A16 Symbol INT0IC to INT2IC INT3IC to INT5IC (1) RW RW RW RW RW RW RW ILVL0 ILVL1 ILVL2 Interrupt Priority Level Select Bit IR POL LVS (b7 - b6) Interrupt Request Bit Polarity Switch Bit Level Sensitive/Edge Sensitive Switch Bit 0 : Requests no interrupt 1 : Requests an interrupt (2) 0 : Selects falling edge or "L"(3) 1 : Selects rising edge or "H" 0 : Edge sensitive 1 : Level sensitive(4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol NOTES: 1. When a 16-bit data bus is used in microprocessor or memory expansion mode, each INT3 to INT5 pin is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers to "000 2". 2. The IR bit can be set to "0" only (do not set to "1"). 3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges). 4. When setting the LVS bit to "1" , set a corresponding bit in the IFSR register to "0" (one edge). b7 b6 b5 b4 b3 b2 b1 b0

Page 107 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Exit Priority Register After Reset XXXX 0000 2 Address 009F Symbol RLVL RW RW RW RW RW RW RLVL0 RLVL1 RLVL2 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit (1) FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt DMAII (b4) (b7 - b6) DMA II Select Bit (4) 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMA II transfer (3) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it to "0" before setting the interrupt control register. Figure 11.5 RLVL Register

11.6.2.3 RLVL2 to RLVL0 Bits

When using an interrupt to exit stop or wait mode, refer to 9.5.2 Wait Mode and 9.5.3 Stop Mode for details.

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11.6.3 Interrupt Sequence

The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA instruction, if an interrupt request is generated while executing the instruction, the microcomputer sus- pends the instruction to start the interrupt sequence. The interrupt sequence is performed as follows: (1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address 000000 16 (address 00000216 for the high-speed interrupt). Then, the IR bit applicable to the interrupt information is set to "0" (interrupt requested). (2) The FLG register, prior to an interrupt sequence, is saved to a temporary register(1) within the CPU. (3) Each bit in the FLG register is set as follows:

The I flag is set to "0" (interrupt disabled)
The D flag is set to "0" (single-step disabled)
The U flag is set to "0" (ISP selected) (4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed interrupt. (5) PC is saved to the stack; or to the SVP register for the high-speed interrupt. (6) The interrupt priority level of the acknowledged interrupt is set in IPL . (7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC. After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt routine. NOTES: 1. Temporary register cannot be modified by users.

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11.6.4 Interrupt Response Time

Figure 11.6 shows an interrupt response time. Interrupt response time is the period between an interrupt generation and the execution of the first instruction in an interrupt routine. Interrupt response time in- cludes the period between an interrupt request generation and the completed execution of an instruction ((a) on Figure 11.6) and the period required to perform an interrupt sequence ((b) on Figure 11.6). Figure 11.6 Interrupt Response Time Time (a) varies depending on an instruction being executed. The DIV, DIVX and DIVU instructions require the longest time (a); 42 cycles when an immediate value or register is set as the divisor. When the divisor is a value in the memory, the following value is added.

Normal addressing : 2 + X
Index addressing : 3 + X
Indirect addressing : 5 + X + 2Y
Indirect index addressing : 6 + X + 2Y X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be doubled. Table 11.4 lists time (b), shown Figure 11.6. (a) Period between an interrupt request generation and the completed execution of an instruction. (b) Period required to perform an interrupt sequence. (a) (b) Time Instruction Interrupt response time Instruction in interrupt routineInterrupt sequence Interrupt request is acknowledgedInterrupt request is generated

Page 110 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Table 11.4 Interrupt Sequence Execution Time 8-Bit Bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles 16 cycles 19 cycles 19 cycles 21 cycles 16-Bit Bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 14 cycles 17 cycles 19 cycles 19 cycles Interrupt Vector Address Even address Odd address (1) Even address Odd address (1) Even address(2) Even address(2) Even address Odd address (1) Even address(2) Vector table is internal register Interrupt Peripheral Function INT Instruction NMI Watchdog Timer Undefined Instruction Address Match Overflow BRK Instruction (relocatable vector table) BRK Instruction (fixed vector table) High-Speed Interrupt 5 cycles NOTES: 1. Allocate interrupt vectors in even addresses. 2. Vectors are fixed to even addresses.

11.6.5 IPL Change when Interrupt Request is Acknowledged

When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowl- edged interrupt. Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has no interrupt priority level is acknowledged, the value shown in Table 11.5 is set in IPL as the interrupt priority level. Table 11.5 Interrupts without Interrupt Priority Levels and IPL Interrupt Source Level Set to IPL Watchdog Timer, NMI, Oscillation Stop Detection, Low Voltage Detection 7 Reset 0 Software, Address Match Not changed NOTES: 1. Low voltage detection interrupt cannot be used in M32C/86T.

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11.6.6 Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack. After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32 bits, are saved to the stack. Figure 11.7 shows stack states before and after an interrupt request is acknowledged. Other important registers are saved by program at the beginning of an interrupt routine. The PUSHM instruction can save several registers (1) in the register bank used. Refer to 11.4 High-Speed Interrupt for the high-speed interrupt. NOTES: 1. Can be selected from the R0, R1, R2, R3, A0, A1, SB and FB registers. [SP] SP value before an interrupt is generated Stack state before an interrupt request is acknowledged Address Stack state after an interrupt request is acknowledged m-6 m-5 m –4 m –3 m –2 m –1 m m+1 LSBMSBLSBMSBAddress The Stack The Stack FLG L PC H FLG H Content of previous stack Content of previous stack Content of previous stack Content of previous stack PC L PC M [SP] New SP value m-6 m-5 m –4 m –3 m –2 m –1 m m+1 0016 Figure 11.7 Stack States

11.6.7 Restoration from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC before the interrupt sequence is performed, which have been saved to the stack, are automatically restored. The pro- gram, executed before an interrupt request was acknowledged, starts running again. Refer to 11.4 High- Speed Interrupt for the high-speed interrupt. Restore registers saved by program in an interrupt routine by the POPM instruction or others before the REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt sequence by the REIT or FREIT instruction.

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11.6.8 Interrupt Priority

If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an interrupt request is generated or not), the interrupt with the highest priority is acknowledged. Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral function interrupt). Priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are set by hardware. Figure 11.8 shows priority levels of hardware interrupts. The interrupt priority does not affect software interrupts. Executing instruction causes the microcomputer to execute an interrupt routine. Oscillation Stop Detection Reset > NMI > Watchdog > Peripheral Function > Address Match Low voltage Detection(1) NOTES: 1. Low voltage detection interrupt cannot be used in M32C/86T. Figure 11.8 Interrupt Priority

11.6.9 Interrupt Priority Level Select Circuit

The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are sampled at the same sampling point. Figure 11.9 shows the interrupt priority level select circuit.

Page 113 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Timer B2 Timer B0 Timer A0 Timer A1 Timer B1 UART1 Reception/ACK UART0 Reception/ACK A/D0 UART1 Transmission/NACK UART0 Transmission/NACK Key Input Interrupt IPL I Flag Watchdog Timer, Oscillation Stop Detection, Low Voltage Detection DMAC II NMI Interrupt request acknowledged (to CPU) Level 0 (Initial Value) Each Interrupt Priority Level Low Peripheral Function Interrupt Priority (if priority levels are the same) UART2 Reception/ACK Address Match Timer B4 Timer B3 DMA0 DMA1 DMA2 DMA3 Timer A2 Timer A3 Timer A4 UART2 Transmission/NACK UART3 Reception/ACK UART3 Transmission/NACK UART4 Reception/ACK UART4 Transmission/NACK Bus Conflict/Start, Stop Condition (UART0, UART3) Bus Conflict/Start, Stop Condition (UART1, UART4) RLVL2 to RLVL0 Bits Interrupt request priority detection results output (to the clock generation circuit) Bus Conflict/Start, Stop Condition(UART2) Intelligent I/O Interrupt 2 Intelligent I/O Interrupt 3 Intelligent I/O Interrupt 4 Intelligent I/O Interrupt 8 Intelligent I/O Interrupt 9 /CAN Interrupt 0 Intelligent I/O Interrupt 10 /CAN Interrupt 1 CAN Interrupt 2 INT3 INT5 INT4 INT1 INT2 INT0 Timer B5 Each Interrupt Priority Level Intelligent I/O Interrupt 0 /CAN Interrupt 3 Intelligent I/O Interrupt 1 /CAN Interrupt 4 CAN interrupt 5 NOTES: 1. Low voltage detection interrupt cannot be used in M32C/86T. (1) High Figure 11.9 Interrupt Priority Level Select Circuit

Page 114 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M External Interrupt Request Source Select Register Symbol Address After Reset IFSR 031F 16 0016 RW INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit (1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity select bit(1) INT5 Interrupt Polarity Select Bit (1) 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges Bit Name Bit Symbol Function NOTES: 1. Set this bit to "0" to select a level-sensitive triggering. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). UART1, UART4 Interrupt Source Select Bit UART0, UART3 Interrupt Source Select Bit 0 : One edge 1 : Both edges IFSR3 IFSR4 IFSR5 IFSR6 IFSR0 IFSR2 IFSR1 IFSR7 RW RW RW RW RW RW RW RW 0 : UART3 bus conflict, start condition detect, stop condition detect 1 : UART0 bus conflict, start condition detect, stop condition detect 0 : UART4 bus conflict, start condition detect, stop condition detect 1 : UART1 bus conflict, start condition detect, stop condition detect b7 b6 b5 b4 b3 b2 b1 b0

11.7 INT Interrupt

External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an inter- rupt at an applied signal level. The POL bit in the INTiIC register determines the polarity. For edge sensitive, when the IFSRi bit in the IFSR register is set to "1", an interrupt occurs on both rising and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding register to "0" (falling edge). For level sensitive, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains unchanged even if the INTi pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when the IR bit is written to "0" by program. Figure 11.10 shows the IFSR register. Figure 11.10 IFSR Register

Page 115 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Interrupt Control Circuit KUPIC Register Key Input Interrupt Request P107/KI3 P106/KI2 P105/KI1 P104/KI0 PU31 Bit in the PUR3 Register PD10_7 Bit Pull-up Transistor PD10_7 Bit PD10_6 Bit PD10_5 Bit PD10_4 Bit Pull-up Transistor Pull-up TransistorPull-up Transistor PSC_7 Bit

11.8 NMI Interrupt(1)

The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal to a low-level ("L") signal. The NMI interrupt is a non-maskable interrupt. Although the P85/NMI pin is used as the NMI interrupt input pin, the P8_5 bit in the P8 register indicates the input level for this pin. NOTES: 1. When the NMI interrupt is not used, connect the NMI pin to VCC via a resistor. Because the NMI interrupt cannot be ignored, the pin must be connected.

11.9 Key Input Interrupt

Key input interrupt request is generated when one of the signals applied to the P104 to P107 pins in input mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait or stop mode. To use the key input interrupt, do not use P10 4 to P107 as A/D input ports. Figure 11.11 shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode, signals applied to other pins are not detected as an interrupt request signal. When the PSC_7 bit in the PSC register (2) is set to "1" (key input interrupt disabled), no key input interrupt occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a port pin is available even when in input mode. NOTES: 2. Refer to 24. Programmable I/O Ports about the PSC register. Figure 11.11 Key Input Interrupt

Page 116 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M AIER0 AIER1 AIER2 Address Match Interrupt 0 Enable Bit Address Match Interrupt 1 Enable Bit Address Match Interrupt 2 Enable Bit Address Match Interrupt 3 Enable Bit AIER3 Function Address Match Interrupt Enable Register Bit NameBit Symbol Symbol Address After Reset AIER 0009 16 0000 0000 2 RW RW RW RW RW AIER4 AIER5 Address Match Interrupt 4 Enable Bit Address Match Interrupt 5 Enable Bit Address Match Interrupt 6 Enable Bit AIER6 RW RW RW Address Match Interrupt 7 Enable Bit AIER7 RW 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt b7 b6 b5 b4 b3 b2 b1 b0

11.10 Address Match Interrupt

The address match interrupt occurs immediately before executing an instruction that is stored into an ad- dress indicated by the RMADi register (i=0 to 7). The address match interrupt can be set in eight ad- dresses. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I flag and IPL do not affect the address match interrupt. Figure 11.12 shows registers associated with the address match interrupt. The starting address of an instruction must be set in the RMADi register. The address match interrupt does not occur when a table data or addresses other than the starting address of the instruction is set. Figure 11.12 AIER Register and RMAD0 to RMAD7 Registers Address Match Interrupt Register i (i=0 to 7) Function RW RW Symbol Address After Reset RMAD0 0012 16 - 001016 000000 16 RMAD1 0016 16 - 001416 000000 16 RMAD2 001A 16 - 001816 000000 16 RMAD3 001E 16 - 001C16 000000 16 RMAD4 002A 16 - 002816 000000 16 RMAD5 002E 16 - 002C16 000000 16 RMAD6 003A 16 - 003816 000000 16 RMAD7 003E 16 - 003C16 000000 16 00000016 to FFFFFF16Addressing Register for the Address Match Interrupt b23 b16 b15 b8 b7 b0 Setting Range

Page 117 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Bit 1 IIOiIR Register(2) Intelligent I/O Interrupt i Request IIOiIE Register(3) IRLT Bit in IIOiIE Register Interrupt Request(1) Interrupt Request(1) Interrupt Request(1) Bit 2 Bit 7 Bit 1 Bit 2 Bit 7 i= 0 to 5, 8 to 11 NOTES: 1. See Figures 11.14 and 11.15 about bits 1 to 7 in the IIOiIR register and bits 1 to 7 in the IIOiIE register. 2. Bits 1 to 7 in the IIOiIR register are not set to "0" automatically even if an interrupt request is generated. Set to "0" by program. 3. Do not change the IRLT bit and the interrupt enable bit in the IIOiIE register simultaneously.

11.11 Intelligent I/O Interrupt and CAN Interrupt

The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 49, 52 to 54, and 57. When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register (i = 0 to 5, 8 to 11) to "1" (interrupt request for interrupt used). Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is gener- ated with each intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1" (interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested). After the IR bit setting changes "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1". Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit to "0" by program. If these bit settings are left "1", all generated interrupt requests are ignored. Figure 11.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 11.14 shows the IIOiIR register. Figure 11.15 shows the IIOiIE register. Figure 11.13 Intelligent I/O Interrupt and CAN Interrupt

Page 118 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M The CANjk (j=0 to 1, k=0 to 2) interrupt and CAN1 wake-up interrupt are provided as the CAN interrupt. The following registers are required for the CAN interrupts:

Bits 7 in the IIO9IR to IIO11IR registers and Bits 7 in the IIO9IE to IIO11IE registers for the CAN00 to CAN02 interrupts.
Bits 7 in the IIO0IR, IIO1IR and IIO5IR registers and Bits 7 in the IIO0IE, IIO1IE and IIO5IE registers for the CAN10 to CAN12 interrupts.
Bit 6 in the IIO5IR register and Bit 6 in the IIO5IE register for the CAN1 wake-up interrupt. The CAN0IC, CAN1IC, CAN3IC and CAN4IC registers share addresses with the following registers:
The CAN0IC register shares an address with the IIO9IC register.
The CAN1IC register shares an address with the IIO10IC register.
The CAN3IC register shares an address with the IIO0IC register.
The CAN4IC register shares an address with the IIO1IC register. Refer to 23.4 CAN Interrupt for details. When using the intelligent I/O interrupt or CAN interrupt to activate DMAC II, set the IRLT bit in the IIOiIE register to "0" (interrupt used for DMAC, DMAC II) to enable the interrupt request that the IIOiIE register requires.

Page 119 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M Function Interrupt Request Register Bit Symbol Symbol Address After Reset IIO0IR to IIO5IR, IIO8IR to IIO11IR See below 0000 000X2 RW RW RW RW RW RW RW (Note 1) (b0) (b3) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) 0 : Requests no interrupt 1 : Requests an interrupt(2) 0 : Requests no interrupt 1 : Requests an interrupt (2) 0 : Requests no interrupt 1 : Requests an interrupt (2) 0 : Requests no interrupt 1 : Requests an interrupt (2) 0 : Requests no interrupt 1 : Requests an interrupt (2) 0 : Requests no interrupt 1 : Requests an interrupt (2) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. See table below for bit symbols. 2. Only "0" can be set (nothing is changed even if "1" is set). Symbol IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO8IR IIO9IR IIO10IR IIO11IR Address 00A0 00A116 00A216 00A316 00A416 00A516 00A816 00A916 00AA 16 00AB 16 Bit 7 CAN10R CAN11R SRT0R CAN12R CAN00R CAN01R CAN02R Bit 6 SRT1R CAN1WUR Bit 5 SIO0RR SIO0TR SIO1RR SIO1TR Bit 0 Bit 4 G0RIR G0TOR G1RIR G1TOR BT1R Bit 3 Bit 2 TM13R/PO13R TM14R/PO14R TM12R/PO12R TM10R/PO10R TM17R/PO17R Bit 1 TM11R/PO11R TM15R/PO15R TM16R/PO16R Bit Symbols for the Interrupt Request Register BT1R TM1jR PO1jR SIOiRR SIOiTR GiTOR GiRIR SRTiR CAN0kR CAN1mR CAN1WUR : Intelligent I/O Base Timer Interrupt Request : Intelligent I/O Time Measurement j Interrupt Request : Intelligent I/O Waveform Generating Function j Interrupt Request : Intelligent I/O Communication Unit i Receive Interrupt Request : Intelligent I/O Communication Unit i Transmit Interrupt Request : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Request (TO: Output to Transmit) : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Request (RI: Input to Receive) : Intelligent I/O Special Communication Function Interrupt Request : CAN0 Communication Function Interrupt Request (k = 0 to 2) : CAN1 Communication Function Interrupt Request (m = 0 to 2) : CAN1 Wake-up Interrupt Request : Reserved Bit. Set to "0". i = 0, 1 j = 0 to 7 Reserved bit. Set to "0". When read, its content is indeterminate. RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 11.14 IIO0IR to IIO5IR, IIO8IR to IIO11IR Registers

Page 120 974fo5002,80.peS00.1.veR 0010-4020B90JER 11. Interrupts)T68/C23M,68/C23M(puorG68/C23M b7 b6 b5 b4 b3 b2 b1 b0 i = 0, 1 j = 0 to 7 Function Interrupt Enable Register Bit NameBit Symbol Symbol Address After Reset IIO0IE to IIO5IE, IIO8IE to IIO11IESee below 0000 0000 2 RW 0 : Disables an interrupt by bit 1 in IIOiIR register 1 : Enables an interrupt by bit 1 in IIOiIR register 0 : Disables an interrupt by bit 7 in IIOiIR register 1 : Enables an interrupt by bit 7 in IIOiIR register 0 : Disables an interrupt by bit 6 in IIOiIR register 1 : Enables an interrupt by bit 6 in IIOiIR register 0 : Disables an interrupt by bit 5 in IIOiIR register 1 : Enables an interrupt by bit 5 in IIOiIR register 0 : Disables an interrupt by bit 4 in IIOiIR register 1 : Enables an interrupt by bit 4 in IIOiIR register 0 : Disables an interrupt by bit 2 in IIOiIR register 1 : Enables an interrupt by bit 2 in IIOiIR register 0 : Interrupt request is used for DMAC, DMAC II 1 : Interrupt request is used for interruptIRLT Interrupt Request Select Bit (2) Address 00B016 00B116 00B216 00B316 00B416 00B516 00B816 00B916 00BA 16 00BB 16 Bit 7 CAN10E CAN11E SRT0E CAN12E CAN00E CAN01E CAN02E Bit Symbols for the Interrupt Enable Register BT1E TM1jE PO1jE SIOiRE SIOiTE GiTOE GiRIE SRT iE CAN0kE CAN1mE CAN1WUE Bit 6 SRT 1E CAN1WUE Bit 5 SIO0RE SIO0TE SIO1RE SIO1TE Bit 4 G0RIE G0TOE G1RIE G1TOE BT1E Bit 3 Bit 2 TM13E/PO13E TM14E/PO14E TM12E/PO12E TM10E/PO10E TM17E/PO17E Bit 1 TM11E/PO11E TM15E/PO15E TM16E/PO16E Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO8IE IIO9IE IIO10IE IIO11IE Bit 0 IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT RW RW RW RW RW RW RW (Note 1) (Note 1) (b3) (Note 1) (Note 1) (Note 1) (Note 1) : Intelligent I/O Base Timer Interrupt Enabled : Intelligent I/O Time Measurement j Interrupt Enabled : Intelligent I/O Waveform Generating Function j Interrupt Enabled : Intelligent I/O Communication Unit i Receive Interrupt Enabled : Intelligent I/O Communication Unit i Transmit Interrupt Enabled : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (TO: Output to Transmit) : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (RI: Input to Receive) : Intelligent I/O Special Communication Function Interrupt Enabled : CAN0 Communication Function Interrupt Enabled (k = 0 to 2) : CAN1 Communication Function Interrupt Enabled (m = 0 to 2) : CAN1 Wake-up Interrupt Enabled : Reserved Bit. Set to "0". Reserved Bit Set to "0" NOTES: 1. See table below for bit symbols. 2. If an interrupt request is used for interrupt, set bit 1, 2, 4 to 7 to "1" after the IRLT bit is set to "1". RW Figure 11.15 IIO0IE to IIO5IE, IIO8IE to IIO11IE Registers

Page 122 974fo5002,80.peS00.1.veR 0010-4020B90JER 12. Watchdog Timer)T68/C23M,68/C23M(puorG68/C23M WDC7 WDC5 (b4 - b0) (b6) Reserved Bit Prescaler Select Bit Watchdog Timer Control Register High-Order Bit of the Watchdog Timer 0 : Divide-by-16 1 : Divide-by-128 0 : Cold start-up 1 : Warm start-up Set to "0" Symbol Address After Reset WDC 000F 16 000X XXXX 2 RW RO RW RW RW Bit Name FunctionBit Symbol Cold Start-up/ Warm Start-up Determine Flag (1,2, 3) NOTES: 1. The WDC5 bit remains set to "1", regardless of setting to "1" or "0". 2. The WDC5 bit is set to "0" when power is turned on and can be set to "1" by program only. 3. The WDC5 bit maintains a value set before reset, even after reset has been performed. b7 b6 b5 b4 b3 b2 b1 b0 Watchdog Timer Start Register(1) Symbol Address After Reset WDTS 000E 16 Indeterminate RW WO Function The watchdog timer is reset to start counting by a write instruction to the WDTS register. Default value of the watchdog timer is always set to "7FFF 16" regardless of the value written. NOTES: 1. Write the WDTS register after the watchdog timer interrupt is generated. b7 b0 Figure 12.2 WDC Register and WDTS Register

Page 123 974fo5002,80.peS00.1.veR 0010-4020B90JER 12. Watchdog Timer)T68/C23M,68/C23M(puorG68/C23M Symbol Address After Reset CM0 0006 16 0000 1000 2 System Clock Control Register 0(1) CM00 CM01 CM02 Clock Output Function Select Bit(2) In Wait Mode, Peripheral Function Clock Stop Bit(9) Port XC Switch Bit Main Clock (XIN-XOUT ) Stop Bit(5, 9) CM04 CM05 CM06 CM07 RWFunctionBit NameBit Symbol RW RW RW RW RW RW RW RW 0 : Main clock oscillates 1 : Main clock stops(6) 0 0 : I/O port P53 0 1 : Outputs fC 1 0 : Outputs f8 1 1 : Outputs f32 0 : I/O port function 1 : XCIN-XCOUT oscillation function(4) XCIN-XCOUT Drive Capacity Select Bit(11) Watchdog Timer Function Select Bit CPU Clock Select Bit 0 (8, 9, 10) 0: Clock selected by the CM21 bit divided by MCD register setting 1: Sub clock 0 : Watchdog timer interrupt 1 : Reset(7) NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 and CM00 bits to "002". When the PM15 and PM14 bits in the PM1 register are set to "012" (ALE output to P53), set the CM01 and CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 and CM00 bits) in microprocessor or memory expansion mode, and the CM01 and CM00 bits are set to "00 2", an "L" signal is output from port P53 (port P53 does not function as an I/O port). 3. fc32 does not stop running. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode. 4. When setting the CM04 bit is set to "1", set the PD8_7 and PD8_6 bits in the PD8 register to "002" (port P87 and P86 in input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up). 5. When entering low-power consumption mode or on-chip oscillator low-power consumption mode, the CM05 bit stops running the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop running the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the CM05 bit is set to "1", the clock applied to X OUT becomes "H". The built-in feedback resistor remains ON. XIN is pulled up to XOUT ("H" level) via the feedback resistor. 6. When the CM05 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002" (divide-by-8 mode). In on-chip oscillation mode, the MCD4 to MCD0 bits are not set to "010002" even if the CM05 bit terminates XIN-XOUT . 7. Once the CM06 bit is set to "1", it cannot be set to "0" by program. 8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0". After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1". Do not set the CM07 bit and CM04 or CM05 bit simultaneously. 9. When the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM02, CM05 and CM07 bits do not change even when written. 10. After the CM07 bit is set to "0", set the PM21 bit to "1". 11. When stop mode is entered, the CM03 bit is set to "1". b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 0 : Peripheral clock does not stop in wait mode 1 : Peripheral clock stops in wait mode (3) CM03 0 : Low 1 : High Figure 12.3 CM0 Register

Page 124 974fo5002,80.peS00.1.veR 0010-4020B90JER 12. Watchdog Timer)T68/C23M,68/C23M(puorG68/C23M

12.1 Count Source Protection Mode

In count source protection mode, the on-chip oscillator clock is used as a count source for the watchdog timer. The count source protection mode allows the on-chip oscillator clock to run continuously, maintain- ing watchdog timer operation even if the program error occurs and the CPU clock stops running. Follow the procedures below when using this mode. (1) Set the PRC0 bit in the PRCR register to "1" (write to CM0 register enabled) (2) Set the PRC1 bit in the PRCR register to "1" (write to PM2 register enabled) (3) Set the CM06 bit in the CM0 register to "1" (reset when the watchdog timer overflows) (4) Set the PM22 bit in the PM2 register to "1" (the on-chip oscillator clock as a count source of the watch- dog timer) (5) Set the PRC0 bit to "0" (write to CM0 register disabled) (6) Set the PRC1 bit to "0" (write to PM2 register disabled) (7) Write to the WDTS register (the watchdog timer starts counting) The followings will occur when the PM22 bit is set to "1".

The on-chip oscillator starts oscillating and the on-chip oscillator clock becomes a count source for the watchdog timer. Watchdog timer cycle =
Write to the CM10 bit in the CM1 register is disabled. (The bit setting remains unchanged even if set it to "1". The microcomputer does not enter stop mode.)
In wait mode or hold state, the watchdog timer continues running. However, the watchdog timer interrupt cannot be used to exit wait mode. Counter value of watchdog timer (32768) On-chip oscillator clock

Page 125 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M 13. DMAC This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized if using DMAC. DMA2 and DMA3 share registers required for high-speed interrupts. High-speed interrupts cannot be used when using three or more DMAC channels. The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. The cycle-steal method employed on DMAC enables high-speed operation between a transfer request and the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 13.1 shows a mapping of registers to ated with DMAC. Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to write to the registers. To set the DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register bank 1) and set the R0 to R3, A0, A1 registers with the MOV instruction. To set the DSA2 and DSA3 registers, set the B flag to "1" and set the SB and FB registers with the LDC instruction. To set the DRA2 and DRA3 registers, set the SVP and VCT registers with the LDC instruction. DMA Mode Register 0 DMA 0 Transfer Count Register DMA 0 Transfer Count Reload Register(1) DMA 0 Memory Address Register DMA 0 SFR Address Register DMA 0 Memory Address Reload Register(1) DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMAC-Associated Registers When Three or More DMAC Channels are Used, the High-Speed Interrupt Register is Used as DMAC Registers DMA2 Transfer Count Register DMA2 Transfer Count Reload Register(1) DMA2 Memory Address Register DMA2 SFR Address Register DCT2 (R0) DCT3 (R1) DRC2 (R2) DRC3 (R3) DMA2 (A0) DMA3 (A1) DSA2 (SB) DSA3 (FB) When using DMA2 and DMA3, use the CPU registers shown in parentheses (). When Three or More DMAC Channels are Used, the Register Bank 1 is Used as DMAC Registers DMA3 Transfer Count Register DMA3 Transfer Count Reload Register(1) DMA3 Memory Address Register DMA3 SFR Address Register SVF DMA2 Memory Address Reload Register(1)DRA2 (SVP) DRA1 (VCT) Flag Save Register DMA3 Memory Address Reload Register(1) DMA Mode Register 1 DMA 1 Transfer Count Register DMA 1 Transfer Count Reload Register(1) DMA 1 Memory Address Register DMA 1 SFR Address Register DMA 1 Memory Address Reload Register(1) NOTES: 1. Registers are used for repeat transfer, not for single transfer. Figure 13.1 Register Mapping for DMAC

Page 126 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. There- fore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged. Table 13.1 DMAC Specifications Item Specification Channels 4 channels (cycle-steal method) Transfer Memory Space • From a desired address in a 16-Mbyte space to a fixed address in a 16-Mbyte space

From a fixed address in a 16-Mbyte space to a desired address in a 16-Mbyte space Maximum Bytes Transferred 128 Kbytes (when a 16-bit data is transferred) or 64 Kbytes (with an 8- bit data is transferred) DMA Request Source(1) Falling edge or both edges of signals applied to the INT0 to INT3 pins Timers A0 to A4 interrupt requests Timers B0 to B5 interrupt requests UART0 to UART4 transmit and receive interrupt requests A/D0 conversion interrupt request Intelligent I/O interrupt request CAN interrupt request Software trigger Channel Priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority) Transfer Unit 8 bits, 16 bits Destination Address Forward/fixed (forward and fixed directions cannot be specified when specifying source and destination addresses simultaneously) Transfer Mode Single TransferTransfer is completed when the DCTi register (i = 0 to 3) is set to "000016" Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register is reloaded into the DCTi register and the DMA transfer is continued DMA Interrupt Request Generation TimingWhen the DCTi register changes "000116" to "000016" DMA Startup Single Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 and MD0 bits in the DMDj register (j = 0,1) are set to "012" (single transfer) Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 and MDi0 bits are set to "112" (repeat transfer) DMA Stop Single TransferDMA stops when the MDi1 and MDi0 bits are set to "002" (DMA dis- abled) and the DCTi register is set to "000016" (0 DMA transfer) by DMA transfer or write Repeat Transfer DMA stops when the MDi1 and MDi0 bits are set to "002" and the DCTi register is set to "000016" and the DRCi register set to "000016" Reload Timing to the DCTi When the DCTi register is set to "000016" from "000116" in repeat trans- or DMAi Register fer mode DMA Transfer Cycles Minimum 3 cycles between SFR and internal RAM NOTES: 1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.

Page 127 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M DMAi Request Source Select Register (i=0 to 3) RW RW RW RW RW RW RW RO RW DSEL0 DSEL1 DSEL2 DMA Request Source Select Bit(1) DSEL3 DSEL4 Software DMA Request Bit(2)DSR (b6) See Table 13.2 for the DMiSL register (i = 0 to 3) function DRQ DMA Request Bit (2, 3) 0 : Not requested 1 : Requested NOTES: 1. Change the DSEL4 to DSEL0 bit settings while the MDi1 and MDi0 bits in the DMD0 and DMD1 registers are set to "002" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the DSEL4 to DSEL0 bit settings are changed. e.g., MOV.B #083h, DMiSL ; Set timer A0 2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously. e.g., OR.B #0A0h, DMiSL 3. Do not set the DRQ bit to "0". Symbol Address After Reset DM0SL to DM3SL 0378 16, 037916, 037A16, 037B16 0X00 0000 2 FunctionBit NameBit Symbol When a software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, its content is always "0") Reserved Bit When read, its content is indeterminate b7 b6 b5 b4 b3 b2 b1 b0 Figure 13.2 DM0SL to DM3SL Registers

Page 128 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M Setting Value DMA Request Source b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 DMA0 Falling Edge of INT0 Both Edges of INT0 DMA1 DMA2 Falling Edge of INT2 Both Edges of INT2 DMA3 Falling Edge of INT3(1) Both Edges of INT3(1) Software trigger Timer A0 Interrupt Request Timer A1 Interrupt Request Timer A2 Interrupt Request Timer A3 Interrupt Request Timer A4 Interrupt Request Timer B0 Interrupt Request Timer B1 Interrupt Request Timer B2 Interrupt Request Timer B3 Interrupt Request Timer B4 Interrupt Request Timer B5 Interrupt Request UART0 Transmit Interrupt Request UART0 Receive or ACK Interrupt Request (3) UART1 Transmit Interrupt Request UART1 Receive or ACK Interrupt Request(3) UART2 Transmit Interrupt Request UART2 Receive or ACK Interrupt Request(3) UART3 Transmit Interrupt Request UART3 Receive or ACK Interrupt Request(3) UART4 Transmit Interrupt Request UART4 Receive or ACK Interrupt Request(3) Falling Edge of INT1 Both Edges of INT1 Intelligent I/O Interrupt 0 Request(6) Intelligent I/O Interrupt 1 Request(7) Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request CAN Interrupt 5 Request Intelligent I/O Interrupt 8 Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request(5) CAN Interrupt 2 Request Intelligent I/O Interrupt 0 Request(6) Intelligent I/O Interrupt 1 Request(7) Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request CAN Interrupt 5 Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request(5) CAN Interrupt 2 Request Intelligent I/O Interrupt 0 Request(6) Intelligent I/O Interrupt 1 Request(7) Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request (Note 2) (Note 2) NOTES: 1. If the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request cannot be generated by a signal applied to the INT3 pin. 2. The falling edge and both edges of signals applied to the INTj pin (j=0 to 3) cause a DMA request generation. The INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa. 3. Use the UkSMR register and UkSMR2 register (k=0 to 4) to switch between the UARTk receive and ACK interrupt as a DMA request source. To use the ACK interrupt for a DMA reqest, set the IICM bit in the UkSMR register to "1" and the IICM2 bit in the UkSMR2 register to "0". 4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request. 5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request. 6. The same setting is used to generate an intelligent I/O interrupt 0 request and a CAN interrupt 3 request. 7. The same setting is used to generate an intelligent I/O interrupt 1 request and a CAN interrupt 4 request. A/D0 Interrupt Request Intelligent I/O Interrupt 8 Request Table 13.2 DMiSL Register (i = 0 to 3) Function

Page 129 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M DMA Mode Register 0(1) RW RW RW RW RW RW RW RW RW MD00 MD01 BW0 Channel 0 Transfer Unit Select Bit Channel 0 Transfer Mode Select Bit RW0 MD10 Channel 0 Transfer Direction Select Bit Channel 1 Transfer Mode Select Bit Channel 1 Transfer Unit Select Bit 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : 8 bits 1 : 16 bits 0 : 8 bits 1 : 16 bits MD11 BW1 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer RW1 Channel 1 Transfer Direction Select Bit NOTES: 1. Use the LDC instruction to set the DMD0 register. Symbol Address After Reset DMD0 (CPU Internal Register) 00 16 FunctionBit NameBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b1 b0 Figure 13.3 DMD0 and DMD1 Registers DMA Mode Register 1(1) RW RW RW RW RW RW RW RW RW MD20 MD21 BW2 Channel 2 Transfer Unit Select Bit Channel 2 Transfer Mode Select Bit RW2 MD30 Channel 2 Transfer Direction Select Bit Channel 3 Transfer Mode Select Bit Channel 3 Transfer Unit Select Bit 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : 8 bits 1 : 16 bits 0 : 8 bits 1 : 16 bits MD31 BW3 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer RW3 Channel 3 Transfer Direction Select Bit NOTES: 1. Use the LDC instruction to set the DMD1 register. Symbol Address After Reset DMD1 (CPU internal register) 00 16 FunctionBit NameBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b1 b0

Page 130 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M Figure 13.4 DCT0 to DCT3 Registers and DRC0 to DRC3 Registers Function DMAi Transfer Count Register (i=0 to 3) Setting Range Symbol Address After Reset DCT0 (2) (CPU Internal Register) XXXX 16 DCT1 (2) (CPU Internal Register) XXXX 16 DCT2(bank1;R0)(3) (CPU Internal Register) 0000 16 DCT3(bank1;R1)(4) (CPU Internal Register) 0000 16 RW 000016 to FFFF16(1)Set the number of transfers RW NOTES: 1. When the DCTi register is set to "000016", no data transfer occurs regardless of a DMA request. 2. Use the LDC instruction to set the DCT0 and DCT1 registers. 3. To set the DCT2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R0 register. Use the MOV instruction to set the R0 register. 4. To set the DCT3 register, set the B flag to "1" and set R1 register. Use the MOV instruction to set the R1 register. b15 b8 b7 b0 Function DMAi Transfer Count Reload Register (i=0 to 3) Setting Range Symbol Address After Reset DRC0 (1) (CPU Internal Register) XXXX 16 DRC1 (1) (CPU Internal Register) XXXX 16 DRC2(bank1;R2)(2) (CPU Internal Register) 0000 16 DRC3(bank1;R3)(3) (CPU Internal Register) 0000 16 RW 000016 to FFFF16Set the number of transfers RW NOTES: 1. Use the LDC instruction to set the DRC0 and DRC1 registers. 2. To set the DRC2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R2 register. Use the MOV instruction to set the R2 register. 3. To set the DRC3 register, set the B flag to "1" and set R3 register. Use the MOV instruction to set the R3 register. b15 b8 b7 b0

Page 131 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M Figure 13.5 DMA0 to DMA3 Registers, DSA0 to DSA3 Registers and DRA0 to DRA3 Registers Function DMAi Memory Address Register (i=0 to 3) Setting Range Symbol Address After Reset DMA0 (2) (CPU Internal Register) XXXXXX 16 DMA1 (2) (CPU Internal Register) XXXXXX 16 DMA2(bank1;A0)(3) (CPU Internal Register) 000000 16 DMA3(bank1;A1)(4) (CPU Internal Register) 000000 16 RW 00000016 to FFFFFF16 (16-Mbyte space) Set a source memory address or destination memory address(1) RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a destination address is selected. When the RWk bit is set to "1" (memory to fixed address), a source address is selected. 2. Use the LDC instruction to set the DMA0 and DMA1 registers. 3. To set the DMA2 register, set the B flag in the FLG register to "1" (register bank 1) and set the A0 register. Use the MOV instruction to set the A0 register. 4. To set the DMA3 register, set the B flag to "1" and set the A1 register. Use the MOV instruction to set the A1 register. b23 b16 b8 b7 b0b15 Function DMAi SFR Address Register (i=0 to 3) Setting Range Symbol Address After Reset DSA0 (2) (CPU Internal Register) XXXXXX 16 DSA1 (2) (CPU Internal Register) XXXXXX 16 DSA2(bank1;SB)(3) (CPU Internal Register) 000000 16 DSA3(bank1;FB)(4) (CPU Internal Register) 000000 16 RW 00000016 to FFFFFF16 (16-Mbyte space) Set a source fixed address or destination fixed address(1) RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a source address is selected. When the RWk bit is set to "1" (memory to fixed address), a destination address is selected. 2. Use the LDC instruction to set the DSA0 and DSA1 registers. 3. To set the DSA2 register, set the B flag in the FLG register to "1" (register bank 1) and the set the SB register. Use the LDC instruction to set the SB register. 4. To set the DSA3 register, set the B flag to "1" and set the FB register. Use the LDC instruction to set the PB register. b23 b16 b8 b7 b0b15 Function DMAi Memory Address Reload Register(1) (i=0 to 3) Setting Range Symbol Address After Reset DRA0 (CPU Internal Register) XXXXXX 16 DRA1 (CPU Internal Register) XXXXXX 16 DRA2(SVP) (2) (CPU Internal Register) XXXXXX 16 DRA3(VCT) (3) (CPU Internal Register) XXXXXX 16 RW 00000016 to FFFFFF16 (16-Mbyte space) Set a source memory address or destination memory address(1) RW NOTES: 1. Use the LDC instruction to set the DRA0 and DRA1 registers. 2. To set the DRA2 register, set the SVP register. 3. To set the DRA3 register, set the VCT register. b23 b16 b8 b7 b0b15

Page 132 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M

13.1 Transfer Cycle

Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus cycle to write data to a memory space or the SFR area (destination write). The number of read and write bus cycles depends on source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on DS register setting. Software wait state insertion and the RDY signal make a bus cycle longer.

13.1.1 Effect of Source and Destination Addresses

When a 16-bit data is transferred with a 16-bit data bus and a source address starting with an odd address, source read cycle is incremented by one bus cycle, compared to a source address starting with an even address. When a 16-bit data is transferred with a 16-bit data bus and a destination address starting with an odd address, a destination write cycle is incremented by one bus cycle, compared to a destination address starting with an even address.

13.1.2 Effect of the DS Register

In an external space in memory expansion or microprocessor mode, transfer cycle varies depending on the data bus used at the source and destination addresses. See Figure 8.1 for details about the DS register.

When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing both source address and destination address, is used to transfer a 16-bit data, 8-bit data is transferred twice. Therefore, two bus cycles are required to read the data and another two bus cycles to write the data.
When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing source address, and a 16-bit data bus, accessing destination address, are used to transfer a 16-bit data, 8- bit data is read twice but is written once as 16-bit data. Therefore, two bus cycles are required for reading and one bus cycle is for writing.
When a 16-bit data bus, accessing source address, and an 8-bit data bus, accessing destination address, are used to transfer a 16-bit data, 16-bit data is read once and 8-bit data is written twice. Therefore, one bus cycle is required for reading and two bus cycles is for writing.

13.1.3 Effect of Software Wait State

When the SFR area or memory space with software wait states is accessed, the number of CPU clock cycles is incremented by software wait states. Figure 13.6 shows an example of a transfer cycle for the source-read bus cycle. In Figure 13.6, the number of source-read bus cycles is illustrated under different conditions, provided that the destination address is an address of an external space with the destination-write cycle as two CPU clock cycles (=one bus cycle). In effect, the destination-write bus cycle is also affected by each condition and the transfer cycles change accordingly. To calculate a transfer cycle, apply respective conditions to both destination-write bus cycle and source-read bus cycle. As shown in example (2) of Figure 13.6, when an 8-bit data bus, accessing both source and destination addresses, is used to transfer a 16-bit data, two bus cycles each are required for the source-read bus cycle and destination-write bus cycle.

13.1.4 Effect of RDY Signal

In memory expansion or microprocessor mode, the RDY signal affects a bus cycle if a source address or destination address is allocated address in an external space. Refer to 8.2.6 RDY Signal for details.

Page 133 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M (1) When 8-bit data is transferred or when 16-bit data is transferred with a 16-bit data bus from an even source address CPU Clock Address Bus RD Signal WR Signal Data Bus (3) When one wait state is inserted into the source-read bus cycle under the conditions in (1) (2) When 16-bit data is transferred from an odd source address or when 16-bit data is transferred and 8-bit bus is used to access a source address CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use CPU Use CPU Use CPU UseSource Source Source + 1 Source + 1 (4) When one wait state is inserted into the source-read bus cycle under the conditions in (2) NOTES: 1. The above applies when the destination-write bus cycle is 2 CPU clock cycles (=1 bus cycle). However, if the destination-write bus cycle is pleaced under these conditions, it will change to the same timing as the source-read cycle illustrated above. Destination Destination CPU Clock Address Bus RD Signal WR Signal Data bus CPU Use CPU Use CPU Use CPU UseSource Source Destination Destination CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use CPU Use CPU Use CPU UseSource Source Source + 1 Source + 1 Destination Destination CPU Use CPU UseSource Destination CPU Use CPU UseSource Destination CPU Clock Figure 13.6 Transfer Cycle Examples with the Source-Read Bus Cycle

Page 134 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M

13.2 DMAC Transfer Cycle

The number of DMAC transfer cycle can be calculated as follows. Any combination of even or odd transfer read and write addresses are possible. Table 13.3 lists the number of DMAC transfer cycles. Table 13.4 lists coefficient j, k. Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k Table 13.3 DMAC Transfer Cycles Single-Chip Mode Memory Expansion Mode Microprocessor ModeTransfer Unit Bus Width Access Address Read Write Read Write Cycle Cycle Cycle Cycle 16-bit Even 1 1 1 1 8-bit transfers Odd 1 1 1 1 (BWi bit in the DMDp 8-bit Even —— 11 register = 0) Odd —— 11 16-bit Even 1 1 1 1 16-bit transfers Odd 2 2 2 2 (BWi bit = 1) 8-bit Even —— 22 Odd —— 22 i= 0 to 3, p = 0, 1 Table 13.4 Coefficient j, k Internal Space External Space Internal ROM Internal ROM SFR or internal RAM or internal RAM area j and k BCLK cycles shown in Table 8.5. with no wait statewith a wait state Add one cycle to j or k cycles when inserting a recovery cycle. j=1 j=2 j=2 k=1 k=2 k=2 j, k=2 to 9

13.3 Channel Priority and DMA Transfer Timing

When multiple DMA requests are generated in the same sampling period, between the falling edge of the CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested) simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3. Figure 13.7 shows an example of the DMA transfer by external source. In Figure 13.7, the DMA0 request having highest priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts. After one DMA1 transfer is completed, the privilege is again returned to the CPU. In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when DMA requests, as DMA1 in Figure 13.7, occur more than once before receiving bus privilege, the DRQ bit is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is completed.

Page 135 974fo5002,80.peS00.1.veR 0010-4020B90JER 13. DMAC)T68/C23M,68/C23M(puorG68/C23M CPU Clock /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLinesDMA0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLinesDMA1 DRQ Bit in DMA0 Register DRQ Bit in DMA1 Register /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLinesCPU INT0 INT1 When DMA transfer request signals by external source are applied to INT0 and INT1 simultaneously and a DMA transfer with minimum cycle occurs /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bus privilege acquired /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Figure 13.7 DMA Transfer by External Source

Page 136 974fo5002,80.peS00.1.veR 0010-4020B90JER 14. DMACII)T68/C23M,68/C23M(puorG68/C23M 14. DMAC II DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which transfers the sum of two data added by an interrupt request from any peripheral functions. Table 14.1 lists specifications of DMAC II. Table 14.1 DMAC II Specifications Item Specification DMAC II Request Source Interrupt requests generated by all peripheral functions when the ILVL2 to ILVL0 bits are set to "1112" Transfer Data • Data in memory is transferred to memory (memory-to-memory transfer)

Immediate data is transferred to memory (immediate data transfer)
Data in memory (or immediate data) + data in memory are transferred to memory (calculation transfer) Transfer Block 8 bits or 16 bits Transfer Space 64-Kbyte space in addresses 00000 16 to 0FFFF16(1, 2) Transfer Direction Fixed or forward address Selected separately for each source address and destination address Transfer Mode Single transfer, burst transfer Chained Transfer FunctionParameters (transfer count, transfer address and other information) are switched when transfer counter reaches zero End-of-Transfer Interrupt Interrupt occurs when a transfer counter reaches zero Multiple Transfer FunctionMultiple data can be transferred by a generated request for one DMAC II transfer NOTES: 1. When transferring a 16-bit data to destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16. 2. The actual space where transfer can occurs is limited due to internal RAM capacity.

14.1 DMAC II Settings

DMAC II can be made available by setting up the following registers and tables.

RLVL register
DMAC II Index
Interrupt control register of the peripheral function causing a DMAC II request
The relocatable vector table of the peripheral function causing a DMAC II request
IRLT bit in the IIOiIE register (i = 0 to 5, 8 to 11) if using the intelligent I/O or CAN interrupt Refer to 11. Interrupts for details on the IIOiIE register.

14.1.1 RLVL Register

When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), DMAC II is activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the interrupt control register set to "111 2" (level 7). Figure 14.1 shows the RLVL register.

Page 137 974fo5002,80.peS00.1.veR 0010-4020B90JER 14. DMACII)T68/C23M,68/C23M(puorG68/C23M Exit Priority Register After Reset XXXX 0000 2 Address 009F Symbol RLVL RW RW RW RW RW RW RLVL0 RLVL1 RLVL2 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit (1) FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt DMAII (b4) (b7 - b6) DMA II Select Bit (4) 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMA II transfer (3) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it to "0" before setting the interrupt control register. Figure 14.1 RLVL Register

Page 138 974fo5002,80.peS00.1.veR 0010-4020B90JER 14. DMACII)T68/C23M,68/C23M(puorG68/C23M Transfer Mode (MOD) Transfer Counter (COUNT) Transfer Source Address (or immediate data) (SADR) Operation Address(1) (OADR) Transfer Destination Address (DADR) Chained Transfer Address(2) (CADR0) Chained Transfer Address(2) (CADR1) End-of-Transfer Interrupt Address(3) (IADR0) End-of-Transfer Interrupt Address(3) (IADR1) 16 bitsDMAC II Index Starting Address (BASE) BASE + 2 BASE + 4 BASE + 6 BASE + 8 BASE + 10 BASE + 14 BASE + 16 BASE + 12 Transfer Mode (MOD) Transfer Counter (COUNT) Transfer Source Address (SADR1) Transfer Destination Address (DADR1) Transfer Source Address (SADR2) Transfer Destination Address (DADR2) Transfer Source Address (SADR7) Transfer Destination Address (DADR7) 16 bits BASE BASE + 2 BASE + 4 BASE + 6 BASE + 8 BASE + 10 BASE + 28 BASE + 30 Memory-to-Memory Transfer, Immediate Transfer, Calculation Transfer Multiple Transfer NOTES: 1. This data is not required when not using the calculation transfer function. 2. This data is not required when not using the chained transfer function. 3. This data is not required when not using the end-of-transfer interrupt. The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation transfer function, set destination address to BASE+6. (See Table 14.2) Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request.

14.1.2 DMAC II Index

The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination ad- dress, chained transfer address, and end-of-transfer interrupt address. This DMAC II index must be located on the RAM area. Figure 14.2 shows a configuration of the DMAC II index. Table 14.2 lists a configuration of the DMAC II index in transfer mode. Figure 14.2 DMAC II Index The followings are details of the DMAC II index. Set these parameters in the specified order listed in Table 14.2, according to DMAC II transfer mode.

Transfer mode (MOD) Two-byte data is required to set transfer mode. Figure 14.3 shows a configuration for transfer mode.
Transfer counter (COUNT) Two-byte data is required to set the number of transfer.
Transfer source address (SADR) Two-byte data is required to set the source memory address or immediate data.
Operation address (OADR) Two-byte data is required to set a memory address to be calculated. Set this data only when using the calculation transfer function.
Transfer destination address (DADR) Two-byte data is required to set the destination memory address.
Chained transfer address (CADR) Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set this data only when using the chained transfer function.
End-of-transfer interrupt address (IADR) Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this data only when using the end-of-transfer interrupt.

Page 139 974fo5002,80.peS00.1.veR 0010-4020B90JER 14. DMACII)T68/C23M,68/C23M(puorG68/C23M Memory-to-Memory Transfer /Immediate Data Transfer Calculation Transfer Multiple Transfer Chained Transfer End-of-Transfer Interrupt Not Used Not Used Not Used Not UsedUsed Not Used Not Used Not Used Used Used Not Used Used Used Used Not Available Not Available Used Used DMAC II Index COUNT MOD SADR DADR COUNT MOD SADR DADR CADR0 CADR1 COUNT MOD SADR OADROADR OADR DADR IADR0 IADR1 COUNT MOD SADR DADR IADR0 IADR1 COUNT MOD SADR DADR CADR0 CADR1 IADR0 IADR1 OADR 8 bytes 12 bytes COUNT MOD SADR DADR COUNT MOD SADR DADR CADR0 CADR1 10 bytes 14 bytes 12 bytes 14 bytes 18 bytes COUNT MOD SADR DADR CADR0 CADR1 IADR0 IADR1 16 bytes COUNT MOD SADR1 DADR1 SADRi DADRi i=1 to 7 max. 32 bytes (when i=7) Transfer Data Function (MULT=0) Function (MULT=1) Transfer Mode (MOD)(1) RW RW RW RW RW RW RW RW RW RW SIZE IMM UPDS Transfer Unit Select Bit UPDD INTE/ CNT2 (2) Transfer Destination Direction Select Bit 0: Fixed address 1: Forward address 0: Single transfer 1: Burst transfer Calculation Transfer Function Select Bit 0: Not used 1: Used 0: 8 bits 1: 16 bits BRST/ CNT1 (2) OPER/ CNT0 (2) CHAIN Transfer Data Select Bit Transfer Source D irection Select Bit Burst Transfer Select Bit End-of-Transfer Interrupt Select Bit Chained Transfer Select Bit 0: Immediate data 1: Memory Set to "1" Set to "0" MULT (b14 - b8) Multiple Transfer Select Bit 0: Multiple transfer not used 1: Use multiple transfer 0: Fixed address 1: Forward address 0: Interrupt not used 1: Use interrupt 0: Chained transfer not used 1: Use chained transfer b6 b5 b4 0 0 0: Do not set to this value 0 0 1: Once 0 1 0: Twice 1 1 0: 6 times 1 1 1: 7 times Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit NameBit Symbol NOTES: 1. MOD must be located on the RAM. When the MULT bit is set to "0" (no multiple transfer), bits 6 to 4 becomes the INTE, OPER and BRST bits. When the MULT bit is set to "1" (multiple transfer), bits 6 to 4 becomes the CNT2 to CNT0 bits. b7 b0b15 b8 Table 14.2 DMAC II Index Configuration in Transfer Mode Figure 14.3 MOD

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14.1.3 Interrupt Control Register for the Peripheral Function

For the peripheral function interrupt activating DMAC II, set the ILVL2 to ILVL0 bits to "1112" (level 7).

14.1.4 Relocatable Vector Table for the Peripheral Function

Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt activating DMAC II. When using the chained transfer, the relocatable vector table must be located in the RAM.

14.1.5 IRLT Bit in the IIOiIE Register (i=0 to 5, 8 to 11)

When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE register of the interrupt to "0".

14.2 DMAC II Performance

Function to activate DMAC II is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II is activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "111 2" (level 7). These peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral function interrupt cannot be used. When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "111 2" (level 7), DMAC II is activated regardless of what state the I flag and IPL are in.

14.3 Transfer Data

DMAC II transfers 8-bit or 16-bit data.

Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space (Addresses 0000016 to 0FFFF16) to another desired memory location in the same space.
Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space.
Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired memory location in a 64-Kbyte space. When a 16-bit data is transferred to the destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16. Actual transferable space varies depending on the internal RAM capacity.

14.3.1 Memory-to-memory Transfer

Data transfer between any two memory locations can be:

a transfer from a fixed address to another fixed address
a transfer from a fixed address to a relocatable address
a transfer from a relocatable address to a fixed address
a transfer from a relocatable address to another relocatable address When a relocatable address is selected, the address is incremented, after a transfer, for the next transfer. In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer address is incremented by two. When a source or destination address exceeds address 0FFFF 16 as a result of address incrementation, the source or destination address returns to address 0000016 and continues incrementation. Maintain source and destination address at address 0FFFF16 or below.

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14.3.2 Immediate Data Transfer

DMAC II transfers immediate data to any memory location. A fixed or relocatable address can be se- lected as the destination address. Store the immediate data into SADR. To transfer an 8-bit immediate data, write the data in the low-order byte of SADR (high-order byte is ignored).

14.3.3 Calculation Transfer

After two memory data or an immediate data and memory data are added together, DMAC II transfers calculated result to any memory location. SADR must have one memory location address to be calcu- lated or immediate data and OADR must have the other memory location address to be calculated. Fixed or relocatable address can be selected as source and destination addresses when using a memory + memory calculation transfer. If the transfer source address is relocatable, the operation address also becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address when using an immediate data + memory calculation transfer.

14.4 Transfer Modes

Single and burst transfers are available. The BRST bit in MOD selects transfer method, either single trans- fer or burst transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set to "0000 16".

14.4.1 Single Transfer

For every transfer request source, DMAC II transfers one transfer unit of 8-bit or 16-bit data once. When the source or destination address is relocatable, the address is incremented, after a transfer, for the next transfer. COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the inter- rupt is acknowledged when COUNT reaches "0".

14.4.2 Burst Transfer

For every transfer request source, DMAC II continuously transfers data the number of times determined by COUNT. COUNT is decremented every time a transfer occurs. The burst transfer ends when COUNT reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer ends if using the end- of-transfer interrupt. All interrupts are ignored while the burst transfer is in progress.

14.5 Multiple Transfer

The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memory-to- memory transfer. One transfer request source initiates multiple transfers. The CNT2 to CNT0 bits in MOD selects the number of transfers from "001 2" (once) to "1112" (7 times). Do not set the CNT2 to CNT0 bits to "0002". The transfer source and destination addresses for each transfer must be allocated alternately in addresses following MOD and COUNT. When the multiple transfer is selected, the calculation transfer, burst transfer, end-of-transfer interrupt and chained transfer cannot be used.

Page 142 974fo5002,80.peS00.1.veR 0010-4020B90JER 14. DMACII)T68/C23M,68/C23M(puorG68/C23M

14.6 Chained Transfer

The CHAIN bit in MOD selects the chained transfer. The following process initiates the chained transfer. (1) Transfer, caused by a transfer request source, occurs according to the content of the DMAC II index. The vectors of the request source indicates where the DMAC II index is allocated. For each request, the BRST bit selects either single or burst transfer. (2) When COUNT reaches "0", the contents of CADR1 and CADR0 are written to the vector of the request source. When the INTE bit in MOD is set to "1", the end-of-transfer interrupt is generated simulta- neously. (3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the DMAC II index indicated by the peripheral function interrupt vector rewritten in (2). Figure 14.4 shows the relocatable vector and DMACII index when the chained transfer is in progress. For the chained transfer, the relocatable vector table must be located in the RAM. RAM Relocatable Vector INTB DMAC II Index(1) DMAC II Index(2) BASE(1) BASE(2) BASE(2) BASE(3) (CADR1 to CADR0) (CADR1 to CADR0) Peripheral I/O interrupt vector causing DMAC II request Default value of DMAC II is BASE(1). The above vector is rewritten to BASE(2) when a transfer is completed. The above vector is rewritten to BASE(3) when a transfer is completed. Starts at BASE(2) when next request conditions are met. Transferred according to the DMAC II Index.Figure 14.4 Relocatable Vector and DMAC II Index

14.7 End-of-Transfer Interrupt

The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt is generated when COUNT reaches "0."

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14.8 Execution Time

DMAC II execution cycle is calculated by the following equations: Multiple transfers: t = 21+ (11 + b + c) x k cycles Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles a: If IMM = 0 (source of transfer is immediate data), a = 0; if IMM = 1 (source of transfer is memory), a = –1 b: If UPDS = 1 (source transfer address is a relocatable address), b = 0; if UPDS = 0 (source transfer address is a fixed address), b = 1 c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0; if UPDD = 0 (destination transfer address is a fixed address), c = 1 d: If OPER = 0 (calculation function is not selected), d = 0; if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed address memory), d = 7; if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address memory), d = 8 e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4 m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in transfer counter n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1 k: Number of transfers set in the CNT2 to CNT0 bits The equations above are approximations. The number of cycles may vary depending on CPU state, bus wait state, and DMAC II index allocation. The first instruction from the end-of-transfer interrupt routine is executed in the eighth cycle after the DMAC II transfer is completed. Figure 14.5 Transfer Cycle When an interrupt request as a DMAC II transfer request source and another interrupt request with higher priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher priority takes precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt sequence has been completed. a=-1 b=0 c=1 d=0 e=0 m=1 First DMAC II transfer t=6+26x1+4x1=36 cycles Second DMAC II transfer t=6+26x1+4x0=32 cycles Transfer counter = 2 Decrement a transfer counter Transfer counter = 1 Transfer counter = 1 Program ProgramDMAC II transfer (First time) DMAC II transfer (Second time) 7 cycles Processing the end-of-transfer interrupt DMAC II transfer request Decrement a transfer counter Transfer counter = 0 32 cycles36 cycles DMAC II transfer request If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address, single transfer and double transfer:

Page 144 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer)T68/C23M,68/C23M(puorG68/C23M 15. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each timer functions independently. The count source for each timer becomes the clock for timer operations including counting and reloading, etc. Figures 15.1 and 15.2 show block diagrams of timer A and timer B configuration. 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter mode TA0 IN TA1 IN TA2 IN TA3 IN TA4 IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 f1 f8 f2n fC32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter TCK1 and TCK0 00: Timer mode 10: One-shot tiemr mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter mode 01: Event counter mode 01: Event counter mode 01: Event counter mode TCK1 and TCK0 TCK1 and TCK0 TMOD1 and TMOD0 TMOD1 and TMOD0 TMOD1 and TMOD0 TA0TGH and TA0TGL CST: Bit in the TCSPR Register TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TAiMR Register (i=0 to 4) TAiTGH and TAiTGL: Bits in the ONSF Register or TRGSR Register TA2TGH and TA2TGL TA3TGH and TA3TGL TA4TGH and TA4TGL TMOD1 and TMOD0 TMOD1 and TMOD0 1/32 fC32XCIN Set the CPSR bit in the CPSRF register to "1" Reset Clock prescaler Timer B2 overflow or underflow signal TCK1 and TCK0 TCK1 and TCK0 TA1TGH and TA1TGL Figure 15.1 Timer A Configuration

Page 145 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer)T68/C23M,68/C23M(puorG68/C23M TB0 IN TB1 IN TB2 IN Timer B0 f1 f8 f2n fC32 Timer B0 interrupt Noise filter Timer B2 overflow or underflow signal (to a count source of Timer A) TB3 IN TB4 IN TB5 IN Timer B3 interrupt Timer B1 interrupt Timer B2 interrupt Timer B4 interrupt Timer B5 interrupt TCK1 to TCK0 Timer B1 TCK1 and TCK0 Noise filter Timer B2 TCK1 and TCK0 Noise filter Timer B3 TCK1 and TCK0 Noise filter TCK1 and TCK0 Timer B4Noise filter TCK1 and TCK0 Timer B5Noise filter 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 TMOD1 and TMOD0 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode TCK1 CST : Bit in the TCSPR Register TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TBiMR Register (i=0 to 5) TMOD1 and TMOD0 TMOD1 and TMOD0 TMOD1 and TMOD0 TMOD1 and TMOD0 TMOD1 and TMOD0 1/32 fC32XCIN Set the CPSR bit in the CPSRF register to "1" Reset Clock prescaler Figure 15.2 Timer B Configuration

Page 146 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M

15.1 Timer A

Figure 15.3 shows a block diagram of the timer A. Figures 15.4 to 15.7 show registers associated with the timer A. The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the same function. The TMOD1 and TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is used.

Timer mode: The timer counts an internal count source.
Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers.
One-shot timer mode: The timer outputs one valid pulse until a counter value reaches "0000 16".
Pulse width modulation mode: The timer continuously outputs desired pulse widths. Table 15.1 lists TAiOUT pin settings when used as an output. Table 15.2 lists TAiIN and TAiOUT pin settings when used as an input. TAiS Increment / decrement TAi Addresses TAj TAk Timer A0 034716 034616 Timer A4 Timer A1 Timer A1 034916 034816 Timer A0 Timer A2 Timer A2 034B16 034A16 Timer A1 Timer A3 Timer A3 034D16 034C 16 Timer A2 Timer A4 Timer A4 034F16 034E16 Timer A3 Timer A0 Select Count Source
Timer Mode (gate function): TMOD1 and TMOD0=00, MR2=1
Timer Mode :TMOD1 and TMOD0=00, MR2=0
One-Shot Timer Mode :TMOD1 and TMOD0=10
Pulse Width Modulation Mode :TMOD1 and TMOD0=11 f2n(1) TAiIN
Event Counter Mode:TMOD1 and TMOD0=01 fC32 Select clock TAj Overflow(2) Pulse Output Toggle Flip Flop TAiOUT Always decrement except in event counter mode 8 low- order bits High-Order Bits of Data Bus Reload Register Counter Low-Order Bits of Data Bus /LiteDiagLines /LiteDiagLines TAiUD Decrement TAk Overflow(2) Polarity Selector TCK1 and TCK0 TB2 Overflow(2) TAiTGH and TAiTGL MR2 TMOD1 and TMOD0 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. Overflow or underflow signal TCK1 and TCK0, TMOD1 and TMOD0, MR2 and MR1 : Bits in the TAiMR register TAiTGH and TAiTGL : Bits in the ONSF register if i=0 or bits in the TRGSR register if i=1 to 4 TAiS : Bits in the TABSR register TAiUD : Bits in the UDF register TMOD1 and TMOD0, MR2 i=0 to 4 j=i-1, except j=4 if i=0 k=i+1, except k=0 if i=4 8 high- order bits Figure 15.3 Timer A Block Diagram

Page 147 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Timer Ai Register (i=0 to 4)(1) Symbol Address After Reset TA0 to TA2 034716-034616, 034916-034816, 034B16-034A16 Indeterminate TA3, TA4 034D 16-034C16, 034F16-034E16 Indeterminate RW RW RW WO WO WO Timer Mode 0000 16 to FFFF16 000016 to FFFF16 000016 to FFFF16(3) 000016 to FFFE16(3) 0016 to FE16(3) (High-order address bits) 0016 to FF16(3) (Low-order address bits) Event Counter Mode (2) One-Shot Timer Mode (4) Pulse Width Modulation Mode(5) (16-Bit PWM) Pulse Width Modulation Mode (5) (8-Bit PWM) Function Setting RangeMode If setting value is n, count source is divided by n+1. If setting value is n, count source is divided by FFFF 16 - n+1 when the counter is incremented and by n+1 when the counter is decremented. If count source frequency is fj and setting value of the TAi register is n, PWM cycle: (2 16-1) / fj "H" width of PWM pulse: n / fj If count source frequency is fj, setting value of high-order bits in the TAi register is n and setting value of low-order bits in the TAi register is m , PWM cycle: (2 8-1)x(m+1) / fj "H" width of PWM pulse: (m+1)n / fj If setting value is n, count source is divided by n, then stops. b15 b8 b7 b0 fj : f1, f8, f2n, fC32 NOTES: 1. Use 16-bit data for reading and writing. 2. The TAi register counts how many pulse inputs are provided externally or how many times another timer counter overflows and underflows. 3. Use the MOV instruction to set the TAi register. 4. When the TAi register is set to "0000 16", the timer counter does not start and the timer Ai interrupt request is not generated. 5. When the TAi register is set to "000016", the pulse width modulator does not operate and the TAiOUT pin is held "L". The TAi interrupt request is also not generated. The same situation occurs in 8-bit pulse width modulator mode if the 8 high-order bits in the TAi register are set to "00 16". Figure 15.4 TA0 to TA4 Registers

Page 148 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Figure 15.5 TA0MR to TA4MR Registers and TABSR Register Timer Ai Mode Register (i=0 to 4) Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 0016 RW RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operating Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit Function varies depending on operating mode Function varies depending on operating mode 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode b1b0 Bit Name FunctionBit Symbol Reserved Bit Set to "0" (b3) b7 b6 b5 b4 b3 b2 b1 b0 Count Start Flag Symbol Address After Reset TABSR 0340 16 00 16 RW RW RW RW RW RW RW RW RW TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag 0 : Stops counting 1 : Starts counting TA2S Timer A2 Count Start Flag 0 : Stops counting 1 : Starts counting TA3S Timer A3 Count Start Flag 0 : Stops counting 1 : Starts counting TA4S Timer A4 Count Start Flag 0 : Stops counting 1 : Starts counting TB0S Timer B0 Count Start Flag 0 : Stops counting 1 : Starts counting TB1S Timer B1 Count Start Flag 0 : Stops counting 1 : Starts counting TB2S Timer B2 Count Start Flag 0 : Stops counting 1 : Starts counting Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0

Page 149 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Figure 15.6 UDF Register and ONSF Register Symbol Address After Reset UDF 0344 16 00 16 Up/Down Flag(1) RW RW RW RW Bit Name FunctionBit Symbol WO WO WO TA0UD Timer A0 Up/Down Flag(2) TA2P 0 : Decrement 1 : Increment TA1UD 0 : Decrement 1 : Increment RWTA2UD 0 : Decrement 1 : Increment TA3UD 0 : Decrement 1 : Increment RWTA4UD 0 : Decrement 1 : Increment Timer A2 Two-Phase Pulse Signal Processing Function Select Bit (3) 0 : Disables two-phase pulse signal processing function 1 : Enables two-phase pulse signal processing function TA3P Timer A3 Two-Phase Pulse Signal Processing Function Select Bit (3) 0 : Disables two-phase pulse signal processing function 1 : Enables two-phase pulse signal processing function Timer A4 Two-Phase Pulse Signal Processing Function Select Bit (3) TA4P 0 : Disables two-phase pulse signal processing function 1 : Enables two-phase pulse signal processing function Timer A1 Up/Down Flag(2) Timer A2 Up/Down Flag (2) Timer A3 Up/Down Flag (2) Timer A4 Up/Down Flag (2) b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Use the MOV instruction to set the UDF register. 2. This bit is enabled when the MR2 bit in the TAiMR register (i=0 to 4) is set to "0" (the UDF register causes increment/decrement switching) in event counter mode. 3. Set this bit to "0" when not using the two-phase pulse signal processing function. One-Shot Start Flag Symbol Address After Reset ONSF 0342 16 00 16 RW RWTA0OS Timer A0 One-Shot Start Flag(1) RWTA1OS Timer A1 One-Shot Start Flag(1) RWTA2OS Timer A2 One-Shot Start Flag(1) RWTA3OS Timer A3 One-Shot Start Flag(1) RWTA4OS Timer A4 One-Shot Start Flag(1) 0 : In an idle state 1 : Starts the timer RWTAZIE Z-Phase Input Enable Bit0 : Disables Z-phase input 1 : Enables Z-phase input Bit Name FunctionBit Symbol RW RW TA0TGL TA0TGH Timer A0 Event/Trigger Select Bit 0 0 : Selects an input to the TA0IN pin 0 1 : Selects the TB2 overflows(2) 1 0 : Selects the TA4 overflows(2) 1 1 : Selects the TA1 overflows(2) b7b6 NOTES: 1. When read, this bit is set to "0". 2. Overflow or underflow. 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer b7 b6 b5 b4 b3 b2 b1 b0

Page 150 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Figure 15.7 TRGSR Register and TCSPR Register Trigger Select Register Symbol Address After Reset TRGSR 0343 16 00 16 RW RW RW RW RW RW RW Bit Name FunctionBit Symbol RW RW TA4TGL TA4TGH Timer A4 Event/Trigger Select Bit TA1TGL TA1TGH Timer A1 Event/Trigger Select Bit b0b1 TA2TGL TA2TGH Timer A2 Event/Trigger Select Bit TA3TGL TA3TGH Timer A3 Event/Trigger Select Bit NOTES: 1. Overflow or underflow 0 0 : Selects an input to the TA1IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA0 overflows(1) 1 1 : Selects the TA2 overflows(1) b3 b2 0 0 : Selects an input to the TA2IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA1 overflows(1) 1 1 : Selects the TA3 overflows(1) b5 b4 0 0 : Selects an input to the TA3IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA2 overflows(1) 1 1 : Selects the TA4 overflows(1) b7 b6 0 0 : Selects an input to the TA4IN pin 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA3 overflows(1) 1 1 : Selects the TA0 overflows(1) b7 b6 b5 b4 b3 b2 b1 b0 Count Source Prescaler Register Symbol Address After Reset (2) TCSPR 035F 16 0XXX 0000 2 RW RW RW RW RW RO Bit Name FunctionBit Symbol RWCST Operation Enable Bit 0 : Stops a divider 1 : Starts a divider CNT0 CNT1 CNT2 CNT3 (b6 - b4) Divide Ratio Select Bit(1) If setting value is n, f2n is the main clock, on-chip oscillator or PLL clock divided by 2n. Not divided if n=0. NOTES: 1. Set the CST bit to "0" before the CNT3 to CNT0 bits are rewritten. 2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has performed. Reserved Bit When read, its content is indeterminate b7 b6 b5 b4 b3 b2 b1 b0

Page 151 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Table 15.1 Pin Settings for Output from TAiOUT Pin (i=0 to 4) Pin Setting PS1, PS2 Registers PSL1, PSL2 Registers PSC Register P70/TA0OUT (1) PS1_0= 1 PSL1_0=1 PSC_0= 0 P72/TA1OUT PS1_2= 1 PSL1_2=1 PSC_2= 0 P74/TA2OUT PS1_4= 1 PSL1_4=0 PSC_4= 0 P76/TA3OUT PS1_6= 1 PSL1_6=1 PSC_6= 0 P80/TA4OUT PS2_0= 1 PSL2_0=0 – NOTES: 1. P70/TA0OUT is a port for the N-channel open drain output. Table 15.2 Pin Settings for Input to TAiIN and TAiOUT Pins (i=0 to 4) PS1_0=0 Pin P70/TA0OUT P71/TA0IN P72/TA1OUT P73/TA1IN P74TA2 OUT PS1_1=0 PS1, PS2 Registers PS1_2=0 PS1_3=0 PS1_4=0 PD7, PD8 Registers PD7_0=0 PD7_1=0 PD7_2=0 PD7_3=0 PD7_4=0 Setting P75/TA2IN P76TA3 OUT P77/TA3IN P80/TA4OUT P81/TA4IN PS1_5=0 PS1_6=0 PS1_7=0 PS2_0=0 PS2_1=0 PD7_5=0 PD7_6=0 PD7_7=0 PD8_0=0 PD8_1=0

Page 152 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M

15.1.1 Timer Mode

In timer mode, the timer counts an internally generated count source (see Table 15.3). Figure 15.8 shows the TAiMR register (i=0 to 4) in timer mode. Table 15.3 Timer Mode Specifications Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio 1/(n+1) n: setting value of the TAi register (i=0 to 4) 000016 to FFFF16 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition The TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter underflows TAiIN Pin Function Programmable I/O port or gate input TAiOUT Pin Function Programmable I/O port or pulse output Read from Timer The TAi register indicates counter value Write to Timer • While the timer counter stops, the value written to the TAi register is also written to both reload register and counter

While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function • Gate function Input signal to the TAiIN pin determines whether the timer counter starts or stops counting
Pulse output function The polarity of the TAiOUT pin is inversed whenever the timer counter underflows NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 153 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Timer Ai Mode Register (i=0 to 4) (Timer Mode) Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 00 16 RW RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operating Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit Gate Function Select Bit Set to "0" in timer mode 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 0 0 : Timer mode b1b0 Bit Name FunctionBit Symbol b7b6 b4b3 NOTES: 1. X can be set to either "0" or "1". 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

0 X : Gate function disabled

(1) (TAiIN pin is a programmable I/O pin) 1 0 : Timer counts only while the TAiIN pin is held "L" 1 1 : Timer counts only while the TAiIN pin is held "H" Reserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 00 0 (b2) Figure 15.8 TA0MR to TA4MR Registers

Page 154 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M

15.1.2 Event Counter Mode

In event counter mode, the timer counts how many external signals are applied or how many times another timer counter overflows and underflows. The timers A2, A3 and A4 can count externally gener- ated two-phase signals. Table 15.4 lists specifications in event counter mode (when not handling a two- phase pulse signal). Table 15.5 lists specifications in event counter mode (when handling a two-phase pulse signal with the timers A2, A3 and A4). Figure 15.9 shows the TAiMR register (i=0 to 4) in event counter mode. Table 15.4 Event Counter Mode Specifications (When Not Processing Two-phase Pulse Signal) Item Specification Count Source • External signal applied to the TAiIN pin (i = 0 to 4) (valid edge can be selected by program)

Timer B2 overflow or underflow signal, timer Aj overflow or underflow signal (j=i-1, except j=4 if i=0) and timer Ak overflow or underflow signal (k=i+1, except k=0 if i=4) Counting Operation • External signal and program can determine whether the timer increments or decre- ments a counter value
When the timer counter underflows or overflows, content of the reload register is reloaded into the count register and counting resumes. When the free-running count function is selected, the timer counter continues running without reloading. Divide Ratio • 1/(FFFF16 - n + 1) for counter increment
1/(n + 1) for counter decrement n : setting value of the TAi register 000016 to FFFF16 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition The TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter overflows or underflows TAiIN Pin Function Programmable I/O port or count source input TAiOUT Pin Function Programmable I/O port, pulse output or input selecting a counter increment or decrement Read from Timer The TAi register indicates counter value Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function • Free-running count function Content of the reload register is not reloaded even if the timer counter overflows or underflows
Pulse output function The polarity of the TAi OUT pin is inversed whenever the timer counter overflows or underflows

Page 155 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Table 15.5 Event Counter Mode Specifications (When Processing Two-phase Pulse Signal on Timer A2, A3 and A4) Item Specification Count Source Two-phase pulse signal applied to the TAi IN and TAiOUT pins (i = 2 to 4) Counting Operation • Two-phase pulse signal determines whether the timer increments or decrements a counter value

When the timer counter overflows or underflows, content of the reload register is reloaded into the count register and counting resumes. With the free-running count function, the timer counter continues running without reloading. Divide Ratio • 1/ (FFFF16 - n + 1) for counter increment
1/ (n + 1) for counter decrement n : setting value of the TAi register 000016 to FFFF16 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition The TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter overflows or underflows TAiIN Pin Function Two-phase pulse signal is applied TAiOUT Pin Function Two-phase pulse signal is applied Read from Timer The TAi register indicates the counter value Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function(1) • Normal processing operation (the timer A2 and timer A3) While a high-level ("H") signal is applied to the TAjOUT pin (j = 2 or 3), the timer increments a counter value on the rising edge of the TAjIN pin or decrements a counter on the falling edge. TAjOUT Increment Decrement TAjIN Increment Increment Decrement Decremen t TAkOUT TAkIN Increment on all edgesDecrement on all edges NOTES: 1. Only timer A3 operation can be selected. The timer A2 is for the normal processing operation. The timer A4 is for the multiply-by-4 operation.
Multiply-by-4 processing operation (the timer A3 and timer A4) While an "H" signal is applied to the TAkOUT pin (k = 3 or 4) on the rising edge of the TAkIN pin, the timer increments a counter value on the rising and falling edges of the TAk OUT and TAkIN pins. While an "H" signal is applied to the TAkOUT pin on the falling edge of the TAkIN pin, the timer decrements a counter value on the rising and falling edges of the TAkOUT and TAkIN pins.

Page 156 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Function (When not processing two-phase pulse signal) Function (When processing two-phase pulse signal) Timer Ai Mode Register (i=0 to 4) (Event Counter Mode) Bit NameBit Symbol Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 00 16 RW 0 1 : Event counter mode(1) b1b0Operating Mode Select Bit Count Polarity Select Bit(2) Increment/Decrement Switching Source Select Bit Count Operation Type Select Bit 0 : Normal processing operation 1 : Multiply-by-4 processing operation 0 : Reloading 1 : Free running Set to "0" in event counter mode 0 : Counts falling edges of an external signal 1 : Counts rising edges of an external signal 0 : UDF registser setting 1 : Input signal to TAi OUT pin(3) Set to "0" Set to "1" Set to "0" TMOD0 TMOD1 (b2) MR1 MR2 MR3 TCK1 TCK0 RW RW RW RW RW RW RW RW Two-Phase Pulse Signal Processing Operation Select Bit (4,5) Reserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The TAiTGH and TAiTGL bits in the ONSF or TRGSR register determine the count source in the event counter mode. 2. MR1 bit setting is enabled only when counting how many times external signals are applied. 3. The timer decrements a counter value when an "L" signal is applied to the TA iOUT pin and the timer increments a counter value when an "H" signal is applied to the TAiOUT pin. 4. The TCK1 bit is enabled only in the TA3MR register. 5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (two-phase pulse signal processing function enabled). Also, set the TAiTGH and TAiTGL bits to "00 2" (input to the TAjIN pin). 0010 Figure 15.9 TA0MR to TA4MR Registers

Page 157 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Pulse width of one count source cycle or more is required NOTES: 1. When the rising edge of INT2 is selected. TA3 OUT (A-phase) Count source TA3 IN (B-phase) INT2 (1) (Z-phase) TA3 OUT (A-phase) Count source TA3 IN (B-phase) Timer counter is reset at this timing Counter value mm + 11 2 3 4 5 INT2 (1) (Z-phase) NOTES: 1. When the rising edge of INT2 is selected.

15.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing

Z-phase input resets the timer counter when processing a two-phase pulse signal. This function can be used in timer A3 event counter mode, two-phase pulse signal processing, free- running count operation type or multiply-by-4 processing. The Z-phase signal is applied to the INT2 pin. When the TAZIE bit in the ONSF register is set to "1" (Z-phase input enabled), Z-phase input can reset the timer counter. To reset the counter by a Z-phase input, set the TA3 register to "0000 16" beforehand. Z-phase input is enabled when the edge of the signal applied to the INT2 pin is detected. The POL bit in the INT2IC register can determine edge polarity. The Z-phase must have a pulse width of one timer A3 count source cycle or more . Figure 15.10 shows two-phase pulses (A-phase and B-phase) and the Z-phase. Z-phase input resets the timer counter in the next count source following Z-phase input. Figure 15.11 shows the counter reset timing. Timer A3 interrupt request is generated twice continuously when a timer A3 overflow or underflow, and a counter reset by INT2 input occur at the same time. Do not use the timer A3 interrupt request when this function is used. Figure 15.10 Two-Phase Pulse (A-phase and B-phase) and Z-phase Figure 15.11 Counter Reset Timing

Page 158 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M

15.1.3 One-Shot Timer Mode

In one-shot timer mode, the timer operates only once for each trigger (see Table 15.6). Once a trigger occurs, the timer starts and continues operating for a desired period. Figure 15.12 shows the TAiMR register (i=0 to 4) in one-shot timer mode. Table 15.6 One-Shot Timer Mode Specifications Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation • The timer decrements a counter value When the timer counter reaches "000016", it stops counting after reloading. If a trigger occurs while counting, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio 1/n n : setting value of the TAi register (i=0 to 4) 000016 to FFFF16, but the timer counter does not run if n=000016 Counter Start Condition The TAiS bit in the TABSR register is set to "1" (starts counting) and following triggers occur:

External trigger input is provided
Timer counter overflows or underflows
The TAiOS bit in the ONSF register is set to "1" (timer started) Counter Stop Condition • After the timer counter has reached "000016" and is reloaded
When the TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter reaches "000016" TAiIN Pin Function Programmable I/O port or trigger input TAiOUT Pin Function Programmable I/O port or pulse output Read from Timer The value in the TAi register is indeterminate when read Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 159 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Figure 15.12 TA0MR to TA4MR Registers b7 b6 b5 b4 b3 b2 b1 b0 00 1 Timer Ai Mode Register (i=0 to 4) (One-Shot Timer Mode) Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 00 16 RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operating Mode Select Bit Trigger Select Bit Set to "0" in the one-shot timer mode MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit External Trigger Select Bit(1) 0 : Falling edge of input signal to TAiIN pin 1 : Rising edge of input signal to TAiIN pin 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 1 0 : One-shot timer mode b1b0 Bit Name FunctionBit Symbol b7b6 NOTES: 1. The MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 0 : The TAiOS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits (b2) Reserved Bit Set to "0"

Page 160 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M

15.1.4 Pulse Width Modulation Mode

In pulse width modulation mode, the timer outputs pulse of desired width continuously (see Table 15.7). The timer counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 15.13 shows the TAiMR register (i=0 to 4) in pulse width modulation mode. Figures 15.14 and 15.15 show examples of how a 16-bit pulse width modulator operates and of how an 8-bit pulse width modulator operates. Table 15.7 Pulse Width Modulation Mode Specifications Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation • The timer decrements a counter value (The counter functions as an 8-bit or a 16-bit pulse width modulator) Content of the reload register is reloaded on the rising edge of PWM pulse and count- ing continues. The timer is not affected by a trigger that is generated during counting. 16-Bit PWM • "H" width = n / fj n : setting value of the TAi register 000016 to FFFE16 fj : count source frequency

Cycle = (216-1) / fj fixed 8-Bit PWM • "H" width = n x (m+1) / fj
Cycles = (28-1) x (m+1) / fj m : setting value of low-order bit address of the TAi register 0016 to FF16 n : setting value of high-order bit address of the TAi register 0016 to FE16 Counter Start Condition • External trigger input is provided
Timer counter overflows or underflows
The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition The TAiS bit is set to "0" (stops counting) Interrupt Request Generation TimingOn the falling edge of the PWM pulse TAiIN Pin Function Programmable I/O port or trigger input TAiOUT Pin Function Pulse output Read from Timer The value in the TAi register is indeterminate when read Write to Timer • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter
While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 161 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer A))T68/C23M,68/C23M(puorG68/C23M Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode) Symbol Address After Reset TA0MR to TA4MR 0356 16, 035716, 035816, 035916, 035A16 00 16 RW RW RW RW RW RW RW RW RW TMOD0 TMOD1 Operating Mode Select Bit Trigger Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit External Trigger Select Bit(1) 16/8-Bit PWM Mode Select Bit 0 : Falling edge of input signal to TAiIN pin 1 : Rising edge of input signal to TAiIN pin 0 : The TAiS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 1 1 : Pulse width modulation (PWM) mode b1b0 Bit Name FunctionBit Symbol b7b6 NOTES: 1. MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (b2) Reserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 101 Figure 15.13 TA0MR to TA4MR Registers

Page 163 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer B))T68/C23M,68/C23M(puorG68/C23M

15.2 Timer B

Figure 15.16 shows a block diagram of the timer B. Figures 15.17 to 15.19 show registers associated with the timer B. The timer B supports the following three modes. The TMOD1 and TMOD0 bits in the TBiMR register (i=0 to 5) determine which mode is used.

Timer mode : The timer counts an internal count source.
Event counter mode : The timer counts pulses from an external source or overflow and underflow of another timer.
Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an external signal. Table 15.8 lists TBi IN pin settings. Figure 15.16 Timer B Block Diagram Figure 15.17 TB0 to TB5 Registers Select Clock Source 01: Event Counter Mode 00: Timer Mode 01: Pulse Period/Pulse Width Measurement Mode Reload Register 8 low-order bits 8 high- order bits Low-order Bits of Data Bus High-order Bits of Data Bus f2n(1) TBj Overflow Signal(2,3) TBiS fc32 Polarity Switching and Edge PulseTBiIN Counter Reset Circuit Counter TBi Address TBj Timer B0 035116 035016 Timer B2 Timer B1 035316 035216 Timer B0 Timer B2 035516 035416 Timer B1 Timer B3 031116 031016 Timer B5 Timer B4 031316 031216 Timer B3 Timer B5 031516 031416 Timer B4 TCK1 and TCK000 TMOD1 and TMOD0 TCK1 i=0 to 5 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. Overflow signal or underflow signal. 3. j=i-1, except j=2 when i=0 j=5 when i=3 TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TBiMR Register TBiS : Bits in the TABSR and the TBSR Register Timer Bi Register(1) (i=0 to 5) Symbol Address After Reset TB0 to TB2 035116 - 035016, 035316 - 035216, 035516 - 035416 Indeterminate TB3 to TB5 031116 - 031016, 031316 - 031216, 031516 - 031416 Indeterminate RW RW RW RO Timer Mode 0000 16 to FFFF16 000016 to FFFF16Event Counter Mode Pulse Period/Pulse Width Measurement Mode Function Setting RangeMode If setting value is n, a count source is divided by n+1 If setting value is n, a count source is divided by n+1(2) A count source is incremented between one valid edge and another valid edge of TBi IN pulse b15 b8 b7 b0 NOTES: 1. Use 16-bit data for reading and writing. 2. The TBi register counts how many pulse inputs are provided externally or how many times another timer counter overflows and underflows.

Page 164 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer B))T68/C23M,68/C23M(puorG68/C23M Figure 15.18 TB0MR to TB5MR Registers, TABSR Register Timer Bi Mode Register (i=0 to 5) Symbol Address After Reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 0000 2 RW RW RW RW RW RW RW RW RW TMOD0 TMOD1 MR0 Operating Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit Function varies depending on operating mode (1, 2) Function varies depending on operating mode 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse width measurement mode 1 1 : Do not set to this value b1b0 Bit Name FunctionBit Symbol NOTES: 1. Only MR2 bits in the TB0MR and TB3MR registers are enabled. 2. Nothing is assigned in the MR2 bit in the TB1MR, TB2MR, TB4MR and TB5MR registers. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Count Start Flag Symbol Address After Reset TABSR 0340 16 00 16 RW RW RW RW RW RW RW RW RW TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag 0 : Stops counting 1 : Starts counting TA2S Timer A2 Count Start Flag 0 : Stops counting 1 : Starts counting TA3S Timer A3 Count Start Flag 0 : Stops counting 1 : Starts counting TA4S Timer A4 Count Start Flag 0 : Stops counting 1 : Starts counting TB0S Timer B0 Count Start Flag 0 : Stops counting 1 : Starts counting TB1S Timer B1 Count Start Flag 0 : Stops counting 1 : Starts counting TB2S Timer B2 Count Start Flag 0 : Stops counting 1 : Starts counting Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0

Page 165 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer B))T68/C23M,68/C23M(puorG68/C23M Timer B3, B4,B5 Count Start Flag Symbol Address After Reset TBSR 0300 16 000X XXXX 2 RW RW RW RW TB3S (b4 - b0) Timer B3 Count Start Flag 0 : Stops counting 1 : Starts counting TB4S Timer B4 Count Start Flag 0 : Stops counting 1 : Starts counting TB5S Timer B5 Count Start Flag 0 : Stops counting 1 : Starts counting Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Figure 15.19 TBSR Register Table 15.8 Settings for the TBiIN Pins (i=0 to 5) PS1_1=0 Port Name P90 PS1, PS3(1) Registers PD7, PD9(1) Registers PD9_0=0 Setting NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" ( write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Function P91 P92 P93 P94 P71 TB0 IN TB1 IN TB2 IN TB3 IN TB4 IN TB5 IN PS3_4=0 PS3_3=0 PS3_2=0 PS3_1=0 PS3_0=0 PD9_1=0 PD9_2=0 PD9_3=0 PD9_4=0 PD7_1=0

Page 166 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer B))T68/C23M,68/C23M(puorG68/C23M

15.2.1 Timer Mode

In timer mode, the timer counts an internally generated count source (see Table 15.9). Figure 15.20 shows the TBiMR register (i=0 to 5) in timer mode. Table 15.9 Timer Mode Specifications Item Specification Count Source f 1, f8, f2n(1), fC32 Counting Operation • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes Divide Ratio 1/(n+1) n: setting value of the TBi register (i=0 to 5) 000016 to FFFF16 Counter Start Condition The TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting) Counter Stop Condition The TBiS bit is set to "0" (stops counting) Interrupt Request Generation TimingTimer counter underflows TBiIN Pin Function Programmable I/O port Read from Timer The TBi register indicates counter value Write to Timer • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter

While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.20 TB0MR to TB5MR Registers Timer Bi Mode Register (i=0 to 5) (Timer Mode) Symbol Address After reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 RW RW RW RW RW RW RW RW RW TMOD0 TMOD1 MR0 Operating Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit TB0MR, TB3MR registers: Set to "0" in timer mode Set to "0" in timer mode Disabled in timer mode. Can be set to "0" or "1". 0 0 : f1 0 1 : f8 1 0 : f2n(1) 1 1 : fC32 0 0 : Timer mode b1b0 Bit Name FunctionBit Symbol b7 b6 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 00 0

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15.2.2 Event Counter Mode

In event counter mode, the timer counts how many external signals are applied or how many times another timer overflows and underflows. (See Table 15.10) Figure 15.21 shows the TBiMR register (i=0 to 5) in event counter mode. Table 15.10 Event Counter Mode Specifications Item Specification Count Source • External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by program)

TBj overflow or underflow signal (j=i-1, except j=2 when i=0, j=5 when i=3) Counting Operation • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register to continue counting Divide Ratio 1/(n+1) n : setting value of the TBi register 000016 to FFFF16 Counter Start Condition The TBiS bits in the TABSR and TBSR register are set to "1" (starts counting) Counter Stop Condition The TBiS bit is set to "0" (stops counting) Interrupt Request Generation TimingThe timer counter underflows TBiIN Pin Function Programmable I/O port or count source input Read from Timer The TBi register indicates counter value Write to Timer • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter
While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing)

Page 168 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer B))T68/C23M,68/C23M(puorG68/C23M Timer Bi Mode Register (i=0 to 5) (Event Counter Mode) Symbol Address After reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 RW RW RW RW RW RW RW RW TMOD0 TMOD1 MR0 Operating Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Event Clock Select Bit 0 : Input signal from the TBiIN pin 1 : TBj overflows or underflows(2) TB0MR and TB3MR registers: Set to "0" in event counter mode Disabled in event counter mode. When write, set to "0". When read, its content is indeterminate. Disabled in event counter mode. Can be set to "0" or "1". Count Polarity Select Bit (1) 0 1 : Event counter mode b1b0 Bit Name FunctionBit Symbol 0 0 : Counts falling edges of external signal 0 1 : Counts rising edges of external signal 1 0 : Counts falling and rising edges of external signal 1 1 : Do not set to this value b3b2 NOTES: 1. MR0 and MR1 bit settings are enabled when the TCK1 bit is set to "0". The MR1 bit can be set to either "0" or "1", when the TCK1 bit is set to "1". 2. j = i-1, except j = 2 when i = 0 and j = 5 when i = 3. TB1MR, TB2MR, TB4MR and TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 00 1 Figure 15.21 TB0MR to TB5MR Registers

Page 169 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer B))T68/C23M,68/C23M(puorG68/C23M

15.2.3 Pulse Period/Pulse Width Measurement Mode

In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. (See Table 15.11) Figure 15.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse width measurement mode. Figure 15.23 shows an operation example in pulse period measurement mode. Figure 15.24 shows an operation example in the pulse width measurement mode. Table 15.11 Pulse Period/Pulse Width Measurement Mode Specifications Item Specification Count Source f 1, f8, f2n(3), fC32 Counting Operation • The timer increments a counter value Counter value is transferred to the reload register on the valid edge of a pulse to be measured. It is set to "000016" and the timer continues counting Counter Start Condition The TBiS bits (i=0 to 5) in the TABSR and TBSR register are set to "1" (starts counting) Counter Stop Condition The TBiS bit is set to "0" (stops counting) Interrupt Request Generation Timing• On the valid edge of a pulse to be measured(1)

The timer counter overflows The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the TBiS bit is set to "1" (start counting) and the next count source is counted after setting the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to the TBiMR register. TBiIN Pin Function Input for a pulse to be measured Read from Timer The TBi register indicates reload register values (measurement results)(2) Write to Timer Value written to the TBi register can be written to neither reload register nor counter NOTES: 1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the timer has started counting. 2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid edge after the timer has started counting. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 170 974fo5002,80.peS00.1.veR 0010-4020B90JER 15. Timer (Timer B))T68/C23M,68/C23M(puorG68/C23M Timer Bi Mode Register (i=0 to 5) (Pulse Period / Pulse Width Measurement Mode) Symbol Address After reset TB0MR to TB5MR 035B 16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 RW RW RW RW RW RW RW RO RW TMOD0 TMOD1 MR0 Operating Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Count Source Select Bit 0 0 : f1 0 1 : f8 1 0 : f2n(3) 1 1 : fC32 TB0MR, TB3MR registers: Set to "0" in pulse period/pulse width measurement mode Timer Bi Overflow Flag(2) 0 : No overflow 1 : Overflow Measurement Mode Select Bit (1) 1 0 : Pulse period measurement mode, Pulse width measurement mode b1b0 Bit Name FunctionBit Symbol 0 0 : Pulse period measurement 1 0 1 : Pulse period measurement 2 1 0 : Pulse width measurement 1 1 : Do not set to this value b3b2 b7b6 NOTES: 1. The MR1 and MR0 bits selects the following measurements. Pulse period measurement 1 (the MR1 and MR0 bits are set to "00 2") : Measures between the falling edge and the next falling edge of a pulse to be measured Pulse period measurement 2 (the MR1 and MR0 bits are set to "01 2") : Measures between the rising edge and the next rising edge of a pulse to be measured Pulse width measurement (the MR1 and MR0 bits are set to "10 2") : Measures between a falling edge and the next rising edge of a pulse to be measured and between the rising edge and the next falling edge of a pulse to be measured 2. The MR3 bit is indeterminate when reset. To set the MR3 bit to "0", se the TBiMR register after the MR3 bit is set to "1" and one or more cycles of the count source are counted, while the TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting). The MR3 bit cannot be set to "1" by program. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Figure 15.22 TB0MR to TB5MR Registers

Page 172 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M 16. Three-Phase Motor Control Timer Functions Three-phase motor driving waveform can be output by using the timers A1, A2, A4 and B2. Table 16.1 lists specifications of the three-phase motor control timer functions. Table 16.2 lists pin settings. Figure 16.1 shows a block diagram. Figures 16.2 to 16.7 show registers associated with the three-phase motor control timer functions. Table 16.1 Three-Phase Motor Control Timer Functions Specification Item Specification Three-Phase Waveform Output Pin Six pins (U, U, V, V, W, W) Forced Cutoff(1) Apply a low-level ("L") signal to the NMI pin Timers to be Used Timer A4, A1, A2 (used in one-shot timer mode): ___ Timer A4: U- and U-phase waveform control ___ Timer A1: V- and V-phase waveform control ___ Timer A2: W- and W-phase waveform control Timer B2 (used in timer mode): Carrier wave cycle control Dead time timer (three 8-bit timers share reload register): Dead time control Output Waveform Triangular wave modulation, Sawtooth wave modulation Can output a high-level waveform or a low-level waveform for one cycle; Can set positive-phase level and negative-phase level separately Carrier Wave Cycle Triangular wave modulation: count source x (m+1) x 2 Sawtooth wave modulation: count source x (m+1) m : setting value of the TB2 register, 000016 to FFFF16 Count source: f1, f8, f2n(2), fc32 Three-Phase PWM Output Width Triangular wave modulation: count source x n x 2 Sawtooth wave modulation: count source x n n : setting value of the TA4, TA1 and TA2 register (of the TA4, TA41, TA1, TA11, TA2 and TA21 registers when setting the INV11 bit to "1"), 000116 to FFFF16 Count source: f1, f8, f2n(2), fc32 Dead Time Count source x p, or no dead time p: setting value of the DTT register, 0116 to FF16 Count source: f1, or f1 divided by 2 Active Level Selected from a high level ("H") or low level ("L") Positive- and Negative-Phase Con- Positive and negative-phases concurrent active disable function current Active Disable Function Positive and negative-phases concurrent active detect function Interrupt Frequency For the timer B2 interrupt, one carrier wave cycle-to-cycle basis through 15 time- carrier wave cycle-to-cycle basis can be selected NOTES: 1. Forced cutoff by the signal applied to the NMI pin is available when the INV02 bit is set to "1" (three- phase motor control timer functions) and the INV03 bit is set to "1" (three-phase motor control timer output enabled). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 173 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M PS1_2 =1 Pin P72/V PS1_3 =1 PS1, PS2 Registers(1) PS1_4 =1 PS1_5 =1 PS2_0 =1 PSL1, PSL2 Registers PSL1_2 =0 PSL1_3 =1 PSL1_4 =1 PSL1_5 =0 PSL2_0 =1 Setting PSC Register PSC_2 =1 NOTES: 1. Set the PS1_5 to PS1_2 bits and PS2_1 and PS2_0 bits in the PS1 and PS2 registers to "1" after the INV02 bit is set to "1". P73/V P74/W P75/W P80/U P81/U PS2_1 =1 PSL2_1 =0 PSC_3 =0 PSC_4 =0 Table 16.2 Pin Settings

Page 174 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M DUB1bit Timer B2(Timer Mode) Timer B2 Underflow ICTB2 Counter Interrupt Request Bit U U V V W W NMI RESET RD D T Q D T Q D T Q D T Q D T Q D T Q Q INV03 INV05 INV04 Timer A4 Counter (One-Shot Timer Mode) (One-Shot Timer Mode) (One-Shot Timer Mode) Trigger TA4 Register Reload TA41 Register Timer A1 Counter TriggerTA1 Register Reload TA11 Register Timer A2 Counter TriggerTA2 Register Reload TA21 RegisterINV07 T Q INV11 Dead Time Timer INV00 1 0 INV01INV11 DU0 bit DU1 bitT DQ T DQ DUB0bit T DQ T DQ U-Phase Output Control Circuit U-Phase Output SignalU-Phase Output Signal V-Phase Output Control Circuit When setting the TA4S bit to "0", signal is set to "0" T Q INV11 T Q INV11 W-Phase Output Control Circuit V-Phase Output Signal W-Phase Output Signal V-Phase Output Signal W-Phase Output Signal Write Signal to Timer B2 Start Trigger Signal for Timers A1, A2, A4 Transfer Trigger (1) INV10 Circuit to set Interrupt Generating Frequency Three-Phase Output Shift Register (U Phase) /LiteDiagLines 0 1 n=1 to 15 Reload Register Dead Time Timer n = 1 to 255 Dead Time Timer n = 1 to 255 n = 1 to 255 Trigger INV06 Trigger TriggerTrigger TriggerTrigger INV06 INV06 INV14 INV13 ICTB2 Register n=1 to 15 Timer B2 n = 1 to 255 INV12 Reload Control Signal for Timer A4 When setting the TA1S bit to "0", signal is set to "0" When setting the TA2S bit to "0", signal is set to "0" INV07 to INV00: Bits in INVC0 RegisterINV15 to INV10: Bits in INVC1 RegisterDUi, DUBi: Bits in IDBi Register (i=0,1)TA4S to TA1S: Bits in TABSR Register Switching to P8 0, P8 1 and P7 2 to P7 5 is not shown in this diagram. NOTES: 1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 counter underflows, if the INV06 bit is set to "0" (triangular wave modulation mode). InverseControl InverseControl InverseControlInverseControl InverseControl InverseControl Timer A4One-Shot Pulse Value to be written to INV03 bit Write signal to INV03 bit T INV02 PWCON Figure 16.1 Three-Phase Motor Control Timer Functions Block Diagram

Page 175 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M Figure 16.2 INVC0 Register INV00 INV01 INV02 INV03 INV05 INV06 INV07 INV04 Function Three-Phase PWM Control Register 0(1) Bit NameBit Symbol Symbol Address After Reset INVC0 0308 16 00 16 RW RW RW RW RW RW RW RW RW Item INV06 = 0 INV06 = 1 Transfer trigger is generated when the INV07 bit is set to "1". Trigger to the dead time timer is also generated when setting the INV06 bit to "1". Its value is "0" when read. NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). Rewrite the INV02 to INV00 and INV06 bits when the timers A1,A2, A4 and B2 stop. 2. Set the INV01 bit to "1" after setting the ICTB2 register. The INV01 and INV00 bit settings are enabled only when the INV11 bit in the INVC1 register is set to "1" (three-phase mode 1). The ICTB2 counter is incremented by one every time the timer B2 counter underflows, regardless of INV01 and INV00bit settings, when the INV11 bit is set to "0" (three-phase mode). When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflows. When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. 4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2 counter. 5. Set pins after the INV02 bit is set to "1". See Table 16.2 for pin settings. 6. When the INV02 bit is set to "1" and the INV03 bit to "0", the U, U, V, V, W and W pins, including pins shared with other output functions, are all placed in high-impedance states. 7. The INV03 bit is set to "0" when the followings occurs : - Reset - A concurrent active state occurs while the INV04 bit is set to "1" - The INV03 bit is set to "0" by program - An "H" signal applied to the NMI pin changes to an "L" signal 8. The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit to "0". 9. The following table describes how the INV06 bit setting works. Transfer trigger : Timer B2 counter underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1 0: The ICTB2 counter is incremented by one on the rising edge of the timer A1 reload control signal 1: The ICTB2 counter is incremented by one on the falling edge of the timer A1 reload control signal 0: ICTB2 counter is incremented by one when timer B2 counter underflows 1: Selected by the INV00 bit 10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the TB2SC register to "0" (timer B2 counter underflows). Transferred once by generating a transfer trigger after setting the IDB0 and IDB1 registers Interrupt Enable Output Polarity Select Bit (3) Interrupt Enable Output Specification Bit(2, 3) Mode Select Bit(4, 5, 6) 0: No three-phase control timer function 1: Three-phase control timer function 0: Disables three-phase control timer output 1: Enables three-phase control timer outputOutput Control Bit(6, 7) 0: Enables concurrent active output 1: Disables concurrent active output Positive and Negative- Phases Concurrent Active Disable Function Enable Bit Positive and Negative- Phases Concurrent Active Output Detect Flag (8) 0: Not detected 1: Detected Modulation Mode Select(9, 10) 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode Software Trigger Select Transferred every time a transfer trigger is generated By a transfer trigger, or the falling edge of a one-shot pulse of the timer A1, A2 or A4 On the falling edge of a one-shot pulse of the timer A1, A2 or A4 Timing to Trigger the Dead Time Timer when the INV16 Bit=0 INV13 Bit Enabled when the INV11 bit=1 and the INV06 bit=0 Disabled Timing to Transfer from the IDB0 and IDB1 Registers to Three- Phase Output Shift Register Mode Triangular wave modulation mode Sawtooth wave modulation mode b7 b6 b5 b4 b3 b2 b1 b0

Page 176 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M INV10 INV11 INV12 INV13 INV15 INV14 Function Three-Phase PWM Control Register 1(1) Timer A1, A2 and A4 Start Trigger Select Bit Carrier Wave Detect Flag(4) Dead Time Timer Trigger Select Bit Output Polarity Control Bit 0: Timer A1 reload control signal is "0" 1: Timer A1 reload control signal is "1" Timer A1-1, A2-1 and A4-1 Control Bit (2, 3) 0: Three-phase mode 0 1: Three-phase mode 1 Dead Time Timer Count Source Select Bit 0 : f 1 : f1 divided-by-2 0: Timer B2 counter underflows 1: Timer B2 counter underflows and write to the TB2 register 0 : Active "L" of an output waveform 1 : Active "H" of an output waveform Dead Time Disable Bit 0: Enables dead time 1: Disables dead time Bit NameBit Symbol Symbol Address After Reset INVC1 0309 16 00 16 RW RW RW RW RO RW RW RW Reserved Bit Set to "0" RW NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). The timers A1, A2, A4, and B2 must be stopped during rewrite. 2. The following table lists how the INV11 bit setting works. 3. When the INV06 bit in the INVC0 registser is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0". Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0" (Timer B2 counter underflows). 4. The INV13 bit setting is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and the INV11 bit to "1". 5. If the following conditions are all met, set the INV16 bit to "1".

The INV15 bit is set to "0"
The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit in the INVC0 register is set to "1". (The positive-phase and negative-phase outputs always provide opposite level signals.) If the above conditions are not met, set the INV16 bit to "0". 0: Falling edge of a one-shot pulse of the timer A1, A2 and A4 (5) 1: Rising edge of the three-phase output shift register (U-, V-, W-phase) INV16 (b7) b7 b6 b5 b4 b3 b2 b1 b0 TA11, TA21 and TA41 RegistersNot used Used INV13 Bit Disabled Enabled Item Mode INV11 = 0 INV11 = 1 Three-phase mode 0 Three-phase mode 1 Disabled. The ICTB2 counter is incremented whenever the timer B2 counter underflows Enabled when INV11=1 and INV06=0 INV01 and INV00 Bit in the INVC0 Register Figure 16.3 INVC1 Register

Page 177 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M Three-Phase Output Buffer Register i(1) (i=0, 1) Symbol Address After Reset IDB0, IDB1 030A16, 030B16 XX11 1111 2 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RO Bit NameBit Symbol DUi DUBi DVi U-Phase Output Buffer i DVBi DWi DWBi (b7 - b6) Function Write output level 0: Active level 1: Inactive level When read, the value of the three- phase shift register is read. U-Phase Output Buffer i V-Phase Output Buffer i V-Phase Output Buffer i W-Phase Output Buffer i W-Phase Output Buffer i NOTES: 1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger. After the transfer trigger occurs, the values written in the IDB0 register determine each phase output signal level first. Then the value written in the IDB1 register on the falling edge of the timers A1, A2 and A4 one-shot pulse determines each phase output signal level. Reserved Bit When read, its content is indeterminate Dead Time Timer(1, 2) Symbol Address After Reset DTT 030C 16 Indeterminate RW WO Function Setting Range 1 to 255 If setting value is n, the timer stops when counting n times a count source selected by the INV12 bit after start trigger occurs. Positive or negative phase, which changes from inactive level to active level, shifts when the dead time timer stops. NOTES: 1. Use the MOV instruction to set the DTT register. 2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06 bit in the INVC0 register determines start trigger of the DTT register. Figure 16.4 IDB0 and IDB1 registers, DTT Register

Page 178 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M Timer B2 Interrupt Generation Frequency Set Counter(1, 2, 3) Symbol Address After Reset ICTB2 030D 16 Indeterminate b7 b0 RW WO Function Setting Range 1 to 15 Nothing is assigned. When write, set to "0". When the INV01 bit is set to "0" (the ICTB2 counter increments whenever the timer B2 counter underflows) and the setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow occurs. When the INV01 bit is set to "1" (the INV00 bit selects count timing of the ICTB2 counter) and setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow meeting the condition selected in the INV00 bit occurs. NOTES: 1. Use the MOV instruction to set the ICTB2 register. 2. If the INV01 bit in the INVC0 register is set to "1", set the ICTB2 register in the TABSR register when the TB2S bit is set to "0" (timer B2 counter stopped). If the INV01 bit is set to "0" and the TB2S bit to "1" (timer B2 counter start), do not set the ICTB2 register when the timer B2 counter underflows. 3. If the INV00 bit in the INVC0 register is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, n being the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. Timer Ai, Ai-1 Register (i=1, 2, 4)(1, 2, 3, 4, 5, 6) Symbol Address After Reset TA1, TA2, TA4 0349 16 - 034816, 034B16 - 034A16, 034F16 - 034E16 Indeterminate TA11, TA21, TA41 030316 - 030216, 030516 - 030416, 030716 - 030616 Indeterminate RW WO Function b0b8 Setting Range 000016 to FFFF16 b15 b7 If setting value is n, the timer stops when the nth count source is counted after a start trigger is generated. Positive phase changes to negative phase, and vice versa, when the timers A1, A2 and A4 stop. NOTES: 1. Use a 16-bit data for read and write. 2. If the TAi or TAi1 register is set to "0000 16", no counter starts and no timer Ai interrupt is generated. 3. Use the MOV instruction to set the TAi and TAi1 registers. 4. When the INV15 bit in the INVC1 register is set to "0" (dead timer enabled), phase switches from an inactive level to an active level when the dead time timer stops. 5. When the INV11 bit in the INVC1 register is set to "0" (three-phase mode 0), the value of the TAi register is transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to "1" (three-phase mode 1), the value of the TAi1 register is first transferred to the reload register by a timer Ai start trigger. Then, the value of the TAi register is transferred by the next trigger. The values of the TAi1 and TAi registers are transferred alternately to the reload register with every timer Ai start trigger. 6. Do not write to these registers when the timer B2 counter underflows. Timer B2 Special Mode Register Symbol Address After Reset TB2SC 035E 16 XXXX XXX0 2 RW RW Bit Name FunctionBit Symbol PWCON Timer B2 Reload Timing Switching Bit(1) 0 : Timer B2 counter underflows 1 : Timer A output in odd-number times Nothing is assigned. When write, set to "0". When read, its content is "0." b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Set the PWCON bit to "0" when setting the INV11 bit to "0" (three-phase mode 0) or the INV06 bit to "1" (sawtooth wave modulation mode). Figure 16.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers, TB2SC Register

Page 179 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M Timer B2 Register(1) Symbol Address After Reset TB2 0355 16 - 035416 Indeterminate RW RW Function b0b8 Setting Range If setting value is n, count source is divided by n+1. The timers A1, A2 and A4 start every time an underflow occurs.000016 to FFFF16 NOTES: 1. Use a 16-bit data for read and write. b15 b7 Trigger Select Register Symbol Address After Reset TRGSR 0343 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Bit NameBit Symbol TA1TGL TA1TGH TA2TGL Timer A1 Event/Trigger Select Bit TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH Function Set to "012" (TB2 underflow) before using a V-phase output control circuit Timer A2 Event/Trigger Select Bit Set to "012" (TB2 underflow) before using a W-phase output control circuit : Selects an input to the TA3IN pin : Selects TB2 overflow(1) : Selects TA2 overflow(1) : Selects TA4 overflow(1) Timer A3 Event/Trigger Select Bit Timer A4 Event/Trigger Select Bit Set to "012" (TB2 underflow) before using a U-phase output control circuit NOTES: 1. Overflow or underflow Count Start Flag Symbol Address After Reset TABSR 0340 16 00 16 RW RW RW RW RW Bit Name FunctionBit Symbol TA0S TA1S TA2S Timer A0 Count Start Flag TA3S RW RW RW RW TA4S TB0S TB1S TB2S 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag b6 b5 b3 b2 b1b4b7 b0 Figure 16.6 TB2, TRGSR and TABSR Registers

Page 180 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M Timer Ai Mode Register (i=1, 2, 4) Symbol Address After Reset TA1MR, TA2MR, TA4MR 035716, 035816, 035A16 0016 RW RW RW RW Bit Name FunctionBit Symbol TMOD0 TMOD1 MR0 Operating Mode Select Bit MR1 RW RW RW RW MR2 MR3 TCK0 TCK1 Set to "102" (one-shot timer mode) when using the three-phase motor control timer function Set to "0" when using the three-phase motor control timer function Set to "1" (selected by the TRGSR register) when using the three- phase motor control timer function : f : f8 : f2n(1) : fC32 External Trigger Select Bit Trigger Select Bit Set to "0" with the three-phase motor control timer function Count Source Select Bit NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Reserved Bit Set to "0" b6 b5 b3 b2 b1b4b7 b0 1100 00 Timer B2 Mode Register Symbol Address After Reset TB2MR 035D 16 00XX 00002 RW RW RW Bit Name FunctionBit Symbol TMOD0 TMOD1 MR0 Operating Mode Select Bit MR1 RW RW RW MR2 MR3 TCK0 TCK1 Set to "002" (timer mode) when using the three-phase motor control timer function : f : f8 : f2n(1) : fC32 Disabled when using the three-phase motor control timer function. When write, set to "0". When read, its content is indeterminate. Set to "0" when using three-phase motor control timer function Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Count Source Select Bit NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). b6 b5 b3 b2 b1b4b7 b0 00 000 Figure 16.7 TA1MR, TA2MR and TA4MR Registers, TB2MR Register

Page 181 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M The three-phase motor control timer function is available by setting the INV02 bit in the INVC0 register to "1". The timer B2 is used for carrier wave control and the timers A1, A2, A4 for three-phase PWM output (U, U, V, V, W, W) control. An exclusive dead time timer controls dead time. Figure 16.8 shows an example of the triangular modulation waveform. Figure 16.9 shows an example of the sawtooth modula- tion waveform. Figure 16.8 Triangular Wave Modulation Operation m m m nn p p p m m q q qm n n n n n p p q qp q r r r TA4 Register(2) TA4-1 Register(2) Reload Register(2) Timer A1 Reload Control Signal(1) Triangular Wave Signal Wave Triangular waveform as a Carrier Wave Timer B2 TB2S Bit in TABSR Register Timer A4 Start Trigger Signal(1) Timer A4 One-Shot Pulse (1) Rewrite the IDB0 and IDB1 registers Transfer the values to the three-phase shift register U-Phase Output Signal(1) U-Phase Output Signal (1) INV14 = 0 ("L" active) U-Phase Dead time Dead timeINV14 = 1 ("H" active) U-Phase U-Phase NOTES: 1. Internal signals. See Figure 16.1. 2. Applies only when the INV11 bit is set to "1" (three-phase mode). Examples of PWM output change are (a) When INV11=1 (three-phase mode 1) - INV01=0 and ICTB2=2 16 (The timer B2 interrupt is generated with every second timer B2 underflow) or INV01=1, INV00=1and ICTB2=1 16 (The timer B2 interrupt is generated on the falling edge of the timer A reload control signal) - Default value of the timer: TA41=m, TA4=m The TA4 and TA41 registers are changed whenever the timer B2 interrupt is generated. First time: TA41=n, TA4:=n. Second time: TA41=p, TA4=p. - Default value of the IDB0 and IDB1 registers DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the third timer B2 interrupt. (b) When INV11=0 (three-phase mode 0) - INV01=0, ICTB2=1 16 (The timer B2 interrupt is generated whenever the timer B2 underflows) - Default value of the timer: TA4=m The TA4 register is changed whenever the timer B2 interrupt is generated. First time: TA4=m. Second time: TA4=n. Third time: TA4=n. Fourth time: TA=p. Fifth time: TA4=p. - Default value of the IDB0 and IDB1 registers: DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the sixth timer B2 interrupt. The above applies to INVC0 = 00XX11XX 2 and INVC1 = 010XXXX02 (X varies depending on each system.) INV00, INV01: Bits in INVC0 register INV11, INV14: Bits in INVC1 register U-Phase

Page 182 974fo5002,80.peS00.1.veR 0010-4020B90JER 16. Three-Phase Motor Control Timer Functions)T68/C23M,68/C23M(puorG68/C23M Figure 16.9 Sawtooth Wave Modulation Operation Timer B2 U-Phase Sawtooth Wave Signal Wave U-Phase Output Signal(1) U-Phase Output Signal (1) INV14 = 0 ("L" active) Sawtooth Waveform as a Carrier Wave NOTES: 1. Internal signals. See Figure 16.1. The examples of PWM output change are - Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt. The above applies to INVC0 = 01XX110X 2 and INVC1 = 000XXX002 (X varies depending on each system.) INV14 = 1 ("H" active) U-Phase U-Phase U-Phase Dead time Dead time Timer A4 One-Shot Pulse (1) Timer A4 Start Trigger Signal(1) INV14: Bits in INVC1 register Rewrite the IDB0 and IDB1 registers Transfer the register values to the three-phase shift register

Page 183 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M 17. Serial I/O Serial I/O consists of five channels (UART0 to UART4). Each UARTi (i=0 to 4) has an exclusive timer to generate the transfer clock and operates independently. Figure 17.1 shows a UARTi block diagram. UARTi supports the following modes : - Clock synchronous serial I/O mode - Clock asynchronous serial I/O mode (UART mode) - Special mode 1 (I 2C mode) - Special mode 2 - Special mode 3 (Clock-divided synchronous function, GCI mode) - Special mode 4 (Bus conflict detect function, IE mode) - Special mode 5 (SIM mode) Figures 17.2 to 17.9 show registers associated with UARTi. Refer to the tables listing each mode for register and pin settings.

Page 184 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M m : setting value of UiBRG register RxDi Receive Control Circuit Transmit Control Circuit 1 / (m+1) UiBRG Register Clock Synchronous (when internal clock is selected) Clock Asynchronous Receive Clock Synchronous Clock Synchronous Clock Synchronous (when internal clock is selected) Clock Synchronous (when external clock is selected) Receive Clock Transmit Clock CLKi CTSi / RTSi f2n(2) VSS CTSi TxDiRxD Polarity Switching Circuit TxD Polarity Switching Circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK Polarity Switching Circuit CKDIR Internal External Selecting Clock Source Transmit/ Receive Unit (Note 1) NOTES: 1. P70 and P71 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). CKPOL CLK1 and CLK0 010, 100, 101, 110 010, 100, 101, 110 001 001 Clock Asynchronous Transmit SMD2 to SMD0 CKDIR CRD CRD RTSi CRS 0 8-bit Clock Asynchronous Clock Synchronous 7-bit Clock Asynchronous SP SP PAR Clock Synchronous Clock Synchronous Low-order bits of data bus TxDi UARTi Transmit RegisterPAR disabled PAR enabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 UiTB Register Clock Synchronous UiRB Register UARTi Receive Register 2SP 1SP RxDi D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 8000 0000 SP SP PAR Inverse No inverse Error Signal Output Circuit RxD Data Inverse Circuit Error Signal Output enable Error Signal Output disable Inverse No inverse Logic Inverse Circuit + MSB/LSB Conversion Circuit Logic Inverse Circuit + MSB/LSB Conversion Circuit PAR enabled PAR disabled Clock Synchronous TxD Data Inverse CircuitSP: Stop bit PAR: Parity bit i=0 to 4 SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in the UiMR register CLK1 and CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register UiERE: Bit in the UiC1 register IOPOL PRYE 9-bit Clock Asynchronous Clock Synchronous 8-bit Clock Asynchronous Clock Asynchronous 9-bit Clock Asynchronous Type 7-bit Clock Asynchronous 1 11 SMD2 to SMD0 STPS 7-bit Clock Asynchronous 8-bit Clock Asynchronous 8-bit Clock Asynchronous 9-bit Clock Asynchronous 7-bit Clock Asynchronous1SP 2SP STPS PRYE Clock Asynchronous 9-bit Clock Asynchronous 1 1 IOPOL UiERE High-order bits of data bus SMD2 to SMD0 Figure 17.1 UARTi Block Diagram

Page 185 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M UARTi Transmit Buffer Register (i=0 to 4)(1) Symbol Address After Reset U0TB to U2TB 036B 16-036A16, 02EB16-02EA 16, 033B16-033A16 Indeterminate U3TB, U4TB 032B 16-032A16, 02FB16-02FA16 Indeterminate RW Transmit data (D7 to D0) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Transmit data (D8) NOTES: 1. Use the MOV instruction to set the UiTB register. WO WO (b15 - b9) (b7 - b0) (b8) Function b7 b0b15 b8 Bit Symbol UARTi Receive Buffer Register (i=0 to 4) Bit NameBit Symbol Symbol Address After Reset U0RB to U2RB 036F 16 - 036E16, 02EF 16 - 02EE 16, 033F16 - 033E16 Indeterminate U3RB, U4RB 032F 16 - 032E16, 02FF16 - 02FE 16 Indeterminate RW Received data (D7 to D0) ABT (b10 - b9) (b7 - b0) (b8) OER FER SUM PER Function Overrun Error Flag(2) Arbitration Lost Detect Flag(1) Framing Error Flag(2, 3) Parity Error Flag(2, 3) Error Sum Flag(2, 3) Received data (D8) 0: Not detected (win) 1: Detected (lose) 0: No overrun error occurs 1: Overrun error occurs 0: No framing error occurs 1: Framing error occurs 0: No parity error occurs 1: Parity error occurs 0: No error occurs 1: Error occurs RW RO RO RO RO RO RO NOTES: 1. The ABT bit can be set to "0" only. 2. When the SMD2 to SMD0 bits in the UiMR register are set to "000 2" (serial I/O disable) or the RE bit in the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0". When all OER, FER and PER bits are set to "0", the SUM bit is set to "0". Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register. 3. These error flags are disabled when the SMD2 to SMD0 bits are set to "001 2" (clock synchronous serial I/O mode) or to "0102" (I2C mode). When read, the contents are indeterminate. b7 b0b15 b8 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Figure 17.2 U0TB to U4TB Registers and U0RB to U4RB Registers

Page 186 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M Function UARTi Bit Rate Register (i=0 to 4)(1, 2) Setting Range Symbol Address After Reset U0BRG to U4BRG 0369 16, 02E916, 033916, 032916, 02F916 Indeterminate If the setting value is m , the UiBRG register divides a count source by m+1 RW 0016 to FF16 NOTES: 1. Use the MOV instruction to set the UiBRG register. 2. Set the UiBRG register while no data transfer occurs. WO b7 b0 UARTi Transmit/Receive Mode Register (i=0 to 4) Symbol Address After Reset U0MR to U4MR 036816, 02E816, 033816, 032816, 02F816 0016 RW CKDIR STPS PRY IOPOL PRYE SMD0 SMD2 SMD1 Serial I/O Mode Select Bit Internal/External Clock Select Bit Stop Bit Length Select Bit Odd/Even Parity Select Bit Parity Enable Bit TxD,RxD Input/Output Polarity Switch Bit 0 0 0: Serial I/O disabled 0 0 1: Clock synchronous serial I/O mode 0 1 0: I 2C mode 1 0 0: UART mode, 7-bit transfer data 1 0 1: UART mode, 8-bit transfer data 1 1 0: UART mode, 9-bit transfer data b2 b1 b0 0: Not inversed 1: Inverse 0 : 1 stop bit 1 : 2 stop bits Enables when PRYE = 1 0 : Odd parity 1 : Even parity 0 : Disables a parity 1 : Enables a parity 0 : Internal clock 1 : External clock Bit Name Bit Symbol Do not set value other than the above RW RW RW RW RW RW RW RW Function b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.3 U0BRG to U4BRG Registers and U0MR to U4MR Registers

Page 187 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M UARTi Transmit/Receive Control Register 0 (i=0 to 4) Symbol Address After Reset U0C0 to U4C0 036C 16, 02EC 16, 033C 16, 032C 16, 02FC 16 0000 1000 2 RO RW TXEPT CRD NCH UFORM CKPOL b0b1 CLK0 CRS CLK1 UiBRG Count Source Select Bit CST/RTS Function Select Bit Transmit Register Empty Flag CTS/RTS Disable Bit Data Output Select Bit(1) CLK Polarity Select Bit Transfer Format Select Bit (3) Enabled when CRD=0 0 : Selects CTS function 1 : Selects RTS function 0 0: Selects f 0 1: Selects f8 1 0: Selects f2n(2) 1 1: Do not set to this value 0 : Data in the transmit register (during transmission) 1 : No data in the transmit register (transmission is completed) 0 : Enables CTS/RTS function 1 : Disables CTS/RTS function 0 : TxDi/SDAi and SCLi are ports for the CMOS output 1 : TxDi/SDAi and SCLi are ports for the N-channel open drain output 0 : LSB first 1 : MSB first Bit NameBit Symbol Function RW RW RW RW RW RW RW NOTES: 1. P7 0/TxD2 and P71/SCL2 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 3. The UFORM bit setting is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001 2" (clock syncronous serial I/O mode) or "1012" (UART mode, 8-bit transfer data). Set the UFORM bit to "1" when setting the SMD2 to SMD0 bits to"0102" (I2C mode), or to "0" when setting them to "1002" (UART mode, 7-bit transfer data) or "1102" (UART mode, 9-bit transfer data). 0 : Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge 1 : Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.4 U0C0 to U4C0 Registers

Page 188 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M UARTi Transmit/Receive Control Register 1 (i=0 to 4) Symbol Address After Reset U0C1 to U4C1 036D 16, 02ED 16, 033D 16, 032D 16, 02FD 16 0000 00102 RW RW RI UiIRS UiRRM UiLCH TE RE TI Transmit Enable Bit Transmit Buffer Empty Flag Receive Enable Bit Receive Complete Flag Clock-Divided Synchronous Stop Bit / E rror Signal Output Enable Bit (1) SCLKSTPB /UiERE UARTi Transmit Interrupt Cause Select Bit UARTi Continuous Receive Mode Enable Bit Data Logic Select Bit (2) 0: Transmit disable 1: Transmit enable 0: Data in the UiTB register 1: No data in the UiTB register 0: Receive disable 1: Receive enable 0: No data in the UiRB register 1: Data in the UiRB register 0: No data in the UiTB register (TI = 1) 1: Transmission is completed (TXEPT = 1) Disables continuous receive mode to be entered 1: Enables continuous receive mode to be entered 0: Not inversed 1: Inverse Clock-divided synchronous stop bit (special mode 3) 0: Stops synchronizing 1: Starts synchronizing Error signal output enable bit (special mode 5) 0: Not output 1: Output Bit Name Bit Symbol RO RW RO RW RW RW RW Function NOTES: 1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register. 2. The UiLCH bit setting is enabled when setting the SMD2 to SMD0 bits to "001 2" (clock syncronous serial I/O mode), "1002" (UART mode, 7-bit transfer data) or "1012" (UART mode, 8-bit transfer data). Set the UiLCH bit to "0" when setting the SMD2 to SMD0 bits to"0102" (I2C mode) or "1102" (UART mode, 9-bit transfer data). b7 b6 b5 b4 b3 b2 b1 b0 UARTi Special Mode Register (i=0 to 4) Symbol Address After Reset U0SMR to U4SMR 036716, 02E716, 033716, 032716, 02F716 0016 RW RW LSYN ABSCS ACSE SSS IICM BBS ABC 0: Except I2C mode 1: I2C mode 0: Update per bit 1: Update per byte 0: Stop condition detected 1: Start condition detected (Busy) 0: Disabled 1: Enabled 0: Not related to RxDi 1: Synchronized with RxDi 0: Rising edge of transfer clock 1: Timer Aj underflow(j=0 to 4)(2) Bit Name Bit Symbol I2C Mode Select Bit Bus Busy Flag NOTES: 1. The BBS bit is set to "0" by program. It is unchanged if set to "1". 2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal, UART3: timer A3 underflow signal, UART4: timer A4 underflow signal. 3. Refer to notes for the SU1HIM bit in the UiSMR2 register. Auto Clear Function Select Bit for Transmit Enable Bit SCLL Sync Output Enable Bit Arbitration Lost Detect Flag Control Bit Bus Conflict Detect Sampling Clock Select Bit Transmit Start Condition Select Bit 0: No auto clear function 1: Auto clear at bus conflict SCLKDIV Clock Divide Synchronous Bit (Note 3) RW RW (1) RW RW RW RW RW Function b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers

Page 189 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M UARTi Special Mode Register 2 (i=0 to 4) Symbol Address After Reset U0SMR2 to U4SMR2 036616, 02E616, 033616, 032616, 02F616 0016 RW IICM2 CSC Clock Synchronous Bit I2C Mode Select Bit 2 0: Output 1: No output (high-impedance) Bit NameBit Symbol Function ALS STC SWC2 SDHI SWC SCL Wait Output Bit SDA Output Stop Bit UARTi Initialize Bit SCL Wait Output Bit 2 SDA Output Inhibit Bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Output 1: No output 0: Disabled 1: Enabled 0: Transfer clock 1: "L" output SU1HIM External Clock Synchronous Enable Bit RW RW RW RW RW RW RW RW NOTES: 1. Refer to Table 17.14. 2. The external clock synchronous function can be selected by combining the SU1HIM bit and the SCLKDIV bit in the UiSMR register. SCLKDIV bit in the UiSMR Register SU1HIM bit in the UiSMR2 Register External Clock Synchronous Function Selection 0 or 1 No synchronization Same division as the external clock External clock divided by 2 b7 b6 b5 b4 b3 b2 b1 b0 (Note 1) (Note 2) Figure 17.6 U0SMR2 to U4SMR2 Registers

Page 190 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M UARTi Special Mode Register 3 (i=0 to 4) Symbol Address After Reset U0SMR3 to U4SMR3 036516, 02E516, 033516, 032516, 02F516 0016 RW NODC ERR DL0 DL1 SSE DINC CKPH DL2 SS Pin Function Enable Bit(1) Clock Phase Set Bit Serial Input Port Set Bit Clock Output Select Bit Fault Error Flag (2) SDAi Digital Delay Time Set Bit(3, 4) 0: Disables SS pin function 1: Enables SS pin function 0: No clock delay 1: Clock delay 0: Selects the TxDi and RxDi pins (master mode) 1: Selects the STxDi and SRxDi pins (slave mode) 0: CMOS output 1: N-channel open drain output 0: No error 1: Error 000 : No delay 001 : 1-to-2 cycles of BRG count source 010 : 2-to-3 cycles of BRG count source 011 : 3-to-4 cycles of BRG count source 100 : 4-to-5 cycles of BRG count source 101 : 5-to-6 cycles of BRG count source 110 : 6-to-7 cycles of BRG count source 111 : 7-to-8 cycles of BRG count source b7 b6 b5 Bit NameBit Symbol Function NOTES: 1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled). 2. The ERR bit is set to "0" by program. It is unchanged if set to "1". 3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I 2C mode. Set these bits to "000 2" (no delay) except in the I2C mode. 4. When the external clock is selected, approximately 100ns delay is added. RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.7 U0SMR3 to U4SMR3 Registers

Page 191 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M UARTi Special Mode Register 4 (i=0 to 4) Symbol Address After Reset U0SMR4 to U4SMR4 0364 16, 02E416, 033416, 032416, 02F416 0016 RW Start Condition Generate Bit(1) Restart Condition Generate Bit (1) Stop Condition Generate Bit (1) SCL, SDA Output Select Bit ACK Data Bit ACK Data Output Enable Bit 0: Clear 1: Start 0: Clear 1: Start 0: Clear 1: Start 0: Selects the serial I/O circuit 1: Selects the start/stop condition generating circuit 0: ACK 1: NACK Bit Name Bit Symbol Function NOTES: 1. When each condition is generated, the STAREQ, RSTAREQ or STPREQ bit is set to "0". When a condition generation is incomplete, the bit remains unchanged as "1". SCL Wait Output Bit 3 SCL Output Stop Enable Bit 0: SCL "L" hold disabled 1: SCL "L" hold enabled 0: Disabled 1: Enabled 0: Serial I/O data output 1: ACK data output STSPSEL ACKD ACKC SCLHI STAREQ STPREQ RSTAREQ SWC9 RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.8 U0SMR4 to U4SMR4 Registers

Page 192 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O)T68/C23M,68/C23M(puorG68/C23M External Interrupt Request Source Select Register Symbol Address After Reset IFSR 031F 16 0016 RW INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit (1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity select bit(1) INT5 Interrupt Polarity Select Bit (1) 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges Bit Name Bit Symbol Function NOTES: 1. Set this bit to "0" to select a level-sensitive triggering. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). UART1, UART4 Interrupt Source Select Bit UART0, UART3 Interrupt Source Select Bit 0 : One edge 1 : Both edges IFSR3 IFSR4 IFSR5 IFSR6 IFSR0 IFSR2 IFSR1 IFSR7 RW RW RW RW RW RW RW RW 0 : UART3 bus conflict, start condition detect, stop condition detect 1 : UART0 bus conflict, start condition detect, stop condition detect 0 : UART4 bus conflict, start condition detect, stop condition detect 1 : UART1 bus conflict, start condition detect, stop condition detect b7 b6 b5 b4 b3 b2 b1 b0 Figure 17.9 IFSR Register

Page 193 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Clock Synchronous Serial I/O))T68/C23M,68/C23M(puorG68/C23M

17.1 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 17.1 lists specifications of clock synchronous serial I/O mode. Table 17.2 lists register settings. Tables 17.3 to 17.5 list pin settings. When UARTi (i=0 to 4) operating mode is selected, the TxDi pin outputs a high-level ("H") signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 17.10 shows transmit and receive timings in clock synchronous serial I/O mode. Table 17.1 Clock Synchronous Serial I/O Mode Specifications Item Specification Transfer Data Format Transfer data : 8 bits long Transfer Clock • The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected): fj=f1, f8, f2n(1)m :setting value of the UiBRG register, 0016 to FF16

The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin Transmit/Receive Control Selected from the CTS function, RTS function or CTS/RTS function disabled Transmit Start Condition To start transmitting, the following requirements must be met(2): - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) - Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected Receive Start Condition To start receiving, the following requirements must be met(2): - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit to "1" (transmit enable) - Set the TI bit to "0" (data in the UiTB register) Interrupt Request Generation Timing• While transmitting, the following conditions can be selected: - The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer): when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed): when a data transfer from the UARTi transmit register is completed
While receiving When data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detect Overrun error (3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register Selectable Function • CLK polarity Transferred data output and input are provided on either the rising edge or falling edge of the transfer clock
LSB first or MSB first Data is transmitted or received in either bit 0 or in bit 7
Continuous receive mode Data can be received simultaneously by reading the UiRB register
Serial data logic inverse This function inverses transmitted/received data logically NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held "L". 3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). fj 2(m+1)

Page 194 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Clock Synchronous Serial I/O))T68/C23M,68/C23M(puorG68/C23M Table 17.2 Register Settings in Clock Synchronous Serial I/O Mode Register Bit Function UiTB 7 to 0 Set transmit data UiRB 7 to 0 Received data can be read OER Overrun error flag UiBRG 7 to 0 Set bit rate UiMR SMD2 to SMD0 Set to "001 2" CKDIR Select the internal clock or external clock IOPOL Set to "0" UiC0 CLK1, CLK0 Select count source for the UiBRG register CRS Select CTS or RTS when using either TXEPT Transmit register empty flag CRD Enables or disables the CTS or RTS function NCH Select output format of the TxDi pin CKPOL Select transmit clock polarity UFORM Select either LSB first or MSB first UiC1 TE Set to "1" to enable data transmission and reception TI Transmit buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select what causes the UARTi transmit interrupt to be generated UiRRM Set to "1" when using continuous receive mode UiLCH Set to "1" when using data logic inverse SCLKSTPB Set to "0" UiSMR 7 to 0 Set to "00 16" UiSMR2 7 to 0 Set to "00 16" UiSMR3 2 to 0 Set to "000 2" NODC Select clock output format 7 to 4 Set to "0000 2" UiSMR4 7 to 0 Set to "00 16" i=0 to 4

Page 195 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Clock Synchronous Serial I/O))T68/C23M,68/C23M(puorG68/C23M Table 17.3 Pin Settings in Clock Synchronous Serial I/O Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P60 CTS0 input PS0_0=0 - PD6_0=0 RTS0 output PS0_0=1 - - P61 CLK0 input PS0_1=0 - PD6_1=0 CLK0 output PS0_1=1 - - P62 RxD0 input PS0_2=0 - PD6_2=0 P63 TxD0 output PS0_3=1 - - P64 CTS1 input PS0_4=0 - PD6_4=0 RTS1 output PS0_4=1 PSL0_4=0 - P65 CLK1 input PS0_5=0 - PD6_5=0 CLK1 output PS0_5=1 - - P66 RxD1 input PS0_6=0 - PD6_6=0 P67 TxD1 output PS0_7=1 - - Table 17.4 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 - P71(1) RxD2 input PS1_1=0 - - PD7_1=0 P72 CLK2 input PS1_2=0 - - PD7_2=0 CLK2 output PS1_2=1 PSL1_2=0 PSC_2=0 - P73 CTS2 input PS1_3=0 - - PD7_3=0 RTS2 output PS1_3=1 PSL1_3=0 PSC_3=0 - NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.5 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PSC3 Register PD9 Register (1) P90 CLK3 input PS3_0=0 - - PD9_0=0 CLK3 output PS3_0=1 - - - P91 RxD3 input PS3_1=0 - - PD9_1=0 P92 TxD3 output PS3_2=1 PSL3_2=0 - - P93 CTS3 input PS3_3=0 PSL3_3=0 - PD9_3=0 RTS3 output PS3_3=1 - - - P94 CTS4 input PS3_4=0 PSL3_4=0 - PD9_4=0 RTS4 output PS3_4=1 - - - P95 CLK4 input PS3_5=0 PSL3_5=0 - PD9_5=0 CLK4 output PS3_5=1 - - - P96 TxD4 output PS3_6=1 - PSC3_6=0 - P97 RxD4 input PS3_7=0 - - PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 196 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Clock Synchronous Serial I/O))T68/C23M,68/C23M(puorG68/C23M D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK Pulse stops because the TE bit is set to "0" Data is set in the UiTB register Transfer Clock TE bit in UiC1 register TI bit in UiC1 register CLKi TxDi TXEPT bit in UiC0 register "H" "L" CTSi IR bit in SiTIC register "0" "1" Pulse stops because an "H" signal is applied to CTSi Data is transferred from the UiTB register to the UARTi transmit register Set to "0" by an interrupt request acknowledgement or by program TC =TCLK =2(m+1)/fj fj : Count source frequency set in the UiBRG register (f1, f8, f2n(1)) m : Setting value of the UiBRG register i = 0 to 4 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division ( n=0) or divide-by-2n (n=1 to 15). The above applies to the following settings:

The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "0" (CTS function selected)
The CKPOL bit the in UiC 0 register is set to "0" (data transmitted on the falling edge of the transfer clock)
The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register) (1) Transmit Timing (Internal clock selected) "0" "1" "0" "1" "0" "1" Dummy data is set in the UiTB registerTE bit in UiC1 register TI bit in UiC1 register CLKi RxDi RI bit in UiC1 register RTSi RE bit in UiC1 register Data is transferred from the UiTB register to the UARTi transmit register Read by the UiRB register The above applies to the following settings:
The CKDIR bit in the UiMR register is set to "1" (external clock selected)
The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "1" (RTS function selected)
The CKPOL bit in the UiC0 register is set to "0" (Data is received on the rising edge of the transfer clock) IR bit in SiRIC register Set to "0" by an interrupt request acknowledgement or by program 1 / fEXT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 0 D 1 D 2 D 3 D 4 D 5D 7D 6 OER bit in UiRB register D 6 Meet the following conditions while an "H" signal is applied to the CLKi pin before receiving data:
Set the TE bit in the UiC 1 register to "1" (transmit enable)
Set the RE bit in the UiC1 register to "1" (receive enable)
Write dummy data to the UiTB register fEXT : External clock frequency i=0 to 4 (2) Receive Timing (External clock selected) "H" "L" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" An "L" signal is applied when the UiRB register is read Received data is taken in Date is transferred from the UARTi receive register to the UiRB register Figure 17.10 Transmit and Receive Operation

Page 197 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Clock Synchronous Serial I/O))T68/C23M,68/C23M(puorG68/C23M D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 0 TXD i R XD i CLK i (1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0" (Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 TXD i R XD i CLK i (2) When the CKPOL bit in the UiC0 register is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) NOTES: 1. The CLKi pin is held high ("H") when no data is transferred. 2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). NOTES: 3. The CLKi pin is held low ("L") when no data is transferred. 4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 re gister is set to "0" (not inversed). "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" (1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0" (LSB first) D 0 D 1 D 2 D 4D 3 D 5 D 6 D 7TXD i R XD i CLK i TXD i R XD i CLK i (2) When the UFORM bit in the UiC0 register is set to "1" (MSB first) NOTES: 2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). D 0 D 1 D 2 D 4D 3 D 5 D 6 D 7 D 7 D 6 D 5 D 3D 4 D 2 D 1 D 0 D 7 D 6 D 5 D 3D 4 D 2 D 1 D 0 "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L"

17.1.1 Selecting CLK Polarity Selecting

As shown in Figure 17.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the transfer clock. Figure 17.11 Transfer Clock Polarity

17.1.2 Selecting LSB First or MSB First

As shown in Figure 17.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format. Figure 17.12 Transfer Format

Page 198 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Clock Synchronous Serial I/O))T68/C23M,68/C23M(puorG68/C23M D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7TxD i (no inverse) Transfer clock "H" "L" "H" "L" TxD i (inverse) "H" "L" (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed) Transfer clock "H" "L" (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge) and the UFORM bit in the UiC0 register is set to "0" (LSB first). D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

17.1.3 Continuous Receive Mode

When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set dummy data in the UiTB register by program.

17.1.4 Serial Data Logic Inverse

When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 17.13 shows a switching example of the serial data logic. Figure 17.13 Serial Data Logic Inverse

Page 199 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (UART))T68/C23M,68/C23M(puorG68/C23M

17.2 Clock Asynchronous Serial I/O (UART) Mode

In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format. Table 17.6 lists specifications of UART mode. Table 17.6 UART Mode Specifications Item Specification Transfer Data Format • Character bit (transfer data) : selected from 7 bits, 8 bits, or 9 bits long

Start bit: 1 bit long
Parity bit: selected from odd, even, or none
Stop bit: selected from 1 bit or 2 bits long Transfer Clock • The CKDIR bit in the UiMR register is set to "0" (internal clock selected): fj/16(m+1) fj = f1, f8, f2n(1) m : setting value of the UiBRG register , 0016 to FF16
The CKDIR bit is set to "1" (external clock selected): fEXT /16(m+1) fEXT : clock applied to the CLKi pin Transmit/Receive Control Select from CTS function, RTS function or CTS/RTS function disabled Transmit Start Condition To start transmitting, the following requirements must be met: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) - Apply a low-velel ("L") signal to the CTSi pin when the CTS function is selected Receive Start Condition To start receiving, the following requirements must be met: - Set the RE bit in the UiC1 register to "1" (receive enable) - The start bit is detected Interrupt Request While transmitting, the following condition can be selected: Generation Timing - The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed): when data transmission from the UARTi transfer register is completed While receiving when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detect • Overrun error(2) This error occurs when the bit before the last stop bit of the next received data is read prior to reading the UiRB register (the first stop bit when selecting 2 stop bits)
Framing error This error occurs when the number of stop bits set is not detected
Parity error When parity is enabled, this error occurs when the number of "1" in parity and charac- ter bits does not match the number of "1" set
Error sum flag This flag is set to "1" when any of an overrun, framing or parity errors occur Selectable Function • LSB first or MSB first Data is transmitted or received in either bit 0 or in bit 7
Serial data logic inverse Logic values of data to be transmitted and received data are inversed. The start bit and stop bit are not inversed
TxD and RxD I/O polarity Inverse TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register remains unchanged as "1" (interrupt requested).

Page 200 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (UART))T68/C23M,68/C23M(puorG68/C23M mode is selected, the TxDi pin outputs a high-level ("H") signal before transfer is started (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 17.14 shows an ex- ample of a transmit operation in UART mode. Figure 17.15 shows an example of a receive operation in UART mode. Table 17.7 Register Settings in UART Mode Register Bit Function UiTB 8 to 0 Set transmit data (1) UiRB 8 to 0 Received data can be read (1) OER, FER, Error flags PER, SUM UiBRG 7 to 0 Set bit rate UiMR SMD2 to SMD0 Set to "100 2" when transfer data is 7 bits long Set to "1012" when transfer data is 8 bits long Set to "1102" when transfer data is 9 bits long CKDIR Select the internal clock or external clock STPS Select stop bit length PRY, PRYE Select parity enable or disable, odd or even IOPOL Select TxD and RxD I/O polarity UiC0 CLK1, CLK0 Select count source for the UiBRG register CRS Select either CTS or RTS when using either TXEPT Transfer register empty flag CRD Select the CTS or RTS function enabled or disabled NCH Select output format of the TxDi pin CKPOL Set to "0" UFORM Select the LSB first or MSB first when a transfer data is 8 bits long Set to "0" when transfer data is 7 bits or 9 bits long UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select what causes the UARTi transmit interrupt to be generated UiRRM Set to "0" UiLCH Select whether data logic is inversed or not inversed when a transfer data is 7 bits or 8 bits long. Set to "0" when transfer data is 9 bits long UiERE Set to either "0" or "1" UiSMR 7 to 0 Set to "00 16" UiSMR2 7 to 0 Set to "00 16" UiSMR3 7 to 0 Set to "00 16" UiSMR4 7 to 0 Set to "00 16" NOTES: 1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long.

Page 201 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (UART))T68/C23M,68/C23M(puorG68/C23M Table 17.8 Pin Settings in UART Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P60 CTS0 input PS0_0=0 – PD6_0=0 RTS0 output PS0_0=1 –– P61 CLK0 input PS0_1=0 – PD6_1=0 P62 RxD0 input PS0_2=0 – PD6_2=0 P63 TxD0 output PS0_3=1 –– P64 CTS1 input PS0_4=0 – PD6_4=0 RTS1 output PS0_4=1 PSL0_4=0 – P65 CLK1 input PS0_5=0 – PD6_5=0 P66 RxD1 input PS0_6=0 – PD6_6=0 P67 TxD1 output PS0_7=1 –– Table 17.9 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 P72 CLK2 input PS1_2=0 –– PD7_2=0 P73 CTS2 input PS1_3=0 –– PD7_3=0 RTS2 output PS1_3=1 PSL1_3=0 PSC_3=0 – NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.10 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PSC3 Register PD9 Register (1) P90 CLK3 input PS3_0=0 –– PD9_0=0 P91 RxD3 input PS3_1=0 –– PD9_1=0 P92 TxD3 output PS3_2=1 PSL3_2=0 –– P93 CTS3 input PS3_3=0 PSL3_3=0 – PD9_3=0 RTS3 output PS3_3=1 ––– P94 CTS4 input PS3_4=0 PSL3_4=0 – PD9_4=0 RTS4 output PS3_4=1 ––– P95 CLK4 input PS3_5=0 PSL3_5=0 – PD9_5=0 P96 TxD4 output PS3_6=1 – PSC3_6=0 – P97 RxD4 input PS3_7=0 –– PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers set immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 202 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (UART))T68/C23M,68/C23M(puorG68/C23M Stop bit Stop bit Start bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1STSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SPSP TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register Start bit Parity bit TxDi CTSi "1" "0" "1" "L" "H" IR bit in SiTIC register Set to "0" by an interrupt request acknowledgement or by program TE bit in UiC1 register TI bit in UiC1 register TxDi TXEPT bit in UiC0 register "0" "1" "0" "1" "0" "1" i=0 to 4 The above timing applies to the following settings :

The PRYE bit in the UiMR register is set to "0" (parity disabled)
The STPS bit in the UiMR register is set to "1" (2 stop bits)
The CRD bit in the UiC0 register is set to "1" (CTS function disabled)
The UilRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) Transfer Clock Tc Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj : count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m : setting value of the UiBRG register NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). IR bit in SiTIC register "0" "1" Tc Transfer Clock Pulse stops because the TE bit is set to "0"Stop bit Data is transferred from the UiTB register to the UARTi transmit register The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin, when the stop bit state is verified. The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin Data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register Data is set in the UiTB register"0" i=0 to 4 The above timing applies to the following settings :
The PRYE bit in the UiMR register is set to "1" (parity enabled)
The STPS bit in the UiMR register is set to "0" (1 stop bit)
The CRD bit in the UiC 0 register is set to "0" and the CRS bit is set to "0" (CTS function selected)
The UilRS bit in the UiC1 register is set to "1" (transmission completed) Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj : count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m : setting value of the UiBRG register NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (1) 8-bit Data Transmit Timing (with a parity and 1 stop bit) (2) 9-bit Data Transmit Timing (with no parity and 2 stop bits) "1" "0" "1" "0" Set to "0" by an interrupt request acknowledgement or by program SP SP Figure 17.14 Transmit Operation

Page 203 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (UART))T68/C23M,68/C23M(puorG68/C23M D 0Start bit Verify if an "L" signal is applied Capture a received data UiBRG register setting output RE bit in UiC1 register RxDi Transfer Clock RI bit in UiC1 register RTSi Stop bit "1" "0" "0" "1" "H" "L" IR bit in SiRIC register "0" "1" Data is transferred from the UARTi receive register to the UiRB register Start receiving when the transfer clock is generated on the falling edge of the start bit D 7D 1 Set to "0" by an interrupt request acknowledgement or by program Change to "L" by reading the UiRB register 8-bit Data Receive Timing (with no parity and 1 stop bit) i=0 to 4 NOTES: 1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set to "1" (RTS function selected). Figure 17.15 Receive Operation

17.2.1 Bit Rate

In UART mode, bit rate is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4) register and again divided by 16. Table 17.11 lists an example of bit rate setting. Table 17.11 Bit Rate etaRtiB )spb( tnuoC ecruoS fo GRBiU :kcolCnoitcnuFlarehpireP zHM61 :kcolCnoitcnuFlarehpireP zHM42 :kcolCnoitcnuFlarehpireP zHM23 eulaVgnitteS :GRBiUfo n etaRtiBlautcA )spb( eulaVgnitteS :GRBiUfo n etaRtiBlautcA )spb( eulaVgnitteS :GRBiUfo n etaRtiBlautcA )spb( 00218 f) h76(3012 021) h69(5512 021) hFC(7022 021 00428 f) h33(154 042) h64(774 042) h76(3014 042 00848 f) h91(528 084) h62(838 084) h33(158 084 00691 f) h76(3015 169) h69(5515 169) hFC(7025 169 004411 f) h44(863 9441) h76(3013 2441) hA8(8318 8341 002911 f) h33(151 3291) h64(771 3291) h76(3011 3291 008821 f) h22(431 7582) h33(156 4882) h44(866 8982 052131 f) hF1(130 5213) hF2(740 5213) hF3(360 5213 004831 f) h91(522 6483) h62(832 6483) h33(152 6483 002151 f) h31(910 0005) hC1(824 2715) h62(832 8215

Page 204 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (UART))T68/C23M,68/C23M(puorG68/C23M P SPST SPST P TxD i (no inverse) Transfer Clock"H" "L" "H" "L" (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse) TxD i (inverse) "H" "L" Transfer Clock "H" "L" (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) NOTES: 1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). D

0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ST : Start bit P : Parity bit SP : Stop bit ST : Start bit P : Parity bit SP : Stop bit CLKi TxD i RxD i D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 P SPST SPST P (1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first) P SPST SPST P (2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first) CLKi TxD i RxD i NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (no inverse). D D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L"

17.2.2 Selecting LSB First or MSB First

As shown in Figure 17.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format. This function is available for 8-bit transfer data. Figure 17.16 Transfer Format

17.2.3 Serial Data Logic Inverse

When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 17.17 shows a switching example of the serial data logic. Figure 17.17 Serial Data Logic Inverse

Page 205 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (UART))T68/C23M,68/C23M(puorG68/C23M P SPST SPST P P SPST SPST P TxD i (no inverse) Transfer Clock (1) When the IOPOL bit in the UiMR register (i=0 to 4) is set to "0" (no inverse) RxD i (no inverse) TxD i (inverse) Transfer Clock (2) When the IOPOL bit in the UiMR register is set to "1" ( inverse) RxD i (inverse) NOTES: 1. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). ST : Start bit P : Even parity SP : Stop bit D D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L"

17.2.4 TxD and RxD I/O Polarity Inverse

TxD pin output and RxD pin input are inversed. All I/O data level, including the start bit, stop bit and parity bit, are inversed. Figure 17.18 shows TxD and RxD I/O polarity inverse. Figure 17.18 TxD and RxD I/O Polarity Inverse

Page 206 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M

17.3 Special Mode 1 (I2C Mode)

I2C mode is a mode to communicate with external devices with a simplified I2C. Table 17.12 lists specifica- a block diagram of I2C mode. Figure 17.20 shows timings for transfer to the UiRB register (i=0 to 4) and interrupts. Tables 17.15 to 17.17 list pin settings. As shown in Table 17.12, I2C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to "0102" and the IICM bit in the UiSMR register is set to "1". Output signal from the SDAi pin changes after the SCLi pin level becomes low ("L") and stabilizes due to a SDAi transmit output via the delay circuit. Table 17.12 I2C Mode Specifications Item Specifications Interrupt Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment detect Selectable Function • Arbitration lost The update timing of the ABT bit in the UiRB register can be selected. Refer to 17.3.3 Arbitration

SDAi digital delay Selected from no digital delay or 2 to 8 cycle delay of the count source of the UiBRG register. Refer to 17.3.5 SDA Output
Clock phase setting Selected from clock delay or no clock delay. Refer to 17.3.4 Transfer clock

Page 207 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M I/O Timer Delay Circuit UARTi Receive Register External Clock Arbitration Detects Start Condition Detects Stop Condition Falling edge detect UARTi Transmission NACK Interrupt Request UARTi Reception ACK Interrupt Request DMA Request 9th Pulse Port reading * When the IICM bit is set to "1", port pin can be read regardless of the direction register being set to "1". i=0 to 4 NOTES: 1. Set the PSj (j=0,1,3), PSLj or PSC register to determine. IICM : Bit in the UiSMR register IICM2 : Bit in the UiSMR2 register LSYN bit Bus Conflict Start Condition Detect Stop Condition Detect Interrupt Request Bus Conflict Detect I/O Noise Filter SDAi SCLi CLK Control Internal ClockUARTi UARTi I/O Timer CLK i Data Register D T Q D T Q D T Q NACK ACK UARTi UARTi R IICM IICM=1 and IICM2=0 IICM IICM=1 IICM=0 S R Q Bus busy IICM ALS R S SWC Falling Edge of 9th Pulse IICM=1 and IICM2=0 IICM=0 or IICM2=1 IICM=0 or IICM2=1 SWC2 SDHI To DMA To DMA Transmit Register UARTi (Note1) (Note 1) Noise Filter Noise Filter IICM (Note 1) Q Figure 17.19 I2C Mode Block Diagram

Page 208 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.13 Register Settings in I2C Mode Register Bit Function Master Slave UiTB 7 to 0 Set transmit data UiRB 7 to 0 Received data can be read

8 ACK or NACK bit can be read

ABT Arbitration lost detect flag Disabled OER Overrun error flag UiBRG 7 to 0 Set bit rate Disabled UiMR SMD2 to SMD0 Set to "010 2" CKDIR Set to "0" Set to "1" IOPOL Set to "0" UiC0 CLK1, CLK0 Select count source of the UiBRG register Disabled CRS Disabled because the CRD bit is set to "1" TXEPT Transfer register empty flag CRD, NCH Set to "1" CKPOL Set to "0" UFORM Set to "1" UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiRRM, UiLCH, Set to "0" UiERE UiSMR IICM Set to "1" ABC Select an arbitration lost detect timing Disabled BBS Bus busy flag 7 to 3 Set to "00000 2" UiSMR2 IICM2 See Table 17.14 CSC Set to "1" to enable clock synchronization Set to "0" SWC Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit of the transfer clock ALS Set to "1" to terminate SDAi output when Not used. Set to "0" detecting the arbitration lost STC Not used. Set to "0" Set to "1" to reset UARTi by detecting the start condition SWC2 Set to "1" for an "L" signal output from SCL forcibly SDHI Set to "1" to disable SDA output SU1HIM Set to "0" UiSMR3 SSE Set to "0" CKPH See Table 17.14 DINC, NODC, ERR Set to "0" DL2 to DL0 Set digital delay value UiSMR4 STAREQ Set to "1" when generating a start condition Not used. Set to "0" RSTAREQ Set to "1" when generating a restart condition STPREQ Set to "1" when generating a stop condition STSPSEL Set to "1" when using a condition generating function ACKD Select ACK or NACK ACKC Set to "1" for ACK data output SCLHI Set to "1" to enable SCL output stop when Not used. Set to "0" detecting stop condition SWC9 Not used. Set to "0" Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit of the transfer clock IFSR IFSR6, IFSR7 Set to "1" i=0 to 4

Page 209 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M noitcnuF suonorhcnySkcolC edoMO/IlaireS 100=0DMSot2DMS( 2, )0=MCII I2 010=0DMSot2DMS(edoMC 2 )1=MCII, 0=2MCII )tpurretniKCA/KCAN( 1=2MCII )tpurretnieviecerTRAU/timsnartTRAU( 0=HPKC )yaledkcolcoN( 1=HPKC )yaledkcolC( 0=HPKC )yaledkcolcoN( 1=HPKC )yaledkcolC( ot93srebmuNtpurretnI detareneG14 )1( )02.71erugiFeeS( - )81.71elbaTeeS(tcetednoitidnocpotsronoitidnoctratS ,91,71rebmuNtpurretnI 73dna53,33 detareneG )1( )02.71erugiFeeS( -noissimsnarTiTRAU rodetratsnoissimsnarT ybdetceles(detelpmoc )retsigerSRIiUeht tnemegdelwonkcAoN -)KCAN(noitceteD iLCSfotibht9foegdegnisiR iTRAU -noissimsnarT foegdegnisiR iLCSfotibht9 -noissimsnarTiTRAU ehtretfaegdegnillaftxeN iLCSfotibht9 ,02,81srebmuNtpurretnI 83dna63,43 detareneG )1( )02.71erugiFeeS( -noitpeceRiTRAU tibht8tagnivieceR )egdegnisir(0=LOPKC )egdegnillaf(1=LOPKC noitceteDtnemegdelwonkcA )KCA(- iLCSfotibht9foegdegnisiR -noitpeceRiTRAU iLCSfotibht9foegdegnillaF morfgnimiTrefsnarTataD tfihSevieceRTRAUeht retsigeRBRiUehtotretsigeR )egdegnisir(0=LOPKC )egdegnillaf(1=LOPKC iLCSfotibht9foegdegnisiR foegdegnillaF iLCSfotibht9 egdegnisirdnaegdegnillaF iLCSfotibht9fo tuptuOtimsnarTiTRAU yaleD yaledoNy aleD 6P 3 6P, 7 7P, 0 9P, 2 9P, 6 snoitcnuFniP tuptuoiDxTt uptuodnatupniiADS 6P 2 6P, 6 7P, 1 9P, 1 9P, 7 snoitcnuFniP tupniiDxRt uptuodnatupniiLCS 6P 1 6P, 5 7P, 2 9P, 0 9P, 5 snoitcnuFniP rotupniiKLCtceleS tuptuo InidesutoN(– 2 )edomC htdiWretliFesioNs n51s n002 iLCSdnaiDxRgnidaeR sleveLniP tropfidaerebnaC "0"ottessitibnoitcerid tibnoitceridtropehtfosseldragerdaerebnaC ,iDxTfoeulaVtluafeD tuptuOiADS )H(0=LOPKC )L(1=LOPKC IgniretneerofebretsigertropehtnitesseulaV 2 edomC )2( dnEdnatluafeDiLCS eulaV – HL HL detareneGAMD )02.71erugiFeeS( noitpeceriTRAU cetedtnemegdelwonkcAn oit )KCA( -noitpeceRiTRAU iLCSfotibht9foegdegnillaF ataDdevieceRerotS ehtfostibht8otts1 derotseraataddeviecer ehtni0ot7stibotni retsigerBRiU deviecerehtfostibht8otts1 0ot7stibotniderotseraatad retsigerBRiUehtni derotseraataddeviecerehtfostibht7otts1 sitibht8.retsigerBRiUehtni0ot6stibotni .retsigerBRiUehtni8tibotniderots otniderotserastibht8otts1 BRiUehtni0ot7stib retsiger )3( ataDdevieceRgnidaeRd aersisutatsretsigerBRiUehT BRiUehtni0ot6stiB stretsiger )4( 7tibsadaerera BRiUehtni8tiB.1ot 0tibsadaersiretsiger Table 17.14 I2C Mode Functions i=0 to 4 NOTES: 1. Use the following procedure to change what causes an interrupt to be generated. (a) Disable interrupt of corresponding interrupt number. (b) Change what causes an interrupt to be generated. (c) Set the IR bit of a corresponding interrupt number to "0" (no interrupt requested). (d) Set the ILVL2 to ILVL0 bits of a corresponding interrupt number. 2. Set default value of the SDAi output when the SMD2 to SMD0 bits in the UiMR register are set to "000 (serial I/O disabled). 3. Second data transfer to the UiRB register (on the rising edge of the ninth bit of SCLi). 4. First data transfer to the UiRB register (on the falling edge of the ninth bit of SCLi).

Page 210 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M (4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1" (3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0" SDAi SCLi Receive interrupt (DMA request) Transmit interrupt SDAi SCLi i=0 to 4 IICM2 : Bit in the UiSMR2 register CKPH : Bit in the UiSMR3 regiser The above timing applies to the following setting :

The CKDIR bit in the UiMR register is set to "1" (slave) (1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay) D 6 D 5 D 4 D 3 D 2 D 1 D 8 (ACK or NACK)D 7SDAi SCLi D 0 ACK interrupt (DMA request) or NACK interrupt (2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay) SDAi SCLi 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15
•• b9 b8 b7 b0 D 8 Contents of the UiRB register b15
•• b9 b8 b7 b0 b15
•• b9 b8 b7 b0 b15
•• b9 b8 b7 b0 b15
•• b9 b8 b7 b0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 6 D 5 D 4 D 3 D 2 D 1D 7 D 0 ACK interrupt (DMA request) or NACK interrupt D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 6 D 5 D 4 D 3 D 2 D 1D 7 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1D 0 D 6 D 5 D 4 D 3 D 2 D 1D 7 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1D 0 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D 8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D 8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit Data is transferred to the UiRB register Data is transferred to the UiRB register Data is transferred to the UiRB register Receive interrupt (DMA request) Transmit interrupt Data is transferred to the UiRB register Data is transferred to the UiRB register Contents of the UiRB register Contents of the UiRB register Contents of the UiRB registerContents of the UiRB register Figure 17.20 SCLi Timing

Page 211 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.15 Pin Settings in I2C Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P62 SCL0 output PS0_2=1 PSL0_2=0 - SCL0 input PS0_2=0 - PD6_2=0 P63 SDA0 output PS0_3=1 - - SDA0 input PS0_3=0 - PD6_3=0 P66 SCL1 output PS0_6=1 PSL0_6=0 - SCL1 input PS0_6=0 - PD6_6=0 P67 SDA1 output PS0_7=1 - - SDA1 input PS0_7=0 - PD6_7=0 Table 17.16 Pin Settings (2) NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.17 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PSC3 Register PD9 Register (1) P91 SCL3 output PS3_1=1 PSL3_1=0 - - SCL3 input PS3_1=0 - - PD9_1=0 P92 SDA3 output PS3_2=1 PSL3_2=0 - - SDA3 input PS3_2=0 - - PD9_2=0 P96 SDA4 output PS3_6=1 - PSC3_6=0 - SDA4 input PS3_6=0 - - PD9_6=0 P97 SCL4 output PS3_7=1 PSL3_7=0 - - SCL4 input PS3_7=0 - - PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. troPn oitcnuF gnitteS retsigeR1SPr etsigeR1LSPr etsigeRCSPr etsigeR7DP 7P 0 )1( tuptuo2ADS1 =0_1SP0 =0_1LSP0 =0_CSP – tupni2ADS0 =0_1SP –– 0=0_7DP 7P 1 )1( tuptuo2LCS1 =1_1SP1 =1_1LSP0 =1_CSP – tupni2LCS0 =1_1SP –– 0=1_7DP

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17.3.1 Detecting Start Condition and Stop Condition

The microcomputer detects either a start condition or stop condition. The start condition detect interrupt is generated when the SCLi (i=0 to 4) pin level is held high ("H") and the SDAi pin level changes "H" to low ("L"). The stop condition detect interrupt is generated when the SCLi pin level is held "H" and the SDAi pin level changes "L" to "H". The start condition detect interrupt shares interrupt control registers and vectors with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which interrupt is requested. Setup time Hold time SCLi SDAi (Start condition) SDAi (Stop condition) 3 to 6 cycles < setup time(1) 3 to 6 cycles < hold time(1) i=0 to 4 NOTES: 1. These cycles are main clock generation frequency cycles (XIN). Figure 17.21 Start Condition or Stop Condition Detecting

17.3.2 Start Condition or Stop Condition Output

The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1" (start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1" (start). The stop condition is generated the STPREQ bit in the UiSMR4 is set to "1" (start). The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4 register is set to "1" (start or stop condition generating circuit selected). The restart condition output is provided when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition output is provided when the STPREQ bit and the STSPSEL bit are set to "1". When the start condition, stop condition or restart condition is output, do not generate an interrupt be- tween the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the STSPSEL bit is set to "1". Table 17.18 lists function of the STSPSEL bit. Figure 17.22 shows functions of the STSPSEL bit.

Page 213 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.18 STSPSEL Bit Function SDAi Start condition detect interrupt Stop condition detect interrupt (1) In slave mode, The CKDIR bit is set to "1" (external clock) The STSPSEL bit is set to "0" (no start condition and stop condition output) SCLi SDAi Start condition detect interrupt Stop condition detect interrupt SCLi The STPREQ bit is set to "1" (start) The STPREQ bit is set to "1" (start) (2) In master mode, The CKDIR bit is set to "0" (internal clock) The STSPSEL bit is set to "1" (start condition and stop condition output) 0 1 0 01Setting value of the STSPEL bit i=0 to 4 Figure 17.22 STSPSEL Bit Function noitcnuF0 =LESPSTS1 =LESPSTS potsdnanoitidnoctratS tuptuonoitidnoc ehtwohsenimretedstrophtiwmargorP tuptuonoitidnocpotsronoitidnoctrats dedivorpsi dnatibQERATSR,tibQERATSehT tratsehtwohenimretedtibQERPTS tuptuonoitidnocpotsronoitidnocs i dedivorp tratsetarenegotgnimiT noitidnocpotsdnanoitidnoc tseuqertpurretnis noitidnocpotsdnanoitidnoctratsehT detcetedera noitidnocpotsdnanoitidnoctratS detelpmoceranoitareneg

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17.3.3 Arbitration

The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB register. On the rising edge of the SCLi pin, the microcomputer determines whether a transmit data matches data input to the SDAi pin. When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" (detected-arbitration is lost) as soon as a data discrepancy is detected. The ABT bit is set to "0" (not detected-arbitration is won) if not detected. When the ABC bit is set to "1" (update per byte), the ABT bit is set to "1" on the falling edge of the ninth bit of the transfer clock if any discrepancy is detected. When the ABT bit is updated per byte, set the ABT bit to "0" between an ACK detection in the first byte data and the next byte data to be transferred. When the ALS bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost occurs. As soon as the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state.

17.3.4 Transfer Clock

The transfer clock transmits and receives data as is shown in Figure 17.20. The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi) with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous en- abled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal applied to the SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals from the internal SCLi and the SCLi pin. The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit is set to "1". The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to be an "L" signal output on the falling edge of the ninth cycle of the transfer clock or not. When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop condition is detected (high-impedance). When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin focibly outputs an "L" signal while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC2 bit to "0" (transfer clock) and the transfer clock input to and output from the SCLi pin are provided. When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to "1" (SCL "L" hold enabled), the SCLi pin is fixed to be an "L" signal output on the next falling edge after the ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to "0" (SCL "L" hold disabled).

17.3.5 SDA Output

Values output set in bits 7 to 0 (D7 to D0) in the UiTB register (i=0 to 4) are provided in descending order from D7. The ninth bit (D8) is ACK or NACK. Set the default value of SDAi transmit output when the IICM bit is set to "1" (I2C mode) and the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled). The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8 UiBRG register count source cycles. When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly placed in a high-impedance state. Do not set the SDHI bit on the rising edge of the UARTi transfer clock. The ABT bit in the UiRB register may be set to "1" (detected).

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17.3.6 SDA Input

When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK. When the IICM2 bit is set to "1", the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the UiRB register. Store the eighth bit (D0) into bit 8 in the UiRB register. If the IICM2 bit is set to "1" and the CKPH bit in the UiSMR3 register is set to "1", the same data as that of when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising edge of the ninth bit of the transfer clock.

17.3.7 ACK, NACK

When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin provides the value output set in the ACKD bit in the UiSMR4 register. If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H") on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock. When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection.

17.3.8 Transmit and Receive Reset

When the STC bit in the UiSMR2 register (i=0 to 4) is set to "1" (UARTi initialization enabled) and a start condition is detected, - the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift register. The first bit starts transmitting when the next clock is input. UARTi output value remains unchanged between when the clock is applied and when the first bit data output is provided. The value remains the same as when start condition was detected. - the receive shift register is reset and the first bit start receiving when the next clock is applied. - the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes "L" on the falling edge of the ninth bit of the transfer clock. If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains unchanged. Select the external clock as the transfer clock when using this function.

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17.4 Special Mode 2

In special mode 2, serial communication between one or multiple masters and multiple slaves is available._____ The SSi input pin (i=0 to 4) controls the serial bus communication. Table 17.19 lists specifications of special Table 17.19 Special Mode 2 Specifications Item Specification Transfer Data Format Transfer data : 8 bits long Transfer Clock • The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected): fj/2(m+1) fj = f1, f8, f2n(1) m : setting value of the UiBRG register, 0016 to FF16

The CKDIR bit to "1" (external clock selected) : input from the CLKi pin Transmit/Receive Control SSi input pin function Transmit Start Condition To start transmitting, the following requirements must be met(2): - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Receive Start Condition To start receiving, the following requirement must be met(2): - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Interrupt Request • While transmitting, the following conditions can be selected: Generation Timing - The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transmission started) - The UiIRS register is set to "1" (transmission completed): when data transmission from UARTi transfer register is completed
While receiving When data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection • Overrun error(3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register
Fault error In master mode, the fault error occurs an "L" signal is applied to the SSi pin Selectable Function • CLK polarity Select from the rising edge or falling edge of the transfer clock when transferred data is output and input are provided
LSB first or MSB first Data is transmitted or received in either bit 0 or in bit 7
Continuous receive mode Reception is enabled simultaneously by reading the UiRB register
Serial data logic inverse This function inverses transmitted or received data logically
TxD and RxD I/O polarity inverse TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
Clock phase Select from one of 4 combinations of transfer data polarity and phases
SSi input pin function Output pin is placed in a high-impedance state to avoid data conflict between master and other masters or slaves NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L"). 3. If an overrun error occurs, the UiRB register is in an indeterminate state. The IR bit in the SiRIC register does not change to "1" (interrupt requested).

Page 217 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.20 Register Settings in Special Mode 2 Register Bit Function UiTB 7 to 0 Set transmit data UiRB 7 to 0 Received data can be read OER Overrun error flag UiBRG 7 to 0 Set bit rate UiMR SMD2 to SMD0 Set to "001 2" CKDIR Set to "0" in master mode or "1" in slave mode IOPOL Set to "0" UiC0 CLK1, CLK0 Select count source for the UiBRG register CRS Disabled because the CRD bit is set to "1" TXEPT Transfer register empty flag CRD Set to "1" NCH Select the output format of the TxDi pin CKPOL Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in the UiSMR3 register UFORM Select either LSB first or MSB first UiC1 TE Set to "1" to enable data transmission and reception TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select what causes the UARTi transmit interrupt to be generated UiRRM Set to "1" to enable continuous receive mode UiLCH, SCLKSTPB Set to "0" UiSMR 7 to 0 Set to "00 16" UiSMR2 7 to 0 Set to "00 16" UiSMR3 SSE Set to "1" CKPH Clock phase can be set by the combination of the CKPH bit and the CKPOL bit in the UiC0 register DINC Set to "0" in master mode or "1" in slave mode NODC Set to "0" ERR Fault error flag 7 to 5 Set to "000 2" UiSMR4 7 to 0 Set to "00 16" i=0 to 4

Page 218 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.21 Pin Settings in Special Mode 2 (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P6 0 SS0 input PS0_0=0 – PD6_0=0 P6 1 CLK0 input (slave) PS0_1=0 – PD6_1=0 CLK0 output (master) PS0_1=1 –– P6 2 RxD0 input (master) PS0_2=0 – PD6_2=0 STxD0 output (slave) PS0_2=1 PSL0_2=1 – P6 3 TxD0 output (master) PS0_3=1 –– SRxD0 input (slave) PS0_3=0 – PD6_3=0 P6 4 SS1 input PS0_4=0 – PD6_4=0 P6 5 CLK1 input (slave) PS0_5=0 – PD6_5=0 CLK1 output (master) PS0_5=1 –– P6 6 RxD1 input (master) PS0_6=0 – PD6_6=0 STxD1 output (slave) PS0_6=1 PSL0_6=1 – P6 7 TxD1 output (master) PS0_7=1 –– SRxD1 input (slave) PS0_7=0 – PD6_7=0 Table 17.22 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output (master) PS1_0=1 PSL1_0=0 PSC_0=0 – SRxD2 input (slave) PS1_0=0 –– PD7_0=0 P71(1) RxD2 input (master) PS1_1=0 –– PD7_1=0 STxD2 output (slave) PS1_1=1 PSL1_1=1 PSC_1=0 – P7 2 CLK2 input (slave) PS1_2=0 –– PD7_2=0 CLK2 output (master) PS1_2=1 PSL1_2=0 PSC_2=0 – P7 3 SS2 input PS1_3=0 – – PD7_3=0 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.23 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PSC3 Register PD9 Register (1) P9 0 CLK3 input (slave) PS3_0=0 –– PD9_0=0 CLK3 output (master) PS3_0=1 ––– P9 1 RxD3 input (master) PS3_1=0 –– PD9_1=0 STxD3 output (slave) PS3_1=1 PSL3_1=1 –– P9 2 TxD3 output (master) PS3_2=1 PSL3_2=0 –– SRxD3 input (slave) PS3_2=0 –– PD9_2=0 P9 3 SS3 input PS3_3=0 PSL3_3=0 – PD9_3=0 P9 4 SS4 input PS3_4=0 PSL3_4=0 – PD9_4=0 P9 5 CLK4 input (slave) PS3_5=0 PSL3_5=0 – PD9_5=0 CLK4 output (master) PS3_5=1 ––– P9 6 TxD4 output (master) PS3_6=1 – PSC3_6=0 – SRxD4 input (slave) PS3_6=0 PSL3_6=0 – PD9_6=0 P9 7 RxD4 input (master) PS3_7=0 –– PD9_7=0 STxD4 output (slave) PS3_7=1 PSL3_7=1 –– NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

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17.4.1 SSi Input Pin Function (i=0 to 4)

____ When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the special mode 2 is selected, activating the pin function. The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave. When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting deter- mines which master microcomputer is active and when.

17.4.1.1 When Setting the DINC Bit to "1" (Slave Mode)

When a high-level ("H") signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a high- impedance state and the transfer clock applied to the CLKi pin is ignored. When a low-level ("L") signal is applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled.

17.4.1.2 When Setting the DINC Bit to "0" (Master Mode)

When using the SSi pin functin in master mode, set the UiIRS bit in the UiC1 register to "1" (transmis- sion completed). When an "H" signal is applied to the SSi pin, serial communication is available due to transmission privilege. The master provides the transfer clock output. When an "L" signal is applied to the SSi pin, it indicates that another master is active. The TxDi and CLKi pins are placed in high-impedance states and the ERR bit in the UiSMR3 register is set to "1" (fault error) Use the transmit complete interrupt routine to verify the ERR bit state. To resume the serial communication after the fault error occurs, set the ERR bit to "0" while applying the "H" signal to the SSi pin. The TxDi and CLKi pins become ready for signal outputs. P13 P12 Microcomputer P93(SS 3) P92(TxD 3) P90(CLK 3) P91(RxD 3) P93(SS 3) P92(SRxD 3) P90(CLK 3) P91(STxD 3) P93(SS 3) P92(SRxD 3) P90(CLK 3) P91(STxD 3) Master Slave Slave Microcomputer Microcomputer ____ Figure 17.23 Serial Bus Communication Control with SS Pin

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17.4.2 Clock Phase Setting Function

The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four combinations of transfer clock polarity and phases. The transfer clock phase and polarity must be the same between the master and the slave involved in the transfer.

17.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))

Figure 17.24 shows transmit and receive timing.

17.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))

When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the transfer clock. Figure 17.25 shows the transmit and receive timing. When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmis- sion is synchronized with the transfer clock. Figure 17.26 shows the transmit and receive timing. Figure 17.24 Transmit and Receive Timing in Master Mode (Internal Clock) Signal Applied to the SS Pin Data Output Timing Data Input Timing D 0 D 1 D 2 D 3 D 4 D 6 D 7D 5 "H" "L" Clock Output (CKPOL=0, CKPH=0) "H" "L" Clock Output (CKPOL=1, CKPH=0) "H" "L" Clock Output (CKPOL=0, CKPH=1) "H" "L" Clock Output (CKPOL=1, CKPH=1) "H" "L" "H" "L"

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17.5 Special Mode 3 (GCI Mode)

In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial I/O mode. pin settings. Table17.24 GCI Mode Specifications Item Specification Transfer Data Format Transfer data : 8 bits long Transfer Clock The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected): input from the CLKi pin Clock Synchronization Function Trigger signal input from the CTSi pin Transmit/Receive Start To start data transmission and reception, meet the following conditions and then apply a Condition trigger signal to the CTSi pin: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TI bit in the UiC1 register to "0" (Data in the UiTB register) Interrupt Request • While transmitting, the following condition can be selected: Generation Timing - The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty): when data is transferred from the UiTB register to the UARTi transmit register (transmission started) - The UiIRS bit is set to "1" (Transmit completed): when a data transmission from the UARTi transfer register is completed

While receiving, when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection Overrun error (1) This error occurs when the seventh bit of the next received data is read before reading the UiRB register. NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested).

Page 223 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.25 Register Settings in GCI Mode Register Bit Function UiTB 7 to 0 Set transmit data UiRB 7 to 0 Received data OER Overrun error flag UiBRG 7 to 0 Set to "00 16" UiMR SMD2 to SMD0 Set to "001 2" CKDIR Set to "1" IOPOL Set to "0" UiC0 CLK1, CLK0 Set to "00 2" CRS Disabled because the CRD bit is set to "1" TXEPT Transfer register empty flag CRD Set to "1" NCH Select the output format of the TxDi pin CKPOL Set to "0" UFORM Set to "0" UiC1 TE Set to "1" to enable data transmission and reception TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Select what causes the UARTi transmit interrupt to be generated UiRRM, UiLCH Set to "0" SCLKSTPB Set to "0" UiSMR 6 to 0 Set to "0000000 2" SCLKDIV See Table 17.29 UiSMR2 6 to 0 Set to "0000000 2" SU1HIM See Table 17.29 UiSMR3 2 to 0 Set to "000 2" NODC Set to "0" 7 to 4 Set to "0000 2" UiSMR4 7 to 0 Set to "00 16" i=0 to 4

Page 224 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.26 Pin Settings in GCI Mode (1) Port Function Setting PS0 Register PD6 Register P6 0 CTS0 input(1) PS0_0=0 PD6_0=0 P6 1 CLK0 input PS0_1=0 PD6_1=0 P6 2 RxD0 input PS0_2=0 PD6_2=0 P6 3 TxD0 output PS0_3=1 – P6 4 CTS1 input(1) PS0_4=0 PD6_4=0 P6 5 CLK1 input PS0_5=0 PD6_5=0 P6 6 RxD1 input PS0_6=0 PD6_6=0 P6 7 TxD1 output PS0_7=1 – NOTES: 1. CTS input is used as a trigger siganl input. Table 17.27 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 P7 2 CLK2 input PS1_2=0 –– PD7_2=0 P7 3 CTS2 input(2) PS1_3=0 –– PD7_3=0 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. 2. CTS input is used as a trigger siganl input. Table 17.28 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PSC3 Register PD9 Register (1) P9 0 CLK3 input PS3_0=0 –– PD9_0=0 P9 1 RxD3 input PS3_1=0 –– PD9_1=0 P9 2 TxD3 output PS3_2=1 PSL3_2=0 –– P9 3 CTS3 input(2) PS3_3=0 PSL3_3=0 – PD9_3=0 P9 4 CTS4 input(2) PS3_4=0 PSL3_4=0 – PD9_4=0 P9 5 CLK4 input PS3_5=0 PSL3_5=0 – PD9_5=0 P9 6 TxD4 output PS3_6=1 PSL3_6=0 PSC3_6=0 – P9 7 RxD4 input PS3_7=0 –– PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. 2. CTS input is used for a trigger siganl input.

Page 225 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Trigger Signal from the CTSi Pin External Clock from the CLKi Pin Transfer Clock TxDi A Transfer Clock i=0 to 4 A, B : See Table 17.29. TxDi B 12345678 12345678 1234567 8 The SCLKSTPB bit in the UiC1 register stops the clock To generate the internal clock synchronized with the external clock, set the SU1HIM bit in the UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 17.29. Then apply a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an external clock operation. Figure 17.27 shows an example of the clock-divided synchronous function. Table 17.29 Clock-Divided Synchronous Function Select SCLKDIV Bit in SU1HIM Bit in Clock-Divided Synchronous Function Example of Waveform UiSMR Register UiSMR2 Register 0 0 Not synchronized - 0 1 Same division as the external clock A in Figure 17.27 1 0 or 1 Same division as the external clock B in Figure 17.27 divided by 2 i=0 to 4 Figure 17.27 Clock-Divided Synchronous Function

Page 226 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M

17.6 Special Mode 4 (IE Mode)

In IE mode, devices connected with the IEBus can communicate in UART mode. Table 17.30 Register Settings in IE Mode Register Bit Function UiTB 8 to 0 Set transmit data UiRB 8 to 0 Received data can be read OER, FER, Error flags PER, SUM UiBRG 7 to 0 Set bit rate UiMR SMD2 to SMD0 Set to "110 2" CKDIR Select the internal clock or external clock STPS Set to "0" PRY Disabled because the PRYE bit is set to "0" PRYE Set to "0" IOPOL Select TxD and RxD I/O polarity UiC0 CLK1, CLK0 Select count source for the UiBRG register CRS Disabled because the CRD bit is set to "1" TXEPT Transfer register empty flag CRD Set to "1" NCH Select output format of the TxDi pin CKPOL Set to "0" UFORM Set to "0" UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" te enable data reception RI Reception complete flag UiIRS Select what causes the UARTi transmit interrupt to be generated UiRRM, UiLCH, Set to "0" SCLKSTPB UiSMR 3 to 0 Set to "0000 2" ABSCS Select bus conflict detect sampling timing ACSE Set to "1" to automatically clear the transmit enable bit SSS Select transmit start condition SCLKDIV Set to "0" UiSMR2 7 to 0 Set to "00 16" UiSMR3 7 to 0 Set to "00 16" UiSMR4 7 to 0 Set to "00 16" IFSR IFSR6, IFSR7 Select how the bus conflict interrupt occurs i=0 to 4

Page 227 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.31 Pin Settings in IE Mode (1) Port Function Setting PS0 Register PSL0 Register PD6 Register P61 CLK0 input PS0_1=0 – PD6_1=0 CLK0 output PS0_1=1 –– P62 RxD0 input PS0_2=0 – PD6_2=0 P63 TxD0 output PS0_3=1 –– P65 CLK1 input PS0_5=0 – PD6_5=0 CLK1 output PS0_5=1 –– P66 RxD1 input PS0_6=0 – PD6_6=0 P67 TxD1 output PS0_7=1 –– Table 17.32 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 P72 CLK2 input PS1_2=0 –– PD7_2=0 CLK2 output PS1_2=1 PSL1_2=0 PSC_2=0 – NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.33 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PSC3 Register PD9 Register (1) P90 CLK3 input PS3_0=0 –– PD9_0=0 CLK3 output PS3_0=1 ––– P91 RxD3 input PS3_1=0 –– PD9_1=0 P92 TxD3 output PS3_2=1 PSL3_2=0 –– P95 CLK4 input PS3_5=0 PSL3_5=0 – PD9_5=0 CLK4 output PS3_5=1 ––– P96 TxD4 output PS3_6=1 – PSC3_6=0 – P97 RxD4 input PS3_7=0 –– PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 228 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M If the output signal level of the TxDi pin (i=0 to 4) differs from the input signal level of the RxDi pin, an interrupt request is generated. UART0 and UART3 are assigned software interrupt number 40. UART1 and UART4 are assigned number 41. When using the bus conflict detect function of UART0 or UART3, of UART1 or UART4, set the IFSR6 bit and the IFSR7 bit in the IFSR register accordingly. When the ABSCS bit in the UiSMR register is set to "0" (rising edge of the transfer clock), it is determined, on the rising edge of the transfer clock, if the output level of the TxD pin and the input level of the RxD pin match. When the ABSCS bit is set to "1" (timer Aj underflow), it is determined when the timer Aj (timer A3 in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3, the timer A4 in UART4) counter overflows. Use the timer Aj in one-shot timer mode. When the ACSE bit in the UiSMR register is set to "1" (automatic clear at bus conflict) and the IR bit in the BCNiIC register to "1" (discrepancy detected), the TE bit in the UiC1 register is set to "0" (transmit disable). When the SSS bit in the UiSMR register is set to "1" (synchronized with RxDi), data is transmitted from the TxDi pin on the falling edge of the RxDi pin. Figure 17.28 shows bits associated with the bus conflict detect function.

Page 229 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M (1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected) Bus conflict is detected on the rising edge of the transfer clock when the ABSCS bit is set to "0" Transfer Clock Timer Aj (2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared) IR bit in BCNilC register TE bit in UiC1 register (3) The SSS bit in the UiSMR Register (Transmit start condition is selected) TxDi transmit enable conditons are met CLKi TxDi RxDi NOTES: 1. Data is transmitted on the falling edge of a signal applied to the RxDi pin when the IOPOL bit is set to "0". Data is transmitted on the rising edge of a signal applied to the RxDi pin when the IOPOL bit is set to "1". 2. Data transmission condition must be met before the falling edge of the RxDi pin. When the SSS bit is set to "0", data is transmitted after one transfer clock cycle if data transmission is enabled. TxDi RxDi ST SP Trigger signal is applied to the TAjIN pin When the ABSCS bit is set to "1", bus conflict is detected when the timer Aj underflows (in the one-shot timer mode). An interrupt request is generated. Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2 Transfer Clock TxDi RxDi ST SP Transfer Clock ST SP ST D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 SP When the SSS bit is set to "1", data is transmitted on the falling edge of RxDi(1) (Note 2) (i=0 to 4) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 Figure 17.28 Bit Function Related Bus Conflict Detection

Page 230 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M

17.7 Special Mode 5 (SIM Mode)

In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are available and a low-level ("L") signal output can be provided from the TxDi pin (i=0 to 4) when a parity error is detected. pin settings. Table 17.34 SIM Mode Specifications Item Specification Transfer Data Format • Transfer data: 8-bit UART mode • One stop bit

In direct format • In inverse format Parity: Even Parity: Odd Data logic: Direct Data logic: Inverse Transfer format: LSB first Transfer format: MSB first Transfer Clock • The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected): fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register, 0016 to FF16 Do not set the CKDIR bit to "1" (external clock selected) Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled) Other Setting Items The UiIRS bit in the UiC1 register is set to "1" (transmission completed) Transmit Start Condition To start transmitting, the following requirements must be met: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Receive Start Condition To start receiving, the following requirements must be met: - Set the RE bit in the UiC1 register to "1" (receive enable) - Detect the start bit Interrupt Request • While transmitting, Generation Timing - The UiIRS bit is set to "1" (transmission completed): when data transmission from the UARTi transfer register is completed
While receiving, when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection • Overrun error(1) This error occurs when the eighth bit of the next data is received before reading the UiRB register
Flaming error This error occurs when the number of the stop bit set is not detected
Parity error This error occurs when the number of "1" in parity bit and character bits differs from the number set
Error sum flag The SUM bit is set to "1" when an overrun error, framing error or parity error occurs NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 231 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.35 Register Settings in SIM Mode Register Bit Function UiTB 7 to 0 Set transmit data UiRB 7 to 0 Received data can be read OER, FER, Error flags PER, SUM UiBRG 7 to 0 Set bit rate UiMR SMD2 to SMD0 Set to "101 2" CKDIR Set to "0" STPS Set to "0" PRY Set to "1" for direct format or "0" for inverse format PRYE Set to "1" IOPOL Set to "0" UiC0 CLK1, CLK0 Select count source for the UiBRG register CRS Disabled because the CRD bit is set to "1" TXEPT Transfer register empty flag CRD Set to "1" NCH Set to "1" CKPOL Set to "0" UFORM Set to "0" for direct format or "1" for inverse format UiC1 TE Set to "1" to enable data transmission TI Transfer buffer empty flag RE Set to "1" to enable data reception RI Reception complete flag UiIRS Set to "1" UiRRM Set to "0" UiLCH Set to "0" for direct format or "1" for inverse format UiERE Set to "1" UiSMR 7 to 0 Set to "00 16" UiSMR2 7 to 0 Set to "00 16" UiSMR3 7 to 0 Set to "00 16" UiSMR4 7 to 0 Set to "00 16" i=0 to 4

Page 232 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Table 17.36 Pin Settings in SIM Mode (1) Port Function Setting PS0 Register PD6 Register P6 2 RxD0 input PS0_2=0 PD6_2=0 P6 3 TxD0 output PS0_3=1 – P6 6 RxD1 input PS0_6=0 PD6_6=0 P6 7 TxD1 output PS0_7=1 – Table 17.37 Pin Settings (2) Port Function Setting PS1 Register PSL1 Register PSC Register PD7 Register P70(1) TxD2 output PS1_0=1 PSL1_0=0 PSC_0=0 – P71(1) RxD2 input PS1_1=0 –– PD7_1=0 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.38 Pin Settings (3) Port Function Setting PS3 Register(1) PSL3 Register PSC3 Register PD9 Register (1) P9 1 RxD3 input PS3_1=0 – PD9_1=0 P9 2 TxD3 output PS3_2=1 PSL3_2=0 – P9 6 TxD4 output PS3_6=1 – PSC3_6=0 – P9 7 RxD4 input PS3_7=0 – PD9_7=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Figure 17.29 shows an example of a SIM interface operation. Figure 17.30 shows an example of a SIM interface connection. Connect the TxDi pin to the RxDi pin for a pull-up.

Page 233 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Figure 17.29 SIM Interface Operation D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP Start bit Parity bit "0" "1" "0" "1" "0" "1" Set to "0" by an interrupt request acknowledgement or by program Tc Transfer Clock Stop bit Data is written to the UARTi register An "L" signal is applied from the SIM card due to a parity error An interrupt routine detects "H" or "L" TxDi "0" "1" Transfer Clock Read the UiRB register Signal Line Level(3) TxDi Signal Line Level(2) NOTES: 1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit. 2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi pin and parity error signal from the receiving end, is generated. 3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end and parity error signal from the TxDi pin, is generated. 4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15). Data is transferred from the UiTB register to the UARi transmit register (Note 1) RE bit in UiC1 register RI bit in UiC1 register IR bit in SiRIC register TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit in SiTIC registeri=0 to 4 The above applies to the following settings :

The PRYE bit in the UiMR register is set to "1" (parity enabled)
The STPS bit in the UiMR register is set to "0" (1 stop bit)
The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated when transmission completed) Tc = 16(m+1) / f j fj : count source frequency of the UiBRG register (f1, f8, f2n(4)) m : setting value of the UiBRG register Start bit Set to "0" by an interrupt request acknowledgement or by program Stop bit TxDi outputs "L" due to a parity error i=0 to 4 The above applies to the following settings :
The PRYE bit in the UiMR register is set to "1" (parity enabled)
The STPS bit in the UiMR register is set to "0" (1 stop bit) Tc = 16(m+1) / f j fj : count source frequency of the UiBRG register (f1, f8, f2n(4)) m : setting value of the UiBRG register Parity bit "0" "1" "0" "0" "1" (1) Transmit Timing (2) Receive Timing Parity Error Signal returned from Receiving End Transmit Waveform from the Transmitting End "1" SP An interrupt routine detects "H" or "L" SP

Page 234 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M Figure 17.30 SIM Interface Connection

17.7.1 Parity Error Signal

17.7.1.1 Parity Error Signal Output Function

When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1" (output), the parity error signal output can be provided. The parity error signal output is provided when a parity error is detected upon receiving data. A low-level ("L") signal output is provided from the TxDi pin in the timing shown in Figure 17.31. When reading the UiRB register during a parity error output, the PER bit in the UiRB register is set to "0" (no error occurs) and a high-level ("H") signal output is again provided simulta- neously.

17.7.1.2 Parity Error Signal

To determine whether the parity error signal is output, the port that shares a pin with the RxDi pin is read by using an end-of-transmit interrupt routine. Microcomputer SIM card TxD i RxD i i=0 to 4 Figure 17.31 Parity Error Signal Output Timing (LSB First) P SPST Hi-Z RxDi TxDi Recieve Complete Flag "H" "L" "H" "L" "1" "0" NOTES: 1. The above applies to direct format conditions. (The PRY bit is set to "1", the UFORM bit is set to "0", and the UiLCH bit is set to "0"). D ST : Start bit P : Even parity SP : Stop bit i=0 to 4 "H" "L" Transfer Clock

Page 235 974fo5002,80.peS00.1.veR 0010-4020B90JER 17. Serial I/O (Special Function))T68/C23M,68/C23M(puorG68/C23M D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 P Transfer Clock TxD i TxD i D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 P (1) Direct Format Transfer Clock (2) Inverse Format P : Odd parity "H" "L" "H" "L" "H" "L" "H" "L" P : Even parity i=0 to 4

17.7.2 Format

17.7.2.1 Direct Format

Set the PRYE bit in the UiMR register (i=0 to 4) to "1" (parity enabled), the PRY bit to "1" (even parity), the UFORM bit in the UiC0 register to "0" (LSB first) and the UiLCH bit in the UiC1 register to "0" (not inversed). When data are transmitted, data set in the UiTB register are transmitted with the even-numbered parity, starting from D 0. When data are received, received data are stored in the UiRB register, starting from D0. The even-numbered parity determines whether a parity error occurs.

17.7.2.2 Inverse Format

Set the PRYE bit to "1", the PRY bit to "0" (odd parity), the UFORM bit to "1" (MSB first) and the UiLCH bit to "1" (inversed). When data are transmitted, values set in the UiTB register are logically inversed and are transmitted with the odd-numbered parity, starting from D 7. When data are re- ceived, received data are logically inversed to be stored in the UiRB register, starting from D7. The odd-numbered parity determines whether a parity error occurs. Figure 17.32 SIM Interface Format

Page 236 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M 18. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter with a capacitive cou- pling amplifier. The result of an A/D conversion is stored into the A/D registers corresponding to selected pins. It is stored into the AD00 register only when DMAC operating mode is entered. Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the A/D converter. Figures 18.2 to 18.6 show registers associated with the A/D converter. Table 18.1 A/D Converter Specifications Item Specification A/D Conversion Method Successive approximation (with a capacitive coupling amplifier) Analog Input Voltage(1) 0V to AVCC (VCC ) Operating Clock, Ø AD (2) fAD , fAD /2, fAD /3, fAD /4, fAD /6, fAD /8 Resolution Select from 8 bits or 10 bits Operating Mode One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1, multi-port single sweep mode, multi-port repeat sweep mode 0 Analog Input Pins(3) 34 pins 8 pins each for AN (AN0 to AN7), AN0 (AN00 to AN07), AN2 (AN20 to AN27), AN15 (AN150 to AN157) 2 extended input pins (ANEX0 and ANEX1) A/D Conversion Start Condition• Software trigger The ADST bit in the AD0CON0 register is set to "1" (A/D conversion started) by program

External trigger (re-trigger is enabled) When a falling edge is applied to the ADTRG pin after the ADST bit is set to "1" by program
Hardware trigger (re-trigger is enabled) The timer B2 interrupt request of the three-phase motor control timer functions (after the ICTB2 counter completes counting) is generated after the ADST bit is set to "1" by program Conversion Rate Per Pin • Without the sample and hold function 8-bit resolution : 49 Ø AD cycles 10-bit resolution : 59 Ø AD cycles
With the sample and hold function 8-bit resolution : 28 Ø AD cycles 10-bit resolution : 33 Ø AD cycles NOTES: 1. Analog input voltage is not affected by the sample and hold function status. 2. Ø AD frequency must be under 16 MHz when VCC =5V. Without the sample and hold function, the Ø AD frequency is 250 kHz or more. With the sample and hold function, the Ø AD frequency is 1 MHz or more. 3. AVCC = VREF = VCC , A/D input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0 and ANEX1) ≤ VCC .

Page 237 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M 000 AN0 0 001 AN0 1 010 AN0 2 011 AN0 3 100 AN0 4 AN0 5 101 110 AN0 6 111 AN0 7 000 AN2 0 001 AN2 1 010 AN2 2 011 AN2 3 100 AN2 4 AN2 5 101 110 AN2 6 111 AN2 7

000 AN15 0

P0(1) P2(1) P15

001 AN15 1

010 AN15 2

011 AN15 3

100 AN15 4

110 AN15 6

111 AN15 7

CSK0 bit in AD0CON0 register CSK1 bit in AD0CON1 register 1/21/2 CSK2 bit in AD0CON3 register fAD ANEX0 ANEX1 OPA1 and OPA0 bits in AD0CON1 register CH2 to CH0 bits in AD0CON0 register CH2 to CH0 bits in AD0CON0 register APS1 and APS0 bits in AD0CON2 register 00 11 10 TRG0 bit in AD0CON2 register

1 TRG bit in

Timer B2 interrupt request of the three-phase motor control timer functions AD0CON2 register AD0CON3 register AD0CON4 register Comparator 0 Decoder Successive conversion register Resistor ladder Ø AD NOTES: 1. These pins are available in single-chip mode. P96 P95 P10 Figure 18.1 A/D Converter Block Diagram

Page 238 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M Figure 18.2 AD0CON0 Register Function A/D0 Control Register 0(1) Bit NameBit Symbol Symbol Address After Reset AD0CON0 0396 16 00 16 RW RW RW RW RW RW RW RW RW CH0 CH1 CH2 Analog Input Pin Select Bit (2, 3, 8, 9) (i=none, 0, 2, 15) MD0 MD1 TRG CKS0 ADST A/D Operating Mode Select Bit 0(2, 6, 7) A/D Conversion Start Flag Trigger Select Bit Frequency Select Bit 0 : Software trigger 1 : External trigger, hardware trigger(4) 0 : A/D conversion stops 1 : A/D conversion starts (4) (Note 5) 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 b1b0 0 0 0 : ANi0 0 0 1 : ANi1 0 1 0 : ANi2 0 1 1 : ANi3 1 0 0 : ANi4 1 0 1 : ANi5 1 1 0 : ANi6 1 1 1 : ANi7 b3b4 NOTES: 1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Analog input pins must be set again after changing an A/D operating mode. 3. The CH2 to CH0 bit settings are enabled in one-shot mode and repeat mode. 4. To set the TRG bit to "1", select the cause of trigger by setting the TRG0 bit in the AD0CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1". AD frequency must be under 16 MHz when VCC =5V. Combination of the CKS0, CKS1 and CKS2 bits selects AD . 6. When the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled), set the MD1 and MD0 bits to "102" to enter multi-port single sweep mode and to "112" to enter multi-port repeat sweep mode 0. 7. When the MSS bit is set to "1", the MD1 and MD0 bits cannot be set to "002" or "012". 8. AVCC =VREF =VCC , AD input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AM27, AN150 to AN157, ANEX0, ANEX1) ≤ VCC . 9. Set the PSC_7 bit in the PSC register to "1" to use the P10 pin as an analog input pin. The CKS0 Bit in the AD0CON0 Register The CKS1 Bit in the AD0CON1 Register AD The CKS2 Bit in the AD0CON3 Register fAD divided by 4 fAD divided by 3 fAD divided by 2 fAD fAD divided by 8 fAD divided by 6 b7 b6 b5 b4 b3 b2 b1 b0

Page 239 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M Figure 18.3 AD0CON1 Register Function A/D0 Control Register 1(1) Bit NameBit Symbol Symbol Address After Reset AD0CON1 0397 16 00 16 RW RW RW RW RW RW RW RW RW SCAN0 SCAN1 MD2 A/D Sweep Pin Select Bit(2, 10) (i=none, 0, 2, 15) Single sweep mode and repeat sweep mode 0 BITS CKS1 VCUT OPA1 OPA0 8/10-Bit Mode Select Bit External Op-Amp Connection Mode Bit (7, 9) 0 : No VREF connection(11) 1 : VREF connection 0 0 : ANEX0 and ANEX1 are not used(8) 0 1 : Signal into ANEX0 is A/D converted 1 0 : Signal into ANEX1 is A/D converted 1 1 : External op-amp connection mode V REF Connection Bit (Note 6) 0 : 8-bit mode 1 : 10-bit mode A/D Operating Mode Select Bit 1 0 0 : ANi0, ANi1 0 1 : ANi0 to ANi3 1 0 : ANi0 to ANi5 1 1 : ANi0 to ANi7 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1(5) Frequency Select Bit Repeat sweep mode 1(3) 0 0 : ANi0 0 1 : ANi0, ANi1 1 0 : ANi0 to ANi2 1 1 : ANi0 to ANi3 b0b1 b6b7 NOTES: 1. When the AD0CON1 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. The SCAN1 and SCAN0 bit settings are disabled in single sweep mode, repeat sweep mode 0, repeat sweep mode 1, mutli-port single sweep mode and multi-port repeat sweep mode 0. 3. This pin is commonly used in the A/D conversion when the MD2 bit is set to "1". 4. In multi-port single sweep mode or multi-port repeat sweep mode 0, do not set the SCAN1 and SCAN0 bits to any setting other than "11 2". 5. When the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled), set the MD2 bit to "0". 6. Refer to the note for the CKS0 bit in the AD0CON0 register. In one-shot mode and repeat mode, the OPA1 and OPA0 bits can be set to "012" or "102" only. Do not set the OPA0 and OPA1 bits to "012" or "102" in other modes. 8. To set the OPA1 and OPA0 bits to "002", set the PSL3_5 bit in PSL3 register to "0" (other than ANEX0) and the PSL3_6 bit to "0" (other than ANEX1). 9. When the MSS bit is set to "1", set the OPA1 and OPA0 bits to "002". 10. AV CC =VREF =VCC , AD input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AM27, AN150 to AN157, ANEX0, ANEX1) ≤ VCC . 11. Do not set the VCUT bit to "0" during the A/D conversion. VREF is a reference voltage for AD0 only. The VCUT bit setting does not affect the VREF performance of the D/A converter. Multi-port single sweep mode and multi-port repeat sweep mode 0(4) 1 1 : ANi0 to ANi7 b7 b6 b5 b4 b3 b2 b1 b0

Page 240 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M Function A/D0 Control Register 2(1) Bit NameBit Symbol Symbol Address After Reset AD0CON2 0394 16 XX0X X000 2 RW RW RW RW RW RW SMP APS0 APS1 (b4 - b3) (b7 - b6) TRG0 A/D Conversion Method Select Bit Analog Input Port Select Bit (2, 3) 0 : Without the sample and hold funtion 1 : With the sample and hold function External Trigger Request Cause Select Bit 0 : Selects AD TRG 1 : Selects a timer B2 interrupt request of the three-phase motor control timer functions (after the ICTB2 counter completes counting) b2b1 0 0 : AN0 to AN7, ANEX0, ANEX1 0 1 : AN150 to AN157 1 0 : AN00 to AN07 1 1 : AN20 to AN27 NOTES: 1. When the AD0CON2 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. When the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled), set the APS1 and APS0 bits to "01 2". 3. The APS1 and APS0 bits can be set to "102" or "112" in single-chip mode only. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Reserved Bit Set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 0 0 Figure 18.4 AD0CON2 Register

Page 241 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M Function A/D0 Control Register 3(1, 2) Bit NameBit Symbol Symbol Address After Reset AD0CON3 0395 16 XXXX X000 2 RW RW RW RW RO RO RW DUS MSS CKS2 MSF0 MSF1 (b7 - b5) Multi-Port Sweep Status Flag(8) DMAC Operation Select Bit (3) Multi-Port Sweep Mode Select Bit Frequency Select Bit 0 0 : AN0 to AN7 0 1 : AN150 to AN157 1 0 : AN00 to AN07 1 1 : AN20 to AN27 b4 b3 NOTES: 1. When the AD0CON3 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. The AD0CON3 may be read uncorrectly during the A/D conversion. It must be read or written after the A/D converter stops operating. 3. When the MSS bit is set to "1", set the DUS bit to "1". 4. When the DUS bit is set to "1", the AD00 register stores all A/D conversion results. 5. When the DUS bit is set to "1", set the DMAC. 6. When the MSS bit is set to "1", set the MD2 bit in the AD0CON1 register to "0" (other than repeat sweep mode 1), the APS1 and APS0 bits in the AD0CON2 register to "01 2" (AN150 to AN157) and the OPA1 and OPA0 bits in the AD0CON1 register to "002" (ANEX0 and ANEX1 not used). 7. Refer to the note for the CKS0 bit in the AD0CON0 register. 8. The MSF1 and MSF0 bit settings are enabled when the MSS bit is set to "1". Value in the bit is indeterminate when the MSS bit is set to "0". Reserved Bit (Note 7) Set to "0". When read, its content is indeterminate. 0 : Disables multi-port sweep mode 1 : Enables multi-port sweep mode (3, 6) 0 : Disables DMAC operating mode 1 : Enables DMAC operating mode (4, 5) b7 b6 b5 b4 b3 b2 b1 b0 000 Figure 18.5 AD0CON3 Register

Page 242 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M Function A/D0 Control Register 4(1) Bit NameBit Symbol Symbol Address After Reset AD0CON4 0392 16 XXXX 00XX 2 RW RW RW RW RW MPS10 MPS11 (b1 - b0) (b7 - b4) Multi-Port Sweep Port Select Bit(2) NOTES: 1. When the AD0CON4 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. The MPS11 and MPS10 bits can be set to "10 2" or "112" in single-chip mode only. 3. When the MSS bit in the AD0CON3 regsiter is set to "0" (multi-port sweep mode disabled), set the MPS11 and MPS10 bits to "002". When the MSS bit is set to "1" (multi-port sweep mode enabled), set the MPS11 and MPS10 bits to Reserved Bit Set to "0". When read, its content is indeterminate. Reserved Bit Set to "0". When read, its content is indeterminate. 0 0 : (Note 3) 0 1 : AN0 to AN7, AN150 to AN157 1 0 : AN0 to AN7, AN00 to AN07 1 1 : AN0 to AN7, AN20 to AN27 b3 b2 b7 b6 b5 b4 b3 b2 b1 b0 0000 00 Figure 18.6 AD0CON4 Register and AD00 to AD07 Registers Function A/D0 Register i (i =0 to 7)(1, 2, 3, 4, 5) Symbol Address After Reset AD00 0381 16 - 038016 00000000 XXXXXXXX 2 AD01 to AD03 038316 - 038216, 038516 - 038416, 038716 - 038616 Indeterminate AD04 to AD06 038916 - 038816, 038B16 - 038A16, 038D16 - 038C16 Indeterminate AD07 038F 16 - 038E16 Indeterminate RW RO RO 8 low-order bits in an A/D conversion result When read, its content is indeterminate. In 10-bit mode In 8-bit mode : 2 high-order bits in an A/D conversion result : When read, its content is indeterminate. RO b7 b0b15 b8 NOTES: 1. In DMAC operating mode, register value read by program is indeterminate. 2. Register value is indeterminate when written while the A/D conversion is stopped. 3. Register value is indeterminate if the next A/D conversion result is stored before reading the register. 4. The AD00 register is available in DMAC operating mode. Other registers are indeterminate. 5. In DMAC operating mode and 10-bit mode, set DMAC for a 16-bit transfer.

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18.1 Mode Description

18.1.1 One-shot Mode

In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.2 lists specifications of one-shot mode. Table 18.2 One-shot Mode Specifications Item Specification Function The CH2 to CH0 bits in the AD0CON0 register, the OPA1 and OPA0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select a pin. Analog voltage applied to the pin is converted to a digital code once Start Condition •When the TRG bit in the AD0CON0 register is set to "0" (software trigger), the ADST bit in the AD0CON0 register is set to "1" (A/D conversion starts) by program

When the TRG bit is set to "1" (external trigger, hardware trigger): - a falling edge is applied to the ADTRG pin after the ADST bit is set to "1" by program - The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 register counter completes counting) is generated after the ADST bit is set to "1" by program Stop Condition •A/D conversion is completed (the ADST bit is set to "0" when the software trigger is selected)
The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingA/D conversion is completed Analog Voltage Input Pins Select one pin from ANi0 to ANi7 (i=none, 0, 2, 15), ANEX0 or ANEX1 Reading of A/D Conversion Result•When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode disabled), the microcomputer reads the AD0j register (j=0 to 7) corre- sponding to selected pin When the DUS bit is set to "1" (DMAC operating mode enabled), do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings

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18.1.2 Repeat Mode

In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 18.3 lists specifications of repeat mode. Table 18.3 Repeat Mode Specifications Item Specification Function The CH2 to CH0 bits in the AD0CON0 register, the OPA1 and OPA0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select a pin. Analog voltage applied to the pin is repeatedly converted to a digital code Start Condition Same as one-shot mode Stop Condition The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing•When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode disabled), no interrupt request is generated.

When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed. Analog Voltage Input Pins Select one pin from ANi0 to ANi7 (i=none, 0, 2, 15), ANEX0 or ANEX1 Reading of A/D Conversion Result•When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to 7) corresponding to the selected pin.
When DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings

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18.1.3 Single Sweep Mode

In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 18.4 lists specifications of single sweep mode. Table 18.4 Single Sweep Mode Specifications Item Specification Function The SCAN1 and SCAN0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select pins. Analog voltage applied to the pin is converted one-by-one to a digital code Start Condition Same as one-shot mode Stop Condition Same as one-shot mode Interrupt Request Generation Timing•When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode disabled), an interrupt request is generated after a sweep is completed.

When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed Analog Voltage Input Pins Select from ANi0 and ANi1 (2 pins) (i=none, 0, 2, 15), ANi0 to ANi3 (4 pins), ANi0 to ANi5 (6 pins) or ANi0 to ANi7 (8 pins) Reading of A/D Conversion Result•When the DUS bit is set to "0", the microcomputer reads the AD0j register corre- sponding to selected pins
When DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings

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18.1.4 Repeat Sweep Mode 0

In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 18.5 lists specifications of repeat sweep mode 0. Table 18.5 Repeat Sweep Mode 0 Specifications Item Specification Function The SCAN1 and SCAN0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select pins. Analog voltage applied to the pins is repeatedly converted to a digital code Start Condition Same as one-shot mode Stop Condition The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing•When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode disabled), no interrupt request is generated

When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed Analog Voltage Input Pins Select from ANi0 and ANi1 (2 pins) (i=none, 0, 2, 15), ANi0 to ANi3 (4 pins), ANi0 to AN i5 (6 pins) or ANi0 to ANi7 (8 pins) Reading of A/D Conversion Result•When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to 7) corresponding to selected pins
When the DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings

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18.1.5 Repeat Sweep Mode 1

In repeat sweep mode 1, analog voltage selectively applied to eight pins is repeatedly converted to a digital code. Table 18.6 lists specifications of repeat sweep mode 1. Table 18.6 Repeat Sweep Mode 1 Specifications Item Specification Function The SCAN1 and SCAN0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select 8 pins. Analog voltage selectively applied to 8 pins is repeatedly converted to a digital code e.g., When ANi 0 is selected (i =none, 0, 2, 15), analog voltage is converted to a digital code in the following order: Start Condition Same as one-shot mode (Any trigger generated during an A/D conversion is invalid) Stop Condition The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing• When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode disabled), no interrupt request is generated

When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed Analog Voltage Input Pins ANi 0 to ANi7 (8 pins) Prioritized Pins ANi 0 (1 pin), ANi0 and ANi1 (2 pins), ANi0 to ANi2 (3 pins) or ANi0 to ANi3 (4 pins) Reading of A/D Conversion Result• When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to 7) corresponding to selected pins
When the DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings

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18.1.6 Multi-Port Single Sweep Mode

In multi-port single sweep mode, analog voltage applied to 16 selected pins is converted one-by-one to a digital code. Set the DUS bit in the AD0CON3 register to "1" (DMAC operating mode enabled). Table 18.7 lists specifications of multi-port single sweep mode. Table 18.7 Multi-Port Single Sweep Mode Specifications Item Specification Function The MPS11 and MPS10 bits in the AD0CON4 register select 16 pins. Analog voltage applied to 16 pins is converted one-by-one to a digital code in the following order: AN 0 to AN7 ANi0 to ANi7 (i=0, 2, 15) e.g., When the MPS11 and MPS10 bits are set to "102" (AN0 to AN7, AN00 to AN07), analog voltage is converted to a digital code in the following order: AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Start Condition Same as one-shot mode Stop Condition The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingAn interrupt request is generated every time A/D conversion is completed (Set the DUS bit to "1") Analog Voltage Input Pins Select from AN0 to AN7 AN150 to AN157, AN0 to AN7 AN00 to AN07 or AN0 to AN 7 AN20 to AN27 Reading of A/D Conversion ResultDo not read the AD00 register. A/D conversion result is stored in the AD00 regis- ter after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit to "1")

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18.1.7 Multi-Port Repeat Sweep Mode 0

In multi-port repeat sweep mode 0, analog voltage that is applied to 16 selected pins is repeatedly con- verted to a digital code. Set the DUS bit in the AD0CON3 register to "1" (DMAC operating mode en- abled). Table 18.8 lists specifications of multi-port repeat sweep mode 0. Table 18.8 Multi-Port Repeat Sweep Mode 0 Specifications Item Specification Function The MPS11 and MPS10 bits in the AD0CON4 register select 16 pins. Analog voltage applied to the 16 pins is repeatedly converted to a digital code in the fol- lowing order: AN 0 to AN7 ANi0 to ANi7 (i=0, 2, 15) e.g., When the MPS11 and MPS10 bits are set to "102" (AN0 to AN7, AN00 to AN07), analog voltage is repeatedly converted to a digital code in the following order: AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Start Condition Same as one-shot mode Stop Condition The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation TimingAn interrupt request is generated after each A/D conversion is completed (Set the DUS bit to "1") Analog Voltage Input Pins Selectable from AN0 to AN7 AN150 to AN157, AN0 to AN7 AN00 to AN07 or AN 0 to AN7 AN20 to AN27 Reading of A/D Conversion ResultDo not read the AD00 register. A/D conversion result is stored in the AD00 regis- ter after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit to "1")

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18.2 Functions

18.2.1 Resolution Select Function

The BITS bit in the AD0CON1 register determines the resolution. When the BITS bit is set to "1" (10-bit precision), the A/D conversion result is stored into bits 9 to 0 in the AD0j register (j = 0 to 7). When the BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 7 to 0 in the AD0j register.

18.2.2 Sample and Hold Function

When the SMP bit in the AD0CON2 register is set to "1" (with the sample and hold function), A/D conver- sion rate per pin increases to 28 Ø AD cycles for 8-bit resolution and 33 Ø AD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold function is to be used or not.

18.2.3 Trigger Select Function

The TRG bit in the AD0CON0 register and the TRG0 bit in the AD0CON2 register select the trigger to start the A/D conversion. Table 18.9 lists settings of the trigger select function. Table 18.9 Trigger Select Function Settings Bit and Setting Trigger AD0CON0 Register AD0CON2 Register TRG = 0 - Software trigger The A/D0 starts the A/D conversion when the ADST bit in the AD0CON0 register is set to "1" TRG = 1(1) TRG0 = 0 External trigger (2) Falling edge of a signal applied to ADTRG TRG0 = 1 Hardware trigger (2) The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 counter completes counting) NOTES: 1. A/D0 starts the A/D conversion when the ADST bit is set to "1" (A/D conversion started) and a trigger is generated. 2. The A/D conversion is restarted if an external trigger or a hardware trigger is inserted during the A/D conversion. (The A/D conversion in process is aborted.)

18.2.4 DMAC Operating Mode

DMAC operating mode is available with all operating modes. When the A/D converter is in multi-port single sweep mode or multi-port repeat sweep mode 0, the DMAC operating mode must be used. When the DUS bit in the AD0CON3 register is set to "1" (DMAC operating mode enabled), all A/D conversion results are stored into the AD00 register. DMAC transfers data from the AD00 register to any memory space every time an A/D conversion is completed in each pin. 8-bit DMA transfer must be selected for 8- bit resolution and 16-bit DMA transfer for 10-bit resolution. Refer to 13. DMAC for instructions.

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18.2.5 Extended Analog Input Pins

In one-shot mode and repeat mode, the ANEX0 and ANEX1 pins can be used as analog input pins. The OPA1 and OPA0 bits in the AD0CON1 register select which pins to use as analog input pins. An A/D conversion result for the ANEX0 pin is stored into the AD00 register. The result for the ANEX1 pin is stored into the AD01 register, but is stored into the AD00 register when the DUS bit in the AD0CON3 register is set to "1" (DMAC operating mode enabled). Set the APS1 and APS0 bits in the AD0CON2 register to "00 2" (AN0 to AN7, ANEX0, ANEX1) and the MSS bit in the AD0CON3 register to "0" (multi-port sweep mode disabled).

18.2.6 External Operating Amplifier (Op-Amp) Connection Mode

In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp using extended analog input pins ANEX0 and ANEX1. When the OPA1 and OPA0 bits in the AD0CON1 register are set to "11 2" (external op-amp connection), voltage applied to the AN0 to AN7 pins are output from ANEX0. Amplify this output signal by an external op-amp and apply it to ANEX1. Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored into the corresponding AD0j register (j=0 to 7). A/D conversion rate varies depending on the response of the external op-amp. The ANEX0 pin cannot be connected to the ANEX1 pin directly. Set the APS1 and APS0 bits in the AD0CON2 register to "00 2" (AN0 to AN7, ANEX0, ANEX1). Figure 18.7 shows an example of an external op-amp connection. Table 18.10 Extended Analog Input Pin Settings AD0CON1 Register ANEX0 Function ANEX1 Function OPA1 Bit OPA0 Bit 0 0 Not used Not used 0 1 P9 5 as an analog input Not used 1 0 Not used P9 6 as an analog input 1 1 Output to an external op-amp Input from an external op-amp AN 0 AN 7 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 ANEX1 ANEX0 Resistor ladder Successive conversion register Analog input External op-amp Comparator 0 002 APS1 and APS0 bits in AD0CON2 register Figure 18.7 External Op-Amp Connection

Page 252 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M

18.2.7 Power Consumption Reducing Function

When the A/D converter is not used, the VCUT bit in the AD0CON1 register isolates the resistor ladder of the A/D converter from the reference voltage input pin (VREF ). Power consumption is reduced by shutting off any current flow into the resistor ladder from the VREF pin. When using the A/D converter, set the VCUT bit to "1" (VREF connection) before setting the ADST bit in the AD0CON0 register to "1" (A/D conversion started). Do not set the ADST bit and VCUT bit to "1" simultaneously, nor set the VCUT bit to "0" (no V REF connection) during the A/D conversion. The VCUT bit does not affect the VREF performance of the D/A converter.

18.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion

For perfect A/D converter performance, complete internal capacitor (C) charging, shown in Figure 18.8, for the specified period (T) as sampling time. Output Impedance of the sensor equivalent circuit (R 0) is determined by the following equations: VC = VIN {1 – e } When t = T, VC = VIN – VIN = VIN (1 – ) e = – T= ln R0 = – – R where: VC = Voltage between pins R = Internal resistance of the microcomputer X = Precision (error) of the A/D converter Y = Resolution of the A/D converter (1024 in 10-bit mode, and 256 in 8-bit mode) Figure 18.8 shows analog input pin and external sensor equivalent circuit. The impedance (R 0) can be obtained if the voltage between pins (VC ) changes from 0 to VIN-(0.1/1024) VIN in the time (T), when the difference between VIN and VC becomes 0.1LSB. (0.1/1024) means that A/D precision drop, due to insufficient capacitor charge, is held to 0.1LSB at time of A/ D conversion in the 10-bit mode. Actual error, however, is the value of absolute precision added to 0.1LSB. When Ø AD = 10 MHz, T = 0.3 µs in the A/D conversion mode with the sample and hold function. Output impedance (R 0) for sufficiently charging capacitor (C) in the time (T) is determined by the following equation: Using T = 0.3 µs, R = 7.8 kΩ , C = 1.5 pF, X = 0.1, Y = 1024, R0 = –– 7.8 X103 = 13.9 X 103 Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less, is approximately 13.9 kΩ maximum. C (R0 +R) Y X Y X Y X Y X C • ln T Y X C (R0 + R)– t T C (R0 + R)

1.5 X 10 –12 • ln

0.1

0.3 X 10-6

Page 253 974fo5002,80.peS00.1.veR 0010-4020B90JER 18. A/D Converter)T68/C23M,68/C23M(puorG68/C23M R 0 R (7.8Ω) C (1.5pF) VIN Microcopmuter Sensor equivalent circuit VC Sampling time Sample and hold function is enabled : 3 φAD φADSample and hold function is disabled : Figure 18.8 Analog Input Pin and External Sensor Equivalent Circuit

Page 254 974fo5002,80.peS00.1.veR 0010-4020B90JER 19. D/A Converter)T68/C23M,68/C23M(puorG68/C23M 19. D/A Converter The D/A converter consists of two separate 8-bit R-2R ladder D/A converters. Digital code is converted to an analog voltage when a value is written to the corresponding DAi registers (i=0,1). The DAiE bit in the DACON register determines whether the D/A conversion result output is pro- vided or not. Set the DAiE bit to "1" (output enabled) to disable a pull-up of a corresponding port. Output analog voltage ( V) is calculated from value n (n=decimal) set in the DAi register. V = (n = 0 to 255) VREF : reference voltage (not related to VCUT bit setting in the AD0CON1 register) Table 19.1 lists specifications of the D/A converter. Table 19.2 lists the DA0 and DA1 pin settings. Figure shows a D/A converter equivalent circuit. When the D/A converter is not used, set the DAi register to "00 16" and the DAiE bit to "0" (output disabled). Table 19.1 D/A Converter Specifications Item Specification D/A Conversion Method R-2R Resolution 8 bits Analog Output Pin 2 channels Table 19.2 Pin Settings Port Function Bit and Setting PD9 Register(1) PS3 Register(1) PSL3 Register P9 3 DA 0 output PD9_3=0 PS3_3=0 PSL3_3=1 P9 4 DA 1 output PD9_4=0 PS3_4=0 PSL3_4=1 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. VREF x n 256

Page 255 974fo5002,80.peS00.1.veR 0010-4020B90JER 19. D/A Converter)T68/C23M,68/C23M(puorG68/C23M /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DA0 Register R-2R Resistor Ladder /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Low-Order Bits of Data Bus /LiteDiagLines R-2R Resistor Ladder DA1 Register DA0E DA1E DA 0 DA 1 DA0E, DA1E: Bits in the DACON register Figure 19.1 D/A Converter

Page 258 974fo5002,80.peS00.1.veR 0010-4020B90JER 20. CRC Calculation)T68/C23M,68/C23M(puorG68/C23M CRC Calculation and Setup Procedure to Generate CRC Code for "80C416" CRC Code : a remainder of a division, (1) Inverse a bit position of "80C416" per byte by program (2) Set "000016" (default value) CRCD register CRCD register CRCIN register Generator Polynomial : X16 + X12 + X5 + 1 (1 0001 0000 0010 00012) value of the CRCIN register with inversed bit position generator polynomial CRC Calculation for M32C Setting Steps Details of CRC Calculation (3) Set "0116" Bit position of the CRC code for "8016" (918816) is inversed to "118916", which is stored into the CRCD register in 3rd cycle. CRCD register Generator Polynomial data 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 - 1 = 1 CRCIN register (4) Set "2316" CRC Code 1 0001 0000 0010 0001 1000 1000 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 Bit position of the CRC code for "80C4 16" (825016) is inversed to "0A4116", which is stored into the CRCD register in 3rd cycle. As shown in (3) above, bit position of "0116" (000000012) written to the CRCIN register is inversed and becomes "100000002". Add "1000 0000 0000 0000 0000 00002", as "100000002" plus 16 digits, to "000016" as the default value of the CRCD register to perform the modulo-2 division. "0001 0001 1000 10012 (118916)", the remainder "1001 0001 1000 10002 (918816)" with inversed bit position, can be read from the CRCD register. When going on to (4) above, "23 16 (001000112)" written in the CRCIN register is inversed and becomes "110001002". Add "1100 0100 0000 0000 0000 00002", as "110001002" plus 16 digits, to "1001 0001 1000 10002" as a remainder of (3) left in the CRCD register to perform the modulo-2 division. "0000 1010 0100 0001 2 (0A4116)", the remainder with inversed bit position, can be read from CRCD register. Modulo-2 Arithmetic is calculated on the law below. b15 b0 b15 b0 b7 b0 118916 b15 b0 b7 b0 0A4116 Figure 20.3 CRC Calculation

Page 259 974fo5002,80.peS00.1.veR 0010-4020B90JER 21. X/Y Conversion)T68/C23M,68/C23M(puorG68/C23M 21. X/Y Conversion The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and inverses high-order bits and low-order bits of a 16-bit data. Figure 21.1 shows the XYC register. The 16-bit XiR register (i=0 to 15) and 16-bit YjR register (j=0 to 15) are allocated to the same address. The XiR register is a write-only register, while the YjR register is a read-only register. Access the XiR and YjR registers from an even address in 16-bit units. Performance cannot be guaranteed if the XiR and YiR registers are accessed in 8-bit units. Function X/Y Control Register Bit NameBit Symbol Symbol Address After Reset XYC 02E0 16 XXXX XX00 2 RW Read Mode Set Bit Write Mode Set Bit Noting is assigned. When write, set to "0". When read, its content is indeterminate. 0 : Data conversion 1 : No data conversion 0 : No bit alignment conversion 1 : Bit alignment conversionXYC1 (b7 - b2) XYC0 RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 21.1 XYC Register

Page 262 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M 22. Intelligent I/O The intelligent I/O is a multifunctional I/O port for time measurement, waveform generating, clock synchro- nous serial I/O, clock asynchronous serial I/O (UART), HDLC data processing and more. The intelligent I/O has one 16-bit base timer for free-running operation, eight 16-bit registers for time mea- surement and waveform generating and two sets of two 8-bit shift registers for communications. Table 22.1 lists functions and channels of the intelligent I/O. Table 22.1 Intelligent I/O Functions and Channels Function Description Time Measurement(1) 8 channels Digital Filter 8 channels Trigger Input Prescaler 2 channels (channel 6 and channel 7) Trigger Input Gate 2 channels (channel 6 and channel 7) Waveform Generating(1) 8 channels Single-Phase Waveform Output Mode 8 channels Phase-Delayed Waveform Output Mode 8 channels SR Waveform Output Mode 8 channels Communication Communication unit 0 Communication unit 1 Clock Synchronous Serial I/O Mode Available UART Mode Not Available Available HDLC Data Processing Mode Available Stepping Motor Control 4 outputs x 4 sets NOTES: 1. The time measurement function and the waveform generating function share a pin. The time measurement function and waveform generating function can be selected for each channel. The communication function is available by a combining multiple channels.

Page 263 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Figures 22.1 shows a block diagram of the intelligent I/O. Figure 22.2 shows a block diagram of the intelligent I/O communication. Figure 22.1 Intelligent I/O Block Diagram G1TM0, G1PO0 Register(1) G1TM1, G1PO1 Register (1) G1TM2, G1PO2 Register (1) G1TM3, G1PO3 Register (1) G1TM4, G1PO4 Register (1) G1TM5, G1PO5 Register (1) G1TM6, G1PO6 Register (1) G1TM7, G1PO 7 Register(1) Base Timer Base timer reset in the communication unit 1 Request by matching the base timer with the G1PO0 register Request from the INT pin Divider 2(n+1) DIV4 to DIV0 fBT1 Edge Select Digital Filter Edge Select Gate Function Gate Function Edge Select Edge Select Edge Select Edge Select Edge Select Edge SelectINPC1 0 BCK1 and BCK0 0010 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 INPC1 1 / ISCLK1 INPC1 2 / ISRxD1 INPC1 3 INPC1 4 INPC1 5 INPC1 6 INPC1 7 BTS BTRE DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 GT GT PR PR Ch0 to Ch7 interrupt request signal OUTC1 0/ISTxD1 /BE1OUT OUTC1 1/ISCLK1 OUTC1 4 OUTC1 2 OUTC1 3 OUTC1 5 OUTC1 6 OUTC1 7 Prescaler Function Prescaler Function Overflow of bit 15 in the base timer Overflow of bit 9 in the base timer 111 000 to 010 111 000 to 010 MOD2 to MOD0 MOD2 to MOD0 DIV4 to DIV0 bits, BCK1 and BCK0 bits : Bits in the G1BCR0 Register BTS : Bit in the G1BCR1 Register CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj Register (j = 0 to 7) MOD2 to MOD0 : Bits in the G1POCRj Register BTRE : Bit in the G1POCR0 Register NOTES: 1. Each register is placed in a reset state after the G1BCR0 register supplies the clock. Communication Unit 1 Communication Unit 0 ISRxD0 ISTxD0 ISCLK0 f2n Two-phase pulse signal is applied Digital Filter Digital Filter Digital Filter Digital Filter Digital Filter Digital Filter Digital Filter PWM Output PWM Output PWM Output PWM Output

Page 264 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Reception Transmission Arbitration Special Interrupt CheckBuffer Register Shift Register Start Bit Generation Circuit Bit Insert Circuit SOF Generation Circuit Stop Bit Generation Circuit Transmit Latch Transmit Data Generation Circuit Clock Wait Control Circuit Transmit Register Transmit Buffer Transmit Register Transmit Buffer Receive Register Receive Buffer Receive Data Generation Circuit Start Bit Check Bit Insert Check Stop Bit Check G1RI Register Receive Register Receive Buffer HDLC Data Receive Interrupt Request Transmit Interrupt Request Receive Interrupt Request Special Communication Interrupt Request Comparator (8bit)Comparator (8bit)Comparator (8bit)Comparator G1CMP0 Register (8bit)G1CMP0 Register (8bit)G1CMP0 Register (8bit)G1CMP3 Register G1RB Register G1TO Register G1TB Register (Transmit Buffer Register) G1DR Register (Receive Data Register) G1TCRC Register G1RCRC Register Data Selector Data Selector Reception ISCLK0 ISRxD0 ISTxD0 Comparator Comparator Comparator Comparator G0CMP0 register G0CMP0 register G0CMP0 register G0CMP3 Register Buffer Register Shift Register Bit Insert Circuit SOF Generation Circuit Transmit Latch Transmit Data Generation Circuit G0TCRC Register Data Selector Clock Wait Control Circuit Transmit Register Transmit Buffer G0TO Register Transmit Register Transmit Buffer G0RB Register Receive Register Receive Buffer Receive Data Generation Circuit Bit Insert Check G0RCRC RegisterG0RI Register CCS1 and CCS0 Receive Register Receive Buffer Communication Unit 0 Communication Unit 1 HDLC Data Receive Interrupt Request HDLC Data Transmit Interrupt Request Transmit Interrupt Request SIO0TR (1) G0TOR (1) SIO0RR (1) SRT0R (1) G0RIR (1) HDLC Data Transmit Interrupt Request Receive Interrupt Request Special Communication Interrupt Request Transmission G0DR Register (Receive Data Register) f2n 01f1 G0TB Register (Transmit Buffer Register) Data Selector TXSL RXSL CKDIR Arbitration ISCLK1 ISRxD1 CKDIR f2n CCS3 and CCS2 f1 01 RXSL TXSL CKDIR : Bit in the GiMR Register (i=0,1) TXSL, RXSL : Bits in the GiEMR Register CCS1 and CCS0 : Bits in the CCS Register Polarity InverseGenerated Clock in the Channel i (i=1 to 3) Transmit Operation Clock Receive Operation Clock Polarity Inverse ISTxD1 Special Interrupt Check Transmit Operation Clock Receive Operation Clock SIO1TR (1) G1TOR (1) G1RIR (1) SIO1RR (1) SRT1R (1) NOTES: 1. See Figure 11.14. Figure 22.2 Intelligent I/O Communication Block Diagram

Page 265 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Figures 22.3 to 22.8 show registers associated with the intelligent I/O base timer, the time measurement function and waveform generating function. (For registers associated with the communication function, see Figures 22.19 to 22.28.) Figure 22.3 G1BT Register and G1BCR0 Register Base Timer Register 1(2) Symbol Address After Reset G1BT 012116 - 012016 Indeterminate RW RW Function Setting Range 000016 to FFFF16 b8b15 b7 When the base timer is counting: When read, the value of the base timer can be read. When write, the counter starts counting from the value written. When the base timer is reset, the G1BT register is set to "0000 16"(1). When the base timer is reset: The G1BT register is set to "0000 16" but value is indeterminate. No value is written(1). NOTES: 1. The base timer stops only when the BCK1 and BCK0 bits in the G1BCR0 register are set to "002" (clock stopped). The base timer counts when the BCK1 and BCK0 bits are set to a value other than "002". When the BTS bit in the G1BCR1 register is set to "0", the base timer is reset continually, remaining set to "0000 16". This, in effect, places the base timer in a "no counting" state. When the BTS bit is set to "1", this state is cleared and counting starts. 2. The G1BT register reflects the base timer value after one half fBT1 cycle. Base Timer Control Register 10 Symbol Address After Reset G1BCR0 0122 16 00 16 RW RW RW RW RW RW RW RW RWBit Name FunctionBit Symbol : Clock stops : Do not set to this value : Two-phase pulse signal is applied (1) : f1 BCK0 BCK1 DIV0 Count Source Select Bit DIV1 Count Source Divide Ratio Select Bit DIV2 DIV3 IT Base Timer Interrupt Select Bit 0 : Bit 15 overflows 1 : Bit 14 overflows DIV4 If setting value is n (n = 0 to 31), count source is divided by 2(n + 1). No division if n=31. (n=0) 0 0 0 0 0 : Divide-by-2 (n=1) 0 0 0 0 1 : Divide-by-4 (n=2) 0 0 0 1 0 : Divide-by-6 (n=30) 1 1 1 1 0 : Divide-by-62 (n=31) 1 1 1 1 1 : No division b6 b5 b4 b3 b2 NOTES: 1. This setting can be used only when the UD1 and UD0 bits in the G1BCR1 register are set to "102" (two-phase signal processing mode). Do not set the BCK1 and BCK0 bits to "102" when setting the UD1 and UD0 bits to "002" (counter increment mode) or "012" (Counter increment/decrement mode). b7 b6 b5 b4 b3 b2 b1 b0

Page 266 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Figure 22.4 G1BCR1 Register Base Timer Control Register 11 Symbol Address After Reset G1BCR1 012316 X000 000X2 RW RW RW RW RW RW RW Bit Name FunctionBit Symbol RST1 (b0) (b3) (b7) RST2 Base Timer Start BitBTS UD0 UD1 Base Timer Reset Cause Select Bit 1 Base Timer Reset Cause Select Bit 2 Counter Increment/ Decrement Control Bit 0: Base timer is reset 1: Base timer starts counting : Counter increment mode : Counter increment/decrement mode : Two-phase pulse signal processing mode (3) : Do not set to this value Reserved Bit Set to "0" NOTES: 1. The base timer is reset after two fBT1 clock cycles when the base timer value matches the G1PO0 register setting. (See Figure 22.7 for details on the G1PO0 register.) When the RST1 bit is set to "1", the G1POj register (j=1 to 7) for the waveform generating function and communication function must be set to a value smaller than the G1PO0 register. 2. The IPSA_0 bit in the IPSA register can select the INT0 or INT1 pin. 3. In two-phase pulse signal processing mode, the base timer is not reset, even though the RST1 bit is set to "1", if the counter is decremented after two clock cycles when the base timer value matches the G1PO0 register setting. 0: The base timer is not reset by matching with the G1PO0 register 1: The base timer is reset by matching with the G1PO0 register (1) 0: The base timer is not reset by applying "L" to the INT0 or INT1 pin 1: The base timer is reset by applying "L" to the INT0 or INT1 pin(2) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0

Page 267 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Figure 22.5 G1TMCR0 to G1TMCR7 Registers, G1TPR6 and G1TPR7 Registers Time Measurement Control Register 1j (j=0 to 7) Symbol G1TMCR0 to G1TMCR3 G1TMCR4 to G1TMCR7 Address 0118 16, 011916, 011A16, 011B16 011C16, 011D16, 011E16, 011F16 After Reset 0016 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol CTS0 CTS1 DF0 Time Measurement Trigger Select Bit DF1 Gate Function Select Bit(1)GT GOC PR GSC Digital Filter Function Select Bit Gate Function Clear Select Bit(1, 2, 3) 0 : Gate function is not used 1 : Gate function is used Gate Function Clear Bit (1, 2) Prescaler Function Select Bit (1) : No time measurement : Rising edge : Falling edge : Both edges : No digital filter : Do not set to this value : f BT1 : f1 0 : Not cleared 1 : The gate is cleared when the base timer matches the GiPOk register The gate is cleared by setting the GSC bit to "1" 0 : Not used 1 : Used NOTES: 1. The GT, GOC, GSC and PR bits in the G1TMCR6 and G1TMCR7 registers can be used to select these functions. Set all bits 7 to 4 in the G1TMCR0 to G1TMCR5 registers to "0". 2. The GOC and GSC bits are enabled only when the GT bit is set to "1". 3. The GOC bit is set to "0" after the gate function is cleared. See Figure 22.7 about the G1POk register (k=4 when j=6 and k=5 when j=7). b7 b6 b5 b4 b3 b2 b1 b0 Time Measurement Prescaler Register 1j (j=6,7) Symbol Address After Reset G1TPR6, G1TPR7 0124 16, 012516 0016 RW RW Function Setting Range If the setting value is n, the base timer value is stored into G1TMj register whenever a trigger input is counted by n+1 (1) 0016 to FF16 NOTES: 1. The first prescaler, after the PR bit setting in the G1TMCRj register is changed from "0" (not used) to "1" (used), may be divided by n rather than n+1. The subsequent prescaler is divided by n+1. b7 b0

Page 268 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Figure 22.6 G1TM0 to G1TM7 Registers and G1POCR0 to G1POCR7 Registers Waveform Generating Control Register 1j (j=0 to 7) Symbol Address After Reset G1POCR0 0110 16 0000 X0002 G1POCR1 to G1POCR3 0111 16, 011216, 011316 0X00 X000 2 G1POCR4 to G1POCR7 0114 16, 011516, 011616, 011716 0X00 X000 2 RW RW RW RW RW RW RW Bit Name FunctionBit Symbol MOD0 MOD1 MOD2 (b3) Operating Mode Select Bit Output Initial Value Select Bit(6)IVL RLD INV 0: "L" output as default value 1: "H" output as default value RWBase Timer Reset Enable Bit(4)BTRE 0: Disables base timer reset when bit 15 in the base timer overflows 1: Enables base timer reset when bit 9 in the base timer overflows (7) Inverse Output Function Select Bit(5) : Single waveform output mode : SR waveform output mode (1) : Phase-delayed waveform output mode : Do not set to this value : Do not set to this value : Do not set to this value : Do not set to this value (2) : Use communication function output (3) 0: Output is not inversed 1: Output is inversed G1POj Register Value Reload Timing Select Bit NOTES: 1. This setting is enabled only for even channels. In SR waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. Even channels provides waveform output. Odd channels provides no waveform output. 2. To receive data in UART mode, set the G1POCR2 register to "0000 0110 2". 3. This setting is enabled only for channels 0 and 1. To use the ISTxD1 pin, set the MOD2 to MOD0 bits in the G1POCR0 register to "1112". To use the ISCLK1 pin for an output, set the MOD2 to MOD0 bits in the G1POCR1 register to"1112". Do not set the MOD2 to MOD0 bits to "1112" except in channels 0 and 1 and for the communication function. 4. The BTRE bit is provided in the G1POCR0 register only. Set each bit 6 in the G1POCR1 to G1POCR7 registers to "0". 5. The inverse output function is the final step in waveform generating process. When the INV bit is set to "1", an "H" signal is provided a default output by setting the IVL bit to "0"; and an "L" signal is provided by setting it to "1". 6. To provide either "H" or "L" signal output set in the IVL bit, set the FSCj bit in the G1FS register to "0" (waveform generating function selected) and IFEj bit in the G1FE register to "1" (channel j function enabled). Then set the IVL bit to "0" or "1". 7. When the BTRE bit is set to "1", set the BCK1 and BCK0 bits in the G1BCR0 register to "11 2" (f1) and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode). Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0: Reloads the G1POj register when value is written 1: Reloads the G1POj register when the base timer is reset b7 b6 b5 b4 b3 b2 b1 b0 Time Measurement Register 1j (j=0 to 7) RW RO Function Setting Range b15 b8 Symbol G1TM0 to G1TM2 G1TM3 to G1TM5 G1TM6, G1TM7 Address 0101 16 - 010016, 010316 - 010216, 010516 - 010416 010716 - 010616, 010916 - 010816, 010B16 - 010A16 010D 16 - 010C16, 010F16 - 010E16 After Reset Indeterminate Indeterminate Indeterminate The base timer value is stored every measurement timing b7 b0

Page 269 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Figure 22.7 G1PO0 to G1PO7 Registers and G1FS Register Waveform Generating Register 1j (j=0 to 7) Symbol G1PO0 to G1PO2 G1PO3 to G1PO5 G1PO6 to G1PO7 RW RW Function Setting Range b15 b8 Address 010116-010016, 010316-010216, 010516-010416 010716-010616, 010916-010816, 010B16-010A16 010D 16-010C16, 010F16-010E16 After Reset Indeterminate Indeterminate Indeterminate

When the RLD bit in the G1POCRj register is set to "0", value is reloaded into the G1POj register for output as soon as written, for example, a waveform output, reflecting the value.
When the RLD bit is set to "1", the value is reloaded when the base timer is reset. The value written can be read until reloading. b7 b0 000016 to FFFF 16 Function Select Register 1 Symbol Address After Reset G1FS 0127 16 00 16 RW RW RW RW RW RW RW RW RW Bit NameBit Symbol b7 b6 b5 b3 b2 b1b4 b0 FSC0 FSC1 FSC2 Channel 0 Time Measure- ment/Waveform Generating Function Select Bit FSC3 FSC4 FSC5 FSC7 Function FSC6 0 : Selects the waveform generating function 1 : Selects the time measurement function Channel 1 Time Measure- ment/Waveform Generating Function Select Bit Channel 2 Time Measure- ment/Waveform Generating Function Select Bit Channel 3 Time Measure- ment/Waveform Generating Function Select Bit Channel 4 Time Measure- ment/Waveform Generating Function Select Bit Channel 5 Time Measure- ment/Waveform Generating Function Select Bit Channel 6 Time Measure- ment/Waveform Generating Function Select Bit Channel 7 Time Measure- ment/Waveform Generating Function Select Bit

Page 270 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M Function Enable Register 1 Symbol Address After Reset G1FE 0126 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Bit NameBit Symbol IFE0 IFE1 IFE2 Channel 0 Function Enable Bit IFE3 IFE4 IFE5 IFE7 Function IFE6 0 : Disables functions for channel j 1 : Enables functions for channel j (j=0 to 7) Channel 1 Function Enable Bit Channel 2 Function Enable Bit Channel 3 Function Enable Bit Channel 4 Function Enable Bit Channel 5 Function Enable Bit Channel 6 Function Enable Bit Channel 7 Function Enable Bit Figure 22.8 G1FE Register

Page 271 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Base Timer))T68/C23M,68/C23M(puorG68/C23M

22.1 Base Timer

The base timer is a free-running counter that counts an internally generated count source. Table 22.2 lists specifications of the base timer. Figures 22.3 and 22.4 show registers associated with the base timer. Figure 22.9 shows a block diagram of the base timer. Figure 22.10 shows an example of the base timer in counter increment mode. Figure 22.11 shows an example of the base timer in counter incre- ment/decrement mode. Figure 22.12 shows an example of two-phase pulse signal processing mode. Table 22.2 Base Timer Specifications Item Specification Count Source (fBT1 )f 1 divided by 2(n+1) , two-phase pulse input divided by 2(n+1) n: determined by the DIV4 to DIV0 bits in the G1BCR0 register n=0 to 31; however no division when n=31 Counting Operation The base timer increments the counter value The base timer increments and decrements the counter value Two-phase pulse signal processing Counter Start Condition The BTS bit in the G1BCR1 register is set to "1" (base timer starts counting) Counter Stop Condition The BTS bit in the G1BCR1 register is set to "0" (base timer reset) Base Timer Reset Condition • The value of the base timer matches the value of the G1PO0 register

An low-level ("L") signal is applied to the INT0 or INT1 pin
Bit 15 or bit 9 in the base timer overflows Value when the Base Timer is Reset"000016" Interrupt Request The BT1R bit in the IIO4IR register is set to "1" (interrupt requested) when bit 9, bit 14 or bit 15 in the base timer overflows (See Figure 11.14.) Read from Base Timer • The G1BT register indicates the counter value while the base timer is running
The G1BT register is indeterminate when the base timer is reset Write to Base Timer When a value is written while the base timer is running, the timer counter immediately starts counting from this value. No value can be written while the base timer is reset Selectable Function • Counter increment/decrement mode The base timer starts counting when the BTS bit is set to "1". After reaching to "FFFF 16", the timer counter is then decremented back to "000016". If the RST1 bit in the G1BCR1 register is set to "1" (the base timer is reset by matching with the G1PO0 register), the timer counter starts decrementing in two counts after the base timer matches the G1PO0 register. The base timer increments the counter value again when the timer counter reaches "0000 16." (See Figure 22.11.)
Two-phase pulse processing mode Two-phase pulse signals from P76 and P77 pins or P80 and P81 pins are counted as well. (See Figure 22.12.) The IPSA_0 bit in the IPSA register controls input pin selection. (Refer to 24. Programmable I/O Ports) The timer increments counter on all edge The timer decrements counter on all edges P80 (P76) P81 (P77)

Page 272 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Base Timer))T68/C23M,68/C23M(puorG68/C23M Figure 22.9 Base Timer Block Diagram Table 22.3 Base Timer Associated Register Settings (Also applies when using time measurement function, waveform generating function and communication function) Register Bit Function G1BCR0 BCK1, BCK0 Select count source DIV4 to DIV0 Select divide ratio of count source IT Select the base timer interrupt G1BCR1 RST2, RST1 Select source for a base timer reset BTS Used to start the base timer independently UD1, UD0 Select how to count G1POCR0 BTRE Select source for a base timer reset G1BT - Read or write base timer value Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register). G1POCR0 MOD2 to MOD0 Set to "000 2" (single-phase waveform output mode) G1PO0 - Set reset cycle G1FS FSC0 Set to "0" (waveform generating function) G1FE IFE0 Set to "1" (channel operation start) f1 2(n+1) Divider RST1 RST2 Apply "L" to the INTi Pin Base Timer Interrupt Request BCK1 and BCK0 IT BTS Bit Apply the Two-Phase Pulse Signal (See the BT1R bit on Figure 11.14) Overflow Signal Base Timer Reset fBT1 BCK1 and BCK0, IT : Bits in the G1BCR0 register RST2 to RST0, BTS : Bits in the G1BCR1 register BTRE : Bit in the G1POCR0 register BTRE Base Timer b14 b15 Matching with the G1PO0 Register (i=0,1)

Page 273 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Base Timer))T68/C23M,68/C23M(puorG68/C23M Figure 22.10 Counter Increment Mode FFFF 16 800016 Base Timer 000016 The above applies to the following conditions:

The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
The UD1 and UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) The above applies to the following conditions:
The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
The UD1 and UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) (2) When the IT bit is set to "1" (bit 14 in the base timer overflows) (1) When the IT bit in the G1BCR0 register is set to "0" (bit 15 in the base timer overflows) "1" "0" "0" "1" Write "0" by program if setting to "0" FFFF 16 800016Base Timer 000016 Bit 14 Overflow Signal BT1R bit in IIO4IR register Bit 15 Overflow Signal BT1R bit in IIO4IR register "1" "0" "0" "1" 400016 C000 16 Write "0" by program if setting to "0"

Page 274 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Base Timer))T68/C23M,68/C23M(puorG68/C23M Bit 15 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" (1) When the IT bit in the G1BCR0 register is set to "0" (bit 15 in the base timer overflows) Bit 14 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" (2) When the IT bit is set to "1" (bit 14 in the base timer overflows) FFFF 16 800016 Base Timer Base Timer 000016 400016 C000 16 FFFF 16 800016 Base Timer The above applies to the following conditions:

The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) The above applies to the following conditions:
The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) (3) When the RST1 bit in the G1BCR1 register is set to "1" (the base timer is reset by matching with the G1PO0 register) 800016 000016 800216 The above applies to the following conditions:
Value of G1PO0 register: "800016"
The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) Figure 22.11 Counter Increment/Decrement Mode

Page 275 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Base Timer))T68/C23M,68/C23M(puorG68/C23M Figure 22.12 Base Timer Operation in Two-phase Pulse Signal Processing Mode (1) When the base timer is reset while the base timer increments the counter value (2) When the base timer is reset while the base timer decrements the counter value mBase TImer min 1 µs (Note 1) min 1 µs m+1 1 2 0 Set to "0" in this timing The base timer starts counting P80 (P76)(2) (A-phase) P81 (P77)(2) (B-phase) INT1 (Z-phase) Set to "1" in this timing min 1 µs (Note 1) min 1 µs mm - 1 FFFF 16 FFFE 160 Set to "0" in this timing NOTES: 1. 1.5 fBT1 clock cycles or more are required. 2. Select either port by setting the IPSA_0 bit in the IPSA register. The base timer starts counting Set to "FFFF16" in this timing Input Waveform ( ) When selects no division with the divider by 2(n+1) "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" fBT1 Base TImer P80 (P76)(2) (A-phase) P81 (P77)(2) (B-phase) INT1 (Z-phase) Input Waveform When selects no division with the divider by 2(n+1) fBT1 "H" "L" ( )

Page 276 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Time Measurement Function))T68/C23M,68/C23M(puorG68/C23M

22.2 Time Measurement Function

When external trigger is applied, the base timer value is stored into the G1TMj register (j=0 to 7). Table 22.4 shows specifications of the time measurement function. Tables 22.5 and 22.6 list pin settings of the time measurement function. Figures 22.13 and 22.14 show operation examples of the time measurement func- tion. Figure 22.15 shows an operation example of the prescaler function and gate function. Table 22.4 Time Measurement Function Specifications Item Specification Measurement Channel Channels 0 to 7 Trigger Input Polarity Rising edge, falling edge and both edges of the INPC1j pin Measurement Start Condition The IFEj bit in the G1FE register is set to "1" (channel j function enabled) while the FSCj bit (j=0 to 7) in the G1FS register is set to "1" (time measurement function selected) Measurement Stop Condition The IFEj bit is set to "0" (channel j function disabled) Time Measurement Timing • No prescaler: every time a trigger signal is applied

Prescaler (for channel 6 and channel 7): every G1TPRk register (k=6,7) value +1 times a trigger signal is applied Interrupt Request Generating TimingThe TM1jR bit in the interrupt request register (See Figure 11.14) is set to "1" (interrupt requested) at time measurement timing INPC1j Pin Function Trigger input pin Selectable Function • Digital filter function The digital filter samples a trigger input signal level every f1 or fBT1 cycles and passes pulse signals, matching trigger input signal level three times
Prescaler function (for channel 6 and channel 7) Time measurement is executed every G1TPRk register value +1 times a trigger signal is applied
Gate function (for channel 6 and channel 7) After time measurement by the first trigger input, trigger input cannot be accepted. However, while the GOC bit in the G1TMCRk register is set to "1" (gate cleared by matching the base timer with the G1POp register (p=4 when k=6, p=5 when k=7), trigger input can be accepted again by matching the base timer value with the G1POp register setting or by setting the GSC bit in the G1TMCRk register is set to "1"

Page 277 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Time Measurement Function))T68/C23M,68/C23M(puorG68/C23M Table 22.5 Pin Settings for Time Measurement Function Pin Bit and Setting PS1, PS2, PS5, PS8 RegistersPD7, PD8, PD11, PD14 Registers IPS Register P70/INPC16 PS1_0 = 0 PD7_0 = 0 IPS1 = 0 P71/INPC17 PS1_1 = 0 PD7_1 = 0 P73/INPC10 PS1_3 = 0 PD7_3 = 0 P74/INPC11 PS1_4 = 0 PD7_4 = 0 P75/INPC12 PS1_5 = 0 PD7_5 = 0 P76/INPC13 PS1_6 = 0 PD7_6 = 0 P77/INPC14 PS1_7 = 0 PD7_7 = 0 P81/INPC15 PS2_1 = 0 PD8_1 = 0 P110/INPC10 PS5_0 = 0 PD11_0 = 0 IPS1 = 1 P111/INPC11 PS5_1 = 0 PD11_1 = 0 P112/INPC12 PS5_2 = 0 PD11_2 = 0 P113/INPC13 PS5_3 = 0 PD11_3 = 0 P140/INPC14 PS8_0 = 0 PD14_0 = 0 P141/INPC15 PS8_1 = 0 PD14_1 = 0 P142/INPC16 PS8_2 = 0 PD14_2 = 0 P143/INPC17 PS8_3 = 0 PD14_3 = 0 Table 22.6 Time Measurement Function Associated Register Settings Register Bit Function G1TMCRj CTS1, CTS0 Select a time measurement trigger DF1, DF0 Select the digital filter function GT, GOC, GSC Select the gate function PR Select the prescaler function G1TPRk - Setting value of the prescaler G1FS FSCj Set to "1" (time measurement function) G1FE IFEj Set to "1" (channel j function enabled) j = 0 to 7 k = 6, 7 Bit configurations and functions vary with channels used. Registers associated with the time measurement function must be set after setting registers associated with the base timer.

Page 278 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Time Measurement Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.13 Time Measurement Function (1) FFFF 16 p p n n m m Base Timer Signal Applied to the INPC1j Pin 000016 G1TMj Register TM1jR Bit in the IIOiIR Register i= 0 to 4, 8 to 10 j= 0 to 7 The above applies to the following conditions: The CTS1 and CTS0 bits in the G1TMCRj registers are set to "012" (rising edge). The PR bit is set to "0" (no prescaler used) and the GT bit is set to "0" (no gate function used). The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset). The UD1 and UD0 bits are set to "002" (counter increment mode). Write "0" by program if setting to "0" To set the base timer to "000016" (setting the RST1 bit to "1" and the RST2 bit to "0") when the base timer value matches the G1PO0 register setting, the base timer is set to "0000 16" after it reaches the G1PO0 register value +2. "H" "L" "1" "0"

Page 279 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Time Measurement Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.14 Time Measurement Function (2) n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n+5 n+8 n-2 n-1 n n+1 n+2 n+3 n+4 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 nn + 2 n+5 n+8 n+12 Delayed by max. 1 clock fBT1 Base timer G1TMj register (1) When selecting the rising edge as a time measurement trigger (The CTS1 and CTS0 bits in the G1TMCRj register (j=0 to 7) are set to "012") TM1jR bit(1) (Note 2) (2) When selecting both edges as a time measurement trigger (The CTS1 and CTS0 bits are set to "112") Maximum 3.5 f1 or fBT1 (1) clock cycles (3) Trigger signal when using the digital filter (The DF1 and DF0 bits in the G1TMCRj register are set to "102" or "112") Signal, which does not match three times, is stripped off fBT1 Base timer INPC1j pin G1TMj register TM1jR bit(1) f1 or fBT1 (1) INPC1j pin Trigger signal after passing the digital filter NOTES: 1. Bits in the IIO0IR to IIO4IR, IIO08IR to IIO10IR registers. See Figure 11.14 about the TM1jR bit. 2. No interrupt is generated if the microcomputer receives a trigger signal when the TM1jR bit is set to "1". However, the value of the G1TMj register changes. NOTES: 1. f BT1 when the DF1 and DF0 bits are set to "102", and f1 when to "112". The trigger signal is delayed by the digital filter Write "0" by program if setting to "0" Write "0" by program if setting to "0" n+5 n+6 (Note 2) "H" "L" "H" "L" "1" "0" "1" "0" "H" "L" "H" "L" INPC1j pin n+6 NOTES: 1. Bits in the IIO0IR to IIO4IR, IIO8IR to IIO10IR registers. See Figure 11.14 about the TM1jR bit. 2. Input pulse applied to the INPC1j pin requires 1.5 f BT1 clock cycles or more.

Page 280 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Time Measurement Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.15 Prescaler Function and Gate Function fBT1 Base Timer TM1jR bit(2) G1TMj register Internal time measurement trigger Prescaler(1) (1) With the Prescaler Function (When the G1TPRj register (j=6, 7) is set to "0216", the PR bit in the G1TMCRj register is set to "1") fBT1 Base Timer INPC1j pin input Internal time measurement trigger IFEj bit in G1FE register Signal to match G1POk register Gate control signal G1TMj register TM1jR bit(1) This trigger input is disabled due to the gate function FFFF 16 000016 n-2 n-1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+14 n n+12 NOTES: 1. This applies to cycles following the first cycle the G1TPRj register decrements after the PR bit in the G1TMCRj register is set to "1" (prescaler used). 2. Bits in the IIO0IR to IIO4IR, IIO8IR to IIO10IR registers. See Figure 11.14 for the TM1jR bit. (2) With the Gate Function (The gate function is cleared by matching the base timer with the G1POk register (k=4, 5). the GT bit in the G1TMCRj register is set to "1", the GOC bit is set to "1") INPC1j pin input Gate GateGate cleared n+1 n+12 n+13 Write "0" by program if setting to "0" Write "0" by program if setting to "0" NOTES: 1. Bits in the IIO0IR to IIO4IR, IIO8IR to IIO10IR registers. See Figure 11.14 for the TM1jR bit. n Value of the G1POk register "H" "L" "H" "L" "1" "0" "1" "H" "L" "1" "0" "H" "L" "H" "L" "H" "L" "0"

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22.3 Waveform Generating Function

Waveforms are generated when the value of the base timer matches that of the G1POj register (j=0 to 7). The waveform generating function has the following three modes :

Single-phase waveform output mode
Phase-delayed waveform output mode
Set/Reset waveform output (SR waveform output) mode Table 22.7 lists pin settings of the waveform generating function. Table 22.8 lists registers associated with the waveform generating function. Table 22.7 Pin Settings for Waveform Generating Function Pin Bit and Setting PS1, PS2, PS5 to PS8 PSL1, PSL2 Registers PSC, PSC2 Registers PSD1 Register Registers P70/OUTC1 6 PS1_0 = 1 PSL1_0 = 0 PSC_0 = 1 PSD1_0=1 P71/OUTC1 7 PS1_1 = 1 PSL1_1 = 0 PSC_1 = 1 PSD1_1=1 P73/OUTC1 0 PS1_3 = 1 PSL1_3 = 0 PSC_3 = 1 - P74/OUTC1 1 PS1_4 = 1 PSL1_4 = 0 PSC_4 = 1 - P75/OUTC1 2 PS1_5 = 1 PSL1_5 = 1 - - P76/OUTC1 3 PS1_6 = 1 PSL1_6 = 0 PSC_6 = 0 PSD1_6=1 P77/OUTC1 4 PS1_7 = 1 PSL1_7 = 1 - - P81/OUTC1 5 PS2_1 = 1 PSL2_1 = 1 PSC2_1=1 - P110/OUTC1 0 PS5_0 = 1 - - - P111/OUTC1 1 PS5_1 = 1 P112/OUTC1 2 PS5_2 = 1 P113/OUTC1 3 PS5_3 = 1 P140/OUTC1 4 PS8_0 = 1 P141/OUTC1 5 PS8_1 = 1 P142/OUTC1 6 PS8_2 = 1 P143/OUTC1 7 PS8_3 = 1 Table 22.8 Waveform Generating Function Associated Register Settings Register Bit Function G1POCRj MOD2 to MOD0 Select waveform output mode IVL Select default output value RLD Select a timing to reload the value of the G1POj register INV Select if output level is inversed G1POj - Select when output waveform is inversed G1FS FSCj Set to "0" (waveform generating function) G1FE IFEj Set to "1" (channel j function enabled) j = 0 to 7 Bit configurations and functions vary with channels used. Registers associated with the waveform generating measurement function must be set after setting registers associated with the base timer.

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22.3.1 Single-Phase Waveform Output Mode

Output signal level of the OUTC1j pin becomes high ("H") when the base timer value matches the G1POj register (j=0 to 7) setting. The "H" signal switches to a low-level ("L") signal when the base timer reaches "0000 16". If the IVL bit in the G1POCRj register is set to "1" ("H" output as default value), an "H" signal output is provided when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the waveform output is inversed. See Figure 22.16 for details on single-phase waveform output mode operation. Table 22.9 lists specifications of single-phase waveform output mode. Table 22.9 Single-Phase Waveform Output Mode Specifications Item Specification Output Waveform(2) • Free-running operation (the RST2 and RST1 bits in the G1BCR1 register are set to "002") Cycle : "L" width : "H" width : m : setting value of the G1POj register (j=0 to 7), 0000 16 to FFFF16

The base timer is cleared to "000016" by matching the base timer with the G1PO0 register (the RST1 bit is set to "1" and the RST2 bit is set to "0") Cycle : "L" width : "H" width : m : setting value of the G1POj register (j=1 to 7), 0000 16 to FFFF16 n : setting value of the G1PO0 register, 000116 to FFFD16 If m ≥ n+2, the output level is fixed to "L" Waveform Output Start Condition(1) The IFEj bit in the G1FE register is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The PO1jR bit in the interrupt request register is set to "1" (interrupt requested) when the base timer value matches the G1POj register setting. (See Figure 11.14) OUTC1j Pin Pulse signal output pin Selectable Function • Default value set function: Set starting waveform output level
Inversed output function: Waveform output signal is inversed and provided from the OUTC1j pin NOTES: 1. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected). 2. When the INV bit in the G1POCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. m fBT1 65536-m f BT1 n+2 f BT1 m f BT1 n+2-m f BT1 65536 f BT1

Page 283 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Waveform Generating Function))T68/C23M,68/C23M(puorG68/C23M FFFF 16 m m fBT1 65536-m f BT1 65536 f BT1 Base Timer (1) Free-Running Operation (The RST2 and RST1 bits in the G1BCR1 register are set to "002") (2) The Base Timer is Reset by Matching the Base Timer with the G1PO0 Registe (The RST1 bit is set to "1" and the RST2 bit is set to "0") 000016 OUTC1j pin(1) OUTC1j pin(2) PO1jR bit in the IIOiIR register PO1jR bit in the IIOiIR register i=0 to 4, 8 to 10; j=0 to 7 m : Setting value of the G1POj register, 000016 to FFFF16 OUTC1j pin m n+2 Base Timer 000016 m fBT1 n+2-m f BT1 n+2 f BT1 i=0 to 4, 8 to 10; j=1 to 7 m : Setting value of the G1POj register, 000016 to FFFF16 n: Setting value of the G1PO0 register, 000116 to FFFD16 The above applies to the following conditions:

The IVL bit in the G1POCRj register is set to "0" ("L" output as default value) and the INV bit is set to "0" (not inversed). The UD1 and UD0 bits are set to "002" (counter increment mode).
m<n+2 NOTES: 1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed) and the IVL bit in the G1POCRi register is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" ("H" output as default value). Write "0" by program if setting to "0" Write "0" by program if setting to "0" "H" "L" "L" "0" "1" "H" "H" "L" "0" "1" The above applies to the following condition:
The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode). Figure 22.16 Single-Phase Waveform Output Mode

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22.3.2 Phase-Delayed Waveform Output Mode

Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj register (j=0 to 7) setting. Table 22.10 lists specifications of phase-delayed waveform output mode. Figure 22.17 lists an example of phase-delayed waveform output mode operation. Table 22.10 Phase-Delayed Waveform Output Mode Specifications Item Specification Output Waveform • Free-running operation (the RST2 and RST1 bits in the G1BCR1 register are set to "002") Cycle : "H" and "L" widths : Setting value of the G1POj (j=0 to 7) register is 000016 to FFFF16

The base timer is cleared to "000016" by matching the base timer with the G1PO0 register (the RST1 bit is set to "1" and the RST2 bit is set to "0") Cycle : "H" and "L" widths : n : setting value of the G1PO0 register, 000116 to FFFD16 Setting value of the G1POj (j=1 to 7) register is 000016 to FFFF16 If G1POj register ≥ n+2, the output level is not inversed Waveform Output Start Condition(1) The IFEj bit (j=0 to 7) in the G1FE register is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The PO1jR bit in the interrupt request register is set to "1" (interrupt requested) when the base timer vslur matches the G1POj register setting. (See Figure 11.14) OUTC1j Pin Pulse signal output pin Selectable Function • Default value set function: Set starting waveform output level
Inversed output function Waveform output level is inversed to output a waveform from the OUTC1j pin NOTES: 1. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected). 65536 x 2 fBT1 65536 f BT1 2(n+2) f BT1 n+2 f BT1

Page 285 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O)T68/C23M,68/C23M(puorG68/C23M FFFF 16 m 65536 fBT1 65536 x 2 f BT1 000016 m n+2 000016 65536 fBT1 m f BT1 n+2 f BT1 n+2 f BT1 2(n+2) f BT1 Base Timer (1) Free-Running Operation (The RST2 and RST1 bits in the G1BCR1 register are set to "002") OUTC1j pin(1) OUTC1j pin(2) PO1jR bit in the IIOiIR register i=0 to 4, 8 to 10; j=0 to 7 m : Setting value of the G1POj register, 000016 to FFFF16 Inverse Inverse Write "0" by program if setting to "0" Inverse Inverse (2) The Base Timer is Reset when the Base Timer Matches the G1PO0 Register (The RST1 bit is set to "1" and the RST2 bit is set to "0") PO1jR bit in the IIOiIR register OUTC1j pin Base Timer Write "0" by program if setting to "0" Inverse i=0 to 4, 8 to 10; j=1 to 7 m : Setting value of the G1POj register, 000016 to FFFF16 n: Setting value of the G1PO0 register, 000116 to FFFD16 The above applies to the following conditions:

The IVL bit in the G1POCRj register is set to "0" ("L" output as default value) and the INV bit is set to "0" (not inversed). The UD1 and UD0 bits are set to "002" (counter increment mode).
m<n+2 Inverse Inverse "H" "L" "H" "H" "1" "0" "L" "L" "1" "0 " NOTES: 1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed) and the IVL bit in the G1POCRj register is set to "0" ("L" output as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" ("H" output as default value). The above applies to the following condition:
The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset) and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode). Figure 22.17 Phase-delayed Waveform Output Mode

Page 286 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Waveform Generating Function))T68/C23M,68/C23M(puorG68/C23M

22.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode

Output signal level of the OUTC1j pin becomes high ("H") when the base timer value matches the G1POj register (j=0, 2, 4, 6) setting. The "H" signal switches to a low-level ("L") signal when the base timer value matches the G1POk register (k=j+1) setting or when the base timer is set to "0000 16". If the IVL bit in the G1POCRj register is set to "1" ("H" output as default value), an "H" signal output is provided when wave- form output starts. If the INV bit is set to "1" (output inversed), the level of the output waveform is inversed. Table 22.11 lists specifications of SR waveform output mode. Figure 22.18 shows an example of a SR waveform output mode operation. Table 22.11 SR Waveform Output Mode Specifications Item Specification Output Waveform(2) • Free-running operation (the RST2 and RST1 bits in the G1BCR1 register are set to "002") (1) m < n "H" width : "L" width : (2) m ≥ n "H" width : "L" width : m : setting value of the G1POj register (j=0, 2, 4, 6 ) n : setting value of the G1POk register (k=j+1)

The base timer is cleared to "000016" by matching the base timer with the G1PO0 register(1) (the RST1 bit is set to "1" and the RST2 bit is set to "0") (1) m < n < p+2 "H" width : "L" width : (2) m < p+2 ≤ n "H" width : "L" width : (3) If m ≥ p+2, the output level is fixed to "L" m : setting value of the G1POj register (j=2, 4, 6), 0000 16 to FFFF16 n : setting value of the G1POk register (k=j+1), 000016 to FFFF16 p : setting value of the G1PO0 register, 000116 to FFFD16 NOTES: 1. When the G1PO0 register resets the base timer, the channel 0 and 1 SR waveform generating functions are not available. 2. When the INV bit in the G1POCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. 3. Waveform from base timer reset until when output level becomes "H". 4. Waveform from when output level becomes "L" until base timer reset. m (3) fBT1 n-m fBT1 + 65536 - n(4) fBT1 65536 - m fBT1 m f BT1 n-m f BT1 m (3) fBT1 + p + 2 - n(4) fBT1 p + 2 - m fBT1 m f BT1

Page 287 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Waveform Generating Function))T68/C23M,68/C23M(puorG68/C23M Table 22.11 SR Waveform Output Mode Specifications (Continued) Item Specification Waveform Output Start Condition(5) The IFEq bit (q=0 to 7) in the G1FE register is set to "1" (channel q function enabled) Waveform Output Stop Condition The IFEq bit is set to "0" (channel q function disabled) Interrupt Request The PO1jR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the G1POj register. The PO1kR bit in the interrupt request register is set to "1" (imterrupt requested) when the value of the base timer matches that of the G1POk register. (See Figure 11.14) OUTC1j Pin Pulse signal output pin Selectable Function • Default value set function: Set starting waveform output level

Inversed output function Waveform output level is inversed to provide a waveform from the OUTC1j pin NOTES: 5. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected).

Page 288 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Waveform Generating Function))T68/C23M,68/C23M(puorG68/C23M FFFF 16 m n n-m fBT1 65536 f BT1 000016 m p+2 n 000016 65536-n+m fBT1 n-m f BT1 p+2-n+m f BT1 p+2 f BT1 (1) Free-Running Operation (The RST2 to RST0 bits in the G1BCR1 register are set to "002") m : Setting value of the G1POj register, 000016 to FFFF16 n: Setting value of the G1POk register, 000016 to FFFF16 Write "0" by program if setting to "0" Write "0" by program if setting to "0" (2) The Base Timer is Reset when the Base Timer Matches the G1PO0 Register (The RST1 bit is set to "1" and the RST2 bit is set to "0") m : Setting value of the G1POj register, 000016 to FFFF16 n: Setting value of the G1POk register, 000016 to FFFF16 p: Setting value of the G1PO0 register, 000116 to FFFD16 Write "0" by program if setting to "0" Write "0" by program if setting to "0" Base timer OUTC1j pin PO1jR bit in the IIOiIR register PO1kR bit in the IIOiIR register Base Timer OUTC1j pin(1) OUTC1j pin(2) PO1jR bit in the IIOiIR register PO1kR bit in the IIOiIR register The above applies to the following conditions:

The IVL bit in the G1POCRj register is set to "0" ("L" output as default value) and the INV bit is set to "0" (not inversed).
The UD1 and UD0 bits are set to "00 2" (counter increment mode).
m<n<p+2 NOTES: 1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed) and the IVL bit in the G1POCRj register is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" ("H" output as default value). "H" "H" "L" "L" "0" "1" "0" "1" "H" "L" "0" "0" "1" "1" The above applies to the following conditions:
The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset) and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode).
m<n Figure 22.18 SR Waveform Output Mode

Page 289 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M

22.4 Communication Unit 0 and 1 Communication Function

In the intelligent I/O communication unit 1, 8-bit clock synchronous serial I/O, 8-bit clock asynchronous serial I/O (UART) or HDLC data processing is available. In the communication unit 0, 8-bit clock synchro- nous serial I/O or HDLC data processing is available. Figures 22.19 to 22.28 show registers associated with the communication function. Receive Input Register i (i=0,1) Symbol Address After Reset G0RI, G1RI 00EC 16, 012C16 Indeterminate RW WO Function Setting Range b7 b0 0016 to FF16Set data to be transmitted to a received data generation circuit Figure 22.19 G0RI and G1RI Registers, G0TO and G1TO Registers Transmit Output Register i (i=0,1) Symbol Address After Reset G0TO, G1TO 00EE 16, 012E16 Indeterminate RW RO Function b7 b0 Can read a data transmitted by a transmitted data generation circuit

Page 290 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.20 G0CR and G1CR Registers, G0RB and G1RB Registers SI/O Communication Control Register i (i=0, 1) Symbol Address After Reset G0CR, G1CR 00EF 16, 012F16 0000 X011 2 RW RW RW RW RW RO RO RO Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its contents is indeterminate. TI TXEPT RI (b3) Transmit Buffer Empty Flag TE RE IPOL OPOL Receive Complete Flag Transmit Enable Bit Receive Enable Bit ISRxD Input Polarity Switch Bit ISTxD Output Polarity Switch Bit 0 : No data in the GiRB register 1 : Data in the GiRB register 0 : Transmit disable 1 : Transmit enable 0 : No inverse 1 : Inverse(1) Transmit Register Empty Flag 0 : Data in the GiTB register 1 : No data in the GiTB register 0 : Data in the transmit register (during transmission) 1 : No data in the transmit register (transmit completed) 0 : No inverse 1 : Inverse (1) NOTES: 1. Set this bit to "1" when using UART mode. b7 b6 b5 b4 b3 b2 b1 b0 0 : Receive disable 1 : Receive enable Function SI/O Receive Buffer Register i (i=0, 1) Bit NameBit Symbol Symbol Address After Reset G0RB, G1RB 00E9 16-00E816, 012916-012816 X000 XXXX XXXX XXXX 2 RW RW RO ROFER Received data OER (b7 - b0) (b11 - b8) (b15) 0 : No overrun error 1 : Overrun error found Nothing is assigned. When read, its content is indeterminate. Nothing is assigned. When read, its content is indeterminate. Framing Error Flag (1) 0 : No framing error 1 : Framing error found Overrun Error Flag b7 b0b15 b8 NOTES: 1. Nothing is assigned in the FER and PER bits in the G0RB register. When read, its content is indeterminate. PER Parity Error Flag(1) 0 : No parity error 1 : Parity error found RO

Page 291 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.22 G0MR and G1MR Registers SI/O Communication Mode Register 0 Symbol Address After Reset G0MR 00ED 16 00 16 RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. Do not set to any bit combinations except the above. GMD0 GMD1 CKDIR (b5 - b3) Communication Mode Select Bit UFORM IRS Internal/External Clock Select Bit Transfer Format Select Bit Transmit Interrupt Cause Select Bit 0 : Internal clock 1 : External clock 0 : LSB first 1 : MSB first : Clock synchronous serial I/O mode : HDLC data processing mode (1) b7 b6 b5 b4 b3 b2 b1 b0 Reserved Bit Set to "0" 000 0 : No data in the G0TB register (TI=1) 1 : Transmission is completed (TXEPT=1) SI/O Communication Mode Register 1 Symbol Address After Reset G1MR 012D 16 00 16 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. In M32C/86, do not set the GMD1 and GMD0 bits to "102" except when using in motor vehicles. GMD0 GMD1 CKDIR Communication Mode Select Bit STPS PRY PRYE UFORM IRS Internal/External Clock Select Bit Stop Bit Length Select Bit Parity Odd/Even Select Bit Parity Enable Select Bit Transfer Format Select Bit Transmit Interrupt Cause Select Bit 0 : Internal clock 1 : External clock 0 : 1 stop bit 1 : 2 stop bits 0 : Parity disabled 1 : Parity enabled 0 : Odd parity 1 : Even parity 0 : LSB first 1 : MSB first : UART mode : Clock synchronous serial I/O mode : Special communication mode (1) : HDLC data processing mode b7 b6 b5 b4 b3 b2 b1 b0 0 : No data in the G1TB register (TI=1) 1 : Transmission is completed (TXEPT=1)

Page 292 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.23 G0EMR and G1EMR Registers SI/O Expansion Mode Register 1(1) Symbol Address After Reset G1EMR 013C 16 00 16 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. The G1EMR register is used in special communication mode or HDLC data processing mode. It must be in a reset state or be set to "0016" in clock synchronous serial I/O mode or UART mode. 2. CRC is reset when data in the G1CMP3 register matches received data. SMODE CRCV ACRC BSINT RXSL TXSL CRC0 CRC1 Synchronous Mode Select Bit Receive Source Switch Bit Transmit Source Switch Bit 0 : Not reset 1 : Reset(2) 0 : Not used 1 : Used 0 : ISRxD1 pin 1 : G1RI register 0 : ISTxD1 pin 1 : G1TO register 0 : Re-synchronous mode not used 1 : Re-synchronous mode CRC Default Value Select Bit 0 : Set to "0000 16" 1 : Set to "FFFF16" CRC Reset Select Bit Bit Stuffing Error Interrupt Select Bit CRC Generation Polynomial Select bit : X8+X 4+X+1 : Do not set to this value : X 16+X 15+X 2+1 : X16+X 12+X 5+1 b7 b6 b5 b4 b3 b2 b1 b0 SI/O Expansion Mode Register 0(1) Symbol Address After Reset G0EMR 00FC 16 00 16 RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. The G0EMR register is used in HDLC data processing mode. It must be in a reset state or set to "0016" in clock synchronous serial I/O mode. 2. CRC is reset when data in the G0CMP3 register matches received data. Reserved Bit Set to "0" RW CRCV (b0) ACRC BSINT RXSL TXSL CRC0 CRC1 Receive Source Switch Bit Transmit Source Switch Bit 0 : Not reset 1 : Reset(2) 0 : Not used 1 : Used 0 : ISRxD0 pin 1 : G0RI register 0 : ISTxD0 pin 1 : G0TO register CRC Default Value Select Bit 0 : Set to "0000 16" 1 : Set to "FFFF16" CRC Reset Select Bit Bit Stuffing Error Interrupt Select Bit CRC Generation Polynomial Select Bit : X8+X4+X+1 : Do not set to this value : X 16+X 15+X 2+1 : X16+X 12+X 5+1 b7 b6 b5 b4 b3 b2 b1 b0

Page 293 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.24 G0ETC and G1ETC Registers SI/O Expansion Transmit Control Register 0(1) Symbol Address After Reset G0ETC 00FF 16 0000 0XXX 2 RW RW RW RW Bit Name FunctionBit Symbol Reserved Bit RW Set to "0" Reserved Bit Set to "0" TCRCE (b3 - b0) (b5) TBSF0 TBSF1 Transmit CRC Enable Bit Transmit Bit Stuffing "1" Insert Select Bit 0 : Not used 1 : Used Transmit Bit Stuffing "0" Insert Select Bit 0 : "1" is not inserted 1 : "1" is inserted 0 : "0" is not inserted 1 : "0" is inserted b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. The G0ETC register is used in HDLC data processing mode. It must be in a reset state or set to "00 16" in clock synchronous serial I/O mode. 0 0 0 SI/O Expansion Transmit Control Register 1(1) Symbol Address After Reset G1ETC 013F 16 0000 0XXX 2 RW RW RO RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. The G1ETC register is used in special communication mode or HDLC data processing mode. It must be in a reset state or set to "0016" in clock synchronous serial I/O mode or UART mode. Reserved Bit When read, its content is indeterminate SOF (b2 - b0) TCRCE ABTE TBSF0 TBSF1 Transmit CRC Enable Bit Arbitration Enable Bit Transmit Bit Stuffing "1" Insert Select Bit 0 : Not used 1 : Used 0 : Not used 1 : Used SOF Transmit Request Bit 0 : No request to transmit SOF 1 : Request to transmit SOF Transmit Bit Stuffing "0" Insert Select Bit 0 : "1" is not inserted 1 : "1" is inserted 0 : "0" is not inserted 1 : "0" is inserted b7 b6 b5 b4 b3 b2 b1 b0

Page 294 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.25 G0ERC and G1ERC Registers SI/O Expansion Receive Control Register i (i=0,1)(1) Symbol Address After Reset G0ERC, G1ERC 00FD 16, 013D16 00 16 RW RW RW RW RW RW RW RW RW Bit Name FunctionBit Symbol NOTES: 1. The GiERC register is used in special communication mode or HDLC data processing mode. It must be set to "0010 0000 2" in clock synchronous serial I/O mode. It must be in a reset state or be set to "0016" in UART mode. 2. When the ACRC bit in the GiEMR register is set to "1" (CRC reset function used), set the CMP3E bit to "1". CMP0E CMP1E CMP2E Data Compare Function 0 Select Bit CMP3E RCRCE RSHTE RBSF0 RBSF1 Receive CRC Enable Bit Receive Shift Operation Enable Bit 0 : Not used 1 : Used 0 : Receive shift operation disabled 1 : Receive shift operation enabled Data Compare Function 1 Select Bit Data Compare Function 2 Select Bit Data Compare Function 3 Select Bit Receive Bit Stuffing "1" Delete Select Bit Receive Bit Stuffing "0" Delete Select Bit 0 : "1" is not deleted 1 : "1" is deleted 0 : "0" is not deleted 1 : "0" is deleted b7 b6 b5 b4 b3 b2 b1 b0 0 : The GiDR register (receive data register) is not compared with the GiCMP0 register 1 : The GiDR register is compared with the GiCMP0 register 0 : The GiDR register (receive data register) is not compared with the GiCMP1 register 1 : The GiDR register is compared with the GiCMP1 register 0 : The GiDR register (receive data register) is not compared with the GiCMP2 register 1 : The GiDR register is compared with the GiCMP2 register 0 : The GiDR register (receive data register) is not compared with the GiCMP3 register 1 : The GiDR register is compared with the GiCMP3 register(2)

Page 295 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.26 G0IRF Register SI/O Special Communication Interrupt Detect Register 0 (1, 2) Symbol Address After Reset G0IRF 00FE 16 00 16 RW RW RW RW RW RW RW RWBit Name FunctionBit Symbol Reserved Bit Reserved Bit Set to "0" Set to "0" NOTES: 1. The G0IRF register is used in HDLC data processing mode. Do not use in clock synchronous serial I/O mode. 2. The SRT0R bit in the IIO4IR register is set to "1" if the BSERR or IRF0 to IRF3 bit is set to "1". BSERR (b1 - b0) (b3) Bit Stuffing Error Detect Flag 0 : Not detected 1 : Detected IRF0 IRF1 IRF2 Interrupt Cause Determination Flag 0 IRF3 Interrupt Cause Determination Flag 1 Interrupt Cause Determination Flag 2 Interrupt Cause Determination Flag 3 b7 b6 b5 b4 b3 b2 b1 b0 0 : The G0DR register (receive data register) does not match the G0CMP0 register 1 : The G0DR register matches the G0CMP0 register 0 : The G0DR register (receive data register) does not match the G0CMP1 register 1 : The G0DR register matches the G0CMP1 register 0 : The G0DR register (receive data register) does not match the G0CMP2 register 1 : The G0DR register matches the G0CMP2 register 0 : The G0DR register (receive data register) does not match the G0CMP3 register 1 : The G0DR register matches the G0CMP3 register 00 0

Page 296 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.27 G1IRF Register, G0TB and G1TB / G0DR and G1DR Registers SI/O Special Communication Interrupt Detect Register 1(1,2) Symbol Address After Reset G1IRF 013E 16 00 16 RW RW RW RW RW RW RW RWBit Name FunctionBit Symbol NOTES: 1. The G1IRF register is used in special communication mode or HDLC data processing mode. It must be in a reset state or set to "0016" in clock synchronous serial I/O mode or UART mode. 2. The SRT1R bit in the IIO4IR register is also set to "1" if the BSERR, ABT or IRF0 to IRF3 bit is set to "1". Reserved Bit Set to "0" ABT BSERR (b1 - b0) Arbitration Lost Detect Flag Bit Stuffing Error Detect Flag 0 : Not detected 1 : Detected 0 : Not detected 1 : Detected IRF0 IRF1 IRF2 Interrupt Cause Determination Flag 0 IRF3 Interrupt Cause Determination Flag 1 Interrupt Cause Determination Flag 2 Interrupt Cause Determination Flag 3 b7 b6 b5 b4 b3 b2 b1 b0 0 : The G1DR register (receive data register) does not match the G1CMP0 register 1 : The G1DR register (receive data register) matches the G1CMP0 register 0 : The G1DR register (receive data register) does not match the G1CMP1 register 1 : The G1DR register (receive data register) matches the G1CMP1 register 0 : The G1DR register (receive data register) does not match the G1CMP2 register 1 : The G1DR register (receive data register) matches the G1CMP2 register 0 : The G1DR register (receive data register) does not match the G1CMP3 register 1 : The G1DR register (receive data register) matches the G1CMP3 register Transmit Buffer (Receive Data) Register (i=0,1) Symbol Address After Reset G0TB, G0DR 00EA 16 Indeterminate G1TB, G1DR 012A16 Indeterminate RW RW Function b7 b0 Set data to be transmitted. In HDLC data processing mode, the receive data register is read by reading the GiTB register. Value is written to the transmit buffer register by writing it to the GiTB register. In HDLC data processing mode, the value set in the GiRI register is transferred to the GiDR register.

Page 297 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.28 G0CMP0 to G0CMP3 Registers and G1CMP0 to G1CMP3 Registers G0MSK0 and G0MSK1 Registers, G1MSK0 and G1MSK1 Registers G0TCRC and G1TCRC Registers, G0RCRC and G1RCRC Registers Data Compare Register ij (i=0,1, j=0 to 3) Symbol Address After Reset G0CMP0 to G0CMP3 00F0 16, 00F116, 00F216, 00F316 Indeterminate G1CMP0 to G1CMP3 013016, 013116, 013216, 013316 Indeterminate RW RW Function Setting Range b7 b0 Data to be compared 0016 to FF16 NOTES: 1. Set the GiMSK0 register to use the GiCMP0 register. Set the GiMSK1 register to use the GiCMP1 register. Data Mask Register ij (i=0,1, j=0,1) Symbol Address After Reset G0MSK0, G0MSK1 00F4 16, 00F516 Indeterminate G1MSK0, G1MSK1 0134 16, 013516 Indeterminate Function Setting Range RW RW b7 b0 Masked data for received data Set incomparable bit to "1" 0016 to FF16 Transmit CRC Code Register i (i=0,1) Symbol Address After Reset G0TCRC, G1TCRC 00FB 16-00FA16, 013B16-013A16 0000 16 Function RW RO Result of the transmit CRC calculation(1, 2) b7b15 b8 NOTES: 1. The calculated result is reset by setting the TE bit in the GiCR register to "0" (transmit disabled). The CRCV bit in the GiEMR register selects a default value. 2. Transmit CRC calculation is performed with each bit of data transmitted while the TCRCE bit in the GiETC register is set to "1" (used). Receive CRC Code Register i (i=0,1) Symbol Address After Reset G0RCRC, G1RCRC 00F9 16-00F816, 013916-013816 Indeterminate Function Result of the receive CRC calculation(1, 2, 3) b7b15 b8 RW RO NOTES: 1. The calculated result is reset by setting the RCRCE bit in the GiERC register to "0" (not used). If the ACRC bit in the GiEMR register is set to "1" (reset), the result is reset by matching data in the GiCMPj register (j=0 to 3) with the received data. 2. The result is reset to the default value selected by the CRCV bit in the GiEMR register before reception starts. 3. Receive CRC calculation is performed with every bit of data received while the RCRCE bit in the GiERC register is set to "1" (used).

Page 298 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.29 CCS Register Communication Clock Select Register Symbol Address After Reset CCS 00F6 16 XXXX 0000 2 RW RW RW RW RWBit Name FunctionBit Symbol Communication Unit 0 Clock Select Bit Communication Unit 1 Clock Select Bit : Do not set to this value : f 1(1) : f2n : f8 : Clock output from the channel i (i=1 to 3) : f 1(1) : f2n : f8 Nothing is assigned. When write, set to "0". When read, its contents is indeterminate. NOTES: 1. This setting is enabled in HDLC data processing mode. Do not set the CCS1 and CC0 bits or CCS3 and CCS2 bits to "01 2" in other modes. CCS0 CCS1 CCS2 CCS3 (b7 - b4) b7 b6 b5 b4 b3 b2 b1 b0

Page 299 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M

22.4.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1)

In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. f8 or f2n can be selected as the communication unit 0 transfer clock. f8, f2n or the clock generated in channels 0 and 3 can be selected as the communication unit 1 transfer clock. Table 22.12 lists specifications of clock synchronous serial I/O mode for the communication units 0 and list pin settings. Figure 22.29 shows an example of transmit and receive operation. Table 22.12 Clock Synchronous Serial I/O Mode Specifications (Communication Units 0 and 1) Item Specification Transfer Data Format Transfer data : 8 bits long Transfer Clock(1) See Tables 22.13 and 22.14 Transmit Start Condition Set registers associated with the waveform generating function, the GiMR and GiERC registers (i=0,1). Then, set as is written below after at least one transfer clock cycle.

Set the TE bit in the GiCR register to "1" (transmit enable)
Set the TI bit in the GiCR register to "0" (data in the GiTB register) Receive Start Condition Set registers associated with the waveform generating function, the GiMR and GiERC registers. Then, set as is written below after at least one transfer clock cycle.
Set the RE bit in the GiCR register to "1" (receive enable)
Set the TE bit to "1" (transmit enable)
Set the TI bit to "0" (data in the GiTB register) Interrupt Request • While transmitting, one of the following conditions can be selected to set the SIOiTR bit to "1" (interrupt requested) (see Figure 11.14) : _ The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data is transferred to the transmit register from the GiTB register _ The IRS bit is set to "1" (transmission completed) and data transfer from the transmit register is completed
While receiving, the following condition can be selected to set SIOiRR bit is set to "1" (data reception is completed): Data is transferred from the receive register to the GiRB register Error Detection Overrun error (2) This error occurs, when the next data reception is started and the 8th bit of the next data is received before reading the GiRB register Selectable Function • LSB first or MSB first Select either bit 0 or bit 7 to transmit or receive data
ISTxDi and ISRxDi I/O polarity inverse ISTxDi pin output level and ISRxDi pin input level are inversed NOTES: 1. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive shift operation enabled). 2. When an overrun error occurs, the GiRB register is indeterminate. When the OPOL bit in the GiCR register is set to "0" (ISTxD output polarity not inversed), the ISTxDi pin puts in a high-level ("H") signal output after selecting operating mode until transfer starts. When the OPOL bit is set to "1" (ISTxD output polarity inversed), the ISTxDi pin puts in a low-level ("L") signal output. Table 22.13 Clock Settings (Communication Unit 0) Transfer Clock G0MR Register CCS Register CKDIR Bit CCS0 Bit CCS1 Bit f8 01 1 f2n(1) 00 1 Input from ISCLK0 1 - - NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

Page 300 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Table 22.14 Clock Settings (Communication Unit 1) Transfer Clock(3) G1MR Register CCS Register CKDIR Bit CCS2 Bit CCS3 Bit fBT1 00 0 2(n+2) f8 01 1 f2n(2) 00 1 Input from ISCLK1 1 - - n: Setting value of the G1PO0 register, 000116 to FFFD16 NOTES: 1. The transfer clock is generated in phase-delayed waveform output mode of the channel 3 waveform generating function. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 3. The transfer clock must be fBT1 divided by six or more. Table 22.15 Register Settings in Clock Synchronous Serial I/O Mode (Communication Units 0 and 1) Register Bit Function Communication Unit 1 Communication Unit 0 CCS CCS1, CCS0 Setting not required when using the Select transfer clock communication unit 1 only CCS3, CSS2 Select transfer clock Setting not required when using the G1BCR0 (2) BCK1, BCK0 Set to "11 2" (f1) communication unit 0 only DIV4 to DIV0 Select divide ratio of count source IT Set to "0" G1BCR1 (2) 7 to 0 Set to "0001 0010 2" G1POCR0 (2) 7 to 0 Set to "0000 0111 2" G1POCR1 (2) 7 to 0 Set to "0000 0111 2" G1POCR3 (2) MOD2 to MOD0 Set to "010 2"(1) IVL Select default ISCLKi output value (1) RLD Set to "0" INV Select whether ISCLKi puts in an inversed signal or not(1) G1PO0 (2) 15 to 0 Set bit rate = transfer clock frequency G1PO3 (2) 15 to 0 Set to a value smaller than the G1PO0 register(1) G1FS (2) FSC3,FSC1,FSC0 Set to "0"(1) G1FE (2) IFE3,IFE1,IFE0 Set to "1"(1) GiERC 7 to 0 Set to "0010 0000 2" GiMR GMD1, GMD0 Set to "01 2" CKDIR Select the internal clock or external clock STPS Set to "0" UFORM Select either LSB first or MSB first IRS Select what cause the transmit interrupt to be generated GiCR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE Set to "1" to enable transmission and reception RE Set to "1" to enable reception IPOL Select ISRxDi input polarity (usually set to "0") OPOL Select ISTxDi output polarity (usually set to "0") GiTB – Write data to be transmitted GiRB – Received data and error flag are stored i = 0 to 1 NOTES: 1. The CKDIR bit in the GiMR register is set to "0" (internal clock). 2. These registers must be set, when f8 or f2n is selected as transfer clock source notwithstanding. fBT1 2 x (setting value + 2) (1)

Page 301 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Table 22.16 Pin Settings in Clock Synchronous Serial I/O Mode (Communication Units 0 and 1)(1) NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output from the communication function used). Table 22.17 Pin Settings (2) Port Function Setting Name PS2 Register PD8 Register IPS Register P80 ISRxD0 input PS2_0 = 0 PD8_0 = 0 IPS0 = 0 Table 22.18 Pin Settings (3) Port Function Setting Register (1) Name PS5 Register PD11 Register IPS Register P110 ISTxD1 output PS5_0 = 1 - - G1POCR0 P111 ISCLK1 input PS5_1 = 0 PD11_1 = 0 IPS1 = 1 - ISCLK1 output PS5_1 = 1 - - G1POCR1 P112 ISRxD1 input PS5_2 = 0 PD11_2 = 0 IPS1 = 1 - NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output from communication function used). Table 22.19 Pin Settings (4) Port Function Setting Name PS9 Register PD15 Register IPS Register P150 ISTxD0 output PS9_0 = 1 - - P151 ISCLK0 input PS9_1 = 0 PD15_2 = 0 IPS0 = 1 ISCLK0 output PS9_1 = 1 - - P152 ISRxD0 input - PD15_2 = 0 IPS0 = 1 troP emaN noitcnuF gnitteS retsigeR )1( 1SP retsigeR 1LSP retsigeR CSP retsigeR 1DSP retsigeR 7DP retsigeR SPI retsigeR 7P 3 tuptuO1DxTSI1 =3_1SP0 =3_1LSP1 =3_CSP- - - 0 RCOP1G 7P 4 tupnI1KLCSI0 =4_1SP- - - 0 =4_7DP0 =1SPI- tuptuO1KLCSI1 =4_1SP0 =4_1LSP1 =4_CSP- - - 1 RCOP1G 7P 5 tupnI1DxRSI0 =5_1SP- - - 0 =5_7DP0 =1SPI- 7p 6 tuptuO0DxTSI1 =6_1SP0 =6_1LSP0 =6_CSP0 =6_1DSP- - - 7p 7 tupnI0KLCSI0 =7_1SP- - - 0 =7_7DP0 =0SPI- tuptuO0KLCSI1 =7_1SP0 =7_1LSP- - -- -

Page 302 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Figure 22.30 Transmit and Receive Operation n+2 m Base Timer The base timer is reset by the channel 0 waveform generation function ISRxD1 Pin Input (received data) ISTxD1 Pin Output (transmit data) ISCLK1 Pin Output (transmit clock in the channel 3 generation function) SIO1TR Bit when IRS=0 (no data in the G1TB register) Write to the G1TB register ISRxDi Pin Input (received data) ISTxDi Pin Output (transmit data) SIOiTR Bit when IRS=0 (no data in the GiTB register) SIOiTR Bit when IRS=1 (transmission completed) Write to the GiTB register The above applies to the following conditions:

The CKDIR bit in the G1MR register is set to "0" (internal clock)
The CCS3 and CCS2 bits in the CCS register are set to "002"
The UFORM bit in the G1MR register is set to "0" (LSB first)
The IPOL and OPOL bits in the G1CR register are set to "0" (no inverse) n : Setting value of the G1PO0 register m : Setting value of the G1PO3 register SIO1TR bit : Bit in the IIO3IR register SIO1RR bit : Bit in the IIO2IR register IRS bit : Bit in the G1MR register The above applies to the following conditions:
The CKDIR bit in the GiMR register is set to "0" (internal clock)
The CCS1 and CCS0 bits or the CCS3 and CCS2 bits in the CCS register are set to "10 2" or "112"
The UFORM bit in the GiMR register is set to "0" (LSB first)
The IPOL and OPOL bits in the GiCR register are set to "0" (no inverse) SIOiTR bit : Bit in the IIOjIR register (j=1, 3) SIOiRR bit : Bit in the IIOkIR register (k=0, 2) IRS bit : Bit in the GiMR register TE bit : Bit in the GiCR register i=0, 1 Bit 1 Bit 2 Bit 6Bit 0 Bit 7 Bit 1 Bit 2 Bit 6Bit 0 Bit7 SIO1RR Bit SIOiRR Bit Write "0" by program if setting to "0" Write "0" by program if setting to "0" Transfer Clock f8, f2n or External Clock TE Bit Bit 1 Bit 2 Bit 6Bit 0 Bit7 Bit 1 Bit 2 Bit 6Bit 0 Bit7 Write "0" by program if setting to "0" Write "0" by program if setting to "0" Write "0" by program if setting to "0" (1) When f8, f2n or External Clock is Selected as the Communication clock (Communication Units 0 and 1) (2) When the Communication Clock is Generated in Channel 3 Phase-Delayed Waveform Output Mode (Communication Unit 1)

Page 303 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M

22.4.2 Clock Asynchronous Serial I/O (UART) Mode (Communication Unit 1)

In clock asynchronous serial I/O (UART) mode, data is transmitted at a desired bit rate and in a desired transfer data format. Table 22.20 lists specifications of UART mode in the communication unit 1. Table Figure 22.30 shows an example of transmit operation. Figure 22.31 shows an example of receive opera- tion. Table 22.20 UART Mode Specifications (Communication Unit 1) Item Specification Transfer Data Format • Character bit (transfer data) : 8 bits long

Start bit : 1 bit long
Parity bit: selected from odd, even, or none
Stop bit : selected length from 1 bit or 2 bits Transfer Clock(1) See Table 22.21 Transmit Start Condition Set registers associated with the waveform generating function, the G1MR and G1ERC registers. Then, set as is written below after at least one transfer clock cycle:
Set the TE bit in the G1CR register to "1" (transmit enable)
Set the TI bit in the G1CR register to "0" (data written to the G1TB register) Receive Start Condition Set registers associated with the waveform generating function, the G1MR and G1ERC registers. Then, set as is written below after at least one transfer clock cycle:
Set the RE bit in the G1CR register to "1" (receive enable)
Detect the start bit Interrupt Request • While transmitting, one of the following conditions can be selected to set the SIO1TR bit to "1" (interrupt requested) (See Figure 11.14.) : _ The IRS bit in the G1MR register is set to "0" (no data in the G1TB register) and data is transferred to the transmit register from the G1TB register. _ The IRS bit is set to "1" (transmission completed) and data transfer from the transmit register is completed
While receiving, the following condition can be selected to set the SIO1RR bit is set to "1": Data is transferred from the receive register to the G1RB register (data reception is completed) Error Detection • Overrun error(2) This error occurs, when the next data reception is started and the final stop bit of the next data is received before reading the G1RB register
Parity error While parity is enabled, this error occurs when the number of "1" in parity and char- acter bits does not match the number of "1" set
Framing error This error occurs when the number of the stop bits set is not detected Selectable Function • Stop bit length The length of the stop bit is selected from 1 bit or 2 bits
LSB first or MSB first Select either bit 0 or bit 7 to transmit or receive data NOTES: 1. The transfer clock must be fBT1 divided by six or more. 2. When an overrun error occurs, the G1RB register is indeterminate.

Page 304 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Table 22.21 Clock Settings (Communication Unit 1) Transfer Clock(3) G1MR Register CCS Register CKDIR Bit CCS2 Bit CCS3 Bit fBT1 00 0 2(n+2) n: Setting value of the G1PO0 register 000116 to FFFD16 NOTES: 1. Transmit clock is generated in phase-delayed waveform output mode of the channel 3 waveform generating function. 2. Received clock is generated when phase-delayed waveform mode of the channel 2 waveform gener- ating function and the channel 2 time measurement function is simultaneously performed. 3. The transfer clock must be fBT1 divided by six or more. Table 22.22 Register Settings in UART Mode (Communication Unit 1) Register Bit Function G1BCR0 BCK1, BCK0 Set to "11 2" (f1) DIV4 to DIV0 Select divide ratio of count source IT Set to "0" G1BCR1 7 to 0 Set to "0001 0010 2" G1POCR0 7 to 0 Set to "0000 0111 2" G1POCR2 7 to 0 Set to "0000 0110 2" G1POCR3 7 to 0 Set to "0000 0010 2" G1TMCR2 7 to 0 Set to "0000 0010 2" G1PO0 15 to 0 Set bit rate = transfer clock frequency G1PO3 15 to 0 Set to a value smaller than the G1PO0 register G1FS FSC3 to FSC0 Set to "0100 2" G1FE IFE3 to IFE0 Set to "1101 2" G1MR GMD1, GMD0 Set to "00 2" CKDIR Set to "0" STPS Select stop bit length PRY, PRYE Select either parity enabled or disabled and either odd parity or even parity UFORM Select either the LSB first or MSB first IRS Select what causes the receive interrupt to be generated G1CR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE Set to "1" to enable transmission and reception RE Set to "1" to enable reception IPOL Set to "1" OPOL Set to "1" G1TB 7 to 0 Write data to be transmitted G1RB 15 to 0 Received data and error flag are stored CCS CCS3, CCS2 Set to "00 2" Table 22.23 Pin Settings in UART Mode Port Function Setting Register (1) Name PS1 Register PSL1 Register PSC RegisterPD7 Register IPS Register P7 3 ISTxD1 output PS1_3 = 1 PSL1_3 = 0 PSC_3 = 1 - - G1POCR0 P7 5 ISRxD1 input PS1_5 = 0 - - PD7_5 = 0 IPS1 = 0 - NOTES: 1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output from communication function used). fBT1 2 x (setting value + 2) (1, 2)

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22.4.3 HDLC Data Processing Mode (Communication Units 0 and 1)

In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are available for HDLC control. f1, f8 or f2n can be selected as the communication unit 0 transfer clock. f1, f8, f2n or clock, generated in the channel 0 or 1, can be selected as the communication unit 1 transfer clock. No pin is used. To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion result is restored after data conversion. If any data are in the GiTO register after data conversion, the conversion is terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless of no data avail- able in the transmit output buffer. A CRC value is calculated every time one bit is converted. If no data is in the GiRI register, received data conversion is terminated. Table 22.28 lists register settings. Table 22.25 HDLC Processing Mode Specifications (Communication Units 0 and 1) Item Specification Input Data Format 8-bit data fixed, bit alignment is optional Output Data Format 8-bit data fixed Transfer Clock See Tables 22.26 and 22.27 I/O Method • During transmit data processing, value set in the GiTB register is converted in HDLC data processing mode and transferred to the GiTO register.

During received data processing, value set in the GiRI register is converted in HDLC data processing mode and transferred to the GiRB register. The value in the GiRI register is also transferred to the GiTB register (received data register). Bit Stuffing During transmit data processing, "0" following five continuous "1" is inserted. During received data processing, "0" following five continuous "1" is deleted. Flag Detection Write the flag data "7E 16" to the GiCMPj register (j=0 to 3) to use the special commu- nication interrupt (the SRTiR bit in the IIO4IR register) Abort Detection Write the masked data "01 16" to the GiMSKj register CRC The CRC1 and CRC0 bits are set to "11 2" (X16+X 12+X 5+1). The CRCV bit is set to "1" (set to "FFFF16").
During transmit data processing, CRC calculation result is stored into the GiTCRC register. The TCRCE bit in the GiETC register is set to "1" (transmit CRC used). The CRC calculation result is reset when the TE bit in the GiCR register is set to "0" (transmit disabled).
During received data processing, CRC calculation result is stored into the GiRCRC register. The RCRCE bit in the GiERC register is set to "1" (receive CRC used). The CRC calculation result is reset by comparing the flag data "7E16" and matching the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR regis- ter is set to "1" (CRC reset). Data Processing Start The following conditions are required to start transmit data processing: Condition • The TE bit in the GiCR register is set to "1" (transmit enable)
Data is written to the GiTB register The following conditions are required to start receive data processing:
The RE bit in the GiCR register is set to "1" (receive enable)
Data is written to the GiRI register

Page 307 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Table 22.25 HDLC Processing Mode Specifications (Continued) Item Specification Interrupt Request(1) During transmit data processing,

One of the following conditions can be selected to set the GiTOR bit in the interrupt request register to "1" (interrupt request) (see Figure 11.14). _ When the IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data is transferred from the GiTB register to the transmit regis- ter (transmit start). _ When the IRS bit is set to "1" (transmission completed) and data transfer from the transmit register to the GiTO register is completed.
When data, which is already converted to HDLC data, is transferred from the receive register of the GiTO register to the transmit buffer, the GiTOR bit is set to "1" During received data processing,
When data is transferred from the GiRI register to the GiRB register (reception completed), the GiRIR bit is set to "1" (See Figure 11.14).
When received data is transferred from the receive buffer of the GiRI register to the receive register, the GiRIR bit is set to "1".
When the GiTB register is compared to the GiCMPj register (j=0 to 3), the SRTiR bit is set to "1". NOTES: 1. See Figure 11.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit. Table 22.26 Clock Settings (Communication Unit 0) Transfer Clock(1) CCS Register CCS0 Bit CCS1 Bit f1 10 f8 11 f2n(2) 01 NOTES: 1. The transfer clock for reception is generated when the RSHTE bit in the G0ERC register is set to "1" (receive shift operation enabled). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Table 22.27 Clock Settings (Communication Unit 1) Transfer Clock(1) CCS Register CCS2 Bit CCS3 Bit fBT1 00 2x(n+2) f1 10 f8 11 f2n(3) 01 n: Setting value of the G1PO0 register, 000116 to FFFD16 NOTES: 1. The transfer clock for reception is generated when the RSHTE bit in the G1ERC register is set to "1" (receive shift operation enabled). 2. The transfer clock is generated in single-phase waveform output mode of the channel 1. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (2)

Page 308 974fo5002,80.peS00.1.veR 0010-4020B90JER 22. Intelligent I/O (Communication Function))T68/C23M,68/C23M(puorG68/C23M Table 22.28 Register Settings in HDLC Processing Mode (Communication Units 0 and 1) Register Bit Function G1BCR0 BCK1, BCK0 Select count source DIV4 to DIV0 Select divide ratio of count source IT Select the base timer interrupt G1BCR1 (1) 7 to 0 Set to "0001 0010 2" G1POCR0 (1) 7 to 0 Set to "0000 0000 2" G1POCR1 (1) 7 to 0 Set to "0000 0000 2" G1PO0 (1) 15 to 0 Set bit rate G1PO1 (1) 15 to 0 Set the timing of the rising edge of the transfer clock. Timing of the falling edge ("H" width of the transfer clock) is fixed. Setting value of the G1PO1 register ≤ Setting value of the G1PO0 register G1FS (1) FSC1, FSC0 Set to "00 2" G1FE (1) IFE1, IFE0 Set to "11 2" GiMR GMD1, GMD0 Set to "11 2" CKDIR Set to "0" UFORM Set to "0" IRS Select what causes the transmit interrupt to be generated GiEMR 7 to 0 Set to "1111 0110 2" GiCR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE Transmit enable bit RE Receive enable bit GiETC SOF Set to "0" TCRCE Select whether transmit CRC is used or not ABTE Set to "0" TBSF1, TBSF0 Transmit bit stuffing GiERC CMP2E to CMP0E S elect whether received data is compared or not CMP3E Set to "1" RCRCE Select whether receive CRC is used or not RSHTE Set to "1" to use it in the receiver RBSF1, RBSF0 Receive bit stuffing GiIRF BSERR, ABT Set to "0" IRF3 to IRF0 Select what causes an interrupt to be generated GiCMP0, 7 to 0 Write "FE 16" to abort processing GiCMP1 GiCMP2 7 to 0 Data to be compared GiCMP3 7 to 0 Write "7E 16" GiMSK0, 7 to 0 Write "01 16" to abort processing GiMSK1 GiTCRC 15 to 0 Transmit CRC calculation result can be read GiRCRC 15 to 0 Receive CRC calculation result can be read GiTO 7 to 0 Data, which is output from a transmit data generation circuit, can be read GiRI 7 to 0 Set data input to a receive data generation circuit GiRB 7 to 0 Received data is stored GiTB 7 to 0 For transmission: write data to be transmitted For reception : received data for comparison is stored CCS CCS1, CCS0 Select the HDLC processing clock CCS3, CCS2 Select the HDLC processing clock i=0, 1 NOTES: 1. These register settings are required when the CCS3 and CCS2 bit in the CCS register are set to "002" (clock output from channel j (j=1 to 3)).

Intelligent I/O (Stepping Moter Control Function) 974fo5002,80.peS00.1.veR 0010-4020B90JER Page 309 )T68/C23M,68/C23M(puorG68/C23M

22.5 Stepping Motor Control Function

The stepping motor control function controls up to four sets of stepping motors by microstepping. Table 22.29 lists pin structure. Table 22.30 lists specifications of the stepping motor control function. Table 22.29 Pin Structure Table 22.30 Stepping Motor Control Function Specifications Item Specification PWM Output 4 sets (4 outputs per set) Count Source f BT1 Carrier Wave Cycle Set the BTRE bit in the G1POCRi register (i=0 to 7) to "1" (base timer reset enabled when bit 10 in the base timer overflows) PWM Output Waveform Primary output width : Inversed level signal width : m: setting value of the G1POi register EMI Countermeasure Delaying PWM output from each set reduces noise generated by output buffer switching 1026 fBTi m f BTi 1026- m f BTi PWM Set Output Pin Function Set 0 GASP0 A-phase positive terminal for Set 0 GASM0 A-phase negative terminal for Set 0 GACP0 B-phase positive terminal for Set 0 GACM0 B-phase negative terminal for Set 0 Set 1 GASP1 A-phase positve terminal for Set 1 GASM1 A-phase negative terminal for Set 1 GACP1 B-phase positive terminal for Set 1 GACM1 B-phase negative terminal for Set 1 Set 2 GASP2 A-phase positive terminal for Set 2 GASM2 A-phase negative terminal for Set 2 GACP2 B-phase positive terminal for Set 2 GACM2 B-phase negative terminal for Set 2 Set 3 GASP3 A-phase positive terminal for Set 3 GASM3 A-phase negative terminal for Set 3 GACP3 B-phase positive terminal for Set 3 GACM3 B-phase negative terminal for Set 3

Intelligent I/O (Stepping Moter Control Function) 974fo5002,80.peS00.1.veR 0010-4020B90JER Page 311 )T68/C23M,68/C23M(puorG68/C23M Figure 22.35 OPS Register Output Port Switch Register Symbol Address After Reset OPS 03DE 16 0000 0000 2 0: PWM generated in channel 0 is output to GASP0 1: Output to GASM0 0: PWM generated in channel 1 is output to GACP0 1: Output to GACM0 0: PWM generated in channel 2 is output to GASP1 1: Output to GASM1 0: PWM generated in channel 3 is output to GACP1 1: Output to GACM1 0: PWM generated in channel 4 is output to GASP2 1: Output to GASM2 0: PWM generated in channel 5 is output to GACP2 1: Output to GACM2 0: PWM generated in channel 6 is output to GASP3 1: Output to GASM3 0: PWM generated in channel 7 is output to GACP3 1: Output to GACM3 RW RW RW RW RW RW RW RW RWFunctionBit Symbol Bit Name b7 b6 b5 b4 b3 b2 b1 b0 OPS0 Port Switch Bit 1 Port Switch Bit 0 Port Switch Bit 3 Port Switch Bit 2 Port Switch Bit 5 Port Switch Bit 4 Port Switch Bit 7 Port Switch Bit 6 OPS1 OPS2 OPS3 OPS4 OPS5 OPS6 OPS7

Intelligent I/O (Stepping Moter Control Function) 974fo5002,80.peS00.1.veR 0010-4020B90JER Page 312 )T68/C23M,68/C23M(puorG68/C23M GASP0 = held fixed "L" GASP0 = PWM output GACP0 = held fixed "L" GACM0 = PWM output GACP0 = held fixed "L" GASP0 = PWM output GASP0 = PWM output GASM0 = held fixed "L" A-phase Current Waveform (Signal Waveform) B-phase Current Waveform (Signal Waveform) (a) (b) (c) (d) (a) (b) (c) (d) Enlarged Settings for the OPS0 to OPS1 bits in the OPS register during periods (a) to (d) Pin status remains unchanged when the OPSi bit (i=0,1) is set to "0". OPS0 bit Periods 00 1 1 OPS1 bit 10 0 1 GASP0 = PWM output GACM0 = held fixed "L" 03FF16 m n Cycle: Signal Waveform GACP0 BT1R Bit in the IIO4IR Register m: Setting value of the G1PO1 register 000016 m fBT1 Set to "0" by program Set the G1PO1 register while processing an interrupt (G1PO1=n) 3FF16+2 fBT1 (3FF16+2)-m fBT1 n f BT1 (3FF16+2)-n fBT1 Figure 22.36 Usage of the OSP Register in Communication Unit 0

Intelligent I/O (Stepping Moter Control Function) 974fo5002,80.peS00.1.veR 0010-4020B90JER Page 313 )T68/C23M,68/C23M(puorG68/C23M Table 22.26 Stepping Motor Control Function-associated Register Settings Register Bit Function G1BCR0 BCK1, BCK0 Set to "11 2" (f1) DIV4 to DIV0 Select divide ratio of count source IT Set to "0" G1BCR1 - Set to "0001 0000 2" G1POCRj MOD2 to MOD0 Set to "000 2" IVL Set to "0" RLD Set to "1" INV Select output inversed or not inversed G1PO0j - Select when the PWM output waveform is inversed G1FS FSCj Set to "0" G1FE (1) IFEj Set to "1" OPS OPSj Set to "1" when the PWM waveform output is selected i=0 to 7 Table 22.27 Pin Settings Pins Settings PS6 and PS7 Registers PSL6 and PSL7 Registers P12 0/GASP0 PS6_0 = 1 PSL6_0 = 1 P12 1/GASM0 PS6_1 = 1 PSL6_1 = 1 P12 2/GACP0 PS6_1 = 1 PSL6_2 = 1 P12 3/GACM0 PS6_3 = 1 PSL6_3 = 1 P12 4/GASP1 PS6_4 = 1 PSL6_4 = 1 P12 5/GASP1 PS6_5 = 1 PSL6_5 = 1 P12 6/GACP1 PS6_6 = 1 PSL6_6 = 1 P12 7/GACM1 PS6_7 = 1 PSL6_7 = 1 P13 0/GASP2 PS7_0 = 1 PSL7_0 = 1 P13 1/GASM2 PS7_1 = 1 PSL7_1 = 1 P13 2/GACP2 PS7_2 = 1 PSL7_2 = 1 P13 3/GACM2 PS7_3 = 1 PSL7_3 = 1 P13 4/GASP3 PS7_4 = 1 PSL7_4 = 1 P13 5/GASM3 PS7_5 = 1 PSL7_5 = 1 P13 6/GACP3 PS7_6 = 1 PSL7_6 = 1 P13 7/GACM3 PS7_7 = 1 PSL7_7 = 1 Table 22.28 Count Source and PWM Output Frequency f(XIN) DIV4 to DIV0 Bits Count Source (ns) Frequency (kHz) Cycles ( µs) in the G1BCR0 Register 30MHz 11111 2 (no division) 33.3 29.2 34.2 000002 (divide-by-2) 66.7 14.6 68.4 20MHz 11111 2 (no division) 50 19.5 51.3 000002 (divide-by-2) 100 9.7 102.6 16MHz 11111 2 (no division) 62.5 15.6 64.1

Page 314 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M 23. CAN Module The CAN (Controller Area Network) module included in the M32C/86 group (M32C/86, M32C/86T) is a Full CAN module, compatible with CAN Specification 2.0 Part B. Two channels, CAN0 and CAN1, can be used. Table 23.1 lists specifications of the CAN module. Table 23.1 CAN Module Specifications Item Specification Protocol CAN Specification 2.0 Part B Message Slots 16 slots Polarity Dominant: "L" Recessive: "H" Acceptance Filter Global mask: 1 (for message slots 0 to 13) Local mask: 2 (for message slots 14 and 15 respectively) Baud Rate Baud rate = --- Max. 1 Mbps Tq clock cycle = Tq per bit = SS + PTS +PBS1+PBS2 Tq: Time quantum BRP: Setting value of the C0BRP and C1BRP registers, 1-255 SS: Synchronization Segment; 1 Tq PTS: Propagation Time Segment; 1 to 8 Tq PBS1: Phase Buffer Segment 1; 2 to 8 Tq PBS2: Phase Buffer Segment 2 ; 2 to 8 Tq Remote Frame Automatic Message slot that receives the remote frame transmits the data frame Answering Function automatically Time Stamp Function Time stamp function with a 16-bit counter. Count source can be selected from the CAN bus bit clock divided by 1, 2, 3 or 4 CAN bus bit clock = BasicCAN Mode BasicCAN function can be used with the CANi message slots 14 and 15 Transmit Abort Function Transmit request is aborted Loopback Function Frame transmitted by the CAN module is received by the same CAN module Forcible Error Active The CAN module is forced into an error active state by resetting an error Transition Function counter. Single-Shot Transmit FunctionThe CAN module does not transmit data again even if arbitration lost or transmission error causes a transmission failure Self-Test Function The CAN module communicates internally and diagnoses its CAN module state NOTES: 1. Use an oscillator with maximum 1.58% oscillator tolerance. Tq clock cycle x Tq per bit BRP + 1 CAN clock CAN bit time

Page 316 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M Figure 23.2 CANi Message Slot and CANi Message Slot Buffer CANi Message Slot Buffer 0 CANi Message Slot 0 CANi Message Slot 1 CANi Message Slot 2 CANi Message Slot 3 CANi Message Slot 4 CANi Message Slot 5 CANi Message Slot 6 CANi Message Slot 7 CANi Message Slot 8 CANi Message Slot 9 CANi Message Slot 10 CANi Message Slot 11 CANi Message Slot 12 CANi Message Slot 13 CANi Message Slot 14 CANi Message Slot 15 CANi Message Slot Buffer 0 Standard ID0 (CiSLOT0_0) CANi Message Slot Buffer 0 Standard ID1 (CiSLOT0_1) CANi Message Slot Buffer 0 Extended ID0 (CiSLOT0_2) CANi Message Slot Buffer 0 Extended ID1 (CiSLOT0_3) CANi Message Slot Buffer 0 Extended ID2 (CiSLOT0_4) CANi Message Slot Buffer 0 Data Length Code (CiSLOT0_5) CANi Message Slot Buffer 0 Data 0 (CiSLOT0_6) CANi Message Slot Buffer 0 Data 1 (CiSLOT0_7) CANi Message Slot Buffer 0 Data 2 (CiSLOT0_8) CANi Message Slot Buffer 0 Data 3 (CiSLOT0_9) CANi Message Slot Buffer 0 Data 4 (CiSLOT0_10) CANi Message Slot Buffer 0 Data 5 (CiSLOT0_11) CANi Message Slot Buffer 0 Data 6 (CiSLOT0_12) CANi Message Slot Buffer 0 Data 7 (CiSLOT0_13) CANi Message Slot Buffer 0 Time Stamp High-Ordered (CiSLOT0_14) CANi Message Slot Buffer 0 Time Stamp Low-Ordered (CiSLOT0_15) CANi Message Slot Buffer 1 Standard ID0 (CiSLOT1_0) CANi Message Slot Buffer 1 Standard ID1 (CiSLOT1_1) CANi Message Slot Buffer 1 Extended ID0 (CiSLOT1_2) CANi Message Slot Buffer 1 Extended ID1 (CiSLOT1_3) CANi Message Slot Buffer 1 Extended ID2 (CiSLOT1_4) CANi Message Slot Buffer 1 Data Length Code (CiSLOT1_5) CANi Message Slot Buffer 1 Data 0 (CiSLOT1_6) CANi Message Slot Buffer 1 Data 1 (CiSLOT1_7) CANi Message Slot Buffer 1 Data 2 (CiSLOT1_8) CANi Message Slot Buffer 1 Data 3 (CiSLOT1_9) CANi Message Slot Buffer 1 Data 4 (CiSLOT1_10) CANi Message Slot Buffer 1 Data 5 (CiSLOT1_11) CANi Message Slot Buffer 1 Data 6 (CiSLOT1_12) CANi Message Slot Buffer 1 Data 7 (CiSLOT1_13) CANi Message Slot Buffer 1 Time Stamp High-Ordered (CiSLOT1_14) CANi Message Slot Buffer 1 Time Stamp Low-Ordered (CiSLOT1_15) Internal Data Bus CAN Protocol Controller CANi Message Slot Buffer 0 (16 bytes) CANi Message Slot Buffer 1 (16 bytes) CAN0 01E016 01EF 16 01F016 01FF16 CiSBS b3 to b0 CiSBS b7 to b4 CANi message slot buffer 0 standard ID0 CANi message slot buffer 0 standard ID1 CANi message slot buffer 0 extended ID0 CANi message slot buffer 0 extended ID1 CANi message slot buffer 0 extended ID2 CANi message slot buffer 0 data length cod CANi message slot buffer 0 data 0 CANi message slot buffer 0 data 1 CANi message slot buffer 0 data 2 CANi message slot buffer 0 data 3 CANi message slot buffer 0 data 4 CANi message slot buffer 0 data 5 CANi message slot buffer 0 data 6 CANi message slot buffer 0 dataO7 CANi Message Slot 15 Time Stamp Low-Ordered CANi Message Slots j i=0, 1, j=0 to 15 CANi Message Slot 0 Standard ID0 CANi Message Slot 0 Standard ID1 CANi Message Slot 0 Extended ID0 CANi Message Slot 0 Extended ID1 CANi Message Slot 0 Extended ID2 CANi Message Slot 0 Data Length Code CANi Message Slot 0 Data 0 CANi Message Slot 0 Data 1 CANi Message Slot 0 Data 2 CANi Message Slot 0 Data 3 CANi Message Slot 0 Data 4 CANi Message Slot 0 Data 5 CANi Message Slot 0 Data 6 CANi Message Slot 0 Data 7 CANi Message Slot 0 Time Stamp High-Ordered CANi Message Slot 0 Time Stamp Low-Ordered CANi Message Slot Buffer 1 CAN1 026016 026F16 027016 027F16

Page 317 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M troPn oitcnuF gnitteSdnatiB ASPI,SPI sretsigeR 3SP,2SP,1SP sretsigeR )1( ,2LSP,1LSP sretsigeR3LSP 3CSP,2CSP,CSP sretsigeR 9DP,8DP,7DP )1( sretisgeR 7P 6 0NAC TUO − 1=6_1SP0 =6_1LSP1 =6_CSP − 7P 7 0NAC NI 0=3SPI0 =7_1SP −− 0=7_7DP 8P 2 0NAC TUO − 1=2_2SP1 =2_2LSP0 =2_2CSP − 1NAC TUO − 1=2_2SP1 =2_2LSP1 =2_2CSP − 8P 3 0NAC NI 1=3SPI −−− 0=3_8DP 1NAC NI 1=3_ASPI −−− 0=3_8DP 9P 5 1NAC NI 0=3_ASPI0 =5_3SP0 =5_3LSP − 0=5_9DP 9P 6 1NAC TUO − 1=6_3SP − 1=6_3CSP − Table 23.2 Pin Settings NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.

Page 318 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Control Register 0 (i=0, 1) Symbol Address After Reset (1) C0CTLR0 0201 16 - 020016 XXXX 0000 XX01 0X01 2 C1CTLR0 0281 16 - 028016 XXXX 0000 XX01 0X01 2 RW RESET1 TSPRE0 TSRESET CAN Reset Bit 1 Time Stamp Counter Reset Bit 0: CAN module reset exited 1: CAN module is reset(2) RESET0 LOOPBACK (b2) BASICCAN CAN Reset Bit 0 Loop Back Mode Select Bit BasicCAN Mode Select Bit 0: Disables BasicCAN mode function 1: Enables BasicCAN mode function 0: Disables loop back function 1: Enables loop back function 0: CAN module reset exited 1: CAN module is reset(2) TSPRE1 ECRESET (b15 - b12) (b7 - b6) (b5) Error Counter Reset Bit 0: Nothing is occurred 1: This bit is automatically set to "0" after the CiTEC and CiREC registers are set to "00 16"(3) Time Stamp Prescaler Select Bit Reserved Bit Set to "0" Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set the RESET1 and RESET0 bits to the same value simultaneously. 3. These bits can only be set to "1", not "0", by program. 0 0: Selects the CAN bus bit clock 0 1: Selects the CAN bus bit clock divided by 2 1 0: Selects the CAN bus bit clock divided by 3 1 1: Selects the CAN bus bit clock divided by 4 b9 b8 0: Nothing is occurred 1: This bit is automatically set to "0" after the CiTSR register is set to "0000 16"(3) b7 b0b15 b8

23.1 CAN-Associated Registers

CAN-associated registers, set the CM21 bit in the CM2 register to "0" (main clock or PLL clock as CPU clock) and the MCD4 to MCD0 bits in the MCD register to "10010 2" (no division mode). Or, set the PM24 bit in the PM2 register to "1" (main clock direct mode) and the PM25 bit in the PM2 regiseter to "1" (CAN clock). Two wait states are added into the bus cycle. Refer to 7. Processor Mode and 9. Clock Generation Circuit.

23.1.1 CANi Control Register 0 (CiCTLR0 Register) (i=0, 1)

Figure 23.3 C0CTLR0 and C1CTLR0 Registers

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23.1.1.1 RESET1 and RESET0 Bits

When both RESET1 and RESET0 bits are set to "1" (CAN module reset), the CAN module is imme- diately initialized regardless of ongoing CAN communication. After the RESET1 and RESET0 bits are set to "1" and the CAN module reset is completed, the CiTSR register (i=0, 1) is set to "0000 16". The CiTEC and CiREC registers are set to "0016" and the STATE_ERRPAS and STATE_BUSOFF bits in the CiSTR register are set to "0" as well. When both RESET1 and RESET0 bit settings are changed "1" to "0", the CiTSR register starts counting. CAN communication is available after 11 continuous recessive bits are detected. NOTES: 1. Set the same value in both RESET1 and RESET0 bits simultaneously. 2. Confirm that the STATE_RESET bit in the CiSTR register is set to "1" (CAN module reset completed) after setting the RESET1 and RESET0 bits to "1". 3. The CAN OUT pin puts in a high-level ("H") signal as soon as the RESET1 and RESET0 bits are set to "1". CAN bus error may occur when the RESET1 and RESET0 bits are set to "1" while the CAN frame is transmitting. 4. For CAN communication, set the PS1, PS2, PS3, PSL1, PSL2, PSL3, PSC, PSC2, PSC3, IPS, IPSA, PD7, PD8 and PD9 registers when the STATE_RESET bit is set to "1" (CAN module reset completed).

23.1.1.2 LOOPBACK Bit

When the LOOPBACK bit is set to "1" (loopback function enabled) and the receive message slot has a matched ID and frame format with a transmitted frame, the transmitted frame is stored to the receive message slot. NOTES: 1. No ACK for the transmitted frame is returned. 2. Change the LOOPBACK bit setting only when the STATE_RESET bit is set to "1" (CAN module reset completed).

23.1.1.3 BASICCAN Bit

When the BASICCAN bit is set to "1", the message slots 14 and 15 enter BasicCAN mode. In BasicCAN mode, the message slots 14 and 15 are used as dual-structured buffers. The message slots 14 and 15 alternately store a received frame having matched ID detected by acceptance filtering. ID in the message slot 14 and the CiLMAR0 to CiLMAR4 registers are used for acceptance filtering when the message slot 14 is active (the next received frame is to be stored in the message slot 14). ID in the message slot 15 and the CiLMBR0 to CiLMBR4 registers are used when the message slot 15 is active. Both data frame and remote frame can be received. Use the following procedure to enter BasicCAN mode. (1) Set the BASICCAN bit to "1". (2) Set the same value into IDs in the message slots 14 and 15. (3) Set the same value in the CiLMAR0 to CiLMAR4 registers and CiLMBR0 to CiLMBR4 registers. (4) Set the IDE14 and IDE15 bits in the CiIDR register to select a frame format (standard or ex- tended) for the message slots 14 and 15. (Set to the same format.) (5) Set the CiMCTL14 and CiMCTL15 registers in the message slots 14 and 15 to receive the data frame.

Page 320 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M NOTES: 1. Change the BASICCAN bit setting only when the STATE_RESET bit is set to "1" (CAN module reset completed). 2. The message slot 14 is the first slot to become active after the RESET1 and RESET0 bits are set to "0". 3. The message slots 0 to 13 are not affected by entering BasicCAN mode.

23.1.1.4 TSPRE1, TSPRE0 Bits

The TSPRE1 and TSPRE0 bits determine which count source is used for the time stamp counter. NOTES: 1. Change the TSPRE1 and TSPRE0 bit settings only when the STATE_RESET bit is set to "1" (CAN module reset completed).

23.1.1.5 TSRESET Bit

When the TSRESET bit is set to "1", the CiTSR register is set to "000016". The TSRESET bit is automatically set to "0" after the CiTSR register is set to "000016".

23.1.1.6 ECRESET Bit

When the ECRESET bit is set to "1", the CiTEC and CiREC registers are set to "0016". The CAN module forcibly goes into an error active state. The ECRESET bit is automatically set to "0" after the CAN module enters an error active state. NOTES: 1. In an error active state, the CAN module is ready to communicate when 11 continuous reces- sive bits are detected on the CAN bus. 2. The CANi OUT pin provides an "H" signal output as soon as the ECRESET bit is set to "1". The CAN bus error may occur when setting the ECRESET bit to "1" during CAN frame transmission.

Page 321 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M BANKSEL (b1 - b0) (b2) (b5 - b4) (b7) CANi Control Register 1 (i=0, 1) Symbol Address After Reset (1) C0CTLR1 0241 16 X000 00XX 2 C1CTLR1 0251 16 X000 00XX 2 RW CANi Bank Switch Bit 0: Selects the message slot control register and single-shot register 1: Selects the mask register Bit Name FunctionBit Symbol Reserved Bit Set to "0" Reserved Bit Set to "0" Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RWINTSEL CANi Interrupt Mode Select Bit 0: Outputs 3 types of interrupts via OR 1: Outputs 3 types of interrupts separatelyRW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b7 b6 b5 b4 b3 b2 b1 b0 000

23.1.2 CANi Control Register 1 (CiCTLR1 Register) (i=0, 1)

Figure 23.4 C0CTLR1 and C1CTLR1 Registers

23.1.2.1 BANKSEL Bit

The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 022016 to 023F16. The BANKSEL bit in the C1CTLR1 register selects registers allocated to addresses 02A016 to 02BF16. The CiSSCTLR register, CiSSSTR register and the CiMCTL0 to CiMCTL15 registers can be ac- cessed by setting the BANKSEL bit to "0". The CiGMR0 to CiGMR4 registers, CiLMAR0 to CiLMAR4 registers and CiLMBR0 to CiLMBR4 registers can be accessed by setting the BANKSEL bit to "1".

23.1.2.2 INTSEL Bit

The INTSEL bit determines whether the three types of interrupt outputs (CANi transmit interrupt, CANi receive interrupt and CANi error interrupt) are provided via OR or is separately. Refer to 23.4 CAN Interrupts for details. NOTES: 1. Change the INTSEL bit setting when the STATE_RESET bit is set to "1" (CAN module reset completed).

Page 322 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M SLEEP (b7 - b1) CANi Sleep Control Register (i=0, 1) Symbol Address After Reset C0SLPR 0242 16 XXXX XXX0 2 C1SLPR 0252 16 XXXX XXX0 2 RW Sleep Mode Control Bit0 : Enters sleep mode 1 : Exits sleep mode(1) Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW NOTES: 1. Set up the initial setting for the CAN module after CAN sleep mode is exited. While the CAN0 module is in sleep mode, no SFR (addresses 01E016 to 024516) for CAN0, except the C0SLPR register, can be accessed. While the CAN1 module is in sleep mode, no SFR (addresses 025016 to 02BF16) for CAN1, except the C1SLPR register, can be accessed. b7 b6 b5 b4 b3 b2 b1 b0

23.1.3 CANi Sleep Control Register (CiSLPR Register) (i=0, 1)

Figure 23.5 C0SLPR and C1SLPR Registers

23.1.3.1 SLEEP Bit

When the SLEEP bit is set to "0", the clock supplied to the CAN module stops running and the CAN module enters sleep mode. When the SLEEP bit is set to "1", the clock supplied to the CAN module starts running and the CAN module exits sleep mode. NOTES: 1. Enter sleep mode after the STATE_RESET bit in the CiSTR register is set to "1" (CAN module reset completed).

Page 323 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Status Register (i=0, 1) Symbol Address After Reset (1) C0STR 0203 16 - 020216 X000 0X01 0000 0000 2 C1STR 0283 16 - 028216 X000 0X01 0000 0000 2 RW 0 0 0 0 : Message slot 0 0 0 0 1 : Message slot 1 0 0 1 0 : Message slot 2 0 0 1 1 : Message slot 3 1 1 0 1 : Message slot 13 1 1 1 0 : Message slot 14 1 1 1 1 : Message slot 15 b2b3 b0b1 MBOX0 TRMSUCC RECSUCC Active Slot Determination Bit TRMSTATE RECSTATE STATE_RESET STATE_LOOPBACK (b10) STATE_BASICCAN STATE_BUSERROR STATE_ERRPAS STATE_BUSOFF (b15) Transmit Complete State Flag Receive Complete State Flag Transmit State Flag Receive State Flag CAN Reset State Flag Loop Back State Flag BasicCAN State Flag CAN Bus Error State Flag Error Passive State Flag Bus-Off State Flag 0: Transmission is not completed 1: Transmission is completed 0: Reception is not completed 1: Reception is completed 0: Not transmitting 1: During transmission 0: Not receiving 1: During reception 0: CAN module is operating 1: CAN module reset is completed 0: Mode except Loop back mode 1: Loop back mode 0: Mode except BasicCAN mode 1: BasicCAN mode 0: No error occurs 1: Error occurs 0: No error passive state 1: Error passive state 0: No bus-off state 1: Bus-off state MBOX1 MBOX2 MBOX3 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RO RO RO RO RO RO RO RO RO RO RO RO RO RO NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b7 b0b15 b8

23.1.4 CANi Status Register (CiSTR Register) (i=0, 1)

Figure 23.6 C0STR and C1STR Registers

23.1.4.1 MBOX3 to MBOX0 Bits

The MBOX3 to MBOX0 bits store relevant slot numbers when the CAN module has completed trans- mitting data or storing received data.

23.1.4.2 TRMSUCC Bit

The TRMSUCC bit is set to "1" when the CAN module has transmitted data as expected. The TRMSUCC bit is set to "0" when the CAN module has received data as expected.

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23.1.4.3 RECSUCC Bit

The RECSUCC bit is set to "1" when the CAN module has received data as expected. (Whether received message has been stored in the message slot or not is irrelevant.) If the received message is transmitted in loopback mode, the TRMSUCC bit is set to "1" and the RECSUCC bit is set to "0". The RECSUCC bit is set to "0" when the CAN module has transmitted data as expected.

23.1.4.4 TRMSTATE Bit

The TRMSTATE bit is set to "1" when the CAN module is performing as a transmit node. The TRMSTATE bit is set to "0" when the CAN module is in a bus-idle state or starts performing as a receive node.

23.1.4.5 RECSTATE Bit

The RECSTATE bit is set to "1" when the CAN module is performing as a receive node. The RECSTATE bit is set to "0" when the CAN module is in a bus-idle state or starts performing as a transmit node.

23.1.4.6 STATE_RESET Bit

After both RESET1 and RESET0 bits are set to "1" (CAN module reset), the STATE_RESET bit is set to "1" as soon as the CAN module is initialized. The STATE_RESET bit is set to "0" when the RESET1 and RESET0 bits are set to "0".

23.1.4.7 STATE_LOOPBACK Bit

The STATE_ LOOPBACK bit is set to "1" when the CAN module is in loopback mode. The STATE_LOOPBACK bit is set to "1" when the LOOPBACK bit in the CiCTLR0 register is set to "1" (loop back function enabled). The STATE_LOOPBACK bit is set to "0" when the LOOPBACK bit is set to "0" (loop back function disabled).

23.1.4.8 STATE_BASICCAN Bit

The STATE_BASICCAN bit is set to "1" when the CAN module is in BasicCAN mode. Refer to 23.1.1.3 BASICCAN bit for BasicCAN mode. The STATE_BASICCAN bit is set to "0" when the BASICCAN bit is set to "0" (BasicCAN mode function disabled). The STATE_BASICCAN bit is set to "1" when the BASICCAN bit is set to "1" (BasicCAN mode function enabled), the REMACTIVE bits in the CiMCTL14 and CiMCTL15 registers in the message slots 14 and 15 are set to "0" (data frame received).

23.1.4.9 STATE_BUSERROR Bit

The STATE_BUSERROR bit is set to "1" when an CAN communication error is detected. The STATE_BUSERROR bit is set to "0" when the CAN module has transmitted or received data as expected. Whether a received message has been stored into the message slot or not is irrelevant. NOTES: 1. When the STATE_BUSERROR bit is set to "1", the STATE_BUSERROR bit remains un- changed even if both RESET1 and RESET0 bits are set to "1" (CAN module reset).

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23.1.4.10 STATE_ERRPAS Bit

The STATE_ERRPAS bit is set to "1" when the value of the CiTEC or CiREC register (i=0, 1) ex- ceeds 127 and the CAN module is placed in an error-passive state. The STATE_ERRPAS bit is set to "0" when the CAN module in an error-passive state is placed in another error state. The STATE_ERRPAS bit is set to "0" when both RESET1 and RESET0 bits are set to "1" (CAN module is reset).

23.1.4.11 STATE_BUSOFF Bit

The STATE_BUSOFF bit is set to "1" when the value of the CiTEC register exceeds 255 and the CAN module is placed in a bus-off state. The STATE_BUSOFF bit is set to "0" when the CAN module in a bus-off state is placed in an error- active state. The STATE_BUSOFF bit is set to "0" when both RESET1 and RESET0 bits are set to "1" (CAN module reset).

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23.1.5 CANi Extended ID Register (CiIDR Register) (i=0, 1)

CANi Extended ID Register(1) (i=0, 1) Symbol Address After Reset (2) C0IDR 0205 16 - 020416 0000 16 C1IDR 0285 16 - 028416 0000 16 RW IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 Extended ID15 (Message Slot 15) IDE9 IDE8 IDE7 IDE6 IDE5 IDE4 IDE3 IDE2 IDE1 IDE0 Extended ID14 (Message Slot 14) Extended ID13 (Message Slot 13) Extended ID12 (Message Slot 12) Extended ID11 (Message Slot 11) Extended ID10 (Message Slot 10) Extended ID9 (Message Slot 9) Extended ID8 (Message Slot 8) Extended ID7 (Message Slot 7) Extended ID6 (Message Slot 6) Extended ID5 (Message Slot 5) Extended ID4 (Message Slot 4) Extended ID3 (Message Slot 3) Extended ID2 (Message Slot 2) Extended ID1 (Message Slot 1) Extended ID0 (Message Slot 0) 0: Standard format 1: Extended format Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW NOTES: 1. Change the CiIDR register setting while the CiMCTLj (j=0to 15) register, corresponding to bits to be changed, is set to "00 16". 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. Standard or extended format is set by the corresponding message slot b7 b0b15 b8 Figure 23.7 C0IDR and C1IDR Registers Bits in the CiIDR register determine the frame format in the message slot corresponding to each bit. The standard format is selected when the bit is set to "0". The extended format is selected when the bit is to set "1".

Page 327 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Configuration Register (i=0, 1) Symbol Address After Reset (1) C0CONR 0207 16 - 020616 0000 0000 0000 XXXX 2 C1CONR 0287 16 - 028616 0000 0000 0000 XXXX 2 RW 0 0 0: 1 T q 0 0 1: 2 T q 0 1 0: 3 T q 0 1 1: 4 T q 1 0 0: 5 T q 1 0 1: 6 T q 1 1 0: 7 T q 1 1 1: 8 T q b6b7 b5 0 0 0 : Do not set to this value 0 0 1: 2 T q 0 1 0: 3 T q 0 1 1: 4 T q 1 0 0: 5 T q 1 0 1: 6 T q 1 1 0: 7 T q 1 1 1: 8 T q b9b10 b8 0 0 0 : Do not set to this value 0 0 1: 2 T q 0 1 0: 3 T q 0 1 1: 4 T q 1 0 0: 5 T q 1 0 1: 6 T q 1 1 0: 7 T q 1 1 1: 8 T q b12b13 b11 0 0 : 1Tq 0 1: 2 T q 1 0 : 3Tq 1 1 : 4Tq b14b15 PTS1 PBS11 PBS21 Propagation Time Segment Phase Buffer Segment 1 Phase Buffer Segment 2 reSynchronization Jump Width SJW0 SJW1 PBS20 PBS22 PBS10 PBS12 PTS0 PTS2 Bit Name FunctionBit Symbol Sampling Number 0: Sampled once 1: Sampled three times Nothing is assigned. When write, set to "0". When read, its content is indeterminate. SAM (b3 - b0) RW RW RW RW RW RW RW RW RW RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b7 b0b15 b8 Figure 23.8 C0CONR and C1CONR Registers

23.1.6 CANi Configuration Register (CiCONR Register) (i=0, 1)

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23.1.6.1 SAM Bit

The SAM bit determines the number of sample points to be taken per bit. When the SAM bit is set to "0", only one sample is taken per bit at the end of the Phase Buffer Segment 1 (PBS1) to determine the value of the bit. When the SAM bit is set to "1", three samples per bit are taken; one time quantum and two time quanta before the end of PBS1, and at the end of PBS1. The sample result value which is detected more than twice becomes the value of the bit sampled.

23.1.6.2 PTS2 to PTS0 Bits

The PTS2 to PTS0 bits determine PTS width.

23.1.6.3 PBS12 to PBS10 Bits

The PBS12 to PBS10 bits determine PBS1 width. Set the PBS12 to 10 bits to "001 2" or more.

23.1.6.4 PBS22 to PBS20 Bits

The PBS22 to PBS20 bits determine PBS2 width. Set the PBS22 to PBS20 bits to "0012" or more.

23.1.6.5 SJW1 and SJW0 Bits

The SJW1 and SJW0 bits determine SJW width. Set the SJW1 and SJW0 bits to values less than or equal to the PBS12 to PBS10 bit settings and the PBS22 to PBS20 bit settings. Table 23.3 Bit Timing when CPU Clock = 30 MHz Baud Rate BRP Tq Clock Cycles (ns) Tq Per Bit PTS+PBS1 PBS2 Sample Point 1Mbps 1 66.7 15 12 2 87% 1 66.7 15 11 3 80% 1 66.7 15 10 4 73% 2 100 10 7 2 80% 2 100 10 6 3 70% 2 100 10 5 4 60% 500Kbps 2 100 20 16 3 85% 2 100 20 15 4 80% 2 100 20 14 5 75% 3 133.3 15 12 2 87% 3 133.3 15 11 3 80% 3 133.3 15 10 4 73% 4 166.7 12 9 2 83% 4 166.7 12 8 3 75% 4 166.7 12 7 4 67% 5 200 10 7 2 80% 5 200 10 6 3 70% 5 200 10 5 4 60%

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23.1.7 CANi Baud Rate Prescaler (CiBRP Register) (i=0, 1)

Figure 23.9 C0BRP and C1BRP Registers The CiBRP register determines the Tq clock cycle of the CAN bit time. The baud rate is obtained from Tq clock cycle x Tq per bit. Tq clock cycle = (BRP+1) / CAN clock Baud rate = Tq per bit = SS + PTS + PBS1 + PBS2 Tq: Time quantum BRP: Setting value of the CiBPR register; 1-255 SS: Synchronization Segment; 1 Tq PTS: Propagation Time Segment; 1 to 8 Tq PBS1: Phase Buffer Segment 1; 2 to 8 Tq PBS2: Phase Buffer Segment 2; 2 to 8 Tq CANi Baud Rate Prescaler (i=0, 1) Symbol Address After Reset (1) C0BRP 0217 16 0000 0001 16 C1BRP 0297 16 0000 0001 16 RWFunction Setting Range 0116 to FF16(2)If setting value is n, the CPU clock is divided by (n+1). RW NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Do not set to "0016" (divide-by-1). b7 b0 Tq clcok cycle x Tq per bit

Page 330 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Time Stamp Register (i=0, 1) Symbol Address After Reset (1) C0TSR 0209 16 - 020816 0000 16 C1TSR 0289 16 - 028816 0000 16 RWFunction Value of time stamp RO b15 b8 b7 b0 NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module.

23.1.8 CANi Time Stamp Register (CiTSR Register) (i=0, 1)

Figure 23.10 C0TSR and C1TSR Registers The CiTSR register is a 16-bit counter. The TSPRE1 and TSPRE0 bits in the CiCTLR0 register select the CAN bus bit clock divided by 1, 2, 3 or 4 as the count source for the CiTSR register. When data transmission or reception is completed, the value of the CiTSR register is automatically stored into the message slot. In loopback mode, when either data frame receive message slot or remote frame receive message slot is available to store the message, the value of the CiTSR register is also stored into the message slot when data reception is completed. The value of the CiTSR register is not stored when data transmission is completed. The CiTSR register starts a counter increment when the RESET1 and RESET0 bits in the CiCTLR0 register are set to "0". The CiTSR register is set to "0000 16":

at the next count timing after the CiTSR register is set to "FFFF16";
when the RESET1 and RESET0 bits are set to "1" (CAN module reset) by program; or
when the TSRESET bit is set to "1" (CiTSR register reset) by program. CAN bus bit clock = 1 CAN bit time

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23.1.9 CANi Transmit Error Count Register (CiTEC Register) (i=0, 1)

CANi Transmit Error Count Register (i=0, 1) Symbol Address After Reset (1) C0TEC 020A 16 00 16 C1TEC 028A 16 00 16 RWFunction Counter value of transmission errors RO NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b7 b0 CANi Receive Error Count Register (i=0, 1) Symbol Address After Reset (1) C0REC 020B 16 00 16 C1REC 028B 16 00 16 RWFunction Counter value of receive error RO NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b7 b0 Figure 23.11 C0TEC and C1TEC Registers In an error active or an error passive state, the counting value of a transmission error is stored into the CiTEC register. The counter is decremented when the CAN module has transmitted data as expected or is incremented when an transmit error occurs. In a bus-off state, an indeterminate value is stored into the CiTEC register. The CiTEC register is set to "00 16" when the CAN module is placed in an error active state again.

23.1.10 CANi Receive Error Count Register (CiREC Register) (i=0, 1)

Figure 23.12 C0REC and C1REC Registers In an error active or an error passive state, a counting value of the reception error is stored into the CiREC register. The counter is decremented when the CAN module has received data as expected or it is incremented when a receive error occurs. The CiREC register is set to 127 when the CiREC register is 128 (error passive state) or more and the CAN module has received as expected. In a bus-off state, an indeterminate value is stored into the CiREC register. The CiREC register is set to "00 16" when the CAN module is placed in an error active state again.

Page 332 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Slot Interrupt Status Register (i=0, 1) Symbol Address After Reset (1) C0SISTR 020D 16 - 020C16 0000 16 C1SISTR 028D 16 - 028C16 0000 16 RW SIS15 SIS14 SIS13 SIS12 SIS11 SIS10 Message Slot 15 Interrupt Request Status Bit SIS9 SIS8 SIS7 SIS6 SIS5 Message Slot 14 Interrupt Request Status Bit Message Slot 13 Interrupt Request Status Bit Message Slot 12 Interrupt Request Status Bit Message Slot 11 Interrupt Request Status Bit Message Slot 10 Interrupt Request Status Bit Message Slot 9 Interrupt Request Status Bit Message Slot 8 Interrupt Request Status Bit Message Slot 7 Interrupt Request Status Bit Message Slot 6 Interrupt Request Status Bit Message Slot 5 Interrupt Request Status Bit Message Slot 4 Interrupt Request Status Bit Message Slot 3 Interrupt Request Status Bit Message Slot 2 Interrupt Request Status Bit Message Slot 1 Interrupt Request Status Bit Message Slot 0 Interrupt Request Status Bit SIS4 SIS3 SIS2 SIS1 SIS0 0: Requests no interrupt 1: Requests an interrupt (2) Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Determines whether an interrupt of a corresponding message slot is requested or not. NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set to "0" by program. If it is set to "1", the value before setting to "1" remains. (2) b7 b0b15 b8

23.1.11 CANi Slot Interrupt Status Register (CiSISTR Register) (i=0, 1)

Figure 23.13 C0SISTR and C1SISTR Registers

Page 333 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M When using the CAN interrupt, the CiSISTR register (i=0, 1) indicates which message slot is requesting an interrupt. The SISj bits (j=0 to 15) are not automatically set to "0" (no interrupt requested) when an interrupt is acknowledged. Set the SISj bits to "0" by program. Use the MOV instruction, instead of the bit clear instruction, to set the SISj bits to "0". The SISj bits, which are not being changed to "0", must be set to "1". For example: To set the SIS0 bit to "0" Assembly language: mov.w #07FFFh, C0SISTR C language: c0sistr = 0x7FFF; Refer to 23.4 CAN Interrupt for details.

23.1.11.1 Message Slot for Transmission

The SISj bit is set to "1" (interrupt requested) when the CiTSR register is stored into the message slot j after data transmission is completed.

23.1.11.2 Message Slot for Reception

The SISj bit is set to "1" (interrupt requested) when the received message is stored in the message slot j after data reception is completed. NOTES: 1.If the automatic answering function is enabled in the remote frame receive message slot, the SISj bit is set to "1" after the remote frame is received and the data frame is transmitted. 2.In the remote frame transmit message slot, the SISj bit is set to "1" after the remote frame is transmitted and the data frame is received. 3.The SISj bit is set to "1" if the SISj bit is set to "1" by an interrupt request and "0" by program simultaneously.

Page 334 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Slot Interrupt Mask Register(1) (i=0, 1) Symbol Address After Reset (2) C0SIMKR 0211 16 - 021016 0000 16 C1SIMKR 0291 16 - 029016 0000 16 SIM15 SIM14 SIM13 SIM12 SIM11 SIM10 Slot 15 Interrupt Request Mask Bit SIM9 SIM8 SIM7 SIM6 SIM5 Slot 14 Interrupt Request Mask Bit Slot 13 Interrupt Request Mask Bit Slot 12 Interrupt Request Mask Bit Slot 11 Interrupt Request Mask Bit Slot 10 Interrupt Request Mask Bit Slot 9 Interrupt Request Mask Bit Slot 8 Interrupt Request Mask Bit Slot 7 Interrupt Request Mask Bit Slot 6 Interrupt Request Mask Bit Slot 5 Interrupt Request Mask Bit Slot 4 Interrupt Request Mask Bit Slot 3 Interrupt Request Mask Bit Slot 2 Interrupt Request Mask Bit Slot 1 Interrupt Request Mask Bit Slot 0 Interrupt Request Mask Bit SIM4 SIM3 SIM2 SIM1 SIM0 Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0: Masks (disables) an interrupt request 1: Enables an interrupt request Controls whether the interrupt request of the corresponding message slot is enabled or masked. NOTES: 1. Change the CiSIMKR register setting while the CiMCTLj (j=0to 15) register, corresponding to the bit to be changed, is set to "00 16". 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b7 b0b15 b8

23.1.12 CANi Slot Interrupt Mask Register (CiSIMKR Register) (i=0, 1)

Figure 23.14 C0SIMKR and C1SIMKR Registers The CiSIMKR register determines whether an interrupt request, generated by a data transmission or reception in the corresponding message slot is enabled or disabled. When the SIMj bit (j=0 to 15) is set to "1" (no interrupt requested), an interrupt request generated by a data transmission or reception in the corresponding message slot is enabled. Refer to 23.4 CAN Interrupt for details.

Page 335 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M BOIM EPIM BEIM (b7 - b3) CANi Error Interrupt Mask Register (i=0, 1) Symbol Address After Reset (1) C0EIMKR 0214 16 XXXX X000 2 C1EIMKR 0294 16 XXXX X000 2 RWBit Name FunctionBit Symbol Bus-Off Interrupt Mask Bit Error-Passive Interrupt Mask Bit CAN Bus-Error Interrupt Mask Bit Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after r eset and supplying the clock to the C AN m odule. 0: Masks (disables) an interrupt request 1: Enables an interrupt request 0: Masks (disables) an interrupt request 1: Enables an interrupt request 0: Masks (disables) an interrupt request 1: Enables an interrupt request b7 b6 b5 b4 b3 b2 b1 b0

23.1.13 CANi Error Interrupt Mask Register (CiEIMKR Register) (i=0, 1)

Figure 23.15 C0EIMKR and C1EIMKR Registers Refer to 23.4 CAN Interrupt for details.

23.1.13.1 BOIM Bit

The BOIM bit determines whether an interrupt request is enabled or disabled when the CAN module is placed in a bus-off state. When the BOIM bit is set to "1", the bus-off interrupt request is enabled.

23.1.13.2 EPIM Bit

The EPIM bit determines whether an interrupt request is enabled or disabled when the CAN module is placed in an error passive state. When the EPIM bit is set to "1", the error passive interrupt request is enabled.

23.1.13.3 BEIM Bit

The BEIM bit determines whether an interrupt request is enabled or disabled when a CAN bus error occurs. When the BEIM bit is set to "1", the CAN bus error interrupt request is enabled.

Page 336 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Error Interrupt Status Register (i=0, 1) Symbol Address After Reset (1) C0EISTR 0215 16 XXXX X000 2 C1EISTR 0295 16 XXXX X000 2 RW BOIS EPIS BEIS (b7 - b3) Bus-Off Interrupt Status Bit (2) Error-Passive Interrupt Status Bit (2) CAN Bus-Error Interrupt Status Bit (2) 0: No interrupt is requested 1: Interrupt is requested 0: No interrupt is requested 1: Interrupt is requested 0: No interrupt is requested 1: Interrupt is requested Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set to "0" by program. When it is set to "1", the value before setting to "1" remains. b7 b6 b5 b4 b3 b2 b1 b0

23.1.14 CANi Error Interrupt Status Register (CiEISTR Register) (i=0, 1)

Figure 23.16 C0EISTR and C1EISTR Registers When using the CAN interrupt, the CiEISTR register indicates the source of the generated error inter- rupt. The BOIS, EPIS and BEIS bits are not automatically set to "0" (no interrupt requested) even if an interrupt is acknowledged. Set these bits to "0" by program. Use the MOV instruction, instead of the bit clear instruction, to set each bit in the CiEISTR register to "0". Bits not being changed to "0" must be set to "1". For example: To set the BOIS bit for CAN0 to "0" Assembly language: mov.b#006h, C0EISTR C language: c0eistr = 0x06; Refer to 23.4 CAN Interrupt for details.

23.1.14.1 BOIS Bit

The BOIS bit is set to "1" when the CAN module is placed in a bus-off state.

23.1.14.2 EPIS Bit

The EPIS bit is set to "1" when the CAN module is placed in an error passive state.

23.1.14.3 BEIS Bit

The BEIS bit is set to "1" when a CAN bus error is detected.

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23.1.15 CANi Error Factor Register (CiEFR Register) (i=0, 1)

Figure 23.17 C0EFR and C1EFR Registers The CiEFR register indicates the cause of error when a communication error is detected. Set the follow- ing bits to "0" by program because they are not changed "1" to "0" automatically. Use the MOV instruction, instead of the bit clear instruction, to set each bit in the CiEFR register to "0". Bits not being changed to "0" must be set to "1". For example: To set the ACKE bit for CAN0 to "0" Assembly language: mov.b#0FEh, C0EFR C language: c0efr = 0xFE;

23.1.15.1 ACKE Bit

The ACKE bit is set to "1" when an ACK error is detected.

23.1.15.2 CRCE Bit

The CRC bit is set to "1" when a CRC error is detected.

23.1.15.3 FORME Bit

The FORME bit is set to "1" when a form error is detected.

23.1.15.4 STFE Bit

The STFE bit is set to "1" when a stuff error is detected.

23.1.15.5 BITE0 Bit

The BITE0 bit is set to "1" when a bit error is detected while transmitting recessive "H".

23.1.15.6 BITE1 Bit

The BITE1 bit is set to "1" when a bit error is detected while transmitting dominant "L".

23.1.15.7 RCVE Bit

The RCVE bit is set to "1" when an error is detected while receiving data.

23.1.15.8 TRE Bit

The TRE bit is set to "1" when an error is detected while transmitting data. CANi Error Factor Register (i=0, 1) Symbol Address After Reset (1) C0EFR 0216 16 00 16 C1EFR 0296 16 00 16 RW ACKE CRCE FORME ACK Error Detect Bit(2) CRC Error Detect Bit(2) FORM Error Detect Bit(2) 0: Detects no ACK error 1: Detects an ACK error 0: Detects no CRC error 1: Detects a CRC error 0: Detects no form error 1: Detects a form error STFE Stuff Error Detect Bit(2) 0: Detects no stuff error 1: Detects a stuff error BITE0 Bit Error Detect Bit 0(2) 0: Detects no bit error while transmitting "H" 1: Detects a bit error while transmitting "H" 0: Detects no bit error while transmitting "L" 1: Detects a bit error while transmitting "L" RCVE Receive Error Detect Bit(2) 0: Detects no error while receiving data 1: Detects an error while receiving data TRE Transmit Error Detect Bit(2)0: Detects no error while transmitting data 1: Detects an error while transmitting data BITE1 Bit Error Detect Bit 1(2) Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set to "0" by program. If it is set to "1", the value before setting to "1" remains. b7 b6 b5 b4 b3 b2 b1 b0

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23.1.16 CANi Mode Register (CiMDR Register) (i=0, 1)

Figure 23.18 C0MDR and C1MDR Registers

23.1.16.1 CMOD Bit

The CMOD bit selects a CAN operating mode.

Normal operating mode: The CAN module transmits and receives data as expected.
Bus monitoring mode(1): The CAN module receives data. Output signal from the CANiOUT pin is fixed as a high-level ("H") signal in bus monitoring mode. The CAN mod ule transmits neither ACK nor error frame.
Self-test mode: The CAN module connects the CANiOUT pin to the CANiIN pin internally. The CAN module can communicate without additional device in loop back mode. Output signal from the CANiOUT pin is fixed as an "H" signal in self-test mode while transmitting data. Figure 23.19 shows an image diagram in self-test mode. NOTES: 1. Do not generate a transmit request in bus monitoring mode. The CAN module assumes the ACK bit is set to dominant "L" regardless of the ACK bit setting. Therefore, when the CRC delimiter is received as expected, the CAN module determines the data is received with no error regardless of the ACK bit setting. CANi Mode Register (i=0, 1)(1) Symbol Address After Reset (2) C0MDR 0219 16 XXXX XX00 2 C1MDR 0299 16 XXXX XX00 2 RW CMOD (b7 - b2) CAN Operating Mode Select Bit Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW 0 0: Normal operating mode 0 1: Bus monitoring mode 1 0: Self-test mode 1 1: Do not set to this value b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Set the CiMDR register when the STATE_RESET bit in the CiSTR register is set to "1" (CAN module reset completed). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module.

Page 339 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M Self-test Mode ACK Signal Generation Circuit CANiIN CANiOUT CANiOUT Pin CANiIN Pin CAN Module i=0, 1 Figure 23.19 Self-Test Mode

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23.1.17 CANi Single-Shot Control Register (CiSSCTLR Register) (i=0, 1)

Figure 23.20 C0SSCTLR and C1SSCTLR Registers According to the CAN Specification 2.0 Part B, if the arbitration lost or transmission error causes a transmit failure, the microcomputer continues transmitting data until the transmission is completed. The CiSSCTLR register determines whether or not, and from which slot, data is re-transmitted. In single-shot mode, if the arbitration lost or transmission error causes a transmission failure, data is not transmitted again. When the SSCj bit (j=0 to 15) is set to "1", the corresponding message slot j is in single-shot mode. CANi Single-Shot Control Register (i=0, 1)(1, 2) Symbol Address After Reset (3) C0SSCTLR 0221 16 - 022016 0000 16 C1SSCTLR 02A1 16 - 02A016 0000 16 RW SSC15 SSC14 SSC13 SSC12 SSC11 SSC10 Message Slot 15 Single-Shot Control Bit SSC9 SSC8 SSC7 SSC6 SSC5 Message Slot 14 Single-Shot Control Bit Message Slot 13 Single-Shot Control Bit Message Slot 12 Single-Shot Control Bit Message Slot 11 Single-Shot Control Bit Message Slot 10 Single-Shot Control Bit Message Slot 9 Single-Shot Control Bit Message Slot 8 Single-Shot Control Bit Message Slot 7 Single-Shot Control Bit Message Slot 6 Single-Shot Control Bit Message Slot 5 Single-Shot Control Bit Message Slot 4 Single-Shot Control Bit Message Slot 3 Single-Shot Control Bit Message Slot 2 Single-Shot Control Bit Message Slot 1 Single-Shot Control Bit Message Slot 0 Single-Shot Control Bit SSC4 SSC3 SSC2 SSC1 SSC0 0: Single-shot mode not used 1: Use single-shot mode Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW NOTES: 1. Set the CiSSCTLR register after the CiMCTLj register (j=0 to 15) in a slot, corresponding to the bit to be changed, is set to "00 16". 2.The CiSSCTLR register can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "0" (message slot control register and single-shot register selected). 3. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0". b7 b0b15 b8

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23.1.18 CANi Single-Shot Status Register (CiSSSTR Register) (i=0, 1)

Figure 23.21 C0SSSTR and C1SSSTR Registers If the arbitration lost or transmission error causes a transmission failure, the bit corresponding to mes- sage slot j (j=0 to 15) is set to "1". The SSSj bit is set to "0" by program because it is not set to "0" automatically. Use the MOV instruction, instead of the bit clear instruction, to set the SSSj bit to "0". Bits not being changed to "0" must be set to "1". For example: To set the SSS0 bit for CAN0 to "0" Assembly language: mov.w #07FFFh, C0SSSTR C language: c0ssstr = 0x7FFF; CANi Single-Shot Status Register (i=0, 1)(1) Symbol Address After Reset (2) C0SSSTR 0225 16 - 022416 0000 16 C1SSSTR 02A5 16 - 02A416 0000 16 RW SSS15 SSS14 SSS13 SSS12 SSS11 SSS10 Message Slot 15 Single-Shot Status Bit SSS9 SSS8 SSS7 SSS6 SSS5 Message Slot 14 Single-Shot Status Bit Message Slot 13 Single-Shot Status Bit Message Slot 12 Single-Shot Status Bit Message Slot 11 Single-Shot Status Bit Message Slot 10 Single-Shot Status Bit Message Slot 9 Single-Shot Status Bit Message Slot 8 Single-Shot Status Bit Message Slot 7 Single-Shot Status Bit Message Slot 6 Single-Shot Status Bit Message Slot 5 Single-Shot Status Bit Message Slot 4 Single-Shot Status Bit Message Slot 3 Single-Shot Status Bit Message Slot 2 Single-Shot Status Bit Message Slot 1 Single-Shot Status Bit Message Slot 0 Single-Shot Status Bit SSS4 SSS3 SSS2 SSS1 SSS0 0: No arbitration is lost, or no transmit error occurs 1: Arbitration is lost, or transmit error occurs Bit Name FunctionBit Symbol RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW (Note 3) NOTES: 1. The CiSSSTR register can be accessed only when the BANKSEL bit in the CiCTLR1 is set to "0" (message slot control register and single-shot register selected). 2.Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. 3. Set to "0" by program. When it is set it to "1", the value before setting to "1" remains b7 b0b15 b8

Page 342 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Global Mask Register Standard ID0(1) CANi Local Mask Register A Standard ID0(1) CANi Local Mask Register B Standard ID0(1) (i=0, 1) Symbol Address After Reset (2) C0GMR0, C1GMR0 0228 16, 02A816 XXX0 0000 2 C0LMAR0, C1LMAR0 0230 16(3), 02B016(4) XXX0 0000 2 C0LMBR0, C1LMBR0 0238 16(5), 02B816(6) XXX0 0000 2 RW SID6M SID7M SID8M SID9M Standard ID6 0: No ID is verified 1: ID is verified Standard ID7 Standard ID8 Standard ID9 SID10M (b7 - b5) Standard ID10 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW NOTES: 1. The CiGMR0, CiLMAR0 and CiLMBR0 registers can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "1" (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "1". 3. The C0LMAR0 register shares the same address with the C0MCTL0 register. 4. The C1LMAR0 register shares the same address with the C1MCTL0 register. 5. The C0LMBR0 register shares the same address with the C0MCTL8 register. 6. The C1LMBR0 register shares the same address with the C1MCTL8 register. b7 b6 b5 b4 b3 b2 b1 b0

23.1.19 CANi Global Mask Register, CANi Local Mask Register A and CANi Local Mask

Register B (CiGMRk, CiLMARk and CiLMBRk Registers) (i=0,1, k=0 to 4) Figure 23.22 C0GMR0, C0LMAR0 and C0LMBR0 Registers C1GMR0, C1LMAR0 and C1LMBR0 Registers

Page 343 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M Figure 23.23 C0GMR1, C0LMAR1 and C0LMBR1 Registers C1GMR1, C1LMAR1 and C1LMBR1 Registers CANi Global Mask Register Standard ID1(1) CANi Local Mask Register A Standard ID1(1) CANi Local Mask Register B Standard ID1(1) (i=0, 1) Symbol Address After Reset (2) C0GMR1, C1GMR1 0229 16, 02A916 XX00 0000 2 C0LMAR1, C1LMAR1 0231 16(3), 02B116(4) XX00 0000 2 C0LMBR1, C1LMBR1 0239 16(5), 02B916(6) XX00 0000 2 RW Standard ID0 0: No ID is verified 1: ID is verified Standard ID1 Standard ID2 Standard ID3 Standard ID4 Standard ID5 SID0M SID1M SID2M SID3M SID4M SID5M (b7 - b6) Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW NOTES: 1. The CiGMR0, CiLMAR0 and CiLMBR0 registers can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "1" (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0". 3. The C0LMAR1 register shares the same address with the C0MCTL1 register. 4. The C1LMAR1 register shares the same address with the C1MCTL1 register. 5. The C0LMBR1 register shares the same address with the C0MCTL9 register. 6. The C1LMBR1 register shares the same address with the C1MCTL9 register. b7 b6 b5 b4 b3 b2 b1 b0

Page 344 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M Figure 23.24 C0GMR2, C0LMAR2 and C0LMBR2 Registers C1GMR2, C1LMAR2 and C1LMBR2 Registers CANi Global Mask Register Extended ID0(1) CANi Local Mask Register A Extended ID0(1) CANi Local Mask Register B Extended ID0(1) (i=0, 1) RW EID14M EID15M EID16M EID17M (b7 - b4) Extended ID14 0: No ID is verified 1: ID is verified Extended ID15 Extended ID16 Extended ID17 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW NOTES: 1. The CiGMR2, CiLMAR2 and CiLMBR2 registers can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "1" (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0". 3. The C0LMAR2 register shares the same address with the C0MCTL2 register. 4. The C1LMAR2 register shares the same address with the C1MCTL2 register. 5. The C0LMBR2 register shares the same address with the C0MCTL10 register. 6. The C1LMBR2 register shares the same address with the C1MCTL10 register. Symbol Address After Reset (2) C0GMR2, C1GMR2 022A 16, 02AA16 XXXX 0000 2 C0LMAR2, C1LMAR2 0232 16(3), 02B216(4) XXXX 0000 2 C0LMBR2, C1LMBR2 023A 16(5), 02BA16(6) XXXX 0000 2 b7 b6 b5 b4 b3 b2 b1 b0

Page 345 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Global Mask Register Extended ID1(1) CANi Local Mask Register A Extended ID1(1) CANi Local Mask Register B Extended ID1(1) (i=0,1) EID6M EID7M EID8M EID9M EID10M EID11M EID13M EID12M Extended ID6 0: No ID is verified 1: ID is verified Extended ID7 Extended ID8 Extended ID9 Extended ID10 Extended ID11 Extended ID12 Extended ID13 Bit Name FunctionBit Symbol Symbol Address After Reset (2) C0GMR3, C1GMR3 022B 16, 02AB16 00 16 C0LMAR3, C1LMAR3 0233 16(3), 02B316(4) 00 16 C0LMBR3, C1LMBR3 023B 16(5), 02BB16(6) 00 16 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW NOTES: 1. The CiGMR3, CiLMAR3 and CiLMBR3 registers can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "1" (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0". 3. The C0LMAR3 register shares the same address with the C0MCTL3 register. 4. The C1LMAR3 register shares the same address with the C1MCTL3 register. 5. The C0LMBR3 register shares the same address with the C0MCTL11 register. 6. The C1LMBR3 register shares the same address with the C1MCTL11 register. Figure 23.25 C0GMR3, C0LMAR3 and C0LMBR3 Registers C1GMR3, C1LMAR3 and C1LMBR3 Registers

Page 346 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Global Mask Register Extended ID2(1) CANi Local Mask Register A Extended ID2(1) CANi Local Mask Register B Extended ID2(1) (i=0, 1) EID0M EID1M EID2M EID3M EID4M EID5M (b7 - b6) Extended ID0 0: No ID is verified 1: ID is verified Extended ID1 Extended ID2 Extended ID3 Extended ID4 Extended ID5 Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW RW NOTES: 1. The CiGMR4, CiLMAR4 and CiLMBR4 registers can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "1" (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0". 3. The C0LMAR4 register shares the same address with the C0MCTL4 register. 4. The C1LMAR4 register shares the same address with the C1MCTL4 register. 5. The C0LMBR4 register shares the same address with the C0MCTL12 register. 6. The C1LMBR4 register shares the same address with the C1MCTL12 register. Symbol Address After Reset (2) C0GMR4, C1GMR4 022C 16, 02AC16 XX00 0000 2 C0LMAR4, C1LMAR4 0234 16(3), 02B416(4) XX00 0000 2 C0LMBR4, C1LMBR4 023C 16(5), 02BC16(6) XX00 0000 2 b7 b6 b5 b4 b3 b2 b1 b0 Figure 23.26 C0GMR4, C0LMAR4 and C0LMBR4 Registers C1GMR4, C1LMAR4 and C1LMBR4 Registers

Page 347 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M The CiGMRk, CiLMARk and CiLMBRk registers are used for acceptance filtering. The users can select and receive user-desired messages. The CiGMRk register determines whether IDs in the message slots 0 to 13 are verified. The CiLMARk register determines whether ID in the message slot 14 is verified. The CiLMBRk register determines whether ID in the message slot 15 is verified.

When bits in these registers are set to "0", each standard ID0 and standard ID1 bits (ID bit) and extended ID0 to extended ID2 bits in the CANi message slots j (j=0 to 15) corresponding to the bits in the above registers, is masked while acceptance filtering. (The corresponding bits are assumed to have matching IDs.)
When bits in these registers are set to "1", corresponding ID bits are compared with received IDs while acceptance filtering. If the received ID matches the ID in the message slot j, the received data having the matched ID is stored into that message slot. NOTES: 1. Change the CiGMRk register setting only when the message slots 0 to 13 have no receive request. 2. Change the CiLMARk register setting only when the message slot 14 has no receive request. 3. Change the CiLMBRk register setting only when the message slot 15 has no receive request. 4. More than two message slots are able to store a receive message ID, the ID is stored into the message slot, having the smallest slot number. Figure 23.27 shows each mask register and corresponding message slot. Figure 23.28 shows the acceptance filtering.

Page 349 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Message Slot j Control Register (i=0,1, j=0 to 15)(1) Symbol Address After Reset (2) C0MCTL0 to C0MCTL3 0230 16(3), 023116(3), 023216(3), 023316(3) 0016 C0MCTL4 to C0MCTL7 023416(3), 023516, 023616, 023716 0016 C0MCTL8 to C0MCTL11 0238 16(4), 023916(4), 023A16(4), 023B16(4) 0016 C0MCTL12 to C0MCTL15 023C 16(4), 023D 16, 023E16, 023F16 0016 C1MCTL0 to C1MCTL3 02B0 16(5), 02B116(5), 02B216(5), 02B316(5) 0016 C1MCTL4 to C1MCTL7 02B416(5), 02B516, 02B616, 02B716 0016 C1MCTL8 to C1MCTL11 02B8 16(6), 02B916(6), 02BA 16(6), 02BB 16(6) 0016 C1MCTL12 to C1MCTL15 02BC 16(6), 02BD 16, 02BE 16, 02BF 16 0016 When receive, NEWDATA When transmit, SENTDATA When receive, INVALDATA When transmit, TRMACTIVE MSGLOST REMACTIVE Receive Complete Flag Transmit Complete Flag Receiving Flag Transmitting Flag In modes other than BasicCan mode 0: Data frame 1: Remote frame In BasicCan mode 0: Receives the data frame (status) 1: Receives the remote frame (status) Overwrite Flag(7) Remote Frame Transmit/Receive Status Flag When receiving 0: Not received(4) 1: Receive complete When transmitting 0: Not transmitted(4) 1: Transmit complete When receiving 0: Except storing received data 1: Stores received data Bit Name FunctionBit Symbol 0: No overrun error occurs 1: Overrun error occurs When transmitting 0: Except transmitting 1: Transmittting b7 b6 b5 b4 b3 b2 b1 b0 RW RW RO RW RO RSPLOCK REMOTE TRMREQ RECREQ 0: Enables automatic answering of the remote frame 1: Disables automatic answering of the remote frame 0: Transmits/receives the data frame 1: Transmits/receives the remote frame 0: No request to receive the frame 1: Request to receive the frame 0: No request to transmit the frame 1: Request to transmit the frame Automatic Answering Disable Mode Select Bit Remote Frame Set Bit Receive Request Bit Transmit Request Bit RW RW RW RW NOTES: 1. The CiMCTLj register can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "0" (message slot control register and single-shot register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0". 3. The C0MCTL0 to C0MCTL4 registers each share addresses with the C0LMAR0 to C0LMAR4 registers. 4. The C0MCTL8 to C0MCTL12 registers each share addresses with the C0LMBR0 to C0LMBR4 registers. 5. The C1MCTL0 to C1MCTL4 registers each share addresses with the C1LMAR0 to C1LMAR4 registers. 6. The C1MCTL8 to C1MCTL12 registers each share addresses with the C1LMBR0 to C1LMBR4 registers. 7. Set to "0" by program. If it is set to "1", the value before setting to "1" remains.

23.1.20 CANi Message Slot j Control Register (CiMCTLj Register) (i=0,1, j=0 to 15)

Figure 23.29 C0MCTL0 to C0MCTL15 Registers and C1MCTL0 to C1MCTL15 Registers

Page 350 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M Table 23.4 CiMCTLj register(i=0,1, j= 0 to 15) Settings and Transmit/Receive Mode Settings for the CiMCTLj Register TRMREQ RECREQ REMOTE RSPLOCK REMACTIVE MSGLOST TRMACTIVE SENTDATA Transmit/Receive Mode INVALDATA NEWDATA 0000 0 0 0 0 No frame is transmitted or received 0 1 0 0 0 0 0 0 Data frame is received 0 1 1 1 0 0 0 0 Remote frame is received or (The data frame is transmitted 0 after receiving the remote frame.) 1 0 0 0 0 0 0 0 Data frame is transmitted 1010 0 0 0 0 Remote frame is transmitted (The data frame is received after transmitting the remote frame)

23.1.20.1 SENTDATA/NEWDATA Bit

The SENTDATA/NEWDATA bit indicates that the CAN module has transmitted or received the CAN message. Set the SENTDATA/NEWDATA bit to "0 " (not transmitted or not received) by program before data transmission and reception is started. The SENTDATA/NEWDATA bit is not set to "0" automatically. When the TRMACTIVE/INVALDATA bit is set to "1" (during transmission or storing received data), the SENTDATA/NEWDATA bit cannot be set to "0". SENTDATA : The SENTDATA bit is set to "1" (transmit complete) when data transmission is com- pleted in the transmit message slot. NEWDATA : The NEWDATA bit is set to "1" (receive complete) when the message to be stored into the message slot j (j=0 to 15) is received in the receive message slot as ex- pected. NOTES: 1. To read a received data from the message slot j, set the NEWDATA bit to "0" before reading. If the NEWDATA bit is set to "1" immediately after reading, this indicates that new received data has been stored into the message slot while reading and the read data contains an indetermi- nate value. In this case, discard the data with indeterminate value and then read the message slot again after the NEWDATA bit is set to "0". 2. When the remote frame is transmitted or received, the SENTDATA/NEWDATA bit remains unchanged after the remote frame transmission or reception is completed. The SENTDATA/ NEWDATA bit is set to "1" when a subsequent data frame transmission or reception is com- pleted.

23.1.20.2 TRMACTIVE/INVALDATA Bit

The TRMACTIVE/INVALDATA bit indicates that the CAN protcol controller is transmitting or receiving a message and accessing the message slot j. The TRMACTIVE/INVALDATA bit is set to "1" when the CAN module is accessing the message slot and to "0 " when not accessing the message slot. TRMACTIVE : The TRMACTIVE bit is set to "1" (except transmitting) when a data transmission is started in the message slot. If the CAN module loses in bus arbitration, the TRMACTIVE bit is set to "0" (stops transmitting) when a CAN bus error occurs or when a data transmission is completed. INVALDATA : The INVALDATA bit is set to "1" (storing received data) when receiving a received message into the messaqe slot j, after a message reception is completed. Then the INVALDATA bit is set to "0" after a message storage is completed. Data, if read from the message slot j while this bit is set to "1", is indeterminate.

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23.1.20.3 MSGLOST Bit

The MSGLOST bit is enabled only when the message slot is set for reception. The MSGLOST bit is set to "1" (overrun error occurred) when the message slot j is overwritten by a new received message while the NEWDATA bit set to "1" (already received). The MSGLOST bit is not automatically set to "0". Set to "0" (no overrun error occurred) by program.

23.1.20.4 REMACTIVE Bit

The CiMCTL0 to CiMCTL15 registers all have the same function when the STATE_BASICCAN bit is set to "0" (other than BasicCAN mode). The REMACTIVE bit is set to "1" (remote frame) when the message slot j is set to transmit or receive the remote frame. The REMACTIVE bit is set to "0" (data frame) after the remote frame has been transmitted or received. The functions of the CiMCTL14 and CiMCTL15 registers change when the STATE_BASICCAN bit is set to "1" (BasicCAN mode). When the REMACTIVE bit is set to "0", this indicates that a message stored into the message slot is the data frame. When the REMACTIVE bit is set to "1", this indicates a message stored into the message slot is the remote frame.

23.1.20.5 RSPLOCK Bit

The RSPLOCK bit is enabled only when remote frame reception shown in Table 23.4 is selected. The RSPLOCK bit determines whether the received remote frame is processed or not. When the RSPLOCK bit is set to "0" (automatic answering of the remote frame enabled), the slot automatically changes to a transmit slot after the remote frame is received and the message stored into the message slot is automatically transmitted as the data frame. When the RSPLOCK bit is set to "1" (automatic answering of the remote frame disabled), message is not automatically transmitted upon receiving the remote frame. Set the RSPLOCK bit to "0" to select any transmit/receive mode other than the remote frame reception.

23.1.20.6 REMOTE Bit

The REMOTE bit selects transmit/receive mode shown in Table 23.4. Set the REMOTE bit to "0" to transmit or receive data frame. Set to "1" to transmit or receive remote frame. The followings occur during remote frame transmission or reception.

Transmitting the remote frame A message stored into the message slot j (j=0 to 15) is transmitted as the remote frame. After transmission, the slot automatically becomes ready to receive data frame. If the data frame is received before the remote frame is transmitted, the data frame is stored into the message slot j. The remote frame is not transmitted.
Receiving the remote frame The message slot receives the remote frame. The RSPLOCK bit determines whether or not to process the received remote frame.

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23.1.20.7 RECREQ Bit

The RECREQ bit selects transmit/receive mode shown in Table 23.4. Set the RECREQ bit to "1" (receive requested) when data frame or remote frame is received. Set the RECREQ bit to "0" (no receive requested) when data frame or remote frame is transmitted. When a data frame is automatically transmitted after a remote frame is received, the RECREQ bit remains set to "1". Set the RECREQ bit to "0" to transmit a remote frame. After a remote frame is transmitted, a data frame is automatically received while the RECREQ bit remains set to "0". When setting the TRMREQ bit to "1" (transmit requested), do not set the RECREQ bit to "1" (receive requested).

23.1.20.8 TRMREQ Bit

The TRMREQ bit selects transmit/receive mode shown in Table 23.4. Set the TRMREQ bit to "1" (transmit requested) when data frame or remote frame is transmitted. Set the TRMREQ bit to "0" (no request to transmit the frame) when data frame or remote frame is received. When the data frame is automatically received after the remote frame is transmitted, the TRMREQ bit remains set to "1". Set the TRMREQ bit to "0" to receive the remote frame. After the remote frame is received, data frame is automatically transmitted while the TRMREQ bit remains set to "0". If the RECREQ bit is set to "1" (request to receive the frame), do not set the TRMREQ bit to "1" ( request to transmit the frame). NOTES: 1. If some message slots are requested to transmit the data frame or remote frame, the message slot, having the smallest slot number starts transmitting. 2. In single-shot mode, the CiMCTLj register is set to "0016" when data transmission is failed, due to the arbitration lost or transmission error.

Page 353 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M Figure 23.30 C0SBS and C1SBS Registers

23.1.21.1 SBS03 to SBS00 Bits

If the SBS03 to SBS00 bits select a number j (j=0 to 15), the message slot j is allocated to the CANi message slot buffer 0. The message slot j can be accessed via addresses 01E0 16 to 01EF16, and 026016 to 026F16.

23.1.21.2 SBS13 to SBS10 Bits

If the SBS13 to SBS10 bits select a number j, the message slot j is allocated to the CANi message slot buffer 1. The message slot j can be accessed via addresses 01F0 16 to 01FF16, and 027016 to 027F16. CANi Slot Buffer Select Register (i=0,1) Symbol Address After Reset (2) C0SBS 0240 16 00 16 C1SBS 0250 16 00 16 SBS00 SBS01 CANi Message Slot Buffer 0 Number Select Bit CANi Message Slot Buffer 1 Number Select Bit SBS02 SBS03 SBS10 SBS11 SBS12 SBS13 0 0 0 0 : Message slot 0 0 0 0 1 : Message slot 1 0 0 1 0 : Message slot 2 0 0 1 1 : Message slot 3 (Note 1) (Note 1) Bit Name FunctionBit Symbol b3 b2 b1 b0 1 1 0 0 : Message slot 12 1 1 0 1 : Message slot 13 1 1 1 0 : Message slot 14 1 1 1 1 : Message slot 15 0 0 0 0 : Message slot 0 0 0 0 1 : Message slot 1 0 0 1 0 : Message slot 2 0 0 1 1 : Message slot 3 b3 b2 b1 b0 1 1 0 0 : Message slot 12 1 1 0 1 : Message slot 13 1 1 1 0 : Message slot 14 1 1 1 1 : Message slot 15 RW RW RW RW RW RW RW RW RW NOTES: 1. 16 CANi message slots are provided. Each message slot can be selected as a transmit or a receive slot. 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b7 b6 b5 b4 b3 b2 b1 b0

23.1.21 CANi Slot Buffer Select Register (CiSBS Register) (i=0,1)

Page 354 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Message Slot Buffer j Standard ID1 (i=0,1, j=0,1)(1) Symbol Address After Reset C0SLOT0_1, C0SLOT1_1 01E116, 01F116 Indeterminate C1SLOT0_1, C1SLOT1_1 026116, 027116 Indeterminate SID0 SID1 SID2 SID3 SID4 SID5 (b7 - b6) Standard ID0 Read or write the standard ID0 in the message slot k (k=0 to 15) Standard ID1 Standard ID2 Standard ID3 Standard ID4 Standard ID5 Read or write the standard ID1 in the message slot k Read or write the standard ID2 in the message slot k Read or write the standard ID3 in the message slot k Read or write the standard ID4 in the message slot k Read or write the standard ID5 in the message slot k Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW NOTES: 1. Select, by setting the CiSBS register, the message slot k to be accessed by the CiSLOTj_1 register. CANi Message Slot Buffer j Standard ID0 (i=0,1, j=0,1)(1) Symbol Address After Reset C0SLOT0_0, C0SLOT1_0 01E016, 01F016 Indeterminate C1SLOT0_0, C1SLOT1_0 026016, 027016 Indeterminate SID6 SID7 SID8 SID9 SID10 (b7 - b5) Standard ID6 Standard ID7 Standard ID8 Standard ID9 Standard ID10 Read or write the standard ID6 in the message slot k (k=0 to 15) Read or write the standard ID7 in the message slot k Read or write the standard ID8 in the message slot k Read or write the standard ID9 in the message slot k Read or write the standard ID10 in the message slot k Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Select, by setting the CiSBS register, the message slot k to be accessed by the CiSLOTj_0 register. RW RW RW RW RW RW

23.1.22 CANi Message Slot Buffer j (i=0,1, j=0,1)

Figure 23.31 C0SLOT0_0, C0SLOT1_0, C0SLOT0_1 and C0SLOT1_1 Registers C1SLOT0_0, C1SLOT1_0, C1SLOT0_1 and C1SLOT1_1 Registers

Page 355 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Message Slot Buffer j Extended ID1 (i=0,1, j=0,1)(1, 2) Symbol Address After Reset C0SLOT0_3, C0SLOT1_3 01E316, 01F316 Indeterminate C1SLOT0_3, C1SLOT1_3 026316, 027316 Indeterminate EID6 EID7 EID8 EID9 Extended ID6 Read or write the extended ID6 in the message slot k (k=0 to 15) Extended ID7 Extended ID8 Extended ID9 Read or write the extended ID7 in the message slot k Read or write the extended ID8 in the message slot k Read or write the extended ID9 in the message slot k EID10 EID11 Extended ID10 Extended ID11 Read or write the extended ID10 in the message slot k Read or write the extended ID11 in the message slot k EID12 EID13 Extended ID12 Extended ID13 Read or write the extended ID12 in the message slot k Read or write the extended ID13 in the message slot k Bit Name FunctionBit Symbol NOTES: 1. If the receive slot is standard ID formatted, the EID13 to EID6 bits are indeterminate when received data is stored. 2. Select, by setting the CiSBS register, the message slot k to be accessed by the CiSLOTj_3 register. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW CANi Message Slot Buffer j Extended ID0 (i=0,1, j=0,1)(1, 2) Symbol Address After Reset C0SLOT0_2, C0SLOT1_2 01E216, 01F216 Indeterminate C1SLOT0_2, C1SLOT1_2 026216, 027216 Indeterminate EID14 EID15 Extended ID14 Extended ID15 Read or write the extended ID14 in the message slot k (k=0 to 15) Read or write the extended ID15 in the message slot k EID16 EID17 (b7 - b4) Extended ID16 Extended ID17 Read or write the extended ID16 in the message slot k Read or write the extended ID17 in the message slot k Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. If the receive slot is standard ID formatted, the EID17 to EID14 bits are indeterminate when received data is stored. 2. Select, by setting the CiSBS register, the message slot k to be accessed by the CiSLOTj_2 register. RW RW RW RW RW Figure 23.32 C0SLOT0_2, C0SLOT1_2, C0SLOT0_3 and C0SLOT1_3 Registers C1SLOT0_2, C1SLOT1_2, C1SLOT0_3 and C1SLOT1_3 Registers

Page 356 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Message Slot Buffer j Data Length Code (i=0,1, j=0,1)(1) Symbol Address After Reset C0SLOT0_5, C0SLOT1_5 01E516, 01F516 Indeterminate C1SLOT0_5, C1SLOT1_5 026516, 027516 Indeterminate Read or write the data length set bit in the message slot k (k=0 to 15) DLC0 DLC1 DLC2 DLC3 (b7 - b4) Data Length Set Bit Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit Name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Select, by setting the CiSBS register, the message slot k to be accessed by the CiSLOTj_5 register. RW RW RW RW RW CANi Message Slot Buffer j Extended ID2 (i=0,1, j=0,1)(1, 2) Symbol Address After Reset C0SLOT0_4, C0SLOT1_4 01E416, 01F416 Indeterminate C1SLOT0_4, C1SLOT1_4 026416, 027416 Indeterminate EID0 EID1 EID2 EID3 Extended ID0 Read or write the extended ID0 in the message slot k (k=0 to 15) Extended ID1 Extended ID2 Extended ID3 Read or write the extended ID1 in the message slot k Read or write the extended ID2 in the message slot k Read or write the extended ID3 in the message slot k EID4 EID5 (b7 - b6) Extended ID4 Extended ID5 Read or write the extended ID4 in the message slot k Read or write the extended ID5 in the message slot k Bit Name FunctionBit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. If the receive slot is standard ID formatted, the EID5 to EID0 bits are indeterminate when received data is stored. 2. Select, by setting the CiSBS register, the message slot k to be accessed by the CiSLOTj_4 register. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW Figure 23.33 C0SLOT0_4, C0SLOT1_4, C0SLOT0_5 and C0SLOT1_5 Registers C1SLOT0_4, C1SLOT1_4, C1SLOT0_5 and C1SLOT1_5 Registers

Page 357 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M CANi Message Slot Buffer j Time Stamp High-Ordered (i=0,1, j=0,1)(1) Symbol Address After Reset C0SLOT0_14, C0SLOT1_14 01EE16, 01FE 16 Indeterminate C1SLOT0_14, C1SLOT1_14 026E16, 027E16 Indeterminate RW RW Function Setting Range Read or write the time stamp high-ordered in the message slot k (k=0 to 15) 0016 to FF16 NOTES: 1. Select, by setting the CiSBS register, the time stamp high-ordered in the message slot k to be accessed by the CiSLOTj_14 register. b7 b0 CANi Message Slot Buffer j Time Stamp Low-Ordered (i=0,1, j=0,1)(1) Symbol Address After Reset C0SLOT0_15, C0SLOT1_15 01EF16, 01FF16 Indeterminate C1SLOT0_15, C1SLOT1_15 026F16, 027F16 Indeterminate RW RW Function Setting Range Read or write the time stamp low-ordered in the message slot k (k=0 to 15) 0016 to FF16 NOTES: 1. Select, by setting the CiSBS register, the time stamp low-ordered in the message slot k to be accessed by the CiSLOTj_15 register. b7 b0 CANi Message Slot Buffer j Data m (i=0,1, j=0,1)(1, 2) Symbol Address After Reset C0SLOT0_6 to C0SLOT0_13 01E616 - 01ED16 Indeterminate C0SLOT1_6 to C0SLOT1_13 01F616 - 01FD16 Indeterminate C1SLOT0_6 to C1SLOT0_13 026616 - 026D16 Indeterminate C1SLOT1_6 to C1SLOT1_13 027616 - 027D16 Indeterminate RW RW Function Setting Range Read or write data m in the message slot k (k=0 to 15, m=0 to 7) 0016 to FF16 NOTES: 1. Select, by setting the CiSBS register, the data m in the message slot k to be accessed by the CiSLOTj_6 to CiSLOTj_13 registers. 2. When the data frame is received, data with less than the data length selected by the CiSLOTj_5 register is indeterminate. b7 b0 Figure 23.34 C0SLOT0_6 to C0SLOT0_13, C0SLOT1_6 to C0SLOT1_13, C0SLOT0_14, C0SLOT1_14, C0SLOT0_15 and C0SLOT1_15 Registers C1SLOT0_6 to C1SLOT0_13, C1SLOT1_6 to C1SLOT1_13, C1SLOT0_14, C1SLOT1_14, C1SLOT0_15 and C1SLOT1_15 Registers The message slot, selected by setting the CiSBS register, is read by reading the message slot buffer. A message can be written in the message slot selected by the CiSBS register if the message is written to the message slot buffer. Write to the message slot k (k=0 to 15) while the corresponding CiMCTLk register is set to "00 16".

Page 358 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M When a received ID is "6F316" 001100110001101 1 SID4 SID3 SID2 SID1 SID0 SID10SID9 SID8 SID7 SID6 1101111001 1 SID10 SID0 0000100011011110 Divide it to 8 bits and 3 bits Received ID Bit search information Address search information SID5 b7b8 b0b15 b7b8 b0 b7 b0 b15 0116 0216 0416 0816 1016 2016 4016 8016 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 116 216 316 416 516 616 716 Bit search information 3 low-order bits of received ID 8 bits 3 bits Because the value of the 3 bits is 3, b3 in the table left is 1. (If the value of the 3 bits is 4, b4 in the table left is 1.) Write to the CiAFS register Read from the CiAFS register i = 0, 1 CANi Acceptance Filter Support Register (i=0,1) Symbol Address After Reset (1) C0AFS 0245 16 - 024416 0100 16 C1AFS 0255 16 - 025416 0100 16 RW RW Function Setting Range Generates data to determine a received ID 000016 to FFFF16 NOTES: 1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. b15 b0 b8 b7 b15 b0 SID5 SID4 SID3 SID2 SID1 SID0 SID10SID9 SID8 SID7SID6 SID5 SID4 SID3CSID2 CSID1 CSID0 SID10SID9 SID8 SID7 SID6CSID5 CSID4 CSID3CSID7 CSID6 Write Read 3-8 decoding b7b8b15 b0 Data used to search a data table is generated from a received ID in stan- dard format. The table search with this data determines whether or not a re- ceived ID is valid. 00716 "0" 00616 "0" 00516 "0" 00416 "0" 00316 "0" 00216 "0" 00116 "1" 00016 "0" 00F16 "1" 00E16 "0" 00D 16 "0" 00C 16 "0" 00B16 "0" 00A16 "0" 00916 "0" 00816 "0" 6F716 "0" 6F616 "0" 6F516 "0" 6F416 "0" 6F316 "1" 6F216 "0" 6F116 "0" 6F016 "0" 7F716 "0" 7F616 "0" 7F516 "0" 7F416 "0" 7F316 "0" 7F216 "0" 7F116 "0" 7F016 "1" 7FF16 "0" 7FE 16 "0" 7FD 16 "1" 7FC 16 "0" 7FB 16 "0" 7FA16 "0" 7F916 "0" 7F816 "0" Top+0016 Top+0116 Top+FE16 Top+FF16 Top+DE 16 b7 b6 b5 b4 b3 b2 b1 b0 Address search information Bit search information

23.1.23 CANi Acceptance Filter Support Register (CiAFS Register) (i=0,1)

Figure 23.35 C0AFS Register and C1AFS Register The CiAFS register enables prompt performance of the table search to determine the varidity of a received ID. This function is for standard-formatted ID only.

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23.2 CAN Clock

The CAN clock is the operating clock for the CAN module. f1 or fCAN can be selected as the CAN clock. fCAN has the same frequency as the main clock. The PM25 bit in the PM2 register determines the CAN clock. Refer to 9. Clock Generation Circuit for details.

23.2.1 Main Clock Direct Mode

fCAN becomes the CAN clock in main clock direct mode. The CAN module must enter main clock direct mode while the PM25 bit is set to "1" (main clock). Set the PM25 bit in CAN sleep mode. Set the PM24 bit in the PM2 register to "1" (main clock) before accessing CAN-associated registers in main clock direct mode. Do not enter wait mode or stop mode when the PM24 bit is set to "1". Table 23.5 lists CAN clock settings. Figure 23.36 shows a flow chart of accessing procedure for CAN- associated registers. Table 23.5 CAN Clock Settings NAC kcolC ecruoSkcolC 0MC retsigeR 1MC retsigeR 2MC retsigeR retsigeR2MP DCM retsigeR tiB70MCt iB71MCt iB12MCt iB42MPt iB52MP ot4DCM stib0DCM f NAC kcolCniaM )edoMtceriDkcolCniaM( 01 011 - -- kcolCniaM 00000 0 1001 2 kcolCLLP0 1 0 0 0 0 1001 2 Figure 23.36 Accessing Procedure for CAN-Associated Registers Start Wait until a clock oscillation stabilized Set the PM24 bit in the PM2 register to "1" (main clock) Set the PM24 bit to "0" (clock selected by the CM07 bit in the CM0 register) Access to CAN-associated registers End NOTES: 1. Waiting time varies depending on the CPU clock frequency before or after PM24 bit setting is changed. 2 x High FrequencyCycles Low Frequency - High Frequency : Higher Frequency compared "before PM24 bit setting changes" with "after PM24 bit setting changes" - Low Frequency : Lower Frequency compared "before PM24 bit setting changes" with "after PM24 bit setting changes" Waiting Time≥

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23.3 Timing with CAN-Associated Registers

23.3.1 CAN Module Reset Timing

Figure 23.37 shows an operation example of when the CAN module is reset. (1) The CAN module can be reset when the STATE_RESET bit in the CiSTR register (i=0,1) is set to "1" (CAN module reset completed) after the RESET1 and RESET0 bits in the CiCTLR0 register are set to "1" (CAN module reset). (2) Set necessary CAN-associated registers. (3) CAN communication can be established after the STATE_RESET bit is set to "0" (resetting) after the RESET1 and RESET0 bits are set to "0" (CAN module reset exited) . Figure 23.37 Example of CAN Module Reset Operation

23.3.2 CAN Transmit Timing

Figure 23.38 shows an operation example of when the CAN transmits a frame. (1) When the TRMREQ bit in the CiMCTLj register (j=0 to 15) is set to "1" (request to transmit the data frame) while the CAN bus is in an idle state, the TRMACTIVE bit in the CiMCTLj register is set to "1" (during transmission) and the TRMSTATE bit in the CiSTR register is set to "1" (during trans- mission). The CAN starts transmitting the frame. (2) After a CAN frame transmission is completed, the SENTDATA bit in the CiMCTLj register is set to "1" (already transmitted), the TRMSUCC bit in the CiSTR register to "1" (transmission completed) and the SISj bit in the CiSISTR register to "1" (interrupt requested). The MBOX3 to MBOX0 bits in the CiSTR register store transmitted message slot numbers. RESET0 bit "1" "0" RESET1 bit "1" "0" STATE_RESET bit "1" "0" Initial Setting for the CAN Module Verify the STATE_RESET bit CAN Operation Set to "1" by program simultaneously Operation (1) Set to "0" by program simultaneously Operation (2) Operation (3) Verify the STATE_RESET bit

Page 361 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M NEWDATA bit RECREQ bit MBOX3 to MBOX0 bits Start receiving Intermission field CAN bus Receive frame INVALDATA bit RECSUCC bit RECSTATE bit SISj bit (1) (4)(3) Set to "1" by program Bus idle Bus idleReceive frame "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0"j=0 to 15 Reception-completed message slot number Reception completed (2) Figure 23.38 Example of CAN Data Frame Transmit Operation

23.3.3 CAN Receive Timing

Figure 23.39 shows an operation example of when the CAN receives a frame. (1) When the RECREQ bit in the CiMCTLj register (i=0,1, j= 0 to 15) is set to "1" (receive requested), the CAN is ready to receive the frame at anytime. (2) When the CAN starts receiving the frame, the RECSTATE bit in the CiSTR register is set to "1" (during reception). (3) After the CAN frame reception is completed, the INVALDATA bit in the CiMCTLj register is set to "1" (storing received data), the NEWDATA bit in the CiMCTLj register is set to "1" (receive com- plete) and the RECSUCC bit in the CiSTR register is set to "1" (reception completed). (4) After data is written to the message slot, the INVALDATA bit is set to "0" (storing receiving data) and the SISj bit in the CiSISTR register is set to "1" (interrupt requested). The MBOX3 to MBOX0 bits in the CiSTR register store received message slot numbers. SENTDATA bit TRMREQ bit MBOX3 to MBOX0 bits Bus idle Start transmtting (1) Intermission field CAN bus Transmit frame "1" "0" "1" "0" TRMACTIVE bit "1" "0" Set to "1" by program TRMSUCC bit "1" "0" TRMSTATE bit "1" "0" SISj bit "1" "0" Transmit frame Bus idle j=0 to 15 Transmission-completed message slot number Transmission completed (2) Figure 23.39 Example of CAN Data Frame Receive Operation

Page 362 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M (1) STATE_BUSERROR bit CAN bus Error frameTransmit / receive frame BEIS bit Error detected "1" "0" "1" "0"

23.3.4 CAN Bus Error Timing

Figure 23.40 shows an operation example of when a CAN bus error occurs. (1) When a CAN bus error is detected, the STATE_BUSERROR bit in the CiSTR register is set to "1", (error occurred) and the BEIS bit in the CiEISTR register is set to "1" (interrupt requested). The CAN starts transmitting the error frame. Figure 23.40 Operation Timing when CAN Bus Error Occurs

23.4 CAN Interrupts

The CAN1 wake-up interrupt and CANij interrupts (i=0,1,j=0 to 2) are provided as the CAN interrupt.

23.4.1 CAN1 Wake-Up Interrupt

When a signal applied to the CAN1WU pin is on the falling edge, the CAN1WUR bit in the IIO5IR register is set to "1" (interrupt requested). At this time, the IR bit in the CAN5IC register is set to "1" (interrupt requested) if the CAN1WUE bit in the IIO5IE register is set to "1" (interrupt enabled). If P7 7 (CAN0IN) is used as a CAN0 input port, the CAN0 wake-up interrupt is available by using event counter mode of Timer A3 (TA3IN) that shares a pin with CAN0. If P83 (CAN0IN/CAN1 IN) is used as a CAN input port, the CAN0 and CAN1 wake-up interrupts are available by using INT1 that shares a pin with CAN0IN/CAN1 IN.

23.4.2 CANij Interrupts

Figure 23.41 shows a block diagram of the CANij interrupts. The followings cause the CAN-associated interrupt request to be generated. - The CANi slot k (k=0 to 15) completes a transmission - The CANi slot k completes a reception - The CANi module detects a bus error - The CANi module moves into an error-passive state - The CANi module moves into a bus-off state The INTSEL bit in the CiCTLR1 register determines how an interrupt request is generated. When the INTSEL bit is set to "0", one of the above CANi interrupt request source causes the CANij interrupts to be generated by the OR circuit. When the INTSEL bit is set to "1", CANi transmission completed, CANi reception completed and CANi errors (CANi bus error detection, CANi module into error-passive state and CANi module into bus-off state) cause the CANij interrupt corresponding to each source to be generated.

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23.4.2.1 When the INTSEL Bit is Set to "0"

If the CAN-associated interrupt is generated by one of the interrupt request source listed in 23.4.2 CANij Interrupts, the corresponding bit in the CiSISTR register (i=0,1) is set to "1" (interrupt re- quested) when the CANi slot k completes a transmission or a reception. The corresponding bit in the CiEISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error, moves into an error-passive state, or moves into a bus-off state. The CANi interrupt request signal is set to "1" when the corresponding bit in the CiSISTR or CiEISTR is set to "1" and the corresponding bit in the CiSIMKR or CiEIMKR is set to "1" When the CAN0 interrupt request signal changes "0" to "1", all CAN0jR bits (j=0 to 2) in the IIO9IR to IIO11IR registers are set to "1" (interrupt requested). If at least one of the CAN0jE bits in the IIO9IE to IIO11IE registers is set to "1" (interrupt enabled), the IR bits in the corresponding CAN0IC to CAN2IC registers are set to "1" (interrupt requested). The CAN0 interrupt request signal remains set to "1" if another interrupt request source causes a corre- sponding bit in the C0SISTR or C0EISTR to be set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR to be set to "1" after the CAN0 interrupt request signal changes "0" to "1". The CAN0jR and IR bits also remain unchanged. When the CAN1 interrupt request signal changes "0" to "1", all three CAN1jR bits in the IIO0IR to IIO1IR and IIO5IR registers are set to "1" (interrupt requested). If at least one of the CAN1jE bits in the IIO0IE to IIO1IE and IIO5IE registers is set to "1", the IR bits in the corresponding CAN3IC to CAN5IC registers are set to "1". The CAN0 interrupt request signal remains set to "1" if another interrupt request causes the corresponding bit in the C1SISTR or C1EISTR to be set to "1" and the corresponding bit in the C1SIMKR or C1EIMKR to be set to "1" after the CAN1 interrupt request signal changes "0" to "1". The CAN1jR and IR bits also remain unchanged. Bits in the CiSISTR or CiEISTR register and CANijR bits (i=0,1, j=0 to 2) in the IIO0IR to IIO1IR, IIO5IR or IIO9IR to IIO11IR registers are not set to "0" automatically, interrupt acknowledgment notwithstand- ing. Set these bits to "0" by program. The CANi interrupts are acknowledged when the CANijR bit in the IIO0IR to IIO1IR, IIO5IR or IIO9IR to IIO11IR register and the corresponding bit in the CiSISTR or CiEISTR register are set to "0". If these bits remain set to "1", all CAN-associated interrupt request source become invalid.

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23.4.2.2 When the INTSEL Bit is Set to "1"

If the CAN-associated interrupt is generated by one of the interrupt request source listed in 23.3.2 CANij Interrupts, the corresponding bit in the CiSISTR register (i=0,1) is set to "1" (interrupt re- quested) when the CANi slot k completes a transmission or a reception. The corresponding bit in the CiEISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error, goes into an error-passive state, or goes into a bus-off state. The CANi receive interrupt request signal is set to "1" if the corresponding bit in the CiSIMKR register is set to "1" (interrupt request enabled) and the corresponding bit in the CiSISTR register is set to "1" when the CANi module completes a reception. The CANi transmit interrupt request signal is set to "1" if the corresponding bit in the CiSIMKR register is set to "1" and the corresponding bit in the CiSISTR register is set to "1" when the CANi module completes a transmission. The CANi error interrupt request signal is set to "1" if corresponding bits in the CiEIMKR register are set to "1" and the corresponding bit in the CiEISTR register is set to "1" when the CANi module detects a bus error, goes into an error-passive state, or goes into a bus-off state. When the CANi receive interrupt request signal changes "0" to "1", the CAN00R bit in the IIO9IR register and the CAN10R bit in the IIO0IR registers are set to "1" (interrupt requested). If the CAN00E in the IIO9IE register is set to "1" (interrupt enabled), the IR bit in the CAN0IC register is set to "1" (interrupt requested). If the CAN10E bit in the IIO0IE register is set to "1" (interrupt enabled), the IR bit in the CAN3IC register is set to "1" (interrupt requested). When the CANi transmit interrupt request signal changes "0" to "1", the CAN01R bit in the IIO10IR register and the CAN11R bit in the IIO1IR registers are set to "1" (interrupt requested). If the CAN01E in the IIO10IE register is set to "1" (interrupt enabled), the IR bit in the CAN1IC register is set to "1" (interrupt requested). If the CAN11E bit in the IIO1IE register is set to "1" (interrupt enabled), the IR bit in the CAN4IC register is set to "1" (interrupt requested). When the CANi error interrupt request signal changes "0" to "1", the CAN02R bit in the IIO11IR register and CAN12R bit in the IIO5IR register are set to "1" (interrupt requested). If the CAN02E in the IIO11IE register is set to "1" (interrupt enabled), the IR bit in the CAN2IC register is set to "1" (interrupt re- quested). If the CAN12E bit in the IIO5IE register is set to "1" (interrupt enabled), the IR bit in the CAN5IC register is set to "1" (interrupt requested). The CANi error interrupt request signal remains set to "1" if another interrupt request causes the corresponding bit in the CiEIMKR register is set to "1" and the corresponding bit in the CiEISTR to be set to "1" after the CANi error interrupt request signal changes "0" to "1". The CAN02R, CAN12R and IR bits also remain unchanged. Bits in the CiSISTR or CiEISTR register and CANijR bits (i=0,1, j=0 to 2) in the IIO0IR to IIO1IR, IIO5IR or IIO9IR to IIO11IR registers are not set to "0" automatically, interrupt acknowledgment notwithstand- ing. Set these bits to "0" by program. The CANi receive interrupt and CANi transmit interrupt are acknowledged when the CAN00R bit in the IIO9IR register, the CAN01R bit in the IIO10IR register, the CAN10R bit in the IIO0IR register and the CAN11R bit in the IIO1IR register are set to "0". Corresponding bits in the CiSISTR register can be set to either "0" or "1". The CANi error interrupt is acknowledged when the CAN02R bit in the IIO11IR register, the CAN12R bit in the IIO5IR register and corresponding bits in the CiEISTR register are set to "0". If these bits remain set to "1", all CAN-associated interrupt request source become invalid.

Page 365 974fo5002,80.peS00.1.veR 0010-4020B90JER 23. CAN Module)T68/C23M,68/C23M(puorG68/C23M SIM0 bit CANi Slot 0 Received CANi Slot 0 Transmitted CANi Slot 15 Received CANi Slot 15 Transmitted CANi Interrupt Request/ CANi Receive Interrupt Request Signal CANi Interrupt Request/ CANi Transmit Interrupt Request Signal CANi Interrupt Request/ CANi Error Interrupt Request Signal i=0, 1 CANi Bus Error Detection CANi Module into Error-Passive State CANi Module into Bus-Off State SIS0 bit SIM15 bit SIS15 bit BEIM bit BEIS bit EPIS bit EPIM bit BOIM bit BOIS bit INTSEL bit "1" "0" INTSEL bit "1" "0" INTSEL bit "1" "0" Figure 23.41 CAN Interrupts

Page 366 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M 24. Programmable I/O Ports 123 programmable I/O ports from P0 to P15 (excluding P85) are available. The direction registers deter- mine each port status, input or output. The pull-up control registers determine whether the ports, divided into groups of four ports, are pulled up or not. P8 5 is an input port and no pull-up for this port is allowed. The P8_5 bit in the P8 register indicates an NMI input level since P85 shares pins with NMI. Figures 24.1 to 24.4 show programmable I/O port configurations. Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus control pin. To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each fuction. Refer to 8. Bus when used as the bus control pin. The registers associated with the programmable I/O ports are as follows.

24.1 Port Pi Direction Register (PDi Register, i=0 to 15)

Figure 24.5 shows the PDi register. The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register corresponds to a port. In memory expansion and microprocessor mode, the PDi register cannot control pins being used as bus control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT , HLDA/ ALE, HOLD, ALE and RDY). No bit controlling P85 is provided in the direction registers.

24.2 Port Pi Register (Pi Register, i=0 to 15)

Figure 24.6 shows the Pi register. The Pi register writes and reads data to communicate with external devices. The Pi register consists of a port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port. In memory expansion and microprocessor mode, the Pi register cannot control pins being used as bus control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT , HLDA/ ALE, HOLD, ALE and RDY).

24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9)

Figures 24.7 to 24.11 show the PSj registers. The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a periph- eral function output (excluding DA0 and DA1.) When multiple peripheral function outputs are assigned to a pin, set the PSL0 to PSL3, PSL6, PSL7, PSC, PSC2, PSC3 and PSD1 registers to select which function is used. Tables 24.3 to 24.12 list peripheral function output control settings for each pin.

24.4 Function Select Register Bk (PSLk Registers) (k=0 to 3, 6, 7)

Figures 24.12 to 24.14 show the PSLk registers. When multiple peripheral function outputs are assigned to a pin, the PSLk registers select which peripheral function output is used. Refer to 24.10 Analog Input and Other Peripheral Function Input for the PSL3_6 to PSL3_3 bits in the PSL3 register.

Page 367 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M

24.5 Function Select Register C, C2, C3 (PSC, PSC2, PSC3 Registers)

Figures 24.15 and 24.16 show the PSC, PSC2 and PSC3 registers. When multiple peripheral function outputs are assigned to a pin, the PSC, PSC2 and PSC3 registers select which peripheral function output is used. Refer to 24.10 Analog Input and Other Peripheral Function Input for the PSC_7 bit in the PSC register.

24.6 Function Select Register D (PSD1 Register)

Figure 24.16 shows the PSD1 register. When multiple peripheral function outputs are assigned to a pin, the PSD1 register selects which peripheral function output is used.

24.7 Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)

Figures 24.17 and 24.18 show the PUR0 to PUR4 registers. The PUR0 to PUR4 registers select whether the ports, divided into groups of four ports, are pulled up or not. Ports with bits in the PUR0 to PUR4 registers set to "1" (pull-up) and the direction registers set to "0" (input mode) are pulled up. Set bits in the PUR0 and PUR1 registers in P0 to P5, running as bus, to "0" (no pull-up) in memory expan- sion mode and microprocessor mode. P0, P1 and P4 0 to P43 can be pulled up when they are used as input ports in memory expansion mode and microprocessor mode.

24.8 Port Control Register (PCR Register)

Figure 24.19 shows the PCR register. The PCR register selects either CMOS output or N-channel open drain output as the P1 output format. If the PCR0 bit is set to "1", N-channel open drain output is selected because the P-channel in the CMOS port is turned off. This is, however, not a perfect open drain. Therefore, the absolute maximum rating of the input voltage is between -0.3V and V CC + 0.3V. If P1 is used as the data bus in memory expansion mode and microprocessor mode, set the PCR0 bit to "0". If P1 is used as a port in memory expansion mode and microprocessor mode, the PCR0 bit determines the output format.

24.9 Input Function Select Register (IPS and IPSA Registers)

Figures 24.19 and 24.20 show the IPS and IPSA registers. The IPS3, IPS1 and IPS0 bits in the IPS register and the IPSA_3 and IPSA_0 bits in the IPSA register select which pin is assigned for the intelligent I/O or CAN input functions. Refer to 24.10 Analog Input and Other Peripheral Function Input for the IPS2 bit.

24.10 Analog Input and Other Peripheral Function Input

The PSL3_6 to PSL3_3 bits in the PSL3 register, the PSC_7 bit in the PSC register and the IPS2 bit in the IPS register each separate analog I/O ports from other peripheral functions. Setting the corresponding bit to "1" (analog I/O) to use the analog I/O port (DA0, DA1, ANEX0, ANEX1, AN 4 to AN7 or AN150 to AN157) prevents an intermediate potential from being impressed to other peripheral functions. The impressed inter- mediate potential may cause increase in power consumption. Set the corresponding bit to "0" (except analog I/O) when analog I/O is not used. All peripheral function inputs except the analog I/O port are available when the corresponding bit is set to "0". These inputs are indeterminate when the bit is set to "1". When the PSC_7 bit is set to "1", key input interrupt request remains unchanged regardless of KI0 to KI3 pin input level change.

Page 368 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.1 Programmable I/O Ports (1) Direction Register Port Latch Input to each Peripheral Function Analog Signal Select Pull-up Data Bus A B C P00 to P07 P20 to P27 P30 to P37 P40 to P47 P50 to P52 P54 P55 P56 P57 P83, P84 P86 P87 P100 to P103 P104 to P107 P114 P144 to P146 P152 to P157 Option Port (A) Hysteresis Circuit (B) Peripheral Function Input Circuit (C) Analog I/F : Available : Not Available Programmable I/O Ports

Page 369 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.2 Programmable I/O Ports (2) P10 to P14 Option Port (A) Hysteresis Circuit (B) Peripheral Function Input P15 to P17 Direction Register Port Latch Input to each Peripheral Function Select Pull-up Data Bus A B PCR Register : Available : Not Available Programmable I/O Ports with the Port Control Register Port : P72, P73, P74, P75, P80, P81 Direction Register Port Latch Input to each Peripheral Function Select Pull-up RESET NMI INV05 INV02 Data Bus Output from each Peripheral Function PS1 and PS2 Registers R D Programmable I/O Ports with the Function Select Register QT INV03 Write Signal to INV03 Value Written to INV03

Page 370 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.3 Programmable I/O Ports (3) A B C P53 P60 to P67 P82 P90 to P92 P93 to P96 P140 to P143 P120 to P127 P130 to P137 P150 P151 Option Port (A) Hysteresis Circuit (B) Peripheral Function Input Circuit (C) Analog I/F P70, P71 P76, P77 P97 P110 to P113 Circuit (D) Direction Register Port Latch Input to each Peripheral Function Analog Signal Select Pull-up Data Bus PS0 to PS9 Registers NOTES: 1. P7 0 and P71 are ports for the N-channel open drain output. D Output from each Peripheral Function (1) : Available : Not Available Programmable I/O ports with the Function Select Register

Page 372 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.6 P0 to P15 Registers NOTES: 1. In memory expansion mode and microprocessor mode, the Pi register cannot control pins being used as bus control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLK OUT , HLDA/ALE, HOLD, ALE and RDY). M32C/86T cannot be used in memory expansion mode and microprocessor mode. 2. P7 0 and P71 are ports for the N-channel open drain output. The pins go into high-impedance states when P70 and P71 output "H" signal. 3. The P8_5 bit is for read only. 4. Nothing is assigned in the P11_7 to P11_5 bits in the P11 register and the P14_7 bit in the P14 register. If write, set these bits to "0". When read, their contents are indeterminate. Function Port Pi Register (i=0 to 15)(1, 2) Bit NameBit Symbol Symbol Address After Reset P0 to P5 03E0 16, 03E116, 03E416, 03E516, 03E816, 03E916 Indeterminate P6 to P10 03C0 16, 03C116(3), 03C416(4), 03C516, 03C816 Indeterminate P11 to P15 03C916(5), 03CC16, 03CD16, 03D016(5), 03D116 Indeterminate RW Pi_0 Pi_1 Pi_2 Port Pi

0 Bit

Pi_3 Pi_4 Pi_5 Pi_7 Pi_6 Port Pi

1 Bit

Pin levels can be read by reading bits corresponding to programmable ports in input mode. Pin levels can be controlled by writing to bits corresponding to programmable ports in output mode. 0: "L" level 1: "H" level b7 b6 b5 b4 b3 b2 b1 b0

Page 373 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.7 PS0 Register and PS1 Register Function Function Select Register A0 Bit NameBit Symbol Symbol Address After Reset PS0 03B0 16 00 16 RW PS0_0 PS0_1 Port P60 Output Function Select Bit PS0_3 PS0_4 PS0_5 PS0_7 0 : I/O port 1 : RTS0 0 : I/O port 1 : CLK0 output 0 : I/O port 1 : TXD0/SDA0 output 0 : I/O port 1 : Selected by the PSL0_4 bit 0 : I/O port 1 : CLK1 output 0 : I/O port 1 : TXD1/SDA1 output Port P61 Output Function Select Bit Port P63 Output Function Select Bit Port P64 Output Function Select Bit Port P65 Output Function Select Bit Port P67 Output Function Select Bit PS0_2 Port P62 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL0_2 bit PS0_6 Port P66 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL0_6 bit RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Function Select Register A1 Bit NameBit Symbol Symbol Address After Reset PS1 03B1 16 00 16 RW PS1_0 PS1_1 Port P70 Output Function Select Bit PS1_3 PS1_4 PS1_5 PS1_7 0 : I/O port 1 : Selected by the PSL1_0 bit 0 : I/O port 1 : Selected by the PSL1_7 bit Port P71 Output Function Select Bit Port P73 Output Function Select Bit Port P74 Output Function Select Bit Port P75 Output Function Select Bit Port P77 Output Function Select Bit PS1_6 Port P76 Output Function Select Bit PS1_2 Port P72 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL1_1 bit 0 : I/O port 1 : Selected by the PSL1_2 bit 0 : I/O port 1 : Selected by the PSL1_3 bit 0 : I/O port 1 : Selected by the PSL1_4 bit 0 : I/O port 1 : Selected by the PSL1_5 bit 0 : I/O port 1 : Selected by the PSL1_6 bit RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0

Page 374 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.8 PS2 Register and PS3 Register Function Function Select Register A2 Bit NameBit Symbol Symbol Address After Reset PS2 03B4 16 00X0 0000 2 PS2_0 PS2_1 Port P80 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL2_0 bit Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Port P81 Output Function Select Bit PS2_2 (b4 - b3) (b5) (b7 - b6) Port P82 Output Function Select Bit Reserved Bit Set to "0" Reserved Bit Set to "0" RW RW RW RW RW RW 0 : I/O port 1 : Selected by the PSL2_1 bit 0 : I/O port 1 : Selected by the PSL2_2 bit b7 b6 b5 b4 b3 b2 b1 b0 0000 Function Function Select Register A3(1) Bit NameBit Symbol Symbol Address After Reset PS3 03B5 16 00 16 PS3_0 PS3_1 Port P90 Output Function Select Bit PS3_3 PS3_4 PS3_5 PS3_7 0 : I/O port 1 : CLK3 output 0 : I/O port 1 : RTS3 0 : I/O port 1 : CLK4 output Port P91 Output Function Select Bit Port P93 Output Function Select Bit Port P94 Output Function Select Bit Port P95 Output Function Select Bit Port P97 Output Function Select Bit PS3_6 0 : I/O port 1 : Selected by the PSC3_6 bit Port P96 Output Function Select Bit PS3_2 Port P92 Output Function Select Bit 0 : I/O port 1 : RTS4 0 : I/O port 1 : Selected by the PSL3_1 bit 0 : I/O port 1 : Selected by the PSL3_2 bit 0 : I/O port 1 : Selected by the PSL3_7 bit NOTES: 1. Set the PS3 register immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PS3 register. b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW

Page 375 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.9 PS5 Register and PS6 Register Function Function Select Register A5 Bit NameBit Symbol Symbol Address After Reset PS5 03B9 16 XXX0 0000 2 RW PS5_0 PS5_1 Port P110 Output Function Select Bit 0 : I/O port 1 : OUTC10/ ISTXD1/BE1OUT 0 : I/O port 1 : OUTC1 1/ ISCLK1 output Port P111 Output Function Select Bit PS5_2 Port P112 Output Function Select Bit 0 : I/O port 1 : OUTC12 PS5_3 (b4) (b7 - b5) Port P113 Output Function Select Bit 0 : I/O port 1 : OUTC1 Reserved Bit Set to "0" Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Function Select Register A6 Bit NameBit Symbol Symbol Address After Reset PS6 03BC 16 00 16 PS6_0 PS6_1 Port P120 Output Function Select Bit PS6_3 PS6_4 PS6_5 PS6_7 0 : I/O port 1 : Selected by the PSL6_0 bit 0 : I/O port 1 : Selected by the PSL6_3 bit 0 : I/O port 1 : Selected by the PSL6_5 bit Port P121 Output Function Select Bit Port P123 Output Function Select Bit Port P124 Output Function Select Bit Port P125 Output Function Select Bit Port P127 Output Function Select Bit PS6_6 0 : I/O port 1 : Selected by the PSL6_6 bit Port P126 Output Function Select Bit PS6_2 Port P122 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL6_4 bit 0 : I/O port 1 : Selected by the PSL6_1 bit 0 : I/O port 1 : Selected by the PSL6_2 bit 0 : I/O port 1 : Selected by the PSL6_7 bit b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW

Page 376 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.10 PS7 Register and PS8 Register Function Function Select Register A7 Bit NameBit Symbol Symbol Address After Reset PS7 03BD 16 00 16 PS7_0 PS7_1 Port P130 Output Function Select Bit PS7_3 PS7_4 PS7_5 PS7_7 0 : I/O port 1 : Selected by the PSL7_0 bit 0 : I/O port 1 : Selected by the PSL7_3 bit 0 : I/O port 1 : Selected by the PSL7_5 bit Port P131 Output Function Select Bit Port P133 Output Function Select Bit Port P134 Output Function Select Bit Port P135 Output Function Select Bit Port P137 Output Function Select Bit PS7_6 0 : I/O port 1 : Selected by the PSL7_6 bit Port P136 Output Function Select Bit PS7_2 Port P132 Output Function Select Bit 0 : I/O port 1 : Selected by the PSL7_4 bit 0 : I/O port 1 : Selected by the PSL7_1 bit 0 : I/O port 1 : Selected by the PSL7_2 bit 0 : I/O port 1 : Selected by the PSL7_7 bit b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Function Function Select Register A8 Bit NameBit Symbol Symbol Address After Reset PS8 03A0 16 X000 0000 2 PS8_0 PS8_1 Port P140 output function select bit 0 : I/O port 1 : OUTC14 0 : I/O port 1 : OUTC1 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Port P14 1 output function select bit PS8_2 Port P142 output function select bit 0 : I/O port 1 : OUTC16 0 : I/O port 1 : OUTC1 PS8_3 (b6 - b4) (b7) Port P143 output function select bit 00 0 Reserved bit Set to "0" RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0

Page 377 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Function Function Select Register A9 Bit NameBit Symbol Symbol Address After Reset PS9 03A1 16 00 16 PS9_0 PS9_1 (b7 - b2) Port P150 Output Function Select Bit 0 : I/O port 1 : ISTXD0 0 : I/O port 1 : ISCLK0 output Port P151 Output Function Select Bit Reserved Bit Set to "0" RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 000 00 0 Figure 24.11 PS9 Register

Page 378 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.12 PSL0 Register and PSL1 Register Function Function Select Register B0 Bit NameBit Symbol Symbol Address After Reset PSL0 03B2 16 00 16 PSL0_4 Port P64 Output Peripheral Function Select Bit 0 : RTS1 1 : Do not set to this value PSL0_6 Port P66 Output Peripheral Function Select Bit 0 : SCL1 output 1 : ST XD1 PSL0_2 (b1 - b0) (b3) (b5) (b7) Port P62 Output Peripheral Function Select Bit 0 : SCL0 output 1 : ST XD0 Reserved Bit Set to "0" Reserved Bit Set to "0" Reserved Bit Set to "0" Reserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 000 0 0 RW RW RW RW RW RW RW RW Function Function Select Register B1 Bit NameBit Symbol Symbol Address After Reset PSL1 03B3 16 00 16 PSL1_0 PSL1_1 Port P70 Output Peripheral Function Select Bit PSL1_3 PSL1_4 PSL1_5 0 : Selected by the PSC_0 bit 1 : TA0OUT output(1) 0 : Selected by the PSC_1 bit 1 : ST XD2 (1) 0 : Selected by the PSC_3 bit 1 : V (1) 0 : Selected by the PSC_4 bit 1 : W (1) 0 : W 1 : OUTC1 2 Port P71 Output Peripheral Function Select Bit Port P73 Output Peripheral Function Select Bit Port P74 Output Peripheral Function Select Bit Port P75 Output Peripheral Function Select Bit PSL1_6 0 : Selected by the PSC_6 bit 1 : TA3OUT output(1) Port P76 Output Peripheral Function Select Bit PSL1_7 0 : ISCLK0 output 1 : OUTC14 Port P77 Output Peripheral Function Select Bit PSL1_2 Port P72 Output Peripheral Function Select Bit 0 : Selected by the PSC_2 bit 1 : TA1OUT output(1) RW RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. When setting the PSL1_i (i = 0 to 4, 6) bit to "1", set the corresponding PSC_i bit in the PSC register to "0".

Page 379 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.13 PSL2 Register and PSL3 Register Function Function Select Register B2 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit NameBit Symbol Symbol Address After Reset PSL2 03B6 16 00X0 0000 2 PSL2_0 PSL2_1 Port P80 Output Peripheral Function Select Bit 0 : TA4OUT output 1 : U Port P81 Output Peripheral Function Select Bit PSL2_2 (b4 - b3) (b5) (b7 - b6) 0 : Do not set to this value 1 : Selected by the PSC2_2 bit Port P82 Output Peripheral Function Select Bit RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 0 : U 1 : Selected by the PSC2_1 bit Reserved Bit Set to "0" Reserved Bit Set to "0" 0 00 0 Function Function Select Register B3 Bit NameBit Symbol Symbol Address After Reset PSL3 03B7 16 00 16 PSL3_1 (b0) PSL3_3 PSL3_4 PSL3_5 PSL3_7 0 : SCL3 output 1 : STxD3 0 : Except DA0 1 : DA0(1) 0 : Except ANEX0 1 : ANEX0 (1) 0 : SCL4 output 1 : STxD4 Port P91 Output Peripheral Function Select Bit Port P93 Output Peripheral Function Select Bit Port P94 Output Peripheral Function Select Bit Port P95 Output Peripheral Function Select Bit Port P97 Output Peripheral Function Select Bit PSL3_6 Port P96 Output Peripheral Function Select Bit PSL3_2 Port P92 Output Peripheral Function Select Bit 0 : TxD3/SDA3 output 1 : Do not set to this value RW RW RW RW RW RW RW RW RW 0 : Except DA1 1 : DA1 (1) 0 : Except ANEX1 1 : ANEX1 (1) NOTES: 1. Although DA0, DA1, ANEX0 and ANEX1 can be used when this bit is set to "0", power consumption may increase. b7 b6 b5 b4 b3 b2 b1 b0 Reserved Bit Set to "0"

Page 380 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.14 PSL6 Register and PSL7 Register Function Function Select Register B6 Bit NameBit Symbol Symbol Address After Reset PSL6 03BE 16 00 16 PSL6_1 PSL6_3 PSL6_4 PSL6_5 PSL6_7 Port P121 Output Peripheral Function Select Bit Port P123 Output Peripheral Function Select Bit Port P124 Output Peripheral Function Select Bit Port P125 Output Peripheral Function Select Bit Port P127 Output Peripheral Function Select Bit PSL6_6 Port P126 Output Peripheral Function Select Bit PSL6_2 Port P122 Output Peripheral Function Select Bit RW RW RW RW RW RW RW RW RW PSL6_0 Port P120 Output Peripheral Function Select Bit 0 : Do not set to this value 1 : GASP0 output 0 : Do not set to this value 1 : GASM0 output 0 : Do not set to this value 1 : GACP0 output 0 : Do not set to this value 1 : GACM0 output 0 : Do not set to this value 1 : GASP1 output 0 : Do not set to this value 1 : GASM1 output 0 : Do not set to this value 1 : GACP1 output 0 : Do not set to this value 1 : GACM1 output b7 b6 b5 b4 b3 b2 b1 b0 Function Function Select Register B7 Bit NameBit Symbol Symbol Address After Reset PSL7 03BF 16 00 16 PSL7_1 PSL7_3 PSL7_4 PSL7_5 PSL7_7 Port P131 Output Peripheral Function Select Bit Port P133 Output Peripheral Function Select Bit Port P134 Output Peripheral Function Select Bit Port P135 Output Peripheral Function Select Bit Port P137 Output Peripheral Function Select Bit PSL7_6 Port P136 Output Peripheral Function Select Bit PSL7_2 Port P132 Output Peripheral Function Select Bit RW RW RW RW RW RW RW RW RW PSL7_0 Port P130 Output Peripheral Function Select Bit 0 : Do not set to this value 1 : GASP2 output 0 : Do not set to this value 1 : GASM2 output 0 : Do not set to this value 1 : GACP2 output 0 : Do not set to this value 1 : GACM2 output 0 : Do not set to this value 1 : GASP3 output 0 : Do not set to this value 1 : GASM3 output 0 : Do not set to this value 1 : GACP3 output 0 : Do not set to this value 1 : GACM3 output b7 b6 b5 b4 b3 b2 b1 b0

Page 381 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Function Function Select Register C Bit NameBit Symbol Symbol Address After Reset PSC 03AF 16 00X0 0000 2 PSC_0 PSC_3 PSC_4 (b5) PSC_7 0 : TxD2/SDA2 output 1 : Selected by the PSD1_0 bit 0 : RTS2 1 : OUTC10/ISTxD1/BE1OUT 0 : TA2OUT output 1 : OUTC11/ISCLK1 0 : P104 to P107 or KI0 to KI3 1 : AN4 to AN7(1) Port P70 Output Peripheral Function Select Bit Port P73 Output Peripheral Function Select Bit Port P74 Output Peripheral Function Select Bit Key Input Interrupt Disabled Select Bit PSC_6 0 : Selected by the PSD1_6 bit 1 : CAN0OUT Port P76 Output Peripheral Function Select Bit PSC_2 Port P72 Output Peripheral Function Select Bit 0 : CLK2 output 1 : V Nothing is assigned. When write, set to "0". When read, its content is indeterminate. PSC_1 Port P71 Output Peripheral Function Select Bit 0 : SCL2 output 1 : Selected by the PSD1_1 bit RW RW RW RW RW RW RW RW NOTES: 1. Set the ILVL2 to ILVL0 bits in the the KUPIC register to "0002" (interrupt disabled) when changing the PSC_7 bit setting. Although AN 4 to AN7 can be used when this bit is set to "0", power consumption may increase. b7 b6 b5 b4 b3 b2 b1 b0 Function Function Select Register C2 Bit NameBit Symbol Symbol Address After Reset PSC2 03AC 16 XXXX X00X 2 PSC2_2 Port P82 Output Peripheral Function Select Bit 0 : CAN0OUT 1 : CAN1OUT Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. PSC2_1 (b0) (b7 - b3) Port P81 Output Peripheral Function Select Bit 0 : Do not set to this value 1 : OUTC15 RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 24.15 PSC Register and PSC2 Register

Page 382 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Function Function Select Register C3 Bit NameBit Symbol Symbol Address After Reset PSC3 03AD 16 X0XX XXXX 2 PSC3_6 (b5 - b0) (b7) Port P96 Output Peripheral Function Select Bit 0 : TxD4/SDA4 output 1 : CAN1OUT Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Function Select Register D1 Bit NameBit Symbol Symbol Address After Reset PSD1 03A7 16 X0XX XX00 2 PSD1_6 Port P76 Output Peripheral Function Select Bit 0 : ISTxD0 1 : OUTC13 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW PSD1_0 Port P7

0 Output Peripheral

0 : Do not set to this value 1 : OUTC16 RW PSD1_1 (b5 - b2) (b7) Port P71 Output Peripheral Function Select Bit 0 : Do not set to this value 1 : OUTC17 RW b7 b6 b5 b4 b3 b2 b1 b0 Figure 24.16 PSC3 Register and PSD1 Register

Page 383 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.17 PUR0 Register, PUR1 Register and PUR2 Register Function Pull-Up Control Register 0(1) Bit NameBit Symbol Symbol Address After Reset PUR0 03F0 16 00 16 RW PU00 PU01 PU02 P00 to P03 Pull-Up PU03 PU04 PU05 PU07 PU06 P04 to P07 Pull-Up P10 to P13 Pull-Up P14 to P17 Pull-Up P20 to P23 Pull-Up P24 to P27 Pull-Up P30 to P33 Pull-Up P34 to P37 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up NOTES: 1. Set each bit in the PUR0 register to "0" when ports P0 to P5 become bus control pins in memory expansion mode and microprocessor mode. When using the ports as I/O ports, pull-up or no pull-up setting can be selected. M32C/86T cannot be used in memory expansion mode and microprocessor mode. RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Pull-Up Control Register 1(1) Bit NameBit Symbol Symbol Address After Reset PUR1 03F1 16 XXXX 0000 2 RW PU10 PU11 PU12 P40 to P43 Pull-Up PU13 (b7 - b4) P44 to P47 Pull-Up P50 to P53 Pull-Up P54 to P57 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up NOTES: 1. Set each bit in the PUR1 register to "0" when ports P0 to P5 become bus control pins in memory expansion mode and microprocessor mode. When using the ports as I/O ports, pull-up or no pull-up setting can be selected. M32C/86T cannot be used in memory expansion mode and microprocessor mode. RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Function Pull-Up Control Register 2 Bit NameBit Symbol Symbol Address After Reset PUR2 03DA 16 00 16 RW PU20 PU21 PU22 P60 to P63 Pull-Up PU23 PU24 PU25 PU27 PU26 P64 to P67 Pull-Up P72 to P73 Pull-Up(1) P74 to P77 Pull-Up P80 to P83 Pull-Up P84 to P87 Pull-Up(2) P90 to P93 Pull-Up P94 to P97 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up NOTES: 1. P7 0 and P71 cannot be pulled up. 2. P8 5 cannot be pulled up. RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0

Page 384 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.18 PUR3 Register and PUR4 Register Function Pull-Up Control Register 3 Bit NameBit Symbol Symbol Address After Reset PUR3 03DB 16 00 16 RW PU30 PU31 PU32 P100 to P103 Pull-Up PU33 PU34 PU35 PU37 PU36 P104 to P107 Pull-Up P110 to P113 Pull-Up P114 Pull-Up P120 to P123 Pull-Up P124 to P127 Pull-Up P130 to P133 Pull-Up P134 to P137 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Function Pull-Up Control Register 4(1) Bit NameBit Symbol Symbol Address After Reset PUR4 03DC 16 XXXX 0000 2 RW PU40 PU41 PU42 P140 to P143 Pull-Up PU43 (b7 - b4) P144 to P146 Pull-Up P150 to P153 Pull-Up P154 to P157 Pull-Up Pull-up setting for corresponding port 0 : Not pulled up 1 : Pulled up RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate.

Page 385 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.19 PCR Register and IPS Register Function Port Control Register(1) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Bit NameBit Symbol Symbol Address After Reset PCR 03FF 16 XXXX XXX0 2 RW PCR0 (b2 - b1) (b7 - b3) Port P1 Control Bit 0 : CMOS output 1 : N-channel open drain output(2) RW RW NOTES: 1. Set the PCR0 bit to "0" when P1 operates as a data bus in memory expansion mode and microprocessor mode. When using the ports as I/O ports, CMOS port or N-channel open drain output port can be selected. M32C/86T cannot be used in memory expansion mode and microprocessor mode. 2. This function is designed not to make port P1 a full open drain but to turn off the P channel in the CMOS port. Absolute maximum rating of the input voltage is between -0.3V and V CC + 0.3V. Reserved Bit Set to "0" b7 b6 b5 b4 b3 b2 b1 b0 Input Function Select Register Symbol Address After Reset IPS 0178 16 00 16 RWBit Name FunctionBit Symbol RW RW RW RW IPS0 IPS1 Communication Unit 0 Input Pin Select Bit 0 Assigns each function of ISCLK0 and ISRxD0 to the following ports. 0 : P7 7, P80 1 : P151, P152 Assigns each function of INPC10, INPC1 1/ISCLK1, INPC12/ISRxD1/BE1IN, INPC1 3, INPC14, INPC15, INPC16 and INPC1 7 to the following ports. 0 : P73, P74, P75, P76, P77, P81, P70, P71 1 : P110, P111, P112, P113, P140, P141, P142, P143 Communication Unit 1 Input Pin Select Bit 1 IPS2 0 : Except AN15(1) 1 : AN15 Port P15 Input Peripheral Function Select Bit IPS3 (b7 - b4) 0 : P77 1 : P83 CAN0 IN Function Pin Select Bit NOTES: 1. Although AN150 to AN157 can be used when the IPS2 bit is set to "0", power consumption may increase. b7 b6 b5 b4 b3 b2 b1 b0 RWReserved Bit Set to "0" 0000

Page 386 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Function Input Function Select Register A Bit NameBit Symbol Symbol Address After Reset IPSA 0179 16 00 16 RW RW RW IPSA_3 IPSA_0 (b2 - b1) (b7 - b4) CAN1 IN Function Pin Select Bit 0 : P95 1 : P83 0 : P80, P81 used as two-phase pulse input pin, INT1 as base timer reset 1 : P7 6, P77 used as two-phase pulse input pin, INT0 as base timer reset RW RW Reserved Bit Set to "0" Reserved Bit Set to "0" Intelligent I/O Two-Phase Pulse Input Pin and Base Timer Reset Pin Switch Bit b7 b6 b5 b4 b3 b2 b1 b0 000 00 0 Figure 24.20 IPSA Register

Page 387 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Table 24.1 Unassigned Pin Settings in Single-Chip Mode Pin Name Setting P0 to P15 Enter input mode and connect each pin to V SS via a resistor (pull-down); (excluding P85)(1,2,3) or enter output mode and leave the pins open XOUT (5) Leave pin open NMI(P85) Connect pin to V CC via a resistor (pull-up) AV CC Connect pin to VCC AV SS , VREF , BYTE Connect pins to VSS NOTES: 1. If the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset. While the port is in input mode, voltage level on the pins is indeterminate and power consumption may increase. Direction register settings may be changed by noise or failure caused by noise. Configure direction register settings regulary to increase the reliability of the program. 2. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm). 3. P7 0 and P71 must put in low-level ("L") signal outputs if they are in output mode. They are ports for the N-channel open-drain output. 4. When the external clock is applied to the XIN pin, set the pin as written above. Table 24.2 Unassigned Pin Setting in Memory Expansion Mode and Microprocessor Mode Pin Name Setting P6 to P15 Enter input mode and connect each pin to V SS via a resistor (pull-down); (excluding P85)(1,2,3) or enter output mode and leave the pins open BHE, ALE, HLDA, Leave pin open XOUT (5), BCLK RDY, HOLD, NMI(P85) Connect pins to VCC via a resistor (pull-up) AV CC Connect pin to VCC AV SS , VREF Connect pins to VSS NOTES: 1. If the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset. While the port is in input mode, voltage level on the pins is indeterminate and power consumption may increase. Direction register settings may be changed by noise or failure caused by noise. Configure direction register settings regulary to increase the reliability of the program. 2. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm). 3. P7 0 and P71 must put in low-level ("L") signal outputs if they are in output mode. They are ports for the N-channel open-drain output. 4. When the external clock is applied to the XIN pin, set the pin as written above.

Page 388 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Figure 24.21 Unassigned Pin Handling P0 to P15 (except for P85) (Input mode)··

(Input mode) (Output mode) NMI(P85) XOUT AV CC BYTE AV SS VREF Microcomputer VCC VSS In single-chip mode P6 to P15 (except for P85) (Input mode)··
(Input mode) (Output mode) XOUT AV CC AV SS VREF Open Microcomputer VCC VSS In memory expansion mode or microprocessor mode HOLD RDY ALE BCLK BHE HLDA Open Open Open
··
·· NOTES: 1. M32C/86T cannot be used in memory expansion mode and microprocessor mode. NMI(P85) VCC VCC VCC (1)

Page 389 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Table 24.3 Port P6 Peripheral Function Output Control PS0 Register PSL0 Register Bit 0 1: RTS0 Bit 1 0: P61/CLK0(input) Set to "0" 1: CLK0(output) Bit 2 0: P62/RxD0/SCL0(input) 0: SCL0(output) 1: Selected by the PSL0 register 1: STxD0 Bit 3 0: P63/SRxD0/SDA0 (input) Set to "0" 1: TxD0/SDA0 (output) Bit 4 0: P64/CTS1/SS1 0: RTS1 1: Selected by the PSL0 register 1: Do not set this value Bit 5 0: P65/CLK1(input) Set to "0" 1: CLK1(output) Bit 6 0: P66/RxD1/SCL1(input) 0: SCL1(output) 1: Selected by the PSL0 register 1: STxD1 Bit 7 0: P67/SRxD1/SDA1 (input) Set to "0" 1: TxD1/SDA1 (output) Table 24.4 Port P7 Peripheral Function Output Control PS1 Register PSL1 Register PSC Register (1) PSD1 Register Bit 0 0: P70/TA0OUT (input)/SRxD20: Selected by the PSC register0: TxD2/SDA2(output) 0: Do not set to this value INPC16/SDA2 (input) 1: Selected by the PSL1 register1: TA0OUT (output) 1: Selected by the PSD1 register1: OUTC16 Bit 1 0: P71/TB5IN/TA0IN/RxD2/ 0: Selected by the PSC register0: SCL2(output) 0: Do not set to this value INPC17/SCL2 (input) 1: Selected by the PSL1 register 1: STxD2 1: Selected by the PSD1 register1: OUTC17 Bit 2 0: P72/TA1OUT (input)/ 0: Selected by the PSC register0: CLK2(output) Set to "0" CLK2(input) 1: Selected by the PSL1 register1: TA1OUT (output) 1: V Bit 3 0: P73/TA1IN/CTS2/SS2/ 0: Selected by the PSC register 0: RTS2 Set to "0" INPC1 0 1: Selected by the PSL1 register 1: V 1: OUTC1 0/ISTxD1/BE1OUT Bit 4 0: P74/INPC11/ISCLK1(input)/0: Selected by the PSC register0: TA2OUT (output) Set to "0" TA2OUT (input) 1: Selected by the PSL1 register1: W 1: OUTC1 1/ISCLK1(output) Bit 5 0: P75/TA2IN/INPC12/ ___ 0: W Set to "0" Set to "0" ISRxD1/BE1IN 1: Selected by the PSL1 register1: OUTC12 Bit 6 0: P76/INPC13/TA3OUT (input)0: Selected by the PSC register0: Selected by the PSD1 register0: ISTxD0 1: Selected by the PSL1 register1: TA3OUT (output) 1: CAN0 OUT 1: OUTC13 Bit 7 0: P77/TA3IN/CAN0 IN/ 0: ISCLK0(output) 0: P10 4 to P107 or KI0 to KI3 Set to "0" ISCLK0(input)/INPC14 1: Selected by the PSL1 register1: OUTC14 1: AN4 to AN7 (No relation to P77) NOTES: 1. When setting the PSL1_i bit (i=0 to 4, 6) to "1", set the corresponding PSC_i bit to "0".

Page 390 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Table 24.5 Port P8 Peripheral Function Output Control PS2 Register PSL2 Register PSC2 Register Bit 0 0: P80/ISRxD0/TA4OUT (input) 0: TA4 OUT (output) Set to "0" 1: Selected by the PSL2 register 1: U Bit 1 0: P81/TA4IN/INPC15 ____ 0: U 0: Do not set to this value 1: Selected by the PSL2 register 1: Selected by the PSC2 register 1: OUTC15 Bit 2 0: P82/INT0 0: Do not set to this value 0: CAN0 OUT 1: Selected by the PSL2 register 1: Selected by the PSC2 register 1: CAN1OUT Bit 3 to 7 Set to "000002" Table 24.6 Port P9 Peripheral Function Output Control PS3 Register PSL3 Register PSC3 Register Bit 0 0: P90/TB0IN/CLK3(input) Set to "0" Set to "0" 1: CLK3(output) Bit 1 0: P91/TB1IN/RxD3/SCL3(input) 0: SCL3(output) Set to "0" 1: Selected by the PSL3 register 1: STxD3 Bit 2 0: P92/TB2IN/SRxD3/SDA3(input) 0: TxD3/SDA3(output) Set to "0" 1: Selected by the PSL3 register 1: Do not set to this value Bit 3 0: P93/TB3IN/CTS3/SS3/DA0(output) 0: Except DA0 Set to "0"________ 1: RTS3 1: DA0 Bit 4 0: P94/TB4IN/CTS4/SS4/DA1(output) 0: Except DA1 Set to "0"________ 1: RTS4 1: DA1 Bit 5 0: P95/ANEX0/CLK4(input)/CAN1IN/ 0: Except ANEX0 Set to "0" CAN1WU 1: CLK4(output) 1: ANEX0 Bit 6 0: P96/SRxD4/ANEX1/SDA4(input) 0: Except ANEX1 0: TxD4/SDA4 1: Selected by the PSC3 register 1: ANEX1 1: CAN1 OUT Bit 7 0: P97/RxD4/ADTRG /SCL4(input) 0: SCL4(output ) Set to "0" 1: Selected by the PSL3 register 1: STxD4 Table 24.7 Port P10 Peripheral Function Output Control PSC Register Bit 7 0: P104 to P107 or KI0 to KI3 1: AN4 to AN7

Page 391 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Table 24.8 Port P11 Peripheral Function Output Control PS5 Register Bit 0 0: P110/INPC10 1: OUTC10/ISTxD1/BE1OUT Bit 1 0: P11 1/INPC11/ISCLK1(input) 1: OUTC11/ISCLK1(output) Bit 2 0: P112/INPC12/ISRxD1/BE1 IN 1: OUTC12 Bit 3 0: P113/INPC13 1: OUTC13 Bit 4 to 7 Set to "00002" Table 24.9 Port P12 Peripheral Function Output Control PS6 Register PSL6 Register Bit 0 0: P120 0: Do not set this value 1: Selected by the PSL6 register 1: GASP0 Bit 1 0: P121 0: Do not set this value 1: Selected by the PSL6 register 1: GASM0 Bit 2 0: P122 0: Do not set this value 1: Selected by the PSL6 register 1: GACP0 Bit 3 0: P123 0: Do not set this value 1: Selected by the PSL6 register 1: GACM0 Bit 4 0: P124 0: Do not set this value 1: Selected by the PSL6 register 1: GASP1 Bit 5 0: P125 0: Do not set this value 1: Selected by the PSL6 register 1: GASM1 Bit 6 0: P126 0: Do not set this value 1: Selected by the PSL6 register 1: GACP1 Bit 7 0: P127 0: Do not set this value 1: Selected by the PSL6 register 1: GACM1 Table 24.10 Port P13 Peripheral Function Output Control PS7 Register PSL7 Register Bit 0 0: P130 0: Do not set this value 1: Selected by the PSL7 register 1: GASP2 Bit 1 0: P131 0: Do not set this value 1: Selected by the PSL7 register 1: GASM2 Bit 2 0: P132 0: Do not set this value 1: Selected by the PSL7 register 1: GACP2 Bit 3 0: P133 0: Do not set this value 1: Selected by the PSL7 register 1: GACM2 Bit 4 0: P134 0: Do not set this value 1: Selected by the PSL7 register 1: GASP3 Bit 5 0: P135 0: Do not set this value 1: Selected by the PSL7 register 1: GASM3 Bit 6 0: P136 0: Do not set this value 1: Selected by the PSL7 register 1: GACP3 Bit 7 0: P137 0: Do not set this value 1: Selected by the PSL7 register 1: GACM3

Page 392 974fo5002,80.peS00.1.veR 0010-4020B90JER 24. Programmable I/O Ports)T68/C23M,68/C23M(puorG68/C23M Table 24.11 Port P14 Peripheral Function Output Control PS8 Register Bit 0 0: P140/INPC14 1: OUTC14 Bit 1 0: P141/INPC15 1: OUTC15 Bit 2 0: P142/INPC16 1: OUTC16 Bit 3 0: P143/INPC17 1: OUTC17 Bit 4 to 7 Set to "00002" Table 24.12 Port P15 Peripheral Function Output Control PS9 Register Bit 0 0: P150/AN150 1: ISTxD0 Bit 1 0: P151/AN151/ISCLK0(input) 1: ISCLK0(output) Bit 2 to 7 Set to "0000002"

Page 393 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M 25. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM version. In the flash memory version, rewrite operation to the flash memory can be performed in three modes: CPU rewrite mode, standard serial I/O mode and parallel I/O mode. Table 25.1 lists specifications of the flash memory version. See Tables 1.1 and 1.2 for the items not listed in Table 25.1. Table 25.1 Flash Memory Version Specifications Item Specification Flash Memory Operating Mode 3 modes (CPU rewrite, standard serial I/O, parallel I/O) Erase Block User ROM Area See Figure 25.1 Boot ROM Area 1 block (4 Kbytes)(1) Program Method Per word (16 bytes), per byte (8 bits) (2) Erase Method All block erase, erase per block Program and Erase Control MethodSoftware commands control programming and erasing on the flash memory Protect Method The lock bit protects each block in the flash memory Number of Commands 8 commands Program and Erase Endurance 100 times (3) Data Retention 10 years ROM Code Protection Standard serial I/O mode and parallel I/O mode supported NOTES: 1. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before ship- ment. This space can be rewritten in parallel I/O mode only. 2. Programming per byte is available in parallel I/O mode only. 3. Program and erase endurance refers to the number of times a block erase can be performed. Every block erase performed after writing data of one word or more counts as one program and erase operation. Table 25.2 Flash Memory Rewrite Mode Overview yromeMhsalF edoMetirweR edoMetirweRUPCe doMO/IlaireSdradnatSe doMO/IlellaraP noitcnuFn oitucexednammocerawtfoS MORresuehtsetirwerUPCyb .aera :0edomWE rehtosaeranielbatirweR yromemhsalfnaht :1edomWE yromemhsalfnielbatirweR lairesdetacidedA resuehtsetirwerremmargorp .aeraMOR :1edomO/IlairesdradnatS O/IlairessuonorhcnyskcolC :2edomO/IlairesdradnatS TRAU :3edomO/IlairesdradnatS NAC lellarapdetacidedA ehtsetirwerremmargorp resudnaaeraMORtoob .aeraMOR elbatirweR ecapS aeraMORresUa eraMORresUa eraMORresU aeraMORtooB gnitarepO edoM edompihc-elgniS edomnoisnapxeyromeM )0edomWE( )0edomWE(edomtooB edomtooBe domO/IlellaraP remmargorPe noNr emmargorplaireSr emmargorplellaraP

Page 394 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M 00FFFF 16 Block A :4 Kbytes00F00016

4 KbytesFFF000 16

NOTES: 1. The boot ROM area can be rewritten in parallel I/O mode only. 2. When specifying a block, use an even address in the block to be specified. 3. Shown here is a flash memory block diagram in single-chip mode. 4. The block A cannot be erased by the all erase unlocked block command. Use the block erase command to erase. FF0000 Block 0 to Block 5 (32+8+8+8 +4+4) Kbytes FE0000 16 Block 6 : 64 Kbytes FEFFFF 16 FD0000 16 FDFFFF 16 FC0000 16 FCFFFF 16 FB0000 16 FBFFFF 16 FA0000 16 FAFFFF 16 FFFFFF 16 FFF000 16 FFFFFF 16 Block 0 : 4 Kbytes Block 1 : 4 Kbytes Block 2 : 8 Kbytes FFE000 16 FFEFFF 16 FFC000 16 FFDFFF 16 Block 3 : 8 Kbytes FFA000 16 FFBFFF 16 Block 4 : 8 Kbytes FF800016 FF9FFF 16 Block 5 : 32 Kbytes FF000016 FF7FFF 16 User ROM area F9000016 F9FFFF 16 F8000016 F8FFFF 16 Block 7 : 64 Kbytes Block 8 : 64 Kbytes Block 9 : 64 Kbytes Block 10 : 64 Kbytes Block 11 : 64 Kbytes Block 12 : 64 Kbytes Boot ROM area(1) (4)

25.1 Memory Map

The flash memory includes the user ROM area and the boot ROM area. The user ROM area has space to store the microcomputer operating programs in single-chip mode or memory expansion mode, and a sepa- rate 4-kbyte space as the block A. Figure 25.1 shows a block diagram of the flash memory. The user ROM area is divided into several blocks, each of which can be protected (locked) from program or erase. The user ROM area can be rewritten in CPU rewrite mode, standard serial I/O mode and parallel I/O mode. The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in parallel I/O mode. A program in the boot ROM area is executed after a hardware reset occurs while a high- level ("H") signal is applied to the CNV SS and P50 pins and a low-level ("L") signal is applied to the P55 pin. A program in the user ROM area is executed after a hardware reset occurs while an "L" signal is applied to the CNV SS pin. Consequently, the boot ROM area cannot be read. Figure 25.1 Flash Memory Block Diagram

Page 395 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M

25.1.1 Boot Mode

The microcomputer enters boot mode when a hardware reset is performed while a high-level ("H") signal is applied to the CNVSS and P50 pins and a low-level ("L") signal is applied to the P55 pin. A program in the boot ROM area is executed. In boot mode, the FMR05 bit in the FMR0 register selects access to either the boot ROM area or the user ROM area. In the factory setting, the rewrite control program for standard serial I/O mode is stored into the boot ROM area. The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase- write mode 0 (EW mode 0) is written in the boot ROM area, the flash memory can be rewritten according to the system implemented.

25.2 Functions to Prevent the Flash Memory from Rewriting

The flash memory has the ROM code protect function for parallel I/O mode and the ID code verify function for standard I/O mode to prevent the flash memory from reading or rewriting.

25.2.1 ROM Code Protect Function

The ROM code protect function prevents the flash memory from reading and rewriting in parallel I/O mode. Figure 25.2 shows the ROMCP register. The ROMCP register is located in the user ROM area. The ROM code protect function is enabled when the ROMCP1 bit is set to "00

25.2.2 ID Code Verify Function

Use the ID code verify function in standard serial I/O mode. The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match. If the ID codes do not match, commands sent from the serial programmer are not accepted. However, if the four bytes of the reset vector are "FFFFFFFF 16", ID codes are not compared, allowing all commands to be accepted. The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFFDF 16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and 0FFFFFB16. The flash memory must have a program with the ID codes set in these addresses.

Page 397 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M

25.3 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel or serial programmer. In CPU rewrite mode, only the user ROM area shown in Figure 25.1 can be rewritten. The boot ROM area cannot be rewritten. The program and block erase commands are executed only for each block in the user ROM area. Erase-write (EW) mode 0 and erase-write mode 1 are provided as CPU rewrite mode. Table 25.3 lists differences between EW mode 0 and EW mode 1. Table 25.3 EW Mode 0 and EW Mode 1 NOTES: 1. Do not generate an interrupt (except NMI interrupt) or a DMA transfer.

25.3.1 EW Mode 0

The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to "1" (CPU rewrite mode enabled) and is ready to accept commands. EW mode 0 is selected by setting the FMR11 bit in the FMR1 register to "0". To set the FMR01 bit to "1", set to "1" after first writing "0". The software commands control programming and erasing. The FMR0 register or the SRD register indi- cates whether a program or erase operation is completed as expected or not.

25.3.2 EW Mode 1

EW mode 1 is selected by setting the FMR11 bit to "1" after the FMR01 bit is set to "1". (Both bits must be set to "0" first before setting to "1".) The FMR0 register indicates whether or not a program or erase operation has been completed as ex- pected. The SRD register cannot be read in EW mode 1. metI0 edomWE1 edomWE edoMgnitarepOe dompihc-elgniS• edomnoisnapxeyromeM• edomtooB• edompihc-elgniS lortnocetirwerehterehwecapS decalpebnacmargorp aeraMORresU• aeraMORtooB• aeraMORresU lortnocetirwerehterehwecapS detucexeebnacmargorp ebtsummargorplortnocetirwerehT hsalfehtnahtrehtoecapsynaotderrefsnart detucexegnieberofeb)MAR,.g.e(yromem detucexeebnacmargorplortnocetirwerehT aeraMORresuehtni nettirwerebnachcihwecapSa eraMORresUa eraMORresU etirwerehthtiwskcolbsedulcxesiht,revewoH margorplortnoc noitcirtseRdnammoCerawtfoSe noN sdnammocesarekcolbdnamargorP• ehtgnivahkcolbanidetucexeebtonnac .margorplortnocetirwer dnammockcolbdekcolnullaesarE• tibkcolehtnehwdetucexeebtonnac lortnocetirwerehtgnivahkcolbani ro)dekcolnu("1"ottessimargorp 0RMFehtnitib20RMFehtnehw .)delbasidtibkcol("1"ottessiretsiger .desuebtonnacdnammocretsigersutatsdaeR• rognimmargorPretfaedoM gnisarE edomretsigersutatsdaeRe domyarradaeR margorPotuAgnirudetatSUPC noitarepOesarEdna gnitarepO etatsehtsniatniamstropO/I(etatsdlohanI )detucexesawdnammocehterofeb )1( noitceteDetatSyromeMhsalF 70RMFdna60RMF,00RMFehtdaeR• margorpybretsiger0RMFehtnistib retsigersutatsdaerehtetucexE• 4RSdna5RS,7RSehtdaerotdnammoc retsigerDRSehtnistib nistib70RMFdna60RMF,00RMFehtdaeR margorpybretsiger0RMFeht

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25.3.3 Flash Memory Control Register (FMR0 Register and FMR1 Register)

Figure 25.4 FMR0 Register Flash Memory Control Register 0 Symbol Address After Reset FMR0 0057 16 0000 0001 2 RW RO RW RW RW RO RW RO FMR00 FMR01 FMR02 RY/BY Status Flag FMSTP (b4) FMR05 FMR06 FMR07 CPU Rewrite Mode Select Bit(1, 7) Lock Bit Disable Select Bit (2) Flash Memory Stop Bit (3, 5) User ROM Area Select Bit(3) (Available in boot mode only) Program Status Flag(4) Erase Status Flag(4) Bit Name FunctionBit Symbol 0 : BUSY (programming or erasing)(6) 1 : READY 0 : Disables CPU rewrite mode 1 : Enables CPU rewrite mode 0 : Enables the lock bit 1 : Disables the lock bit 0 : Starts the flash memory 1 : Stops the flash memory (Enters low power consumption state and flash memory is reset) 0 : Boot ROM area is accessed 1 : User ROM area is accessed 0 : Successfully completed 1 : Terminated by error 0 : Successfully completed 1 : Terminated by error Reserved Bit Set to "0" NOTES: 1. Set the FMR01 bit while the NMI pin is held "H". Set it by program in a space other than the flash memory in EW mode 0. 2. Set the FMR02 bit to "1" in 8-bit unit immediately after setting it first to "0" while the FMR01 bit is set to "1". Do not generate an interrupt or a DMA transfer between setting the FMR02 bit to "0" and setting it to "1". 3. Set the FMSTP and FMR05 bits by program in a space other than the flash memory. 4. The FMR07 and FMR06 bits is set to "0" by executing the clear status command. 5. FMSTP bit setting is enabled when the FMR01 bit is set to "1" (CPU rewrite mode enabled). The FMSTP bit can be set to "1" when the FMR01 bit is set to "0", but the flash memory does not enter low-power consumption state nor is reset. 6. Write and read operations by the lock bit program command and read lock bit status command are included. To change a FMR01 bit setting from "0" to "1", set the FMR01 bit to "1" immediately after setting it first to "0" in 8-bit unit. Do not generate an interrupt or a DMA transfer between setting the FMR01 bit to "0" and setting it to "1". To change a FMR01 bit setting from "1" to "0", enter read array mode to write to addresses 0057 in 16-bit unit. Write "0016" into 8 high-order bits. e. g., to change a FMR01 bit setting from "1" to "0"; Assembly language: mov.w #0000h, 0057h RW b7 b6 b5 b4 b3 b2 b1 b0

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25.3.3.1 FMR00 Bit

The FMR00 bit indicates the flash memory operating state. It is set to "0" while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to "1".

25.3.3.2 FMR01 Bit

The microcomputer can accept commands when the FMR01 bit is set to "1" (CPU rewrite mode). Set the FMR05 bit to "1" (user ROM area access) as well if in boot mode.

25.3.3.3 FMR02 Bit

The lock bit is invalid by setting the FMR02 bit to "1" (lock bit disabled). (Refer to 25.3.6 Data Protect Function.) The lock bit is valid by setting the FMR02 bit to "0" (lock bit enabled). The FMR02 bit does not change the lock bit status but disables the lock bit function. If the block erase or erase all unlocked block command is executed when the FMR02 bit is set to "1", the lock bit status changes "0" (locked) to "1" (unlocked) after command execution is completed. Figure 25.5 FMR1 Register Flash Memory Control Register 1 Symbol Address After Reset FMR1 0055 16 0000 0101 2 RW RO RW RO RW RW RO FMR11 (b0) (b3 - b2) (b5 - b4) (b7) FMR16 EW Mode Select Bit(1) Lock Bit Status Flag Bit Name FunctionBit Symbol 0 : EW mode 0 1 : EW mode 1 0 : Locked 1 : Unlocked Reserved Bit Reserved Bit Set to "0" Reserved Bit Reserved Bit NOTES: 1. Set the FMR11 bit to "1" in 8-bit unit immediately after setting it first to "0" while the FMR01 bit is set to "1". Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to "0" and setting it to "1". Set it while the NMI pin is held "H". If the FMR01 bit is set to "0", the FMR01 bit and FMR11 bit are both set to "0". Set to "0" When read, its content is indeterminate When read, its content is indeterminate b7 b6 b5 b4 b3 b2 b1 b0 00 0

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25.3.3.4 FMSTP Bit

The FMSTP bit initializes the flash memory control circuits and minimizes power consumption in the flash memory. Access to the flash memory is disabled when the FMSTP bit is set to "1". Set the FMSTP bit by program in a space other than the flash memory. Set the FMSTP bit to "1" if one of the followings occurs:

A flash memory access error occurs while erasing or programming in EW mode 0 (FMR00 bit does not switch back to "1" (ready)).
Low-power consumption mode or on-chip low-power consumption mode is entered. Use the following the procedure to change the FMSTP bit setting. (1) Set the FMSTP bit to "1" (2) Set tps (the wait time to stabilize flash memory circuit) (3) Set the FMSTP bit to "0" (4) Set tps (the wait time to stabilize flash memory circuit) Figure 25.8 shows a flow chart illustrating how to start and stop the flash memory before and after entering low power mode. Follow the procedure on this flow chart. When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or wait mode, the flash memory is turned back on. The FMR0 register does not need to be set.

25.3.3.5 FMR05 Bit

The FMR05 bit selects the boot ROM or user ROM area in boot mode. Set to "0" to access (read) the boot ROM area or to "1" (user ROM access) to access (read, write or erase) the user ROM area.

25.3.3.6 FMR06 Bit

The FMR06 bit is a read-only bit indicating an auto program operation state. The FMR06 bit is set to "1" when a program error occurs; otherwise, it is set to "0". Refer to 25.3.8 Full Status Check.

25.3.3.7 FMR07 Bit

The FM07 bit is a read-only bit indicating the auto erase operation state. The FMR07 bit is set to "1" when an erase error occurs; otherwise, it is set to “0”. For details, refer to 25.3.8 Full Status Check. Figure 25.6 shows how to enter and exit EW mode 0. Figure 25.7 shows how to enter and exit EW mode 1.

25.3.3.8 FMR11 Bit

EW mode 0 is entered by setting the FMR11 bit to "0" (EW mode 0). EW mode 1 is entered by setting the FMR11 bit to "1" (EW mode 1).

25.3.3.9 FMR16 Bit

The FMR16 bit is a read-only bit indicating the execution result of the read lock bit status command. When the block, where the read lock bit status command is executed, is locked, the FMR16 bit is set to "0". When the block, where the read lock bit status command is executed, is unlocked, the FMR16 bit is set to "1".

Page 401 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Execute the read array command(3) Single-chip mode, memory expansion mode or boot mode Set MCD and PM1 registers(1) Execute the software commands Jump to the rewrite control program transferred to a space other than the flash memory. (In the following steps, use the rewrite control program in a space other than the flash memory) Transfer the rewrite control program in CPU rewrite mode to a space other than the flash memory In boot mode only Set the FMR05 bit to "0" (boot ROM area accessed) (4) Set the FMR01 bit to "0" (CPU rewrite mode disabled)(5) In boot mode only Set the FMR05 bit to "1"(user ROM area accessed) Set the FMR01 bit to "1" (CPU rewrite mode enabled) after writing "0" (2) Procedure to Enter EW Mode 0 Rewrite control program Jump to a desired address in the flash memory NOTES: 1. In CPU rewrite mode, set the MCD register to be the 10-MHz CPU clock frequency or less and set the PM12 bit in the PM1 register to "1" (internal access wait). 2. To set the FMR01 bit to "1", set it to "1" in 8-bit unit immediately after setting it first to "0". Do not generate an interrupt or a DMA transfer between setting the bit to "0" and setting it to "1". Set the FMR01 bit in a space other than flash memory. Set the FMR01 bit while the NMI pin is held "H". 3. Exit CPU rewrite mode after executing the read array command. 4. When the FMR05 bit is set to "1", the user ROM area can be accessed. 5. To change the FMR01 bit setting from "1" to "0", enter read array mode to write to addresses 0057 16 in 16-bit unit. Write "0016" into 8 high-order bits. Figure 25.6 How to Enter and Exit EW Mode 0

Page 402 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Single-chip mode(1) Set the MCD and PM1 registers(2) Set the FMR01 bit to "1" (CPU rewrite mode enabled) after writing "0" Set the FMR11 bit to "1" (EW mode 1) after writing "0" (3) Program in the ROM Procedure to Enter EW Mode 1 Execute the software commands Set the FMR01 bit to "0" (CPU rewrite mode disabled)(4) NOTES: 1. In EW mode 1, do not enter memory expansion or boot mode. 2. In CPU rewrite mode, set the MCD register to be the 10-MHz CPU clock frequency or less. Set the PM12 bit in the PM1 register to "1" (internal access wait). 3. To set the FMR01 bit to "1", set it to "1" in 8-bit unit immediately after setting it first to "0". Do not generate an interrupt or a DMA transfer between setting the FMR01 bit to "0" and setting it to "1". To set the FMR11 bit to "1", set it to "1" in 8-bit unit immediately after setting it first to "0". Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to "0" and setting it to "1". Set the FMR01 and FMR11 bits while the NMI pin is held "H". 4. To change the FMR01 bit setting from "1" to "0", enter read array mode to write to addresses 0057 16 in 16-bit unit. Write "0016" into 8 high-order bits. Figure 25.7 How to Enter and Exit EW Mode 1

Page 403 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Start main clock oscillation Transfer the low-power consumption mode program to a space other than the flash memory Switch clock source of the CPU clock. The main clock stops. (2) Wait until the flash memory stabilizes (tps ms)(3) Set the FMSTP bit to "0" (flash memory operation) Set the FMSTP bit to "1" (The flash memory stops operating. It is in a low-power consumption state)(1) Process in low-power consumption mode or on-chip oscillator low-power consumption mode Switch clock source of the CPU clock(2) Low-power consumption mode program Set the FMR01 bit to "0" (CPU rewrite mode disabled)(5) Set the FMR01 bit to "1" after setting it to "0" (CPU rewrite mode enabled)(4) Jump to a desired address in the flash memory Wait until oscillation stabilizes Jump to the low-power consumption mode program transferred to a space other than the flash memory. (In the following steps, use the low-power consumption mode program in a space other than the flash memory.) NOTES: 1. Set the FMSTP bit to "1" after the FMR01 bit is set to "1" (CPU rewrite mode enabled). 2. Wait until clock stabilizes to switch a clock source of the CPU clock to the main clock or sub clock. 3. Add tps ms wait time by program. Do not access the flash memory during this wait time. 4. To set the FMR01 bit to "1", set it to "1" in 8-bit unit immediately after setting it first to "0". Do not generate an interrupt or a DMA transfer between setting the bit to "0" and setting it to "1". Set the FMR01 bit while the NMI pin is held "H". 5. To change the FMR01 bit setting from "1" to "0", enter read array mode to write to addresses 0057 16 in 16-bit unit. Write "0016" into 8 high-order bits. Figure 25.8 Handling Before and After Low Power Consumption Mode

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25.3.4 Precautions in CPU Rewrite Mode

25.3.4.1 Operating Speed

Set the MCD4 to MCD0 bits in the MCD register to CPU clock frequency of 10 MHz or less before entering CPU rewrite mode (EW mode 0 or EW mode 1). Also, set the PM12 bit in the PM1 register to "1" (wait state).

25.3.4.2 Prohibited Instructions

The following instructions cannot be used in EW mode 0 because the CPU tries to read data in the flash memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.

25.3.4.3 Interrupts (EW Mode 0)

To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM area.
The NMI and watchdog timer interrupts are available since the FMR0 and FMR1 registers are forc- ibly reset when either interrupt occurs. Allocate the forward addresses for each interrupt routine to the fixed vector table. Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt occurs. Execute the rewrite program again after exiting the interrupt routine.
The address match interrupt is not available since the CPU tries to read data in the flash memory.

25.3.4.4 Interrupts (EW Mode 1)

Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase period.
Do not use the watchdog timer interrupt.
The NMI interrupt is available since the FMR0 and FMR1 registers are forcibly reset when either interrupt occurs. Allocate the forward address for the interrupt routine to the fixed vector table. Flash memory rewrite operation is aborted when the NMI interrupt occurs. Execute the rewrite program again after exiting the interrupt routine.

25.3.4.5 How to Access

To set the FMR01, FMR02 in the FMR0 register or FMR11 bit in the FMR1 register to "1", set to "1" in 8-bit units immediately after setting to "0". Do not generate an interrupt or a DMA transfer between the instruction to set the bit to "0" and the instruction to set the bit to "1". Set the bit while a high-level ("H") signal is applied to the NMI pin. To change the FMR01 bit from "1" to "0", enter read array mode first, and write into address 0057 16 in 16-bit units. Eight high-order bits must be set to "0016".

25.3.4.6 Rewriting in the User ROM Area (EW Mode 0)

If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash memory cannot be rewritten because the rewrite control program is not rewritten as expected. If this error occurs, rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode.

25.3.4.7 Rewriting in the User ROM Area (EW Mode 1)

Do not rewrite the block where the rewrite control program is stored.

25.3.4.8 DMA Transfer

In EW mode 1, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to "0" (busy-programming or erasing).

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25.2.4.9 Writing Command and Data

Write commands and data to even addresses in the user ROM area.

25.3.4.10 Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to "0" (CPU rewrite mode disabled) before executing the WAIT instruction.

25.3.4.11 Stop Mode

When entering stop mode, the following settings are required:

Set the FMR01 bit to "0" (CPU rewrite mode disabled). Disable a DMA transfer before setting the CM10 bit to "1" (stop mode).
Execute the instruction to set the CM10 bit to "1" (stop mode) and then the JMP.B instruction. e.g., BSET 0, CM1 ; Stop mode JMP.B L1 L1: Program after exiting stop mode

25.3.4.12 Low-Power Consumption Mode and On-Chip Oscillator Low-Power Consumption Mode

If the CM05 bit is set to "1" (main clock stopped), do not execute the following commands:

Program
Block erase
Erase all unlocked blocks
Lock bit program
Read lock bit status

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25.3.5 Software Commands

Read or write 16-bit commands and data from or to even addresses in the user ROM area, in 16-bit units. When writing a command code, 8 high-order bits (D15 to D8) are ignored. Table 25.4 Software Commands Command Program Clear Status Register Read Array Read Status Register First Bus Cycle Second Bus Cycle Lock Bit Program Erase All Unlocked Block(1) Block Erase Read Lock Bit Status Write Write Write Write Write Write Write Write Mode Read Write Write Write Write Write Mode X BA X WA BA BA Address SRD xxD016 xxD016 WD xxD016 xxD016 Data (D15 to D0) xxFF16 xx7016 xx5016 xx4016 xx7716 xxA716 xx2016 xx7116 Data (D15 to D0) X X X WA BA X X X Address NOTES: 1. Blocks 0 to 12 can be erased by the erase all unlocked block command. Block A cannot be erased. The block erase command must be used to erase the block A. SRD: Data in the SRD register (D7 to D0) WA: Address to be written (The address specified in the the first bus cycle is the same even address as the address specified in the second bus cycle.) WD: 16-bit write data BA: Highest-order block address (must be an even address) X: Any even address in the user ROM space xx: 8 high-order bits of command code (ignored)

25.3.5.1 Read Array Command

The read array command reads the flash memory. Read array mode is entered by writing command code "xxFF 16" in the first bus cycle. Content of a specified address can be read in 16-bit units after the next bus cycle. The microcomputer remains in read array mode until another command is written. Therefore, contents from multiple addresses can be read consecutively.

25.3.5.2 Read Status Register Command

The read status register command reads the SRD register (refer to 25.3.7 Status Register for detail). By writing command code "xx7016" in the first bus cycle, the SRD register can be read in the second bus cycle. Read an even address in the user ROM area. Do not execute this command in EW mode 1.

25.3.5.3 Clear Status Register Command

The clear status register command clears the SRD register. By writing "xx50 16" in the first bus cycle, the FMR07 and FMR06 bits in the FMR0 register are set to "002" and the SR5 and SR4 bits in the SRD register are set to "002".

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25.3.5.4 Program Command

The program command writes 1-word, or 2-byte, data to the flash memory. Auto program operation (data program and verify) will start by writing command code "xx40 16" in the first bus cycle and data to the write address in the second bus cycle. The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether or not an auto program operation has been completed. The FMR00 bit is set to "0" (busy) during auto program and to "1" (ready) when the auto program operation is completed. After the completion of auto program operation, the FMR06 bit in the FMR0 register indicates whether or not the auto program operation has been completed as expected. (Refer to 25.3.8 Full Status Check .) An address that is already written cannot be altered or rewritten. Figure 25.9 shows a flow chart of the program command programming. The lock bit can protect each block from being programmed inadvertently. (Refer to 25.3.6 Data Protect Function.) In EW mode 1, do not execute this command on the block where the rewrite control program is allocated. In EW mode 0, the microcomputer enters read status register mode as soon as an auto program operation starts. The SRD register can be read. The SR7 bit in the SRD register is set to "0" at the same time an auto program operation starts. It is set to "1" when an auto program operation is completed. The microcomputer remains in read status register mode until the read array command is written. After completion of an auto program operation, the SRD register indicates whether or not the auto program operation has been completed as expected. NOTES: 1. Write the command code and data to even addresses. Start Program operation is completed YES NO Write the command code "xx4016" to an address to be written Write data to an address to be written FMR00=1? Full status check Figure 25.9 Program Command

Page 408 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Write "xxD016" to the highest- order block address Start Block erase operation is completed YES NO Write the command code "xx2016" FMR00=1? Full status check NOTES: 1. Write the command code and data to even addresses.

25.3.5.5 Block Erase Command

The block erase command erases each block. Auto erase operation (erase and verify) will start in the specified block by writing command code "xx20 16" in the first bus cycle and "xxD016" to the highest-order even address of a block in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether or not an auto erase operation has been completed. The FMR00 bit is set to "0" (busy) during auto erase and to "1" (ready) when the auto erase operation is completed. After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether or not the auto erase operation has been completed as expected. (Refer to 25.3.8 Full Status Check .) Figure 25.10 shows a flow chart of the block erase command programming. The lock bit can protect each block from being programmed inadvertently. (Refer to 25.3.6 Data Protect Function.) In EW mode 1, do not execute this command on the block where the rewrite control program is allocated. In EW mode 0, the microcomputer enters read status register mode as soon as an auto erase opera- tion starts. The SRD register can be read. The SR7 bit in the SRD register is set to "0" at the same time an auto erase operation starts. It is set to "1" when an auto erase operation is completed. The microcomputer remains in read status register mode until the read array command or read lock bit status command is written. Figure 25.10 Block Erase Command

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25.3.5.6 Erase All Unlocked Block Command

The erase all unlocked block command erases all blocks except the block A. By writing command code "xxA7 16" in the first bus cycle and "xxD016" in the second bus cycle, auto erase (erase and verify) operation will run continuously in all blocks except the block A. The FMR00 bit in the FMR0 register indicates whether or not an auto erase operation has been completed. After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether or not the auto erase operation has been completed as expected. The lock bit can protect each block from being programmed inadvertently. (Refer to 25.3.6 Data Protect Function.) In EW mode 1, do not execute this command when the lock bit for any block storing the rewrite control program is set to "1" (unlocked) or when the FMR02 bit in the FMR0 register is set to "1" (lock bit disabled). In EW mode 0, the microcomputer enters read status register mode as soon as an auto erase opera- tion starts. The SRD register can be read. The SR7 bit in the SRD register is set to "0" (busy) at the same time an auto erase operation starts. It is set to "1" (ready) when an auto erase operation is completed. The microcomputer remains in read status register mode until the read array command or read lock bit status command is written. Only blocks 0 to 12 can be erased by the erase all unlocked block command. The block A cannot be erased. Use the block erase command to erase the block A.

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25.3.5.7 Lock Bit Program Command

The lock bit program command sets the lock bit for a specified block to "0" (locked). By writing command code "xx77 16" in the first bus cycle and "xxD016" to the highest-order even ad- dress of a block in the second bus cycle, the lock bit for the specified block is set to "0". The address value specified in the first bus cycle must be the same highest-order even address of a block specified in the second bus cycle. Figure 25.11 shows a flow chart of the lock bit program command programming. Execute read lock bit status command to read lock bit state (lock bit data). The FMR00 bit in the FMR0 register indicates whether a lock bit program operation is completed. Refer to 25.3.6 Data Protect Function for details on lock bit functions and how to set it to "1" (un- locked). Start Lock bit program operation is completed YES NO Write the command code "xx7716" to the highest-order block address FMR00=1? Full status check Write "xxD016" to the highest-order block address NOTES: 1. Write the command code and data to even addresses. Figure 25.11 Lock Bit Program Command

Page 411 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Block is not locked Write "xxD016" to the highest- order block address Start Block is locked YES NO Write the command code "xx7116" FMR00=1? YES NO FMR16=0? NOTES: 1. Write the command code and data to even addresses. Figure 25.12 Read Lock Bit Status Command

25.3.5.8 Read Lock Bit Status Command

The read lock bit status command reads the lock bit state (the lock bit data) of a specified block. By writing command code "xx71 16" in the first bus cycle and "xxD016" to the highest-order even ad- dress of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to "1" (ready). Figure 25.12 shows a flow chart of the read lock bit status command programming.

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25.3.6 Data Protect Function

Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to "0" (lock bit enabled). The lock bit individually protects (locks) each block against program and erase. This prevents data from being inadvertently written to or erased from the flash memory. When the lock bit status is set to "0", the block is locked (block is protected against program and erase).

When the lock bit status is set to "1", the block is not locked (block can be programmed or erased). The lock bit status is set to "0" (locked) by executing the lock bit program command and to "1" (unlocked) by erasing the block. The lock bit status cannot be set to "1" by any commands. The lock bit status can be read by the read lock bit status command. The lock bit function is disabled by setting the FMR02 bit to "1". All blocks are unlocked. However, individual lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit to "0". Lock bit status is retained. If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to "1", the target block or all blocks are erased regardless of lock bit status. The lock bit status of each block are set to "1" after an erase operation is completed. Refer to 25.3.5 Software Commands for details on each command.

25.3.7 Status Register (SRD Register)

The SRD register indicates the flash memory operating state and whether or not an erase or program operation is completed as expected. The FMR00, FMR06 and FMR07 bits in the FMR0 register indicate SRD register states. Table 25.5 shows the SRD register. In EW mode 0, the SRD register can be read when the followings occur.

Any even address in the user ROM area is read after writing the read status register command
Any even address in the user ROM area is read from when the program, block erase, erase all unlocked block, or lock bit program command is executed until when the read array command is executed.

25.3.7.1 Sequencer Status (SR7 and FMR00 Bits )

The sequencer status indicates the flash memory operating state. It is set to "0" while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to "1".

25.3.7.2 Erase Status (SR5 and FMR07 Bits)

Refer to 25.3.8 Full Status Check.

25.3.7.3 Program Status (SR4 and FMR06 Bits)

Refer to 25.3.8 Full Status Check.

Page 413 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Table 25.5 Status Register D 0 to D7: These data buses are read when the read status register command is executed. NOTES: 1. The FMR07 (SR5) and FMR06 (SR4) bits are set to "0" by executing the clear status register command. When the FMR07 (SR5) or FMR06 (SR4) bit is set to "1", the program, block erase, erase all unlocked block and lock bit program commands are not accepted. Bits in SRD register SR4 (D4) SR5 (D5) SR7 (D7) SR6 (D6) Status Name Definition SR1 (D1) SR2 (D2) SR3 (D3) SR0 (D0) Program status Erase status Sequencer status Reserved bit Reserved bit Reserved bit Reserved bit "1" READY "0" BUSY -Reserved bit Bits in FMR0 Register FMR00 FMR07 FMR06 Value after Reset Successfully completed Successfully completed Error Error (1) (1)

Page 414 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M

25.3.8 Full Status Check

If an error occurs when a program or erase operation is completed, the FMR07 and FMR06 bits in the FMR0 register are set to "1", indicating a specific error. Therefore, execution results can be confirmed by verifying these bits (full status check). Table 25.6 lists errors and FMR0 register state. Figure 25.13 shows a flow chart of the full status check and handling procedure for each error. Table 25.6 Errors and FMR0 Register State FMR0 Register (SRD Register) State Error Error Occurrence Conditions FMR07 FMR06 (SR5) (SR4) 1 1 Command • An incorrect command is written sequence error• A value other than "xxD016" or "xxFF16" is written in the second bus cycle of the lock bit program, block erase or erase all un- locked block command(1) 1 0 Erase error • The block erase command is executed on a locked block(2)

The block erase or erase all unlocked block command is ex- ecuted on an unlock block, but the erase operation is not suc- cessfully completed 0 1 Program error • The program command is executed on locked blocks(2)
The program command is executed on an unlocked block, but the program operation is not completed as expected
The lock bit program command is executed but the program op- eration is not successfully completed NOTES: 1. The flash memory enters read array mode when command code "xxFF16" is written in the second bus cycle of these commands. The command code written in the first bus cycle is ignored. 2. When the FMR02 bit is set to "1" (lock bit disabled), no error occurs even under the conditions above.

Page 415 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Full status check FMR06 =1 and FMR07=1? NO Command sequence error YES FMR07=0? YES Erase error NO (1) Execute the clear status register command and set the SR5 and SR4 bits to "0" (successfully completed) . (2) Execute the correct commands again. (1) Execute the clear status register command and set the SR5 bit to "0". (2) Execute the lock bit read status command. Set the FMR02 bit to "1" ( lock bit disabled) if the lock bit in the block where the error occurred is set to "0" (locked). (3) Execute the block erase or erase all unlocked block command again. NOTE: If similar error occurs, that block cannot be used. If the lock bit is set to "1" (unlocked) in (2) above, that block cannot be used. FMR06=0? YES Program errorNO Full status check completed (1) Execute the clear status register command and set the SR4 bit to "0"( successfully completed) . (2) Execute the read lock bit status command and set the FMR02 bit to "1" if the lock bit in the block where the error occurred is set to "0". (3) Execute the program command again. NOTE: If a similar error occurs, that block cannot be used. If the lock bit is set to "1" in (2) above, that block cannot be used. [When a program operation is executed] [When a lock bit program operation is executed] NOTE: When either FMR06 or FMR07 bit is set to "1" (terminated by error) , the program, block erase, erase all unlocked block, lock bit program and read lock bit status commands cannot be accepted. Execute the clear status register command before each command. (1) Execute the clear status register command and set the SR4 bit to "0". (2) Set the FMR02 bit in the FMR0 register to "1". (3) Execute the block erase command to erase the block where the error occurred. (4) Execute the lock bit program command again. NOTE: If similar error occurs, that block cannot be used. Figure 25.13 Full Status Check and Handling Procedure for Each Error

Page 416 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M

25.4 Standard Serial I/O Mode

In standard serial I/O mode, the serial programmer supporting the M32C/86 group (M32C/86, M32C/86T) can be used to rewrite the flash memory user ROM area, while the microcomputer is mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual included with your serial programmer for instructions. Table 25.7 lists pin descriptions (flash memory standard serial I/O mode). Figures 25.14 to 25.16 show pin connections in serial I/O mode.

25.4.1 ID Code Verify Function

The ID code verify function determines whether or not the ID codes sent from the serial programmer matches those written in the flash memory. (Refer to 25.2 Functions to Prevent Flash Memory from Rewriting.)

Page 417 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Table 25.7 Pin Description (Flash Memory Standard Serial I/O Mode) Symbol Function I/O Function VCC Power supply I Apply the guaranteed program/erase supply voltage to the VCC pin. VSS input Apply 0 V to the V SS pin CNV SS CNV SS I Connect this pin to VCC RESET Reset input I Reset input pin. Apply 20 or more clock cycles to the XIN pin while an "L" signal is applied to the RESET pin XIN Clock input I Connect a ceramic resonator or crystal oscillator between XIN and XOUT XOUT Clock output O To use the external clock, input the clock from XIN and leave XOUT open BYTE BYTE input I Connect this pin to V SS or VCC AV CC Analog power I Connect AV CC to VCC AV SS supply input Connect AV SS to VSS VREF Reference I Reference voltage input pin for the A/D converter voltage input P00 to P07 Input port P0 I Apply an "H" or "L" signal to this pin, or leave open P10 to P17 Input port P1 I Apply an "H" or "L" signal to this pin, or leave open P20 to P27 Input port P2 I Apply an "H" or "L" signal to this pin, or leave open P30 to P37 Input port P3 I Apply an "H" or "L" signal to this pin, or leave open P40 to P47 Input port P4 I Apply an "H" or "L" siganlto this pin, or leave open P50 ___ CE input I Apply "H" to this pin P55 EPM input I Apply "L" to this pin P51 to P54 Input port P5 I Apply "H" or "L" to this pin, or leave open P56, P57 P60 to P63 Input port P6 I Apply an "H" or "L" signal to this pin, or leave open P64 BUSY output O Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Program running verify monitor Standard serial I/O mode 3: Leave open P65 SCLK input I Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2, 3: Apply "L" to this pin P66 RxD I Standard serial I/O mode 1, 2: Serial data input pin Data input Standard serial I/O mode 3: Apply "H" to this pin P67 TxD O Standard serial I/O mode 1, 2: Serial data output pin Data output Standard serial I/O mode 3: Leave open P70 to P75 Input port P7 I Apply "H" or "L" to this pin, or leave open P76 CAN output O Standard serial I/O mode 1, 2: Apply an "H" or "L" signal to this pin, or leave open Standard serial I/O mode 3: CAN output pin P77 CAN input I St andard serial I/O mode 1, 2: Apply an "H" or "L" signal to this pin, or leave open Standard serial I/O mode 3: CAN input pin P80 to P84 Input port P8 I Apply an "H" or "L" signal to this pin, or leave open P86, P87 P85 ____ NMI input I Connect this pin to V CC P90 to P97 Input port P9 I Apply an "H" or "L" signal to this pin, or leave open P100 to P107 Input port P10 I Apply an "H" or "L" signal to this pin, or leave open P110 to P114 Input port P11 I Apply an "H" or "L" signal to this pin, or leave open P120 to P127 Input port P12 I Apply an "H" or "L" signal to this pin, or leave open P130 to P137 Input port P13 I Apply an "H" or "L" signal to this pin, or leave open P140 to P146 Input port P14 I Apply an "H" or "L" signal to this pin, or leave open P150 to P157 Input port P15 I Apply an "H" or "L" signal to this pin, or leave open I : Input O : Output I/O : Input and output

Page 418 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 37 7374757677798081828384858687888990919293949596979899100101102103104105106107108 78 1234 7 6 8 9 1 01 11 21 31 41 5 1 6 1 7 1 81 92 02 12 22 32 42 52 6 2 72 82 93 05 31 32 33 34 35 36 CNV SS RESET EPM CE VCC VSS TxD RxD SCLK BUSY M32C/86 Group (M32C/86, M32C/86T) Flash Memory Version 144-Pin Package Signal Value CNVss Vcc EPM Vss RESET Vss >> Vcc CE Vcc Mode settings Connect to oscillation circuit PLQP0144KA-A (144P6Q-A) VCC CAN IN CAN OUT Figure 25.14 Pin Connections in Standard Serial I/O Mode

Page 419 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M Clock input BUSY output Data output Data input BUSY SCLK TXD CNVss P50(CE) P55(EPM) NMI RESET RxD Reset input User reset signal Microcomputer NOTES: 1. Control pins and external circuitry vary with the serial programmer. Refer to the user's manual included with the serial programmer. 2. In this example, a selector controls the voltage applied to the CNVSS pin to switch between in single-chip mode and in standard serial I/O mode. 3. In standard serial I/O mode 1, if the user reset signal becomes "L" while the microcomputer is communicating with the serial programmer, break the connection between the user reset signal and the RESET pin by, for example, a jumper selector. VCC VCC VCC VCC VCC

25.4.2 Circuit Application in Standard Serial I/O Mode

Figure 25.17 shows an example of a circuit application in standard serial I/O mode 1. Figure 25.18 shows an example of a circuit application serial I/O mode 2. Figure 25.19 shows an example of a circuit applica- tion serial I/O mode 3. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer. Figure 25.15 Circuit Application in Standard Serial I/O Mode 1

Page 421 974fo5002,80.peS00.1.veR 0010-4020B90JER 25. Flash Memory Version)T68/C23M,68/C23M(puorG68/C23M

25.5 Parallel I/O Mode

In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M32C/86 Group (M32C/86, M32C/86T). Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user's manual included with your parallel pro- grammer for instructions.

25.5.1 Boot ROM Area

An erase block operation in the boot ROM area is applied to only one 4-Kbyte block. The rewrite control program in standard serial I/O mode is written in the boot ROM area before shipment. Do not rewrite the boot ROM area if using the serial programmer. In parallel I/O mode, the boot ROM area is located in addresses FFF00016 to FFFFFF16. Rewrite this address range only if rewriting the boot ROM area. (Do not access addresses other than addresses FFF000 16 to FFFFFF16.)

25.5.2 ROM Code Protect Function

The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O mode. (Refer to 25.2 Functions to Prevent Flash Memory from Rewriting.)

Page 422 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86))T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics

26.1 Electrical Characteristics (M32C/86)

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Page 423 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86))T68/C23M,68/C23M(puorG68/C23M Table 26.2 Recommended Operating Conditions (VCC =4.2 V to 5.5 V at Topr=– 20 to 85oC unless otherwise specified) lobmySr etemaraP dradnatS tinU.niM. pyT. xaM V CC egatloVylppuS 2.40 .55 .5V VA CC egatloVylppuSgolanA V CC V V SS egatloVylppuS 0V VA SS egatloVylppuSgolanA 0V V HI )"H"(hgiHtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7, 8P 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7,11P 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, V8.0 CC V CC V 7P 0 7P, 1 V8.0 CC 0.6 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(V 8.0 CC V CC 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( V5.0 CC V CC V LI )"L"(woLtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7, 8P 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7,11P 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, 0V 2.0 CC V 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(0 V 2.0 CC 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( 0V 61.0 CC I )kaep(HO tuptuOkaeP )"H"(hgiH tnerruC )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.01-A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.02- I )gva(HO tuptuOegarevA )"H"(hgiH tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.5-A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.01- I )kaep(LO woLtuptuOkaeP tnerruC)"L"( )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.01A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.02 I )gva(LO tuptuOegarevA )"L"(woL tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.5A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.01 :SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(LO 8P,7P,6P,5P,4P,3Prof 0 8Pot 4 .sselroAm08ebtsum31Pdna21P, IlatoT )kaep(HO .sselroAm04-ebtsum11Pdna,2P,1P,0Prof IlatoT )kaep(HO 8Prof 6 8P, 7 .sselroAm04-ebtsum51Pdna41P,01P,9P, IlatoT )kaep(HO .sselroAm04-ebtsum31Pdna21P,5P,4P,3Prof IlatoT )kaep(HO 8Pdna,7P,6Prof 0 8Pot 4 .sselroAm04-ebtsum ehT.3V HI Vdna LI 8Profecnerefer 7 8Pnehwseilppa 7 .troptupnielbammargorpasadesusi 8PnehwylppatonseodtI 7 Xsadesusi NIC . .desusinoitcnuflortnocrotomgnippetsehtnehwseilppaecnerefersihT.4 I )gva(LO I.sselroAm08ebtsum )kaep(LO .sselroAm021ebtsum I )gva(HO I.sselroAm08-ebtsum )kaep(HO .sselroAm021-ebtsum

Page 424 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86))T68/C23M,68/C23M(puorG68/C23M Table 26.2 Recommended Operating Conditions (Continued) (VCC =4.2 V to 5.5 V at Topr=–20 to 85oC unless otherwise specified) lobmySr etemaraP dradnatS tinU .niM. pyT. xaM (f KLCB )y cneuqerFkcolCUPCV CC V5.5ot2.4=0 2 3z HM X(f NI )y cneuqerFtupnIkcolCniaMV CC V5.5ot2.4=0 2 3z HM X(f NIC )y cneuqerFkcolCbuS 867.230 5z Hk (f gniR )( ycneuqerFrotallicsOpihc-nOV CC 52=rpoT,V0.5=) C° 5.01 2 z HM (f LLP )y cneuqerFkcolCLLPV CC V5.5ot2.4=0 12 3z HM t )LLP(US rezisehtnySycneuqerFLLPezilibatSotemiTtiaWV CC V0.5=5 s m

Page 425 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V Table 26.3 Electrical Characteristics (VCC =4.2 V to 5.5 V, VSS =0 V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified) lobmySr etemaraPn oitidnoC dradnatS tinU.niM. pyT. xaM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I HO Am5-= V CC -0.2 V CC V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I HO 002-= µA V CC -3.0 V CC V 21P 0 21P- 7 31P, 0 31P- 7 )1( I HO Am01-= V CC -0.2 V X TUO I HO Am1-=0 .3V CC V X TUOC rewoPhgiH deilppadaoloN5 .2V rewoPwoL deilppadaoloN6 .1 V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I LO 002= µA5 4.0V 21P 0 21P- 7 31P, 0 31P- 7 )1( I HO Am01-=0 .2V X TUO I LO Am1=0 .2V X TUOC rewoPhgiH deilppadaoloN0 V rewoPwoL deilppadaoloN0 V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT ,4KLC-0KLC,4STC-0STC, 0AT TUO 4AT- TUO ,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, VI V5=0 .5 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, VI V0=0 .5- µA R PULLUP ecnatsiseRpu-lluP 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 VI V0=0 30 57 61k Ω :SETON .desusinoitcnuflortnocrotomgnippetsehtnehwseilppaecnerefersihT.1

Page 426 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V Table 26.3 Electrical Characteristics (Continued) (VCC =4.2 V to 5.5 V, VSS =0 V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified) lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU.niM. pyT. xaM fR NIX ecnatsiseRkcabdeeFX NI 5.1M Ω fR NICX ecnatsiseRkcabdeeFX NIC 01M Ω V MAR egatloVybdnatSMARe dompotsnI0 .2V I CC tnerruCylppuSrewoP, edompihc-elgnisnI nepotfelerasniptuptuo erasniprehtodna Votdetcennoc SS . ,evawerauqS,zHM23=)KLCB(f noisividoN 825 4A m zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MORnogninnurmargorP 034 µA zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MARnogninnurmargorP )1( 52 µA ,edomtiawnI,zHk23=)KLCB(f 52=rpoTC ° 01 µA ,spotskcolcelihW5 2=rpoTC ° 8.05 µA ,spotskcolcelihW5 8=rpoTC ° 05 µA :SETON .)deppotsyromemhsalf("1"otretsiger0RMFehtnitibPTSMFehtgnittesnehwdeniatbosieulaV.1

Page 427 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= CC 01s tiB LNIr orrEytiraenilnoNlargetnIV FER V= CC V5= NA 0 NAot 7,0NA 0 ot 0NA 7 2NA, 0 2NAot 7, 51NA 0 51NAot 7, 1XENA,0XENA BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orrEytiraenilnoNlaitnereffiD 1±B SL -r orrEtesffO 3±B SL -r orrEniaG 3±B SL R REDDAL reddaLrotsiseRV =FER V CC 80 4k Ω t VNOC emiTnoisrevnoCtib-01 )2,1( 60.2 µs t VNOC emiTnoisrevnoCtib-8 )2,1( 57.1 µs t PMAS emiTgnilpmaS )1( 881.0 µs V FER egatloVecnerefeR 2V CC V V AI egatloVtupnIgolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM61gnideecxefi,) φ .sselrozHM61taycneuqerfDA .noitcnufdlohdnaelpmasehtgnisuhtiW.2 lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(5 .1A m :SETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwtnemerusaeM.1 00"ottessi,desu 61 .dedulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf FER .)noitcennoc Table 26.4 A/D Conversion Characteristics (VCC =AV CC =V REF =4.2 to 5.5 V, Vss= AVSS = 0 V at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified) Table 26.5 D/A Conversion Characteristics (VCC =V REF =4.2 to 5.5 V, VSS =AV SS= 0 V at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)

Page 428 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V Table 26.6 Flash Memory Version Electrical Characteristics (VCC =4.5 to 5.5 V at Topr=0 to 60oC unless otherwise specified) lobmySr etemaraP dradnatS tinU.niM. pyT. xaM - ecnarudnEesarEdnamargorP )2( 001s elcyc -V (emiTmargorPdroW CC 52=rpoT,V0.5=C ° )5 20 02 µs -e miTmargorPtiBkcoL 520 02 µs -e miTesarEkcolB V( CC 52=rpoT,V0.5=C ° ) kcolBetybK-4 3.04 s kcolBetybK-8 3.04 s kcolBetybK-23 5.04 s kcolBetybK-46 8.04 s -e miTesarEkcolB-dekcolnU-llA )1( x4 n s t SP tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs -( emiTdloHataDC °58ot04-=rpoT) 0 1s raey :SETON .1 n .desareebotkcolbforebmunehtsetoned .kcolbrepselcycesare-margorpforebmuN.2 siecnarudnEesarEdnamargorPfI n (elcyc n demmargorpdnadesareebnackcolbhcae,)001= n .selcyc tnereffidaothcae,semit840,2ataddrowagnimmargorpretfadesaresiAkcolbetybK-4afi,elpmaxeroF sserddaemasehtotdemmargorpebtonnacataD.ecnarudneesarednamargorpenosastnuocsiht,sserdda .)detibihorpetirwer(.kcolbehtgnisaretuohtiwecnonahterom

Page 429 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM 4tedVe gatloVnoitceteDegatloVwoL )1( V CC V5.5ot2.4= 8.3V 3tedVe gatloVnoitceteDecapSteseR )1( 0.3V s3tedVe gatloVdloHteseRegatloVwoL 0.2V r3tedV egatloVesaeleRteseRegatloVwoL )2( 1.3V :SETON 3tedV>4tedV.1 .deetnaraugtonsi3tedV>r3tedV.2 lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM )R-P(dt nehwegatloVylppuSlanretnIezilibatSotemiTtiaW no-rewoP V CC V5.5ot2.4=2 s m )R-S(dtt eseRnoitceteDtuo-nworBesaeleRotemiTtiaWV CC V5.5otr3tedV=6 )1( 02s m )A-E(dt tiucriCnoitceteDegatloVwoLrofemiTpu-tratS noitarepO V CC V5.5ot2.4=0 2 µs :SETON V.1 CC V5= td(P-R) VCC CPU Clock td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on td(S-R) Vdet3r VCC CPU Clock td(S-R) Wait Time to Release Brown-out Detection Reset (Hardware Reset 2) VC26, VC27 td(E-A) td(E-A) Start-up Time for Low Voltage Detection Circuit Operation Stop Operating Recommanded Operating Voltage Low Voltage Detection Circuit Table 26.7 Voltage Detection Circuit Electrical Characteristics (VCC =4.2 V to 5.5 V, Vss=0 V at Topr=25oC unless otherwise specified) Table 26.8 Power Supply Timing Figure 26.1 Power Supply Timing Diagram

Page 430 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V tac1(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (if external bus cycle is aφ + bφ, m=(bx2)+1) tac2(AD – DB) = f(BCLK) X 2 – 3510 X p9 [ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1) – 3510 X n9 [ns] (if external bus cycle is aφ + bφ, n=a+b)f(BCLK) tac1(AD – DB) = tac2(RD – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (if external bus cycle is aφ + bφ, m=(bx2)-1) lobmySr etemaraP dradnatS tinU .niM. xaM 1cat )BD-DR( )dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 1cat )BD-DA( )dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DR( )subdrxelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n ust )KLCB-BD( emiTputeStupnIataD 62s n ust )KLCB-YDR( emiTputeStupnIYDR 62s n ust )KLCB-DLOH( emiTputeStupnIDLOH 03s n ht )BD-DR( emiTdloHtupnIataD 0s n ht )YDR-KLCB( emiTdloHtupnIYDR 0s n ht )DLOH-KLCB( emiTdloHtupnIDLOH 0s n dt )ADLH-KLCB( emiTyaleDtuptuOADLH 52s n :SETON atresnI.selcycsublanretxednaycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepoehtrewolroetatstiaw KLCB .evitagensieulavdetaluclacehtfi,) lobmySr etemaraP dradnatS tinU .niM. xaM cte miTelcyCtupnIkcolClanretxE 52.13s n wt )H( htdiW)"H"(hgiHtupnIkcolClanretxE 57.31s n wt )L( htdiW)"L"(woLtupnIkcolClanretxE 57.31s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n Timing Requirements (VCC =4.2 V to 5.5 V, VSS =0 V at Topr=–20 to 85oC unless otherwise specified) Table 26.9 External Clock Input Table 26.10 Memory Expansion Mode and Microprocessor Mode

Page 431 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiW)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiW)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n Timing Requirements (VCC =4.2 V to 5.5 V, VSS =0 V at Topr=–20 to 85oC unless otherwise specified) Table 26.11 Timer A Input (Count Source Input in Event Counter Mode) Table 26.12 Timer A Input (Gate Input in Timer Mode) Table 26.13 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 26.14 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 26.15 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)

Page 432 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiW)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niMx aM ct )DA( DA GRT )reggirtrofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiW)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiW)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiW)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTputeStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HNI( htdiW)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiW)"L"(woLtupnIiTNI 052s n Timing Requirements (VCC =4.2 V to 5.5 V, VSS = 0 V at Topr = –20 to 85oC unless otherwise specified) Table 26.16 Timer B Input (Count Source Input in Event Counter Mode) Table 26.17 Timer B Input (Pulse Period Measurement Mode) Table 26.18 Timer B Input (Pulse Width Measurement Mode) Table 26.19 A/D Trigger Input Table 26.20 Serial I/O Table 26.21 External Interrupt INTi Input

Page 433 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )3( 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )3( )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )3( 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )3( )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 5-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )3( )1etoN(s n wt )RW( htdiWtuptuORW )2etoN(s n td(DB – WR) = f(BCLK) – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2

10 X n

– 15 [ns] 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles. (if external bus cycle is aφ + bφ, n=(bx2)-1)

10 X m

(if external bus cycle is aφ + bφ, m= b) NOTES: 3. tc ns is added when recovery cycle is inserted. See Figure 26.2 Switching Characteristics (VCC =4.2 V to 5.5 V, VSS = 0 V at Topr = –20 to 85oC unless otherwise specified) Table 26.22 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)

Page 434 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )5( )1etoN(s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )5( )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )5( )1etoN(s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )5( )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 5-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht (- RW) BD )dradnatsRW(emiTdloHtuptuOataD )5( )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 2-s n dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )3etoN(s n ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )4etoN(s n zdt )DA-DR( emiTtratStaolFtuptuOsserddA 8s n td(DB – WR) = 10 X m – 25 [ns] (if external bus cycle is aφ + bφ, m= (bx2)-1) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 – 20 [ns] (if external bus cycle is aφ + bφ, n= a) th(ALE – AD) = f(BCLK) X 2 – 10 [ns] (if external bus cycle is aφ + bφ, n= a) f(BCLK) X 2 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle. 3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.

Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.

NOTES: 5. tc ns is added when recovery cycle is inserted. See Figure 26.2 Switching Characteristics (VCC =4.2 V to 5.5 V, VSS = 0 V at Topr = –20 to 85oC unless otherwise specified) Table 26.23 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)

Page 435 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 26. Electrical Characteristics (M32C/86) VCC =5V P10 30pF P14 P13 P12 P15 P11 Figure 26.2 P0 to P15 Measurement Circuit

Page 436 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86))T68/C23M,68/C23M(puorG68/C23M Figure 26.3 VCC =5V Timing Diagram (1) BCLK RD 18ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min tsu(DB-BCLK) td(BCLK-RD) 26ns.min(1) CSi td(BCLK-CS) 18ns.max(1) ADi th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) 0ns.min tac1(AD-DB)(2) WR,WRL, WRH 18ns.max -5ns.min BCLK CSi td(BCLK-CS) 18ns.max ADi td(BCLK-AD) 18ns.max -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) th(WR-DB) (3) td(DB-WR) =(tcyc x m-20)ns.min (if external bus cycle is aφ+bφ, m=b) th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (if external bus cycle is aφ+bφ , n=(bx2)-1) Vcc=5V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (3) th(WR-AD) (3) tw(WR) (3) tac1(RD-DB)(2) 18ns.max(1) [ Read Timing ] (1φ +1φ Bus Cycle) [ Write timing ] (1φ +1φ Bus Cycle) NOTES: 3. Varies with operation frequency: Measurement Conditions:

VCC =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VOH =2.0V, VOL =0.8V Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1) tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b) td(DB-WR) (3) tcyc= 10 f(BCLK)

Page 437 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86))T68/C23M,68/C23M(puorG68/C23M Figure 26.4 VCC =5V Timing Diagram (2) BCLK CSi ADi RD -5ns.min BHE ADi /DBi 26ns.min td(BCLK-RD) tsu(DB-BCLK) tac2(RD-DB) tdz(RD-AD) 8ns.max ALE td(BCLK-ALE) 18ns.max td(BCLK-CS) td(AD-ALE) th(ALE-AD) th(BCLK-RD) th(RD-AD) th(RD-DB)td(BCLK-AD) th(BCLK-CS) th(RD-CS) th(BCLK-ALE) tcyc Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) -5ns.min BCLK CSi ADi BHE ADi /DBiWR,WRL, WRH th(WR-CS) ALE th(BCLK-WR) td(DB-WR) 18ns.max tac2(AD-DB) [ Read Timing ] (2φ +2φ Bus Cycle) Address (1) (1) (1) td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a) th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1) tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1) NOTES: 1. Varies with operation frequency: Data input Address (1) [ Write Timing ] (2φ +2φ Bus Cycle) Address Data output Address (2) (2) td(AD-ALE)=(tcyc/2 x n - 20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n -10)ns.min (if external bus cycle is aφ + bφ, n=a) th(WR-AD) =(tcyc/2-10)ns.min, th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (if external bus cycle is aφ + bφ, m=(b x 2)-1) NOTES: 2. Varies with operation frequency: Measurement Conditions:

V CC =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VOH =2.0V, VOL =0.8V -3ns.min (1) th(BCLK-AD) -3ns.min0ns.min (1) 18ns.max -2ns.min 18ns.max 18ns.max th(WR-DB) (2) th(BCLK-AD) -3ns.min th(WR-AD) 18ns.max td(BCLK-WR) 18ns.max td(BCLK-AD) td(AD-ALE) (2) td(BCLK-CS) 18ns.max td(BCLK-ALE) -2ns.min th(BCLK-ALE) tcyc (2) th(BCLK-CS) -3ns.min th(ALE-AD) (2) tcyc= 10 f(BCLK) Vcc=5V

Page 438 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86))T68/C23M,68/C23M(puorG68/C23M tsu(D–C) TAiIN Input TAiOUT Input In event counter mode TBiIN Input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN Input (When counting on the falling edge) TAiIN Input (When counting on the rising edge) TAiOUT Input (Counter increment/ decrement input) INTi Input AD TRG Input NMI input

2 CPU clock cycles +

("L" width) Vcc=5V Figure 26.5 VCC =5V Timing Diagram (3)

Page 439 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86))T68/C23M,68/C23M(puorG68/C23M th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Hi–Z Measurement Conditions

VCC =4.2 to 5.5V
Input high and low voltage: VIH=4.0V, VIL=1.0V
Output high and low voltage: VOH =2.5V, VOL =2.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD Input HLDA Output P0, P1, P2, P3, P4, 0 to P52 RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Vcc=5V Figure 26.6 VCC =5V Timing Diagram (4)

Page 440 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T))T68/C23M,68/C23M(puorG68/C23M

26.2 Electrical Characteristics (M32C/86T)

Table 26.24 Absolute Maximum Ratings lobmySr etemaraPn oitidnoCe ulaVt inU V CC egatloVylppuSV CC VA= CC 0.6ot3.0- V VA CC egatloVylppuSgolanAV CC VA= CC 0.6ot3.0- V VI egatloVtupnI0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7, V FER X, NI VNC,TESER, SS ETYB, Vot3.0- CC 3.0+V 7P 0 7P, 1 0.6ot3.0-V VO egatloVtuptuO0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7, X TUO Vot3.0- CC 3.0+V 7P 0 7P, 1 0.6ot3.0- dPn oitapissiDrewoP C°52=rpoT0 05W m rpoT gnitarepO tneibmA erutarepmeT noitarepoUPCgnirudn oisrevT5 8ot04- C°esarednamargorpyromemhsalfgnirud noitarepo 06ot0 gtsTe rutarepmeTegarotS 051ot56-C °

Page 441 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T))T68/C23M,68/C23M(puorG68/C23M Table 26.25 Recommended Operating Conditions (VCC =4.2 to 5.5 V, VSS =0 V at Topr = -40 to 85oC (T version) unless otherwise specified) lobmySr etemaraP dradnatS tinU.niM. pyT. xaM V CC egatloVylppuS 2.40 .55 .5V VA CC egatloVylppuSgolanA V CC V V SS egatloVylppuS 0V VA SS egatloVylppuSgolanA 0V V HI )"H"(hgiHtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7, 8P 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7,11P 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, V8.0 CC V CC V 7P 0 7P, 1 V8.0 CC 0.6 V LI )"L"(woLtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7, 8P 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7,11P 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, 0V 2.0 CC V I )kaep(HO tuptuOkaeP )"H"(hgiH tnerruC )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.01-A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.02- I )gva(HO tuptuOegarevA )"H"(hgiH tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.5-A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.01- I )kaep(LO woLtuptuOkaeP tnerruC)"L"( )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.01A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.02 I )gva(LO tuptuOegarevA )"L"(woL tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6, 51P 0 51P- 7 0.5A m 21P 0 21P- 7 31P, 0 31P- 7 )4( 0.01 :SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(LO 8P,7P,6P,5P,4P,3Prof 0 8Pot 4 .sselroAm08ebtsum31Pdna21P, IlatoT )kaep(HO .sselroAm04-ebtsum11Pdna,2P,1P,0Prof IlatoT )kaep(HO 8Prof 6 8P, 7 .sselroAm04-ebtsum51Pdna41P,01P,9P, IlatoT )kaep(HO .sselroAm04-ebtsum31Pdna21P,5P,4P,3Prof IlatoT )kaep(HO 8Pdna,7P,6Prof 0 8Pot 4 .sselroAm04-ebtsum ehT.3V HI Vdna LI 8Profecnerefer 7 8Pnehwseilppa 7 .troptupnielbammargorpasadesusi 8PnehwylppatonseodtI 7 Xsadesusi NIC . .desusinoitcnuflortnocrotomgnippetsehtnehwseilppaecnerefersihT.4 I )gva(LO I.sselroAm08ebtsum )kaep(LO .sselroAm021ebtsum I )gva(HO I.sselroAm08-ebtsum )kaep(HO .sselroAm021-ebtsum

Page 442 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T))T68/C23M,68/C23M(puorG68/C23M Table 26.26 Recommended Operating Conditions (Continued) (VCC =4.2 to 5.5 V, VSS =0 V at Topr = -40 to 85oC (T version) unless otherwise specified) lobmySr etemaraP dradnatS tinU .niM. pyT. xaM (f KLCB )y cneuqerFkcolCUPCV CC V5.5ot2.4=0 2 3z HM X(f NI )y cneuqerFtupnIkcolCniaMV CC V5.5ot2.4=0 2 3z HM X(f NIC )y cneuqerFkcolCbuS 867.230 5z Hk (f gniR )( ycneuqerFrotallicsOpihc-nOV CC 52=rpoT,V0.5=) C° 5.01 2 z HM (f LLP )y cneuqerFkcolCLLPV CC V5.5ot2.4=0 12 3z HM t )LLP(US rezisehtnySycneuqerFLLPezilibatSotemiTtiaWV CC V0.5=5 s m

Page 443 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M lobmySr etemaraPn oitidnoC dradnatS tinU.niM. pyT. xaM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I HO Am5-= V CC -0.2 V CC V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I HO 002-= µA V CC -3.0 V CC V 21P 0 21P- 7 31P, 0 31P- 7 )1( I HO Am01-= V CC -0.2 V X TUO I HO Am1-=0 .3V X TUOC rewoPhgiH deilppadaoloN5 .2V rewoPwoL deilppadaoloN6 .1 V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 I LO 002= µA5 4.0V 21P 0 21P- 7 31P, 0 31P- 7 )1( I HO Am01-=0 .2V X TUO I LO Am1=0 .2V X TUOC rewoPhgiH deilppadaoloN0 V rewoPwoL deilppadaoloN0 V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT ,4KLC-0KLC,4STC-0STC, 0AT TUO 4AT- TUO ,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, VI V5=0 .5 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 X, NI ,TESER, VNC SS ETYB, VI V0=0 .5- µA R PULLUP ecnatsiseRpu-lluP 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 VI V0=0 30 57 61k Ω :SETON .desusinoitcnuflortnocrotomgnippetsehtnehwseilppaecnerefersihT.1 Table 26.27 Electrical Characteristics (VCC =4.2 to 5.5 V, VSS =0 V at Topr = -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified)

Page 444 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU.niM. pyT. xaM fR NIX ecnatsiseRkcabdeeFX NI 5.1M Ω fR NICX ecnatsiseRkcabdeeFX NIC 01M Ω V MAR egatloVybdnatSMARe dompotsnI0 .2V I CC tnerruCylppuSrewoP, edompihc-elgnisnI nepotfelerasniptuptuo erasniprehtodna Votdetcennoc SS . ,evawerauqS,zHM23=)KLCB(f noisividoN 820 5A m zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MORnogninnurmargorP 034 µA zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MARnogninnurmargorP )1( 52 µA ,edomtiawnI,zHk23=)KLCB(f 52=rpoTC ° 01 µA ,spotskcolcelihW5 2=rpoTC ° 8.05 µA ,spotskcolcelihW5 8=rpoTC ° 05 µA :SETON .)deppotsyromemhsalf("1"otretsiger0RMFehtnitibPTSMFehtgnittesnehwdeniatbosieulaV.1 Table 26.28 Electrical Characteristics (Continued) (VCC =4.2 to 5.5 V, VSS =0 V at Topr = -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified)

Page 445 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(5 .1A m :SETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwtnemerusaeM.1 00"ottessi,desu 61 .dedulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf FER .)noitcennoc lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= CC 01s tiB LNIr orrEytiraenilnoNlargetnIV FER V= CC V5= NA 0 NAot 7,0NA 0 ot 0NA 7 2NA, 0 2NAot 7, 51NA 0 51NAot 7, 1XENA,0XENA BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orrEytiraenilnoNlaitnereffiD 1±B SL -r orrEtesffO 3±B SL -r orrEniaG 3±B SL R REDDAL reddaLrotsiseRV =FER V CC 80 4k Ω t VNOC emiTnoisrevnoCtib-01 )2,1( 60.2 µs t VNOC emiTnoisrevnoCtib-8 )2,1( 57.1 µs t PMAS emiTgnilpmaS )1( 881.0 µs V FER egatloVecnerefeR 2V CC V V AI egatloVtupnIgolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM61gnideecxefi,) φ .sselrozHM61taycneuqerfDA .noitcnufdlohdnaelpmasehtgnisuhtiW.2 Table 26.29 A/D Conversion Characteristics (VCC =4.2 to 5.5 V, VSS =0 V at Topr= -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified) Table 26.30 D/A Conversion Characteristics (VCC =4.2 to 5.5 V, VSS =0 V at Topr= -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified)

Page 446 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M td(P-R) VCC CPU Clock td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on Recommanded Operating Voltage lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM )R-P(dt nehwegatloVylppuSlanretnIezilibatSotemiTtiaW no-rewoP V CC V5.5ot2.4=2 s m Table 26.31 Flash Memory Version Electrical Characteristics (VCC =4.5 to 5.5 V at Topr= 0 to 60oC unless otherwise specified) Figure 26.8 Power Supply Timing Diagram lobmySr etemaraP dradnatS tinU.niM. pyT. xaM - ecnarudnEesarEdnamargorP )2( 001s elcyc -V (emiTmargorPdroW CC 52=rpoT,V0.5=C ° )5 20 02 µs -e miTmargorPtiBkcoL 520 02 µs -e miTesarEkcolB V( CC 52=rpoT,V0.5=C ° ) kcolBetybK-4 3.04 s kcolBetybK-8 3.04 s kcolBetybK-23 5.04 s kcolBetybK-46 8.04 s -e miTesarEkcolB-dekcolnU-llA )1( x4 n s t SP tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs -( emiTdloHataDC °58ot04-=rpoT) 0 1s raey :SETON .1 n .desareebotkcolbforebmunehtsetoned .kcolbrepselcycesare-margorpforebmuN.2 siecnarudnEesarEdnamargorPfI n (elcyc n demmargorpdnadesareebnackcolbhcae,)001= n .selcyc tnereffidaothcae,semit840,2ataddrowagnimmargorpretfadesaresiAkcolbetybK-4afi,elpmaxeroF sserddaemasehtotdemmargorpebtonnacataD.ecnarudneesarednamargorpenosastnuocsiht,sserdda .)detibihorpetirwer(.kcolbehtgnisaretuohtiwecnonahterom Table 26.32 Power Supply Timing

Page 447 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M lobmySr etemaraP dradnatS tinU .niM. xaM cte miTelcyCtupnIkcolClanretxE 52.13s n wt )H( htdiW)"H"(hgiHtupnIkcolClanretxE 57.31s n wt )L( htdiW)"L"(woLtupnIkcolClanretxE 57.31s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n Timing Requirements (VCC =4.2 to 5.5 V, VSS =0 V at Topr= -40 to 85oC (T version) unless otherwise specified) Table 26.33 External Clock Input

Page 448 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiW)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiW)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n Timing Requirements (VCC =4.2 to 5.5 V, VSS =0 V at Topr= -40 to 85oC (T version) unless otherwise specified) Table 26.34 Timer A Input (Count Source Input in Event Counter Mode) Table 26.35 Timer A Input (Gate Input in Timer Mode) Table 26.36 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 26.37 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 26.38 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)

Page 449 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M Timing Requirements (VCC =4.2 to 5.5 V, VSS =0 V at Topr= -40 to 85oC (T version) unless otherwise specified) Table 26.39 Timer B Input (Count Source Input in Event Counter Mode) Table 26.40 Timer B Input (Pulse Period Measurement Mode) Table 26.41 Timer B Input (Pulse Width Measurement Mode) Table 26.42 A/D Trigger Input Table 26.43 Serial I/O Table 26.44 External Interrupt INTi Input lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiW)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niMx aM ct )DA( DA GRT )reggirtrofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiWesluP)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiW)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiW)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTputeStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HNI( htdiW)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiW)"L"(woLtupnIiTNI 052s n

Page 450 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T) VCC =5V )T68/C23M,68/C23M(puorG68/C23M P10 30pF P14 P13 P12 P15 P11 Figure 26.9 P0 to P15 Measurement Circuit

Page 451 974fo5002,80.peS00.1.veR 0010-4020B90JER 26. Electrical Characteristics (M32C/86T))T68/C23M,68/C23M(puorG68/C23M tsu(D–C) TAiIN Input TAiOUT Input In event counter mode TBiIN Input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN Input (When counting on the falling edge) TAiIN Input (When counting on the rising edge) TAiOUT Input (Counter increment/ decrement input) INTi Input AD TRG Input Vcc=5V NMI input ("L" width) Figure 26.10 VCC =5V Timing Diagram

Page 452 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 27. Precautions

27.1 Restrictions to Use M32C/86T (High-Reliability Version)

The M32C/86T microcomputer (high-reliability version) has the following usage restrictions:

M32C/86T must be used in single-chip mode only. M32C/86T cannot be used in memory expansion mode and microprocessor mode.
Bus control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE, HLDA/ALE, HOLD, ALE, RDY) and BCLK pins in M32C/86T cannot be used.
The voltage detection circuit in M32C/86T cannot be used. Low voltage detection interrupt and brown- out detection reset cannot also be used.
The DS register, VCR1 register, VCR2 register, D4INT register and EWCR0 to EWCR3 registers in M32C/86T cannot be used. 27. Precautions (Restrictions to Use M32C/86T)

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27.2 Reset

Voltage applied to the VCC pin must meet the SVCC standard. Table 27.1 Power Supply Increasing Slope SV CC V SV CC Power Supply Increasing Slope (VCC ) lobmySr etemaraP dradnatS tinU .niM. pyT. xaM VS CC V(epolSgnisaercnIylppuSrewoP CC )5 0.0s m/V Figure 27.1 SVCC Timing 27. Precautions (Reset)

Page 454 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 27. Precautions (Bus)

27.3 Bus

27.3.1 HOLD Signal

When entering microprocessor mode or memory expansion mode from single-chip mode and using HOLD input, set the PM01 and PM00 bits to "112" (microprocessor mode) or to "012" (memory expansion mode) after setting the PD4_7 to PD4_0 bits in the PD4 register and the PD5_2 to PD5_0 bits in the PD5 register to "0" (input mode). P40 to P47 (A16 to A22, A23, CS0 to CS3, MA8 to MA12) and P50 to P52 (RD/WR/BHE, RD/WRL/WRH) are not placed in high-impedance states even when a low-level ("L") signal is applied to the HOLD pin, if the PM01 and PM00 bits are set to "11 2" (microprocessor mode) or to "012" (memory expansion mode) after setting the PD4_7 to PD4_0 bits in the PD4 register and the PD5_2 to PD5_0 bits in the PD5 register to "1" (output mode) in single-chip mode.

27.3.2 External Bus

The internal ROM cannot be read when a high-level ("H") signal is applied to the CNVSS pin and the hardware reset (hardware reset 1 or brown-out detection reset) occurs.

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27.4 SFR

27.4.1 Register Settings

Table 27.2 lists registers containing bits which can only be written to. Set these registers with immediate values. When establishing the next value by altering the present value, write the present value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 27.2 Registers with Write-only Bits 27. Precautions (SFR) retsigeRs serddAr etsigeRs serddA retsigeRSTDWE 000 61 retsigeRGRB3U9 230 61 retsigeRIR0GC E00 61 retsigeRBT3UB 230 61 A230, 61 retsigeRIR1GC 210 61 retsigeRGRB2U9 330 61 retsigeRGRB1U9 E20 61 retsigeRBT2UB 330 61 A330, 61 retsigeRBT1UB E20 61 AE20, 61 retsigeRFDU4 430 61 retsigeRGRB4U9 F20 61 retsigeR0AT )1( 7430 61 6430, 61 retsigeRBT4UB F20 61 AF20, 61 retsigeR1AT )1( 9430 61 8430, 61 retsigeR11AT3 030 61 2030, 61 retsigeR2AT )1( B430 61 A430, 61 retsigeR12AT5 030 61 4030, 61 retsigeR3AT )1( D430 61 C430, 61 retsigeR14AT7 030 61 6030, 61 retsigeR4AT )1( F430 61 E430, 61 retsigeRTTDC 030 61 retsigeRGRB0U9 630 61 retsigeR2BTCID 030 61 retsigeRBT0UB 630 61 A63, 61 NOTES : 1. In one-shot timer mode and pulse width modulation mode only.

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27.5 Clock Generation Circuit

27.5.1 CPU Clock

When the CPU operating frequency is 24 MHz or more, use the following procedure for better EMC (Electromagnetic Compatibility) performance. 1) Oscillator connected between the XIN and XOUT pins, or external clock applied to the XIN pin, has less than 24 MHz frequency. 2) Use the PLL frequency synthesizer to multiply the main clock.
In M32C/86T, the main clock frequency must be 24 MHz or less.

27.5.2 Sub Clock

Set the CM03 bit to "0" (XCIN-XCOUT drive capacity "LOW") when selecting the sub clock (XCIN-XCOUT ) as the CPU clock, or Timer A or Timer B count source (fC32 ).

27.5.2.1 Sub Clock Oscillation

When oscillating the sub clock, set the CM04 bit in the CM0 register to "1" (XCIN-XCOUT oscillation function) after setting the CM07 bit in the CM0 register to "0" (clock other than sub clock) and the CM03 bit to "1" (X CIN-XCOUT drive capacity "HIGH"). Set the CM03 bit to "0" after sub clock oscillation stabilizes. Set the sub clock as the CPU clock, or Timer A or Timer B count source (f C32 ) after the above settings are completed.

27.5.2.2 Using Stop Mode

When the microcomputer enters stop mode, the CM03 bit is automatically set to "1" (XCIN-XCOUT drive capacity "HIGH"). Use the following procedure to select the main clock as the CPU clock when enter- ing stop mode. 1) Set the CM17 bit in the CM1 register to "0" (main clock). 2) Set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit). 3) Set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by the MCD register setting). After exiting stop mode, wait for the sub clock oscillation to stabilize. Then set the CM03 bit to "0" and the CM07 bit to "1" (sub clock).

27.5.2.3 Oscillation Parameter Matching

If the sub slock oscillation parameters have only been evaluated with the drive capacity "HIGH", the parameters should be reevaluated for drive capacity "LOW". Contact your oscillator manufacturer for details on matching parameters. 27. Precautions (Clock Generation Circuit)

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27.5.3 PLL Frequency Synthesizer

Stabilize supply voltage to meet the power supply standard when using the PLL frequency synthesizer. Table 27.3 Power Supply Ripple 27. Precautions (Clock Generation Circuit) Figure 27.2 Power Supply Fluctuation Timing

27.5.4 External Clock

Do not stop an external clock running if the main clock is selected as the CPU clock while the external clock is applied to the XIN pin. Do not set the CM05 bit in the CM0 register to "1" (main clock stopped) while the external clock input is used for the CPU clock.

27.5.5 Clock Divide Ratio

Set the PM12 bit in the PM1 register to "0" (no wait state) when changing the MCD4 to MCD0 bit settings in the MCD register.

27.5.6 Power Consumption Control

Stabilize the main clock, sub clock or PLL clock to switch the CPU clock source to each clock.

27.5.6.1 Wait Mode

When entering wait mode while the CM02 bit in the CM0 register is set to "1" (peripheral function stop in wait mode), set the MCD4 to MCD0 bits in the MCD register to maintain the 10-MHz CPU clock frequency or less. When entering wait mode, the instruction queue reads ahead to instructions following the WAIT in- struction, and the program stops. Write at least 4 NOP instructions after the WAIT instruction. Vp-p(ripple) f(ripple) VCC f(ripple) Power Supply Ripple Tolerable Frequency (VCC ) Vp-p(ripple) Power Supply Ripple Amplitude Voltage lobmySr etemaraP dradnatS tinU .niM. pyT. xaM f )elppir( V(ycneuqerFelbareloTelppiRylppuSrewoP CC )V 1CC V5=0 1z Hk V )elppir(P-P egnaRnoitautculFegatloVelppiRylppuSrewoPV 1CC V5=5 .0V V )|T/V|(CC etaRnoitautculFegatloVelppiRylppuSrewoPV 1CC V5=1 s m/V

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27.5.6.2 Stop Mode

Use the following procedure to select the main clock as the CPU clock when entering stop mode. 1) Set the CM17 bit in the CM1 register to "0" (main clock). 2) Set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit). 3) Set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by the MCD register setting). If the PLL clock is selected as the CPU clock source, set the CM17 bit to "0" (main clock) and the PLC07 bit in the PLC0 register to "0" (PLL off) before entering stop mode.
The microcomputer cannot enter stop mode if a low-level signal ("L") is applied to the NMI pin. Apply a high-level ("H") signal instead.
If stop mode is exited by any reset, apply an "L" signal to the RESET pin until a main clock oscilla- tion is stabilized enough.
If using the NMI interrupt to exit stop mode, use the following procedure to set the CM10 bit in the CM1 register (all clocks stopped). 1) Exit stop mode with using the NMI interrupt. 2) Generate a dummy interrupt. 3) Set the CM10 bit to "1". e.g., int #63 ; dummy interrupt bset cm1 ; all clocks stopped /* dummy interrupt handling */ dummy reit
When entering stop mode, the instruction queue reads ahead to instructions following the instruc- tion setting the CM10 bit in the CM1 register to "1" (all clocks stopped), and the program stops. When the microcomputer exits stop mode, the instruction lined in the instruction queue is executed before the interrupt routine for recovery is done. Write the JMP.B instruction, as follows, after the instruction setting the CM10 bit in the CM1 register to "1" (all clocks stopped). e.g., bset 0, prcr ; protection removed bset 0, cm1 ; all clocks stopped jmp.b LABEL_001 ; JMP.B instruction executed (no instuction between JMP.B ; and LABEL.) LABEL_001: nop ; NOP (1) nop ; NOP (2) nop ; NOP (3) nop ; NOP (4) mov.b #0, prcr ; Protection set 27. Precautions (Clock Generation Circuit)

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27.5.6.3 Suggestions for Reducing Power Consumption

The followings are suggestions for reducing power consumption when programming or designing systems. Ports: I/O ports maintains the same state despite the microcomputer entering wait mode or stop mode. Current flows through active output ports. Feedthrough current flows through input ports in a high-impedance state. Set unassigned ports as input ports and stabilize electrical potential before entering wait mode or stop mode. A/D Converter: If the A/D conversion is not performed, set the VCUT bit in the AD0CON1 register to "0" (no V REF connection). Set the VCUT bit to "1" (VREF connection) and wait at least 1µs before starting the A/D conversion. D/A Converter: Set the DAi bit (i=0, 1) in the DACON register to "0" (output disabled) and set the DAi register to "0016" when the D/A conversion is not performed. Peripheral Function Stop: Set the CM02 bit in the CM0 register while in wait mode to stop unnec- essary peripheral functions. However, this does not reduce power consumption because the pe- ripheral function clock (fc32) generating from the sub clock does not stop. When in low-speed mode and low-power consumption mode, do not enter wait mode when the CM02 bit is set to "1" (periph- eral clock stops in wait mode). 27. Precautions (Clock Generation Circuit)

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27.6 Protection

The PRC2 bit setting in the PRCR register is changed to "0" (write disable) when an instruction is written to any address after the PRC2 bit is set to "1" (write enable). Write instruction immediately after setting the PRC2 bit to "1" to change registers protected by the PRC2 bit. Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the following instruction. 27. Precautions (Protection)

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27.7 Interrupts

27.7.1 ISP Setting

After reset, the ISP is set to "00000016". The program runs out of control if an interrupt is acknowledged before the ISP is set. Therefore, the ISP must be set before an interrupt request is generated. Set the ISP to an even address, which allows interrupt sequences to be executed at a higher speed. To use NMI interrupt, set the ISP at the beginning of the program. The NMI interrupt can be acknowl- edged after the first instruction has been executed after reset.

27.7.2 NMI Interrupt

NMI interrupt cannot be denied. Connect the NMI pin to VCC via a resistor (pull-up) when not in use.
The P8_5 bit in the P8 register indicates the NMI pin value. Read the P8_5 bit only to determine the pin level after a NMI interrupt occurs.
"H" and "L" signals applied to the NMI pin must be over 2 CPU clock cycles + 300 ns wide.
NMI interrupt request may not be acknowledged if this and other interrupt requests are generated simultaneously.

27.7.3 INT Interrupt

Edge Sensitive "H" and "L" signals applied to the INT0 to INT5 pins must be at least 250 ns wide, regardless of the CPU clock.
Level Sensitive "H" and "L" signals applied to the INT0 to INT5 pins must be at least 1 CPU clock cycle + 200 ns wide. For example, "H" and "L" must be at least 234ns wide if XIN=30MHz with no division.
The IR bit setting may change to "1" (interrupt requested) when switching the polarity of the INT0 to INT5 pins. Set the IR bit to "0" (no interrupt requested) after selecting the polarity. Figure 27.3 shows an example of the switching procedure for the INT interrupt. 27. Precautions (Interrupts) Set the POL bit in the INTiIC register Set the IR bit in the INTiIC register to "0" Set the ILVL2 to ILVL0 bits to "0012" (level 1) to "1112" (level 7) (INT interrupt request acknowledgement enabled) Set the ILVL2 to ILVL0 bits in the INTiIC register (i = 0 to 5) to "000 2" (level 0) (INT interrupt disabled) Figure 27.3 Switching Procedure for INT Interrupt

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27.7.4 Watchdog Timer Interrupt

Reset the watchdog timer after a watchdog timer interrupt occurs.

27.7.5 Changing Interrupt Control Register

To change the interrupt control register while the interrupt request is denied, follow the instructions below. Changing IR bit The IR bit setting may not change to "0" (no interrupt requested) depending on the instructions written. If this is a problem, use the following instruction to change the register: MOV Changing Bits Except IR Bit When an interrupt request is generated while executing an instruction, the IR bit may not be set to "1" (interrupt requested) and the interrupt may be ignored. If this is a problem, use the following instructions to change the register: AND, OR, BCLR, BSET

27.7.6 Changing IIOiIR Register (i = 0 to 5, 8 to 11)

Use the following instructions to set bits 1 to 7 in the IIOilR register to "0" (no interrupt requested): AND, BCLR

27.7.7 Changing RLVL Register

The DMAII bit is indeterminate after reset. When using the DMAII bit to generate an interrupt, set the interrupt control register after setting the DMAII bit to "0" (interrupt priority level 7 available for interrupts). 27. Precautions (Interrupts)

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27.8 DMAC

Set DMAC-associated registers while the MDi1 and MDi0 bits (i=0 to 3) in the channel to be used are set to "002" (DMA disabled). Set the MDi1 and MDi0 bits to "012" (single transfer) or "112" (repeat transfer) at the end of setup procedure to start DMA requests.
Do not set the DRQ bit in the DMiSL register to "0" (no request). If a DMA request is generated but the receiving channel is not ready to receive(1), the DMA transfer does not occur and the DRQ bit is set to "0". NOTES: 1. The MDi1 and MDi0 bits are set to "002" or the DCTi register is set to "000016" (transferred 0 times).
To start a DMA transfer by a software trigger, set the DSR bit and DRQ bit in the DMiSL register to "1" simultaneously. e.g., OR.B #0A0h,DMiSL ; Set the DSR and DRQ bits to "1" simultaneously
Do not generate a channel i DMA request when setting the MDi1 and MDi0 bits in the DMDj register (j=0,1) corresponding to channel i to "012" (single transfer) or "112" (repeat transfer), if the DCTi register of channel i is set to "1".
Select the peripheral function which causes the DMA request after setting the DMA-associated regis- ters. If none of the conditions above (setting INT interrupt as DMA request source) apply, do not write "1" to the DCTi register.
Enable DMA(2) after setting the DMiSL register (i=0 to 3) and waiting six BCLK cycles or more by program. NOTES: 2. DMA is enabled when the values set in the MDi1 and MDi0 bits in the DMDj register are changed from "002" (DMA disabled) to "012" (single transfer) or "112" (repeat transfer). 27. Precautions (DMAC)

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27.9 Timer

27.9.1 Timers A and B

Timers stop after reset. Set the TAiS(i=0 to 4) bit or TBjS(j=0 to 5) bit in the TABSR register or TBSR register to "1" (starts counting) after setting operating mode, count source and counter. The following registers and bits must be set while the TAiS bit or TBjS bit is set to "0" (stops counting).

TAiMR, TBjMR register
TAi, TBj register
UDF register
TAZIE, TA0TGL, TA0TGH bits in the ONSF register
TRGSR register

27.9.2 Timer A

The TA1OUT , TA2OUT and TA4OUT pins are placed in high-impedance states when a low-level ("L") signal is applied to the NMI pin while the INV03 and INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three-phase output by an "L" signal applied to the NMI pin).

27.9.2.1 Timer A (Timer Mode)

The TAiS bit (i=0 to 4) in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit to "1" (starts counting) after selecting an operating mode and setting the TAi register.
The TAi register indicates the counter value during counting at any given time. However, the counter is "FFFF16" when reloading. The setting value can be read after setting the TAi register while the counter stops and before the counter starts counting.

27.9.2.2 Timer A (Event Counter Mode)

The TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit to "1" (starts counting) after selecting an operating mode and setting the TAi register.
The TAi register indicates the counter values during counting at any given time. However, the counter will be "FFFF16" during underflow and "000016" during overflow, when reloading. The set- ting value can be read after setting the TAi register while the counter stops and before the counter starts counting. 27. Precautions (Timer)

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27.9.2.3 Timer A (One-shot Timer Mode)

The TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit to "1" (starts counting) after selecting an operating mode and setting the TAi register.
The followings occur when the TABSR register is set to "0" (stops counting) while counting: - The counter stops counting and the microcomputer reloads contents of the reload register. - The TAi OUT pin becomes low ("L"). - The IR bit in the TAiIC register is set to "1" (interrupt requested) after one CPU clock cycle.
The output of the one-shot timer is synchronized with an internal count source. When set to an external trigger, there is a delay of one count source cycle maximum, from trigger input to the TAiIN pin to the one-shot timer output.
The IR bit is set to "1" when the following procedures are performed to set timer mode: - selecting one-shot timer mode after reset. - switching from timer mode to one-shot timer mode. - switching from event counter mode to one-shot timer mode. Therefore, set the IR bit to "0" to generate a timer Ai interrupt (IR bit) after performing these proce- dures.
When a trigger is generated while counting, the reload register reloads and continues counting after the counter has decremented once following a re-trigger. To generate a trigger while counting, wait at least 1 count source cycle after the previous trigger has been generated and generate a re- trigger.
If an external trigger input is selected to start counting in timer A one-shot timer mode, do not provide another external trigger input again for 300 ns before the timer A counter value reaches "0000 16". One-shot timer may stop counting.

27.9.2.4 Timer A (Pulse Width Modulation Mode)

The TAiS(i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit to "1" (starts counting) after selecting an operating mode and setting the TAi register.
The IR bit is set to "1" when the following procedures are performed to set timer mode: - Selecting PWM mode after reset - Switching from timer mode to PWM mode - Switching from event counter mode to PWM mode Therefore, set the IR bit to "0" by program to generate a timer Ai interrupt (IR bit) after performing these procedures.
The followings occur when the TAiS bit is set to "0" (stops counting) while PWM pulse is output: - The counter stops counting Output level changes to low ("L") and the IR bit changes to "1" when the TAiOUT pin is held high ("H") - The IR bit and the output level remain unchanged when TAiOUT pin is held "L" 27. Precautions (Timer)

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27.9.3 Timer B

27.9.3.1 Timer B (Timer Mode, Event Counter Mode)

The TBiS (i=0 to 5) bit is set to "0" (stops counting) after reset. Set the TBiS bit to "1" (starts counting) after selecting an operating mode and setting TBi register. The TB2S to TB0S bits are bits 7 to 5 in the TABSR register. The TB5S to TB3S bits are bits 7 to 5 in the TBSR register.
The TBi register indicates the counter value during counting at any given time. However, the counter is "FFFF16" when reloading. The setting value can be read after setting the TBi register while the counter stops and before the counter starts counting.

27.9.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode)

The IR bit in the TBiIC (i=0 to 5) register is set to "1" (interrupt requested) when the valid edge of a pulse to be measured is input and when the timer Bi counter overflows. The MR3 bit in the TBiMR register determines the interrupt source within an interrupt routine.
Use another timer to count how often the timer counter overflows when an interrupt source cannot be determined by the MR3 bit, such as when a pulse to be measured is input at the same time the timer counter overflows.
To set the MR3 bit in the TBiMR register to "0" (no overflow), set the TBiMR register after the MR3 bit is set to "1" (overflow) and one or more cycles of the count source are counted, while the TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting).
The IR bit in the TBiIC register is used to detect overflow only. Use the MR3 bit only to determine interrupt source within an interrupt routine.
Indeterminate values are transferred to the reload register during the first valid edge input after counting is started. Timer Bi interrupt request is not generated at this time.
The counter value is indeterminate when counting is started. Therefore, the MR3 bit setting may change to "1" (overflow) and causes timer Bi interrupt requests to be generated until a valid edge is input after counting is started.
The IR bit may be set to "1" (interrupt requested) if the MR1 and MR0 bits in the TBiMR register are set to a different value after a count begins. If the MR1 and MR0 bits are rewritten, but to the same value as before, the IR bit remains unchanged.
Pulse width measurement measures pulse width continuously. Use program to determine whether measurement results are high ('"H") or low ("L"). 27. Precautions (Timer)

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27.10 Serial I/O

27.10.1 Clock Synchronous Serial I/O Mode

The RTS2 and CLK2 pins are placed in high-impedance states when a low-level ("L") signal is applied to the NMI pin while the INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three- phase output by an "L" signal applied to the NMI pin).

27.10.1.1 Transmission /Reception

When the RTS function is used while an external clock is selected, the output level of the RTSi pin is held "L" indicating that the microcomputer is ready for reception. The transmitting microcomputer is notified that reception is possible. The output level of the RTSi pin becomes high ("H") when reception begins. Therefore, connecting the RTSi pin to the CTSi pin of the transmitting microcomputer synchro- nizes transmission and reception. The RTS function is disabled if an internal clock is selected.

27.10.1.2 Transmission

When an external clock is selected while the CKPOL bit in the UiC0 (i=0 to 4) register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the external clock is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the transfer clock and received on the falling edge) and the external clock is held "L", meet the following conditions:

Set the TE bit in the UiC1 register to "1" (receive enabled)
Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Apply "L" signal to the CTSi pin if the CTS function is selected

27.10.1.3 Reception

Activating the transmitter in clock synchronous serial I/O mode generates the shift clock. Therefore, set for transmission even if the microcomputer is used for reception only. Dummy data is output from the TxDi pin while receiving. If an internal clock is selected, the shift clock is generated when the TE bit in the UiC1 registers is set to "1" (receive enabled) and dummy data is set in the UiTB register. If an external clock is selected, the shift clock is generated when the external clock is input into CLKi pin while the TE bit is set to "1" (receive enabled) and dummy data is set in the UiTB register. When receiving data consecutively while the RE bit in the UiC1 register is set to "1" (data in the UiRB register) and the next data is received by the UARTi reception register, an overrun error occurs and the OER bit in the UiRB register is set to "1" (overrun error). In this case, the UiRB register is indeter- minate. When overrun error occurs, program both reception and transmission registers to retransmit earlier data. The IR bit in the SiRIC does not change when an overrun error occurs. When receiving data consecutively, feed dummy data to the low-order byte in the UiTB register every time a reception is made. When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the external clock is held "H" or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the transfer clock and received on the falling edge) and the external clock is held "L", meet the following conditions:

Set the RE bit in the UiC1 register to "1" (receive enabled)
Set the TE bit in the UiC1 register to "1" (transmit enabled)
Set the TI bit in the UiC1 register to "0" (data in the UiTB register) 27. Precautions (Serial I/O)

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27.10.2 UART Mode

Set the UiERE bit (i=0 to 4) in the UiC1 register after setting the UiMR register.

27.10.3 Special Mode 1 (I2C Mode)

To generate the start condition, stop condition or restart condition, set the STSPSEL bit in the UiSMR4 register to "0" first. Then, change each condition generating bit (the STAREQ bit, STPREQ bit or RSTAREQ bit) setting from "0" to "1" after going through a half cycle of the transfer clock. 27. Precautions (Serial I/O)

Page 469 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M

27.11 A/D Converter

Set the AD0CON0 (bit 6 excluded), AD0CON1, AD0CON2, AD0CON3, and AD0CON4 registers while the A/D conversion is stopped (before a trigger is generated).
Wait a minimum of 1µs before starting the A/D conversion when changing the VCUT bit setting in the AD0CON1 register from "0" (VREF no connection) to "1" (VREF connection). Change the VCUT bit setting from "1" to "0" after the A/D conversion is completed.
Insert capacitors between the AVCC pin, VREF pin, analog input pin ANij (i=none, 0, 2, 15; j=0 to 7) and AV SS pin to prevent latch-ups and malfunctions due to noise, and to minimize conversion errors. The same applies to the VCC and VSS pins. Figure 27.4 shows the use of capacitors to reduce noise. 27. Precautions (A/D Converter) Microcomputer NOTES: 2. Use thick and shortest possible wiring to connect capacitors. VCC VSS AV CC AV SS VREF ANi C1 C2 C3VCC VSS ANi: ANi, AN0i, AN15i and AN2i (i=0 to 7) VCC VCC VCC Figure 27.4 Use of Capacitors to Reduce Noise
Set the bit in the port direction register, which corresponds to the pin being used as the analog input, to "0" (input mode). Set the bit in the port direction register, which corresponds to the ADTRG pin, to "0" (input mode) if the TRG bit in the AD0CON0 register is set to "1" (external trigger).
When generating a key input interrupt, do not use the AN4 to AN7 pins as analog input pins (key input interrupt request is generated when the A/D input voltage becomes "L").
The φAD frequency must be 16MHz or less. When the sample and hold function is not activated, the φAD frequency must be 250 kHz or more. If the sample and hold function is activated, the φAD frequency must be 1MHz or more.
Set the CH2 to CH0 bits in the AD0CON0 register or the SCAN1 and SCAN0 bits in the AD0CON1 register to re-select analog input pins when changing A/D conversion mode.

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AVCC = VREF = VCC , A/D input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0, and ANEX1) ≤ VCC .
Wrong values are stored in the AD0i register (i=0 to 7) if the CPU reads the AD0i register while the AD0i register stores results from a completed A/D conversion. This occurs when the CPU clock is set to a divided main clock or a sub clock. In one-shot mode or single sweep mode, read the corresponding AD0i register after verifying that the A/D conversion has been completed. The IR bit in the AD0IC register determines the completion of the A/D conversion. In repeat mode, repeat sweep mode 0, repeat sweep mode 1, multi-port single sweep mode, and multi- port repeat sweep mode 0, use an undivided main clock as the CPU clock.
Conversion results of the A/D converter are indeterminate if the ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) and the conversion is forcibly terminated by program during the A/D conversion. The AD0i register not performing the A/D conversion may also be indeterminate. If the ADST bit is changed to "0" by program, during the A/D conversion, do not use any values obtained from the AD0i registers.
External triggers cannot be used in DMAC operating mode. Do not read the AD00 register by program.
Do not perform the A/D conversion in wait mode.
Set the MCD4 to MCD0 bits in the MCD register to "10010 2" (no division) if using the sample and hold function.
Do not acknowledge any interrupt requests, even if generated, before setting the ADST bit, if the A/D conversion is terminated by setting the ADST bit in the AD0CON0 register to "0" (A/D conversion stopped) while the microcomputer is A/D converting in single sweep mode. 27. Precautions (A/D Converter)

Page 471 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M

27.12 Intelligent I/O

27.12.1 Register Setting

Operations, controlled by the values written to the G1BT, G1BCR1, G1TMCR0 to G1TMCR7, G1TPR6, G1TPR7, G1TM0 to G1TM7, G1POCR0 to G1POCR7, G1PO0 to G1PO7, G1FS and G1FE registers, are affected by the count source (f BT1 ) set in the BCK1 and BCK0 bits in the G1BCR0 register. Set the BCK1 and BCK0 bits before setting the G1BT, G1BCR1, G1TMCR0 to G1TMCR7, G1TPR6, G1TPR7, G1TM0 to G1TM7, G1POCR0 to G1POCR7, G1PO0 to G1PO7, G1FS and G1FE registers. Operations, controlled by the values written to the G0RI and G1RI, G0TO and G1TO, G0CR and G1CR, G0RB and G1RB, G0MR and G1MR, G0EMR and G1EMR, G0ETC and G1ETC, G0ERC and G1ERC, G0IRF, G1IRF, G0TB and G1TB, G0CMP0 to G0CMP3, G1CMP0 to G1CMP3, G0MSK0 and G0MSK1, G1MSK0 and G1MSK1, G0TCRC and G1TCRC, G0RCRC and G1RCRC registers are affected by the transfer clock. Set trasfer clock before setting the G0RI and G1RI, G0TO and G1TO, G0CR and G1CR, G0RB and G1RB, G0MR and G1MR, G0EMR and G1EMR, G0ETC and G1ECT, G0ERC and G1ERC, G0IRF and G1IRF, G0TB and G1TB, G0CMP0 to G0CMP3, G1CMP0 to G1CMP3, G0MSK0 and G0MSK1, G1MSK0 and G1MSK1, G0TCRC and G1TCRC, G0RCRC and G1RCRC registers. 27. Precautions (Intelligent I/O)

Page 472 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M

27.13 Programmable I/O Ports

Because ports P72 to P75, P80, and P81 have three-phase PWM output forced cutoff function, they are affected by the three-phase motor control timer function and the NMI pin when these ports are set for output functions (port output, timer output, three-phase PWM output, serial I/O output, intelligent I/O output). Table 27.4 shows the INVC0 register setting, the NMI pin input level and the state of output ports. Table 27.4 INVC0 Register and the NMI Pin 27. Precautions (Programmable I/O Ports) NOTES : 1. The INV03 bit is set to "0" after a low-level ("L") signal is applied to the NMI pin.
The availability of pull-up resistors is indeterminate until internal power voltage stabilizes, if the RESET pin is held "L".
The input threshold voltage varies between programmable I/O ports and peripheral functions. There- fore, if the lelvel of the voltage applied to a pin shared by both programmable I/O ports and peripheral functions is not within the recommended operating condition, V IH and VIL (neither "H" nor "L"), the level may vary depending on the programmable ports and peripheral functions. retsigeR0CVNIehtfoeulaVgnitteS deilppAlevellangiS niPIMNehtot 7P 2 7Pot ,5 8P 0 8P, 1 setatSniP )sniPtuptuOsamehTgnitteSnehW(tiB20VNIt iB30VNI esahP-eerhTehtgnisUtoN( remiTlortnoCrotoM )snoitcnuF -- e htybdetcelessnoitcnufsedivorP 2LSP,2SP,CSP,1LSP,1SP sretsiger esahP-eerhTehtgnisU( remiTlortnoCrotoM )snoitcnuF (l ortnoCrotoMesahP-eerhT delbasiDtuptuOremiT) -e tatsecnadepmi-hgiH (l ortnoCrotoMesahP-eerhT delbanEtuptuOremiT) )1( He htybdetcelessnoitcnufsedivorP 2LSP,2SP,CSP,1LSP,1SP sretsiger L )detanimreTylbicroF( etatsecnadepmi-hgiH

Page 473 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 27. Precautions (Flash Memory Version)

27.14 Flash Memory Version

27.14.1 Boot Mode

I/O pins may not be placed in high-impedance states until internal voltage stabilizes, when power is turned on in boot mode. Use the following procedure to turn on power in boot mode. 1) Apply an "L" signal to the RESET and the CNVSS pin 2) Wait a minimum of 2ms after VCC reaches 2.7V or above (until internal voltage stabilizes) 3) Apply an "H" signal to the CNVSS pin 4) Apply an "H" signal to the RESET pin (reset exited)

Page 474 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M 27. Precautions (Noise)

27.15 Noise

Connect a bypass capacitor (0.1µF or more) between VCC and VSS by shortest path, using thick wires.

Page 475 974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Package Dimensions Package Dimensions Terminal cross section c 1.0 0.125 0.20 1.25 1.25 0.08 0.200.1450.09 0.270.220.17 MaxNomMin Dimension in Millimeters Symbol Reference 20.120.019.9D 20.120.019.9E 1.4A2 22.222.021.8 22.222.021.8 1.7A 0.150.10.05 0.650.50.35L x 8∞0∞ c 0.5e 0.10y HD HE bp ZD ZE P-LQFP144-20x20-0.50 1.2g MASS[Typ.] 144P6Q-A / FP-144L / FP-144LVPLQP0144KA-A RENESAS CodeJEITA Package Code Previous Code F 1 36 73108 109 144 y HE E D HD ZD Z Detail F c A L A1 A2 1. * *2" NOTE)

974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M Register Index A AD00 to AD07 242 AD0CON0 238 AD0CON1 239 AD0CON2 240 AD0CON3 241 AD0CON4 242 AIER 116 C C0AFS 358 C0BPR 329 C0CONR 327 C0CTLR0 318 C0CTLR1 321 C0EFR 337 C0EIMKR 335 C0EISTR 336 C0GMR0 342 C0GMR1 343 C0GMR2 344 C0GMR3 345 C0GMR4 346 C0IDR 326 C0LMAR0 342 C0LMAR1 343 C0LMAR2 344 C0LMAR3 345 C0LMAR4 346 C0LMBR0 342 C0LMBR1 343 C0LMBR2 344 C0LMBR3 345 C0LMBR4 346 C0MCTL0 to C0MCTL15 349 C0MDR 338 C0REC 331 C0SBS 353 C0SIMKR 334 C0SISTR 332 C0SLOT0_0 354 C0SLOT0_1 354 C0SLOT0_2 355 C0SLOT0_3 355 C0SLOT0_4 356 C0SLOT0_5 356 C0SLOT0_6 to C0SLOT0_13 357 C0SLOT0_14 357 C0SLOT0_15 357 C0SLOT1_0 354 C0SLOT1_1 354 C0SLOT1_2 355 C0SLOT1_3 355 C0SLOT1_4 356 C0SLOT1_5 356 C0SLOT1_6 to C0SLOT1_13 357 C0SLOT1_14 357 C0SLOT1_15 357 C0SLPR 322 C0SSCTLR 340 C0SSSTR 341 C0STR 323 C0TEC 331 C0TSR 330 C1AFS 358 C1BRP 329 C1CONR 327 C1CTLR0 318 C1CTLR1 321 C1EFR 337 C1EIMKR 335 C1EISTR 336 C1GMR0 342 C1GMR1 343 C1GMR2 344 C1GMR3 345 C1GMR4 346 C1IDR 326 C1LMAR0 342 C1LMAR1 343 C1LMAR2 344 C1LMAR3 345 C1LMAR4 346 C1LMBR0 342 C1LMBR1 343

974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M C1LMBR2 344 C1LMBR3 345 C1LMBR4 346 C1MCTL0 to C1MCTL15 349 C1MDR 338 C1REC 331 C1SBS 353 C1SIMKR 334 C1SISTR 332 C1SLOT0_0 354 C1SLOT0_1 354 C1SLOT0_2 355 C1SLOT0_3 355 C1SLOT0_4 356 C1SLOT0_5 356 C1SLOT0_6 to C1SLOT0_13 357 C1SLOT0_14 357 C1SLOT0_15 357 C1SLOT1_0 354 C1SLOT1_1 354 C1SLOT1_2 355 C1SLOT1_3 355 C1SLOT1_4 356 C1SLOT1_5 356 C1SLOT1_6 to C1SLOT1_13 357 C1SLOT1_14 357 C1SLOT1_15 357 C1SLPR 322 C1SSCTLR 340 C1SSSTR 341 C1STR 323 C1TEC 331 C1TSR 330 CCS 298 CM0 73, 123 CM1 74 CM2 76 CPSRF 77 CRCD 257 CRCIN 257 D D4INT 45 DA0, DA1 256 DACON 256 DCT0 to DCT3 130 DM0SL to DM3SL 127 DMA0 to DMA3 131 DMD0, DMD1 129 DRA0 to DRA3 131 DRC0 to DRC3 130 DS 54 DSA0 to DSA3 131 DTT 177 E EWCR0 to EWCR3 60 F FMR0 398 FMR1 399 G G0CMP0 to G0CMP3 297 G0CR, G1CR 290 G0DR, G1DR 296 G0EMR 292 G0ERC, G1ERC 294 G0ETC 293 G0IRF 295 G0MR 291 G0MSK0, G0MSK1 297 G0RB, G1RB 290 G0RCRC, G1RCRC 297 G0RI, G1RI 289 G0TB, G1TB 296 G0TCRC, G1TCRC 297 G0TO, G1TO 289 G1BCR0 265 G1BCR1 266 G1BT 265 G1CMP0 to G1CMP3 297 G1EMR 292 G1ETC 293 G1FE 270 G1FS 269 G1IRF 296 G1MR 291 G1MSK0, G1MSK1 297 G1PO0 to G1PO7 269

974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M G1POCR0 to G1POCR7 268 G1TM0 to G1TM7 268 G1TMCR0 to G1TMCR7 267 G1TPR6, G1TPR7 267 I ICTB2 178 IDB0, IDB1 177 IFSR 114, 192 IIO0IE to IIO5IE, IIO8IE to IIO11IE120 IIO0IR to IIO5IR, IIO8IR to IIO11IR119 Interrupt Control105, 106 INVC0 175 INVC1 176 IPS 385 IPSA 386 M MCD 75 O ONSF 149 OPS 311 P P0 to P15 372 PCR 385 PD0 to PD15 371 PLC0 78 PLC1 78 PM0 51 PM1 52 PM2 79 PRCR 96 PS0 373 PS1 373 PS2 374 PS3 374 PS5 375 PS6 375 PS7 376 PS8 376 PS9 377 PSC 381 PSC2 381 PSC3 382 PSD1 382 PSL0 378 PSL1 378 PSL2 379 PSL3 379 PSL6 380 PSL7 380 PUR0 383 PUR1 383 PUR2 383 PUR3 384 PUR4 384 R RLVL 107, 137 RMAD0 to RMAD7 116 ROMCP 396 T TA0 to TA4 147 TA0MR to TA4MR 148, 153, 156, 159, 161 TA1, TA2, TA4, TA11, TA21, TA41178 TA1MR, TA2MR, TA4MR 180 TABSR 148, 164, 179 TB0 to TB5 163 TB0MR to TB5MR 164, 166, 168, 170 TB2 179 TB2MR 180 TB2SC 178 TBSR 165 TCSPR 77, 150 TRGSR 150, 179 U U0BRG to U4BRG 186 U0C0 to U4C0 187 U0C1 to U4C1 188 U0MR to U4MR 186 U0RB to U4RB 185 U0SMR to U4SMR 188 U0SMR2 to U4SMR2 189 U0SMR3 to U4SMR3 190 U0SMR4 to U4SMR4 191 U0TB to U4TB 185 UDF 149

974fo5002,80.peS00.1.veR 0010-4020B90JER )T68/C23M,68/C23M(puorG68/C23M V VCR1 44 VCR2 44 W WDC 43, 122 WDTS 122 X X0R to X15R 259 XYC 259 Y Y0R to Y15R 259

REVISION HISTORY

Rev. Date Description Page Summary C-1 M32C/86 Group(M32C/86, M32C/86T) Hardware Manual − New Document1.00 Sep.08, 05

RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M32C/86 Group (M32C/86, M32C/86T) Publication Data : Rev.1.00 Sep. 08, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.

M32C/86 Group (M32C/86, M32C/86T) Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan

Product Information

M32C/86 specifications and overview.

Summary

RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

Description

RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

Source title M32C/86 Datasheet(PDF) - Renesas Technology Corp

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