M30LW128D

M30LW128D STMICROELECTRONICS | Alldatasheet

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Technical content

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories)

Figure 1. Packages

The M30LW128D is a 128 Mbit device that is com- posed of two separate 64 Mbit M58LW064D Flash memories. The device can be erased electrically at block level and programmed in-system using a 2.7V to 3.6V (V DD ) supply for the circuitry and a 1.8V to VDD (VDDQ ) supply for the Input/Output pins. The bus width can be configured for x8 or x16 for the devices available in the TSOP56 (14 x 20 mm) and TBGA64 (10x13mm , 1mm pitch) packages. The bus width is set to x16 for the devices avail- able in the LFBGA88 (8x10mm, 0.8mm pitch) package. Each internal M58LW064D has 3 Chip Enable sig- nals to allow up to 4 memories to be connected to- gether without the use of additional glue logic. In this way the address space is contiguous and the microprocessor only requires one Chip Enable, E to control both memories. The device is divided into 128 blocks of 1Mbit (2 x 64 x 1Mb) that can be erased independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the Command Interface of the device. An on- chip Program/Erase Controller (P/E.C) simplifies the process of programming or erasing the device by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be de- tected and any error conditions identified in the Status Register. The command set required to control the device is consistent with JEDEC stan- dards. The Write Buffer allows the microprocessor to pro- gram from 1 to 16 Words in parallel, both speeding up the programming and freeing up the micropro- cessor to perform other work. A Word Program command is available to program a single word. Erase can be suspended in order to perform either Read or Program in any other block and then re- sumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cy- cles. Individual block protection against Program or Erase is provided for data security. All blocks are protected during power-up. The protection of the blocks is non-volatile; after power-up the protec- tion status of each block is restored to the state when power was last removed. Software com- mands are provided to allow protection of some or all of the blocks and to cancel all block protection bits simultaneously. All Program or Erase opera- tions are blocked when the Program Erase Enable input V PEN is low. The Reset/Power-Down pin is used to apply a Hardware Reset to the enabled memory and to set the device in power-down mode. The STS signal is an open drain output that can be used to identify the Program/Erase Controller sta- tus. It can be configured in two modes: Ready/ Busy mode where a static signal indicates the sta- tus of the P/E.C, and Status mode where a pulsing signal indicates the end of a Program or Block Erase operation. In both modes it can be used as a system interrupt signal, useful for saving CPU time. The STS signal is only available with the TSOP56 and TBGA64 packages. Each memory includes a 128 bit Protection Regis- ter. The Protection Register is divided into two 64 bit segments, the first one is written by the manu- facturer (contact STMicroelectronics to define the code to be written here), while the second one is programmable by the user. The user programma- ble segment can be locked.

Figure 2. Logic Diagram Note: 1. Not available with LFBGA88 package. Table 1. Signal Names Note: 1. Not available with LFBGA88 package.

Figure 3. TSOP56 Connections tied to ground (VSS ) to assure compatibility with a single chip 128Mbit device.

Figure 4. TBGA64 Connections (Top view through package) be tied to ground (VSS ) to assure compatibility with a single chip 128Mbit device.

Figure 5. LFBGA Connections (Top view through package) Note: 1. The BYTE, STS and A0 connections are not available with the LFBGA88 package.

See Figure 2, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Input (A0).The A0 address input is used to select the higher or lower Byte in x8 mode. It is not used in x16 mode (where A1 is the Lowest Significant bit). The A0 address input is not available with the LFBGA88 package. Address Inputs (A1-A22).The Address Inputs are used to select the cells to access in the mem- ory array during Bus Read operations either to read or to program data to. During Bus Write oper- ations they control the commands sent to the Command Interface of the internal state machine. The device must be enabled (refer to Table 3, M30LW128D Device Enable) when selecting the addresses. The address inputs are latched on the rising edge of Write Enable or Chip Enable, E whichever occurs first. Address Input (A23).Address Input A23 is used to select between the two internal memories. When it is High, VIH, it selects the Upper Memory, when it is Low, VIL, it selects the Lower Memory. Refer to Memory Enable section for more details. Data Inputs/Outputs (DQ0-DQ15).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. Dur- ing Bus Write operations they represent the com- mands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, E , whichever occurs first. When the device is enabled and Output Enable is low, VIL, the data bus outputs data from the mem- ory array, the Electronic Signature, the Block Pro- tection status, the CFI Information or the contents of the Status Register. The data bus is high imped- ance when the device is deselected, Output En- able is high, V IH, or the Reset/Power-Down signal is low, VIL. When the Program/Erase Controller is active the Ready/Busy status is given on DQ7. Chip Enable (E).The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. The M30LW128D stacked memory uses the A23 address line and the external Chip Enable, E , to select and enable the internal memories. Refer to Memory Enable section and Table 3, for more details. When the Chip Enable deselects the memory, power consumption is reduced to the Standby lev- el, IDD1 . Output Enable (G).The Output Enable, G, gates the outputs through the data output buffers during a read operation. When Output Enable, G , is at VIH the outputs are high impedance. Write Enable (W).The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write En- able. Reset/Power-Down (RP ).The Reset/Power- Down signal can be used to apply a Hardware Re- set to the memory. A Hardware Reset is achieved by holding Reset/ Power-Down Low, V IL, for at least tPLPH . When Reset/Power-Down is Low, VIL, the Status Regis- ter information is cleared and the power consump- tion is reduced to power-down level. The device is deselected and outputs are high impedance. If Re- set/Power-Down goes low, V IL,during a Block Erase, a Write to Buffer and Program or a Block Protect/Unprotect the operation is aborted and the data may be corrupted. In this case the STS pin stays low, V IL, for a maximum timing of tPLPH + tPH- BH, until the completion of the Reset/Power-Down pulse. After Reset/Power-Down goes High, VIH, the de- vice will be ready for Bus Read and Bus Write op- erations after t PHQV . Note that STS does not fall during a reset, see Ready/Busy Output section. In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset opera- tion occurs while the device is performing an Erase or Program operation, the device may out- put the Status Register information instead of be- ing initialized to the default Asynchronous Random Read. Byte/Word Organization Select (BYTE ).The Byte/Word Organization Select signal is used to switch between the x8 and x16 bus widths of the memory. When Byte/Word Organization Select is Low, V IL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode. The Byte/Word Organization Select signal is not available with the LFBGA88 package. Status/(Ready/Busy) (STS).The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: ■ Ready/Busy - the pin is Low, VOL , during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation.

■ Status - the pin gives a pulsing signal to indicate the end of a Program or Block Erase operation. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured for Status mode using the Configure STS com- mand. When the Program/Erase Controller is idle, or sus- pended, STS can float High through a pull-up re- sistor. The use of an open-drain output allows the STS pins from several devices to be connected to a single pull-up resistor (a Low will indicate that one, or more, of the memories is busy). STS is not Low during a reset unless the reset was applied when the Program/Erase controller was active. The STS signal is not available with the LFBGA88 package. Program/Erase Enable (V PEN ).The Program/ Erase Enable input, VPEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data. Program/Erase Enable must be kept High during all Program/Erase Controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. VDD Supply Voltage.VDD provides the power supply to the internal core of the device. It is the main power supply for all operations (Read, Pro- gram and Erase). VDDQ Supply Voltage.VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD . VDDQ can be tied to VDD or can use a separate supply. It is recommended to power-up and power-down VDD and VDDQ together to avoid any condition that would result in data corruption. VSS Ground. Ground, VSS, is the reference for the core power supply. It must be connected to the system ground. V SSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VDDQ . VSSQ must be connected to VSS . Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, in- herently low inductance capacitors should be as close as possible to the package). See Fig- ure 10, AC Measurement Load Circuit.

Figure 6. Stacked Flash Memory

64 Mbit

Figure 7. Block Addresses

1 Mbit or

128 KBytes

1 Mbit Blocks

64 KWords

Table 4. Bus Operations Note: 1. DQ8-DQ15 are High Z in x8 mode.

1. X = Don’t Care VIL or VIH. High = VIH or VHH .

All Bus Write operations to the device are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. As the device contains two internal memo- ries care must be taken to issue the commands to the correct address. Commands issued with A23 High will be addressed to the Upper Memory, com- mands issued with A23 Low will be addressed to the Lower Memory. The Commands are summarized in Table 5, Com- mands. Refer to Table 5 in conjunction with the text descriptions below. After power-up or a Reset operation the device en- ters Read mode. Read Memory Array Command. The Read Mem- ory Array command is used to return the device to Read mode. One Bus Write cycle is required to is- sue the Read Memory Array command and return the device to Read mode. Once the command is issued the device remains in Read mode until an- other command is issued. From Read mode Bus Read operations will access the memory arrays. After power-up or a reset the device defaults to Read Array mode (Page Read). While the Program/Erase Controller is executing a Program, Erase, Block Protect, Blocks Unprotect or Protection Register Program operation the de- vice will not accept the Read Memory Array com- mand until the operation completes. Read Electronic Signature Command.The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Protection Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the com- mand is issued subsequent Bus Read operations read the Manufacturer Code, the Device Code, the Block Protection Status or the Protection Register until another command is issued. Refer to Table 7, Read Electronic Signature, Tables 8 and 9, Word and Byte-wide Read Protection Register and Fig- ure 8, Protection Register Memory Map for infor- mation on the addresses. Read Query Command. The Read Query Com- mand is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash In- terface Memory Area. See Appendix B, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface (CFI) memory area. Read Status Register Command.The Read Sta- tus Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. As the device contains two Status Registers (one for each inter- nal memory) the command must be issued to the same address as the previous operation (Block Erase, Write to Buffer, Word Program etc.). Once the command is issued subsequent Bus Read op- erations to the same internal memory (A23 Low or A23 High depending on where the command was issued to) read the Status Register until another command is issued. If the Bus Read operation is issued to the other internal memory, then the other Status Register will be read, giving the status of the last command issued in the other internal memory. The Status Register information is present on the output data bus (DQ1-DQ7) when the device is en- abled and Output Enable is Low, V IL. See the section on the Status Register and Table 11 for details on the definitions of the Status Reg- ister bits Clear Status Register Command.The Clear Sta- tus Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. The command must be issued to the same address as the previous operation (Block Erase, Write to Buffer, Word Program etc.). The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Write to Buffer and Program, Erase, Block Protect, Block Unprotect or Protection Register Program com- mand is issued. If any error occurs then it is essen- tial to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command. The Block Erase com- mand can be used to erase a block. It sets all of the bits in the block to ‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read opera- tions read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During Erase, the device being erased will only ac- cept the Read Status Register and Program/Erase Suspend commands, ignoring all other com- mands. The device not being erased will accept

any command. Typical Erase times are given in Table 10. See Appendix C, Figure 21, Block Erase Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Word/Byte Program Command. The Word/ Byte Program command is used to program a sin- gle Word or Byte in the memory array. Two Bus Write operations are required to issue the com- mand; the first write cycle sets up the Word Pro- gram command, the second write cycle latches the address and data to be programmed in the internal state machine and starts the Program/Erase Con- troller. If the block being programmed is protected an er- ror will be set in the Status Register and the oper- ation will abort without affecting the data in the memory array. The block must be unprotected us- ing the Blocks Unprotect command. Write to Buffer and Program Command.The Write to Buffer and Program command is used to program the memory array. If the command is is- sued with A23 High the Upper Memory will be pro- grammed, if the command is issued with A23 Low the Lower Memory will be programmed. Up to 16 Words/32 Bytes can be loaded into the Write Buffer and programmed into the memory ar- ray. Each Write Buffer has the same A5-A22 ad- dresses. In Byte-wide mode only A0-A4 may change, in Word-wide mode only A1-A4 may change. Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program Command. Is- sue the set up command with the selected memory Block Address where the program op- eration should occur (any address in the block where the values will be programmed can be used). Any Bus Read operations will start to out- put the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the same block address along with the value N on the Data Inputs/Output, where N+1 is the number of Words/Bytes to be programmed. 3. Use N+1 Bus Write operations to load the ad- dress and data for each Word into the Write Buffer. The addresses must have the same A5- A22. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the oper- ation without affecting the data in the memory ar- ray. The Status Register should be cleared before re-issuing the command. If the block being programmed is protected an er- ror will be set in the Status Register and the oper- ation will abort without affecting the data in the memory array. The block must be unprotected us- ing the Blocks Unprotect command. See Appendix C, Figure 19, Write to Buffer and Program Flowchart and Pseudo Code, for a sug- gested flowchart on using the Write to Buffer and Program command. Program/Erase Suspend Command. The Pro- gram/Erase Suspend command is used to pause a Write to Buffer and Program or Erase operation. The command will only be accepted during a Pro- gram or an Erase operation. It can be issued at any time during an Erase operation but will only be accepted during a Write to Buffer and Program command if the Program/Erase Controller is run- ning. One Bus Write cycle is required to issue the Pro- gram/Erase Suspend command and pause the Program/Erase Controller. The command must be issued to the same address as the current Pro- gram or Erase operation. Once the command is is- sued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the device will con- tinue to output the Status Register until another command is issued. During the polling period between issuing the Pro- gram/Erase Suspend command and the Program/ Erase Controller pausing, it is possible for the op- eration to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Pro- gram/Erase Controller is no longer active, the Pro- gram Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to deter- mine if the operation has completed or is suspend- ed. For timing on the delay between issuing the Program/Erase Suspend command and the Pro- gram/Erase Controller pausing see Table 10. During Program/Erase Suspend the Read Memo- ry Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Re- sume commands will be accepted by the Com- mand Interface. Additionally, if the suspended operation was Erase then the Word Program, Write to Buffer and Program, and Program Sus- pend commands will also be accepted. When one of the devices is being Program or Erase Suspended, any command issued to the other internal Flash memory will be accepted. When a program operation is completed inside a

Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix C, Figure 20, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 22, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Pro- gram/Erase Resume command can be used to re- start the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Pro- gram/Erase Resume command. The command must be issued to the same address as the Pro- gram/Erase Suspend command. Once the com- mand is issued subsequent Bus Read operations read the Status Register. Block Protect Command. The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to is- sue the Block Protect command; the second Bus Write cycle latches the block address in the inter- nal state machine and starts the Program/Erase Controller. Once the command is issued subse- quent Bus Read operations read the Status Reg- ister. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Protect operation the device will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 10. The Block Protection bits are non-volatile, once set they remain set through reset and power- down/power-up. They are cleared by a Blocks Un- protect command. See Appendix C, Figure 23, Block Protect Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Protect command. Blocks Unprotect Command. The Blocks Un- protect command is used to unprotect all of the blocks. To unprotect all of the blocks in both of the internal memories the command must be issued to both memories, that is first with A23 Low and then with A23 High. Four Bus Write cycles are required to issue the Blocks Unprotect command; the first two are writ- ten with A23 Low, the second two are written with A23 High. Once the command is issued subse- quent Bus Read operations read the Status Reg- ister. See the section on the Status Register for details on the definitions of the Status Register bits. During the Blocks Unprotect operation the device will only accept the Read Status Register com- mand. All other commands will be ignored. Typical Block Protection times are given in Table 10. See Appendix C, Figure 24, Blocks Unprotect Flowchart and Pseudo Code, for a suggested flow- chart on using the Blocks Unprotect command. Protection Register Program Command. The Protection Register Program command is used to Program the 64 bit user segment of the Protection Register. Only the lower address Pro- tection Register is available to the customer (A23 Low), the other Protection Register is reserved. Two write cycles are required to issue the Protec- tion Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The user-programmable segment can be locked by programming bit 1 of the Protection Register Lock location to ‘0’ (see Table 8 and x for Word- wide and Byte-wide protection addressing). Bit 0 of the Protection Register Lock location locks the factory programmed segment and is programmed to ‘0’ in the factory. The locking of the Protection Register is not reversible, once the lock bits are programmed no further changes can be made to the values stored in the Protection Register, see Figure 8, Protection Register Memory Map. At- tempting to program a previously protected Pro- tection Register will result in a Status Register error. The Protection Register Program cannot be sus- pended. See Appendix C, Figure 25, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the Protection Register Program command. Configure STS Command. The Configure STS command is used to configure the Status/(Ready/Busy) pin. It has to be config- ured for both internal memories, that is the com- mand has to be issued first with A23 Low and then with A23 High. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured in Status mode using the Configure STS command (refer to Status/(Ready/Busy) sec- tion for more details. Four Bus Write cycles are required to issue the Configure STS command. The first two cycles

error in the Status Register. Table 5. Commands Protection Register Data, CC Configuration Code. The shaded areas highlight the differences with a single M58LW064D memory.

1. For Identifier addresses and data refer to Table 7, Read Electronic Signature.
2. For Query Address and Data refer to Appendix B, CFI.
3. Not available with LFBGA88 package.

Table 6. Configuration Codes

1. When STS pin is pulsing it remains Low for a typical time of 250ns.

Table 7. Read Electronic Signature Note: 1. SBA is the Start Base Address of each block, PRD is Protection Register Data.

1. Base Address, refer to Figure 8 and Tables 8 and 9 for more information. A23 must be Low to address the customer’s Protection

Register. The other Protection Register is reserved.

1. A0 is not used in Read Electronic Signature in either x8 or x16 mode. The data is always presented on the lower byte in x16 mode.

of a Block Erase or Program operation.

Figure 8. Protection Register Memory Map Table 8. Word-Wide Read Protection Register

0 Factory (Unique ID) 1 0 000001

1 Factory (Unique ID) 1 0 000010

2 Factory (Unique ID) 1 0 000011

3 Factory (Unique ID) 1 0 000100

4 U s e r 10000101

5 U s e r 10000110

6 U s e r 10000111

7 U s e r 10001000

Table 9. Byte-Wide Read Protection Register

1 Factory (Unique ID) 1 0 000001

2 Factory (Unique ID) 1 0 000010

3 Factory (Unique ID) 1 0 000010

4 Factory (Unique ID) 1 0 000011

5 Factory (Unique ID) 1 0 000011

6 Factory (Unique ID) 1 0 000100

7 Factory (Unique ID) 1 0 000100

8 U s e r 10000101

9 U s e r 10000101

Table 10. Program/Erase Times and Program/Erase Endurance Cycles Note: 1. Typical values measured at room temperature and nominal voltages.

1. Sampled, but not 100% tested.
2. Effective byte programming time 6µs, effective word programming time 12µs.
3. Maximum value measured at worst case conditions for both temperature and VDD after 100,000 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VDD .

The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Reg- ister command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Blocks Unprotect and Program/Erase Re- sume commands. As the device contains two Sta- tus Registers (one for each internal memory) the Status Register must be read at the same address as the previous operation. The contents of the Status Register can be updat- ed during an Erase or Program operation by tog- gling the Output Enable pin or by dis-activating and then reactivating the device (refer to Table 3). Status Register bits 5, 4, 3 and 1 are associated with various error conditions and can only be reset with the Clear Status Register command. The Sta- tus Register bits are summarized in Table 11, Sta- tus Register Bits. Refer to Table 11 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7).The Pro- gram/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low, V OL , the Program/Erase Controller is active and all other Status Register bits are High Imped- ance; when the bit is High, VOH , the Program/ Erase Controller is inactive. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High. During Program, Erase, Block Protect and Blocks Unprotect operations the Program/Erase Control- ler Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Con- troller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6).The Erase Sus- pend Status bit indicates that an Erase operation has been suspended and is waiting to be re- sumed. The Erase Suspend Status should only be considered valid when the Program/Erase Con- troller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend com- mand is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is Low, V OL , the Program/Erase Controller is active or has com- pleted its operation; when the bit is High, V OH , a Program/Erase Suspend command has been is- sued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status (Bit 5).The Erase Status bit can be used to identify if the device has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). When the Erase Status bit is Low, V OL , the device has successfully verified that the block has erased correctly or all blocks have been unprotected suc- cessfully. When the Erase Status bit is High, V OH , the erase operation has failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH . ■ If only the Erase Status bit (bit 5) is set High, V OH , then the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. ■ If the failure is due to an erase or blocks unprotect with VPEN low, VOL , then VPEN Status bit (bit 3) is also set High, VOH . ■ If the failure is due to an erase on a protected block then Block Protection Status bit (bit 1) is also set High, V OH . ■ If the failure is due to a program or erase incorrect command sequence then Program Status bit (bit 4) is also set High, V OH . Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4).The Program Status bit is used to identify a Program or Block Protect fail- ure. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is Low, V OL , the de- vice has successfully verified that the Write Buffer has programmed correctly or the block is protect- ed. When the Program Status bit is High, V OH , the program or block protect operation has failed. De- pending on the cause of the failure other Status Register bits may also be set to High, V OH .

■ If only the Program Status bit (bit 4) is set High, VOH , then the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the Write Buffer has programmed correctly or that the Block is protected. ■ If the failure is due to a program or block protect with V PEN low, VOL , then VPEN Status bit (bit 3) is also set High, VOH . ■ If the failure is due to a program on a protected block then Block Protection Status bit (bit 1) is also set High, V OH . ■ If the failure is due to a program or erase incorrect command sequence then Erase Status bit (bit 5) is also set High, VOH . Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. V PEN Status (Bit 3).The VPEN Status bit can be used to identify if a Program, Erase, Block Protec- tion or Block Unprotection operation has been at- tempted when VPEN is Low, VIL. When the VPEN Status bit is Low, VOL , no Pro- gram, Erase, Block Protection or Block Unprotec- tion operations have been attempted with VPEN Low, VIL, since the last Clear Status Register com- mand, or hardware reset. When the VPEN Status bit is High, VOH , a Program, Erase, Block Protec- tion or Block Unprotection operation has been at- tempted with VPEN Low, VIL. Once set High, the VPEN Status bit can only be re- set by a Clear Status Register command or a hard- ware reset. If set High it should be reset before a new Program, Erase, Block Protection or Block Unprotection command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2).The Program Suspend Status bit indicates that a Program oper- ation has been suspended and is waiting to be re- sumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive); after a Program/Erase Suspend command is issued the device may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is Low, V OL , the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH , a Program/Erase Suspend command has been is- sued and the device is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1).The Block Pro- tection Status bit can be used to identify if a Pro- gram or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is Low, V OL , no Program or Erase operations have been at- tempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is High, V OH , a Program (Program Status bit 4 set High) or Erase (Erase Status bit 5 set High) operation has been attempted on a protected block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register com- mand or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (Bit 0).Bit 0 of the Status Register is reserved. Its value should be masked.

Table 11. Status Register Bits

Table 12. Absolute Maximum Ratings Note: 1. Maximum one output short-circuited at a time and for no longer than 1 second.

when relying on the quoted parameters. Table 13. Operating and AC Measurement Conditions Figure 9. AC Measurement Input Output Figure 10. AC Measurement Load Circuit Table 14. Capacitance

1. Sampled only, not 100% tested.

0.5 VDDQ

Table 15. DC Characteristics

Figure 11. Bus Read AC Waveforms Note: 1. Refer to Table 3 for details of how the device is enabled.

1. BYTE can be Low or High. The BYTE signal is not available with the LFBGA88 package.

Table 16. Bus Read AC Characteristics

Figure 12. Page Read AC Waveforms Note: 1. Refer to Table 3 for details of how the device is enabled. Table 17. Page Read AC Characteristics Note: For other timings see Table 16, Bus Read AC Characteristics.

Figure 13. Write AC Waveform, Write Enable Controlled Note: 1. Refer to Table 3 for details of how the device is enabled.

1. Not available with the LFBGA88 package.

Table 18. Write AC Characteristics, Write Enable Controlled

Figure 14. Write AC Waveforms, Chip Enable Controlled Note: 1. Refer to Table 3 for details of how the device is enabled.

1. Not available with the LFBGA88 package.

Table 19. Write AC Characteristics, Chip Enable Controlled.

Figure 15. Reset, Power-Down and Power-Up AC Waveform Note: 1. Refer to Table 3 for details of how the device is enabled.

1. Not available with the LFBGA88 package.

Table 20. Reset, Power-Down and Power-Up AC Characteristics

Figure 16. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline Note: Drawing is not to scale. Table 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data

Figure 17. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline Note: Drawing is not to scale. Table 22. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data

Figure 18. LFBGA88 8x10 mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 23. LFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data Note: All of the values in the table are preliminary and are subject to change.

Table 24. Ordering Information Scheme Note: Devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.

Table 25. Block Addresses

128 FE0000h-FFFFFFh 7F0000h-7FFFFFh

127 FC0000h-FDFFFFh 7E0000h-7EFFFFh

126 FA0000h-FBFFFFh 7D0000h-7DFFFFh

125 F80000h-F9FFFFh 7C0000h-7CFFFFh

124 F60000h-F7FFFFh 7B0000h-7BFFFFh

123 F40000h-F5FFFFh 7A0000h-7AFFFFh

122 F20000h-F3FFFFh 790000h-79FFFFh

121 F00000h-F1FFFFh 780000h-78FFFFh

120 EE0000h-EFFFFFh 770000h-77FFFFh

119 EC0000h-EDFFFFh 760000h-76FFFFh

118 EA0000h-EBFFFFh 750000h-75FFFFh

117 E80000h-E9FFFFh 740000h-74FFFFh

116 E60000h-E7FFFFh 730000h-73FFFFh

115 E40000h-E5FFFFh 720000h-72FFFFh

114 E20000h-E3FFFFh 710000h-71FFFFh

113 E00000h-E1FFFFh 700000h-70FFFFh

112 DE0000h-DFFFFFh 6F0000h-6FFFFFh

111 DC0000h-DDFFFFh 6E0000h-6EFFFFh

110 DA0000h-DBFFFFh 6D0000h-6DFFFFh

109 D80000h-D9FFFFh 6C0000h-6CFFFFh

108 D60000h-D7FFFFh 6B0000h-6BFFFFh

107 D40000h-D5FFFFh 6A0000h-6AFFFFh

106 D20000h-D3FFFFh 690000h-69FFFFh

105 D00000h-D1FFFFh 680000h-68FFFFh

104 CE0000h-CFFFFFh 670000h-67FFFFh

103 CC0000h-CDFFFFh 660000h-66FFFFh

102 CA0000h-CBFFFFh 650000h-65FFFFh

101 C80000h-C9FFFFh 640000h-64FFFFh

100 C60000h-C7FFFFh 630000h-63FFFFh

99 C40000h-C5FFFFh 620000h-62FFFFh

98 C20000h-C3FFFFh 610000h-61FFFFh

97 C00000h-C1FFFFh 600000h-60FFFFh

96 BE0000h-BFFFFFh 5F0000h-5FFFFFh

95 BC0000h-BDFFFFh 5E0000h-5EFFFFh

94 BA0000h-BBFFFFh 5D0000h-5DFFFFh

93 B80000h-B9FFFFh 5C0000h-5CFFFFh

92 B60000h-B7FFFFh 5B0000h-5BFFFFh

91 B40000h-B5FFFFh 5A0000h-5AFFFFh

90 B20000h-B3FFFFh 590000h-59FFFFh

89 B00000h-B1FFFFh 580000h-58FFFFh

88 AE0000h-AFFFFFh 570000h-57FFFFh

87 AC0000h-ADFFFFh 560000h-56FFFFh

86 AA0000h-ABFFFFh 550000h-55FFFFh

85 A80000h-A9FFFFh 540000h-54FFFFh

84 A60000h-A7FFFFh 530000h-53FFFFh

83 A40000h-A5FFFFh 520000h-52FFFFh

82 A20000h-A3FFFFh 510000h-51FFFFh

81 A00000h-A1FFFFh 500000h-50FFFFh

64 7E0000h-7FFFFFh 3F0000h-3FFFFFh 63 7C0000h-7DFFFFh 3E0000h-3EFFFFh 62 7A0000h-7BFFFFh 3D0000h-3DFFFFh 61 780000h-79FFFFh 3C0000h-3CFFFFh 60 760000h-77FFFFh 3B0000h-3BFFFFh 59 740000h-75FFFFh 3A0000h-3AFFFFh 58 720000h-73FFFFh 390000h-39FFFFh 57 700000h-71FFFFh 380000h-38FFFFh 56 6E0000h-6FFFFFh 370000h-37FFFFh 55 6C0000h-6DFFFFh 360000h-36FFFFh 54 6A0000h-6BFFFFh 350000h-35FFFFh 53 680000h-69FFFFh 340000h-34FFFFh 52 660000h-67FFFFh 330000h-33FFFFh 51 640000h-65FFFFh 320000h-32FFFFh 50 620000h-63FFFFh 310000h-31FFFFh 49 600000h-61FFFFh 300000h-30FFFFh 48 5E0000h-5FFFFFh 2F0000h-2FFFFFh 47 5C0000h-5DFFFFh 2E0000h-2EFFFFh 46 5A0000h-5BFFFFh 2D0000h-2DFFFFh 45 580000h-59FFFFh 2C0000h-2CFFFFh 44 560000h-57FFFFh 2B0000h-2BFFFFh 43 540000h-55FFFFh 2A0000h-2AFFFFh 42 520000h-53FFFFh 290000h-29FFFFh 41 500000h-51FFFFh 280000h-28FFFFh 40 4E0000h-4FFFFFh 270000h-27FFFFh 39 4C0000h-4DFFFFh 260000h-26FFFFh 38 4A0000h-4BFFFFh 250000h-25FFFFh 37 480000h-49FFFFh 240000h-24FFFFh 36 460000h-47FFFFh 230000h-23FFFFh 35 440000h-45FFFFh 220000h-22FFFFh 34 420000h-43FFFFh 210000h-21FFFFh 33 400000h-41FFFFh 200000h-20FFFFh 32 3E0000h-3FFFFFh 1F0000h-1FFFFFh 31 3C0000h-3DFFFFh 1E0000h-1EFFFFh 30 3A0000h-3BFFFFh 1D0000h-1DFFFFh Block No. Address Range (x8 Bus Width) Address Range (x16 Bus Width) Lower Memory 29 380000h-39FFFFh 1C0000h-1CFFFFh 28 360000h-37FFFFh 1B0000h-1BFFFFh 27 340000h-35FFFFh 1A0000h-1AFFFFh 26 320000h-33FFFFh 190000h-19FFFFh 25 300000h-31FFFFh 180000h-18FFFFh 24 2E0000h-2FFFFFh 170000h-17FFFFh 23 2C0000h-2DFFFFh 160000h-16FFFFh 22 2A0000h-2BFFFFh 150000h-15FFFFh 21 280000h-29FFFFh 140000h-14FFFFh 20 260000h-27FFFFh 130000h-13FFFFh 19 240000h-25FFFFh 120000h-12FFFFh 18 220000h-23FFFFh 110000h-11FFFFh 17 200000h-21FFFFh 100000h-10FFFFh 16 1E0000h-1FFFFFh 0F0000h-0FFFFFh 15 1C0000h-1DFFFFh 0E0000h-0EFFFFh 14 1A0000h-1BFFFFh 0D0000h-0DFFFFh 13 180000h-19FFFFh 0C0000h-0CFFFFh 12 160000h-17FFFFh 0B0000h-0BFFFFh 11 140000h-15FFFFh 0A0000h-0AFFFFh 10 120000h-13FFFFh 090000h-09FFFFh 9 100000h-11FFFFh 080000h-08FFFFh 8 0E0000h-0FFFFFh 070000h-07FFFFh 7 0C0000h-0DFFFFh 060000h-06FFFFh 6 0A0000h-0BFFFFh 050000h-05FFFFh 5 080000h-09FFFFh 040000h-04FFFFh 4 060000h-07FFFFh 030000h-03FFFFh 3 040000h-05FFFFh 020000h-02FFFFh 2 020000h-03FFFFh 010000h-01FFFFh 1 000000h-01FFFFh 000000h-00FFFFh Block No. Address Range (x8 Bus Width) Address Range (x16 Bus Width)

Table 26. Query Structure Overview Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.

1. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
2. SBA is the Start Base Address for each block.
3. In x8 mode A0 must be set to VIL. Otherwise, 00h will be output.

Table 27. CFI - Query Address and Data Output Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to '0'.

1. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
2. In x8 mode A0 must be set to VIL. Otherwise, 00h will be output.

Table 28. CFI - Device Voltage and Timing Specification Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.

1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
2. In x8 mode A0 must be set to VIL. Otherwise, 00h will be output.

Table 29. Device Geometry Definition Note: 1. In x8 mode A0 must be set to VIL. Otherwise, 00h will be output.

1. N/A = Not Applicable. Only the x16 mode is available with the LFBGA88 package.

Table 30. Block Status Register Note: 1. BA specifies the block address location, A22-A17.

0 Block Unprotected

1 Block Protected

0 Last erase operation ended successfully (2)

1 Last erase operation not ended successfully (2)

Table 31. Extended Query information Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.

1. In x8 mode, A0 must be set to VIL, otherwise 00h will be output.

Figure 19. Write to Buffer and Program Flowchart and Pseudo Code

Figure 20. Program Suspend & Resume Flowchart and Pseudo Code

1. The Read Status Register command must be issued to the same address as the Program/ Erase Suspend command.
2. PA = Program Address. The Program/ Erase Resume command must be issued to the same address as the Program/ Erase Sus-

Figure 21. Erase Flowchart and Pseudo Code Note: 1. The Read Status Register command must be issued to the same address as the Block Erase command.

1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper-

Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code Note: 1. The Program/ Erase Suspend command must be issued to the same address as the current Erase command.

1. The Read Status Register command must be issued to the same address as the Program/ Erase Suspend command.
2. The Program/ Erase Resume command must be issued to the same address as the Program/ Erase Suspend command.

Figure 23. Block Protect Flowchart and Pseudo Code Note: 1. The Read Status Register command must be issued to the same address as the Block Protect command.

Figure 24. Blocks Unprotect Flowchart and Pseudo Code

Figure 25. Protection Register Program Flowchart and Pseudo Code

1. The Read Status Register command must be issued to the same address as the Protection Register Program command.

Figure 26. Command Interface and Program Erase Controller Flowchart (a) Note: The commands must be issued to the addresses detailed in the Command Interface section, Table 5. Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.

Figure 27. Command Interface and Program Erase Controller Flowchart (b) Note: The commands must be issued to the addresses detailed in the Command Interface section, Table 5.

Figure 28. Command Interface and Program Erase Controller Flowchart (c). Note: The commands must be issued to the addresses detailed in the Command Interface section, Table 5.

REVISION HISTORY

Table 32. Document Revision History VIH and VLKO values refined in DC Characteristics table. modified for Blocks Unprotect and Configure STS commands in Table 5, Commands. Addresses modified in Figure 24, Blocks Unprotect Flowchart and Pseudo Code. Figure 23, Block Protect Flowchart and Pseudo Code, clarified. Blocks Temporary Unprotect feature of Reset/Power Down pin no longer available.

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