M30L0R8000T0ZAQT

M30L0R8000T0 STMICROELECTRONICS | Alldatasheet

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256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst)

Figure 1. Package

M30L0R8000T0, M30L0R8000B0 SUMMARY DESCRIPTION The M30L0R8000T0 and M30L0R8000B0 are 256 Mbit (16 Mbit x16) non-volatile Flash memories that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7V to 2.0V V DD supply for the circuitry and a 1.7V to 2.0V VDDQ supply for the Input/Out- put pins. An optional 9V VPP power supply is pro- vided to speed up factory programming. The device features an asymmetrical block archi- tecture and is based on a multi-level cell technolo- gy. The M30L0R8000x0 has an array of 259 blocks, and is divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 KWords, and one parameter bank containing 4 pa- rameter blocks of 16 KWords and 15 main blocks of 64 KWords. The Multiple Bank Architecture allows Dual Oper- ations, while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2., and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M30L0R8000T0, and at the bottom for the M30L0R8000B0. Each block can be erased separately. Erase can be suspended, in order to perform a program or read operation in any other block, and then re- sumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD . There is a Buffer Enhanced Factory programming command avail- able to speed up programming. Program and erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the tim- ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC stan- dards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at fre- quencies of up to 54MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switch- es to the Automatic Standby mode. In this condi- tion the power consumption is reduced to the standby value and the outputs are still driven. The M30L0R8000x0 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any acciden- tal programming or erasure. There is an additional hardware protection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at power- up. The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protec- tion Register and the other for the 16 One-Time- Programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 64 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 5., shows the Pro- tection Register Memory Map. The M30L0R8000x0 is offered in a Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch package. In addition to the standard version, the packages are also available in Lead-free version, in compli- ance with JEDEC Std J-STD-020B, the ST ECO- PACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free solder- ing processes. The devices are supplied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. TFBGA88 Package Connections (Top view through package)

Table 2. Bank Architecture Figure 4. Memory Map

16 Main

64 KWord000000h

64 KWord0F0000h

64 KWordC00000h

64 KWordCF0000h

64 KWordD00000h

64 KWordDF0000h

64 KWordE00000h

64 KWordEF0000h

64 KWordF00000h

64 KWordFE0000h

16 KWordFF0000h

16 KWordFFC000h

4 Parameter

16 KWord000000h

16 KWord00C000h

64 KWord010000h

64 KWord100000h

64 KWord1F0000h

64 KWord200000h

64 KWord2F0000h

64 KWord300000h

64 KWord3F0000h

64 KWordFF0000h

15 Main

M30L0R8000T0, M30L0R8000B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names , for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A23).The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the Program/Erase Con- troller. Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address dur- ing a Bus Read operation or input a command or the data to be programmed during a Bus Write op- eration. Chip Enable (E ). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G ).The Output Enable input controls data outputs during the Bus Read opera- tion of the memory. Write Enable (W).The Write Enable input con- trols the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Write Protect (WP ). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock- Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or un- locked. (refer to Table 16., Lock Status). Reset (RP ). The Reset input provides a hard- ware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is re- duced to the Reset Supply Current I DD2 . Refer to Table 21., DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is re- set. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transi- tion of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to V RPH (refer to Table 22., DC Characteristics - Voltages). Latch Enable (L).Latch Enable latches the ad- dress bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at V IH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Clock (K).The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configura- tion settings) when Latch Enable is at V IL. Clock is ignored during asynchronous read and in write op- erations. Wait (WAIT).Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high imped- ance when Chip Enable is at V IH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in ad- vance. VDD Supply Voltage .VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). V DDQ Supply Voltage.VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently of V DD . VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage.VPP is both a control input and a power supply pin. The two functions are selected by the voltage range ap- plied to the pin. If V PP is kept in a low voltage range (0V to VDDQ ) VPP is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while if VPP is within the VPP1 range these functions are enabled (see Ta- bles 21 and 22, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable un- til the Program/Erase algorithm is completed.

M30L0R8000T0, M30L0R8000B0 VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VDDQ . VSSQ must be connected to VSS Note: Each device in a system should have V DD , VDDQ and VPP decoupled with a 0.1µF ce- ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors should be as close as possible to the pack- age). See Figure 9., AC Measurement Load Cir- cuit. The PCB track widths should be sufficient to carry the required V PP program and erase currents.

dress Latch, Output Disable, Standby and Reset. See Table 3., Bus Operations, for a summary. not affect Bus Write operations. the memory (see Command Interface section). details of the timing requirements. aborted and the memory content is no longer valid. Table 3. Bus Operations

1. L can be tied to VIH if the valid address has been previously latched.
2. WAIT signal polarity is configured using the Set Configuration Register command.

the progress or the result of the operation. invalid combination of commands will be ignored. Table 4. Command Codes until the program or erase operation has finished. The read modes of other banks are not affected. to monitor program or erase operations. edge of the Chip Enable or Output Enable signals. quired to return the bank to Read Array mode.

M30L0R8000T0, M30L0R8000B0 Read Electronic Signature Command The Read Electronic Signature command is used to read the Manufacturer and Device Codes, the Lock Status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent read operations in the same bank will output the Manufacturer Code, the Device Code, the Lock Status of the addressed bank, the Protection Reg- ister, or the Configuration Register (see Table 7.). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Pro- gram operations. Dual operations between the Pa- rameter bank and the Electronic Signature locations are not allowed (see Table 15., Dual Op- eration Limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase op- eration the bank will go into Read Electronic Sig- nature mode. Subsequent Bus Read cycles will output the Electronic Signature data and the Pro- gram/Erase controller will continue to program or erase in the background. The Read Electronic Signature command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Elec- tronic Signature. A Read Array command is re- quired to return the bank to Read Array mode. Read CFI Query Command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank will output the contents of the Com- mon Flash Interface. The Read CFI Query command can be issued at any time, even during program or erase opera- tions. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank will go into Read CFI Query mode. Subse- quent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to program or erase in the background. The Read CFI Query command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asyn- chronous Read and Single Synchronous Read op- erations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 15., Dual Operation Limitations for details). See APPENDIX B., COMMON FLASH INTER- FACE , Tables 36, 37, 38, 39, 40, 42, 43, 44 and 45 for details on the information contained in the Common Flash Interface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Reg- ister command does not affect the read mode of the bank. The error bits in the Status Register do not auto- matically return to ‘0’ when a new command is is- sued. The error bits in the Status Register should be cleared before attempting a new program or erase command. Block Erase Command The Block Erase command is used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. ■ The first bus cycle sets up the Block Erase command. ■ The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Con- firm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read opera- tion within the addressed bank will output the con- tents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank contain- ing the block being erased will only accept the Read Array, Read Status Register, Read Electron- ic Signature, Read CFI Query and the Program/ Erase Suspend command, all other commands will be ignored. The Block Erase operation aborts if Reset, RP goes to VIL. As data integrity cannot be guaran-

M30L0R8000T0, M30L0R8000B0 teed when the Block Erase operation is aborted, the block must be erased again. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 17., Program/Erase Times and Endurance Cy- cles. See APPENDIX C. , Figure 23., Block Erase Flow- chart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Program Command The program command is used to program a sin- gle Word to the memory array. If the block is protected, the program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the Program Command. ■ The first bus cycle sets up the Program command. ■ The second latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, read opera- tions in the bank being programmed output the Status Register content. During a Program operation, the bank containing the Word being programmed will only accept the Read Array, Read Status Register, Read Electron- ic Signature, Read CFI Query and the Program/ Erase Suspend command, all other commands will be ignored. A Read Array command is re- quired to return the bank to Read Array mode. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 17., Program/Erase Times and Endurance Cy- cles. The Program operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the Word must be reprogrammed. See APPENDIX C. , Figure 20., Program Flow- chart and Pseudo Code, for the flowchart for using the Program command. Buffer Program Command The Buffer Program Command makes use of the device’s 32-Word Write Buffer to speed up pro- gramming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program command dra- matically reduces in-system programming time compared to the standard non-buffered Program command. If the block is protected, the Buffer Program oper- ation will abort, the data in the block will not be changed and the Status Register will output the er- ror. Four successive steps are required to issue the Buffer Program command. 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, read operations in the bank will output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of Words to be programmed. Value n is written to the same block address, where n+1 is the number of Words to be programmed. 3. Use n+1 Bus Write cycles to load the address and data for each Word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n. Optimum performance is obtained when the start address corresponds to a 32 Word boundary. If the start address is not aligned to a 32 word boundary, the total programming time is doubled 4. The final Bus Write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program op- eration must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the oper- ation without affecting the data in the memory ar- ray. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not accepted. Clear the Status Register before re-issuing the command. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed in banks not being programmed.

M30L0R8000T0, M30L0R8000B0 See APPENDIX C. , Figure 21., Buffer Program Flowchart and Pseudo Code, for a suggested flow- chart on using the Buffer Program command. Buffer Enhanced Factory Program Command The Buffer Enhanced Factory Program command has been specially developed to speed up pro- gramming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. The use of the Buffer Enhanced Factory Program command requires certain operating conditions: ■ VPP must be set to VPPH ■ VDD must be within operating range ■ Ambient temperature TA must be 30°C ± 10°C ■ The targeted block must be unlocked ■ The start address must be aligned with the start of a 32 Word buffer boundary ■ The address must remain the Start Address throughout programming. Dual operations are not supported during the Buff- er Enhanced Factory Program operation and the command cannot be suspended. If the block is protected, the Buffer Enhanced Fac- tory Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase, Please refer to Table 6., Factory Program Com- mand for detail information. Setup Phase. The Buffer Enhanced Factory Pro- gram command requires two Bus Write cycles to initiate the command. ■ The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. ■ The second Bus Write cycle confirms the command. After the confirm command is issued, read opera- tions output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program opera- tion is terminated. See Status Register section for details on the error. Program and Verify Phase.The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer. The data is stored se- quentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be programmed with FFFFh. Three successive steps are required to issue and execute the Program and Verify Phase of the com- mand. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address that is not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Once the Write Buffer is full, the data is pro- grammed sequentially to the memory array. After the program operation the device auto- matically verifies the data and reprograms if necessary. The Program and Verify phase can be repeated, without re-issuing the command, to program addi- tional 32 Word locations as long as the address re- mains in the same block. 4. Finally, after all Words, or the entire block have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate Program and Verify Phase. Status Register bit SR0 must be checked to deter- mine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed. Exit Phase.Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has exited the Buffer Enhanced Factory Program operation and re- turned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details.

M30L0R8000T0, M30L0R8000B0 For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical program times are given in Table 17. See APPENDIX C. , Figure 27., Buffer Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer En- hanced Factory Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is re- quired to restart the suspended operation. One bus write cycle is required to issue the Pro- gram/Erase Suspend command. Once the Pro- gram/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘1’. The following commands are accepted during Pro- gram/Erase Suspend: – Program/Erase Resume – Read Array (data from erase-suspended block or program-suspended Word is not valid) – Read Status Register – Read Electronic Signature – Read CFI Query. Additionally, if the suspended operation was a Block Erase then the following commands are also accepted: – Clear Status Register – Program (except in erase-suspended block) – Buffer Program (except in erase suspended blocks) – Block Lock – Block Lock-Down – Block Unlock. During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-Down commands. When the Program/ Erase Resume command is issued the operation will complete. It is possible to accumulate multiple suspend oper- ations. For example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase Suspend, the erase operation cannot be re- sumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the sus- pended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corre- sponding data. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/erase is aborted if Reset, RP, goes to VIL. See APPENDIX C. , Figure 22., Program Suspend & Resume Flowchart and Pseudo Code, and Fig- ure 24., Erase Suspend & Resume Flowchart and Pseudo Code , for flowcharts for using the Pro- gram/Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command is used to restart the program or erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the sus- pended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corre- sponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be re- sumed until the program operation has completed. See APPENDIX C. , Figure 22., Program Suspend & Resume Flowchart and Pseudo Code, and Fig- ure 24., Erase Suspend & Resume Flowchart and Pseudo Code , for flowcharts for using the Pro- gram/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to program the user One-Time-Programma- ble (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Fig- ure 5., Protection Register Memory Map. The segments are programmed one Word at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’.

Protection Register Program command. starts the Program/Erase Controller. Memory Map , for details on the Lock bits. to write a new value to the Configuration Register. Configuration Register command. Register data and the confirm command. Set Configuration Register command is issued. address and locks the block. using the Read Electronic Signature command. Table 16. shows the Lock Status after issuing a are cleared by a Block Unlock command. Code , for a flowchart for using the Lock command. address and unlocks the block. using the Read Electronic Signature command. Table 16. shows the protection status after issuing down a locked or unlocked block. by the Block Unlock command.

address and locks-down the block. using the Read Electronic Signature command. ter issuing a Block Lock-Down command. Table 5. Standard Commands PRD = Protection Register Data, CRD = Configuration Register Data.

1. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.
2. Any address within the bank can be used.
3. n+1 is the number of Words to be programmed.

Table 6. Factory Program Command Note: 1. WA = Word Address in targeted bank, BKA= Bank Address, PD = Program Data, BA = Block Address, X = Don’t Care.

1. WA 1 is the Start Address, NOT BA1 = Not Block Address of WA1.
2. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block.
3. Any address within the bank can be used.

Table 7. Electronic Signature Codes Note: CR = Configuration Register, PRLD = Protection Register Lock Data.

Figure 5. Protection Register Memory Map

M30L0R8000T0, M30L0R8000B0 Table 8. Protection Register Locks

Description

Bit 0 preprogrammed to protect Unique Device Number, address 81h to 84h in PR0 Bit 1 protects 64bits of OTP segment, address 85h to 88h in PR0 Bits 2 to 15 reserved Lock 2 89h Bit 0 protects 128bits of OTP segment PR1 Bit 1 protects 128bits of OTP segment PR2 Bit 2 protects 128bits of OTP segment PR3 ---- ---- Bit 13 protects 128bits of OTP segment PR14 Bit 14 protects 128bits of OTP segment PR15 Bit 15 protects 128bits of OTP segment PR16

M30L0R8000T0, M30L0R8000B0 STATUS REGISTER The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more de- tails. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to V IH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during program and erase operations. The various bits convey information about the sta- tus and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on er- rors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 9., Status Register Bits. Refer to Table 9. in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7).The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Pro- gram/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High. Erase Suspend Status Bit (SR6).The Erase Suspend Status bit indicates that an erase opera- tion has been suspended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Pro- gram/Erase Resume command. The Erase Suspend Status bit should only be con- sidered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inac- tive). SR6 is set within the Erase Suspend Latency time of the Program/Erase Suspend command be- ing issued therefore the memory may still com- plete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5).The Erase Status bit is used to identify if there was an error during a block or bank erase operation. When the Erase Status bit is High (set to ‘1’), the Program/Erase Control- ler has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Pro- gram/Erase Controller Status bit is High (Program/ Erase Controller inactive). Once set High, the Erase Status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is is- sued, otherwise the new command will appear to fail. Program Status Bit (SR4).The Program Status bit is used to identify if there was an error during a program operation. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Pro- gram/Erase Controller inactive). When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the Word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already pro- grammed bit while V PP = VPPH will also set the Program Status bit High. If VPP is different from VPPH , SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the Program Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail. V PP Status Bit (SR3).The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an oper- ation. When the VPP Status bit is Low (set to ‘0’), the volt- age on the VPP pin was sampled at a valid voltage. when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK , the memory is protected and pro- gram and erase operations cannot be performed.

M30L0R8000T0, M30L0R8000B0 Once set High, the VPP Status bit must be set Low by a Clear Status Register command or a hard- ware reset before a new program or erase com- mand is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2).The Pro- gram Suspend Status bit indicates that a program operation has been suspended in the addressed block. The Program Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Pro- gram/Erase Resume command. SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command be- ing issued therefore the memory may still com- plete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1).The Block Protection Status bit is used to identify if a Pro- gram or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to ‘1’), a program or erase operation has been at- tempted on a locked block. Once set High, the Block Protection Status bit must be set Low by a Clear Status Register com- mand or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail. Bank Write/Multiple Word Program Status Bit (SR0).The Bank Write Status bit indicates wheth- er the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new Word to be programmed to the memory array. The Bank Write Status bit should only be consid- ered valid when the Program/Erase Controller Sta- tus SR7 is Low (set to ‘0’). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to ‘0’), the addressed bank is executing a program or erase operation. When the Program/Erase Con- troller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode if Mul- tiple Word Program Status bit is Low (set to ‘0’), the device is ready for the next Word, if the Multi- ple Word Program Status bit is High (set to ‘1’) the device is not ready for the next Word. For further details on how to use the Status Regis- ter, see the Flowcharts and Pseudo codes provid- ed in APPENDIX C.

Table 9. Status Register Bits Note: Logic level '1' is High, '0' is Low.

synchronous burst configurations. is set to ’0’, read operations are synchronous. ’1’ for asynchronous access. tency and Data Output Configuration Example.). Table 10. shows how to set the X-Latency param- read the Flash memory in Synchronous mode. Table 10. X-Latency Settings valid or a WAIT state must be inserted. to ‘1’ the Wait signal is active High. two clock cycles during synchronous mode. is valid for two clock cycles. ■ tKQV is the clock to data valid time. when WAIT is de-asserted, Data is Valid. dresses read during Synchronous Burst Reads. ory outputs from sequential addresses only.

M30L0R8000T0, M30L0R8000B0 chronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the rising edge of the Clock is the active edge. Wrap Burst Bit (CR3) The Wrap Burst bit, CR3, is used to select be- tween wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the burst read does not wrap. Burst length Bits (CR2-CR0) The Burst Length bits are used to set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 Words no- wrap, depending on the starting address, the de- vice asserts the WAIT signal to indicate that a de- lay is necessary before the data is output. If the starting address is aligned to an 8 Word boundary no WAIT states are needed and the WAIT output is not asserted. If the starting address is not aligned to the 8 Word boundary, WAIT will be asserted when the burst sequence crosses the first 16 Word boundary to indicate that the device needs an internal delay to read the successive Words in the array. WAIT will be asserted only once during a continu- ous burst access. See also Table 12., Burst Type Definition. CR14, CR5 and CR4 are reserved for future use.

Table 11. Configuration Register Note: 1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.

0 Synchronous Read

1 Asynchronous Read (Default at power-on)

0 WAIT is active Low

1 WAIT is active high (default)

0 Data held for one clock cycle

1 Data held for two clock cycles (default)

0 WAIT is active during WAIT state

1 WAIT is active one data cycle before WAIT state (default)1

0 Reserved

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge (default)

1 No Wrap (default)

111 Continuous (default)

Table 12. Burst Type Definition

4 Words 8 Words 16 Words

Figure 6. X-Latency and Data Output Configuration Example Note: 1. The settings shown are X-latency = 4, Data Output held for one clock cycle.

Figure 7. Wait Configuration Example

M30L0R8000T0, M30L0R8000B0 READ MODES Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchro- nous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). All banks support both asynchronous and synchro- nous read operations. Asynchronous Read Mode In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corre- sponding to the address latched, that is the mem- ory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Reg- ister must be set to ‘1’ for asynchronous opera- tions. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Ac- cess Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. In Asynchronous Read mode a Page of data is in- ternally read and stored in a Page Buffer. The Page has a size of 8 Words and is addressed by address inputs A0, A1 and A2. The first read operation within the Page has a longer access time (t AVQV , Random access time), subsequent reads within the same Page have much shorter access times (tAVQV1 , Page access time). If the Page changes then the normal, longer timings apply again. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always de-asserted. See Table 23., Asynchronous Read AC Charac- teristics, Figure 10., Asynchronous Random Ac- cess Read AC Waveforms , and Figure 11., Asynchronous Page Read AC Waveforms, for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is out- put in bursts synchronized with the clock. It is pos- sible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read opera- tions, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchro- nous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are con- figured in the Configuration Register. A burst sequence starts at the first clock edge (ris- ing or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of Words to be output during a Syn- chronous Burst Read operation can be configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cy- cles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word bound- ary (Wrap) or overcome the boundary (No Wrap). The WAIT signal may be asserted to indicate to the system that an output delay will occur. This de- lay will depend on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word burst. It is only de-asserted when output data are valid. In Continuous Burst Read mode a WAIT state will oc- cur when crossing the first 16 Word boundary. If the starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Config- uration Register. See Table 24., Synchronous Read AC Character- istics, and Figure 12., Synchronous Burst Read AC Waveforms , for details.

M30L0R8000T0, M30L0R8000B0 Synchronous Burst Read Suspend. A Syn- chronous Burst Read operation can be suspend- ed, freeing the data bus for other higher priority devices. It can be suspended during the initial ac- cess latency time (before data is output) in which case the initial latency time can be reduced to ze- ro, or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previous- ly latched internal data is retained. A burst se- quence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspend- ed when Chip Enable, E , is Low and the current address has been latched (on a Latch Enable ris- ing edge or on a valid clock edge). The Clock sig- nal is then halted at V IH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT will revert to high-impedance when Output Enable, G, or Chip Enable, E, goes High. See Table 24., Synchronous Read AC Character- istics, and Figure 14., Synchronous Burst Read Suspend AC Waveforms, for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is as- serted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word burst. It is only de- asserted when output data are valid. See Table 24., Synchronous Read AC Character- istics, and Figure 12., Synchronous Burst Read AC Waveforms , for details.

ture memory space are not allowed. Table 15. ture locations and the memory array. ble in other banks and in the same bank. Table 13. Dual Operations Allowed In Other Banks Table 14. Dual Operations Allowed In Same Bank Note: 1. Not allowed in the Word that is being erased or programmed.

1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.

Table 15. Dual Operation Limitations scheme has three levels of protection. only control of block locking. a flowchart for the locking operations. The lock status is represented by DQ0 and DQ1. status and is set by the Lock-Down command. hardware reset or power-down. locked by issuing the Unlock command. not be changed using software commands alone. device is reset or powered-down.

and protection status changes. cluding those in Lock-Down, to the Locked state. is resumed, the erase operation will complete. Table 16. Lock Status in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Table 17. Program/Erase Times and Endurance Cycles

1. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution).
2. Excludes the time needed to execute the command sequence.
3. This is an average value on the entire device.

Table 18. Absolute Maximum Ratings and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

ing on the quoted parameters. Table 19. Operating and AC Measurement Conditions Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit Table 20. Capacitance Note: Sampled only, not 100% tested.

Table 21. DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.

1. VDD Dual Operation current is the sum of read and program or erase currents.

4 Word 16 18 mA

8 Word 18 20 mA

16 Word 23 25 mA

Table 22. DC Characteristics - Voltages

Figure 10. Asynchronous Random Access Read AC Waveforms Note: 1. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.

1. Write Enable, W, is High, WAIT is active Low.

Figure 11. Asynchronous Page Read AC Waveforms VALID ADD. VALID ADD.VALID ADD.VALID ADD.

Table 23. Asynchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .

Figure 12. Synchronous Burst Read AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
3. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.

Figure 13. Single Synchronous Read AC Waveforms Note: 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.

1. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be config-

ured as the active edge. Here, the active edge is the rising one.

Figure 14. Synchronous Burst Read Suspend AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. The CLOCK signal can be held high or low
3. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.

Here, the active edge is the rising one.

Figure 15. Clock input AC Waveform Table 24. Synchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. For other timings please refer to Table 23., Asynchronous Read AC Characteristics.

Figure 16. Write AC Waveforms, Write Enable Controlled

Table 25. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

1. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System
2. Meaningful only if L is always kept low.

Figure 17. Write AC Waveforms, Chip Enable Controlled

Table 26. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.

1. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System

Figure 18. Reset and Power-up AC Waveforms Table 27. Reset and Power-up AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns.

1. Sampled only, not 100% tested.
2. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

Figure 19. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 28. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data

Table 29. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. please contact the ST Sales Office nearest to you.

M30L0R8000T0, M30L0R8000B0 APPENDIX A. BLOCK ADDRESS TABLES The following set of equations can be used to calculate a complete set of block addresses using the infor- mation contained in Tables 30, 31, 32, 33, 34 and 35. To calculate the Block Base Address from the Block Number: First it is necessary to calculate the Bank Number and the Block Number Offset. This can be achieved using the following formulas: Bank_Number = (Block_Number − 3) / 16 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16) If Bank_Number = 0, the Block Base Address can be directly read from Table 30. or Table 33. (Parameter Bank Block Addresses) in the Block Number Offset row. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the Bank Number and the Block Number from the Block Base Address: If the address is in the range of the Parameter Bank, the Bank Number is 0 and the Block Number can be directly read from Table 30. or Table 33. (Parameter Bank Block Addresses), in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below: For the top configuration (M30L0R8000T0): Block_Number = ((NOT address) / 216) + 3 For the bottom configuration (M30L0R8000B0): Block_Number = (address / 216) + 3 For both configurations the Bank Number and the Block Number Offset can be calculated using the fol- lowing formulas: Bank_Number = (Block_Number − 3) / 16 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)

Table 30. M30L0R8000T0 - Parameter Bank Table 31. M30L0R8000T0 - Main Bank Base Table 32. M30L0R8000T0 - Block Addresses in main blocks (Parameter Bank).

00 F 0 0 0 0

10 E 0 0 0 0

20 D 0 0 0 0

30 C 0 0 0 0

40 B 0 0 0 0

50 A 0 0 0 0

Table 33. M30L0R8000B0 - Parameter Bank Table 34. M30L0R8000B0 - Main Bank Base Table 35. M30L0R8000B0 - Block Addresses in main blocks (Parameter Bank).

Table 36. Query Structure Overview detailed in Tables 37, 38, 39 and 40. Query data is always presented on the lowest order data outputs. Table 37. CFI Query Identification String

Table 38. CFI Query System Interface Information

Table 39. Device Geometry Definition

Table 40. Primary Algorithm-Specific Extended Query Table contains less significant byte.

Table 41. Protection Register Information

M30L0R8000T0, M30L0R8000B0 Table 42. Burst Read Information Table 43. Bank and Erase Block Region Information Note: 1. The variable P is a pointer which is defined at CFI offset 015h.

1. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32, 33, 34 and 35 in APPENDIX A.

determine page-mode data output width.

16 Bytes

Synchronous mode read capability configuration 4 Cont. (P+23)h = 12Dh 02h (P+23)h = 12Dh 02h Number of Bank Regions within the device

M30L0R8000T0, M30L0R8000B0 Table 44. Bank and Erase Block Region 1 Information (P+24)h = 12Eh 0Fh (P+24)h = 12Eh 01h Number of identical banks within Bank Region 1 (P+25)h = 12Fh 00h (P+25)h = 12Fh 00h (P+26)h = 130h 11h (P+26)h = 130h 11h Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+27)h = 131h 00h (P+27)h = 131h 00h Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+28)h = 132h 00h (P+28)h = 132h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+29)h = 133h 01h (P+29)h = 133h 02h Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region (2). (P+2A)h = 134h 0Fh (P+2A)h = 134h 03h Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: n×256 = number of bytes in erase block region (P+2B)h = 135h 00h (P+2B)h = 135h 00h (P+2C)h = 136h 00h (P+2C)h = 136h 80h (P+2D)h = 137h 02h (P+2D)h = 137h 00h (P+2E)h = 138h 64h (P+2E)h = 138h 64h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles × 1000(P+2F)h = 139h 00h (P+2F)h = 139h 00h (P+30)h = 13Ah 02h (P+30)h = 13Ah 02h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+31)h = 13Bh 03h (P+31)h = 13Bh 03h Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+32)h = 13Ch 0Eh Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: n×256 = number of bytes in erase block region (P+33)h = 13Dh 00h (P+34)h = 13Eh 00h (P+35)h = 13Fh 02h (P+36)h = 140h 64h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles × 1000(P+37)h = 141h 00h

M30L0R8000T0, M30L0R8000B0 Note: 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32, 33, 34 and 35 in APPENDIX A. Table 45. Bank and Erase Block Region 2 Information (P+32)h = 13Ch 01h (P+3A)h = 144h 0Fh Number of identical banks within bank region 2 (P+33)h = 13Dh 00h (P+3B)h = 145h 00h (P+34)h = 13Eh 11h (P+3C)h = 146h 11h Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+35)h = 13Fh 00h (P+3D)h = 147h 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+36)h = 140h 00h (P+3E)h = 148h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+37)h = 141h 02h (P+3F)h = 149h 01h Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region. (2) (P+38)h = 142h 0Eh (P+40)h = 14Ah 0Fh Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: n×256 = number of bytes in erase block region (P+39)h = 143h 00h (P+41)h = 14Bh 00h (P+3A)h = 144h 00h (P+42)h = 14Ch 00h (P+3B)h = 145h 02h (P+43)h = 14Dh 02h (P+3C)h = 146h 64h (P+44)h = 14Eh 64h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles × 1000(P+3D)h = 147h 00h (P+45)h = 14Fh 00h (P+3E)h = 148h 02h (P+46)h = 150h 02h Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved Flash memory (top) Flash memory (bottom)

M30L0R8000T0, M30L0R8000B0 Note: 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32, 33, 34 and 35 in APPENDIX A. (P+3F)h = 149h 03h (P+47)h = 151h 03h Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined in Table 42.) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+40)h = 14Ah 03h Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: n×256 = number of bytes in erase block region (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h (P+44)h =14Eh 64h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000(P+45)h = 14Fh 00h (P+46)h = 150h 02h Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+47)h = 151h 03h Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined in Table 42.) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+48)h = 152h Feature Space definitions (P+49)h = 153h (P+43)h = 153h Reserved Flash memory (top) Flash memory (bottom)

Figure 20. Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 21. Buffer Program Flowchart and Pseudo Code Note: 1. n + 1 is the number of data being programmed.

1. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to
2. Routine for Error Check by reading SR3, SR4 and SR1.

Figure 22. Program Suspend & Resume Flowchart and Pseudo Code Note: The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.

Figure 23. Block Erase Flowchart and Pseudo Code Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.

1. Any address within the bank can equally be used.

Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code Note: The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.

Figure 25. Locking Operations Flowchart and Pseudo Code Note: 1. Any address within the bank can equally be used.

Figure 26. Protection Register Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 27. Buffer Enhanced Factory Program Flowchart and Pseudo Code

Table 46. Command Interface States - Modify Table, Next State

M30L0R8000T0, M30L0R8000B0 Note: 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Con- troller. 2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data out- put. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. Buffer Program in Erase Suspend Setup Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N not =0) go to Buffer Program Load 2 Buffer Load 1 Buffer Program Load 2 in Erase Suspend (data load) Buffer Load 2 Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Confirm Ready (error) Buffer Program Busy in Erase Suspend Ready (error) Busy Buffer Program Busy in Erase Suspend Buffer Program Suspend in Erase Suspend Buffer Program Busy in Erase Suspend Suspend Buffer Program Suspend in Erase Suspend Buffer Program Busy in Erase Suspend Buffer Program Suspend in Erase Suspend Lock/CR Setup in Erase Suspend Erase Suspend (Lock Error) Erase Suspend Erase Suspend (Lock Error) Buffer EFP Setup Ready (error) BEFP Busy Ready (error) Busy BEFP Busy (6) Current CI State Command Input Read Array(2) (FFh) Program Setup (3,4) (10/40h) Buffer Program (3,4) (E8h) Block Erase, Setup (3,4) (20h) BEFP Setup (80h) Erase Confirm P/E Resume, Block Unlock confirm, BEFP Confirm (3,4) (D0h) Buffer Program, Program/ Erase Suspend (B0h) Read Status Register (70h) Clear status Register (5) (50h) Read Electronic Signature, Read CFI Query (90h, 98h)

Table 47. Command Interface States - Modify Table, Next Output

1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Con-
2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data out-
3. The two cycle command should be issued to the same bank address.
4. If the P/E.C. is active, both cycles are ignored.

Table 48. Command Interface States - Lock Table, Next State troller, WA0 = Address in a block different from first BEFP address.

1. If the P/E.C. is active, both cycles are ignored.
2. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
3. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other

commands are treated as data.

1. Illegal commands are those not defined in the command set.
2. if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load).
3. if N=0 go to Buffer Program Confirm in Erase Suspend. Else (N ≠ 0) go to Buffer Program Load 2 in Erase Suspend.

Table 49. Command Interface States - Lock Table, Next Output

1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Con-

troller, WA0 = Address in a block different from first BEFP address.

1. If the P/E.C. is active, both cycles are ignored.
2. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
3. Illegal commands are those not defined in the command set.

M30L0R8000T0, M30L0R8000B0

REVISION HISTORY

Table 50. Document Revision History 24-Nov-2003 0.1 First Issue. Buffer and Program command renamed Buffer Program. and IDD1 (for f=66MHz) added in Table 21., DC Characteristics - Currents. 0.8mm pitch, Package Mechanical Data. APPENDIX A., BLOCK ADDRESS TABLES updated. Table 39., Device Geometry Definition. Note 2 to Tables 43, 44 and 45 clarified. Lead-free packages are compliant with the ST ECOPACK specification. Table 11., Configuration Register modified. AC waveforms simplified. C., FLOWCHARTS AND PSEUDO CODES revised. 70ns speed class removed, operating frequency 66MHz removed. Daisy chain information removed. VPP is 12V tolerant (VPP max changed in Table 18., Absolute Maximum Ratings). AC Characteristics, Chip Enable Controlled. Device changed from PRELIMINARY DATA TO full Datasheet. tWHQV AC parameter removed throughout the document. Program commands in the COMMAND INTERFACE section. Wait at Boundary table replaced by X-Latency Bits (CR13-CR11), page 27. Figure 6., X-Latency and Data Output Configuration Example modified.

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