M30C221F3-XXXFP

M30221 RENESAS | Alldatasheet

Document overview

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDescription

Description

The M30221 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. The M30221 group has LCD controller/driver. M30221 group is packaged in a 120-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are ca- pable of executing instructions at high speed.

Features

2.7 to 5.5V (f(XIN)=7MHz with software one-wait) interrupt sources; 7 levels(including key input interrupt) 7, shared with NMI pin) 2, 3 and 4 duty 4 common outputs 40 segment outputs built-in charge pump (built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Camera, Home appliances, Portable equipment, Audio, office equipment, etc. Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDescription Pin Configuration Figures 1.1.1 show the pin configurations (top view). PIN CONFIGURATION (top view) Package: 120P6R-A Figure 1.1.1. Pin configuration for the M30221 group (top view) "7$$ 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( $0. $0. $0. $0. "744 73&' 1%" 1"%53(%" 065 065 9%4$- /PUF 90657449*/ 7$$ 9$0659$*/ $/7 065 9%4%" /PUF $-, 5Y% 3Y% */5 065 */5 3&4&5 1 /.* */5 */5 */5 $54 354 1$,065 15#*/ 15"065 15"*/ 1$-, 15#*/ 15#*/ 15#*/ 1$54354 1*/5 15"*/*/5 15"065*/5 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 1,* 4&( 4&( 4&( 4&( 4&( 7$$744 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 4&( 14&( 14&( M30221MX-XXXFP Note. N channel open-drain output.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDescription Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns (f(X IN)=10MHz Memory ROM 24 Kbytes capacity RAM 1.5 Kbytes I/O port P0 to P13 (except P77) 8 bits x 4, 2 bits x 1, 6 bits x 3, 7 bits x 2 5 bits x 1, 4 bits x 3 Input port P7 7 1 bit x 1 Output port SEG2 to SEG15 2 bits x 7 Multifunction TA0 to TA7 16 bits x 8 timer TB0 to TB5 16 bits x 6 Real time port outputs 8 bits x 3 lines,6 bits x 1 lines Serial I/O UART0 , UART2 (UART or clock synchronous) x 2 A-D converter 10 bits x 7 channels D-A converter 8 bits x 2 channels DMAC 2 channel(trigger:24 sources) LCD COM0 to COM3 4 lines SEG2 to SEG47 40 lines (26 lines are shared with I/O ports) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 24 internal and 8 external sources, 4 software sources Clock generating circuit 2 built-in clock generation circuits (built-in feedbackresistor, and external ceramic or quartz oscillator) Supply voltage 4.0 to 5.5V (f(X IN)=10MHz) 2.7 to 5.5V (f(XIN)=7MHz with software one-wait) Power consumption 18 mW (Vcc=3.3V, f(X IN)=7MHz with software one-wait) I/O withstand voltage (P0 to P13) 5 V Output current P1 to P9,P13 5 mA P0, P10 to P12 0.1mA("H" output), 2.5mA("L" output) Device configuration CMOS silicon gate Package 120-pin plastic mold QFP Table 1.1.1. Performance outline of M30221 group Performance Outline Table 1.1.1 is performance outline of M30221 group. I/O char- acteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description VCC , VSS CNV SS XIN XOUT AV CC AV SS VREF P00 to P07 P10 to P17 P30 to P35 P41, P42, P46, P47 Signal name Power supply input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P3 I/O port P4 Supply 2.7 to 5.5 V to the V CC pin. Supply 0 V to the VSS pin. Function Connect it to the VSS pin. A “L” on this input resets the microcomputer. This pin is a reference voltage input for the A-D converter. Pin name I/O Analog power supply input RESET I/O port P5 I/O port P6 P50 to P53, P56, P57 P60 to P63 P20 to P27 I/O port P2 I I I O I I/O I/O I/O I/O I/O I/O I/O XCIN XCOUT Clock input Clock output I O These pins are provided for the sub clock generating circuit.Connect a ceramic resonator or crystal between the XCIN and the XCOUT pins. To use an externally derived clock, input it to the XCIN pin and leave the XCOUT open. These pins are provided for the main clock generating. circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT open. This pin is a power supply input for the A-D converter. Connect it to VCC. This pin is a power supply input for the A-D converter. Connect it to VSS. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. Pins in this port also use as LCD segment output and real time port output. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as input pins for the key input interrupt function and real time port output. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as input pins for the key input interrupt function and real time port output. This is a 6-bit I/O port equivalent to P0. P3 0 to P33 also function as input pins for the key input interrupt function. This is a 4-bit I/O port equivalent to P0. The P41 pin is shared with timer A0 input. The P42 pin is shared with timer A1 output. The P46 pin is shared with timer A3 output and INT4. The P47 pin is shared with timer A3 input and INT4. This is a 6-bit I/O port equivalent to P0. The P50, P51, P52, and P53 pins are shared with timerB0, B1, B2, and B3 input, respectively. The P56 pin is shared with INT3. The P57 pin is shared with CKOUT output. This is an 4-bit I/O port equivalent to P0. The P60 pin is shared with CTS0 and RTS0. The P61, P62, and P63 pins are shared with CLK0, RxD0, and TxD0, respectively.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Signal name FunctionPin name I/O I/O I/O I/O I/O port P7 I/O port P8 I/O port P9 I/O port P10 P70 to P76 P80 to P82, P84, P86 P90 to P96 P100 to P103 This is an 7-bit I/O port equivalent to P0. Pins in this port also function as A-D converter input pins. This is an 4-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD. P77 I This is an 2-bit I/O port equivalent to P0. P130 pins in this port also function as D-A converter output pins or start trigger for A-D input pins. P131 pins in this port also function as D-A converter output pins. I/OI/O port P11P110 to P117 This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD. I/OI/O port P13P13 0, P131 OSegment outputSEG 2 to SEG 15 Pins in this port function as SEG output for LCD drive circuit. OCommon output COM 0 to COM 3 Power supply input for LCD drive circuit.Power supply input for LCD V L1 to VL3 Pins in this port function as common output for LCD drive circuit. Step-up condenser connect port C 1, C2 Pins in this port function as external pin for LCD step-up condenser. Connect a condenser between C 1 and C2. I/OI/O port P12P120 to P125 This is an 6-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD and real time port output. P70 to P76 are I/O ports equivalent to P0 (P70 and P71 are N channel open-drain output). The P70, P71, and P72 pins are shared with TxD2, RxD2, and CLK 2, respectively. The P73 is shared with CTS2 and RTS2. The P74, P75 and P76 pins are shared with INT0, INT1 and INT2, respectively. P77 is an input-only port that also functions for NMI. This is a 5-bit I/O port equivalent to P0. The P80 pin is shared with timer A4 output and INT5 input . The P81 pin is shared with timer A4 input and INT5 input. The P82 pin is shared with timer A5 output. The P84 pin is shared with timer A6 output. The P86 pin is shared with timer A7 output. I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R0 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R1 (Note) R2 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 R3 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A0(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A1(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 FB (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 Data registers Address registers Frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 H L Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG Note: These registers consist of two register banks. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines C D Z S B O I UIPL Figure 1.5.1. Central processing unit register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config- ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

• Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. Figure 1.5.2. Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Flag register (FLG) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines C D Z S B O I UIPL b0 b15

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.6.3. Device's internal status after a reset is cleared(1) The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. 0100 1 000 000 0 0 0 0 1 0016 0016 000 0 0016 0016 000 0 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 0 0? 000 000? 000? 0 0 ? 0000 0 0 0 ? 0000 0 000 0 00 0 000? 000? 000? 000? 000? 00 000? 00 000? 00 000? ?000 ?000 ?000 0000 0 000 0016 0016 0016 ?0000 0 ?0000 0 0 000 0 00 0 000 0 00 0 00 00 0 0 00 0 0 ?0 0 000 0 ?0 0 000 0 ?0 0 000 0 0 0000 0016 0016(26)UART0 receive interrupt control register (005216)••• (1)Processor mode register 0 (0004 16)••• (2)Processor mode register 1 (0005 16)••• (3)System clock control register 0 (0006 16)••• (4)System clock control register 1 (0007 16)••• (5)Address match interrupt enable register (000916)••• (6)Protect register (000A 16)••• (7)Watchdog timer control register (000F 16)••• (8)Address match interrupt register 0 (001016)••• (001116)••• (001216)••• (9)Address match interrupt register 1 (001416)••• (001516)••• (001616)••• (10)DMA0 control register (002C 16)••• (11)DMA1 control register (003C 16)••• (12)INT3 interrupt control register (0044 16)••• (13)Timer B5 interrupt control register (004516)••• (14)Timer B4 interrupt control register (004616)••• (15)Timer B3 interrupt control register (004716)••• (16)Timer A7 interrupt control register (004816)••• (17)Timer A6 interrupt control register (004916)••• (18)Timer A5 interrupt control register (004A16)••• (19)DMA0 interrupt control register (004B 16)••• (20)DMA1 interrupt control register (004C 16)••• (21)Key input interrupt control register (004D16)••• (22)A-D conversion interrupt control register (004E16)••• (23)UART2 transmit interrupt control register (004F16)••• (24)UART2 receive interrupt control register (005016)••• (25)UART0 transmit interrupt control register (005116)••• (56)UART2 transmit/receive mode register (037816)••• (27)Timer A0 interrupt control register (005516)••• (28)Timer A1 interrupt control register (005616)••• (29)Timer A2 interrupt control register (005716)••• (30)Timer A3 interrupt control register (005816)••• (31)Timer A4 interrupt control register (005916)••• (32)Timer B0 interrupt control register (005A16)••• (33)Timer B1 interrupt control register (005B16)••• (34)Timer B2 interrupt control register (005C16)••• (35)INT0 interrupt control register (005D 16)••• (36)INT1 interrupt control register (005E 16)••• (37)INT2 interrupt control register (005F 16)••• (38)LCD mode register (0120 16)••• (39)Segment output enable register (0122 16)••• (40)Key input mode register (0126 16)••• (41)Count start flag 1 (0340 16)••• (42)One-shot start flag 1 (0342 16)••• (43)Trigger select flag 1 (0343 16)••• (44)Up-down flag 1 (0344 16)••• (45)Timer A5 mode register (0356 16)••• (46)Timer A6 mode register (0357 16)••• (47)Timer A7 mode register (0358 16)••• (48)Timer B3 mode register (035B 16)••• (49)Timer B4 mode register (035C 16)••• (50)Timer B5 mode register (035D 16)••• (51)Interrupt cause select register 0 (035E16)••• (52)Interrupt cause select register 1 (035F16)••• (55)UART2 special mode register (0377 16)••• 0 11 00 00 0 (53)Clock division counter control register (036016)••• 0 0016(54)UART2 special mode register 2 (0376 16)••• x : Nothing is mapped to this bit ? : Undefined 0016 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.6.4. Device's internal status after a reset is cleared(2) 000 ? ?? 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0000000 000000 0016 (83)Port P0 direction register (84)Port P1 direction register (85)Port P2 direction register (86)Port P3 direction register (87)Port P4 direction register (88)Port P5 direction register (89)Port P6 direction register (90)Port P7 direction register (91)Port P8 direction register (92)Port P9 direction register (93)Port P10 direction register (94)Port P11 direction register 000016 000016 000016 0000016 000016 000016 000016 000016 0016 000 0016 (108)Flag register (FLG) (95)Port P12 direction register (96)Port P13 direction register (97)Pull-up control register 0 (98)Pull-up control register 1 (99)Pull-up control register 2 (100)Real time port control register (101)Data registers (R0/R1/R2/R3) (102)Address registers (A0/A1) (103)Frame base register (FB) (104)Interrupt table register (INTB) (105)User stack pointer (USP) (106)Interrupt stack pointer (ISP) (107)Static base register (SB) 0016 11000 0 00 00011 1 10 (03E216)· · · (03E316)· · · (03E616)· · · (03E716)· · · (03EA16)· · · (03EB16)· · · (03EE16)· · · (03EF16)· · · (03F216)· · · (03F316)· · · (03F616)· · · (03F716)· · · (03FA16)· · · (03FB16)· · · (03FC16)· · · (03FD16)· · · (03FE16)· · · (03FF16)· · ·

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• · ·
• · · (57)UART2 transmit/receive control register 0 (58)UART2 transmit/receive control register 1 (59)Count start flag 0 (60) Clock prescaler reset flag (61)One-shot start flag 0 (62)Trigger select flag 0 (63)Up-down flag 0 (64)Timer A0 mode register (65)Timer A1 mode register (66)Timer A2 mode register (82) D-A control register (67)Timer A3 mode register (68)Timer A4 mode register (69)Timer B0 mode register (70)Timer B1 mode register (71)Timer B2 mode register (72)UART0 transmit/receive mode register (73)UART0 transmit/receive control register 0 (74)UART0 transmit/receive control register 1 (75)UART transmit/receive control register 2 (76)Flash memory control register (Note) (77)DMA0 cause select register (78)DMA1 cause select register (80)A-D control register 0 (81)A-D control register 1 (79)A-D control register 2 (037C16)· · · (037D16)· · · (038016)· · · (038116)· · · (038216)· · · (038316)· · · (038416)· · · (039616)· · · (039716)· · · (039816)· · · (039916)· · · (039A16)· · · (039B16)· · · (039C16)· · · (039D16)· · · (03A016)· · · (03A416)· · · (03A516)· · · (03B016)· · · (03B416)· · · (03B816)· · · (03BA16)· · · (03D416)· · · (03D616)· · · (03D716)· · · (03DC16)· · · 0016 00000 0 01 01000 0 00 0016 0016 0016 0016 0016 0016 0016 0016 0016 x : Nothing is mapped to this bit ? : Undefined 0 00 0 0 0 0 0 ?00 0 0 0 0 ?00 0 0 0 0 ?00 0 0 0 00 010000 00 000100 000 The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note : This register is only exist in flash memory version. 00 0 0 0 00 01 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.7.1. Location of peripheral unit control registers (1) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C 16 010D 16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 012016 012116 012216 012316 012416 012516 012616 INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer B2 interrupt control register (TB2IC) Timer A1 interrupt control register (TA1IC) Timer A3 interrupt control register (TA3IC) UART0 transmit interrupt control register (S0TIC) INT2 interrupt control register (INT2IC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Timer A0 interrupt control register (TA0IC) Timer A2 interrupt control register (TA2IC) Timer A4 interrupt control register (TA4IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) INT3 interrupt control register (INT3IC) INT4 interrupt control register (INT4IC) INT5 interrupt control register (INT5IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) Timer A7 interrupt control register (TA7IC) Timer A6 interrupt control register (TA6IC) Timer A5 interrupt control register (TA5IC) DMA0 source pointer (SAR0) DMA0 destination pointer (DAR0) DMA0 transfer counter (TCR0) DMA0 control register (DM0CON) DMA1 source pointer (SAR1) DMA1 destination pointer (DAR1) DMA1 transfer counter (TCR1) DMA1 control register (DM1CON) LCD RAM0(LRAM0) LCD RAM1(LRAM1) LCD RAM2(LRAM2) LCD RAM3(LRAM3) LCD RAM4(LRAM4) LCD RAM5(LRAM5) LCD RAM6(LRAM6) LCD RAM7(LRAM7) LCD RAM8(LRAM8) LCD RAM9(LRAM9) LCD RAM12(LRAM12) LCD RAM13(LRAM13) LCD RAM14(LRAM14) LCD RAM15(LRAM15) LCD RAM16(LRAM16) LCD RAM17(LRAM17) LCD RAM18(LRAM18) LCD RAM20(LRAM20) LCD RAM21(LRAM21) LCD RAM22(LRAM22) LCD RAM23(LRAM23) DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) LCD mode register (LCDM) Segment output enable register (SEG) Key input mode register (KUPM) LCD frame frequency counter (LCDTIM) Bus collision detection interrupt control register (BCNIC) Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.7.2. Location of peripheral unit control registers (2) 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C 16 034D 16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C 16 035D 16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C 16 036D 16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C 16 037D 16 037E16 037F16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 UART0 transmit/receive mode register (U0MR) UART0 transmit buffer register (U0TB) UART0 receive buffer register (U0RB) Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Count start flag 0 (TABSR0) One-shot start flag 0 (ONSF0) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Up-down flag 0 (UDF0) Timer A3 register (TA3) Timer A4 register (TA4) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Trigger select register 0 (TRGSR0) UART0 bit rate generator (U0BRG) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART transmit/receive control register 2 (UCON) Clock prescaler reset flag (CPSRF) Count start flag 1 (TABSR1) Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register(TB5MR) Timer A5 register (TA5) Timer A6 register (TA6) Timer A7 register (TA7) One-shot start flag 1 (ONSF1) Trigger select register 1 (TRGSR1) Up-down flag 1(UDF1) Timer A5 mode register (TA5MR) Timer A6 mode register (TA6MR) Timer A7 mode register (TA7MR) UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) Interrupt cause select register 1 (IFSR1) DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL) Clock division counter (CDC) Interrupt cause select register 0 (IFSR0) Clock division counter control register (CDCC) UART2 special mode register 2(U2SMR2) Flash memory control register (FMCR)(Note) Note1 : This register is only exist in flash memory version. Note2 : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.7.3. Location of peripheral unit control registers (3) 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF16 Port P0 register (P0) Port P0 direction register (PD0) Port P1 register (P1) Port P1 direction register (PD1) Port P2 register (P2) Port P2 direction register (PD2) Port P3 register (P3) Port P3 direction register (PD3) Port P4 register (P4) Port P4 direction register (PD4) Port P5 register (P5) Port P5 direction register (PD5) Port P6 register (P6) Port P6 direction register (PD6) Port P7 register (P7) Port P7 direction register (PD7) Port P8 register (P8) Port P8 direction register (PD8) Port P9 register (P9) Port P9 direction register (PD9) Port P10 register (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) A-D control register 2 (ADCON2) Port P11 register (P11) Port P11 direction register (PD11) Port P12 register (P12) Port P12 direction register (PD12) Real time port control register (RTP) Port P13 register (P13) Port P13 direction register (PD13) Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports There are 83 programmable I/O ports: P0 to P13 (excluding P77). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P77 is an input-only port and has no built-in pull-up resistance. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con- verter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. (1) Direction registers These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis- ters corresponds one for one to each I/O pin. Note: There is no direction register bit for P7 (2) Port registers These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. (3) Pull-up control registers The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register. When pull-up is ON for ports P1 and P2, an intermittent pull-up that pulls up the port for only a set period of time, can be performed from the key input mode register. (4) Key input mode register With bits 0 and 1 of this register, it is possible to select both edges or the fall edge of the key input for P1 and P2. Also, with bit 2, it is possible to make the pull-up for a port (P1 or P2), which is set for pull-up using the pull-up control register, automatically connect as an intermittent pull-up. And, using the significant 3 bits, the pull-up resistance can be connected to and disconnected from ports P12 and P13. (5) Real-time port control register The real-time port control register can be used to set the registers of ports P0, P1, P2 and P12 for real- time port output, whereby output is synchronized with timer overflow of timers A0, A1, A5 and A6 in the timer mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.19.1. Programmable I/O ports (1) P10 to P17, P20 to P27 P00 to P07, P120 to P125 Data bus Direction register Port latch Pull-up selected P30 to P33, P41, P47, P50 to P53, P56, P62, P74 to P76, P81 Data bus Direction register Port latch Pull-up selection P34, P35 Port ON/OFF LCD drive timing Port/segment VL1/VSS VL3/VCC Data bus Direction register Port latch Timer A overflow “1” “1” Segment output D CK Q VL3/VCC VL2/VCC Data bus Direction register Port latch Pull-up selection Timer A overflow Intermittent pull-up control “1” D CK Q D CK Q Interface logic level shift circuit Intermittent pull-up control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.19.2. Programmable I/O ports (2) P42, P46, P60, P61, P72, P73, P80, P82, P84, P86 P57, P63 Data bus Direction register Port latch Pull-up selection Output Data bus Direction register Port latch Pull-up selection Output P70, P71 Data bus Direction register Port latch Output Input respective peripheral functions P77 Data bus NMI interrupt input “1” “1” Input respective peripheral functions “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.19.3. Programmable I/O ports (3) P90 to P96 Data bus Direction register Port latch Pull-up selection Analog input P100 to P103, P110 to P117 Port ON/OFF LCD drive timing Port/segment Interface logic level shift circuit Data bus Direction register Port latch “1” Segment output VL1/VSS VL3/VCCVL3/VCC VL2/VCC P130 Data bus Direction register Analog output Pull-up selection Input respective peripheral functions Port latch

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.19.1. Example connection of unused pins in single-chip mode Figure 1.19.13. Example connection of unused pins Port P0 to P13 (except for P77) (Input mode) (Input mode) (Output mode) NMI AV CC AV SS VREF Microcomputer VCC VSS Open VL3 VL2 VL1 CNV SS Open Open Open XCOUT COM 0ʙCOM 3 SEG 2ʙSEG 15 XCIN /PUF*GTFUUJOHUIFTFQJOTJOPVUQVUNPEFBOEPQFOJOHUIFN QPSUTBSFJOJOQVUNPEFVOUJMMTXJUDIFEJOUP PVUQVUNPEFCZVTFPGTPGUXBSFBGUFSSFTFU5IVTUIFWPMUBHFMFWFMTPGUIFQJOTCFDPNFVOTUBCMF BOEUIFSFDBOCFJOTUBODFTJOXIJDIUIFQPXFSTPVSDFDVSSFOUJODSFBTFTXIJMFUIFQPSUTBSFJOJOQVU NPEF*OWJFXPGBOJOTUBODFJOXIJDIUIFDPOUFOUTPGUIFEJSFDUJPOSFHJTUFSTDIBOHFEVFUPB SVOBXBZHFOFSBUFECZOPJTFPSPUIFSDBVTFT TFUUJOHUIFDPOUFOUTPGUIFEJSFDUJPOSFHJTUFST QFSJPEJDBMMZCZVTFPGTPGUXBSFJODSFBTFTQSPHSBNSFMJBCJMJUZ /PUF8JUIFYUFSOBMDMPDLJOQVUUP9*/QJO /PUF0VUQVU-JGQPSU1BOE1BSFTFUUPPVUQVUNPEF1PSU1BOE1BSF/DIBOOFMPQFOESBJO Pin name Connection Ports P0 to P13 (excluding P77) XOUT (Note 2),XCOUT AV SS , VREF AV CC After setting for output mode, leave these pins open; or after setting for input mode, connect every pin to VSS via a resistor.(Note1,Note3) Open Connect to VCC Connect to VSS NMI Connect via resistor to VCC (pull-up) C1, C2 VL1 VL2, VL3 Open Connect to VCC Connect to VSS CNV SS XCIN Connect via resistor to VSS (pull-down) COM 0ʙCOM 3 SEG 2ʙSEG 15 Open Open Connect via resistor to VSS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (timer mode) Usage Precaution Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF 16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF 16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (1) Setting the count start flag to “0” while a count is in progress causes as follows:

• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”. (2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. Timer A (one-shot timer mode) (1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an “H ” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”. Timer A (pulse width modulation mode) Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets “FFFF 16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Stop Mode and Wait Mode A-D Converter (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. Timer B (pulse period/pulse width measurement mode) (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 µs or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A- D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”. (3) When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with peripheral function clock stop bit (CM02) set to "1". (1) Make sure timer Ai for real time port output is set for timer mode, and is set to have “no gate function” using the gate function select bit. (2) Before setting the real time port mode select bit to “1”, temporarily turn off the timer Ai used and write its set value to the timer Ai register. Real time port (1) In case IIC mode select bit (bit 0 of address 037716) is set to "1" with UART2.When setting up port direction P7 (address 03EF16), write immediate values. If you use Read/Modify/Write instructions (BSET,BCLR,AND,OR,etc..) on the P7 direction register, the value of P71 direction register may change to unknown data. (2) MASK ROM version ONRY when IIC mode select bit (bit 0 of address 037716) and the internal/ external select bit (bit 3 of address 037816) are both set to "1". The function of "SCL wait output bit 2 (bit 5 of address 037616)" dose not work. (3) MASK ROM version ONRY when IIC mode select bit (bit 0 of address 037716) and the internal/ external select bit (bit 3 of address 037816) are both set to "1". According to the datasheet, when IICM is set to "1", the port terminal is readable by the CPU even though "1" is assigned to P71 of the direction register. However, the CPU cannot read port P71 data if the P71 direction register is set to "1". Sirial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts (1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. (3) The NMI interrupt
• The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused.
• Do not get either into stop mode with the NMI pin set to “L”. (4) External interrupt
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0".

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts.

• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below in- structions to change the register. Instructions : AND, OR, BCLR, BSET (5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:

Electric characteristics (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.21.1. Absolute maximum ratings Operating ambient temperature Parameter Unit Input voltage RESET, VREF , XIN Analog supply voltage Supply voltage Output voltage V O – 0.3 to Vcc+0.3 – 0.3 to Vcc+0.3 Pd Power dissipation Storage temperature – 0.3 to 6.5 Rated value – 0.3 to 6.5 V V V Condition VI AVcc Vcc Tstg Topr Symbol mW V – 40 to 150 300 – 20 to 85 P30 to P35, P41 ,P42, P46, P47, P00 to P07, P10 to P17, P20 to P27, P41, P42, P46, P47, P50 to P53, P10 to P17, P20 to P27, P30 to P35, Vcc=AVcc Vcc=AVcc P72 to P77, P80 to P82, P84, P86, P90 to P96, P100 to P103, VL1 P130, P131 – 0.3 to VL2 VL2 VL1 to VL3 VL3 VL2 to 6.5 P70, P71, C1, C2 – 0.3 to 6.5 P56, P57, P60 to P63, P72 to P76, P130, P131, XOUT P00 to P07, P100 to P103, P110 to P117, P120 to P125 – 0.3 to VccWhen output port When segment output – 0.3 to VL3 P70, P71 – 0.3 to 6.5 (Mask ROM version CNVss) (flash memory version CNVss) P110 to P117, P120 to P125, Ta = 25°C P50 to P53, P56, P57, P60 to P63, P80 to P82, P84, P86, P90 to P96,

Electric characteristics (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P30 to P35, P4, P5, P6, P70 to P76 and P122 to P127 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P30 to P35, P4, P5, P6, P72 to P76 and P122 to P127 must be 80mA max. The total IOL (peak) for ports P8, P9, P10, P11, P120, P121 and P130 to P132 must be 80mA max. The total IOH (peak) for ports P8, P9, P10, P11, P12 0,P121 and P130 to P132 must be 80mA max. Note 3: Relationship between main clock oscillation frequency and supply voltage. unless otherwise specified) Typ. Max. UnitParameter Vcc Supply voltage Symbol Min. Standard f (XcIN) Subclock oscillation frequency kHz5032.768 V Analog supply voltage VccAVcc V 0Analog supply voltage Analog supply voltageVss AVss 0.8Vcc V V V Vcc 0.2Vcc0 LOW input voltage HIGH input voltage –0.5 LOW peak output current 10.0 f (XIN) Main clock input oscillation frequency MHz IOL (peak) 10VCC =4.0V to 5.5V With wait

5 X VCC

IOH (avg) HIGH average output current IOH (peak) HIGH peak output current IOL (avg) LOW average output current mA mA mA 2.5 P00 to P07, P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P00 to P07, P100 to P103, P110 to P117, P120 to P125 5.0 0VCC =2.7V to 4.0V –10.000 MHz10VCC =4.0V to 5.5V

2.31 X VCC MHz

0VCC =2.7V to 4.0V +0.760 No wait 2.7 5.55.0 P70, P71 0.8Vcc 6.5 P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, –10.0 –0.1 mA –5.0 5.0 (Note 1) (Note 1) (Note 3) P47, P50 to P53, P56, P57, P60 to P63, P72 to P77, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P50 to P53, P56, P57, P60 to P63, P72 to P76, P80 to P82, P84, P86, P90 to P96, P130, P131, P130, P131, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P50 to P53, P56, P57, P60 to P63, P70 to P77, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131, XIN, RESET, CNVSS P00 to P07, P100 to P103, P110 to P117, P120 to P125 P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P50 to P53, P56, P57, P60 to P63, P72 to P76, P80 to P82, P84, P86, P90 to P96, P130, P131, P00 to P07, P100 to P103, P110 to P117, P120 to P125 P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P50 to P53, P56, P57, P60 to P63, P70 to P76, P80 to P82, P84, P86, P90 to P96, P130, P131, P00 to P07, P100 to P103, P110 to P117, P120 to P125 P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P50 to P53, P56, P57, P60 to P63, P70 to P76, P80 to P82, P84, P86, P90 to P96, P130, P131, (Note 2) (Note 2) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 5.5 4.02.7 0.0 3.5 10.0 Main clock input oscillation frequency (No wait) Supply voltage [V] (BCLK: no division) Operating maximum frequency [MH 5 X Vcc–10.000MHz /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 5.54.02.7 0.0 10.0 Main clock input oscillation frequency (With wait) Supply voltage [V] (BCLK: no division) 7.0 2.31 X VCC +0.760MHz Operating maximum frequency [MH

Electric characteristics (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.21.3. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN)=10MH Z unless otherwise specified) VCC = 5V Symbol VOH VOH Feedback resistance XCIN HIGH output voltage HIGH output voltage Feedback resistance XIN P60 to P63, P72 to P76, P80 to P82, P00 to P07, P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P84, P86, P90 to P96, P130, P131 P50 to P53, P56, P57, P60 to P63, P70 to P76, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131 Standard Typ. UnitMeasuring condition V 4.7 INT0 to INT5, ADTRG , CTS0, CLK0, NMI, KI0 to KI15 (Note), KI16 to KI19 Min. TA3 OUT , TA4OUT , TA7OUT , P00 to P07, P10 to P17, P20 to P27, P50 to P53, P56, P57, P60 to P63, Max. 3.0 Parameter IOH = –0.1mA IOH = –5mA P00 to P07, P100 to P103, P110 to P117, P120 to P125 P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P50 to P53, P56, P57, V VOH XOUTHIGH output voltage HIGHPOWER LOWPOWER V3.0 3.0 IOH = –1mA IOH = –0.5mA VOL LOW output voltage V2.0IOL =5mA VOL XOUTLOW output voltage HIGHPOWER LOWPOWER V2.0 2.0 IOH =1mA IOH =0.5mA Hysteresis Hysteresis HIGH input current IIH VT+-VT- VT+-VT- 0.2 0.8 V 0.2 1.8 V 5.0 µA µA RESET TA0IN, TA3IN, TA4IN, TB0IN to TB3IN, VI=5V –5.0 LOW input current IIL VRAM RAM retention voltage When clock is stopped 2.0 V VI=0V VOL XCOUTLOW output voltage HIGHPOWER LOWPOWER VWith no load applied With no load applied VOH XCOUTHIGH output voltage HIGHPOWER LOWPOWER V 1.6 With no load applied With no load applied 3.0 k167.0 Pull-up resistance R PULLUP VI=0V 30.0 50.0 R fXCIN 6.0 M R fXIN 1.0 M IOH = –200µA IOL =200µA 0.45 3.0 Note : Has no effect during intermittent pullup operation. P30 to P35, P41, P42, P46, P47, P70 to P77, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P50 to P53, P56, P57, P60 to P63, P30 to P35, P41, P42, P46, P47, P70 to P77, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P50 to P53, P56, P57, P60 to P63, P30 to P35, P41, P42, P46, P47, P72 to P76, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131,

Electric characteristics (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.21.5. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) VCC = 5V Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Icc Power supply current Square wave, no division When clock is stopped Ta=25 ºC 1.0 µA mA Ta=85 ºC 20.0 When clock is stopped 19.0 38.0f(XIN)=10MHz f(XCIN)=32kHz When a WAIT instruction is executed 4.0 µA I/o pin is no load applied f(XCIN)=32kHz Square wave 90.0 µA VL1 Supply voltage (VL1) When voltage multiplier used V1.3 2.11.7 IL1 Power supply current (VL1) VL1=1.7V,f(LCDCK )=200Hz 6.0 µA3.0 f(XCIN)=32kHz Square wave Mask ROM version Flash memory version 200.0 µA Standard Min. Typ. Max. Resolution Absolute accuracy Bits LSB VREF =V CC Symbol Parameter Measuring condition Unit VREF =VCC = 5V R LADDER tCONV Ladder resistance Conversion time(10bit) Reference voltage Analog input voltage k µs V VIA VREF V 0 VCC VREF 3.3 Conversion time(8bit) µs2.8tCONV tSAMP Sampling time 0.3 µs VREF =VCC Sample & hold function not available Sample & hold function available(10bit)VREF =VCC = 5V LSB±3 Sample & hold function available(8bit)VREF = VCC = 5V ±2 LSB Min. Typ. Max. tsu R O Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Bits k mAIVREF 1.0 1.5 Symbol Parameter Measuring condition Unit 20 10 4 µs (Note) Standard Table 1.21.4. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN)=10MH Z unless otherwise specified) Table 1.21.6. D-A conversion characteristics (referenced to VCC = AVCC =VREF =5V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.

Timing (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.7. External clock input Table 1.21.9. Timer A input (gating input in timer mode) Table 1.21.10. Timer A input (external trigger input in one-shot timer mode) Table 1.21.11. Timer A input (external trigger input in pulse width modulation mode) Table 1.21.12. Timer A input (up/down input in event counter mode) VCC = 5V Max. External clock rise time nstr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol UnitStandard 100 Standard Max. nsTAiIN input LOW pulse widthtw(TAL) Min. ns ns Unit TAiIN input HIGH pulse widthtw(TAH) ParameterSymbol tc(TA) TAiIN input cycle time 100 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 400 200 200 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 200 100 100 Standard Max.Min. ns ns Unit tw(TAH) tw(TAL) Symbol Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 100 Standard Max.Min. ns ns ns Unit ns ns Symbol Parameter TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 2000 1000 1000 400 400 Table 1.21.8. Timer A input (counter input in event counter mode)

Timing (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.13. Timer B input (counter input in event counter mode) Table 1.21.14. Timer B input (pulse period measurement mode) Table 1.21.15. Timer B input (pulse width measurement mode) Table 1.21.16. A-D trigger input Table 1.21.17. Serial I/O Table 1.21.18. External interrupt INTi inputs VCC = 5V Standard Max.Min. TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) ns ns ns tc(TB) tw(TBH) tw(TBL) ParameterSymbol Unit tc(TB) tw(TBL) tw(TBH) ns ns ns TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) Standard Max.Min. ns ns tc(TB) tw(TBH) Symbol Parameter Unit tw(TBL) ns TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width Standard Max.Min. ns ns tc(TB) Symbol Parameter Unit tw(TBL) ns tw(TBH) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Max.Min. ns ns tc(AD) tw(ADL) Symbol Parameter Unit AD TRG input cycle time (trigger able minimum) AD TRG input LOW pulse width 100 200 400 200 200 400 200 200 1000 125 ns ns ns ns ns ns ns Standard Max.Min. ns ns tw(INH) tw(INL) Symbol Parameter Unit INTi input LOW pulse width INTi input HIGH pulse width Standard Max. Min. CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width tc(CK) tw(CKH) tw(CKL) Parameter Symbol Unit td(C-Q) tsu(D-C) th(C-Q) TxDi hold time RxDi input setup time TxDi output delay time th(C-D) RxDi input hold time 250 250 200 100 100

Timing (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.21.1. Port P0 to P13 measurement circuit P10 30pF P11 P12 P13

Timing (VCC = 5V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER tsu(D–C) TAiIN input TAiOUT input During event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input AD TRG input VCC = 5V

Electric characteristics (VCC = 3V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Table 1.21.19. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait) Symbol VOH VOH Feedback resistance XCIN HIGH output voltage HIGH output voltage Feedback resistance XIN P60 to P63, P72 to P76, P80 to P82, P00 to P07, P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P84, P86, P90 to P96, P130, P131 P50 to P53, P56, P57, P60 to P63, P70 to P76, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131 Standard Typ. UnitMeasuring condition INT0 to INT5, ADTRG , CTS0, CLK0, NMI, KI0 to KI15 (Note), KI16 to KI19 Min. TA3 OUT , TA4OUT , TA7OUT , P00 to P07, P10 to P17, P20 to P27, P50 to P53, P56, P57, P60 to P63, Max.Parameter P00 to P07, P100 to P103, P110 to P117, P120 to P125 P10 to P17, P20 to P27, P30 to P35, P41, P42, P46, P47, P50 to P53, P56, P57, VOH XOUTHIGH output voltage HIGHPOWER LOWPOWER VOL LOW output voltage VOL XOUTLOW output voltage HIGHPOWER LOWPOWER Hysteresis Hysteresis HIGH input current IIH VT+-VT- VT+-VT- RESET TA0IN, TA3IN, TA4IN, TB0IN to TB3IN, LOW input current IIL VRAM RAM retention voltage VOL XCOUTLOW output voltage HIGHPOWER LOWPOWER VOH XCOUTHIGH output voltage HIGHPOWER LOWPOWER Pull-up resistance R PULLUP R fXCIN R fXIN Note : Has no effect during intermittent pullup operation. P30 to P35, P41, P42, P46, P47, P70 to P77, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P50 to P53, P56, P57, P60 to P63, P30 to P35, P41, P42, P46, P47, P70 to P77, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P50 to P53, P56, P57, P60 to P63, P30 to P35, P41, P42, P46, P47, P72 to P76, P80 to P82, P84, P86, P90 to P96, P100 to P103, P110 to P117, P120 to P125, P130, P131, V2.0IOH = –20µA IOH = –1mA V V 2.5 2.5 IOH = –0.1mA IOH = –50µA V0.5IOL =1mA V 0.5 0.5 IOH =0.1mA IOH =50µA 0.2 0.8 V 0.2 1.8 V 4.0 µA µA VI=3V –4.0 When clock is stopped 2.0 V VI=0V V With no load applied With no load applied V 1.6 With no load applied With no load applied 3.0 k500.0VI=0V 66.0 120.0 10.0 M 3.0 M 2.5

Electric characteristics (VCC = 3V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Table 1.21.22. D-A conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS = 0V, at Ta = 25oC, f(XIN) = 7MHZ unless otherwise specified) Note : This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent. Table 1.21.21. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait unless otherwise specified) Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Icc Power supply current Square wave, no division When clock is stopped Ta=25 ºC 1.0 µA mA Ta=85 ºC 20.0 When clock is stopped 6.0 15.0f(XIN)=7MHz f(XCIN)=32kHz When a WAIT instruction is executed Oscillation capacity High (Note) 2.8 µA I/o pin is no load applied f(XCIN)=32kHz Square wave 40.0 µA VL1 Supply voltage (VL1) When voltage multiplier used V1.3 2.1 1.7 IL1 Power supply current (VL1) VL1=1.7V,f(LCDCK )=200Hz 6.0 µA3.0 f(XCIN)=32kHz Square wave Mask ROM version Flash memory version 150.0 µA f(XCIN)=32kHz When a WAIT instruction is executed Oscillation capacity Low (Note) 0.9 µA Note: With one timer operated using fC32 . Standard Resolution Absolute accuracy Bits LSB VREF =VCC Symbol Parameter Measuring condition VREF =VCC = 3V, ПAD =fAD /2 R LADDER Ladder resistance Reference voltage Analog input voltage k V VIA VREF V 0 2.7 VCC VREF Conversion time(8bit) µs14.0tCONV VREF =VCC Sample & hold function not available(8bit) Min. Typ. Max. Unit Min. Typ. Max. tsu R O Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Bits k mAIVREF 1.0 1.0 Symbol Parameter Measuring condition Unit 20104 µs (Note) Standard Table 1.21.20. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait)

Timing (VCC = 3V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.21.25. Timer A input (gating input in timer mode) Table 1.21.26. Timer A input (external trigger input in one-shot timer mode) Table 1.21.27. Timer A input (external trigger input in pulse width modulation mode) Table 1.21.28. Timer A input (up/down input in event counter mode) Table 1.21.24. Timer A input (counter input in event counter mode) Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) VCC = 3V Table 1.21.23. External clock input Max. External clock rise time nstr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol UnitStandard 143 Standard Max. nsTAiIN input LOW pulse widthtw(TAL) Min. ns ns Unit TAiIN input HIGH pulse widthtw(TAH) ParameterSymbol tc(TA) TAiIN input cycle time 150 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 600 300 300 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 300 150 150 Standard Max.Min. ns ns Unit tw(TAH) tw(TAL) Symbol Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width 150 150 Standard Max.Min. ns ns ns Unit ns ns Symbol Parameter TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 3000 1500 1500 600 600

Timing (VCC = 3V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) VCC = 3V Table 1.21.29. Timer B input (counter input in event counter mode) Table 1.21.30. Timer B input (pulse period measurement mode) Table 1.21.31. Timer B input (pulse width measurement mode) Table 1.21.32. A-D trigger input Table 1.21.33. Serial I/O Table 1.21.34. External interrupt INTi inputs Standard Max. Min. TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) ns ns ns tc(TB) tw(TBH) tw(TBL) Parameter Symbol Unit tc(TB) tw(TBL) tw(TBH) ns ns ns TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) Standard Max.Min. ns ns tc(TB) tw(TBH) Symbol Parameter Unit tw(TBL) ns TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width Standard Max.Min. ns ns tc(TB) Symbol Parameter Unit tw(TBL) ns tw(TBH) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Max.Min. ns ns tc(AD) tw(ADL) Symbol Parameter Unit AD TRG input cycle time (trigger able minimum) AD TRG input LOW pulse width 150 160 160 300 600 300 300 600 300 300 1500 200 ns ns ns ns ns ns ns Standard Max.Min. ns ns tw(INH) tw(INL) Symbol Parameter Unit INTi input LOW pulse width INTi input HIGH pulse width Standard Max. Min. CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width tc(CK) tw(CKH) tw(CKL) Parameter Symbol Unit td(C-Q) tsu(D-C) th(C-Q) TxDi hold time RxDi input setup time TxDi output delay time th(C-D) RxDi input hold time 380 380 300 150 150 160

Timing (VCC = 3V) Mitsubishi microcomputers M30221 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V tsu(D–C) TAiIN input TAiOUT input During event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input AD TRG input

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M30221 Group Specification REV.D May. First Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2001 MITSUBISHI ELECTRIC CORPORATION