M30853FJFP

Renesas Technology Corp

SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

Manufacturer: Renesas Technology Corp

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M32C/85 Group (M32C/85, M32C/85T) SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 78fo5002,10.luJ12.1.veR REJ03B0046-0121 Rev.1.21 Jul. 01, 2005 1. Overview The M32C/85 group (M32C/85, M32C/85T) microcomputer is a single-chip control unit that utilizes high- performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/85 group (M32C/85, M32C/85T) is available in 144-pin and 100-pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili- ties to process complex instructions by less bytes and execute instructions at higher speed. It includes a multiplier and DMAC adequate for office automation, communication devices and industrial equipments, and other high-speed processing applications.

1.1 Applications

Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc.

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M

1.2 Performance Overview

Tables 1.1 and 1.2 list performance overview of the M32C/85 group (M32C/85, M32C/85T). Table 1.1 M32C/85 Group (M32C/85, M32C/85T) Performance (144-Pin Package) Characteristic Performance M32C/85 M32C/85T CPU Basic Instructions 108 instructions Minimum Instruction Execution Time31.3 ns 31.3 ns (f(BCLK)=32 MHz, VCC1 =4.2 V to 5.5 V) (f(BCLK)=32 MHz, VCC1 =4.2 V to 5.5 V) 41.7 ns (f(BCLK)=24 MHz, VCC1 =3.0 V to 5.5 V) Operating Mode Single-chip mode, Memory expansionSingle-chip mode mode and Microprocessor mode Address Space 16 Mbytes Memory Capacity See Table 1.3 PeripheralI/O Port 123 I/O pins and 1 input pin Function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function or Waveform generating function: 16 bits x 8 channels Communication function (Clock synchronous serial I/O, Clock asyn- chronous serial I/O, HDLC data processing) Serial I/O 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) CAN Module 2 channels Supporting CAN 2.0B specification A/D Converter 10-bit A/D converter: 1 circuit, 34 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 39 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation Stop Detect Function Main clock oscillation stop detect function Voltage Detection Circuit Available (optional) Not available (4) Charact- (f(BCLK)=32 MHz) (f(BCLK)=32 MHz) (3) eristics VCC1 =3.0 V to 5.5 V, VCC2 =3.0 V to VCC1 (f(BCLK)=24 MHz) Power Consumption 28 mA (V CC1 =V CC2 =5 V, 28 mA (V CC1 =VCC2 =5 V, f(BCLK)=32 MHz) f(BCLK)=32 MHz) 22 mA (VCC1 =V CC2 =3.3 V, 10 µA (VCC1 =VCC2 =5 V, f(BCLK)=24 MHz) f(BCLK)=32 kHz, in wait mode) 10µA (VCC1 =V CC2 =5 V, f(BCLK)=32 kHz, in wait mode) Memory Program and Erase Endurance 100 times (all space) Operating Ambient Temperature –20 to 85 oC –40 to 85 oC (T version) –40 to 85oC (optional) Package 144-pin plastic molded LQFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. The supply voltage of M32C/85T (High-reliability version) must be VCC1 =V CC2 . 4. The cold start-up/warm start-up determine function is available only at the user's option. All options are on a request basis.

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Table 1.2 M32C/85 Group (M32C/85, M32C/85T) Performance (100-Pin Package) Characteristic Performance M32C/85 M32C/85T CPU Basic Instructions 108 instructions Minimum Instruction Execution Time31.3 ns 31.3 ns (f(BCLK)=32 MHz, VCC1 =4.2 V to 5.5 V) (f(BCLK)=32 MHz, VCC1 =4.2 V to 5.5 V) 41.7 ns (f(BCLK)=24 MHz, VCC1 =3.0 V to 5.5 V) Operating Mode Single-chip mode, Memory expansionSingle-chip mode mode and Microprocessor mode Address Space 16 Mbytes Memory Capacity See Table 1.3 PeripheralI/O Port 87 I/O pins and 1 input pin Function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function or Waveform generating function: 16 bits x 8 channels Communication function (Clock synchronous serial I/O, Clock asyn- chronous serial I/O, HDLC data processing) Serial I/O 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) CAN Module 2 channels Supporting CAN 2.0B specification A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 39 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation Stop Detect Function Main clock oscillation stop detect function Voltage Detection Circuit Available (optional) Not available (4) Charact- (f(BCLK)=32 MHz) (f(BCLK)=32 MHz) (3) eristics VCC1 =3.0 V to 5.5 V, VCC2 =3.0 V to VCC1 (f(BCLK)=24 MHz) Power Consumption 28 mA (V CC1 =V CC2 =5 V, 28 mA (V CC1 =V CC2 =5 V, f(BCLK)=32 MHz) f(BCLK)=32 MHz) 22 mA (VCC1 =V CC2 =3.3 V, 10 µA (VCC1 =V CC2 =5 V, f(BCLK)=24 MHz) f(BCLK)=32 kHz, in wait mode) 10µA (VCC1 =V CC2 =5 V, f(BCLK)=32 kHz, in wait mode) Memory Program and Erase Endurance 100 times (all space) Operating Ambient Temperature –20 to 85 oC –40 to 85 oC (T version) –40 to 85oC (optional) Package 100-pin plastic molded LQFP/QFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. The supply voltage of M32C/85T (High-reliability version) must be VCC1 =V CC2 . 4. The cold start-up/warm start-up determine function is available only at the user's option. All options are on a request basis.

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M

1.3 Block Diagram

Figure 1.1 shows a block diagram of the M32C/85 group (M32C/85, M32C/85T) microcomputer. Figure 1.1 M32C/85 Group (M32C/85, M32C/85T) Block Diagram Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Port P14 Port P15 Port P11 Port P12 Port P10 Port P9 Port P8 P85 Port P13 R0H R0L R1H R1L FB SB NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. Included in the 144-pin package only. 3. The supply voltage of M32C/85T must be V CC1 =VCC2 . FLG INTB ISP USP PC SVF SVP VCT Multiplier M32C/80 series CPU Core Clock Generation Circuit XIN - XOUT XCIN - XCOUT On-chip Oscillator PLL Frequency Synthesizer A/D Converter: 1 circuit Standard: 10 inputs Maximum: 34 inputs(2) UART/Clock Synchronous Serial I/O: 5 channels CRC Calculation Circuit (CCITT): X16+X12+X5+1 X/Y Converter: 16 bits x 16 bits D/A Converter: 8 bits x 2 channels Peripheral Functions <VCC2 >(3) <VCC1 >(3) <VCC1>(3) ROM RAM Memory <VCC1 >(3) <VCC2 >(3) 78 5 8 8 (Note 1) 8 8 7 888888 8 DMACII DMAC Watchdog Timer (15 bits) CAN Module: 2 channels Intelligent I/O Time Measurement: 8 channels Waveform Generating: 8 channels Communication Functions: Clock Synchronous Serial I/O, UART, HDLC Data Processing Timer (16 bits) Timer A: 5 channels Timer B: 6 channels Three-Phase Motor Control Circuit

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M

1.4 Product Information

Table 1.3 lists the product information. Figure 1.2 shows the product numbering system. Table 1.3 M32C/85 Group (1) (M32C/85) As of July, 2005 rebmuNepyTe pyTegakcaP MOR yticapaC MAR yticapaC skrameR PGJF55803M) A-Q6P441(A-AK4410PQLP K4+K215 K42 yromeMhsalF PGJF35803M) A-Q6P001(A-BK0010PQLP PFJF35803M) A-S6P001(A-BJ0010PQRP PGHF55803M) A-Q6P441(A-AK4410PQLP K4+K483PGHF35803M) A-Q6P001(A-BK0010PQLP PFHF35803M) A-S6P001(A-BJ0010PQRP PGWF55803M) A-Q6P441(A-AK4410PQLP K4+K023PGWF35803M) A-Q6P001(A-BK0010PQLP PFWF35803M) A-S6P001(A-BJ0010PQRP PGXXX-WM55803M) A-Q6P441(A-AK4410PQLP K023M ORksaMPGXXX-WM35803M) A-Q6P001(A-BK0010PQLP PFXXX-WM35803M) A-S6P001(A-BJ0010PQRP Table 1.3 M32C/85 Group (2) (T Version, M32C/85T) As of July, 2005 rebmuNepyTe pyTegakcaP MOR yticapaC MAR yticapaC skrameR JF55803MT P G) A-Q6P441(A-AK4410PQLP K4+K215 K42 yromeMhsalF noisreVT ytilibailer-hgiH( 58 o )noisreVC JF35803MT P G) A-Q6P001(A-BK0010PQLP HF55803MT P G) A-Q6P441(A-AK4410PQLP K4+K483 HF35803MT P G) A-Q6P001(A-BK0010PQLP WF55803MT P G) A-Q6P441(A-AK4410PQLP K4+K023 WF35803MT P G) A-Q6P001(A-BK0010PQLP

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Figure 1.2 Product Numbering System Package Type: FP = Package PRQP0100JB-A (100P6S-A) GP = Package PLQP0100KB-A (100P6Q-A) ROM Capacity: W = 320 Kbytes H = 384 Kbytes J = 512 Kbytes Memory Type: M = Mask ROM Version F = Flash Memory Version M30 85 5 M W -XXX GP M32C/85 Group M16C Family RAM Capacity, Pin Count, etc ROM Number: Omitted in the Flash Memory Version Classification: Blank = General Industrial Use T = T Version

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M CAN1 OUT / SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CAN1WU / CAN1 IN / CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 P146 P145 P144 OUTC1 7 / INPC17 / P143 OUTC1 6 / INPC16 / P142 OUTC1 5 / INPC15 / P141 OUTC1 4 / INPC14 / P140 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 CAN0 IN / CAN1IN / INT1 / P83 CAN0 OUT / CAN1OUT / INT0 / P82 INPC15 / OUTC15 / U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / INPC14 / OUTC14 / CAN0IN / TA3IN / P77 ISTxD0 / INPC13 / OUTC13 / CAN0OUT / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / INPC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (2)INPC1 7 / OUTC17 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 108 107 106 105 104 103 102 101 100 131 132 133 134 135 136 137 138 139 140 141 142 143 144 125 126 127 128 129 130 119 120 121 122 123 124 113 114 115 116 117 118 109 110 111 112 M32C/85 GROUP P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss 0 / A8 ( / D8 ) Vcc2 P120 P121 P122 P123 P124 P31 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 Vss 2 / A18 Vcc2 P43 / A19 D 8 / P10 AN0 7 / D7 / P07 AN06 / D6 / P06 AN05 / D5 / P05 AN04 / D4 / P04 P114 OUTC1 3 / INPC13 / P113 BE1 IN / ISRxD1 / OUTC12 / INPC12 / P112 ISCLK1 / OUTC11 / INPC11 / P111 BE1 OUT / ISTxD1 / OUTC10 / INPC10 / P110 AN03 / D3 / P03 AN02 / D2 / P02 AN01 / D1 / P01 AN00 / D0 / P00 AN15 7 / P157 AN156 / P156 AN155 / P155 AN15 4 / P154 AN153 / P153 ISRxD0 / AN152 / P152 ISCLK0 / AN151 / P151 Vss ISTxD0 / AN150 / P150 Vcc1 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P125 P126 P127 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P130 P131 Vcc2 P132 Vss P13 P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P134 P135 P136 P137 P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 Vss 6 / RxD1 / SCL1 / STxD1 Vcc1 P67 / TxD1 / SDA1 / SRxD1 P70(1, 2) NOTES: 1. P7 0 / TA0OUT / TxD2 / SDA2 / SRxD2 / INPC16 / OUTC16 2. P7 0 and P71 are ports for the N-channel open drain output. 3. The supply voltage of M32C/85T must be VCC1 =V CC2 . <VCC2 > <VCC1 > PLQP0144KA-A (144P6Q-A)

1.5 Pin Assignments and Descriptions

Figures 1.3 to 1.5 show pin assignments (top view). Figure 1.3 Pin Assignment for 144-Pin Package

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M BYTE CNV SS XCIN XCOUT RESET X OUT VSS XIN VCC1 VCC1 VSS P96 P95 P94 P93 P92 P91 P90 P146 P145 P144 P143 P142 P141 P140 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P137 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4/CAN1 OUT CLK4/CAN1 IN/CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CAN0 IN/CAN1 IN CAN0 OUT /CAN1 OUT CAN0 IN CAN0 OUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 INPC1 7/OUTC1 7 INPC1 6/OUTC1 6 INPC1 5/OUTC1 5 INPC1 4/OUTC1 4 INPC1 5/OUTC1 5 ISRxD0 INPC1 4/OUTC1 4/ISCLK0 INPC1 3/OUTC1 3/ISTxD0 INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 INPC1 0/OUTC1 0/ISTxD1/BE1OUT INPC1 7/OUTC1 7 INPC1 6/OUTC1 6 ANEX1 ANEX0 DA1 DA0 Intelligent I/O Pin Bus Control Pin (1)Analog PinInterrupt Pin Pin No. Control Pin Port Timer Pin UART/CAN Pin NOTES: 1. Bus control pins in M32C/85T cannot be used. Table 1.4 Pin Characteristics for 144-Pin Package

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M VSS VCC2 VCC2 VSS VCC2 VSS P136 P135 P134 P57 P56 P55 P54 P133 P132 P131 P130 P53 P52 P51 P50 P127 P126 P125 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P124 P123 P122 P121 P120 P30 P27 P26 P25 Timer Pin UART/CAN Pin AN2 7 AN2 6 AN2 5 RDY ALE HOLD HLDA/ALE CLK OUT /BCLK/ALE RD WRH/BHE WRL/WR CS0/A CS1/A22 CS2/A21 CS3/A20 A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) A8(/D8) A7(/D7) A6(/D6) A5(/D5) Intelligent I/O Pin Bus Control Pin (1)Analog PinInterrupt Pin Pin No. Control Pin Port NOTES: 1. Bus control pins in M32C/85T cannot be used. Table 1.4 Pin Characteristics for 144-Pin Package (Continued)

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS VCC1 AV SS VREF AV CC P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P114 P113 P112 P111 P110 P03 P02 P01 P00 P157 P156 P155 P154 P153 P152 P151 P150 P107 P106 P105 P104 P103 P102 P101 P100 P97 INT5 INT4 INT3 KI KI2 KI1 KI0 Timer Pin RxD4/SCL4/STxD4 AN2 4 AN2 3 AN2 2 AN2 1 AN2 0 AN0 7 AN0 6 AN0 5 AN0 4 AN0 3 AN0 2 AN0 1 AN0 0 AN15 7 AN15 6 AN15 5 AN15 4 AN15 3 AN15 2 AN15 1 AN15 0 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 AD TRG A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Bus Control Pin(1)Analog PinInterrupt Pin Pin No. INPC1 3/OUTC1 3 INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 INPC1 0/OUTC1 0/ISTxD1/BE1OUT ISRxD0 ISCLK0 ISTxD0 Control Pin Port UART/CAN Pin Intelligent I/O Pin NOTES: 1. Bus control pins in M32C/85T cannot be used, Table 1.4 Pin Characteristics for 144-Pin Package (Continued)

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 100 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 CAN0 IN / CAN1IN / INT1 / P83 CAN0 OUT / CAN1OUT / INT0 / P82 OUTC1 5 / INPC15 / U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / OUTC14 / INPC14 / CAN0IN / TA3IN / P77 ISTxD0 / OUTC13 / INPC13 / CAN0OUT / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / SS2 / INPC10 / RTS2 / CTS2 / V / TA1IN / P73 P42 / A18 P43 / A19 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70(1, 4) P71(2, 4) P72 / TA1OUT / V / CLK2 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss 0 / A8 ( / D8 ) Vcc2 P31 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 D 10 / P12 D 9 / P11 D 8 / P10 D 7 / AN07 / P07 D 6 / AN06 / P06 D 5 / AN05 / P05 D 4 / AN04 / P04 D 3 / AN03 / P03 D 2 / AN02 / P02 D 1 / AN01 / P01 D 0 / AN00 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 (3)P96 CAN1WU / CAN1 IN / CLK4 / ANEX0 / P95 NOTES: 1. P7 0 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC16 / INPC16 2. P7 1 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC17 / INPC17 3. P9 6 / ANEX1 / TxD4 / SDA4 / SRxD4 / CAN1OUT 4. P7 0 and P71 are ports for the N-channel open drain output. 5. The supply voltage of M32C/85T must be VCC1 =VCC2 . <VCC2 > <VCC1 > PLQP0100KB-A (100P6Q-A) M32C/85 GROUP Figure 1.4 Pin Assignment for 100-Pin Package

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 100 CAN1 OUT / SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CAN1WU / CAN1 IN / CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 CAN0 IN / CAN1IN / INT1 / P83 CAN0 OUT / CAN1OUT / INT0 / P82 OUTC15 / INPC15 / U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / OUTC14 / INPC14 / CAN0IN / TA3IN / P77 ISTxD0 / OUTC13 / INPC13 / CAN0OUT / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / INPC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (2)OUTC1 7 / INPC17 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 (2)OUTC1 6 / INPC16 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P10 / D8 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss 0 / A8 ( / D8 ) Vcc2 P31 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 P42 / A18 P43 / A19 D 7 / AN07 / P07 D 6 / AN06 / P06 D 5 / AN05 / P05 D 4 / AN04 / P04 D 3 / AN03 / P03 D 2 / AN02 / P02 D 1 / AN01 / P01 D 0 / AN00 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc (1)P97 NOTES: 1. P9 7 / ADTRG / RxD4 / SCL4 / STxD4 2. P70 and P71 are ports for the N-channel open drain output. <VCC2 > <VCC1 > PRQP0100JB-A (100P6S-A) M32C/85 GROUP (M32C/85) Figure 1.5 Pin Assignment for 100-Pin Package

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M BYTE CNV SS XCIN XCOUT RESET X OUT VSS XIN VCC1 P96 P95 P94 P93 P92 P91 P90 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4/CAN1 OUT CLK4/CAN1IN/CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CAN0 IN/CAN1 IN CAN0 OUT /CAN1 OUT CAN0 IN CAN0 OUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 INPC1 5/OUTC1 5 ISRxD0 INPC1 4/OUTC1 4/ISCLK0 INPC1 3/OUTC1 3/ISTxD0 INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 INPC1 0/OUTC1 0/ISTxD1/BE1OUT INPC1 7/OUTC1 7 INPC1 6/OUTC1 6 ANEX1 ANEX0 DA1 DA0 100 RDY ALE HOLD HLDA/ALE CLK OUT /BCLK/ALE RD WRH/BHE WRL/WR CS0/A CS1/A22 CS2/A21 CS3/A20 Package Pin No. FP GP Control Pin Port Timer Pin UART/CAN Pin Intelligent I/O Pin Bus Control Pin (1)Analog Pin Interrupt Pin NOTES: 1. Bus control pins in M32C/85T cannot be used. Table 1.5 Pin Characteristics for 100-Pin Package

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 100 VCC2 VSS AV SS VREF AV CC P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 P100 P97 Timer Pin UART/CAN Pin AN2 7 AN2 6 AN2 5 AN2 4 AN2 3 AN2 2 AN2 1 AN2 0 AN0 7 AN0 6 AN0 5 AN0 4 AN0 3 AN0 2 AN0 1 AN0 0 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 AD TRG A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) A8(/D8) A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Intelligent I/O Pin Bus Control Pin (1)Analog Pin Interrupt Pin INT5 INT4 INT3 KI KI2 KI1 KI0 RxD4/SCL4/STxD4 FP GP Package Pin No. Control Pin Port NOTES: 1. Bus control pins in M32C/85T cannot be used. Table 1.5 Pin Characteristics for 100-Pin Package (Continued)

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Apply 3.0 to 5.5V to both VCC1 and VCC2 pins. Apply 0V to the VSS pin. VCC1 ≥ VCC2 (1, 2) Supplies power to the A/D converter. Connect the AVCC pin to VCC1 and the AVSS pin to VSS The microcomputer is in a reset state when "L" is applied to the RESET pin Switches processor mode. Connect the CNVSS pin to VSS to start up in single-chip mode or to VCC1 to start up in microprocessor mode Switches data bus width in external memory space 3. The data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Set to either. Connect the BYTE pin to VSS to use the microcomputer in single-chip mode Inputs and outputs data (D 0 to D7) while accessing an external memory space with separate bus Inputs and outputs data (D 8 to D15) while accessing an external memory space with 16-bit separate bus Outputs address bits A0 to A22 Outputs inversed address bit A23 Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing while accessing an external memory space with multiplexed bus Inputs and outputs data (D 8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing while accessing an external memory space with 16-bit multiplexed bus Outputs CS0 to CS3 that are chip-select signals specifying an external space Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH can be switched with WR and BHE by program WRL, WRH and RD selected: If external data bus is 16 bits wide, data is written to an even address in external memory space when WRL is held "L". Data is written to an odd address when WRH is held "L". Data is read when RD is held "L". WR, BHE and RD selected: Data is written to external memory space when WR is held "L". Data in an external memory space is read when RD is held "L". An odd address is accessed when BHE is held "L". Select WR, BHE and RD for external 8-bit data bus. ALE is a signal latching the address The microcomputer is placed in a hold state while the HOLD pin is held "L" Outputs an "L" signal while the microcomputer is placed in a hold state Bus is placed in a wait state while the RDY pin is held "L" VCC1, VCC2 VSS AV CC AV SS RESET CNV SS BYTE D 0 to D7 D 8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL / WR WRH / BHE RD ALE HOLD HLDA RDY Power Supply Analog Power Supply Reset Input CNV SS Input to Switch External Data Bus Width(3) Bus Control Pins(3) I I I I I I/O I/O O O I/O I/O O O O I O I VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 Supply Classsfication Symbol I/O Type FunctionVoltage I : Input O : Output I/O : Input and output NOTES: 1. V CC1 is hereinafter referred to as VCC unless otherwise noted. 3. Bus control pins in M32C/85T cannot be used.

1.6 Pin Description

Table 1.6 Pin Description (100-Pin and 144-Pin Packages)

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M XIN XOUT XCIN XCOUT BCLK CLK OUT INT0 to INT2 INT3 to INT5 NMI KI0 to KI3 TA0 OUT to TA4 OUT TA0 IN to TA4 IN TB0 IN to TB5 IN U, U, V, V, ___ W, W CTS0 to CTS4 RTS0 to RTS4 CLK0 to CLK4 RxD0 to RxD4 TxD0 to TxD4 SDA0 to SDA4 SCL0 to SCL4 STxD0 to STxD4 SRxD0 to SRxD4 SS0 to SS4 Main Clock Input Main Clock Output Sub Clock Input Sub Clock Output BCLK Output(1) Clock Output INT Interrupt Input NMI Interrupt Input Key Input Interrupt Timer A Timer B Three-phase Motor Control Timer Output Serial I/O I2C Mode Serial I/O Special Function VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 I O I O O O I I I I/O I I O I O I/O I O I/O O I I I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT . To apply external clock, apply it to XIN and leave XOUT open I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between X CIN and XCOUT . To apply external clock, apply it to XCIN and leave XCOUT open Outputs BCLK signal Outputs the clock having the same frequency as fC , f8 or f32 Input pins for the INT interrupt Input pin for the NMI interrupt Input pins for the key input interrupt I/O pins for the timer A0 to A4 (TA0OUT is a pin for the N-channel open drain output.) Input pins for the timer A0 to A4 Input pins for the timer B0 to B5 Output pins for the three-phase motor control timer Input pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Outputs serial data (TxD2 is a pin for the N-channel open drain output.) Inputs and outputs serial data (SDA2 is a pin for the N-channel open drain output.) Inputs and outputs the transfer clock (SCL2 is a pin for the N-channel open drain output.) Outputs serial data when slave mode is selected (STxD2 is a pin for the N-channel open drain output.) Inputs serial data when slave mode is selected Input pins to control serial I/O special function Supply Classsfication Symbol I/O Type FunctionVoltage I : Input O : Output I/O : Input and output NOTES: 1. Bus control pins in M32C/85T cannot be used. Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M VREF AN 0 to AN7 AN0 0 to AN07 AN2 0 to AN27 AD TRG ANEX0 ANEX1 DA0, DA1 INPC1 0 to INPC13 INPC1 4 to INPC17 OUTC1 0 to OUTC13 OUTC1 4 to OUTC17 ISCLK0 ISCLK1 ISRXD0 ISRXD1 ISTXD0 ISTXD1 BE1 IN BE1 OUT CAN0 IN CAN1 IN CAN0 OUT CAN1 OUT CAN1WU P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P90 to P97 P100 to P107 P80 to P84 P86, P87 P85 Reference Voltage Input A/D Converter D/A Converter Intelligent I/O CAN I/O Ports Input Port VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 /VCC2 (1) VCC1 VCC1 /VCC2 (1) VCC1 VCC1 VCC1 /VCC2 (1) VCC1 VCC1 /VCC2 (1) VCC1 VCC1 /VCC2 (1) VCC1 /VCC2 (1) VCC1 /VCC2 (1) VCC1 VCC2 VCC1 VCC1 VCC1 Applies reference voltage to the A/D converter and D/A converter Analog input pins for the A/D converter Input pin for an external A/D trigger Extended analog input pin for the A/D converter and output pin in external op-amp connection mode Extended analog input pin for the A/D converter Output pin for the D/A converter Input pins for the time measurement function Output pins for the waveform generating function (OUTC1 6 and OUTC1 7 assigned to P70 and P71 are pins for the N-channel open drain output.) Inputs and outputs the clock for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Input pin for the CAN communication function Output pin for the CAN communication function Input pin for the CAN1 wake-up interrupt I/O ports for CMOS. Each port can be programmed for input or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units I/O ports having equivalent functions to P0 (P7 0 and P71 are ports for the N-channel open drain output.) I/O ports having equivalent functions to P0 Shares a pin with NMI. NMI input state can be got by reading P85 Supply Classsfication Symbol I/O Type FunctionVoltage I I I I/O I O I O I/O I O I O I O I I/O I/O I/O I I : Input O : Output I/O : Input and output NOTES: 1. VCC2 is not available in the 100-pin package. VCC1 only available. Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)

Overview 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Supply Classsfication Symbol I/O Type FunctionVoltage AN15 0 to AN157 P11 0 to P114 P12 0 to P127 P13 0 to P137 P14 0 to P146 P15 0 to P157 A/D Converter I/O Ports I I/O I/O VCC1 VCC2 VCC1 Analog input pins for the A/D converter I/O ports having equivalent functions to P0 I/O ports having equivalent functions to P0 I : Input O : Output I/O : Input and output Table 1.6 Pin Description (144-Pin Package only) (Continued)

Page 20 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 2. Central Processing Unit (CPU)

2.1 General Registers

2.1.1 Data Registers (R0, R1, R2 and R3)

R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3.

2.1.2 Address Registers (A0 and A1)

A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith- metic and logic operations.

2.1.3 Static Base Register (SB)

SB is a 24-bit register for SB-relative addressing.

2.1.4 Frame Base Register (FB)

FB is a 24-bit register for FB-relative addressing.

2.1.5 Program Counter (PC)

PC, 24 bits wide, indicates the address of an instruction to be executed.

2.1.6 Interrupt Table Register (INTB)

INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.

2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.

2.1.8 Flag Register (FLG)

FLG is a 16-bit register indicating a CPU state.

2.1.8.1 Carry Flag (C)

The C flag indicates whether carry or borrow has occurred after executing an instruction.

2.1.8.2 Debug Flag (D)

The D flag is for debug only. Set to "0".

2.1.8.3 Zero Flag (Z)

The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".

2.1.8.4 Sign Flag (S)

The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".

Page 21 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 2. Central Processing Unit (CPU)

2.1.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1".

2.1.8.6 Overflow Flag (O)

The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".

2.1.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged.

2.1.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.1.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.1.8.10 Reserved Space

When writing to a reserved space, set to "0". When reading, its content is indeterminate.

2.2 High-Speed Interrupt Registers

Registers associated with the high-speed interrupt are as follows: - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT)

2.3 DMAC-Associated Registers

Registers associated with DMAC are as follows: - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1)

Memory 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 3. Memory Figure 3.1 shows a memory map of the M32C/85 group (M32C/85, M32C/85T). The M32C/85 group (M32C/85, M32C/85T) provides 16-Mbyte address space from addresses 00000016 to FFFFFF 16. The internal ROM is allocated lower addresses beginning with address FFFFFF16. For example, a 64- Kbyte internal ROM is allocated addresses FF000016 to FFFFFF16. The fixed interrupt vectors are allocated addresses FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 000400 16. For example, a 10- Kbyte internal RAM is allocated addresses 00040016 to 002BFF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowledged. SFR, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O, timers, is allocated addresses 000000 16 to 0003FF16. All blank spaces within SFR are reserved and cannot be accessed by users. The special page vectors are allocated addresses FFFE00 16 to FFFFDB16. It is used for the JMPS instruc- tion and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details. In memory expansion mode and microprocessor mode, some spaces are reserved and cannot be ac- cessed by users. SFR Internal RAM Reserved Space External Space(1) BRK Instruction Overflow Undefined Instruction FFFFFF 16 NMI 00000016 00040016 XXXXXX 16 00F00016 00FFFF 16 F0000016 YYYYYY 16 FFFFFF 16 Reserved Space(2) Internal ROM(4) Special Page Vector Table Address Match Watchdog Timer(5) Reset NOTES: 1. In memory expansion and microprocessor modes. 2. In memory expansion mode. This space becomes external space in microprocessor mode. 3. Additional 4-Kbyte space is provided in the flash memory version for storing data. This space can be used in single-chip mode and memory expansion mode. This space becomes reserved space in microprocessor mode. 4. This space can be used in single-chip mode and memory expansion mode. This space becomes external space in microprocessor mode. 5. Watchdog timer interrupt, oscillation stop detection interrupt, and low voltage detection interrupt share vectors. FFFFDC FFFE00 16 Internal ROM(3) (Data space) Internal ROM Capacity

320 Kbytes

384 Kbytes

512 Kbytes

24 Kbytes

Figure 3.1 Memory Map

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 000016 000116 000216 000316 1000 00002(CNVss pin ="L")

000416 Processor Mode Register(1) PM0 0000 00112(CNVss pin ="H")

000516 Processor Mode Register 1 PM1 00 16

000616 System Clock Control Register 0 CM0 0000 1000 2

000716 System Clock Control Register 1 CM1 0010 0000 2

000916 Address Match Interrupt Enable Register AIER 00 16

000A 16 Protect Register PRCR XXXX 0000 2 XXXX 10002(BYTE pin ="L") 000B 16 External Data Bus Width Control Register(2) DS XXXX 00002(BYTE pin ="H") 000C 16 Main Clock Division Register MCD XXX0 1000 2 000D 16 Oscillation Stop Detection Register CM2 00 16 000E 16 Watchdog Timer Start Register WDTS XX 16 000F16 Watchdog Timer Control Register WDC 000X XXXX 2 001016

001116 Address Match Interrupt Register 0 RMAD0 000000 16

001316 Processor Mode Register 2 PM2 00 16

001516 Address Match Interrupt Register 1 RMAD1 000000 16

001716 Voltage Detection Register 2(2) VCR2 0016

001916 Address Match Interrupt Register 2 RMAD2 000000 16

001B 16 Voltage Detection Register 1(2) VCR1 0000 10002 001C 16 001D 16 Address Match Interrupt Register 3 RMAD3 000000 16 001E 16 001F16 002016 002116 002216 002316 002416 002516

002616 PLL Control Register 0 PLC0 0001 X010 2

002716 PLL Control Register 1 PLC1 000X 0000 2

002916 Address Match Interrupt Register 4 RMAD4 000000 16

002D 16 Address Match Interrupt Register 5 RMAD5 000000 16 002E 16 002F16 Low Voltage Detection Interrupt Register(2) D4INT 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The PM01 and PM00 bits in the PM0 register maintain values set before reset, even after software reset or watch- dog timer reset has been performed. 2. These registers in M32C/85T cannot be used. 4. Special Function Registers (SFR)

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 003016 003116 003216 003316 003416 003516 003616 003716 003816

003916 Address Match Interrupt Register 6 RMAD6 00000016

003D 16 Address Match Interrupt Register 7 RMAD7 00000016 003E 16 003F16 004016 004116 004216 004316 004416 004516 004616 004716

004816 External Space Wait Control Register 0(1) EWCR0 X0X0 00112

004916 External Space Wait Control Register 1(1) EWCR1 X0X0 00112

004A 16 External Space Wait Control Register 2(1) EWCR2 X0X0 00112 004B 16 External Space Wait Control Register 3(1) EWCR3 X0X0 00112 004C 16 004D 16 004E 16 004F16 005016 005116 005216 005316 005416

005516 Flash Memory Control Register 1 FMR1 0000 01012

0000 00012(Flash memory version)

005716 Flash Memory Control Register 0 FMR0XXXX XXX0 2(Masked ROM version)

X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. These registers cannot be used in M32C/85T.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 006016 006116 006216 006316 006416 006516 006616 006716

006816 DMA0 Interrupt Control Register DM0IC XXXX X000 2

006916 Timer B5 Interrupt Control Register TB5IC XXXX X000 2

006A 16 DMA2 Interrupt Control Register DM2IC XXXX X000 2 006B 16 UART2 Receive /ACK Interrupt Control Register S2RIC XXXX X000 2 006C 16 Timer A0 Interrupt Control Register TA0IC XXXX X000 2 006D 16 UART3 Receive /ACK Interrupt Control Register S3RIC XXXX X000 2 006E 16 Timer A2 Interrupt Control Register TA2IC XXXX X000 2 006F16 UART4 Receive /ACK Interrupt Control Register S4RIC XXXX X000 2

007016 Timer A4 Interrupt Control Register TA4IC XXXX X000 2

007116 UART0/UART3 Bus Conflict Detect Interrupt Control Register BCN0IC/BCN3IC XXXX X000 2

007216 UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X000 2

007316 A/D0 Conversion Interrupt Control Register AD0IC XXXX X000 2

007416 UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X000 2

Intelligent I/O Interrupt Control Register 0/ IIO0IC/

007516 XXXX X000 2CAN Interrupt 3 Control Register CAN3IC

007616 Timer B1 Interrupt Control Register TB1IC XXXX X000 2

007716 Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X000 2

007816 Timer B3 Interrupt Control Register TB3IC XXXX X000 2

007916 Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X000 2

007A 16 INT5 Interrupt Control Register INT5IC XX00 X000 2 007B 16 007C 16 INT3 Interrupt Control Register INT3IC XX00 X000 2 007D 16 Intelligent I/O Interrupt Control Register 8 IIO8IC XXXX X000 2 007E 16 INT1 Interrupt Control Register INT1IC XX00 X000 2 Intelligent I/O Interrupt Control Register 10/ IIO10IC/ 007F16 XXXX X000 2CAN Interrupt 1 Control Register CAN1IC 008016

008116 CAN Interrupt 2 Control Register CAN2IC XXXX X000 2

008816 DMA1 Interrupt Control Register DM1IC XXXX X000 2

008916 UART2 Transmit /NACK Interrupt Control Register S2TIC XXXX X000 2

008A 16 DMA3 Interrupt Control Register DM3IC XXXX X000 2 008B 16 UART3 Transmit /NACK Interrupt Control Register S3TIC XXXX X000 2 008C 16 Timer A1 Interrupt Control Register TA1IC XXXX X000 2 008D 16 UART4 Transmit /NACK Interrupt Control Register S4TIC XXXX X000 2 008E 16 Timer A3 Interrupt Control Register TA3IC XXXX X000 2 008F16 UART2 Bus Conflict Detect Interrupt Control Register BCN2IC XXXX X000 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET

009016 UART0 Transmit /NACK Interrupt Control Register S0TIC XXXX X000 2

009116 UART1/UART4 Bus Conflict Detect Interrupt Control Register BCN1IC/BCN4IC XXXX X000 2

009216 UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X000 2

009316 Key Input Interrupt Control Register KUPIC XXXX X000 2

009416 Timer B0 Interrupt Control Register TB0IC XXXX X000 2

Intelligent I/O Interrupt Control Register 1/ IIO1IC/

009516 XXXX X000 2CAN Interrupt 4 Control Register CAN4IC

009616 Timer B2 Interrupt Control Register TB2IC XXXX X000 2

009716 Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X000 2

009816 Timer B4 Interrupt Control Register TB4IC XXXX X000 2

009916 CAN Interrupt 5 Control Register CAN5IC XXXX X000 2

009A 16 INT4 Interrupt Control Register INT4IC XX00 X000 2 009B 16 009C 16 INT2 Interrupt Control Register INT2IC XX00 X000 2 Intelligent I/O Interrupt Control Register 9/ IIO9IC/ 009D 16 XXXX X000 2CAN Interrupt 0 Control Register CAN0IC 009E 16 INT0 Interrupt Control Register INT0IC XX00 X000 2 009F16 Exit Priority Control Register RLVL XXXX 0000 2 00A0 16 Interrupt Request Register 0 IIO0IR 0000 000X 2 00A1 16 Interrupt Request Register 1 IIO1IR 0000 000X 2 00A2 16 Interrupt Request Register 2 IIO2IR 0000 000X 2 00A3 16 Interrupt Request Register 3 IIO3IR 0000 000X 2 00A4 16 Interrupt Request Register 4 IIO4IR 0000 000X 2 00A5 16 Interrupt Request Register 5 IIO5IR 0000 000X 2 00A6 16 00A7 16 00A8 16 Interrupt Request Register 8 IIO8IR 0000 000X 2 00A9 16 Interrupt Request Register 9 IIO9IR 0000 000X 2 00AA 16 Interrupt Request Register 10 IIO10IR 0000 000X 2 00AB 16 Interrupt Request Register 11 IIO11IR 0000 000X 2 00AC 16 00AD 16 00AE 16 00AF 16 00B0 16 Interrupt Enable Register 0 IIO0IE 00 16 00B1 16 Interrupt Enable Register 1 IIO1IE 00 16 00B2 16 Interrupt Enable Register 2 IIO2IE 00 16 00B3 16 Interrupt Enable Register 3 IIO3IE 00 16 00B4 16 Interrupt Enable Register 4 IIO4IE 00 16 00B5 16 Interrupt Enable Register 5 IIO5IE 00 16 00B6 16 00B7 16 00B8 16 Interrupt Enable Register 8 IIO8IE 00 16 00B9 16 Interrupt Enable Register 9 IIO9IE 00 16 00BA 16 Interrupt Enable Register 10 IIO10IE 00 16 00BB 16 Interrupt Enable Register 11 IIO11IE 00 16 00BC 16 00BD 16 00BE 16 00BF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 00E0 16 00E1 16 00E2 16 00E3 16 00E4 16 00E5 16 00E6 16 00E7 16 00E8 16 XXXX XXXX 2 SI/O Receive Buffer Register 0 G0RB00E9 16 X000 XXXX 2 00EA 16 Transmit Buffer/Receive Data Register 0 G0TB/G0DR XX 16 00EB 16 00EC 16 Receive Input Register 0 G0RI XX 16 00ED 16 SI/O Communication Mode Register 0 G0MR 00 16 00EE 16 Transmit Output Register 0 G0TO XX 16 00EF 16 SI/O Communication Control Register 0 G0CR 0000 X011 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 00F016 Data Compare Register 00 G0CMP0 XX 16 00F116 Data Compare Register 01 G0CMP1 XX 16 00F216 Data Compare Register 02 G0CMP2 XX 16 00F316 Data Compare Register 03 G0CMP3 XX 16 00F416 Data Mask Register 00 G0MSK0 XX 16 00F516 Data Mask Register 01 G0MSK1 XX 16 00F616 Communication Clock Select Register CCS XXXX 0000 2 00F716 00F816 XX 16 Receive CRC Code Register 0 G0RCRC00F916 XX 16 00FA 16 0016 Transmit CRC Code Register 0 G0TCRC00FB 16 0016 00FC 16 SI/O Extended Mode Register 0 G0EMR 00 16 00FD 16 SI/O Extended Receive Control Register 0 G0ERC 00 16 00FE 16 SI/O Special Communication Interrupt Detect Register 0 G0IRF 00 16 00FF 16 SI/O Extended Transmit Control Register 0 G0ETC 0000 0XXX 2

010016 XX 16

Time Measurement/Waveform Generating Register 10 G1TM0/G1PO0010116 XX 16

010216 XX 16

Time Measurement/Waveform Generating Register 11 G1TM1/G1PO1010316 XX 16

010416 XX 16

Time Measurement/Waveform Generating Register 12 G1TM2/G1PO2010516 XX 16

010616 XX 16

Time Measurement/Waveform Generating Register 13 G1TM3/G1PO3010716 XX 16

010816 XX 16

Time Measurement/Waveform Generating Register 14 G1TM4/G1PO4010916 XX 16 010A 16 XX 16 Time Measurement/Waveform Generating Register 15 G1TM5/G1PO5010B 16 XX 16 010C 16 XX 16 Time Measurement/Waveform Generating Register 16 G1TM6/G1PO6010D 16 XX 16 010E 16 XX 16 Time Measurement/Waveform Generating Register 17 G1TM7/G1PO7010F16 XX 16

011016 Waveform Generating Control Register 10 G1POCR0 0000 X000 2

011116 Waveform Generating Control Register 11 G1POCR1 0X00 X000 2

011216 Waveform Generating Control Register 12 G1POCR2 0X00 X000 2

011316 Waveform Generating Control Register 13 G1POCR3 0X00 X000 2

011416 Waveform Generating Control Register 14 G1POCR4 0X00 X000 2

011516 Waveform Generating Control Register 15 G1POCR5 0X00 X000 2

011616 Waveform Generating Control Register 16 G1POCR6 0X00 X000 2

011716 Waveform Generating Control Register 17 G1POCR7 0X00 X000 2

011816 Time Measurement Control Register 10 G1TMCR0 00 16

011916 Time Measurement Control Register 11 G1TMCR1 00 16

011A 16 Time Measurement Control Register 12 G1TMCR2 00 16 011B 16 Time Measurement Control Register 13 G1TMCR3 00 16 011C 16 Time Measurement Control Register 14 G1TMCR4 00 16 011D 16 Time Measurement Control Register 15 G1TMCR5 00 16 011E 16 Time Measurement Control Register 16 G1TMCR6 00 16 011F16 Time Measurement Control Register 17 G1TMCR7 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET

012016 XX 16

Base Timer Register 1 G1BT012116 XX 16

012216 Base Timer Control Register 10 G1BCR0 00 16

012316 Base Timer Control Register 11 G1BCR1 X000 000X 2

012416 Time Measurement Prescaler Register 16 G1TPR6 00 16

012516 Time Measurement Prescaler Register 17 G1TPR7 00 16

012616 Function Enable Register 1 G1FE 00 16

012716 Function Select Register 1 G1FS 00 16

012816 XXXX XXXX 2

SI/O Receive Buffer Register 1 G1RB012916 X000 XXXX 2 012A 16 Transmit Buffer/Receive Data Register 1 G1TB/G1DR XX 16 012B 16 012C 16 Receive Input Register 1 G1RI XX 16 012D 16 SI/O Communication Mode Register 1 G1MR 00 16 012E 16 Transmit Output Register 1 G1TO XX 16 012F16 SI/O Communication Control Register 1 G1CR 0000 X011 2

013016 Data Compare Register 10 G1CMP0 XX 16

013116 Data Compare Register 11 G1CMP1 XX 16

013216 Data Compare Register 12 G1CMP2 XX 16

013316 Data Compare Register 13 G1CMP3 XX 16

013416 Data Mask Register 10 G1MSK0 XX 16

013516 Data Mask Register 11 G1MSK1 XX 16

013816 XX 16

Receive CRC Code Register 1 G1RCRC013916 XX 16 013A 16 0016 Transmit CRC Code Register 1 G1TCRC013B 16 0016 013C 16 SI/O Extended Mode Register 1 G1EMR 00 16 013D 16 SI/O Extended Receive Control Register 1 G1ERC 00 16 013E 16 SI/O Special Communication Interrupt Detection Register 1 G1IRF 00 16 013F16 SI/O Extended Transmit Control Register 1 G1ETC 0000 0XXX 2 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A 16 014B 16 014C 16 014D 16 014E 16 014F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A 16 015B 16 015C 16 015D 16 015E 16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A 16 016B 16 016C 16 016D 16 016E 16 016F16 017016 017116 017216 017316 017416 017516 017616 017716

017816 Input Function Select Register IPS 00 16

017916 Input Function Select Register A IPSA 00 16

X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 01E0 16 CAN0 Message Slot Buffer 0 Standard ID0 C0SLOT0_0 XX 16 01E1 16 CAN0 Message Slot Buffer 0 Standard ID1 C0SLOT0_1 XX 16 01E2 16 CAN0 Message Slot Buffer 0 Extended ID0 C0SLOT0_2 XX 16 01E3 16 CAN0 Message Slot Buffer 0 Extended ID1 C0SLOT0_3 XX 16 01E4 16 CAN0 Message Slot Buffer 0 Extended ID2 C0SLOT0_4 XX 16 01E5 16 CAN0 Message Slot Buffer 0 Data Length Code C0SLOT0_5 XX 16 01E6 16 CAN0 Message Slot Buffer 0 Data 0 C0SLOT0_6 XX 16 01E7 16 CAN0 Message Slot Buffer 0 Data 1 C0SLOT0_7 XX 16 01E8 16 CAN0 Message Slot Buffer 0 Data 2 C0SLOT0_8 XX 16 01E9 16 CAN0 Message Slot Buffer 0 Data 3 C0SLOT0_9 XX 16 01EA 16 CAN0 Message Slot Buffer 0 Data 4 C0SLOT0_10 XX 16 01EB 16 CAN0 Message Slot Buffer 0 Data 5 C0SLOT0_11 XX 16 01EC 16 CAN0 Message Slot Buffer 0 Data 6 C0SLOT0_12 XX 16 01ED 16 CAN0 Message Slot Buffer 0 Data 7 C0SLOT0_13 XX 16 01EE 16 CAN0 Message Slot Buffer 0 Time Stamp High-Order C0SLOT0_14 XX 16 01EF 16 CAN0 Message Slot Buffer 0 Time Stamp Low-Order C0SLOT0_15 XX 16 01F016 CAN0 Message Slot Buffer 1 Standard ID0 C0SLOT1_0 XX 16 01F116 CAN0 Message Slot Buffer 1 Standard ID1 C0SLOT1_1 XX 16 01F216 CAN0 Message Slot Buffer 1 Extended ID0 C0SLOT1_2 XX 16 01F316 CAN0 Message Slot Buffer 1 Extended ID1 C0SLOT1_3 XX 16 01F416 CAN0 Message Slot Buffer 1 Extended ID2 C0SLOT1_4 XX 16 01F516 CAN0 Message Slot Buffer 1 Data Length Code C0SLOT1_5 XX 16 01F616 CAN0 Message Slot Buffer 1 Data 0 C0SLOT1_6 XX 16 01F716 CAN0 Message Slot Buffer 1 Data 1 C0SLOT1_7 XX 16 01F816 CAN0 Message Slot Buffer 1 Data 2 C0SLOT1_8 XX 16 01F916 CAN0 Message Slot Buffer 1 Data 3 C0SLOT1_9 XX 16 01FA 16 CAN0 Message Slot Buffer 1 Data 4 C0SLOT1_10 XX 16 01FB 16 CAN0 Message Slot Buffer 1 Data 5 C0SLOT1_11 XX 16 01FC 16 CAN0 Message Slot Buffer 1 Data 6 C0SLOT1_12 XX 16 01FD 16 CAN0 Message Slot Buffer 1 Data 7 C0SLOT1_13 XX 16 01FE 16 CAN0 Message Slot Buffer 1 Time Stamp High-Order C0SLOT1_14 XX 16 01FF 16 CAN0 Message Slot Buffer 1 Time Stamp Low-Order C0SLOT1_15 XX 16

020016 XX01 0X01 2(1)

CAN0 Control Register 0 C0CTLR0020116 XXXX 0000 2(1) 020216 0000 00002(1) CAN0 Status Register C0STR020316 X000 0X012(1) 020416 0016(1) CAN0 Extended ID Register C0IDR020516 0016(1) 020616 0000 XXXX 2(1) CAN0 Configuration Register C0CONR020716 0000 00002(1) 020816 0016(1) CAN0 Time Stamp Register C0TSR020916 0016(1) 020A 16 CAN0 Transmit Error Count Register C0TEC 00 16(1) 020B 16 CAN0 Receive Error Count Register C0REC 00 16(1) 020C 16 0016(1) CAN0 Slot Interrupt Status Register C0SISTR020D 16 0016(1) 020E 16 020F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 021016 0016(2) CAN0 Slot Interrupt Mask Register C0SIMKR021116 0016(2) 021216 021316

021416 CAN0 Error Interrupt Mask Register C0EIMKR XXXX X000 2(2)

021516 CAN0 Error Interrupt Status Register C0EISTR XXXX X000 2(2)

021616 CAN0 Error Cause Register C0EFR 00 16(2)

021716 CAN0 Baud Rate Prescaler C0BRP 0000 0001 2(2)

021916 CAN0 Mode Register C0MDR XXXX XX00 2(2)

022016 0016(2) CAN0 Single Shot Control Register C0SSCTLR022116 0016(2) 022216 022316 022416 0016(2) CAN0 Single Shot Status Register C0SSSTR022516 0016(2) 022616 022716

022816 CAN0 Global Mask Register Standard ID0 C0GMR0 XXX0 0000 2(2)

022916 CAN0 Global Mask Register Standard ID1 C0GMR1 XX00 0000 2(2)

022A 16 CAN0 Global Mask Register Extended ID0 C0GMR2 XXXX 0000 2(2) 022B 16 CAN0 Global Mask Register Extended ID1 C0GMR3 00 16(2) 022C 16 CAN0 Global Mask Register Extended ID2 C0GMR4 XX00 0000 2(2) 022D 16 022E 16 022F16 CAN0 Message Slot 0 Control Register / C0MCTL0/ 0000 0000 2(2)

023016 CAN0 Local Mask Register A Standard ID0 C0LMAR0 XXX0 0000 2(2)

CAN0 Message Slot 1 Control Register / C0MCTL1/ 0000 0000 2(2)

023116 CAN0 Local Mask Register A Standard ID1 C0LMAR1 XX00 0000 2(2)

CAN0 Message Slot 2 Control Register / C0MCTL2/ 0000 0000 2(2)

023216 CAN0 Local Mask Register A Extended ID0 C0LMAR2 XXXX 0000 2(2)

CAN0 Message Slot 3 Control Register / C0MCTL3/ 00 16(2)

023316 CAN0 local Mask Register A Extended ID1 C0LMAR3 00 16(2)

CAN0 Message Slot 4 Control Register / C0MCTL4/ 0000 0000 2(2)

023416 CAN0 Local Mask Register A Extended ID2 C0LMAR4 XX00 0000 2(2)

023516 CAN0 Message Slot 5 Control Register C0MCTL5 00 16(2)

023616 CAN0 Message Slot 6 Control Register C0MCTL6 00 16(2)

023716 CAN0 Message Slot 7 Control Register C0MCTL7 00 16(2)

CAN0 Message Slot 8 Control Register / C0MCTL8/ 0000 0000 2(2)

023816 CAN0 Local Mask Register B Standard ID0 C0LMBR0 XXX0 0000 2(2)

CAN0 Message Slot 9 Control Register / C0MCTL9/ 0000 0000 2(2)

023916 CAN0 Local Mask Register B Standard ID1 C0LMBR1 XX00 0000 2(2)

X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET CAN0 Message Slot 10 Control Register / C0MCTL10/ 0000 0000 2(2) 023A 16 CAN0 Local Mask Register B Extended ID0 C0LMBR2 XXXX 0000 2(2) CAN0 Message Slot 11 Control Register / C0MCTL11/ 00 16(2) 023B 16 CAN0 Local Mask Register B Extended ID1 C0LMBR3 00 16(2) CAN0 Message Slot 12 Control Register / C0MCTL12/ 0000 0000 2(2) 023C 16 CAN0 Local Mask Register B Extended ID2 C0LMBR4 XX00 0000 2(2) 023D 16 CAN0 Message Slot 13 Control Register C0MCTL13 00 16(2) 023E 16 CAN0 Message Slot 14 Control Register C0MCTL14 00 16(2) 023F16 CAN0 Message Slot 15 Control Register C0MCTL15 00 16(2)

024016 CAN0 Slot Buffer Select Register C0SBS 00 16(2)

024116 CAN0 Control Register 1 C0CTLR1 X000 00XX 2(2)

024216 CAN0 Sleep Control Register C0SLPR XXXX XXX0 2

024416 0016(2) CAN0 Acceptance Filter Support Register C0AFS024516 0116(2) 024616 024716 024816 024916 024A 16 024B 16 024C 16 024D 16 024E 16 024F16

025016 CAN1 Slot Buffer Select Register C1SBS 00 16(3)

025116 CAN1 Control Register 1 C1CTLR1 X000 00XX 2(3)

025216 CAN1 Sleep Control Register C1SLPR XXXX XXX0 2

025416 0016(3) CAN1 Acceptance Filter Support Register C1AFS025516 0116(3) 025616 025716 025816 025916 025A 16 025B 16 025C 16 025D 16 025E 16 025F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. 3. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET

026016 CAN1 Message Slot Buffer 0 Standard ID0 C1SLOT0_0 XX 16

026116 CAN1 Message Slot Buffer 0 Standard ID1 C1SLOT0_1 XX 16

026216 CAN1 Message Slot Buffer 0 Extended ID0 C1SLOT0_2 XX 16

026316 CAN1 Message Slot Buffer 0 Extended ID1 C1SLOT0_3 XX 16

026416 CAN1 Message Slot Buffer 0 Extended ID2 C1SLOT0_4 XX 16

026516 CAN1 Message Slot Buffer 0 Data Length Code C1SLOT0_5 XX 16

026616 CAN1 Message Slot Buffer 0 Data 0 C1SLOT0_6 XX 16

026716 CAN1 Message Slot Buffer 0 Data 1 C1SLOT0_7 XX 16

026816 CAN1 Message Slot Buffer 0 Data 2 C1SLOT0_8 XX 16

026916 CAN1 Message Slot Buffer 0 Data 3 C1SLOT0_9 XX 16

026A 16 CAN1 Message Slot Buffer 0 Data 4 C1SLOT0_10 XX 16 026B 16 CAN1 Message Slot Buffer 0 Data 5 C1SLOT0_11 XX 16 026C 16 CAN1 Message Slot Buffer 0 Data 6 C1SLOT0_12 XX 16 026D 16 CAN1 Message Slot Buffer 0 Data 7 C1SLOT0_13 XX 16 026E 16 CAN1 Message Slot Buffer 0 Time Stamp High-Order C1SLOT0_14 XX 16 026F16 CAN1 Message Slot Buffer 0 Time Stamp Low-Order C1SLOT0_15 XX 16

027016 CAN1 Message Slot Buffer 1 Standard ID0 C1SLOT1_0 XX 16

027116 CAN1 Message Slot Buffer 1 Standard ID1 C1SLOT1_1 XX 16

027216 CAN1 Message Slot Buffer 1 Extended ID0 C1SLOT1_2 XX 16

027316 CAN1 Message Slot Buffer 1 Extended ID1 C1SLOT1_3 XX 16

027416 CAN1 Message Slot Buffer 1 Extended ID2 C1SLOT1_4 XX 16

027516 CAN1 Message Slot Buffer 1 Data Length Code C1SLOT1_5 XX 16

027616 CAN1 Message Slot Buffer 1 Data 0 C1SLOT1_6 XX 16

027716 CAN1 Message Slot Buffer 1 Data 1 C1SLOT1_7 XX 16

027816 CAN1 Message Slot Buffer 1 Data 2 C1SLOT1_8 XX 16

027916 CAN1 Message Slot Buffer 1 Data 3 C1SLOT1_9 XX 16

027A 16 CAN1 Message Slot Buffer 1 Data 4 C1SLOT1_10 XX 16 027B 16 CAN1 Message Slot Buffer 1 Data 5 C1SLOT1_11 XX 16 027C 16 CAN1 Message Slot Buffer 1 Data 6 C1SLOT1_12 XX 16 027D 16 CAN1 Message Slot Buffer 1 Data 7 C1SLOT1_13 XX 16 027E 16 CAN1 Message Slot Buffer 1 Time Stamp High-Order C1SLOT1_14 XX 16 027F16 CAN1 Message Slot Buffer 1 Time Stamp Low-Order C1SLOT1_15 XX 16

028016 XX01 0X01 2(1)

CAN1 Control Register 0 C1CTLR0028116 XXXX 0000 2(1) 028216 0000 00002(1) CAN1 Status Register C1STR028316 X000 0X012(1) 028416 0016(1) CAN1 Extended ID Register C1IDR028516 0016(1) 028616 0000 XXXX 2(1) CAN1 Configuration Register C1CONR028716 0000 00002(1) 028816 0016(1) CAN1 Time Stamp Register C1TSR028916 0016(1) 028A 16 CAN1 Transmit Error Count Register C1TEC 00 16(1) 028B 16 CAN1 Receive Error Count Register C1REC 00 16(1) 028C 16 0016(1) CAN1 Slot Interrupt Status Register C1SISTR028D 16 0016(1) 028E 16 028F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 029016 0016 CAN1 Slot Interrupt Mask Register C1SIMKR029116 0016 029216 029316

029416 CAN1 Error Interrupt Mask Register C1EIMKR XXXX X000 2(2)

029516 CAN1 Error Interrupt Status Register C1EISTR XXXX X000 2(2)

029616 CAN1 Error Factor Register C1EFR 00 16(2)

029716 CAN1 Baud Rate Prescaler C1BRP 0000 0001 2(2)

029916 CAN1 Mode Register C1MDR XXXX XX00 2(2)

02A0 16 0016(2) CAN1 Single Shot Control Register C1SSCTLR02A1 16 0016(2) 02A2 16 02A3 16 02A4 16 0016(2) CAN1 Single Shot Status Register C1SSSTR02A5 16 0016(2) 02A6 16 02A7 16 02A8 16 CAN1 Global Mask Register Standard ID0 C1GMR0 XXX0 0000 2(2) 02A9 16 CAN1 Global Mask Register Standard ID1 C1GMR1 XX00 0000 2(2) 02AA 16 CAN1 Global Mask Register Extended ID0 C1GMR2 XXXX 0000 2(2) 02AB 16 CAN1 Global Mask Register Extended ID1 C1GMR3 00 16(2) 02AC 16 CAN1 Global Mask Register Extended ID2 C1GMR4 XX00 0000 2(2) 02AD 16 02AE 16 02AF 16 CAN1 Message Slot 0 Control Register / C1MCTL0/ 0000 0000 2(2) 02B0 16 CAN1 Local Mask Register A Standard ID0 C1LMAR0 XXX0 0000 2(2) CAN1 Message Slot 1 Control Register / C1MCTL1/ 0000 0000 2(2) 02B1 16 CAN1 Local Mask Register A Standard ID1 C1LMAR1 XX00 0000 2(2) CAN1 Message Slot 2 Control Register / C1MCTL2/ 0000 0000 2(2) 02B2 16 CAN1 Local Mask Register A Extended ID0 C1LMAR2 XXXX 0000 2(2) CAN1 Message Slot 3 Control Register / C1MCTL3/ 00 16(2) 02B3 16 CAN1 Local Mask Register A Extended ID1 C1LMAR3 00 16(2) CAN1 Message Slot 4 Control Register / C1MCTL4/ 0000 0000 2(2) 02B4 16 CAN1 Local Mask Register A Extended ID2 C1LMAR4 XX00 0000 2(2) 02B5 16 CAN1 Message Slot 5 Control Register C1MCTL5 00 16(2) 02B6 16 CAN1 Message Slot 6 Control Register C1MCTL6 00 16(2) 02B7 16 CAN1 Message Slot 7 Control Register C1MCTL7 00 16(2) CAN1 Message Slot 8 Control Register / C1MCTL8/ 0000 0000 2(2) 02B8 16 CAN1 Local Mask Register B Standard ID0 C1LMBR0 XXX0 0000 2(2) CAN1 Message Slot 9 Control Register / C1MCTL9/ 0000 0000 2(2) 02B9 16 CAN1 Local Mask Register B Standard ID1 C1LMBR1 XX00 0000 2(2) X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C1CTLR1 register switches functions for addresses 02A016 to 02BF16. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET CAN1 Message Slot 10 Control Register / C1MCTL10/ 0000 0000 2(2) 02BA 16 CAN1 Local Mask Register B Extended ID0 C1LMBR2 XXXX 0000 2(2) CAN1 Message Slot 11 Control Register / C1MCTL11/ 00 16(2) 02BB 16 CAN1 Local Mask Register B Extended ID1 C1LMBR3 00 16(2) CAN1 Message Slot 12 Control Register / C1MCTL12/ 0000 0000 2(2) 02BC 16 CAN1 Local Mask Register B Extended ID2 C1LMBR4 XX00 0000 2(2) 02BD 16 CAN1 Message Slot 13 Control Register C1MCTL13 00 16(2) 02BE 16 CAN1 Message Slot 14 Control Register C1MCTL14 00 16(2) 02BF 16 CAN1 Message Slot 15 Control Register C1MCTL15 00 16(2) 02C0 16 XX 16 X0 Register Y0 Register X0R,Y0R02C1 16 XX 16 02C2 16 XX 16 X1 Register Y1 Register X1R,Y1R02C3 16 XX 16 02C4 16 XX 16 X2 Register Y2 Register X2R,Y2R02C5 16 XX 16 02C6 16 XX 16 X3 Register Y3 Register X3R,Y3R02C7 16 XX 16 02C8 16 XX 16 X4 Register Y4 Register X4R,Y4R02C9 16 XX 16 02CA 16 XX 16 X5 Register Y5 Register X5R,Y5R02CB 16 XX 16 02CC 16 XX 16 X6 Register Y6 Register X6R,Y6R02CD 16 XX 16 02CE 16 XX 16 X7 Register Y7 Register X7R,Y7R02CF 16 XX 16 02D0 16 XX 16 X8 Register Y8 Register X8R,Y8R02D1 16 XX 16 02D2 16 XX 16 X9 Register Y9 Register X9R,Y9R02D3 16 XX 16 02D4 16 XX 16 X10 Register Y10 Register X10R,Y10R02D5 16 XX 16 02D6 16 XX 16 X11 Register Y11 Register X11R,Y11R02D7 16 XX 16 02D8 16 XX 16 X12 Register Y12 Register X12R,Y12R02D9 16 XX 16 02DA 16 XX 16 X13 Register Y13 Register X13R,Y13R02DB 16 XX 16 02DC 16 XX 16 X14 Register Y14 Register X14R,Y14R02DD 16 XX 16 02DE 16 XX 16 X15 Register Y15 Register X15R,Y15R02DF 16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C1CTLR1 register switches functions for addresses 02A016 to 02BF16. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and applying the clock to the CAN module. (Note 1)

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 02E0 16 X/Y Control Register XYC XXXX XX00 2 02E1 16 02E2 16 02E3 16 02E4 16 UART1 Special Mode Register 4 U1SMR4 00 16 02E5 16 UART1 Special Mode Register 3 U1SMR3 00 16 02E6 16 UART1 Special Mode Register 2 U1SMR2 00 16 02E7 16 UART1 Special Mode Register U1SMR 00 16 02E8 16 UART1 Transmit/Receive Mode Register U1MR 00 16 02E9 16 UART1 Bit Rate Register U1BRG XX 16 02EA 16 XX 16 UART1 Transmit Buffer Register U1TB02EB 16 XX 16 02EC 16 UART1 Transmit/Receive Control Register 0 U1C0 0000 1000 2 02ED 16 UART1 Transmit/Receive Control Register 1 U1C1 0000 0010 2 02EE 16 XX 16 UART1 Receive Buffer Register U1RB02EF 16 XX 16 02F016 02F116 02F216 02F316 02F416 UART4 Special Mode Register 4 U4SMR4 00 16 02F516 UART4 Special Mode Register 3 U4SMR3 00 16 02F616 UART4 Special Mode Register 2 U4SMR2 00 16 02F716 UART4 Special Mode Register U4SMR 00 16 02F816 UART4 Transmit/Receive Mode Register U4MR 00 16 02F916 UART4 Bit Rate Register U4BRG XX 16 02FA 16 XX 16 UART4 Transmit Buffer Register U4TB02FB 16 XX 16 02FC 16 UART4 Transmit/Receive Control Register 0 U4C0 0000 1000 2 02FD 16 UART4 Transmit/Receive Control Register 1 U4C1 0000 0010 2 02FE 16 XX 16 UART4 Receive Buffer Register U4RB02FF 16 XX 16

030016 Timer B3, B4, B5 Count Start Flag TBSR 000X XXXX 2

030216 XX 16

Timer A1-1 Register TA11030316 XX 16

030416 XX 16

Timer A2-1 Register TA21030516 XX 16

030616 XX 16

Timer A4-1 Register TA41030716 XX 16

030816 Three-Phase PWM Control Register 0 INVC0 00 16

030916 Three-Phase PWM Control Register 1 INVC1 00 16

030A 16 Three-Phase Output Buffer Register 0 IDB0 XX11 1111 2 030B 16 Three-Phase Output Buffer Register 1 IDB1 XX11 1111 2 030C 16 Dead Time Timer DTT XX 16 030D 16 Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XX 16 030E 16 030F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET

031016 XX 16

Timer B3 Register TB3031116 XX 16

031216 XX 16

Timer B4 Register TB4031316 XX 16

031416 XX 16

Timer B5 Register TB5031516 XX 16 031616 031716 031816 031916 031A 16 031B 16 Timer B3 Mode Register TB3MR 00XX 0000 2 031C 16 Timer B4 Mode Register TB4MR 00XX 0000 2 031D 16 Timer B5 Mode Register TB5MR 00XX 0000 2 031E 16 031F16 External Interrupt Request Source Select Register IFSR 00 16 032016 032116 032216 032316

032416 UART3 Special Mode Register 4 U3SMR4 00 16

032516 UART3 Special Mode Register 3 U3SMR3 00 16

032616 UART3 Special Mode Register 2 U3SMR2 00 16

032716 UART3 Special Mode Register U3SMR 00 16

032816 UART3 Transmit/Receive Mode Register U3MR 00 16

032916 UART3 Bit Rate Register U3BRG XX 16

UART3 Transmit Buffer Register U3TB032B 16 XX 16 032C 16 UART3 Transmit/Receive Control Register 0 U3C0 0000 1000 2 032D 16 UART3 Transmit/Receive Control Register 1 U3C1 0000 0010 2 032E 16 XX 16 UART3 Receive Buffer Register U3RB032F16 XX 16 033016 033116 033216 033316

033416 UART2 Special Mode Register 4 U2SMR4 00 16

033516 UART2 Special Mode Register 3 U2SMR3 00 16

033616 UART2 Special Mode Register 2 U2SMR2 00 16

033716 UART2 Special Mode Register U2SMR 00 16

033816 UART2 Transmit/Receive Mode Register U2MR 00 16

033916 UART2 Bit Rate Register U2BRG XX 16

UART2 Transmit Buffer Register U2TB033B 16 XX 16 033C 16 UART2 Transmit/Receive Control Register 0 U2C0 0000 1000 2 033D 16 UART2 Transmit/Receive Control Register 1 U2C1 0000 0010 2 033E 16 XX 16 UART2 Receive Buffer Register U2RB033F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed. Address Register Symbol Value after RESET

034016 Count Start Flag TABSR 00 16

034116 Clock Prescaler Reset Flag CPSRF 0XXX XXXX 2

034216 One-Shot Start Flag ONSF 00 16

034316 Trigger Select Register TRGSR 00 16

034416 Up/Down Flag UDF 00 16

034616 XX 16

Timer A0 Register TA0034716 XX 16

034816 XX 16

Timer A1 Register TA1034916 XX 16 034A 16 XX 16 Timer A2 Register TA2034B 16 XX 16 034C 16 XX 16 Timer A3 Register TA3034D 16 XX 16 034E 16 XX 16 Timer A4 Register TA4034F16 XX 16

035016 XX 16

Timer B0 Register TB0035116 XX 16

035216 XX 16

Timer B1 Register TB1035316 XX 16

035416 XX 16

Timer B2 Register TB2035516 XX 16

035616 Timer A0 Mode Register TA0MR 00 16

035716 Timer A1 Mode Register TA1MR 00 16

035816 Timer A2 Mode Register TA2MR 00 16

035916 Timer A3 Mode Register TA3MR 00 16

035A 16 Timer A4 Mode Register TA4MR 00 16 035B 16 Timer B0 Mode Register TB0MR 00XX 0000 2 035C 16 Timer B1 Mode Register TB1MR 00XX 0000 2 035D 16 Timer B2 Mode Register TB2MR 00XX 0000 2 035E 16 Timer B2 Special Mode Register TB2SC XXXX XXX0 2 035F16 Count Source Prescaler Register(1) TCSPR 0XXX 0000 2 036016 036116 036216 036316

036416 UART0 Special Mode Register 4 U0SMR4 00 16

036516 UART0 Special Mode Register 3 U0SMR3 00 16

036616 UART0 Special Mode Register 2 U0SMR2 00 16

036716 UART0 Special Mode Register U0SMR 00 16

036816 UART0 Transmit/Receive Mode Register U0MR 00 16

036916 UART0 Bit Rate Register U0BRG XX 16

UART0 Transmit Buffer Register U0TB036B 16 XX 16 036C 16 UART0 Transmit/Receive Control Register 0 U0C0 0000 1000 2 036D 16 UART0 Transmit/Receive Control Register 1 U0C1 0000 0010 2 036E 16 XX 16 UART0 Receive Buffer Register U0RB036F16 XX 16

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Address Register Symbol Value after RESET 037016 037116 037216 037316 037416 037516 037616 037716

037816 DMA0 Request Source Select Register DM0SL 0X00 0000 2

037916 DMA1 Request Source Select Register DM1SL 0X00 0000 2

037A 16 DMA2 Request Source Select Register DM2SL 0X00 0000 2 037B 16 DMA3 Request Source Select Register DM3SL 0X00 0000 2 037C 16 XX 16 CRC Data Register CRCD037D 16 XX 16 037E 16 CRC Input Register CRCIN XX 16 037F16

038016 XXXX XXXX 2

A/D0 Register 0 AD00038116 0000 00002

038216 XX 16

A/D0 Register 1 AD01038316 XX 16

038416 XX 16

A/D0 Register 2 AD02038516 XX 16

038616 XX 16

A/D0 Register 3 AD03038716 XX 16

038816 XX 16

A/D0 Register 4 AD04038916 XX 16 038A 16 XX 16 A/D0 Register 5 AD05038B 16 XX 16 038C 16 XX 16 A/D0 Register 6 AD06038D 16 XX 16 038E 16 XX 16 A/D0 Register 7 AD07038F16 XX 16 039016 039116

039216 A/D0 Control Register 4 AD0CON4 XXXX 00XX 2

039416 A/D0 Control Register 2 AD0CON2 XX0X X000 2

039516 A/D0 Control Register 3 AD0CON3 XXXX X000 2

039616 A/D0 Control Register 0 AD0CON0 00 16

039716 A/D0 Control Register 1 AD0CON1 00 16

039816 D/A Register 0 DA0 XX 16

039A 16 D/A Register 1 DA1 XX 16 039B 16 039C 16 D/A Control Register DACON XXXX XX00 2 039D 16 039E 16 039F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M <144-pin package> Address Register Symbol Value after RESET 03A0 16 Function Select Register A8 PS8 X000 0000 2 03A1 16 Function Select Register A9 PS9 00 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 Function Select Register D1 PSD1 X0XX XX00 2 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 Function Select Register C2 PSC2 XXXX X00X 2 03AD 16 Function Select Register C3 PSC3 X0XX XXXX 2 03AE 16 03AF 16 Function Select Register C PSC 00X0 0000 2 03B0 16 Function Select Register A0 PS0 00 16 03B1 16 Function Select Register A1 PS1 00 16 03B2 16 Function Select Register B0 PSL0 00 16 03B3 16 Function Select Register B1 PSL1 00 16 03B4 16 Function Select Register A2 PS2 00X0 0000 2 03B5 16 Function Select Register A3 PS3 00 16 03B6 16 Function Select Register B2 PSL2 00X0 0000 2 03B7 16 Function Select Register B3 PSL3 00 16 03B8 16 03B9 16 Function Select Register A5 PS5 XXX0 0000 2 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 03C0 16 Port P6 Register P6 XX 16 03C1 16 Port P7 Register P7 XX 16 03C2 16 Port P6 Direction Register PD6 00 16 03C3 16 Port P7 Direction Register PD7 00 16 03C4 16 Port P8 Register P8 XX 16 03C5 16 Port P9 Register P9 XX 16 03C6 16 Port P8 Direction Register PD8 00X0 0000 2 03C7 16 Port P9 Direction Register PD9 00 16 03C8 16 Port P10 Register P10 XX 16 03C9 16 Port P11 Register P11 XX 16 03CA 16 Port P10 Direction Register PD10 00 16 03CB 16 Port P11 Direction Register PD11 XXX0 0000 2 03CC 16 Port P12 Register P12 XX 16 03CD 16 Port P13 Register P13 XX 16 03CE 16 Port P12 Direction Register PD12 00 16 03CF 16 Port P13 Direction Register PD13 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M <144-pin package> Address Register Symbol Value after RESET 03D0 16 Port P14 Register P14 XX 16 03D1 16 Port P15 Register P15 XX 16 03D2 16 Port P14 Direction Register PD14 X000 0000 2 03D3 16 Port P15 Direction Register PD15 00 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-Up Control Register 2 PUR2 00 16 03DB 16 Pull-Up Control Register 3 PUR3 00 16 03DC 16 Pull-Up Control Register 4 PUR4 XXXX 0000 2 03DD 16 03DE 16 03DF 16 03E0 16 Port P0 Register P0 XX 16 03E1 16 Port P1 Register P1 XX 16 03E2 16 Port P0 Direction Register PD0 00 16 03E3 16 Port P1 Direction Register PD1 00 16 03E4 16 Port P2 Register P2 XX 16 03E5 16 Port P3 Register P3 XX 16 03E6 16 Port P2 Direction Register PD2 00 16 03E7 16 Port P3 Direction Register PD3 00 16 03E8 16 Port P4 Register P4 XX 16 03E9 16 Port P5 Register P5 XX 16 03EA 16 Port P4 Direction Register PD4 00 16 03EB 16 Port P5 Direction Register PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-Up Control Register 0 PUR0 00 16 03F116 Pull-Up Control Register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register PCR XXXX XXX0 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M <100-pin package> Address Register Symbol Value after RESET 03A0 16 03A1 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 Function Select Register D1 PSD1 X0XX XX00 2 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 Function Select Register C2 PSC2 XXXX X00X 2 03AD 16 Function Select Register C3 PSC3 X0XX XXXX 2 03AE 16 03AF 16 Function Select Register C PSC 00X0 0000 2 03B0 16 Function Select Register A0 PS0 00 16 03B1 16 Function Select Register A1 PS1 00 16 03B2 16 Function Select Register B0 PSL0 00 16 03B3 16 Function Select Register B1 PSL1 00 16 03B4 16 Function Select Register A2 PS2 00X0 0000 2 03B5 16 Function Select Register A3 PS3 00 16 03B6 16 Function Select Register B2 PSL2 00X0 0000 2 03B7 16 Function Select Register B3 PSL3 00 16 03B8 16 03B9 16 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 03C0 16 Port P6 Register P6 XX 16 03C1 16 Port P7 Register P7 XX 16 03C2 16 Port P6 Direction Register PD6 00 16 03C3 16 Port P7 Direction Register PD7 00 16 03C4 16 Port P8 Register P8 XX 16 03C5 16 Port P9 Register P9 XX 16 03C6 16 Port P8 Direction Register PD8 00X0 0000 2 03C7 16 Port P9 Direction Register PD9 00 16 03C8 16 Port P10 Register P10 XX 16 03C9 16 03CA 16 Port P10 Direction Register PD10 00 16 03CB 16 Set default value to "FF16" 03CC 16 03CD 16 03CE 16 Set default value to "FF16" 03CF 16 Set default value to "FF16" X: Indeterminate Blank spaces are reserved. No access is allowed.

Special Function Registers (SFR) 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M <100-pin package> Address Register Symbol Value after RESET 03D0 16 03D1 16 03D2 16 Set default value to "FF16" 03D3 16 Set default value to "FF16" 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-Up Control Register 2 PUR2 00 16 03DB 16 Pull-Up Control Register 3 PUR3 00 16 03DC 16 Set default value to "0016" 03DD 16 03DE 16 03DF 16 03E0 16 Port P0 Register P0 XX 16 03E1 16 Port P1 Register P1 XX 16 03E2 16 Port P0 Direction Register PD0 00 16 03E3 16 Port P1 Direction Register PD1 00 16 03E4 16 Port P2 Register P2 XX 16 03E5 16 Port P3 Register P3 XX 16 03E6 16 Port P2 Direction Register PD2 00 16 03E7 16 Port P3 Direction Register PD3 00 16 03E8 16 Port P4 Register P4 XX 16 03E9 16 Port P5 Register P5 XX 16 03EA 16 Port P4 Direction Register PD4 00 16 03EB 16 Port P5 Direction Register PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-up Control Register 0 PUR0 00 16 03F116 Pull-up Control Register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register PCR XXXX XXX0 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

Page 45 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics

5.1 Electrical Characteristics (M32C/85)

Table 5.1 Absolute Maximum Ratings lobmySr etemaraPn oitidnoCe ulaVt inU V 1CC V, 2CC egatloVylppuSV 1CC VA= CC 0.6ot3.0- V V 2CC egatloVylppuS- V ot3.0- 1CC V VA CC egatloVylppuSgolanAV 1CC VA= CC 0.6ot3.0- V VI egatloVtupnIV NC,TESER SS 6P,ETYB, 0 6P- 7 7P, 2 7P- 7, 8P 0 8P- 7 9P, 0 9P- 7 01P, 0 01P- 7 41P, 0 41P- 6, 51P 0 51P- 7 )1( V, FER X, NI Vot3.0- 1CC 3.0+V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 )1( Vot3.0- 2CC 3.0+ 7P 0 7P, 1 0.6ot3.0- VO egatloVtuptuO6 P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( , X TUO Vot3.0- 1CC 3.0+V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 )1( Vot3.0- 2CC 3.0+ 7P 0 7P, 1 0.6ot3.0- dPn oitapissiDrewoP C°52=rpoT0 05W m rpoT gnitarepO tneibmA erutarepmeT noitarepoUPCgnirud /58ot02- 58ot04- )2( esarednamargorpyromemhsalfgnirud noitarepo 06ot0 gtsTe rutarepmeTegarotS 051ot56-C ° :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1 58ot04-foegnarerutarepmetfi,dtL,.oCselaSygolonhceTsaseneRtcatnoC.2 .deriuqersiC°

Page 46 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M Table 5.2 Recommended Operating Conditions (VCC1 = VCC2 =3.0V to 5.5V at Topr=– 20 to 85oC unless otherwise specified) lobmySr etemaraP dradnatS tinU.niM. pyT. xaM V 1CC V, 2CC V(egatloVylppuS 1CC V 2CC )0 .30 .55 .5V VA CC egatloVylppuSgolanA V 1CC V V SS egatloVylppuS 0V VA SS egatloVylppuSgolanA 0V V HI )"H"(hgiHtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 )4( V8.0 2CC V 2CC V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7,41P 0- 41P 6 51P, 0 51P- 7 )4( X, NI VNC,TESER, SS ETYB, V8.0 1CC V 1CC 7P 0 7P, 1 V8.0 1CC 0.6 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(V 8.0 2CC V 2CC 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( V5.0 2CC V 2CC V LI )"L"(woLtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 )4( 0V 2.0 2CC V 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )4( X, NI VNC,TESER, SS ETYB, 0V 2.0 1CC 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(0 V 2.0 2CC 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( 0V 61.0 2CC I )kaep(HO tuptuOkaeP )"H"(hgiH tnerruC )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01-A m I )gva(HO tuptuOegarevA )"H"(hgiH tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5-A m I )kaep(LO woLtuptuOkaeP tnerruC)"L"( )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01A m I )gva(LO tuptuOegarevA )"L"(woL tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5A m :SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(LO 8P,7P,6P,5P,4P,3Prof 0 8Pot 4 .sselroAm08ebtsum31Pdna21P, IlatoT )kaep(HO .sselroAm04-ebtsum11Pdna,2P,1P,0Prof IlatoT )kaep(HO 8Prof 6 8P, 7 .sselroAm04-ebtsum51Pdna41P,01P,9P, IlatoT )kaep(HO .sselroAm04-ebtsum31Pdna21P,5P,4P,3Prof IlatoT )kaep(HO 8Pdna,7P,6Prof 0 8Pot 4 .sselroAm04-ebtsum .3V HI Vdna LI 8Profecnerefer 7 8Pnehwseilppa 7 .troptupnielbammargorpasadesusi 8PnehwylppatonseodtI 7 Xsadesusi NIC . .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.4

Page 47 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraP dradnatS tinU .niM. pyT. xaM (f KLCB )y cneuqerFkcolCUPCV 1CC V5.5ot2.4=0 2 3z HM V 1CC V5.5ot0.3=0 4 2z HM X(f NI )y cneuqerFtupnIkcolCniaMV 1CC V5.5ot2.4=0 2 3z HM V 1CC V5.5ot0.3=0 4 2z HM X(f NIC )y cneuqerFkcolCbuS 867.230 5z Hk (f gniR ) (ycneuqerFrotallicsOpihc-nOV 1CC V= 2CC 52=rpoT,V0.5=) C° 5.01 2 z HM (f LLP )y cneuqerFkcolCLLPV 1CC V5.5ot2.4=0 12 3z HM V 1CC V5.5ot0.3=0 14 2z HM t )LLP(US rezisehtnySycneuqerFLLPezilibatSotemiTtiaWV 1CC V0.5=5 s m V 1CC V3.3=0 1s m Table 5.2 Recommended Operating Conditions (Continued) (VCC1 =V CC2 =3.0V to 5.5V at Topr=–20 to 85oC unless otherwise specified)

Page 48 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V Table 5.3 Electrical Characteristics (VCC1 =VCC2 =4.2 to 5.5V, VSS =0V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified) lobmySr etemaraPn oitidnoC dradnatS tinU.niM. pyT. xaM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 I HO Am5-= V CC -2 0.2 V CC 2 V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO Am5-= V CC -1 0.2 V CC 1 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 I HO 002-= µA V CC -2 3.0 V CC 2 V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO 002-= µA V CC -1 3.0 V CC 1 X TUO I HO Am1-=0 .3V CC 1 V X TUOC rewoPhgiH deilppadaoloN5 .2V rewoPwoL deilppadaoloN6 .1 V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO 002= µA5 4.0V X TUO I LO Am1=0 .2V X TUOC rewoPhgiH deilppadaoloN0 V rewoPwoL deilppadaoloN0 V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT ,4KLC-0KLC,4STC-0STC, 0AT TUO 4AT- TUO ,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI ,TESER, VNC SS ETYB, VI V5=0 .5 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI ,TESER, VNC SS ETYB, VI V0=0 .5- µA R PULLUP ecnatsiseRpu-lluP0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( VI V0=h salF yromeM 030 57 61k Ω deksaM MOR 020 47 61 fR NIX ecnatsiseRkcabdeeFX NI 5.1M Ω fR NICX ecnatsiseRkcabdeeFX NIC 01M Ω V MAR egatloVybdnatSMARe dompotsnI0 .2V :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

Page 49 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V Table 5.3 Electrical Characteristics (Continued) (VCC1 =VCC2 =4.2 to 5.5V, VSS =0V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified) lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU.niM. pyT. xaM I CC tnerruCylppuSrewoPp ihc-elgnisnI sniptuptuo,edom dnanepotfelera erasniprehto Votdetcennoc SS . ,evawerauqS,zHM23=)KLCB(f noisividoN 825 4A m zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MORnogninnurmargorP hsalF yromeM 034 µA deksaM MOR zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MARnogninnurmargorP )1( 52 µA 52=rpoT,edomtiawnI,zHk23=)KLCB(fC ° 01 µA ,spotskcolcelihW5 2=rpoTC ° 8.05 µA ,spotskcolcelihW5 8=rpoTC ° 05 µA :SETON .)deppotsyromemhsalf("1"otretsiger0RMFehtnitibPTSMFehtgnittesnehwdeniatbosieulaV.1

Page 50 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= 1CC 01s tiB LNIr orrEytiraenilnoNlargetnIV FER V= 1CC V= 2CC V5= NA 0 NAot 7,0NA 0 ot 0NA 7 2NA, 0 2NAot 7, 51NA 0 51NAot 7, 1XENA,0XENA BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orrEytiraenilnoNlaitnereffiD 1±B SL -r orrEtesffO 3±B SL -r orrEniaG 3±B SL R REDDAL reddaLrotsiseRV =FER V 1CC 80 4k Ω t VNOC emiTnoisrevnoCtib-01 )2,1( 60.2 µs t VNOC emiTnoisrevnoCtib-8 )2,1( 57.1 µs t PMAS emiTgnilpmaS )1( 881.0 µs V FER egatloVecnerefeR 2V 1CC V V AI egatloVtupnIgolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM61gnideecxefi,) φ .sselrozHM61taycneuqerfDA .noitcnufdlohdnaelpmasehtgnisuhtiW.2 lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(5 .1A m :SETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwtnemerusaeM.1 00"ottessi,desu 61 .dedulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf FER .)noitcennoc Table 5.4 A/D Conversion Characteristics (VCC1 =V CC2 =AV CC =V REF =4.2 to 5.5V, Vss= AVSS = 0V at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified) Table 5.5 D/A Conversion Characteristics (VCC1 =V CC2 =V REF =4.2 to 5.5V, VSS =AV SS= 0V at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)

Page 51 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V lobmySr etemaraP dradnatS tinU.niM. pyT. xaM - ecnarudnEesarEdnamargorP )2( 001s elcyc -V (emiTmargorPdroW 1CC 52=rpoT,V0.5=C ° )5 20 02 µs -e miTmargorPtiBkcoL 520 02 µs -e miTesarEkcolB V( 1CC 52=rpoT,V0.5=C ° ) kcolBetybK-4 3.04 s kcolBetybK-8 3.04 s kcolBetybK-23 5.04 s kcolBetybK-46 8.04 s -e miTesarEkcolB-dekcolnU-llA )1( x4 n s t SP tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs -( emiTdloHataDC °58ot04-=rpoT) 0 1s raey :SETON .1 n .desareebotkcolbforebmunehtsetoned .kcolbrepselcycesare-margorpforebmuN.2 siecnarudnEesarEdnamargorPfI n (elcyc n demmargorpdnadesareebnackcolbhcae,)001= n .selcyc tnereffidaothcae,semit840,2ataddrowagnimmargorpretfadesaresiAkcolbetybK-4afi,elpmaxeroF sserddaemasehtotdemmargorpebtonnacataD.ecnarudneesarednamargorpenosastnuocsiht,sserdda .)detibihorpetirwer(.kcolbehtgnisaretuohtiwecnonahterom Topr=0 to 60oC unless otherwise specified)

Page 52 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM 4tedVe gatloVnoitceteDegatloVwoL )1( V 1CC V5.5ot0.3= 8.3V 3tedVe gatloVnoitceteDecapSteseR )1( 0.3V s3tedVe gatloVdloHteseRegatloVwoL 0.2V r3tedV egatloVesaeleRteseRegatloVwoL )2( 1.3V :SETON 3tedV>4tedV.1 .deetnaraugtonsi3tedV>r3tedV.2 lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM )R-P(dt nehwegatloVylppuSlanretnIezilibatSotemiTtiaW no-rewoP V 1CC V5.5ot0.3=2 s m )R-S(dtt eseRnoitceteD.tuo-nworBesaeleRotemiTtiaWV 1CC V5.5otr3tedV=6 )1( 02s m )A-E(dt tiucriCnoitceteDegatloVwoLrofemiTpu-tratS noitarepO V 1CC V5.5ot0.3=0 2 µs :SETON V.1 1CC V5= td(P-R) VCC1 CPU Clock td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on td(S-R) Vdet3r VCC1 CPU Clock td(S-R) Wait Time to Release Brown-out Detection Reset (Hardware Reset 2) VC26, VC27 td(E-A) td(E-A) Start-up Time for Low Voltage Detection Circuit Operation Stop Operating Recommanded Operating Voltage Low Voltage Detection Circuit Table 5.7 Voltage Detection Circuit Electrical Characteristics (VCC1 =V CC2 =3.0 to 5.5V, Vss=0V at Topr=25oC unless otherwise specified) Table 5.8 Power Supply Timing Figure 5.1 Power Supply Timing Diagram

Page 53 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V tac1(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (if external bus cycle is aφ + bφ, m=(bx2)+1) tac2(AD – DB) = f(BCLK) X 2 – 3510 X p9 [ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1) – 3510 X n9 [ns] (if external bus cycle is aφ + bφ, n=a+b)f(BCLK) tac1(AD – DB) = tac2(RD – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (if external bus cycle is aφ + bφ, m=(bx2)-1) lobmySr etemaraP dradnatS tinU .niM. xaM 1cat )BD-DR( )dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 1cat )BD-DA( )dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n ust )KLCB-BD( emiTputeStupnIataD 62s n ust )KLCB-YDR( emiTputeStupnIYDR 62s n ust )KLCB-DLOH( emiTputeStupnIDLOH 03s n ht )BD-DR( emiTdloHtupnIataD 0s n ht )YDR-KLCB( emiTdloHtupnIYDR 0s n ht )DLOH-KLCB( emiTdloHtupnIDLOH 0s n dt )ADLH-KLCB( emiTyaleDtuptuOADLH 52s n :SETON atresnI.selcycsublanretxednaycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepoehtrewolroetatstiaw KLCB .evitagensieulavdetaluclacehtfi,) lobmySr etemaraP dradnatS tinU .niM. xaM cte miTelcyCtupnIkcolClanretxE 52.13s n wt )H( htdiW)"H"(hgiHtupnIkcolClanretxE 57.31s n wt )L( htdiW)"L"(woLtupnIkcolClanretxE 57.31s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n Timing Requirements (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr=–20 to 85oC unless otherwise specified) Table 5.9 External Clock Input Table 5.10 Memory Expansion Mode and Microprocessor Mode

Page 54 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiW)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiW)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n Timing Requirements (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr=–20 to 85oC unless otherwise specified) Table 5.11 Timer A Input (Count Source Input in Event Counter Mode) Table 5.12 Timer A Input (Gate Input in Timer Mode) Table 5.13 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 5.14 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 5.15 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)

Page 55 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiW)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niMx aM ct )DA( DA GRT )reggirtrofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiW)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiW)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiW)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTputeStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HNI( htdiW)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiW)"L"(woLtupnIiTNI 052s n Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.16 Timer B Input (Count Source Input in Event Counter Mode) Table 5.17 Timer B Input (Pulse Period Measurement Mode) Table 5.18 Timer B Input (Pulse Width Measurement Mode) Table 5.19 A/D Trigger Input Table 5.20 Serial I/O Table 5.21 External Interrupt INTi Input

Page 56 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )3( 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )3( )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )3( 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )3( )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 5-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )3( )1etoN(s n wt )RW( htdiWtuptuORW )2etoN(s n td(DB – WR) = f(BCLK) – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2

10 X n

– 15 [ns] 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles. (if external bus cycle is aφ + bφ, n=(bx2)-1)

10 X m

(if external bus cycle is aφ + bφ, m= b) NOTES: 3. tc ns is added when recovery cycle is inserted. See Figure 5.2 Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.22 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)

Page 57 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )5( )1etoN(s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )5( )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )5( )1etoN(s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )5( )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 5-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht (- RW) BD )dradnatsRW(emiTdloHtuptuOataD )5( )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 2-s n dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )3etoN(s n ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )4etoN(s n zdt )DA-DR( emiTtratStaolFtuptuOsserddA 8s n td(DB – WR) = 10 X m – 25 [ns] (if external bus cycle is aφ + bφ, m= (bx2)-1) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 – 20 [ns] (if external bus cycle is aφ + bφ, n= a) th(ALE – AD) = f(BCLK) X 2 – 10 [ns] (if external bus cycle is aφ + bφ, n= a) f(BCLK) X 2 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle. 3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.

Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.

NOTES: 5. tc ns is added when recovery cycle is inserted. See Figure 5.2 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.23 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)

Page 58 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =5V P10 30pF P14 P13 P12 P15 P11 Note 1 NOTES: 1. P11 to P15 are provided in the 144-pin package only. Figure 5.2 P0 to P15 Measurement Circuit

Page 59 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M Figure 5.3 VCC1 =V CC2 =5V Timing Diagram (1) BCLK RD 18ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min tsu(DB-BCLK) td(BCLK-RD) 26ns.min(1) CSi td(BCLK-CS) 18ns.max(1) ADi th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) 0ns.min tac1(AD-DB)(2) WR,WRL, WRH 18ns.max -5ns.min BCLK CSi td(BCLK-CS) 18ns.max ADi td(BCLK-AD) 18ns.max -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) th(WR-DB) (3) td(DB-WR) =(tcyc x m-20)ns.min (if external bus cycle is aφ+bφ, m=b) th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (if external bus cycle is aφ+bφ , n=(bx2)-1) Vcc1=Vcc2=5V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (3) th(WR-AD) (3) tw(WR) (3) tac1(RD-DB)(2) 18ns.max(1) [ Read Timing ] (1φ +1φ Bus Cycle) [ Write timing ] (1φ +1φ Bus Cycle) NOTES: 3. Varies with operation frequency: Measurement Conditions:

VCC1 =VCC2 =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VOH =2.0V, VOL =0.8V Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1) tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b) td(DB-WR) (3) tcyc= 10 f(BCLK)

Page 60 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M Figure 5.4 VCC1 =V CC2 =5V Timing Diagram (2) BCLK CSi ADi RD -5ns.min BHE ADi /DBi 26ns.min td(BCLK-RD) tsu(DB-BCLK) tac2(RD-DB) tdz(RD-AD) 8ns.max ALE td(BCLK-ALE) 18ns.max td(BCLK-CS) td(AD-ALE) th(ALE-AD) th(BCLK-RD) th(RD-AD) th(RD-DB)td(BCLK-AD) th(BCLK-CS) th(RD-CS) th(BCLK-ALE) tcyc Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) -5ns.min BCLK CSi ADi BHE ADi /DBiWR,WRL, WRH th(WR-CS) ALE th(BCLK-WR) td(DB-WR) 18ns.max tac2(AD-DB) [ Read Timing ] (2φ +2φ Bus Cycle) Address (1) (1) (1) td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a) th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1) tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1) NOTES: 1. Varies with operation frequency: Data input Address (1) [ Write Timing ] (2φ +2φ Bus Cycle) Address Data output Address (2) (2) td(AD-ALE)=(tcyc/2 x n - 20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n -10)ns.min (if external bus cycle is aφ + bφ, n=a) th(WR-AD) =(tcyc/2-10)ns.min, th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (if external bus cycle is aφ + bφ, m=(b x 2)-1) NOTES: 2. Varies with operation frequency: Measurement Conditions:

V CC1 =V CC2 =4.2 to 5.5V
Input high and low voltage: VIH=2.5V, VIL=0.8V
Output high and low voltage: VOH =2.0V, VOL =0.8V Vcc1=Vcc2=5V -3ns.min (1) th(BCLK-AD) -3ns.min0ns.min (1) 18ns.max -2ns.min 18ns.max 18ns.max th(WR-DB) (2) th(BCLK-AD) -3ns.min th(WR-AD) 18ns.max td(BCLK-WR) 18ns.max td(BCLK-AD) td(AD-ALE) (2) td(BCLK-CS) 18ns.max td(BCLK-ALE) -2ns.min th(BCLK-ALE) tcyc (2) th(BCLK-CS) -3ns.min th(ALE-AD) (2) tcyc= 10 f(BCLK)

Page 61 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M tsu(D–C) TAiIN Input TAiOUT Input In event counter mode TBiIN Input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tg(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN Input (When counting on the falling edge) TAiIN Input (When counting on the rising edge) TAiOUT Input (Counter increment/ decrement input) INTi Input AD TRG Input Vcc1=Vcc2=5V NMI input

2 CPU clock cycles +

("L" width) Figure 5.5 VCC1 =V CC2 =5V Timing Diagram (3)

Page 62 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Hi–Z Measurement Conditions

VCC1 =VCC2 =4.2 to 5.5V
Input high and low voltage: VIH=4.0V, VIL=1.0V
Output high and low voltage: VOH =2.5V, VOL =2.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD Input HLDA Output P0, P1, P2, P3, P4, 0 to P52 RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Vcc1=Vcc2=5V Figure 5.6 VCC1 =V CC2 =5V Timing Diagram (4)

Page 63 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =3.3V )T58/C23M,58/C23M(puorG58/C23M Table 5.24 Electrical Characteristics (VCC1 =V CC2 =3.0 to 3.6V, VSS =0V at Topr = –20 to 85oC, f(BCLK)=24MHZ unless otherwise specified) lobmySr etemaraPn oitidnoC dradnatS tinU.niM. pyT. xaM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 I HO Am1-=V 2CC 6.0-V 2CC V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( V 1CC 6.0-V 1CC V X TUO I HO Am1.0-=7 .2V 1CC V X TUOC rewoPhgiH deilppadaoloN5 .2V rewoPwoL deilppadaoloN6 .1V V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4, 8P 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4, 21P 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0- 51P 7 )1( I LO Am1=5 .0V X TUO I LO Am1.0=5 .0V X TUOC rewoPhgiH deilppadaoloN0 V rewoPwoL deilppadaoloN0 V V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT -0KLC,4STC-0STC, 0AT,4KLC TUO 4AT- TUO -0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS,4DxR 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI , VNC,TESER SS ETYB, VI V3=0 .4 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7, 9P 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI , VNC,TESER SS ETYB, VI V0=0 .4- µA R PULLUP ecnatsiseRpu-lluP0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( VI V0=h salF yromeM 660 210 05k Ω deksaM MOR 040 70 05k Ω fR NIX ecnatsiseRkcabdeeFX NI 0.3M Ω fR NICX ecnatsiseRkcabdeeFX NIC 0.02M Ω V MAR egatloVybdnatSMARe dompotsni0 .2V I CC ylppuSrewoP tnerruC :noitidnoctnemerusaeM ,edompihc-elgnisnI nepotfelerasniptuptuo erasniprehtodna Votdetcennoc SS . oN,evawerauqS,zHM42=)KLCB(f noisivid 225 3A m ,edomtiawnI,zHk23=)KLCB(f 52=rpoTC ° 01 µA ,spotskcolcelihW5 2=rpoTC ° 8.05 µA ,spotskcolcelihW5 8=rpoTC ° 05 µA :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

Page 64 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =3.3V )T58/C23M,58/C23M(puorG58/C23M Table 5.25 A/D Conversion Characteristics (VCC1 =V CC2 =AV CC =V REF = 3.0 to 3.6V, VSS =AV SS =0V at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified) Table 5.26 D/A Conversion Characteristics (VCC1 =V CC2 =VREF =3.0 to 3.6V, VSS =AV SS =0V at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified) lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= 1CC 01s tiB LNIr orrEytiraenilnoNlargetnI) tib-8(H&SoNV 1CC V= 2CC V= FER V3.3=2 ±B SL LNDr orrEytiraenilnoNlaitnereffiD) tib-8(H&SoN1 ±B SL -r orrEtesffO) tib-8(H&SoN2 ±B SL -r orrEniaG) tib-8(H&SoN2 ±B SL R REDDAL reddaLrotsiseRV FER V= 1CC 80 4k Ω t VNOC emiTnoisrevnoCtib-8 )2,1( 1.6 µs V FER egatloVecnerefeR 3V 1CC V V AI egatloVtupnIgolanA 0V FER V dloHdnaelpmaS:H&S :SETON X(fediviD.1 NI peekot,zHM01gnideecxefi,) φ .sselrozHM01taycneuqerfDA .elbaliavatonH&S.2 lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(0 .1A m :SETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwstlusertnemerusaeM.1 00"ottessi,desu 61 .dedulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf FER .)noitcennoc

Page 65 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =3.3V )T58/C23M,58/C23M(puorG58/C23M Timing Requirements (VCC1 =V CC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.27 External Clock Input Table 5.28 Memory Expansion Mode and Microprocessor Mode lobmySr etemaraP dradnatS tinU .niM. xaM cte miTelcyCtupnIkcolClanretxE 14s n wt )H( htdiW)"H"(hgiHtupnIkcolClanretxE 81s n wt )L( htdiW)"L"(woLtupnIkcolClanretxE 81s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n tac1(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (if external bus cycle is aφ + bφ, m=(bx2)+1) tac2(AD – DB) = f(BCLK) X 2 – 3510 X p9 [ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1) – 3510 X n9 [ns] (if external bus cycle is aφ + bφ, n=a+b)f(BCLK) tac1(AD – DB) = tac2(RD – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (if external bus cycle is aφ + bφ, m=(bx2)-1) lobmySr etemaraP dradnatS tinU .niM. xaM 1cat )BD-DR( )dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 1cat )BD-DA( )dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n ust )KLCB-BD( emiTputeStupnIataD 03s n ust )KLCB-YDR( emiTputeStupnIYDR 04s n ust )KLCB-DLOH( emiTputeStupnIDLOH 06s n ht )BD-DR( emiTdloHtupnIataD 0s n ht )YDR-KLCB( emiTdloHtupnIYDR 0s n ht )DLOH-KLCB( emiTdloHtupnIDLOH 0s n dt )ADLH-KLCB( emiTyaleDtuptuOADLH 52s n :SETON atresnI.selcycsublanretxednaycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepoehtrewolroetatstiaw KLCB .evitagensieulavdetaluclacehtfi,)

Page 66 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =3.3V )T58/C23M,58/C23M(puorG58/C23M Timing Requirements (VCC1 =VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.29 Timer A Input (Count Source Input in Event Counter Mode) Table 5.30 Timer A Input (Gate Input in Timer Mode) Table 5.31 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 5.32 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 5.33 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiW)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiW)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n

Page 67 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =3.3V )T58/C23M,58/C23M(puorG58/C23M Timing Requirements (VCC1 =VCC 2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.34 Timer B Input (Count Source Input in Event Counter Mode) Table 5.35 Timer B Input (Pulse Period Measurement Mode) Table 5.36 Timer B Input (Pulse Width Measurement Mode) Table 5.37 A/D Trigger Input Table 5.38 Serial I/O Table 5.39 External Interrupt INTi Input lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiW)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )DA( DA GRT )reggirtrofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiW)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiW)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiW)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTputeStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HNI( htdiW)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiW)"L"(woLtupnIiTNI 052s n

Page 68 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =3.3V )T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )3( 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )3( )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 0s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )3( 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )3( )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )3( )1etoN(s n wt )RW( htdiWtuptuORW )2etoN(s n td(DB – WR) = f(BCLK) 10 x m – 20 [ns] (if external bus cycle is aφ + bφ, m=b) th(WR – DB) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2 10 x n9 – 15 [ns] (if external bus cycle is aφ + bφ, n=(b x 2)-1) NOTES: 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles. 3. tc ns is added when recovery cycle is inserted. See Figure 5.2 Switching Characteristics (VCC1 =V CC2 =3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.40 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)

Page 69 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85) VCC1 =VCC2 =3.3V )T58/C23M,58/C23M(puorG58/C23M Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.41 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )5( )1etoN(s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )5( )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 0s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )5( )1etoN(s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )5( )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0s n dt )RW-BD( )dradnatsRW(emiTyaledtuptuOataD )2etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )5( )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 2-s n dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )3etoN(s n ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )4etoN(s n zdt )DA-DR( emiTtratStaolFtuptuOsserddA 8s n td(DB – WR) = 10 X m9 – 25 [ns] (if external bus cycle is aφ + bφ, m=(b+2)-1) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 –10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 20 [ns] td(AD – ALE) = f(BCLK) X 2 10 x n – 20 [ns] (if external bus cycle is aφ + bφ, n=a) th(ALE – AD) = f(BCLK) X 2 10 x n9 – 10 [ns] (if external bus cycle is aφ + bφ, n=a) f(BCLK) X 2 NOTES: 1. Values can be obtained by the following equations, according to BLCK frequency. 2. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. 3. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. 4. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. 5. tc ns is added when recovery cycle is inserted. See Figure 5.2

Page 70 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M Figure 5.7 VCC1 =V CC2 =3.3V Timing Diagram (1) BCLK RD 18ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-RD) 30ns.min(1) tac1(RD-DB)(2) CSi td(BCLK-CS) 18ns.max(1) ADi 18ns.max(1) th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) tac1(AD-DB)(2) WR,WRL, WRH 18ns.max 0ns.min BCLK CSi 18ns.max ADi 18ns.max 0ns.min 0ns.min tcyc BHE DBi td(BCLK-WR) th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (3) td(DB-WR) (3) th(WR-DB) (3) th(WR-AD) (3) [Read Timing] (1φ + 1φ Bus Cycles) [Write Timing] (1φ + 1φ Bus Cycles) Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) tw(WR) (3) Vcc1=Vcc2=3.3V NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency. tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2) + 1) tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n = a + b) td(DB-WR) =(tcyc x m-20)ns.min (if external bus cycle is aφ + bφ, m=b) th(WR-DB) =(tcyc/2-20)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (if external bus cycle is aφ + bφ, n=(bx2)-1) NOTES: 3. Varies with operation frequency. Measurement Conditions

VCC 1=V CC 2=3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH =1.5V, VOL =1.5V tcyc= 10 f(BCLK)

Page 71 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) BCLK CSi ADi RD -3ns.min BHE ADi /DBi 30ns.min td(BCLK-RD) tsu(DB-BCLK) tdz(RD-AD) 8ns.max ALE td(BCLK-ALE) 18ns.max td(AD-ALE) th(ALE-AD) th(BCLK-RD) th(RD-AD) td(BCLK-AD) th(BCLK-CS) th(RD-CS) th(BCLK-ALE) tcyc Memory Expansion Mode and Microprocessor Mode (when accessing external memory space and using the multiplexed bus) 0ns.min BCLK CSi ADi BHE ADi /DBiWR,WRL, WRH ALE th(BCLK-WR) 18ns.max tac2(AD-DB) [ Read Timing ] (2φ +2φ Bus Cycles) Address (1) (1) (1) (1) (1) td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a) th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1) tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1) NOTES: 1. Varies with operation frequency: (1) [ Write Timing ] (2φ +2φ Bus Cycles) Address Address td(AD-ALE)=(tcyc/2 x n - 20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n -10)ns.min (if external bus cycle is aφ + bφ, n=a) th(WR-AD) =(tcyc/2-10)ns.min, th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-20)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (if external bus cycle is aφ + bφ, m=(b x 2)-1) NOTES: 2. Varies with operation frequency: Measurement Conditions:

VCC 1=V CC 2=3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH =1.5V, VOL =1.5V Vcc1=Vcc2=3.3V 18ns.max td(BCLK-WR) th(WR-AD) (2) th(BCLK-AD) 0ns.min Data output th(ALE-AD) -2ns.min td(BCLK-ALE) th(BCLK-ALE) 18ns.max 18ns.max 0ns.minth(WR-CS) td(AD-ALE) td(BCLK-CS) td(BCLK-AD) th(BCLK-CS) td(DB-WR) th(WR-DB) tcyc (2) (2) (2) (2) (2) 18ns.max 18ns.max 18ns.max 0ns.min 0ns.mintac2(RD-DB) -2ns.min td(BCLK-CS) th(RD-DB) th(BCLK-AD) 0ns.min Data input Address tcyc= 10 f(BCLK) Figure 5.8 VCC1 =V CC2 =3.3V Timing Diagram (2)

Page 72 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85))T58/C23M,58/C23M(puorG58/C23M Figure 5.9 VCC1 =V CC2 =3.3V Timing Diagram (3) tsu(D–C) TAiIN Input TAiOUT Input In event counter mode TBiIN Input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN Input (When counting on falling edge) TAiIN Input (When counting on rising edge) TAiOUT Input (Counter increment/ decrement input) INTi Input AD TRG Input Vcc1=Vcc2=3.3V NMI input ("L" width)

Page 73 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M 5. Electrical Characteristics (M32C/85) Figure 5.10 VCC1 =V CC2 =3.3V Timing Diagram (4) Measurement Conditions:

VCC1 =V CC2 =3.0 to 3.6V
Input high and low voltage: VIH=2.4V, VIL=0.6V
Output high and low voltage: VOH =1.5V, VOL =1.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Hi–Z th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Vcc1=Vcc2=3.3V

Page 74 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T))T58/C23M,58/C23M(puorG58/C23M

5.2 Electrical Characteristics (M32C/85T)

Table 5.42 Absolute Maximum Ratings lobmySr etemaraPn oitidnoCe ulaVt inU V 1CC V, 2CC egatloVylppuSV 1CC V= 2CC VA= CC 0.6ot3.0- V VA CC egatloVylppuSgolanAV 1CC V= 2CC VA= CC 0.6ot3.0- V VI egatloVtupnIV NC,TESER SS 6P,ETYB, 0 6P- 7 7P, 2 7P- 7, 8P 0 8P- 7 9P, 0 9P- 7 01P, 0 01P- 7 41P, 0 41P- 6, 51P 0 51P- 7 )1( V, FER X, NI Vot3.0- 1CC 3.0+V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 )1( Vot3.0- 2CC 3.0+ 7P 0 7P, 1 0.6ot3.0- VO egatloVtuptuO6 P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( , X TUO Vot3.0- 1CC 3.0+V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 )1( Vot3.0- 2CC 3.0+ 7P 0 7P, 1 0.6ot3.0- dPn oitapissiDrewoP C°52=rpoT0 05W m rpoT gnitarepO tneibmA erutarepmeT noitarepoUPCgnirudn oisrevT5 8ot04- C°esarednamargorpyromemhsalfgnirud noitarepo 06ot0 gtsTe rutarepmeTegarotS 051ot56-C ° :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

Page 75 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T))T58/C23M,58/C23M(puorG58/C23M Table 5.43 Recommended Operating Conditions (VCC1 =VCC2 =4.2 to 5.5V, VSS =0V at Topr = -40 to 85oC (T version) unless otherwise specified) lobmySr etemaraP dradnatS tinU.niM. pyT. xaM V 1CC V, 2CC V(egatloVylppuS 1CC V 2CC )2 .40 .55 .5V VA CC egatloVylppuSgolanA V 1CC V V SS egatloVylppuS 0V VA SS egatloVylppuSgolanA 0V V HI )"H"(hgiHtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 )4( V8.0 2CC V 2CC V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7,41P 0- 41P 6 51P, 0 51P- 7 )4( X, NI VNC,TESER, SS ETYB, V8.0 1CC V 1CC 7P 0 7P, 1 V8.0 1CC 0.6 0P 0 0P- 7 1P, 0 1P- 7 V8.0 2CC V 2CC V LI )"L"(woLtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 )4( 0V 2.0 2CC V 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )4( X, NI VNC,TESER, SS ETYB, 0V 2.0 1CC 0P 0 0P- 7 1P, 0 1P- 7 0V 2.0 2CC I )kaep(HO tuptuOkaeP )"H"(hgiH tnerruC )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01-A m I )gva(HO tuptuOegarevA )"H"(hgiH tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5-A m I )kaep(LO woLtuptuOkaeP tnerruC)"L"( )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.01A m I )gva(LO tuptuOegarevA )"L"(woL tnerruC )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )4( 0.5A m :SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08ebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(LO 8P,7P,6P,5P,4P,3Prof 0 8Pot 4 .sselroAm08ebtsum31Pdna21P, IlatoT )kaep(HO .sselroAm04-ebtsum11Pdna,2P,1P,0Prof IlatoT )kaep(HO 8Prof 6 8P, 7 .sselroAm04-ebtsum51Pdna41P,01P,9P, IlatoT )kaep(HO .sselroAm04-ebtsum31Pdna21P,5P,4P,3Prof IlatoT )kaep(HO 8Pdna,7P,6Prof 0 8Pot 4 .sselroAm04-ebtsum .3V HI Vdna LI 8Profecnerefer 7 8Pnehwseilppa 7 .troptupnielbammargorpasadesusi 8PnehwylppatonseodtI 7 Xsadesusi NIC . .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.4

Page 76 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T))T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraP dradnatS tinU .niM. pyT. xaM (f KLCB )y cneuqerFtupnIUPCV 1CC V5.5ot2.4=0 2 3z HM X(f NI )y cneuqerFtupnIkcolCniaMV 1CC V5.5ot2.4=0 2 3z HM X(f NIC )y cneuqerFkcolCbuS 867.230 5z Hk (f gniR ) (ycneuqerFrotallicsOpihc-nOV 1CC V= 2CC 52=rpoT,V0.5=) C° 5.01 2 z HM (f LLP )y cneuqerFkcolCLLPV 1CC V5.5ot2.4=0 12 3z HM t )LLP(US rezisehtnySycneuqerFLLPezilibatSotemiTtiaWV 1CC V0.5=5 s m Table 5.43 Recommended Operating Conditions (Continued) (VCC1 =VCC2 =4.2 to 5.5V, VSS =0V at Topr = -40 to 85oC (T version) unless otherwise specified)

Page 77 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraPn oitidnoC dradnatS tinU.niM. pyT. xaM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 I HO Am5-= V CC -2 0.2 V CC 2 V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO Am5-= V CC -1 0.2 V CC 1 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 I HO 002-= µA V CC -2 3.0 V CC 2 V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I HO 002-= µA V CC -1 3.0 V CC 1 X TUO I HO Am1-=0 .3V X TUOC rewoPhgiH deilppadaoloN5 .2V rewoPwoL deilppadaoloN6 .1 V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( I LO 002= µA5 4.0V X TUO I LO Am1=0 .2V X TUOC rewoPhgiH deilppadaoloN0 V rewoPwoL deilppadaoloN0 V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT ,4KLC-0KLC,4STC-0STC, 0AT TUO 4AT- TUO ,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI ,TESER, VNC SS ETYB, VI V5=0 .5 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( X, NI ,TESER, VNC SS ETYB, VI V0=0 .5- µA R PULLUP ecnatsiseRpu-lluP 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0- 21P 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( VI V0=h salF yromeM 030 57 61k Ω fR NIX ecnatsiseRkcabdeeFX NI 5.1M Ω fR NICX ecnatsiseRkcabdeeFX NIC 01M Ω V MAR egatloVybdnatSMARe dompotsnI0 .2V :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1 Table 5.44 Electrical Characteristics (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr = -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified)

Page 78 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU.niM. pyT. xaM I CC tnerruCylppuSrewoPt uptuo,edompihc-elgnisnI rehtodnanepotfelerasnip Votdetcennocerasnip SS . ,evawerauqS,zHM23=)KLCB(f noisividoN 820 5A m zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MORnogninnurmargorP 034 µA zHk23=)KLCB(f, edomnoitpmusnocrewop-wolnI, MARnogninnurmargorP )1( 52 µA ,edomtiawnI,zHk23=)KLCB(f 52=rpoTC ° 01 µA ,spotskcolcelihW5 2=rpoTC ° 8.05 µA ,spotskcolcelihW5 8=rpoTC ° 05 µA :SETON .)deppotsyromemhsalf("1"otretsiger0RMFehtnitibPTSMFehtgnittesnehwdeniatbosieulaV.1 Table 5.44 Electrical Characteristics (Continued) (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr = -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified)

Page 79 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(5 .1A m :SETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwtnemerusaeM.1 00"ottessi,desu 61 .dedulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf FER .)noitcennoc lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= 1CC 01s tiB LNIr orrEytiraenilnoNlargetnIV FER V= 1CC V= 2CC V5= NA 0 NAot 7,0NA 0 ot 0NA 7 2NA, 0 2NAot 7, 51NA 0 51NAot 7, 1XENA,0XENA BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orrEytiraenilnoNlaitnereffiD 1±B SL -r orrEtesffO 3±B SL -r orrEniaG 3±B SL R REDDAL reddaLrotsiseRV =FER V 1CC 80 4k Ω t VNOC emiTnoisrevnoCtib-01 )2,1( 60.2 µs t VNOC emiTnoisrevnoCtib-8 )2,1( 57.1 µs t PMAS emiTgnilpmaS )1( 881.0 µs V FER egatloVecnerefeR 2V 1CC V V AI egatloVtupnIgolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM61gnideecxefi,) φ .sselrozHM61taycneuqerfDA .noitcnufdlohdnaelpmasehtgnisuhtiW.2 Table 5.45 A/D Conversion Characteristics (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr= -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified) Table 5.46 D/A Conversion Characteristics (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr= -40 to 85oC (T version), f(BCLK)=32MHz unless otherwise specified)

Page 80 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M td(P-R) VCC1 CPU Clock td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on Recommanded Operating Voltage lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM )R-P(dt nehwegatloVylppuSlanretnIezilibatSotemiTtiaW no-rewoP V 1CC V5.5ot0.3=2 s m Table 5.47 Flash Memory Version Electrical Characteristics (VCC1 =4.5 to 5.5V, 3.0 to 3.6V at Topr= 0 to 60oC unless otherwise specified) Figure 5.11 Power Supply Timing Diagram lobmySr etemaraP dradnatS tinU.niM. pyT. xaM - ecnarudnEesarEdnamargorP )2( 001s elcyc -V (emiTmargorPdroW 1CC 52=rpoT,V0.5=C ° )5 20 02 µs -e miTmargorPtiBkcoL 520 02 µs -e miTesarEkcolB V( 1CC 52=rpoT,V0.5=C ° ) kcolBetybK-4 3.04 s kcolBetybK-8 3.04 s kcolBetybK-23 5.04 s kcolBetybK-46 8.04 s -e miTesarEkcolB-dekcolnU-llA )1( x4 n s t SP tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs -( emiTdloHataDC °58ot04-=rpoT) 0 1s raey :SETON .1 n .desareebotkcolbforebmunehtsetoned .kcolbrepselcycesare-margorpforebmuN.2 siecnarudnEesarEdnamargorPfI n (elcyc n demmargorpdnadesareebnackcolbhcae,)001= n .selcyc tnereffidaothcae,semit840,2ataddrowagnimmargorpretfadesaresiAkcolbetybK-4afi,elpmaxeroF sserddaemasehtotdemmargorpebtonnacataD.ecnarudneesarednamargorpenosastnuocsiht,sserdda .)detibihorpetirwer(.kcolbehtgnisaretuohtiwecnonahterom Table 5.48 Power Supply Timing

Page 81 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraP dradnatS tinU .niM. xaM cte miTelcyCtupnIkcolClanretxE 52.13s n wt )H( htdiW)"H"(hgiHtupnIkcolClanretxE 57.31s n wt )L( htdiW)"L"(woLtupnIkcolClanretxE 57.31s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n Timing Requirements (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr= -40 to 85oC (T version) unless otherwise specified) Table 5.49 External Clock Input

Page 82 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiW)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiW)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n Timing Requirements (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr= -40 to 85oC (T version) unless otherwise specified) Table 5.50 Timer A Input (Count Source Input in Event Counter Mode) Table 5.51 Timer A Input (Gate Input in Timer Mode) Table 5.52 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 5.53 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 5.54 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)

Page 83 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M Timing Requirements (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr= -40 to 85oC (T version) unless otherwise specified) Table 5.55 Timer B Input (Count Source Input in Event Counter Mode) Table 5.56 Timer B Input (Pulse Period Measurement Mode) Table 5.57 Timer B Input (Pulse Width Measurement Mode) Table 5.58 A/D Trigger Input Table 5.59 Serial I/O Table 5.60 External Interrupt INTi Input lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiW)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niMx aM ct )DA( DA GRT )reggirtrofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiWesluP)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiW)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiW)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTputeStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HNI( htdiW)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiW)"L"(woLtupnIiTNI 052s n

Page 84 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T) VCC1 =VCC2 =5V )T58/C23M,58/C23M(puorG58/C23M P10 30pF P14 P13 P12 P15 P11 Note 1 NOTES: 1. P11 to P15 are provided in the 144-pin package only. Figure 5.12 P0 to P15 Measurement Circuit

Page 85 78fo5002,10.luJ12.1.veR 5. Electrical Characteristics (M32C/85T))T58/C23M,58/C23M(puorG58/C23M tsu(D–C) TAiIN Input TAiOUT Input In event counter mode TBiIN Input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN Input (When counting on the falling edge) TAiIN Input (When counting on the rising edge) TAiOUT Input (Counter increment/ decrement input) INTi Input AD TRG Input Vcc1=Vcc2=5V NMI input ("L" width) Figure 5.13 VCC1 =V CC2 =5V Timing Diagram

Page 86 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Package Dimensions PLQP0144KA-A (144P6Q-A) Plastic 144pin 20✕ 20mm body LQFP 0.125 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 0.95 ––M D 20.4 ––M E 20.4 8°0° 0.1 1.0 0.650.50.35 22.222.021.8 22.222.021.8 0.5 20.120.019.9 20.120.019.9 0.1750.1250.105 0.270.220.17 1.4 0.05 1.7 e A H D D H E E 37 72 108 109144 F e Lp 0.45 0.6 0.25 0.75 0.08 x M D l2 b2 M E e Recommended Mount Pad y b x M A1 A2 L Detail F Lp c P-LQFP144-20x20-0.50 Previous Code PLQP0144KA-A 144P6Q-A RENESAS CodeJEITA Package Code Mass[Typ.] 1.2g PRQP0100JB-A (100P6S-A) Plastic 100pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 ––I2 1.3 ––M D 14.6 ––M E 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c H E H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F 100 x –– 0.13 b x M P-QFP100-14x20-0.65 Previous Code PRQP0100JB-A 100P6S-A RENESAS CodeJEITA Package Code Mass[Typ.] 1.6g Package Dimensions

Page 87 78fo5002,10.luJ12.1.veR )T58/C23M,58/C23M(puorG58/C23M Package Dimensions P-LQFP100-14x14-0.50 Previous Code PLQP0100KB-A 100P6Q-A RENESAS CodeJEITA Package Code Mass[Typ.] 0.6g PLQP0100KB-A (100P6Q-A) Plastic 100pin 14✕ 14mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 0.9 ––M D 14.4 ––M E 14.4 10°0° 0.1 1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e E H E 5026 H D D A F y 100 Lp 0.45 0.6 0.25 0.75 0.08 x b x M A1 A2 L Detail F Lp c M D l2 b2 M E e Recommended Mount Pad

REVISION HISTORY

Rev. Date Description Page Summary M32C/85 Group (M32C/85, M32C/85T) Datasheet A-1 0.30 Jul.18, 2003 – New Document Overview 2 to 3 • Tables 1.1 and 1.2 M32C/85 Performance “Oscillator Stop Detect Function” added 5• Figure 1.2 ROM/RAM Capacity and Table 1.3. M32C/85 Group M30852ME- XXXGP and M30850ME-XXXGP/FP deleted 6 • ROM capacity “192 Kbytes” deleted 7, 11, 12 • Figures 1.4 to 1.6 Pin Assignments Note 2 added 10,14 - V REF pin changed from analog input pins to control pins. 16 to 18 - SDA0 to SDA4 pins changed from output pins to I/O pins. 17 - TA4 OUT changed from input pin to I/O pin. - TA4IN pin changed from output pin to input pin. - ISRxD1 pin modified to ISRxD0 pin in port P8. 18 - DA0 and DA1 pins changed from input pins to output pins. 19 - Symbol “P11 7” modified to “P114” and description from “8-bit” to “5-bit”. - Descriptions of ISTxD1 and BE1IN modified from “received data” to “transmit data”. SFR 44,45 - Notes written directly in the Tables. Overview 2, 3 • Tables 1.1 and 1.2 M32C/85 Performance “Shortest Instruction Execution Time” and “Power Comsumption” values modified Memory 23 • Figure 3.1 Memory Map Diagram modified SFR 24 • “After RESET” values of PM 1, PM 2, D4INT, G0IRF, G1IRF, IDB0 to IDB1, TA0MR to TA4MR, TCSPR, DM0SL to DM3SL registers corrected

NOTES added to PM0 and TCSPR registers

Electrical Characteristics

Newly added

52 • Table 5.6 Flash Memory Version Electrical Characteristics Note 4 changed 59 • Figure 5.2 V CC 1=V CC 2=5V Timing Diagram (1) Notes 1 and 2 changed 60 • Figure 5.3 VCC 1=V CC 2=5V Timing Diagram (2) Notes 1, 2, and 3 changed 70 • Figure 5.6 VCC 1=VCC 2=3.3V Timing Diagram (1) Notes 1, 2, and 3 changed 71 • Figure 5.7 VCC 1=V CC 2=3.3V Timing Diagram (2) Notes 1 and 2 changed Overview 2, 3 • Table 1.1 and 1.2 M32C/85 Group Performance Value of Power Consump- tion modified 0.40 Sep.30, 2003 0.50 Feb.05, 2004 0.51 Feb.09, 2004 0.52 Mar.12, 2004

Rev. Date Description Page Summary M32C/85 Group (M32C/85, M32C/85T) Datasheet A-2 50 • Table 5.3 Electrical Characteristics Maximum values for Power Supply Current modified 52 • Table 5.6 Flash Memory Version Electrical Characteristics Note 1. 100-cycle Products (D3, D5, U3, U5) deleted; Note 4 modified

Table 5.7 Flash Memory Version Program and Erase Voltage and Read Operation Voltage Characteristics (at Topr=0 to 60°C) deleted 63 • Table 5.22 Electrical Characteristics Maximum values for Power Supply Consumption modified and standard values when “Topr=85°C while clock is stopped” deleted - M32C/85T (High-reliability version) added All Pages Words standardized: On-chip oscillator, A/D converter and D/A converter Overview 1• 1.1 Applications Automobiles added 2, 3 • Table 1.1 and Table 1.2 M32C/85 Group (M32C/85, M32C/85T) Performance M32C/85T added; note 3 added 4• Figure 1.1 M32C/85 Group (M32C/85, M32C/85T) Block Diagram Note 3 added 5 • 1.4 Product Information Description modified
Figure 1.2 ROM/RAM Capacity figure modified 5, 6 • Table 1.3 M32C/85 Group M32C/85T added 6• Figure 1.3 Product Numbering System M32C/85T added 7• Figure 1.4 Pin Assignment for 144-Pin Package Note 3 added 12 • Figure 1.6 Pin Assignment for 100-Pin Pacakage Note 5 added 8 to 10 • Table 1.5 Pin Characteristics for 144-Pin Package Note 1 added 13, 14 • Table 1.6 Pin Characteristics for 100-Pin Package Note 1 added 15 to 18 • Table 1.7 Pin Description Notes added Memory 22 • Figure 3.1 Memory Map Tables of internal ROM/internal RAM modified; note 2 modified; notes 4 and 5 added SFR 23 • Note 2 added 24 • PWCR0 and PWCR1 registers deleted
“Values after RESET” of the masked ROM version added to the FMR0 register
Note 1 added

46 • Table 5.2 Recommended Operating Conditions f (ripple), Vp-p(ripple), VCC , SV CC and note 1 deleted 47 • Table 5.3 Electrical Characteristics RPULLUP value for the masked ROM ver- sion added 1.00 Jun.01, 2004

Rev. Date Description Page Summary M32C/85 Group (M32C/85, M32C/85T) Datasheet A-3 49 • Table 5.3 Electrical Characteristics Maximum ICC value modified 50 • Table 5.4 A/D Conversion Characteristics tSMP value modified; note 1 added 52 • Table 5.7 Low Voltage Detect Circuit Electrical Characteristics added

Table 5.8 Power Supply Timing added
Figure 5.1 Power Supply Timing Diagram added 57 • Table 5.23 Memory Expassion Mode and Microprocessor Mode th(BCLK-ALE) value modified 63 • Table 5.24 Electrical Characteristics Maximum ICC value modified 61 • Table 5.24 Electrical Characteristics RPULLUP value for the masked ROM version added 64 • Table 5.25 A/D Conversion Characteristics tCONV value modified 65 • Table 5.28 Memory Expassion Mode and Microprocessor Mode tsu(DB- BCLK) , tsu(RDY-BCLK) and tsu(HOLD-BCLK) value modified 68 • Table 5.40 Memory Expassion Mode and Microprocessor Mode equetion of th(WR-DB) modified 69 • Table 5.41 Memory Expassion Mode and Microprocessor Mode th(BCLK-ALE) value modified; equetion of th(WR-DB) modified 74 • 5.2 Electrical Characteristics (M32C/85T) added - High-reliability version (U version) deleted Overview 5• Table 1.3 M32C/85 Group (1) (2) development status modified 6• Figure 1.2 Product Numbering System figure modified Memory
Figure 3.1 Memory Map A sentence added to Note 3 SFR 24 • Value after reset of the RLVL register revised 27 • Value after reset of the G0RB register revised 29 • Value after reset of the G1BCR1 register revised
Value after reset of the G1RB register revised 37 • Value after reset of the IDB0 register revised
Value after reset of the IDB1 register revised 43 • Value after reset of the PSC register revised

49 • Table 5.3 Electrical Characteristics ICC standard value revised 51 • Table 5.6 Flash Memory Electrical Characteristics Topr value modified 52 • Table 5.7 Voltage Detection Circuit Electrical Characteristics VCC1 value modified 60 • Figure 5.4 VCC1 =VCC2 =5V Timing Diagram (2) Diagram modified 63 • Table 5.24 Electrical Characteristics ICC standard value revised 1.10 Jun.28, 2004 1.20 Mar.30, 2005

Rev. Date Description Page Summary M32C/85 Group (M32C/85, M32C/85T) Datasheet A-4 65 • Table 5.28 Memory Expansion Mode and Microprocessor Mode tac1(AD-DB) expression modified 77 • Table 5.44 Electrical Characteristics ICC standard value revised 80 • Table 5.47 Flash Memory Electrical Characteristics Topr value modified All pages Package code changed: 144P6Q-A to PLQP0144KA-A, 100P6Q-A to PLQP0100KB-A, 100P6S-A to PRQP0100JB-A All pages"Low Voltage Detection Reset" changed to "Brown-out Detection Reset" Special Function Register (SFR) 27 • The G0RB register Value after reset modified 39 • The TCSPR register Value after reset modified 47 • Table 5.2 Electrical Characteristics Parameter f(BCLK) and its values added 51 • Table 5.6 Flash Memory Version Electrical Characteristics Mesurement condition changed 53 • Table 5.10 Memory Expansion Mode and Microprocessor Mode tac1(RD-DB) expression on Note 1 modified; tac2(RD-DB) expression on Note 1 added 59 • Figure 5.3 VCC1 =V CC2 =5V Timing Diagram (1) tw(ER) expression on Note 3 modified; tcyc expression added 60 • Figure 5.4 VCC1 =VCC2 =5V Timing Diagram (2) tac2(AD-DB) expression on Note 1 modified; th(ALE-AD) expressions on Notes 1 and 2 modified; tcyc expression added 65 • Table 5.28 Memory Expansion Mode and Microprocessor Mode tac1(RD-DB) expression on Note 1 modified; tac2(RD-DB) expression on Note 1 added 70 • Figure 5.7 VCC1 =VCC2 =3.3V Timing Diagram (1) tw(ER) expression on Note 3 modified; tcyc expression added 71 • Figure 5.8 VCC1 =V CC2 =3.3V Timing Diagram (2) tac2(RD-DB) expression on Note 1 modified; th(ALE-AD) expressions on Notes 1 and 2 modified; th(WR-CS) expression on Note 2 modified; tcyc expression added 76 • Table 5.43 Electrical Characteristics Parameter f(BCLK) and its values added 80 • Table 5.47 Flash Memory Version Electrical Characteristics Mesurement condition changed 1.21 Jul.01, 2005

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Product Information

M30853FJFP specifications and overview.

Summary

SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

Description

SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER

Source title M30853FJFP Datasheet(PDF) - Renesas Technology Corp

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