M30823MW-XXXGP

32C82 RENESAS | Alldatasheet

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Technical content

SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER REJ03B0032-0120Z Rev.1.20 Jun. 01, 2004 page 1 38fo4002,10.nuJ00.1.veR 1. Overview The M32C/82 group microcomputer is a single-chip control unit that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/82 group is available in 144-pin and 100- pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili- ties to process complex instructions by less bytes and execute instructions at higher speed. It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial equipments and other high-speed processing applications.

1.1 Applications

Audio, cameras, office equipment, communications equipment, portable equipment, etc.

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1.2 Difference between the M32C/82 Group and the M32C/83 Group

The M32/C82 group microcomputer has less peripheral functions than the M32C/83 group miccrocomputer. The intelligent I/O group 3, CAN and the A/D1 converter are not provided in the M32C/82 group. Interrupt requests, and as a result interrupts, DMAC, and DMACII, caused by these peripheral functions are not available in the M32C/82 group.

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1.2 Performance Outline

Tables 1.1 and 1.2 list performance outlines of the M32C/82 group. Table 1.1 M32C/82 Group Performance (144-Pin Package) Item Performance CPU Basic instructions 108 instructions Shortest instruction execution time 33 ns (f(BCLK)=30 MHz, VCC =4.2 V to 5.5 V) 50 ns (f(BCLK)=20 MHz, VCC =3.0 V to 5.5 V) Operation mode Single-chip mode, Memory expansion mode and Microprocessor mode Address space 16 Mbytes Memory capacity See Table 1.3 PeripheralPort 123 I/O pins and 1 input pin function Multifunction timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function: 16 bits x 12 channels Waveform generating function: 16 bits x 20 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchro- nous variable length serial I/O, IEBus(1)) Serial I/O 5 channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) A/D converter 10-bit A/D converter: 1 circuit, 34 channels D/A converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt factors Immediate transfer, Calculation transfer and Chain transfer functions DRAMC CAS-before-RAS refresh, self-refresh, EDO, FP CRC calculation circuit CRC-CCITT XY converter 16 bits x 16 bits Watchdog timer 15 bits x 1 channel (with prescaler) Interrupt 41 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock generating circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation stop detect function Main clock oscillation stop detect function Electric Supply voltage 4.2 V to 5.5 V (f(BCLK)=30 MHz) charact- 3.0 V to 5.5 V (f(BCLK)=20 MHz, through VDC) eristics 3.0 V to 3.6 V (f(BCLK)=20 MHz, not through VDC) Power consumption 28 mA (V CC =5 V, f(BCLK)=30 MHz) 17 mA (VCC =3.3 V, f(BCLK)=20 MHz) 470 µA (VCC =5 V, f(XCIN)=32 kHz, in wait mode) 340 µA (VCC =3.3 V, f(XCIN)=32 kHz, through VDC in wait mode) 5.0 µA (VCC =3.3 V, f(XCIN)=32 kHz, not through VDC in wait mode) 0.4 µA (VCC =5 V, f(XCIN)=32 kHz, in stop mode) 0.4 µA (VCC =3.3 V, f(XCIN)=32 kHz, in stop mode) Operating ambient temperature –20 to 85 oC, –40 to 85oC (optional) Package 144-pin plastic molded LQFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. All options are on a request basis.

08fo4002,10.nuJ02.1.veR page 4 puorG28/C23M 1. Overview Table 1.2 M32C/82 Group Performance (100-Pin Package) Item Performance CPU Basic instructions 108 instructions Shortest instruction execution time 33 ns (f(BCLK)=30 MHz, VCC =4.2 V to 5.5 V) 50 ns (f(BCLK)=20 MHz, VCC =3.0 V to 5.5 V) Operation mode Single-chip mode, Memory expansion mode and Microprocessor mode Address space 16 Mbytes Memory capacity See Table 1.3 PeripheralPort 87 I/O pins and 1 input pin function Multifunction timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function: 16 bits x 5 channels Waveform generating function: 16 bits x 8 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchro- nous variable length serial I/O, IEBus(1)) Serial I/O 5 channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) A/D converter 10-bit A/D converter: 1 circuit, 26 channels D/A converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt factors Immediate transfer, Calculation transfer and Chain transfer functions DRAMC CAS-before-RAS refresh, self-refresh, EDO, FP CRC calculation circuit CRC-CCITT X Y converter 16 bits x 16 bits Watchdog timer 15 bits x 1 channel (with prescaler) Interrupt 41 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock generating circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation stop detect function Main clock oscillation stop detect function Electric Supply voltage 4.2 V to 5.5 V (f(BCLK)=30 MHz) charact- 3.0 V to 5.5 V (f(BCLK)=20 MHz, through VDC) eristics 3.0 V to 3.6 V (f(BCLK)=20 MHz, not through VDC) Power consumption 28 mA (V CC =5 V, f(BCLK)=30 MHz) 17 mA (VCC =3.3 V, f(BCLK)=20 MHz) 470 µA (VCC =5 V, f(XCIN)=32 kHz, in wait mode) 340 µA (VCC =3.3 V, f(XCIN)=32 kHz, through VDC in wait mode) 5.0 µA (VCC =3.3 V, f(XCIN)=32 kHz, not through VDC in wait mode) 0.4 µA (VCC =5 V, f(XCIN)=32 kHz, in stop mode) 0.4 µA (VCC =3.3 V, f(XCIN)=32 kHz, in stop mode) Operating ambient temperature –20 to 85 oC, –40 to 85oC (optional) Package 100-pin plastic molded LQFP/QFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. All options are on a request basis.

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1.3 Block Diagram

Figure 1.1 shows a block diagram of the M32C/82 group microcomputer. The M32C/82 group microcomputer contains ROM and RAM as memory to store instructions and data, CPU to execute calculations and peripheral functions such as interrupt, timer, serial I/O, DMAC, CRC calculation circuit, A/D converter, D/A converter, DRAMC, intelligent I/O and ports. Figure 1.1 M32C/82 Group Block Diagram Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Port P15 Port P14 Port P13 Port P12 Port P10 Port P9 Port P8P85Port P11 R0H R0L R1H R1L FB SB NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. Included in the 144-pin package only. FLG INTB ISP USP PC SVF SVP VCT Multiplier M32C/80 series CPU core Clock generating circuit XIN - XOUT XCIN - XCOUT On-chip oscillator PLL frequency synthesizer A/D converter 1 circuit Standard 10 inputs Maximum 34 inputs(2) UART/Clock synchronous serial I/O 5 channels XY converter 16 bits x 16 bits CRC calculation circuit (CCITT) X16+X12+X5+1 Timer (16 bits) Timer A 5 channels Timer B 6 channels Three-phase motor control circuit Watchdog timer (15 bits) D/A converter (8-bit x 2 circuits) Intelligent I/O ( 3 groups ) Peripheral functions ROM RAM Memory 87 88 5 (Note1) 88 7 8888888 8 DMAC DMACII DRAMC Time measurement 12 channels(2) Wave generating 20 channels(2) Communication function Clock synchronous serial I/O, UART, IEBus, HDLC data processing

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1.4 Product Information

Renesas plans to release the following products in the M32C/82 group: (1) Support for the masked ROM version (2) ROM/RAM capacity (3) Package 100P6S-A : Plastic molded QFP 100P6Q-A : Plastic molded LQFP 144P6Q-A : Plastic molded LQFP Figure 1.2 ROM/RAM Table 1.3 M32C/82 Group Type number ROM capacity RAM capacity Package type Remarks M30825MW-XXXGP 144P6Q-A M30823MW-XXXGP 320 Kbytes 24 Kbytes 100P6Q-A M30823MW-XXXFP 100P6S-A M30825MH-XXXGP 144P6Q-A M30823MH-XXXGP 384 Kbytes 24 Kbytes 100P6Q-A Masked ROM M30823MH-XXXFP 100P6S-A M30828MH-XXXGP 144P6Q-A M30826MH-XXXGP 384 Kbytes 31 Kbytes 100P6Q-A M30826MH-XXXFP 100P6S-A 24K 384K 31K M30826MH-XXXFP M30826MH-XXXGP M30828MH-XXXGP 320K M30823MW-XXXFP M30823MW-XXXGP M30825MW-XXXGP M30823MH-XXXFP M30823MH-XXXGP M30825MH-XXXGP ROM size (Byte) RAM size (Byte)

08fo4002,10.nuJ02.1.veR page 7 puorG28/C23M 1. Overview Package type options: FP = Package 100P6S-A GP = Package 100P6Q-A, 144P6Q-A ROM capacity: W = 320K bytes H = 384K bytes Memory type: M = Masked ROM version M30 82 3 M H GP M32C/82 Group M16C Family Shows RAM capacity, pin count, etc (Value itself has no specific meaning) Figure 1.3 Product Numbering System

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1.5 Pin Assignments

Figures 1.4 to 1.6 show pin assignments (top view). Figure 1.4 Pin Assignment for 144-Pin Package SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 P146 P145 P144 OUTC1 7 / INPC17 / P143 OUTC1 6 / INPC16 / P142 OUTC1 5 / P141 OUTC1 4 / P140 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 BE0 IN / ISRxD0 / INPC02 / U / TA4OUT / P80 ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 BE0 OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (3)IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 108 107 106 105 104 103 102 101 100 131 132 133 134 135 136 137 138 139 140 141 142 143 144 125 126 127 128 129 130 119 120 121 122 123 124 113 114 115 116 117 118 109 110 111 112 M32C/82 GROUP 144P6Q-A P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss Vcc P12 0 / OUTC30 / ISTxD3 P121 / OUTC31 / ISCLK3 P122 / OUTC32 / ISRxD3 P123 / OUTC33 P124 / OUTC34 P31 / A9 ( MA1 ) ( / D9 ) P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) Vss 2 / A18 ( MA10 ) Vcc 3 / A19 ( MA11 ) D 8 / P10 AN07 / D7 / P07 AN06 / D6 / P06 AN05 / D5 / P05 AN04 / D4 / P04 P114 OUTC1 3 / P113 BE1 IN / ISRxD1 / OUTC12 / INPC12 / P112 ISCLK1 / OUTC11 / INPC11 / P111 BE1 OUT / ISTxD1 / OUTC10 / P110 AN03 / D3 / P03 AN02 / D2 / P02 AN01 / D1 / P01 AN00 / D0 / P00 INPC0 7 / AN157 / P157 INPC0 6 / AN156 / P156 OUTC0 5 / INPC05 / AN155 / P155 OUTC0 4 / INPC04 / AN154 / P154 INPC0 3 / AN153 / P153 BE0 IN / ISRxD0 / INPC02 / AN152 / P152 ISCLK0 / OUTC01 / INPC01 / AN151 / P151 Vss BE0 OUT / ISTxD0 / OUTC00 / INPC00 / AN150 / P150 Vcc KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P125 P126 P127 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P130 / OUTC24 P131 / OUTC25 Vcc P13 2 / OUTC26 Vss P13 3 / OUTC23 P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P134 / OUTC20 / ISTxD2 / IEOUT P135 / OUTC22 / ISRxD2 / IEIN P136 / OUTC21 / ISCLK2 P137 / OUTC27 P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 Vss 6 / RxD1 / SCL1 / STxD1 Vcc 7 / TxD1 / SDA1 / SRxD1 P70(2, 3) NOTES: 1. P6 4 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P7 0 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P7 0 and P71 are ports for the N-channel open drain output.

08fo4002,10.nuJ02.1.veR page 9 puorG28/C23M 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package BYTE CNV SS XCIN/VCONT XCOUT RESET X OUT VSS XIN VCC VCC VSS P96 P95 P94 P93 P92 P91 P90 P146 P145 P144 P143 P142 P141 P140 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P137 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 OUTC2 0/IEOUT /ISTxD2 IEIN/ISRxD2 INPC1 7/OUTC1 7 INPC1 6/OUTC1 6 OUTC1 5 OUTC1 4 INPC0 2/ISRxD0/BE0IN INPC0 1/OUTC0 1/ISCLK0 INPC0 0/OUTC0 0/ISTxD0/BE0OUT INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 OUTC1 0/ISTxD1/BE1OUT OUTC2 2/ISRxD2/IEIN OUTC2 0/ISTxD2/IEOUT OUTC2 1/ISCLK2 OUTC2 7 ANEX1 ANEX0 DA1 DA0 Intelligent I/O pin Bus control pinAnalog pinInterrupt pin Pin No Control pin Port Timer pin UART pin

08fo4002,10.nuJ02.1.veR page 10 puorG28/C23M 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package (Continued) VSS VCC VCC VSS VCC VSS P136 P135 P134 P57 P56 P55 P54 P133 P132 P131 P130 P53 P52 P51 P50 P127 P126 P125 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P124 P123 P122 P121 P120 P30 P27 P26 P25 Timer pin UART pin OUTC2 1/ISCLK2 OUTC2 2/ISRxD2/IEIN OUTC2 0/ISTxD2/IEOUT OUTC2 3 OUTC2 6 OUTC2 5 OUTC2 4 AN2 7 AN2 6 AN2 5 RDY ALE/RAS HOLD HLDA/ALE CLK OUT /BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL CS0/A CS1/A22 CS2/A21 CS3/A20(MA 12) A19(MA 11) A18(MA 10) A17(MA 9) A16(MA 8) A15(MA 7)(/D15) A14(MA 6)(/D14) A13(MA 5)(/D13) A12(MA 4)(/D12) A11(MA 3)(/D11) A10(MA 2)(/D10) A9(MA 1)(/D9) A8(MA 0)(/D8) A7(/D7) A6(/D6) A5(/D5) Intelligent I/O pin Bus control pinAnalog pinInterrupt pin Pin No Control pin Port

08fo4002,10.nuJ02.1.veR page 11 puorG28/C23M 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package (Continued) 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS VCC AV SS VREF AV CC P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P114 P113 P112 P111 P110 P03 P02 P01 P00 P157 P156 P155 P154 P153 P152 P151 P150 P107 P106 P105 P104 P103 P102 P101 P100 P97 INT5 INT4 INT3 KI KI2 KI1 KI0 Timer pin RxD4/SCL4/STxD4 AN2 4 AN2 3 AN2 2 AN2 1 AN2 0 AN0 7 AN0 6 AN0 5 AN0 4 AN0 3 AN0 2 AN0 1 AN0 0 AN15 7 AN15 6 AN15 5 AN15 4 AN15 3 AN15 2 AN15 1 AN15 0 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 AD TRG A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Bus control pinAnalog pinInterrupt pin Pin No OUTC1 3 INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 OUTC1 0/ISTxD1/BE1OUT INPC0 7 INPC0 6 INPC0 5/OUTC0 5 INPC0 4/OUTC0 4 INPC0 3 INPC0 2/ISRxD0/BE0IN INPC0 1/OUTC0 1/ISCLK0 INPC0 0/OUTC0 0/ISTxD0/BE0OUT Control pin Port UART pin Intelligent I/O pin

08fo4002,10.nuJ02.1.veR page 12 puorG28/C23M 1. Overview Figure 1.5 Pin assignment for 100-Pin Package 100 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 BE0 OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (3)IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 (3)IEOUT / ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70 P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P10 / D8 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss Vcc P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) P42 / A18 ( MA10 ) P43 / A19 ( MA11 ) D 7 / AN07 / P07 D 6 / AN06 / P06 D 5 / AN05 / P05 D 4 / AN04 / P04 D 3 / AN03 / P03 D 2 / AN02 / P02 D 1 / AN01 / P01 D 0 / AN00 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc (2)P97 M32C/82 GROUP 100P6S-A NOTES: 1. P6 4 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P9 7 / ADTRG / RxD4 / STxD4 / SCL4 3. P7 0 and P71 are ports for the N-channel open drain output.

08fo4002,10.nuJ02.1.veR page 13 puorG28/C23M 1. Overview Figure 1.6 Pin Assignment for 100-Pin Package 100 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN/ ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 BE0 OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1 IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1 OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 P42 / A18 ( MA10 ) P43 / A19 ( MA11 ) P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70(2, 4) P71(3, 4) P72 / TA1OUT / V / CLK2 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss Vcc P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) D 10 / P12 D 9 / P11 D 8 / P10 D 7 / AN07 / P07 D 6 / AN06 / P06 D 5 / AN05 / P05 D 4 / AN04 / P04 D 3 / AN03 / P03 D 2 / AN02 / P02 D 1 / AN01 / P01 D 0 / AN00 / P00 KI3 / AN37 / P107 KI2 / AN36 / P106 KI1 / AN35 / P105 KI0 / AN34 / P104 AN3 3 / P103 AN3 2 / P102 AN3 1 / P101 AVss AN3 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 M32C/82 GROUP 100P6Q-A NOTES: 1. P6 4 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P7 0 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P7 1 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22 / ISRxD2 / IEIN 4. P7 0 and P71 are ports for the N-channel open drain output.

08fo4002,10.nuJ02.1.veR page 14 puorG28/C23M 1. Overview Table 1.5 Pin Characteristics for 100-Pin Package BYTE CNV SS XCIN/VCONT XCOUT RESET X OUT VSS XIN VCC P96 P95 P94 P93 P92 P91 P90 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 OUTC2 0/IEOUT /ISTxD2 IEIN/ISRxD2 INPC0 2/ISRxD0/BE0IN INPC0 1/OUTC0 1/ISCLK0 INPC0 0/OUTC0 0/ISTxD0/BE0OUT INPC1 2/OUTC1 2/ISRxD1/BE1IN INPC1 1/OUTC1 1/ISCLK1 OUTC1 0/ISTxD1/BE1OUT OUTC2 2/ISRxD2/IEIN OUTC2 0/ISTxD2/IEOUT OUTC2 1/ISCLK2 ANEX1 ANEX0 DA1 DA0 100 RDY ALE/RAS HOLD HLDA/ALE CLK OUT /BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL CS0/A CS1/A22 CS2/A21 CS3/A20(MA 12) Package Pin No FP GP Control pin Port Timer pin UART pin Intelligent I/O pin Bus control pin Analog pin Interrupt pin

08fo4002,10.nuJ02.1.veR page 15 puorG28/C23M 1. Overview Table 1.5 Pin Characteristics for 100-Pin Package (Continued) 100 VCC VSS AV SS VREF AV CC P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 P100 P97 Timer pin UART pin AN2 7 AN2 6 AN2 5 AN2 4 AN2 3 AN2 2 AN2 1 AN2 0 AN0 7 AN0 6 AN0 5 AN0 4 AN0 3 AN0 2 AN0 1 AN0 0 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 AD TRG A19(MA 11) A18(MA 10) A17(MA 9) A16(MA 8) A15(MA 7)(/D15) A14(MA 6)(/D14) A13(MA 5)(/D13) A12(MA 4)(/D12) A11(MA 3)(/D11) A10(MA 2)(/D10) A9(MA 1)(/D9) A8(MA 0)(/D8) A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Intelligent I/O pin Bus control pinAnalog pin Interrupt pin INT5 INT4 INT3 KI KI2 KI1 KI0 RxD4/SCL4/STxD4 FP GP Package pin No Control pin Port

08fo4002,10.nuJ02.1.veR page 16 puorG28/C23M 1. Overview

1.6 Pin Description

Table 1.6 Pin Description (100-Pin and 144-Pin Packages) Apply 3.0 to 5.5 V to the VCC pins. Apply 0 V to the VSS pin. Switches processor mode. Connect this pin to VSS to start up in single-chip mode (memory expansion mode). Connect this pin to VCC to start up in microprocessor mode. The microcomputer is in a reset state when applying "L" to the RESET pin. I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT . To use an external clock, input the clock to XIN and leave XOUT open. Switches the data bus in external memory space 3. The data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when the BYTE pin is held "H". Set to either. Connect this pin to VSS when an external bus is not used. Applies power supply for the A/D converter and D/A converter. Connect this pin to VCC. Applies power supply for the A/D converter and D/A converter. Connect this pin to VSS. Applies reference voltage for the A/D converter. 8-bit I/O ports in CMOS having a direction register to select input or output. Each pin is set as an input port or output port. An input port in single-chip mode can be set for a pull-up or for no pull-up in 4-bit unit by program. When these pins are used as bus control pins in memory expansion mode and microprocessor mode, internal pull-up resistor cannot be selected. Ports used as input ports can be set for a pull-up or for no pull-up in the modes above. Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. Analog input pins for the A/D converter 8-bit I/O ports having equivalent functions to P0 Input pins for the INT interrupt Inputs and outputs data (D8 to D15) when these pins are set as the separate bus. 8-bit I/O ports having equivalent functions to P0 Outputs 8 low-order address bits (A0 to A7). Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing when these pins are set as the multiplexed bus. Analog input pins for A/D converter 8-bit I/O ports having equivalent functions to P0 Outputs 8 middle-order address bits (A8 to A15). Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing when external 16-bit data bus is set as the multi- plexed bus. Outputs row addresses and column addresses by time-sharing when accessing the DRAM area. V CC VSS CNV SS RESET XIN XOUT BYTE AV CC AV SS VREF P00 to P07 D 0 to D7 AN0 0 to AN07 P10 to P17 INT3 to INT5 D 8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 AN2 0 to AN27 P30 to P37 A8 to A15 A8/D8 to A15/D15 MA 0 to MA7 Power supply input CNV SS Reset input Clock input Clock output Input to switch external data bus width Analog power supply input Analog power supply input Reference voltage input I/O port P0 Data bus Analog input pin I/O port P1 INT interrupt input pin Data bus I/O port P2 Address bus Address bus/data bus Analog input pin I/O port P3 Address bus Address bus/data bus Address bus I I I I I O I I I I I/O I/O I I/O I I/O I/O O I/O I I/O O I/O O Symbol Function I/O type Description I : Input O : Output I/O : Input and output

08fo4002,10.nuJ02.1.veR page 17 puorG28/C23M 1. Overview Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) P40 to P47 A16 to A22, A23 CS0 to CS3 MA 8 to MA12 P50 to P57 CLK OUT WRL WR WRH BHE RD BCLK HLDA HOLD ALE RDY DW CASL CASH RAS P60 to P67 CTS0, CTS1 RTS0, RTS1 SS0, SS1 CLK0, CLK1 RxD0, RxD1 SCL0, SCL1 STxD0, STxD1 TxD0, TxD1 SDA0, SDA1 SRxD0, SRxD1 ISCLK2 OUTC2 I/O port P4 Address bus Chip-select Address bus I/O port P5 Clock output Bus control pin DRAM bus control pin I/O port P6 UART pin Intelligent I/O pin I/O O O O I/O O O O O O O O O I O I O O O O I/O I O I I/O I I/O O O I/O I I/O O 8-bit I/O ports having equivalent functions to P0 Outputs 8 high-order address bits (A16 to A22, A23). The highest-order bit (A23) inversed is also output. Outputs CS0 to CS3 signals. CS0 to CS3 are chip-select signals specifying an external space. Outputs row addresses and column addresses by time-sharing when accessing the DRAM area. 8-bit I/O ports having equivalent functions to P0 Outputs the main clock divided by 8 or divided by 32 or the clock having the same frequency as the sub clock from P53. Outputs WRL, WRH, (WR, BHE), RD, BCLK, HLDA and ALE signals. WRL and WRH or BHE and WR can be switched by program. WRL, WRH and RD are selected The WRL signal becomes "L" by writing data to an even address in an external memory space. The WRH signal becomes "L" by writing data to an odd address in an external memory space. The RD pin signal becomes "L" by reading data in an external memory space. WR, BHE and RD are selected The WR signal becomes "L" by writing data to an external memory space. The RD signal becomes "L" by reading data in an external memory space. The BHE signal becomes "L" by accessing an odd address. Select WR, BHE and RD for an external 8-bit data bus. While the HOLD pin is held "L", the microcomputer is placed in a hold state. In a hold state, HLDA outputs a "L" signal. ALE is a signal latching the address. While the RDY pin is held "L", the microcomputer is placed in a wait state. The DW signal becomes "L" by writing data to the DRAM area. CASL and CASH are signals indicating a timing to latch column addresses. The CASL signal becomes "L" by accessing an even address. The CASH signal becomes "L" by accessing an odd address. RAS is a signal latching row addresses. 8-bit I/O ports having equivalent functions to P0 I/O pins for UART0 (P6 0 to P63) and UART1 (P64 to P67) ISCKL2 inputs and outputs the clock for the intelligent I/O communication function. OUTC2 1 outputs the clock for the waveform generating function. I : Input O : Output I/O : Input and output Symbol Function I/O type Description

08fo4002,10.nuJ02.1.veR page 18 puorG28/C23M 1. Overview P70 to P77 TA0 OUT to TA3OUT TA0 IN to TA3IN TB5 IN ___ V, V ___ W, W CTS2 RTS2 SS2 CLK2 RxD2 SCL2 STxD2 TxD2 SDA2 SRxD2 INPC0 0, INPC01 INPC1 1, INPC12 OUTC0 0, OUTC01 OUTC1 0 to OUTC12 OUTC2 0, OUTC22 ISCLK0, ISCLK1 ISTxD0 to ISTxD2 ISRxD1, ISRxD2 IEOUT IEIN BE0 OUT BE1 OUT BE1 IN I/O port P7 Timer A pin Timer B pin Three-phase motor control output pin UART pin Intelligent I/O pin 8-bit I/O ports having equivalent functions to P0 (P70 and P71 are ports for the N-channel open drain output.) I/O pins for timer A0 to A3 Input pin for timer B5 V-phase output pin W-phase output pin I/O pins for UART2 INPC0 0, INPC01, INPC11 and INPC12 are input pins for the time measure- ment function. OUTC0 0, OUTC01, OUTC10 to OUTC12, OUTC20 and OUTC2 2 are output pins for the waveform generating function. ISCLK0 and ISCLK1 input and output the clock for the intelligent I/O communi- cation function. ISRxD1, ISRxD2, IEIN and BE1IN input received data for the intelligent I/O communication function. ISTxD0 to ISTxD2, IEOUT, BE0OUT and BE1OUT output transmit data for the intelligent I/O communication function. I/O I/O I I O O I O I I/O I I/O O O I/O I I O I/O O I O I O O I I : Input O : Output I/O : Input and output Symbol Function I/O type Description Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)

08fo4002,10.nuJ02.1.veR page 19 puorG28/C23M 1. Overview P80 to P84, P86, P87 XCIN XCOUT VCONT TA4 OUT TA4 IN ___ U, U INT0 to INT2 INPC0 2 ISRxD0 BE0 IN P85/NMI P90 to P97 TB0 IN to TB4IN CTS3, CTS4 RTS3, RTS4 SS3, SS4 CLK3, CLK4 RxD3, RxD4 SCL3, SCL4 STxD3, STxD4 TxD3, TxD4 SDA3, SDA4 SRxD3, SRxD4 DA0, DA1 ANEX0, ANEX1, AD TRG OUTC2 0 ISTxD2 IE OUT IEIN ISRxD2 P10 0 to P107 KI0 to KI3 AN 0 to AN7 I/O port P8 Sub clock Low-pass filter connect pin for PLL frequency synthesizer pin Timer A pin Three-phase motor control output pin INT interrupt input pin Intelligent I/O pin NMI interrupt input pin I/O port P9 Timer B pin UART pin D/A output pin A/D related pin Intelligent I/O pin I/O port P10 Key input interrupt pin Analog input pin I/O I O I/O I O I I I I I I/O I I O I I/O I I/O O O I/O I O I/O I I O O O I I I/O I I I/O ports having equivalent functions to P0 I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT . Connects the low-pass filter to the VCONT pin when using the PLL frequency synthesizer. Connect P86 to VSS to stabilize the PLL frequency. I/O pins for timer A4 U-phase output pins Input pins for the INT interrupt INPC0 2 is an input pin for the time measurement function. ISRxD0 and BE0IN input received data for the intelligent I/O communication function. Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. 8-bit I/O ports having equivalent functions P0. The PRCR register prevents PD9 and PS3 registers from rewriting. Input pins for timers B0 to B4 I/O pins for UART3 (P90 to P93) and UART4 (P94 to P97) Output pins for the D/A converter ANEX0 is an extended analog I/O pin for the A/D converter. ANEX1 is an extended analog input pin for the A/D converter. AD TRG is an A/D trigger input pin. OUTC2 0 is an output pin for the waveform generating function. ISTxD2 and IEOUT output transmit data for the intelligent I/O communication function. ISRxD2 and IEIN input received data for the intelligent I/O communication function. 8-bit I/O ports having equivalent functions to P0 Input pins for the key input interrupt Analog input pins for the A/D converter I : Input O : Output I/O : Input and output Symbol Function I/O type Description Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)

08fo4002,10.nuJ02.1.veR page 20 puorG28/C23M 1. Overview P11 0 to P114 INPC11, INPC12 OUTC1 0 to OUTC13 ISCLK1 ISRxD1 BE1 IN ISTxD1 BE1 OUT P12 0 to P127 P13 0 to P137 OUTC2 0 to OUTC27 ISCLK2 ISRxD2 IE IN ISTxD2 IE OUT P14 0 to P146 INPC16, INPC17 OUTC1 4 to OUTC17 P15 0 to P157 INPC00 to INPC07 OUTC0 0, OUTC01 OUTC0 4, OUTC05 ISCLK0 ISRxD0 BE0 IN ISTxD0 BE0 OUT AN15 0 to AN157 I/O port P11 Intelligent I/O pin I/O port P12 I/O port P13 Intelligent I/O pinI/O port P14 Intelligent I/O pin I/O port P15 Intelligent I/O pin Analog input port I/O I O I/O I I O O I/O I/O O I/O I I O O I/O I O I/O I O I/O I I O O I 5-bit I/O ports having equivalent functions to P0. INPC1 1 and INPC12 are input pins for the time measurement function. OUTC1 0 to OUTC13 are output pins for the waveform generating function. ISCLK1 inputs and outputs the clock for the intelligent I/O communication function. ISRxD1 and BE1IN input received data for the intelligent I/O communication function. ISTxD1 and BE1OUT output transmit data for the intelligent I/O communication function. 8-bit I/O ports having equivalent functions to P0 8-bit I/O ports having equivalent functions to P0 OUTC2 0 to OUTC27 are output pins for the waveform generating function. ISCLK2 inputs and outputs the clock for the intelligent I/O communication function. ISRxD2 and IEIN input received data for the intelligent I/O communication function. ISTxD2 and IEOUT output transmit data for the intelligent I/O communication function. 7-bit I/O ports having equivalent functions to P0 INPC1 6 and INPC17 are input pins for the time measurement function. OUTC1 4 to OUTC17 are output pins for the waveform generating function. 8-bit I/O ports having equivalent functions to P0 INPC0 0 to INPC07 are input pins for the time measurement function. OUTC0 0, OUTC01, OUTC0 4 and OUTC0 5 are output pins for the waveform generating function. ISCLK0 inputs and outputs the clock for the intelligent I/O communication function. ISRxD0 and BE0IN input received data for the intelligent I/O communication function. ISTxD0 and BE0OUT output transmit data for the intelligent I/O communication function. Analog input pins for the A/D converter Symbol Function I/O type Description I : Input O : Output I/O : Input and output Table 1.6 Pin Description (144-Pin Package only) (Continued)

page 22 08fo4002,10.nuJ02.1.veR puorG28/C23M 2. Central Processing Unit (CPU)

2.1 General Register

2.1.1 Data Registers (R0, R1, R2 and R3)

R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R3R1.

2.1.2 Address Registers (A0 and A1)

A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith- metic and logic operations.

2.1.3 Static Base Register (SB)

SB is a 24-bit register for SB-relative addressing.

2.1.4 Frame Base Register (FB)

FB is a 24-bit register for FB-relative addressing.

2.1.5 Program Counter (PC)

PC is 24 bits wide. It indicates an address of an instruction to be executed.

2.1.6 Interrupt Table Register (INTB)

INTB is a 24-bit register indicating a starting address of an interrupt vector table.

2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

USP and ISP as the stack pointer are 24 bits wide. The U flag can switch USP to ISP and vice versa. Refer to "2.1.8 Flag Register (FLG)" about the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.

2.1.8 Flag Register (FLG)

FLG is a 16-bit register indicating a CPU state.

2.1.8.1 Carry Flag (C)

The C flag indicates whether carry or borrow occurs after an instruction is executed.

2.1.8.2 Debug Flag (D)

The D flag is for debug only. Set to "0".

2.1.8.3 Zero Flag (Z)

The Z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0".

2.1.8.4 Sign Flag (S)

The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0".

page 23 08fo4002,10.nuJ02.1.veR puorG28/C23M 2. Central Processing Unit (CPU)

2.1.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1".

2.1.8.6 Overflow Flag (O)

The O flag is set to "1" when a result of an arithmetic operation overflows; otherwise "0".

2.1.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0" and is enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged.

2.1.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.1.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide. It assigns an interrupt priority levels from level 0 to level 7. If a requested interrupt has a greater priority than IPL, the interrupt is enabled.

2.1.8.10 Reserved Space

When writing to the reserved space, set to "0". When read, its content is indeterminate.

2.2 High-Speed Interrupt Registers

Registers associated with the high-speed interrupt are as follows. - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT)

2.3 DMAC-associated Registers

Registers associated with DMAC are as follows. - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1)

08fo4002,10.nuJ02.1.veR page 25 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 000016 000116 000216 000316 1000 00002 (CNVss pin ="L")

000416 Processor mode register 0 PM0 0000 00112 (CNVss pin ="H")

000516 Processor mode register 1 PM1 0X00 0000 2

000616 System clock control register 0 CM0 0000 X000 2

000716 System clock control register 1 CM1 0010 0000 2

000816 Wait control register WCR 1111 1111 2

000916 Address match interrupt enable register AIER XXXX 0000 2

000A 16 Protect register PRCR XXXX 0000 2 XXXX 1000 2 (BYTE pin ="L") 000B 16 External data bus width control register DS XXXX 0000 2 (BYTE pin ="H") 000C 16 Main clock division register MCD XXX0 1000 2 000D 16 Oscillation stop detect register CM2 00 16 000E 16 Watchdog timer start register WDTS XX 16 000F16 Watchdog timer control register WDC 000X XXXX 2 001016

001116 Address match interrupt register 0 RMAD0 000000 16

001516 Address match interrupt register 1 RMAD1 000000 16

001716 VDC control register for PLL PLV XXXX XX01 2

001916 Address match interrupt register 2 RMAD2 000000 16

001B 16 VDC control register 0 VDC0 00 16 001C 16 001D 16 Address match interrupt register 3 RMAD3 000000 16 001E 16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A 16 002B 16 002C 16 002D16 002E 16 002F16 X: Indeterminate Blank spaces are reserved. No access is allowed. 4. Special Function Registers (SFR)

08fo4002,10.nuJ02.1.veR page 26 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A 16 003B 16 003C 16 003D 16 003E 16 003F16

004016 DRAM control register DRAMCONT XX 16

004116 DRAM refresh interval set register REFCNT XX 16

X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 27 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 006016 006116 006216 006316 006416 006516 006616 006716

006816 DMA0 interrupt control register DM0IC XXXX X000 2

006916 Timer B5 interrupt control register TB5IC XXXX X000 2

006A 16 DMA2 interrupt control register DM2IC XXXX X000 2 006B 16 UART2 receive /ACK interrupt control register S2RIC XXXX X000 2 006C 16 Timer A0 interrupt control register TA0IC XXXX X000 2 006D 16 UART3 receive /ACK interrupt control register S3RIC XXXX X000 2 006E 16 Timer A2 interrupt control register TA2IC XXXX X000 2 006F16 UART4 receive /ACK interrupt control register S4RIC XXXX X000 2

007016 Timer A4 interrupt control register TA4IC XXXX X000 2

007116 UART0/UART3 bus conflict detect interrupt control register BCN0IC/BCN3IC XXXX X000 2

007216 UART0 receive/ACK interrupt control register S0RIC XXXX X000 2

007316 A/D0 conversion interrupt control register AD0IC XXXX X000 2

007416 UART1 receive/ACK interrupt control register S1RIC XXXX X000 2

007516 Intelligent I/O interrupt control register 0 IIO0IC XXXX X000 2

007616 Timer B1 interrupt control register TB1IC XXXX X000 2

007716 Intelligent I/O interrupt control register 2 IIO2IC XXXX X000 2

007816 Timer B3 interrupt control register TB3IC XXXX X000 2

007916 Intelligent I/O interrupt control register 4 IIO4IC XXXX X000 2

007A 16 INT5 interrupt control register INT5IC XX00 X000 2 007B 16 Intelligent I/O interrupt control register 6 IIO6IC XXXX X000 2 007C 16 INT3 interrupt control register INT3IC XX00 X000 2 007D 16 Intelligent I/O interrupt control register 8 IIO8IC XXXX X000 2 007E 16 INT1 interrupt control register INT1IC XX00 X000 2 007F16 Intelligent I/O interrupt control register 10 IIO10IC XXXX X000 2 008016

008116 Intelligent I/O interrupt control register 11 IIO11IC XXXX X000 2

008816 DMA1 interrupt control register DM1IC XXXX X000 2

008916 UART2 transmit /NACK interrupt control register S2TIC XXXX X000 2

008A 16 DMA3 interrupt control register DM3IC XXXX X000 2 008B 16 UART3 transmit /NACK interrupt control register S3TIC XXXX X000 2 008C 16 Timer A1 interrupt control register TA1IC XXXX X000 2 008D 16 UART4 transmit /NACK interrupt control register S4TIC XXXX X000 2 008E 16 Timer A3 interrupt control register TA3IC XXXX X000 2 008F16 UART2 bus conflict detect interrupt control register BCN2IC XXXX X000 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 28 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET

009016 UART0 transmit /NACK interrupt control register S0TIC XXXX X000 2

009116 UART1/UART4 bus conflict detect interrupt control register BCN1IC/BCN4IC XXXX X000 2

009216 UART1 transmit/NACK interrupt control register S1TIC XXXX X000 2

009316 Key input interrupt control register KUPIC XXXX X000 2

009416 Timer B0 interrupt control register TB0IC XXXX X000 2

009516 Intelligent I/O interrupt control register 1 IIO1IC XXXX X000 2

009616 Timer B2 interrupt control register TB2IC XXXX X000 2

009716 Intelligent I/O interrupt control register 3 IIO3IC XXXX X000 2

009816 Timer B4 interrupt control register TB4IC XXXX X000 2

009916 Intelligent I/O interrupt control register 5 IIO5IC XXXX X000 2

009A 16 INT4 interrupt control register INT4IC XX00 X000 2 009B 16 Intelligent I/O interrupt control register 7 IIO7IC XXXX X000 2 009C 16 INT2 interrupt control register INT2IC XX00 X000 2 009D 16 Intelligent I/O interrupt control register 9 IIO9IC XXXX X000 2 009E 16 INT0 interrupt control register INT0IC XX00 X000 2 009F16 Exit priority control register RLVL XXXX 0000 2 00A0 16 Interrupt request register 0 IIO0IR 0000 000X 2 00A1 16 Interrupt request register 1 IIO1IR 0000 000X 2 00A2 16 Interrupt request register 2 IIO2IR 0000 000X 2 00A3 16 Interrupt request register 3 IIO3IR 0000 000X 2 00A4 16 Interrupt request register 4 IIO4IR 0000 000X 2 00A5 16 Interrupt request register 5 IIO5IR 0000 000X 2 00A6 16 Interrupt request register 6 IIO6IR 0000 000X 2 00A7 16 Interrupt request register 7 IIO7IR 0000 000X 2 00A8 16 Interrupt request register 8 IIO8IR 0000 000X 2 00A9 16 Interrupt request register 9 IIO9IR 0000 000X 2 00AA 16 Interrupt request register 10 IIO10IR 0000 000X 2 00AB 16 Interrupt request register 11 IIO11IR 0000 000X 2 00AC 16 00AD 16 00AE 16 00AF 16 00B0 16 Interrupt enable register 0 IIO0IE 00 16 00B1 16 Interrupt enable register 1 IIO1IE 00 16 00B2 16 Interrupt enable register 2 IIO2IE 00 16 00B3 16 Interrupt enable register 3 IIO3IE 00 16 00B4 16 Interrupt enable register 4 IIO4IE 00 16 00B5 16 Interrupt enable register 5 IIO5IE 00 16 00B6 16 Interrupt enable register 6 IIO6IE 00 16 00B7 16 Interrupt enable register 7 IIO7IE 00 16 00B8 16 Interrupt enable register 8 IIO8IE 00 16 00B9 16 Interrupt enable register 9 IIO9IE 00 16 00BA 16 Interrupt enable register 10 IIO10IE 00 16 00BB 16 Interrupt enable register 11 IIO11IE 00 16 00BC 16 00BD 16 00BE 16 00BF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 29 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 00C0 16 XX 16 Group 0 time measurement/waveform generating register 0 G0TM0/G0PO000C1 16 XX 16 00C2 16 XX 16 Group 0 time measurement/waveform generating register 1 G0TM1/G0PO100C3 16 XX 16 00C4 16 XX 16 Group 0 time measurement/waveform generating register 2 G0TM2/G0PO200C5 16 XX 16 00C6 16 XX 16 Group 0 time measurement/waveform generating register 3 G0TM3/G0PO300C7 16 XX 16 00C8 16 XX 16 Group 0 time measurement/waveform generating register 4 G0TM4/G0PO400C9 16 XX 16 00CA 16 XX 16 Group 0 time measurement/waveform generating register 5 G0TM5/G0PO500CB 16 XX 16 00CC 16 XX 16 Group 0 time measurement/waveform generating register 6 G0TM6/G0PO600CD 16 XX 16 00CE 16 XX 16 Group 0 time measurement/waveform generating register 7 G0TM7/G0PO700CF 16 XX 16 00D0 16 Group 0 waveform generating control register 0 G0POCR0 0X00 X000 2 00D1 16 Group 0 waveform generating control register 1 G0POCR1 0X00 X000 2 00D2 16 Group 0 waveform generating control register 2 G0POCR2 0X00 X000 2 00D3 16 Group 0 waveform generating control register 3 G0POCR3 0X00 X000 2 00D4 16 Group 0 waveform generating control register 4 G0POCR4 0X00 X000 2 00D5 16 Group 0 waveform generating control register 5 G0POCR5 0X00 X000 2 00D6 16 Group 0 waveform generating control register 6 G0POCR6 0X00 X000 2 00D7 16 Group 0 waveform generating control register 7 G0POCR7 0X00 X000 2 00D8 16 Group 0 time measurement control register 0 G0TMCR0 00 16 00D9 16 Group 0 time measurement control register 1 G0TMCR1 00 16 00DA 16 Group 0 time measurement control register 2 G0TMCR2 00 16 00DB 16 Group 0 time measurement control register 3 G0TMCR3 00 16 00DC 16 Group 0 time measurement control register 4 G0TMCR4 00 16 00DD 16 Group 0 time measurement control register 5 G0TMCR5 00 16 00DE 16 Group 0 time measurement control register 6 G0TMCR6 00 16 00DF 16 Group 0 time measurement control register 7 G0TMCR7 00 16 00E0 16 XX 16 Group 0 base timer register G0BT00E1 16 XX 16 00E2 16 Group 0 base timer control register 0 G0BCR0 00 16 00E3 16 Group 0 base timer control register 1 G0BCR1 00 16 00E4 16 Group 0 time measurement prescaler register 6 G0TPR6 00 16 00E5 16 Group 0 time measurement prescaler register 7 G0TPR7 00 16 00E6 16 Group 0 function enable register G0FE 00 16 00E7 16 Group 0 function select register G0FS 00 16 00E8 16 XXXX XXXX 2 Group 0 SI/O receive buffer register G0RB00E9 16 XX00 XXXX 2 00EA 16 Group 0 transmit buffer/receive data register G0TB/G0DR XX 16 00EB 16 00EC 16 Group 0 receive input register G0RI XX 16 00ED 16 Group 0 SI/O communication mode register G0MR 00 16 00EE 16 Group 0 transmit output register G0TO XX 16 00EF 16 Group 0 SI/O communication control register G0CR 0000 X000 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 30 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 00F016 Group 0 data compare register 0 G0CMP0 XX 16 00F116 Group 0 data compare register 1 G0CMP1 XX 16 00F216 Group 0 data compare register 2 G0CMP2 XX 16 00F316 Group 0 data compare register 3 G0CMP3 XX 16 00F416 Group 0 data mask register 0 G0MSK0 XX 16 00F516 Group 0 data mask register 1 G0MSK1 XX 16 00F616 00F716 00F816 XX 16 Group 0 receive CRC code register G0RCRC00F916 XX 16 00FA 16 0016 Group 0 transmit CRC code register G0TCRC00FB 16 0016 00FC 16 Group 0 SI/O extended mode register G0EMR 00 16 00FD 16 Group 0 SI/O extended receive control register G0ERC 00 16 00FE 16 Group 0 SI/O special communication interrupt detect register G0IRF 0000 00XX 2 00FF 16 Group 0 SI/O extended transmit control register G0ETC 0000 0XXX 2

010016 XX 16

Group 1 time measurement/waveform generating register 0 G1TM0/G1PO0010116 XX 16

010216 XX 16

Group 1 time measurement/waveform generating register 1 G1TM1/G1PO1010316 XX 16

010416 XX 16

Group 1 time measurement/waveform generating register 2 G1TM2/G1PO2010516 XX 16

010616 XX 16

Group 1 time measurement/waveform generating register 3 G1TM3/G1PO3010716 XX 16

010816 XX 16

Group 1 time measurement/waveform generating register 4 G1TM4/G1PO4010916 XX 16 010A 16 XX 16 Group 1 time measurement/waveform generating register 5 G1TM5/G1PO5010B 16 XX 16 010C 16 XX 16 Group 1 time measurement/waveform generating register 6 G1TM6/G1PO6010D 16 XX 16 010E 16 XX 16 Group 1 time measurement/waveform generating register 7 G1TM7/G1PO7010F16 XX 16

011016 Group 1 waveform generating control register 0 G1POCR0 0X00 X000 2

011116 Group 1 waveform generating control register 1 G1POCR1 0X00 X000 2

011216 Group 1 waveform generating control register 2 G1POCR2 0X00 X000 2

011316 Group 1 waveform generating control register 3 G1POCR3 0X00 X000 2

011416 Group 1 waveform generating control register 4 G1POCR4 0X00 X000 2

011516 Group 1 waveform generating control register 5 G1POCR5 0X00 X000 2

011616 Group 1 waveform generating control register 6 G1POCR6 0X00 X000 2

011716 Group 1 waveform generating control register 7 G1POCR7 0X00 X000 2

011816 Group 1 time measurement control register 0 G1TMCR0 00 16

011916 Group 1 time measurement control register 1 G1TMCR1 00 16

011A 16 Group 1 time measurement control register 2 G1TMCR2 00 16 011B 16 Group 1 time measurement control register 3 G1TMCR3 00 16 011C 16 Group 1 time measurement control register 4 G1TMCR4 00 16 011D 16 Group 1 time measurement control register 5 G1TMCR5 00 16 011E 16 Group 1 time measurement control register 6 G1TMCR6 00 16 011F16 Group 1 time measurement control register 7 G1TMCR7 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 31 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET

012016 XX 16

Group 1 base timer register G1BT012116 XX 16

012216 Group 1 base timer control register 0 G1BCR0 00 16

012316 Group 1 base timer control register 1 G1BCR1 00 16

012416 Group 1 time measurement prescaler register 6 G1TPR6 00 16

012516 Group 1 time measurement prescaler register 7 G1TPR7 00 16

012616 Group 1 function enable register G1FE 00 16

012716 Group 1 function select register G1FS 00 16

012816 XXXX XXXX 2

Group 1 SI/O receive buffer register G1RB012916 XX00 XXXX 2 012A 16 Group 1 transmit buffer/receive data register G1TB/G1DR XX 16 012B 16 012C 16 Group 1 receive input register G1RI XX 16 012D 16 Group 1 SI/O communication mode register G1MR 00 16 012E 16 Group 1 transmit output register G1TO XX 16 012F16 Group 1 SI/O communication control register G1CR 0000 X000 2

013016 Group 1 data compare register 0 G1CMP0 XX 16

013116 Group 1 data compare register 1 G1CMP1 XX 16

013216 Group 1 data compare register 2 G1CMP2 XX 16

013316 Group 1 data compare register 3 G1CMP3 XX 16

013416 Group 1 data mask register 0 G1MSK0 XX 16

013516 Group 1 data mask register 1 G1MSK1 XX 16

013816 XX 16

Group 1 receive CRC code register G1RCRC013916 XX 16 013A 16 0016 Group 1 transmit CRC code register G1TCRC013B 16 0016 013C 16 Group 1 SI/O extended mode register G1EMR 00 16 013D 16 Group 1 SI/O extended receive control register G1ERC 00 16 013E 16 Group 1 SI/O special communication interrupt detect register G1IRF 0000 00XX 2 013F16 Group 1 SI/O extended transmit control register G1ETC 0000 0XXX 2

014016 XX 16

Group 2 waveform generating register 0 G2PO0014116 XX 16

014216 XX 16

Group 2 waveform generating register 1 G2PO1014316 XX 16

014416 XX 16

Group 2 waveform generating register 2 G2PO2014516 XX 16

014616 XX 16

Group 2 waveform generating register 3 G2PO3014716 XX 16

014816 XX 16

Group 2 waveform generating register 4 G2PO4014916 XX 16 014A 16 XX 16 Group 2 waveform generating register 5 G2PO5014B 16 XX 16 014C 16 XX 16 Group 2 waveform generating register 6 G2PO6014D 16 XX 16 014E 16 XX 16 Group 2 waveform generating register 7 G2PO7014F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 32 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET

015016 Group 2 waveform generating control register 0 G2POCR0 00 16

015116 Group 2 waveform generating control register 1 G2POCR1 00 16

015216 Group 2 waveform generating control register 2 G2POCR2 00 16

015316 Group 2 waveform generating control register 3 G2POCR3 00 16

015416 Group 2 waveform generating control register 4 G2POCR4 00 16

015516 Group 2 waveform generating control register 5 G2POCR5 00 16

015616 Group 2 waveform generating control register 6 G2POCR6 00 16

015716 Group 2 waveform generating control register 7 G2POCR7 00 16

016016 XX 16

Group 2 base timer register G2BT016116 XX 16

016216 Group 2 base timer control register 0 G2BCR0 00 16

016316 Group 2 base timer control register 1 G2BCR1 00 16

016416 Base timer start register BTSR XXXX 0000 2

016616 Group 2 function enable register G2FE 00 16

016716 Group 2 RTP output buffer register G2RTP 00 16

016A 16 Group 2 SI/O communication mode register G2MR 00XX X000 2 016B 16 Group 2 SI/O communication control register G2CR 0000 X000 2 016C 16 XX 16 Group 2 SI/O transmit buffer register G2TB016D 16 XX 16 016E 16 XX 16 Group 2 SI/O receive buffer register G2RB016F16 XX 16

017016 XX 16

Group 2 IEBus address register IEAR017116 XX 16

017216 Group 2 IEBus control register IECR 00XX X000 2

017316 Group 2 IEBus transmit interrupt cause detect register IETIF XXX0 0000 2

017416 Group 2 IEBus receive interrupt cause detect register IERIF XXX0 0000 2

017816 Input function select register IPS 00 16

01D4 16 A/D1 control register 2 AD1CON2 X00X X000 2 01D5 16 01D6 16 A/D1 control register 0 AD1CON0 00 16 01D7 16 A/D1 control register 1 AD1CON1 XX00 0000 2 01D8 16 to 02BF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 33 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 02C0 16 XX 16 X0 register Y0 register X0R,Y0R02C1 16 XX 16 02C2 16 XX 16 X1 register Y1 register X1R,Y1R02C3 16 XX 16 02C4 16 XX 16 X2 register Y2 register X2R,Y2R02C5 16 XX 16 02C6 16 XX 16 X3 register Y3 register X3R,Y3R02C7 16 XX 16 02C8 16 XX 16 X4 register Y4 register X4R,Y4R02C9 16 XX 16 02CA 16 XX 16 X5 register Y5 register X5R,Y5R02CB 16 XX 16 02CC 16 XX 16 X6 register Y6 register X6R,Y6R02CD 16 XX 16 02CE 16 XX 16 X7 register Y7 register X7R,Y7R02CF 16 XX 16 02D0 16 XX 16 X8 register Y8 register X8R,Y8R02D1 16 XX 16 02D2 16 XX 16 X9 register Y9 register X9R,Y9R02D3 16 XX 16 02D4 16 XX 16 X10 register Y10 register X10R,Y10R02D5 16 XX 16 02D6 16 XX 16 X11 register Y11 register X11R,Y11R02D7 16 XX 16 02D8 16 XX 16 X12 register Y12 register X12R,Y12R02D9 16 XX 16 02DA 16 XX 16 X13 register Y13 register X13R,Y13R02DB 16 XX 16 02DC 16 XX 16 X14 register Y14 register X14R,Y14R02DD 16 XX 16 02DE 16 XX 16 X15 register Y15 register X15R,Y15R02DF 16 XX 16 02E0 16 XY control register XYC XXXX XX00 2 02E1 16 02E2 16 02E3 16 02E4 16 UART1 special mode register 4 U1SMR4 00 16 02E5 16 UART1 special mode register 3 U1SMR3 00 16 02E6 16 UART1 special mode register 2 U1SMR2 00 16 02E7 16 UART1 special mode register U1SMR 00 16 02E8 16 UART1 transmit/receive mode register U1MR 00 16 02E9 16 UART1 baud rate register U1BRG XX 16 02EA 16 XX 16 UART1 transmit buffer register U1TB02EB 16 XX 16 02EC 16 UART1 transmit/receive control register 0 U1C0 0000 1000 2 02ED 16 UART1 transmit/receive control register 1 U1C1 0000 0010 2 02EE 16 XX 16 UART1 receive buffer register U1RB02EF 16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 34 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 02F016 02F116 02F216 02F316 02F416 UART4 special mode register 4 U4SMR4 00 16 02F516 UART4 special mode register 3 U4SMR3 00 16 02F616 UART4 special mode register 2 U4SMR2 00 16 02F716 UART4 special mode register U4SMR 00 16 02F816 UART4 transmit/receive mode register U4MR 00 16 02F916 UART4 baud rate register U4BRG XX 16 02FA 16 XX 16 UART4 transmit buffer register U4TB02FB 16 XX 16 02FC 16 UART4 transmit/receive control register 0 U4C0 0000 1000 2 02FD 16 UART4 transmit/receive control register 1 U4C1 0000 0010 2 02FE 16 XX 16 UART4 receive buffer register U4RB02FF 16 XX 16

030016 Timer B3,B4,B5 count start flag TBSR 000X XXXX 2

030216 XX 16

Timer A1-1 register TA11030316 XX 16

030416 XX 16

Timer A2-1 register TA21030516 XX 16

030616 XX 16

Timer A4-1 register TA41030716 XX 16

030816 Three-phase PWM control register 0 INVC0 00 16

030916 Three-phase PWM control register 1 INVC1 00 16

030A 16 Three-phase output buffer register 0 IDB0 XX11 1111 2 030B 16 Three-phase output buffer register 1 IDB1 XX11 1111 2 030C 16 Dead time timer DTT XX 16 030D 16 Timer B2 interrupt generating frequency set counter ICTB2 XX 16 030E 16 030F16

031016 XX 16

Timer B3 register TB3031116 XX 16

031216 XX 16

Timer B4 register TB4031316 XX 16

031416 XX 16

Timer B5 register TB5031516 XX 16 031616 031716 031816 031916 031A 16 031B 16 Timer B3 mode register TB3MR 00XX 0000 2 031C 16 Timer B4 mode register TB4MR 00XX 0000 2 031D 16 Timer B5 mode register TB5MR 00XX 0000 2 031E 16 031F16 External interrupt cause select register IFSR 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 35 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET 032016 032116 032216 032316

032416 UART3 special mode register 4 U3SMR4 00 16

032516 UART3 special mode register 3 U3SMR3 00 16

032616 UART3 special mode register 2 U3SMR2 00 16

032716 UART3 special mode register U3SMR 00 16

032816 UART3 transmit/receive mode register U3MR 00 16

032916 UART3 baud rate register U3BRG XX 16

UART3 transmit buffer register U3TB032B 16 XX 16 032C 16 UART3 transmit/receive control register 0 U3C0 0000 1000 2 032D 16 UART3 transmit/receive control register 1 U3C1 0000 0010 2 032E 16 XX 16 UART3 receive buffer register U3RB032F16 XX 16 033016 033116 033216 033316

033416 UART2 special mode register 4 U2SMR4 00 16

033516 UART2 special mode register 3 U2SMR3 00 16

033616 UART2 special mode register 2 U2SMR2 00 16

033716 UART2 special mode register U2SMR 00 16

033816 UART2 transmit/receive mode register U2MR 00 16

033916 UART2 baud rate register U2BRG XX 16

UART2 transmit buffer register U2TB033B 16 XX 16 033C 16 UART2 transmit/receive control register 0 U2C0 0000 1000 2 033D 16 UART2 transmit/receive control register 1 U2C1 0000 0010 2 033E 16 XX 16 UART2 receive buffer register U2RB033F16 XX 16

034016 Count start flag TABSR 00 16

034116 Clock prescaler reset flag CPSRF 0XXX XXXX 2

034216 One-shot start flag ONSF 00 16

034316 Trigger select register TRGSR 00 16

034416 Up-down flag UDF 00 16

034616 XX 16

Timer A0 register TA0034716 XX 16

034816 XX 16

Timer A1 register TA1034916 XX 16 034A 16 XX 16 Timer A2 register TA2034B 16 XX 16 034C 16 XX 16 Timer A3 register TA3034D 16 XX 16 034E 16 XX 16 Timer A4 register TA4034F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 36 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET

035016 XX 16

Timer B0 register TB0035116 XX 16

035216 XX 16

Timer B1 register TB1035316 XX 16

035416 XX 16

Timer B2 register TB2035516 XX 16

035616 Timer A0 mode register TA0MR 0000 0X00 2

035716 Timer A1 mode register TA1MR 0000 0X00 2

035816 Timer A2 mode register TA2MR 0000 0X00 2

035916 Timer A3 mode register TA3MR 0000 0X00 2

035A 16 Timer A4 mode register TA4MR 0000 0X00 2 035B 16 Timer B0 mode register TB0MR 00XX 0000 2 035C 16 Timer B1 mode register TB1MR 00XX 0000 2 035D 16 Timer B2 mode register TB2MR 00XX 0000 2 035E 16 Timer B2 special mode register TB2SC XXXX XXX0 2 035F16 Count source prescaler register TCSPR 0XXX 0000 2 036016 036116 036216 036316

036416 UART0 special mode register 4 U0SMR4 00 16

036516 UART0 special mode register 3 U0SMR3 00 16

036616 UART0 special mode register 2 U0SMR2 00 16

036716 UART0 special mode register U0SMR 00 16

036816 UART0 transmit/receive mode register U0MR 00 16

036916 UART0 baud rate register U0BRG XX 16

UART0 transmit buffer register U0TB036B 16 XX 16 036C 16 UART0 transmit/receive control register 0 U0C0 0000 1000 2 036D 16 UART0 transmit/receive control register 1 U0C1 0000 0010 2 036E 16 XX 16 UART0 receive buffer register U0RB036F16 XX 16 037016 037116 037216 037316 037416 037516

037616 PLL control register 0 PLC0 0011 X100 2

037716 PLL control register 1 PLC1 XXXX 0000 2

037816 DMA0 cause select register DM0SL 0X00 0000 2

037916 DMA1 cause select register DM1SL 0X00 0000 2

037A 16 DMA2 cause select register DM2SL 0X00 0000 2 037B 16 DMA3 cause select register DM3SL 0X00 0000 2 037C 16 XX 16 CRC data register CRCD037D 16 XX 16 037E 16 CRC input register CRCIN XX 16 037F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 37 puorG28/C23M 3. Special Function Registers (SFR) Address Register Symbol Value after RESET

038016 XX 16

A/D0 register 0 AD00038116 XX 16

038216 XX 16

A/D0 register 1 AD01038316 XX 16

038416 XX 16

A/D0 register 2 AD02038516 XX 16

038616 XX 16

A/D0 register 3 AD03038716 XX 16

038816 XX 16

A/D0 register 4 AD04038916 XX 16 038A 16 XX 16 A/D0 register 5 AD05038B 16 XX 16 038C 16 XX 16 A/D0 register 6 AD06038D 16 XX 16 038E 16 XX 16 A/D0 register 7 AD07038F16 XX 16 039016 039116 039216 039316

039416 A/D0 control register 2 AD0CON2 X000 0000 2

039616 A/D0 control register 0 AD0CON0 00 16

039716 A/D0 control register 1 AD0CON1 00 16

039816 D/A register 0 DA0 XX 16

039A 16 D/A register 1 DA1 XX 16 039B 16 039C 16 D/A control register DACON XXXX XX00 2 039D 16 039E 16 039F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 38 puorG28/C23M 3. Special Function Registers (SFR) <144-pin package> Address Register Symbol Value after RESET 03A0 16 Function select register A8 PS8 X000 0000 2 03A1 16 Function select register A9 PS9 00 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 Function select register C PSC 00X0 0000 2 03B0 16 Function select register A0 PS0 00 16 03B1 16 Function select register A1 PS1 00 16 03B2 16 Function select register B0 PSL0 00 16 03B3 16 Function select register B1 PSL1 00 16 03B4 16 Function select register A2 PS2 00X0 0000 2 03B5 16 Function select register A3 PS3 00 16 03B6 16 Function select register B2 PSL2 00X0 0000 2 03B7 16 Function select register B3 PSL3 00 16 03B8 16 03B9 16 Function select register A5 PS5 XXX0 0000 2 03BA 16 03BB 16 03BC 16 03BD 16 Function select register A7 PS7 00 16 03BE 16 03BF 16 03C0 16 Port P6 register P6 XX 16 03C1 16 Port P7 register P7 XX 16 03C2 16 Port P6 direction register PD6 00 16 03C3 16 Port P7 direction register PD7 00 16 03C4 16 Port P8 register P8 XX 16 03C5 16 Port P9 register P9 XX 16 03C6 16 Port P8 direction register PD8 00X0 0000 2 03C7 16 Port P9 direction register PD9 00 16 03C8 16 Port P10 register P10 XX 16 03C9 16 Port P11 register P11 XX 16 03CA 16 Port P10 direction register PD10 00 16 03CB 16 Port P11 direction register PD11 XXX0 0000 2 03CC 16 Port P12 register P12 XX 16 03CD 16 Port P13 register P13 XX 16 03CE 16 Port P12 direction register PD12 00 16 03CF 16 Port P13 direction register PD13 00 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 39 puorG28/C23M 3. Special Function Registers (SFR) <144-pin package> Address Register Symbol Value after RESET 03D0 16 Port P14 register P14 XX 16 03D1 16 Port P15 register P15 XX 16 03D2 16 Port P14 direction register PD14 X000 0000 2 03D3 16 Port P15 direction register PD15 00 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-up control register 2 PUR2 00 16 03DB 16 Pull-up control register 3 PUR3 00 16 03DC 16 Pull-up control register 4 PUR4 XXXX 0000 2 03DD 16 03DE 16 03DF 16 03E0 16 Port P0 register P0 XX 16 03E1 16 Port P1 register P1 XX 16 03E2 16 Port P0 direction register PD0 00 16 03E3 16 Port P1 direction register PD1 00 16 03E4 16 Port P2 register P2 XX 16 03E5 16 Port P3 register P3 XX 16 03E6 16 Port P2 direction register PD2 00 16 03E7 16 Port P3 direction register PD3 00 16 03E8 16 Port P4 register P4 XX 16 03E9 16 Port P5 register P5 XX 16 03EA 16 Port P4 direction register PD4 00 16 03EB 16 Port P5 direction register PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-up control register 0 PUR0 00 16 03F116 Pull-up control register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port control register PCR XXXX XXX0 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

08fo4002,10.nuJ02.1.veR page 40 puorG28/C23M 3. Special Function Registers (SFR) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 <100-pin package> Address Register Symbol Value after RESET 03A0 16 03A1 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 Function select register C PSC 0X00 0000 2 03B0 16 Function select register A0 PS0 00 16 03B1 16 Function select register A1 PS1 00 16 03B2 16 Function select register B0 PSL0 00 16 03B3 16 Function select register B1 PSL1 00 16 03B4 16 Function select register A2 PS2 00X0 0000 2 03B5 16 Function select register A3 PS3 00 16 03B6 16 Function select register B2 PSL2 00X0 0000 2 03B7 16 Function select register B3 PSL3 00 16 03B8 16 03B9 16 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 03C0 16 Port P6 register P6 XX 16 03C1 16 Port P7 register P7 XX 16 03C2 16 Port P6 direction register PD6 00 16 03C3 16 Port P7 direction register PD7 00 16 03C4 16 Port P8 register P8 XX 16 03C5 16 Port P9 register P9 XX 16 03C6 16 Port P8 direction register PD8 00X0 0000 2 03C7 16 Port P9 direction register PD9 00 16 03C8 16 Port P10 register P10 XX 16 03C9 16 03CA 16 Port P10 direction register PD10 00 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Set address spaces 03CB16, 03CE16 and 03CF16 to "FF16" in the 100-pin package. 2. Address spaces 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16 and 03CD16 are not provided in the 100-pin package. 1234567 1 23456 7 1 23456 7 1234567 1234 1234 (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 1) (Note 1)

08fo4002,10.nuJ02.1.veR page 41 puorG28/C23M 3. Special Function Registers (SFR) 12345678901234567890123456789012123456789012345678901234567890121234567890123456 1 234567890123456789012345678901212345678901234567890123456789012123456789012345 6 12345678901234567890123456789012123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789 0 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789 0 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789 0 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789 0 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789 0 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789 0 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 123456 1 2345 6 123456 1234 1234 12345 1 234 5 12345 (Note 3) (Note 1) (Note 2) <100-pin package> Address Register Symbol Value after RESET 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-up control register 2 PUR2 00 16 03DB 16 Pull-up control register 3 PUR3 00 16 03DC 16 03DD 16 03DE 16 03DF 16 03E0 16 Port P0 register P0 XX 16 03E1 16 Port P1 register P1 XX 16 03E2 16 Port P0 direction register PD0 00 16 03E3 16 Port P1 direction register PD1 00 16 03E4 16 Port P2 register P2 XX 16 03E5 16 Port P3 register P3 XX 16 03E6 16 Port P2 direction register PD2 00 16 03E7 16 Port P3 direction register PD3 00 16 03E8 16 Port P4 register P4 XX 16 03E9 16 Port P5 register P5 XX 16 03EA 16 Port P4 direction register PD4 00 16 03EB 16 Port P5 direction register PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-up control register 0 PUR0 00 16 03F116 Pull-up control register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port control register PCR XXXX XXX0 2 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Set address spaces 03D216 and 03D316 to "FF16" in the 100-pin package. 2. Set address spaces 03DC16 to "0016" in the 100-pin package. 3. Address spaces 03D016 and 03D116 are not provided in the 100-pin package.

08fo4002,10.nuJ02.1.veR page 42 puorG28/C23M 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings lobmySr etemaraPn oitidnoCe ulaVt inU V CC egatlovylppuSV CC VA= CC 0.6ot3.0- V VA CC egatlovylppusgolanAV CC VA= CC 0.6ot3.0- V VI egatlovtupnIV NC,TESER SS 0P,ETYB, 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7, 3P 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0- 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7, 31P 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )1( V, FER X, NI Vot3.0- CC 3.0+V 7P 0 7P, 1 0.6ot3.0- VO egatlovtuptuO0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )1( X, TUO Vot3.0- CC 3.0+V 7P 0 7P, 1 0.6ot3.0-V dPn oitapissiDrewoP C°52=rpoT0 05W m rpoTe rutarepmettneibmagnitarepO 58ot04-/58ot02- )2( C° gtsTe rutarepmetegarotS 051ot56-C ° :SETON .egakcapnip-441ehtnidedivorpera51Pot11P.1 .sisabtseuqernositahtnoitponasisihT.2

08fo4002,10.nuJ02.1.veR page 43 puorG28/C23M 5. Electrical Characteristics Table 5.2 Recommended Operating Conditions (VCC = 3.0V to 5.5V at Topr = – 20 to 85oC/– 40 to 85oC (3)) lobmySr etemaraPd radnatSt inU niMp yTx aM V CC )CDVhguorhT(egatlovylppuS 0.30 .55 .5V )CDVhguorhttoN(egatlovylppuS 0.33 .36 .3V VA CC egatlovylppusgolanA V CC V V SS egatlovylppuS 0V VA SS egatlovylppusgolanA 0V V HI )"H"(hgihtupnI egatlov 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0- 8P 7 )4( 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )5( X, NI VNC,TESER, SS ETYB, V8.0 CC V CC V 7P 0 7P, 1 V8.0 CC 0.6 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisnI(V 8.0 CC V CC V 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemnI( V5.0 CC V CC V V LI )"L"(woltupnI egatlov 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0- 8P 7 )4( 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0- 31P 7 41P, 0 41P- 6 51P, 0 51P- 7 )5( X, NI VNC,TESER, SS ETYB, 0V 2.0 CC V 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisnI(0 V 2.0 CC V 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemnI( 0V 61.0 CC V I )kaep(HO tuptuokaeP )"H"(hgih tnerruc )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )5( 0.01-A m I )gva(HO tuptuoegarevA )"H"(hgih tnerruc )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )5( 0.5-A m I )kaep(LO tuptuokaeP )"L"(wol tnerruc )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )5( 0.01A m I )gva(LO tuptuoegarevA )"L"(wol tnerruc )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 6P, 0- 6P 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 11P, 0- 11P 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0 41P- 6 51P, 0 51P- 7 )5( 0.5A m X(f NI )k colcniaM ycneuqerftupni CDVhguorhTV CC V5.5ot2.4=0 0 3z HM V CC V5.5ot0.3=0 0 2z HM CDVhguorhttoNV CC V6.3ot0.3=0 0 2z HM X(f NIC )y cneuqerfnoitallicsokcolcbuS 867.230 5z Hk :SETON .sm001htiwdegarevasitnerructuptuO.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .Am08otlauqeronahtsselebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(HO 8P,2P,1P,0Prof 6 8P, 7 .Am08-otlauqeronahtsselebtsum51Pdna41P,11P,01P,9P, IlatoT )kaep(LO 8P,7P,6P,5P,4P,3Prof 0 8Pot 4 .Am08otlauqeronahtsselebtsum31Pdna21P, IlatoT )kaep(HO 7P,6P,5P,4P,3Prof 2 7Pot 7 8P, 0 8Pot 4 .Am08-otlauqeronahtsselebtsum31Pdna21P, .3. sisabtseuqernositahtnoitponasisihT .4V HI Vdna LI 8Profecnerefer 7 8Potseilppa 7 8PotylppatonseodtI.stroptupnielbammargorpasadesu 7 Xsadesu NIC . .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.5

08fo4002,10.nuJ02.1.veR page 44 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V Table 5.3 Electrical Characteristics (VCC =4.2 to 5.5V, VSS =0V at Topr= –20 to 85oC unless otherwise specified) lobmySr etemaraPn oitidnoCd radnatSt inU niMp yTx aM V HO )"H"(hgihtuptuO egatlov 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( V CC V5= I HO Am5-= 0.3V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( V CC V5= I HO 002-= µA 7.4V X TUO V CC V5= I HO Am1-= 0.3V X TUOC deilppadaoloN3 .3V V LO )"L"(woltuptuO egatlov 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( I LO 002= µA5 4.0V X TUO I LO Am1=0 .2V X TUOC deilppadaoloN0 V V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI ,5TNI-0TNI, DA GRT 0AT,4KLC-0KLC,4STC-0STC, TUO 4AT- TUO , -0ADS,4LCS-0LCS,4DxR-0DxR,3IK-0IK,IMN 4ADS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgihtupnI tnerruc 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS ETYB, VI V= CC 0.5 µA ILI tnerruc)"L"(woltupnI0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS ETYB, VI V0=0 .5- µA R PULLUP ecnatsiserpu-lluP0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( VI V0=0 30 57 61k Ω fR NIX ecnatsiserkcabdeeFX NI 5.1M Ω fR NICX ecnatsiserkcabdeeFX NIC 01M Ω V MAR egatlovybdnatsMARC DVhguorhT5 .2V I CC tnerrucylppusrewoP: snoitidnoctnemerusaeM tuptuo,edompihc-elgnisnI rehtodnanepotfelerasnip Votdetcennocerasnip SS . X(f NI ,evawerauqs,zHM03=) noisividon 824 5A m X(f NIC ,etatstiawahtiw,zHk23=) 52=rpoTC ° 074 µA 52=rpoTs potskcolcehtnehwC° 4.00 2 µA :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

08fo4002,10.nuJ02.1.veR page 45 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V Table 5.4 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5V, Vss = AVSS = 0V at Topr = –20 to 85oC unless otherwise specified) lobmySr etemaraPn oitidnoctnemerusaeM dradnatS tinU niMp yTx aM -n oituloseRV FER V= CC 01s tiB LNIr orreytiraenilnonlargetnIV FER V= CC V5= NA 0 NAot 7 NA 0XE NA, 1XE BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orreytiraenilnonlaitnereffiD 1±B SL -r orretesffO 3±B SL -r orreniaG 3±B SL R REDDAL reddalrotsiseRV FER V= CC 80 4k Ω t VNOC emitnoisrevnoctib-01 3.3 µs t VNOC emitnoisrevnoctib-8 8.2 µs t PMAS emitelpmaS 3.0 µs V FER egatlovecnerefeR 2V CC V V AI egatlovtupnigolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM01gnideecxefi,) φ .zHM01otlauqeronahtsselycneuqerfDA lobmySr etemaraPn oitidnoctnemerusaeM dradnatS tinU niMp yTx aM -n oituloseR 8s tiB -y caruccaetulosbA 0.1% tUS emitputeS 3 µs R O ecnatsisertuptuO 40 10 2k Ω I FERV tnerructupniylppusrewopecnerefeR) 1etoN(5 .1A m :SETON ehtrof)1,0=i(retsigeriADehtdnadesusisretrevnocA/DowtfoenotahtsinoitidnoctnemeruseM.1 00"otretrevnocA/Ddesunu 61 .deulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOCiDAehtfineveswolf FER .)noitcennoc Table 5.5 D/A Conversion Characteristics (VCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V at Topr = –20 to 85oC unless otherwise specified)

08fo4002,10.nuJ02.1.veR page 46 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V lobmySr etemaraP dradnatS tinU niMx aM cte mitelcyctupnikcolclanretxE 33s n wt )H( htdiweslup)"H"(hgihtupnikcolclanretxE 31s n wt )L( htdiweslup)"L"(woltupnikcolclanretxE 31s n rte mitegdegnisirkcolclanretxE 5s n fte mitegdegnillafkcolclanretxE 5s n tac1(RD – DB) = f(BCLK) X 2 – 35109 [ns] tac2(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) tac1(AD – DB) = f(BCLK) – 3510 9 [ns] tac2(AD – DB) = – 3510 X n [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) tac3(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD – DB) = f(BCLK) X 2 – 3510 X n9 [ns] (n=5 with 2 wait states and n=7 with 3 wait states) tac4(RAS – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS – DB) = – 3510 X n9 [ns] (n=1 with 1 wait state and n=3 when 2 wait states) tac4(CAD – DB) = f(BCLK ) – 3510 X l9 [ns] (l=1 with 1 wait state and l=2 with 2 wait states) f(BCLK) f(BCLK) X 2 Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.6 External Clock Input Table 5.7 Memory Expansion and Microprocessor Modes lobmySr etemaraP dradnatS tinU niMx aM 1cat )BD-DR( )etatstiawonhtiw,dradnatsDR(emitsseccatupniataD )1etoN(s n 1cat )BD-DA( )etatstiawonhtiw,dradnatsSC,dradnatsDA(emitsseccatupniataD )1etoN(s n 2cat )BD-DR( )etatstiawahtiw,dradnatsDR(emitsseccatupniataD )1etoN(s n 2cat )BD-DA( )etatstiawahtiw,dradnatsSC,dradnatsDA(emitsseccatupniataD )1etoN(s n 3cat )BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emitsseccatupniataD )1etoN(s n 3cat )BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsSC,dradnatsDA(emitsseccatupniataD )1etoN(s n 4cat )BD-SAR( )ecapsMARDagnisseccanehw,dradnatsSAR(emitsseccatupniataD )1etoN(s n 4cat )BD-SAC( )ecapsMARDagnisseccanehw,dradnatsSAC(emitsseccatupniataD )1etoN(s n 4cat )BD-DAC( )ecapsMARDagnisseccanehw,dradnatsDAC(emitsseccatupniataD )1etoN(s n ust )KLCB-BD( emitputestupniataD 62s n ust )KLCB-YDR( emitputestupniYDR 62s n ust )KLCB-DLOH( emitputestupniDLOH 03s n ht )BD-DR( emitdlohtupniataD 0s n ht )BD-SAC( emitdlohtupniataD 0s n ht )YDR-KLCB( emitdlohtupniYDR 0s n ht )DLOH-KLCB( emitdlohtupniDLOH 0s n dt )ADLH-KLCB( emityaledtuptuoADLH 52s n :SETON rewolesuroetatstiawatresnI.ycnceuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 (f KLCB .evitagensieulavdetaluclacafiycneuqerfnoitareponasa)

08fo4002,10.nuJ02.1.veR page 47 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emitelcyctupni 001s n wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 04s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 04s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emitelcyctupni 004s n wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 002s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emitelcyctupni 002s n wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 001s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 001s n lobmySr etemaraP dradnatS tinU niMx aM wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 001s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 001s n lobmySr etemaraP dradnatS tinU niMx aM ct )PU( iAT TUO emitelcyctupni 0002s n wt )HPU( iAT TUO htdiweslup)"H"(hgihtupni 0001s n wt )LPU( iAT TUO htdiweslup)"L"(woltupni 0001s n ust )NIT-PU( iAT TUO emitputestupni 004s n ht )PU-NIT( iAT TUO emitdlohtupni 004s n Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.8 Timer A Input (Count Source Input in Event Counter Mode) Table 5.9 Timer A Input (Gate Input in Timer Mode) Table 5.10 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 5.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 5.12 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

08fo4002,10.nuJ02.1.veR page 48 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.13 Timer B Input (Count Source Input in eEvent Counter Mode) Table 5.14 Timer B Input (Pulse Period Measurement Mode) Table 5.15 Timer B Input (Pulse Width Measurement Mode) Table 5.16 A/D trigger Input Table 5.17 Serial I/O Table 5.18 External Interrupt INTi Input lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI )egdeenonodetnuoc(emitelcyctupni 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiweslup)"H"(hgihtupni 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiweslup)"L"(woltupni 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emitelcyctupni 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiweslup)"H"(hgihtupni 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiweslup)"L"(woltupni 08s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emitelcyctupni 004s n wt )HBT( iBT NI htdiweslup)"H"(hgihtupni 002s n wt )LBT( iBT NI htdiweslup)"L"(woltupni 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emitelcyctupni 004s n wt )HBT( iBT NI htdiweslup)"H"(hgihtupni 002s n wt )LBT( iBT NI htdiweslup)"L"(woltupni 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )DA( DA GRT )muminimtaelbaliavareggirt(htdiweslup)"H"(hgihtupni 0001s n wt )LDA( DA GRT htdiweslup)"L"(woltupni 521s n lobmySr etemaraP dradnatS tinU niMx aM ct )KC( emitelcyctupniiKLC 002s n wt )HKC( htdiweslup)"H"(hgihtupniiKLC 001s n wt )LKC( htdiweslup)"L"(woltupniiKLC 001s n dt )Q-C( emityaledtuptuoiDxT 08s n ht )Q-C( emitdlohiDxT 0s n ust )C-D( emitdlohtupniiDxR 03s n ht )Q-C( emitdlohtupniiDxR 09s n lobmySr etemaraP dradnatS tinU niMx aM wt )HNI( htdiweslup)"H"(hgihtupniiTNI 052s n wt )LNI( htdiweslup)"L"(woltupniiTNI 052s n

08fo4002,10.nuJ02.1.veR page 49 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V See Figure 5.1 lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddA 3-s n ht )DA-DR( )dradnatsDR(emitdlohtuptuosserddA 0s n ht )DA-RW( )dradnatsRW(emitdlohtuptuosserddA )1etoN(s n dt )SC-KLCB( emityaledtuptuolangistceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emitdlohtuptuolangistceles-pihC 3-s n ht )SC-DR( )dradnatsDR(emitdlohtuptuolangistceles-pihC 0s n ht )SC-RW( )dradnatsRW(emitdlohtuptuolangistceles-pihC )1etoN(s n dt )ELA-KLCB( emityaledtuptuolangisELA 81s n ht )ELA-KLCB( emitdlohtuptuolangisELA 2-s n dt )DR-KLCB( emityaledtuptuolangisDR 81s n ht )DR-KLCB( emitdlohtuptuolangisDR 5-s n dt )RW-KLCB( emityaledtuptuolangisRW 81s n dt )RW-KLCB( emitdlohuptuolangisRW 3-s n dt )RW-BD( )dradnatsRW(emityaledtuptuoataD )1etoN(s n ht )BD-RW( )dradnatsRW(emitdlohuptuoataD )1etoN(s n wt )RW( htdiweslupetirW )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 td(DB – WR) = f(BCLK) 10 9 – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2 10 9 – 15 [ns] Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.19 Memory Expansion Mode and Microprocessor Mode (with No Wait State)

08fo4002,10.nuJ02.1.veR page 50 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddA 3-s n ht )DA-DR( )dradnatsDR(emitdlohtuptuosserddA 0s n ht )DA-RW( )dradnatsRW(emitdlohtuptuosserddA )1etoN(s n dt )SC-KLCB( emityaledtuptuolangistceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emitdlohtuptuolangistceles-pihC 3-s n ht )SC-DR( )dradnatsDR(emitdlohtuptuolangistceles-pihC 0s n ht )SC-RW( )dradnatsRW(emitdlohtuptuolangistceles-pihC )1etoN(s n dt )ELA-KLCB( emityaledtuptuolangisELA 81s n ht )ELA-KLCB( emitdlohtuptuolangisELA 2-s n dt )DR-KLCB( emityaledtuptuolangisDR 81s n ht )DR-KLCB( emitdlohtuptuolangisDR 5-s n dt )RW-KLCB( emityaledtuptuolangisRW 81s n dt )RW-KLCB( emitdlohuptuolangisRW 3-s n dt )RW-BD( )dradnatsRW(emityaledtuptuoataD )1etoN(s n ht )BD-RW( )dradnatsRW(emitdlohuptuoataD )1etoN(s n wt )RW( htdiweslupetirW )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 [ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) td(DB – WR) = f(BCLK)

10 X n9

– 20 th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states) tw( WR) = 10 X n9 – 15f(BCLK) X 2 See Figure 5.1 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.20 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory)

08fo4002,10.nuJ02.1.veR page 51 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddA 3-s n ht )DA-DR( )dradnatsDR(emitdlohtuptuosserddA )1etoN(s n ht )DA-RW( )dradnatsRW(emitdlohtuptuosserddA )1etoN(s n dt )SC-KLCB( emityaledtuptuolangistceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emitdlohtuptuolangistceles-pihC 3-s n ht )SC-DR( )dradnatsDR(emitdlohtuptuolangistceles-pihC )1etoN(s n ht )SC-RW( )dradnatsRW(emitdlohtuptuolangistceles-pihC )1etoN(s n dt )DR-KLCB( emityaledtuptuolangisDR 81s n ht )DA-KLCB( emitdlohtuptuolangisDR 5-s n dt )RW-KLCB( emityaledtuptuolangisRW 81s n dt )RW-KLCB( emitdlohtuptuolangisRW 3-s n dt )RW-BD( )dradnatsRW(emityaledtuptuoataD )1etoN(s n ht )BD-RW( )dradnatsRW(emitdlohtuptuoataD )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emityaledtuptuolangisELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emitdlohtuptuolangisELA 2-s n dt )ELA-DA( )dradnatssserdda(emityaledtuptuolangisELA )1etoN(s n ht )DA-ELA( )dradnatssserdda(emitdlohtuptuolangisELA )1etoN(s n zdt )DA-DR( emitecnadepmi-hgihtuptuosserddA 8s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 td(DB – WR) = 10 X m – 25 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 10 9 – 20 [ns] th(ALE – AD) = f(BCLK ) X 2 10 9 – 10 [ns] f(BCLK) X 2 See Figure 5.1 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.21 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting a Space with the Multiplexed Bus)

08fo4002,10.nuJ02.1.veR page 52 puorG28/C23M 5. Electrical Characteristics (VCC = 5 V) VCC = 5V lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddawoR 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddawoR 3-s n ht )DAC-KLCB( emityaledtuptuosserddanmuloC 81s n dt )DAC-KLCB( )dradnatsKLCB(emitdlohtuptuosserddanmuloC 3-s n ht )DAR-SAR( tuptuoSARretfaemitdlohtuptuosserddawoR )1etoN(s n dt )SAR-KLCB( )dradnatsKLCB(emityaledtuptuoSAR 81s n ht )SAR-KLCB( )dradnatsKLCB(emitdlohtuptuoSAR 3-s n t PR emitdloh)"H"(hgihSAR )1etoN(s n dt )SAC-KLCB( )dradnatsKLCB(emityaledtuptuoSAC 81s n ht )SAC-KLCB( )dradnatsKLCB(emitdlohtuptuoSAC 3-s n dt )WD-KLCB( )dradnatsKLCB(emityaledtuptuoWD 81s n ht )WD-KLCB( )dradnatsKLCB(emitdlohtuptuoWD 5-s n ust )SAC-BD( tuptuoBDretfaemitputestuptuoSAC )1etoN(s n ht BD-KLCB( )dradnatsKLCB(emitdlohtuptuolangisBD 7-s n ust )SAR-SAC( )hserfer(tuptuoSARerofebemitputestuptuoSAC )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 tsu(CAS – RAS) = f(BCLK) X 2 – 13 [ns] th(RAS – RAD) = f(BCLK) X 2 10 9 – 13 [ns] tRP = f(BCLK) X 2 10 9 X 3 – 20 [ns] tsu(DB – CAS) = f(BCLK) 10 9 – 20 [ns] See Figure 5.1 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.22 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting the DRAM Area)

08fo4002,10.nuJ02.1.veR page 53 puorG28/C23M 5. Electrical Characteristics P10 30pF P14 P13 P12 P15 P11 Note 1 NOTES: 1. P11 to P15 are provided in the 144-pin package only. Figure 5.1 P0 to P15 Measurement Circuit

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 54 Figure 5.2 VCC =5V Timing Diagram (1) BCLK ALE -2ns.min RD 18ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) tsu(DB-BCLK) td(BCLK-RD) 26ns.min(1) CSi td(BCLK-CS) 18ns.max(1) ADi th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) 0ns.min tac1(AD-DB)(2) WR,WRL, WRH 18ns.max -3ns.min BCLK CSi td(BCLK-CS) 18ns.max ADi td(BCLK-AD) 18ns.max td(BCLK-ALE) -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min th(WR-DB) (1) td(DB-WR) =(tcyc-20)ns.min th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2-15)ns.min Vcc=5V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (1) th(WR-AD) (1) tw(WR) (1) tac1(RD-DB)(2) 18ns.max(1) Read timing Write timing ( written in 2 cycles with no wait state) NOTES: 1. It varies with the operation frequency. Measurement conditions

• VCC =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH =2.0V, VOL =0.8V Memory expansion mode and microprocessor mode (with no wait state) NOTES: 1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac1(RD-DB)=(tcyc/2-35)ns.max tac1(AD-DB)=(tcyc-35)ns.max 18ns.max td(DB-WR) (1)

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 55 BCLK ALE 18ns.max -2ns.min RD 18ns.max -5ns.min Hi-Z DB 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 26ns.min(1) tac2(RD-DB)(2) CSi td(BCLK-CS) 18ns.max(1) ADi 18ns.max(1) th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)(2) WR,WRL, WRH 18ns.max BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min Vcc=5V th(BCLK-RD) th(RD-DB)tsu(DB-BCLK) th(RD-CS) 0ns.min td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (1) td(DB-WR) (1) th(WR-DB) (1) th(WR-AD) (1) td(DB-WR) =(tcyc x n-20)ns.min (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) t h(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states) NOTES: 1. It varies with the operation frequency. Measurement conditions

• VCC =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0
• Output high and low voltage: VOH =2.0V, VOL =0.8V th(BCLK-ALE) Read timing Write timing (written in 2 cycles with no wait state) Memory expansion mode and microprocessor mode (with a wait state) th(RD-AD) tw(WR) (1) th(BCLK-WR) 0ns.min Notes : 1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.) -3ns.min Figure 5.3 VCC =5V Timing Diagram (2)

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 56 BCLK CSi 18ns.max ADi 18ns.max RD 18ns.max -5ns.min th(BCLK-AD) -3ns.min -3ns.min BHE ADi /DBi 0ns.min 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.min tcyc BHE ADi /DBi Data output WR,WRL, WRH Address AddressData input 26ns.min td(BCLK-RD) th(WR-CS) (1) Address td(AD-ALE)(1) Address tsu(DB-BCLK) tac3(RD-DB)(1) tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 18ns.max td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states) ALE 18ns.max -2ns.mintd(BCLK-ALE) th(ALE-AD)(1) td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min Vcc=5V td(BCLK-CS) td(AD-ALE)(1) th(ALE-AD)(1) th(BCLK-RD) th(RD-AD)(1) th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)(1) td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) (1) td(DB-WR) (1) th(WR-DB) (1) th(BCLK-ALE) th(BCLK-ALE) tcyc NOTES: 1. It varies with the operation frequency. Measurement conditions

• V CC =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VO H =2.0V, VO L=0.8V NOTES: 1. It varies with the operation frequency. Read timing Write timing (written in 2 cycles with no wait state) Memory expansion mode and microprocessor mode (with a wait state, when accessing an external memory and using the multiplexed bus) tac3(AD-DB)(1) Figure 5.4 VCC =5V Timing Diagram (3)

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 57 BCLK DW DB MAi Vcc=5V RAS CASL CASH Hi-Z tac4(CAS-DB)(2) 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) tac4(RAS-DB)(2) Row address Column address th(BCLK-RAD) -3ns.min 18ns.max(1) td(BCLK-CAD) 18ns.max(1) td(BCLK-RAS) 18ns.max(1) td(BCLK-CAS) th(RAS-RAD) (2) tRP (2) tac4(CAD-DB)(2) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min 0ns.min tsu(DB-BCLK) 26ns.min(1) th(CAS-DB) Measurement conditions

• VCC =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH =2.0V, VOL =0.8V Read timing Memory expansion mode and microprocessor mode (When accessing the DRAM area) NOTES: 1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) 2. It varies with the operation frequency. tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states) th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min Figure 5.5 VCC =5V Timing Diagram (4)

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 58 BCLK DW DB MAi th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Vcc=5V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) -3ns.min 18ns.max td(BCLK-CAD) 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(RAS-RAD) (1) tRP (1) 18ns.max td(BCLK-DW) tsu(DB-CAS)(1) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) -5ns.min Row address Column address NOTES: 1. It varies with the operation frequency. Measurement conditions

• VCC =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH =2.0V, VOL =0.8V Write timing Memory expansion mode and microprocessor mode (When accessing the DRAM area) Figure 5.6 VCC =5V Timing Diagram (5)

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 59 tcyc 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min tsu(CAS-RAS)(1) 18ns.max tcyc td(BCLK-CAS) tsu(CAS-RAS)(1) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min 18ns.max td(BCLK-RAS) BCLK DW tsu(CAS-RAS)=(tcyc/2-13)ns.min Vcc=5V RAS CASL CASH BCLK DW tsu(CAS-RAS)=(tcyc/2-13)ns.min RAS CASL CASH NOTES : 1. It varies with the operation frequency. Measurement conditions

• VCC =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH =2.0V, VOL =0.8V Refresh timing (CAS-before-RAS refresh) Memory expansion mode and microprocessor mode NOTES: 1. It varies with the operation frequency. Refresh timing (Self-refresh) Figure 5.7 VCC =5V Timing Diagram (6)

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 60 tsu(D–C) TAiIN input TAiOUT input In event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When counting on falling edge is selected) TAiIN input (When counting on rising edge is selected) TAiOUT input (Counter increment/ decrement input) INTi input AD TRG input Vcc=5V Figure 5.8 VCC =5V Timing Diagram (7)

M32C/82 Group 5. Electrical Characteristics (V CC = 5V) 08fo4002,10.nuJ02.1.veR page 61 th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Hi–Z Measurement conditions

• VCC =4.2 to 5.5V
• Input high and low voltage: VIH=4.0V, VIL=1.0V
• Output high and low voltage: VOH =2.5V, VOL =2.5V Memory expansion mode and microprocessor mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 (Valid with a wait state or with no wait state) (Valid only with a wait state) RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Vcc=5V Figure 5.9 VCC =5V Timing Diagram (8)

08fo4002,10.nuJ02.1.veR page 62 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Table 5.23 Electrical Characteristics (VCC =3.0 to 3.6V, VSS =0V at Topr = –20 to 85oC, unless otherwise specified) lobmySr etemaraPn oitidnoCd radnatSt inU niMp yTx aM V HO )"H"(hgihtuptuO egatlov 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( I HO Am1-=7 .2V X TUO I HO Am1.0-=7 .2V X TUOC deilppadaoloN3 .3V V LO )"L"(woltuptuO egatlov 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( I LO Am1=5 .0V X TUO I LO Am1.0=5 .0V X TUOC deilppadaoloN0 V V +T V- -T siseretsyH0 AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI ,5TNI-0TNI, DA GRT 0AT,4KLC-0KLC,4STC-0STC, TUO 4AT- TUO , -0ADS,4LCS-0LCS,4DxR-0DxR,3IK-0IK,IMN 4ADS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgihtupnI tnerruc 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS ETYB, VI V= CC 0.4 µA ILI tnerruc)"L"(woltupnI0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7 01P, 0- 01P 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7 41P, 0- 41P 6 51P, 0 51P- 7 )1( X, NI VNC,TESER, SS ETYB, VI V0=0 .4- µA R PULLUP ecnatsiserpu-lluP0 P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0- 5P 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 11P, 0 11P- 4 21P, 0 21P- 7 31P, 0 31P- 7, 41P 0 41P- 6 51P, 0 51P- 7 )1( VI V0=6 60 210 05k Ω fR NIX ecnatsiserkcabdeeFX NI 0.3M Ω fR NICX ecnatsiserkcabdeeFX NIC 0.02M Ω V MAR egatlovybdnatsMARC DVhguorhT5 .2V CDVhguorhttoN0 .2 I CC tnerrucylppusrewoP: noitidnoctnemerusaeM tuptuo,edompihc-elgnisnI rehtodnanepotfelerasnip Votdetcennocerasnip SS . X(f NI ,evawerauqs,zHM02=) noisividon 718 3A m X(f NIC ,etatstiawahtiw,zHk23=) 52=rpoT,CDVhguorhttonC ° 0.5 µA X(f NIC ,etatstiawahtiw,zHk23=) 52=rpoT,CDVhguorhtC ° 043 µA 52=rpoTs potskcolcehtnehwC° 4.00 2 µA :SETON .ylnoegakcapnip-441ehtnidedivorpera51Pot11P.1

08fo4002,10.nuJ02.1.veR page 63 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Table 5.24 A/D Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6V, VSS = AVSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.25 D/A Conversion Characteristics (VCC = VREF = 3.0 to 3.6V, VSS = AVSS = 0V at Topr = –20 to 85oC unless otherwise specified) lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMp yTx aM -n oituloseRV FER V= CC 01s tiB LNIr orreytiraenilnonlargetnI) tib-8(noitcnufH&SoNV CC V= FER V3.3=2 ±B SL LNDr orreytiraenilnonlaitnereffiD) tib-8(noitcnufH&SoN1 ±B SL -r orretesffO) tib-8(noitcnufH&SoN2 ±B SL -r orreniaG) tib-8(noitcnufH&SoN2 ±B SL R REDDAL reddalrotsiseRV FER V= CC 80 4k Ω t VNOC emitnoisrevnoctib-8 9.4 µs V FER egatlovecnerefeR 0.3V CC V V AI egatlovtupnigolanA 0V FER V dlohdnaelpmaS:H&S :SETON X(fediviD.1 NI peekot,zHM01gnideecxefi,) φ .zHM01otlauqeronahtsselycneuqerfDA lobmySr etemaraPn oitidnoctnemerusaeM dradnatS tinU niMp yTx aM -n oituloseR 8s tiB -y caruccaetulosbA 0.1% tUS emitputeS 3 µs R O ecnatsisertuptuO 40 10 2k Ω I FERV tnerructupniylppusrewopecnerefeR) 1etoN(0 .1A m :SETON ehtrof)1,0=i(retsigeriADehtdnadesusisretrevnocA/DowtfoenotahtsinoitidnoctnemeruseM.1 00"otretrevnocA/Ddesunu 61 .deulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOCiDAehtfineveswolf FER .)noitcennoc

08fo4002,10.nuJ02.1.veR page 64 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.26 External Clock Input Table 5.27 Memory Expansion Mode and Microprocessor Mode lobmySr etemaraP dradnatS tinU niMx aM cte mitelcyctupnikcolclanretxE 05s n wt )H( htdiweslup)"H"(hgihtupnikcolclanretxE 22s n wt )L( htdiweslup)"L"(woltupnikcolclanretxE 22s n rte mitegde-gnisirkcolclanretxE 5s n fte mitegde-gnillafkcolclanretxE 5s n tac1(RD – DB) = f(BCLK) X 2 – 35109 [ns] tac2(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) tac1(AD – DB) = f(BCLK) – 3510 9 [ns] tac2(AD – DB) = – 3510 X n [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) tac3(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD – DB) = f(BCLK) X 2 – 3510 X n9 [ns] (n=5 with 2 wait states and n=7 with 3 wait states) tac4(RAS – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS – DB) = – 3510 X n9 [ns] (n=1 with 1 wait state and n=3 when 2 wait states) tac4(CAD – DB) = f(BCLK ) – 3510 X l9 [ns] (l=1 with 1 wait state and l=2 with 2 wait states) f(BCLK) f(BCLK) X 2 lobmySr etemaraP dradnatS tinU niMx aM 1cat )BD-DR( )etatstiawonhtiw,dradnatsDR(emitsseccatupniataD )1etoN(s n 1cat )BD-DA( )etatstiawonhtiw,dradnatsSC,dradnatsDA(emitsseccatupniataD )1etoN(s n 2cat )BD-DR( )etatstiawahtiw,dradnatsDR(emitsseccatupniataD )1etoN(s n 2cat )BD-DA( )etatstiawahtiw,dradnatsSC,dradnatsDA(emitsseccatupniataD )1etoN(s n 3cat )BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emitsseccatupniataD )1etoN(s n 3cat )BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsSC,dradnatsDA(emitsseccatupniataD )1etoN(s n 4cat )BD-SAR( )ecapsMARDagnisseccanehw,dradnatsSAR(emitsseccatupniataD )1etoN(s n 4cat )BD-SAC( )ecapsMARDagnisseccanehw,dradnatsSAC(emitsseccatupniataD )1etoN(s n 4cat )BD-DAC( )ecapsMARDagnisseccanehw,dradnatsDAC(emitsseccatupniataD )1etoN(s n ust )KLCB-BD( emitputestupniataD 03s n ust )KLCB-YDR( emitputestupniYDR 04s n ust )KLCB-DLOH( emitputestupniDLOH 06s n ht )BD-DR( emitdlohtupniataD 0s n ht )BD-SAC( emitdlohtupniataD 0s n ht )YDR-KLCB( emitdlohtupniYDR 0s n ht )DLOH-KLCB( emitdlohtupniDLOH 0s n dt )ADLH-KLCB( emityaledtuptuoADLH 52s n :SETON rewolesuroetatstiawatresnI.ycnceuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 (f KLCB .evitagensieulavdetaluclacafiycneuqerfnoitareponasa)

08fo4002,10.nuJ02.1.veR page 65 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.28 Timer A Input (Count Source Input in Event Counter Mode) Table 5.29 Timer A Input (Gate Input in Timer Mode) Table 5.30 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 5.31 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 5.32 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emitelcyctupni 001s n wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 04s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 04s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emitelcyctupni 004s n wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 002s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )AT( iAT NI emitelcyctupni 002s n wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 001s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 001s n lobmySr etemaraP dradnatS tinU niMx aM wt )HAT( iAT NI htdiweslup)"H"(hgihtupni 001s n wt )LAT( iAT NI htdiweslup)"L"(woltupni 001s n lobmySr etemaraP dradnatS tinU niMx aM ct )PU( iAT TUO emitelcyctupni 0002s n wt )HPU( iAT TUO htdiweslup)"H"(hgihtupni 0001s n wt )LPU( iAT TUO htdiweslup)"L"(woltupni 0001s n ust )NIT-PU( iAT TUO emitputestupni 004s n ht )PU-NIT( iAT TUO emitdlohtupni 004s n

08fo4002,10.nuJ02.1.veR page 66 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.33 Timer B input (Count Source Input in Event Counter Mode) Table 5.34 Timer B input (Pulse Period Measurement Mode) Table 5.35 Timer B input (Pulse Width Measurement Mode) Table 5.36 A/D Trigger Input Table 5.37 Serial I/O Table 5.38 External Interrupt INTi input lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI )egdeenonodetnuoc(emitelcyctupni 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiweslup)"H"(hgihtupni 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiweslup)"L"(woltupni 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emitelcyctupni 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiweslup)"H"(hgihtupni 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiweslup)"L"(woltupni 08s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emitelcyctupni 004s n wt )HBT( iBT NI htdiweslup)"H"(hgihtupni 002s n wt )LBT( iBT NI htdiweslup)"L"(woltupni 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )BT( iBT NI emitelcyctupni 004s n wt )HBT( iBT NI htdiweslup)"H"(hgihtupni 002s n wt )LBT( iBT NI htdiweslup)"L"(woltupni 002s n lobmySr etemaraP dradnatS tinU niMx aM ct )DA( DA GRT )muminimtaelbaliavareggirt(htdiweslup)"H"(hgihtupni 0001s n wt )LDA( DA GRT htdiweslup)"L"(woltupni 521s n lobmySr etemaraP dradnatS tinU niMx aM ct )KC( emitelcyctupniiKLC 002s n wt )HKC( htdiweslup)"H"(hgihtupniiKLC 001s n wt )LKC( htdiweslup)"L"(woltupniiKLC 001s n dt )Q-C( emityaledtuptuoiDxT 08s n ht )Q-C( emitdlohiDxT 0s n ust )C-D( emitdlohtupniiDxR 03s n ht )Q-C( emitdlohtupniiDxR 09s n lobmySr etemaraP dradnatS tinU niMx aM wt )HNI( htdiweslup)"H"(hgihtupniiTNI 052s n wt )LNI( htdiweslup)"L"(woltupniiTNI 052s n

08fo4002,10.nuJ02.1.veR page 67 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC, unless otherwise specified) Table 5.39 Memory Expansion Mode and Microprocessor Mode (with No Wait State) lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddA 0s n ht )DA-DR( )dradnatsDR(emitdlohtuptuosserddA 0s n ht )DA-RW( )dradnatsRW(emitdlohtuptuosserddA )1etoN(s n dt )SC-KLCB( emityaledtuptuolangistceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emitdlohtuptuolangistceles-pihC 0s n ht )SC-DR( )dradnatsDR(emitdlohtuptuolangistceles-pihC 0s n ht )SC-RW( )dradnatsRW(emitdlohtuptuolangistceles-pihC )1etoN(s n dt )ELA-KLCB( emityaledtuptuolangisELA 81s n ht )ELA-KLCB( emitdlohtuptuolangisELA 2-s n dt )DR-KLCB( emityaledtuptuolangisDR 81s n ht )DR-KLCB( emitdlohtuptuolangisDR 3-s n dt )RW-KLCB( emityaledtuptuolangisRW 81s n dt )RW-KLCB( emitdlohuptuolangisRW 0s n dt )RW-BD( )dradnatsRW(emityaledtuptuoataD )1etoN(s n ht )BD-RW( )dradnatsRW(emitdlohuptuoataD )1etoN(s n wt )RW( htdiweslupetirW )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 td(DB – WR) = f(BCLK) 10 9 – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2 10 9 – 15 [ns] See Figure 5.1

08fo4002,10.nuJ02.1.veR page 68 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.40 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory) lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddA 0s n ht )DA-DR( )dradnatsDR(emitdlohtuptuosserddA 0s n ht )DA-RW( )dradnatsRW(emitdlohtuptuosserddA )1etoN(s n dt )SC-KLCB( emityaledtuptuolangistceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emitdlohtuptuolangistceles-pihC 0s n ht )SC-DR( )dradnatsDR(emitdlohtuptuolangistceles-pihC 0s n ht )SC-RW( )dradnatsRW(emitdlohtuptuolangistceles-pihC )1etoN(s n dt )ELA-KLCB( emityaledtuptuolangisELA 81s n ht )ELA-KLCB( emitdlohtuptuolangisELA 2-s n dt )DR-KLCB( emityaledtuptuolangisDR 81s n ht )DR-KLCB( emitdlohtuptuolangisDR 3-s n dt )RW-KLCB( emityaledtuptuolangisRW 81s n dt )RW-KLCB( emitdlohuptuolangisRW 0s n dt )RW-BD( )dradnatsRW(emityaledtuptuoataD )1etoN(s n ht )BD-RW( )dradnatsRW(emitdlohuptuoataD )1etoN(s n wt )RW( htdiweslupetirW )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 [ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) td(DB – WR) = f(BCLK) – 20 th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n=5w i t h3w a i ts t a t e s ) tw( WR) = 10 X n9 – 15f(BCLK) X 2 See Figure 5.1

08fo4002,10.nuJ02.1.veR page 69 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.41 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting a Space with the Multiplexed Bus) lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddA 0s n ht )DA-DR( )dradnatsDR(emitdlohtuptuosserddA )1etoN(s n ht )DA-RW( )dradnatsRW(emitdlohtuptuosserddA )1etoN(s n dt )SC-KLCB( emityaledtuptuolangistceles-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emitdlohtuptuolangistceles-pihC 0s n ht )SC-DR( )dradnatsDR(emitdlohtuptuolangistceles-pihC )1etoN(s n ht )SC-RW( )dradnatsRW(emitdlohtuptuolangistceles-pihC )1etoN(s n dt )DR-KLCB( emityaledtuptuolangisDR 81s n ht )DA-KLCB( emitdlohtuptuolangisDR 3-s n dt )RW-KLCB( emityaledtuptuolangisRW 81s n dt )RW-KLCB( emitdlohtuptuolangisRW 0s n dt )RW-BD( )dradnatsRW(emityaledtuptuoataD )1etoN(s n ht )BD-RW( )dradnatsRW(emitdlohtuptuoataD )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emityaledtuptuolangisELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emitdlohtuptuolangisELA 2-s n dt )ELA-DA( )dradnatssserdda(emityaledtuptuolangisELA )1etoN(s n ht )DA-ELA( )dradnatssserdda(emitdlohtuptuolangisELA )1etoN(s n zdt )DA-DR( emitecnadepmi-hgihtuptuosserddA 8s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 td(DB – WR) = 10 X m9 – 25 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 –10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 10 9 – 20 [ns] th(ALE – AD) = f(BCLK ) X 2 10 9 – 10 [ns] f(BCLK) X 2 See Figure 5.1

08fo4002,10.nuJ02.1.veR page 70 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3 V) VCC = 3.3V Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.42 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting the DRAM Area) lobmySr etemaraP tnemerusaeM noitidnoc dradnatS tinU niMx aM dt )DA-KLCB( emityaledtuptuosserddawoR 81s n ht )DA-KLCB( )dradnatsKLCB(emitdlohtuptuosserddawoR 0s n ht )DAC-KLCB( emityaledtuptuosserddanmuloC 81s n dt )DAC-KLCB( )dradnatsKLCB(emitdlohtuptuosserddanmuloC 0s n ht )DAR-SAR( tuptuoSARretfaemitdlohtuptuosserddawoR )1etoN(s n dt )SAR-KLCB( )dradnatsKLCB(emityaledtuptuoSAR 81s n ht )SAR-KLCB( )dradnatsKLCB(emitdlohtuptuoSAR 0s n t PR emitdloh)"H"(hgihSAR )1etoN(s n dt )SAC-KLCB( )dradnatsKLCB(emityaledtuptuoSAC 81s n ht )SAC-KLCB( )dradnatsKLCB(emitdlohtuptuoSAC 0s n dt )WD-KLCB( )dradnatsKLCB(emityaledtuptuoWD 81s n ht )WD-KLCB( )dradnatsKLCB(emitdlohtuptuoWD 3-s n ust )SAC-BD( tuptuoBDretfaemitputestuptuoSAC )1etoN(s n ht BD-KLCB( )dradnatsKLCB(emitdlohtuptuolangisBD 7-s n ust )SAR-SAC( )hserfer(tuptuoSARerofebemitputestuptuoSAC )1etoN(s n :SETON .ycneuqerfKLCBehtotgnidroccasnoisserpxegniwollofehtmorfdeniatboebnaceulavA.1 tsu(CAS – RAS) = f(BCLK ) X 2 – 13 [ns] th(RAS – RAD) = f(BCLK) X 2 10 9 – 13 [ns] tRP = f(BCLK) X 2

10 X 39

– 20 [ns] tsu(DB – CAS) = f(BCLK) 10 9 – 20 [ns] See Figure 5.1

08fo4002,10.nuJ02.1.veR page 71 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) Figure 5.10 VCC =3.3V Timing Diagram (1) BCLK ALE -2ns.min RD 18ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) tsu(DB-BCLK) td(BCLK-RD) 30ns.min(1) CSi td(BCLK-CS) 18ns.max(1) ADi th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) 0ns.min tac2(AD-DB)(2) WR,WRL, WRH 18ns.max 0ns.min BCLK CSi td(BCLK-CS) 18ns.max ADi td(BCLK-AD) 18ns.max td(BCLK-ALE) 0ns.min 0ns.min tcyc BHE td(DB-WR) (1) DBi td(BCLK-WR) ALE -2ns.min th(WR-DB) (1) td(DB-WR) =(tcyc-20)ns.min th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2-15)ns.min Vcc=3.3V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (1) th(WR-AD) (1) tac2(RD-DB)(2) 18ns.max(1) Read timing Write timing NOTES: 1. It varies with the operation frequency. Measurement conditions

• VCC =3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V Memory expansion mode and microprocessor mode (with no wait state) NOTES: 1. A value is guarantee with no external factor. Maximum 35ns is garanteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac2(RD-DB)=(tcyc/2-35)ns.max tac2(AD-DB)=(tcyc-35)ns.max 18ns.max tw(WR) (1) 18ns.max

08fo4002,10.nuJ02.1.veR page 72 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) BCLK ALE 18ns.max -2ns.min RD 18ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 30ns.min(1) tac2(RD-DB)(2) CSi td(BCLK-CS) 18ns.max(1) ADi 18ns.max(1) th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)(2) WR,WRL, WRH 18ns.max 0ns.min BCLK CSi 18ns.max ADi 18ns.max 0ns.min 0ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min Vcc=3.3V th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (1) td(DB-WR) (1) th(WR-DB) (1) th(WR-AD) (1) td(DB-WR) =(tcyc x n-20)ns.min (n=1 when 1 wait, n=2 with 2 wait states and n=3 with 3 wait states) t h(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states NOTES: 1. It varies with the operation frequency. Measurement conditions

• VCC =3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V NOTES: 1. A value is guarantee with no external factor. Maximum 35ns is garanteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) th(BCLK-ALE) Read timing Write timing Memory expansion mode and microprocessor mode (with a wait state) tw(WR) (1) Figure 5.11 VCC =3.3V Timing Diagram (2)

08fo4002,10.nuJ02.1.veR page 73 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) BCLK CSi 18ns.max ADi 18ns.max RD 18ns.max -3ns.min th(BCLK-AD) 0ns.min 0ns.min BHE ADi /DBi 0ns.min 18ns.max 0ns.min BCLK CSi 18ns.max ADi 18ns.max 0ns.min 0ns.mintcyc BHE ADi /DBi Data output WR,WRL, WRH Address AddressData input 30ns.min td(BCLK-RD) th(WR-CS) (1) Address td(AD-ALE)(1) Address tsu(DB-BCLK) tac3(RD-DB)(1) tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 18ns.max ALE -2ns.min td(BCLK-ALE) th(ALE-AD)(1) Vcc=3.3V td(BCLK-CS) td(AD-ALE)(1) th(ALE-AD)(1) th(BCLK-RD) th(RD-AD)(1) th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)(1) td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) () td(DB-WR) (1) th(WR-DB) (1) th(BCLK-ALE) th(BCLK-ALE) tcyc NOTES: 1. It varies with the operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (m=3 with 2 wait states and m=5 with 3 wait states) Measurement conditions

• VCC =3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V NOTES: 1. It varies with the operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states) Read timing Write Timing Memory expansion mode and microprocessor mode (with a wait state, when accessing an external memory and using the multiplexed bus) 18ns.max tac3(AD-DB)(1) Figure 5.12 VCC =3.3V Timing Diagram (3)

08fo4002,10.nuJ02.1.veR page 74 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) BCLK DW DB MAi Vcc=3.3V RAS CASL CASH Hi-Z tac4(CAS-DB)(2) 18ns.max(1) th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) tac4(RAS-DB)(2) Row address Column address th(BCLK-RAD) 0ns.min 18ns.max(1) td(BCLK-CAD) 18ns.max(1) td(BCLK-RAS) 18ns.max(1) td(BCLK-CAS) th(RAS-RAD) (1) tRP (2) tac4(CAD-DB)(2) th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min 0ns.min tsu(DB-BCLK) 30ns.min(1) th(CAS-DB) Measurement conditions

• VCC =3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V Read timing Memory expansion mode and microprocessor mode (With 2 wait states, when accessing the DRAM area) NOTES: 1. A value is guaranteed with no external factor. Maximum 35ns is garanteed for the followings: td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) 2. It varies with the operation frequency. tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states) th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min Figure 5.13 VCC =3.3V Timing Diagram (4)

08fo4002,10.nuJ02.1.veR page 75 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) BCLK DW DB MAi Vcc=3.3V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 18ns.max th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) 0ns.min 18ns.max td(BCLK-CAD) 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) tRP (1) 18ns.max td(BCLK-DW) tsu(DB-CAS)(1) th(BCLK-RAS) 0ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) 0ns.min Row address Column address NOTES: 1. It varies with the operation frequency. th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Measurement conditions

• VCC =3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V Write timing Memory expansion mode and microprocessor mode (With 2 wait states, when accessing the DRAM area) th(RAS-RAD) (1) Figure 5.14 VCC =3.3V Timing Diagram (5)

08fo4002,10.nuJ02.1.veR page 76 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) tcyc 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min tsu(CAS-RAS)(1) 18ns.max tcyc td(BCLK-CAS) tsu(CAS-RAS)(1) th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min 18ns.max td(BCLK-RAS) BCLK DW Vcc=3.3V RAS CASL CASH BCLK DW RAS CASL CASH NOTES: 1. It varies with the operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Measurement conditions

• VCC =3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V Refresh timing (CAS-before-RAS refresh) Memory expansion mode and microprocessor mode NOTES: 1. It varies with the operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Refresh timing (Self-refresh) Figure 5.15 VCC =3.3V Timing Diagram (6)

08fo4002,10.nuJ02.1.veR page 77 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) tsu(D–C) TAiIN input TAiOUT input In event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When counting on falling edge is selected) TAiIN input (When counting on rising edge is selected) TAiOUT input (Counter increment/ decrement input) INTi input AD TRG input Vcc=3.3V Figure 5.16 VCC =3.3V Timing Diagram (7)

08fo4002,10.nuJ02.1.veR page 78 puorG28/C23M 5. Electrical Characteristics (VCC = 3.3V) Measurement conditions

• VCC=3.0 to 3.6V
• Input high or low voltage: VIH=2.4V, VIL=0.6V
• Output high or low voltage: VOH=1.5V, VOL=1.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 (Valid with a wait state and no wait state) (Valid only with a wait state) RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Hi–Z th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Vcc=3.3V Figure 5.17 VCC =3.3V Timing Diagram (8)

08fo4002,10.nuJ02.1.veR page 79 puorG28/C23M Package Dimensions LQFP144-P-2020-0.50 Weight(g) – 1.23 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 144P6Q-A Plastic 144pin 20✕ 20mm body LQFP 0.125 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 0.95 ––M D 20.4 ––M E 20.4 8°0° 0.1 1.0 0.650.50.35 22.222.021.8 22.222.021.8 0.5 20.120.019.9 20.120.019.9 0.1750.1250.105 0.270.220.17 1.4 0.05 1.7 e A H D D H E E 37 72 108 109144 F e Lp 0.45 0.6 0.25 0.75 0.08 x M D l2 b2 M E e Recommended Mount Pad y b x M A1 A2 L Detail F Lp c Recommended QFP100-P-1420-0.65 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 ––I2 1.3 ––M D 14.6 ––M E 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c H E H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F 100 x –– 0.13 b x M Recommended Package Dimensions

08fo4002,10.nuJ02.1.veR page 80 puorG28/C23M Package Dimensions LQFP100-P-1414-0.50 Weight(g) – 0.63 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100P6Q-A Plastic 100pin 14✕ 14mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 0.9 ––M D 14.4 ––M E 14.4 10°0° 0.1 1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e E H E 5026 H D D A F y 100 Lp 0.45 0.6 0.25 0.75 0.08 x b x M A1 A2 L Detail F Lp c M D l2 b2 M E e Recommended Mount Pad Recommended

REVISION HISTORY

Rev. Date Description Page Summary A-1 M32C/82 Group Short Sheet/Data Sheet 1.00 15/07/2003 1.10 30/09/2003 New Document Overview - “1.2 Difference between the M32C/82 Group and the M32C/83 Group” has been added. “DRAMC” and “Oscillator stop detect function” have been added to Tables 1.1 and 1.2 - VREF pin has been changed from analog input pin to control pin. - SDA0 to SDA4 pins have been changed from output pins to I/O pins. - Description of intelligent I/O has been modified. - BE IN and BEOUT pins have been modified to IEIN and IEOUT pins in port P13. SFR - Value after RLVL register reset has been modified.

Electrical Characteristics

• Maximum value of sub clock oscillation frequency has been added in Table 5.2. Words standardized: On-chip oscillator, A/D converter and D/A converter 3 to 4 11,15 17,18 All pages 1.20 Jun. 01, 2004

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